From b2f548fe672f24122c7f92027b2c9eeea8a0483a Mon Sep 17 00:00:00 2001 From: Armando Visconti Date: Fri, 16 Aug 2024 17:10:54 +0200 Subject: [PATCH] sensor/stmemsc: Align stmemsc i/f to v2.6 Align stmemsc HAL i/f to v2.6 Signed-off-by: Armando Visconti --- sensor/stmemsc/CMakeLists.txt | 12 +- sensor/stmemsc/README | 156 +- .../_resources/FIFO_Utility_Tool/main.c | 101 - .../_resources/FIFO_Utility_Tool/makefile | 11 - .../_resources/FIFO_Utility_Tool/st_fifo.c | 937 -- .../_resources/FIFO_Utility_Tool/st_fifo.h | 173 - .../a3g4250d_STdC/driver/a3g4250d_reg.c | 128 +- .../a3g4250d_STdC/driver/a3g4250d_reg.h | 136 +- .../stmemsc/ais25ba_STdC/driver/ais25ba_reg.c | 22 +- .../stmemsc/ais25ba_STdC/driver/ais25ba_reg.h | 18 +- .../ais2dw12_STdC/driver/ais2dw12_reg.c | 176 +- .../ais2dw12_STdC/driver/ais2dw12_reg.h | 172 +- .../stmemsc/ais2ih_STdC/driver/ais2ih_reg.c | 222 +- .../stmemsc/ais2ih_STdC/driver/ais2ih_reg.h | 218 +- .../ais328dq_STdC/driver/ais328dq_reg.c | 160 +- .../ais328dq_STdC/driver/ais328dq_reg.h | 154 +- .../ais3624dq_STdC/driver/ais3624dq_reg.c | 162 +- .../ais3624dq_STdC/driver/ais3624dq_reg.h | 156 +- .../asm330lhb_STdC/driver/asm330lhb_reg.c | 958 +- .../asm330lhb_STdC/driver/asm330lhb_reg.h | 625 +- .../asm330lhbg1_STdC/driver/asm330lhbg1_reg.c | 6619 ++++++++++ .../asm330lhbg1_STdC/driver/asm330lhbg1_reg.h | 2699 ++++ .../asm330lhh_STdC/driver/asm330lhh_reg.c | 312 +- .../asm330lhh_STdC/driver/asm330lhh_reg.h | 308 +- .../asm330lhhx_STdC/driver/asm330lhhx_reg.c | 490 +- .../asm330lhhx_STdC/driver/asm330lhhx_reg.h | 485 +- .../driver/asm330lhhxg1_reg.c | 8371 +++++++++++++ .../driver/asm330lhhxg1_reg.h | 3555 ++++++ .../h3lis100dl_STdC/driver/h3lis100dl_reg.c | 122 +- .../h3lis100dl_STdC/driver/h3lis100dl_reg.h | 118 +- .../h3lis331dl_STdC/driver/h3lis331dl_reg.c | 134 +- .../h3lis331dl_STdC/driver/h3lis331dl_reg.h | 130 +- .../stmemsc/hts221_STdC/driver/hts221_reg.c | 80 +- .../stmemsc/hts221_STdC/driver/hts221_reg.h | 76 +- .../i3g4250d_STdC/driver/i3g4250d_reg.c | 132 +- .../i3g4250d_STdC/driver/i3g4250d_reg.h | 140 +- .../stmemsc/iis2dh_STdC/driver/iis2dh_reg.c | 192 +- .../stmemsc/iis2dh_STdC/driver/iis2dh_reg.h | 202 +- .../iis2dlpc_STdC/driver/iis2dlpc_reg.c | 222 +- .../iis2dlpc_STdC/driver/iis2dlpc_reg.h | 218 +- .../iis2iclx_STdC/driver/iis2iclx_reg.c | 412 +- .../iis2iclx_STdC/driver/iis2iclx_reg.h | 402 +- .../stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.c | 98 +- .../stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.h | 94 +- .../iis328dq_STdC/driver/iis328dq_reg.c | 162 +- .../iis328dq_STdC/driver/iis328dq_reg.h | 156 +- .../iis3dhhc_STdC/driver/iis3dhhc_reg.c | 128 +- .../iis3dhhc_STdC/driver/iis3dhhc_reg.h | 124 +- .../stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.c | 258 +- .../stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.h | 208 +- .../ilps22qs_STdC/driver/ilps22qs_reg.c | 201 +- .../ilps22qs_STdC/driver/ilps22qs_reg.h | 199 +- .../ilps28qsw_STdC/driver/ilps28qsw_reg.c | 116 +- .../ilps28qsw_STdC/driver/ilps28qsw_reg.h | 186 +- .../ism303dac_STdC/driver/ism303dac_reg.c | 286 +- .../ism303dac_STdC/driver/ism303dac_reg.h | 276 +- .../ism330bx_STdC/driver/ism330bx_reg.c | 8439 +++++++++++++ .../ism330bx_STdC/driver/ism330bx_reg.h | 3738 ++++++ .../ism330dhcx_STdC/driver/ism330dhcx_reg.c | 638 +- .../ism330dhcx_STdC/driver/ism330dhcx_reg.h | 646 +- .../ism330dlc_STdC/driver/ism330dlc_reg.c | 488 +- .../ism330dlc_STdC/driver/ism330dlc_reg.h | 497 +- .../ism330is_STdC/driver/ism330is_reg.c | 444 +- .../ism330is_STdC/driver/ism330is_reg.h | 222 +- .../l20g20is_STdC/driver/l20g20is_reg.c | 1343 -- .../l20g20is_STdC/driver/l20g20is_reg.h | 572 - .../stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.c | 160 +- .../stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.h | 148 +- .../stmemsc/lis25ba_STdC/driver/lis25ba_reg.c | 28 +- .../stmemsc/lis25ba_STdC/driver/lis25ba_reg.h | 18 +- .../lis2de12_STdC/driver/lis2de12_reg.c | 196 +- .../lis2de12_STdC/driver/lis2de12_reg.h | 186 +- .../lis2dh12_STdC/driver/lis2dh12_reg.c | 204 +- .../lis2dh12_STdC/driver/lis2dh12_reg.h | 198 +- .../stmemsc/lis2dh_STdC/driver/lis2dh_reg.c | 2668 ---- .../stmemsc/lis2dh_STdC/driver/lis2dh_reg.h | 1042 -- .../lis2ds12_STdC/driver/lis2ds12_reg.c | 260 +- .../lis2ds12_STdC/driver/lis2ds12_reg.h | 254 +- .../lis2dtw12_STdC/driver/lis2dtw12_reg.c | 228 +- .../lis2dtw12_STdC/driver/lis2dtw12_reg.h | 224 +- .../lis2du12_STdC/driver/lis2du12_reg.c | 528 +- .../lis2du12_STdC/driver/lis2du12_reg.h | 450 +- .../lis2dux12_STdC/driver/lis2dux12_reg.c | 980 +- .../lis2dux12_STdC/driver/lis2dux12_reg.h | 402 +- .../lis2duxs12_STdC/driver/lis2duxs12_reg.c | 990 +- .../lis2duxs12_STdC/driver/lis2duxs12_reg.h | 390 +- .../lis2dw12_STdC/driver/lis2dw12_reg.c | 228 +- .../lis2dw12_STdC/driver/lis2dw12_reg.h | 224 +- .../lis2hh12_STdC/driver/lis2hh12_reg.c | 159 +- .../lis2hh12_STdC/driver/lis2hh12_reg.h | 146 +- .../stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.c | 108 +- .../stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.h | 100 +- .../lis331dlh_STdC/driver/lis331dlh_reg.c | 168 +- .../lis331dlh_STdC/driver/lis331dlh_reg.h | 162 +- .../stmemsc/lis3de_STdC/driver/lis3de_reg.c | 198 +- .../stmemsc/lis3de_STdC/driver/lis3de_reg.h | 188 +- .../stmemsc/lis3dh_STdC/driver/lis3dh_reg.c | 206 +- .../stmemsc/lis3dh_STdC/driver/lis3dh_reg.h | 204 +- .../stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.c | 130 +- .../stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.h | 120 +- .../stmemsc/lis3dsh_STdC/driver/lis3dsh_reg.c | 881 -- .../stmemsc/lis3dsh_STdC/driver/lis3dsh_reg.h | 908 -- .../stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.c | 124 +- .../stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.h | 114 +- .../stmemsc/lps22ch_STdC/driver/lps22ch_reg.c | 158 +- .../stmemsc/lps22ch_STdC/driver/lps22ch_reg.h | 154 +- .../stmemsc/lps22df_STdC/driver/lps22df_reg.c | 186 +- .../stmemsc/lps22df_STdC/driver/lps22df_reg.h | 203 +- .../stmemsc/lps22hb_STdC/driver/lps22hb_reg.c | 260 +- .../stmemsc/lps22hb_STdC/driver/lps22hb_reg.h | 184 +- .../stmemsc/lps22hh_STdC/driver/lps22hh_reg.c | 146 +- .../stmemsc/lps22hh_STdC/driver/lps22hh_reg.h | 150 +- .../stmemsc/lps25hb_STdC/driver/lps25hb_reg.c | 164 +- .../stmemsc/lps25hb_STdC/driver/lps25hb_reg.h | 154 +- .../lps27hhtw_STdC/driver/lps27hhtw_reg.c | 158 +- .../lps27hhtw_STdC/driver/lps27hhtw_reg.h | 154 +- .../lps27hhw_STdC/driver/lps27hhw_reg.c | 158 +- .../lps27hhw_STdC/driver/lps27hhw_reg.h | 154 +- .../lps28dfw_STdC/driver/lps28dfw_reg.c | 116 +- .../lps28dfw_STdC/driver/lps28dfw_reg.h | 211 +- .../stmemsc/lps33hw_STdC/driver/lps33hw_reg.c | 2079 --- .../stmemsc/lps33hw_STdC/driver/lps33hw_reg.h | 651 - .../stmemsc/lps33k_STdC/driver/lps33k_reg.c | 66 +- .../stmemsc/lps33k_STdC/driver/lps33k_reg.h | 56 +- .../stmemsc/lps33w_STdC/driver/lps33w_reg.c | 2071 --- .../stmemsc/lps33w_STdC/driver/lps33w_reg.h | 644 - .../lsm303agr_STdC/driver/lsm303agr_reg.c | 288 +- .../lsm303agr_STdC/driver/lsm303agr_reg.h | 284 +- .../lsm303ah_STdC/driver/lsm303ah_reg.c | 336 +- .../lsm303ah_STdC/driver/lsm303ah_reg.h | 326 +- .../stmemsc/lsm6ds3_STdC/driver/lsm6ds3_reg.c | 6873 ---------- .../stmemsc/lsm6ds3_STdC/driver/lsm6ds3_reg.h | 2474 ---- .../lsm6ds3tr-c_STdC/driver/lsm6ds3tr-c_reg.c | 478 +- .../lsm6ds3tr-c_STdC/driver/lsm6ds3tr-c_reg.h | 489 +- .../stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.c | 482 +- .../stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.h | 493 +- .../stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.c | 556 +- .../stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.h | 567 +- .../lsm6dso16is_STdC/driver/lsm6dso16is_reg.c | 442 +- .../lsm6dso16is_STdC/driver/lsm6dso16is_reg.h | 222 +- .../lsm6dso32_STdC/driver/lsm6dso32_reg.c | 832 +- .../lsm6dso32_STdC/driver/lsm6dso32_reg.h | 549 +- .../lsm6dso32x_STdC/driver/lsm6dso32x_reg.c | 638 +- .../lsm6dso32x_STdC/driver/lsm6dso32x_reg.h | 912 +- .../stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.c | 630 +- .../stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.h | 626 +- .../lsm6dsox_STdC/driver/lsm6dsox_reg.c | 781 +- .../lsm6dsox_STdC/driver/lsm6dsox_reg.h | 1089 +- .../stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.c | 660 +- .../stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.h | 670 +- .../lsm6dsrx_STdC/driver/lsm6dsrx_reg.c | 664 +- .../lsm6dsrx_STdC/driver/lsm6dsrx_reg.h | 674 +- .../lsm6dsv16b_STdC/driver/lsm6dsv16b_reg.c | 7664 +++++++++++ .../lsm6dsv16b_STdC/driver/lsm6dsv16b_reg.h | 3408 +++++ .../lsm6dsv16bx_STdC/driver/lsm6dsv16bx_reg.c | 673 +- .../lsm6dsv16bx_STdC/driver/lsm6dsv16bx_reg.h | 618 +- .../lsm6dsv16x_STdC/driver/lsm6dsv16x_reg.c | 2189 ++-- .../lsm6dsv16x_STdC/driver/lsm6dsv16x_reg.h | 590 +- .../lsm6dsv32x_STdC/driver/lsm6dsv32x_reg.c | 10459 ++++++++++++++++ .../lsm6dsv32x_STdC/driver/lsm6dsv32x_reg.h | 5273 ++++++++ .../stmemsc/lsm6dsv_STdC/driver/lsm6dsv_reg.c | 2126 ++-- .../stmemsc/lsm6dsv_STdC/driver/lsm6dsv_reg.h | 567 +- .../stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.c | 284 +- .../stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.h | 276 +- .../st1vafe6ax_STdC/driver/st1vafe6ax_reg.c | 7948 ++++++++++++ .../st1vafe6ax_STdC/driver/st1vafe6ax_reg.h | 3609 ++++++ .../sths34pf80_STdC/driver/sths34pf80_reg.c | 531 +- .../sths34pf80_STdC/driver/sths34pf80_reg.h | 205 +- .../stmemsc/stts22h_STdC/driver/stts22h_reg.c | 95 +- .../stmemsc/stts22h_STdC/driver/stts22h_reg.h | 57 +- .../stmemsc/stts751_STdC/driver/stts751_reg.c | 54 +- .../stmemsc/stts751_STdC/driver/stts751_reg.h | 44 +- 172 files changed, 96450 insertions(+), 45089 deletions(-) delete mode 100644 sensor/stmemsc/_resources/FIFO_Utility_Tool/main.c delete mode 100644 sensor/stmemsc/_resources/FIFO_Utility_Tool/makefile delete mode 100644 sensor/stmemsc/_resources/FIFO_Utility_Tool/st_fifo.c delete mode 100644 sensor/stmemsc/_resources/FIFO_Utility_Tool/st_fifo.h create mode 100644 sensor/stmemsc/asm330lhbg1_STdC/driver/asm330lhbg1_reg.c create mode 100644 sensor/stmemsc/asm330lhbg1_STdC/driver/asm330lhbg1_reg.h create mode 100644 sensor/stmemsc/asm330lhhxg1_STdC/driver/asm330lhhxg1_reg.c create mode 100644 sensor/stmemsc/asm330lhhxg1_STdC/driver/asm330lhhxg1_reg.h create mode 100644 sensor/stmemsc/ism330bx_STdC/driver/ism330bx_reg.c create mode 100644 sensor/stmemsc/ism330bx_STdC/driver/ism330bx_reg.h delete mode 100644 sensor/stmemsc/l20g20is_STdC/driver/l20g20is_reg.c delete mode 100644 sensor/stmemsc/l20g20is_STdC/driver/l20g20is_reg.h delete mode 100644 sensor/stmemsc/lis2dh_STdC/driver/lis2dh_reg.c delete mode 100644 sensor/stmemsc/lis2dh_STdC/driver/lis2dh_reg.h delete mode 100644 sensor/stmemsc/lis3dsh_STdC/driver/lis3dsh_reg.c delete mode 100644 sensor/stmemsc/lis3dsh_STdC/driver/lis3dsh_reg.h delete mode 100644 sensor/stmemsc/lps33hw_STdC/driver/lps33hw_reg.c delete mode 100644 sensor/stmemsc/lps33hw_STdC/driver/lps33hw_reg.h delete mode 100644 sensor/stmemsc/lps33w_STdC/driver/lps33w_reg.c delete mode 100644 sensor/stmemsc/lps33w_STdC/driver/lps33w_reg.h delete mode 100644 sensor/stmemsc/lsm6ds3_STdC/driver/lsm6ds3_reg.c delete mode 100644 sensor/stmemsc/lsm6ds3_STdC/driver/lsm6ds3_reg.h create mode 100644 sensor/stmemsc/lsm6dsv16b_STdC/driver/lsm6dsv16b_reg.c create mode 100644 sensor/stmemsc/lsm6dsv16b_STdC/driver/lsm6dsv16b_reg.h create mode 100644 sensor/stmemsc/lsm6dsv32x_STdC/driver/lsm6dsv32x_reg.c create mode 100644 sensor/stmemsc/lsm6dsv32x_STdC/driver/lsm6dsv32x_reg.h create mode 100644 sensor/stmemsc/st1vafe6ax_STdC/driver/st1vafe6ax_reg.c create mode 100644 sensor/stmemsc/st1vafe6ax_STdC/driver/st1vafe6ax_reg.h diff --git a/sensor/stmemsc/CMakeLists.txt b/sensor/stmemsc/CMakeLists.txt index 6949a8f1..355a2418 100644 --- a/sensor/stmemsc/CMakeLists.txt +++ b/sensor/stmemsc/CMakeLists.txt @@ -12,8 +12,10 @@ set(stmems_pids ais328dq ais3624dq asm330lhb + asm330lhbg1 asm330lhh asm330lhhx + asm330lhhxg1 h3lis100dl h3lis331dl hts221 @@ -28,14 +30,13 @@ set(stmems_pids ilps22qs ilps28qsw ism303dac + ism330bx ism330dhcx ism330dlc ism330is - l20g20is l3gd20h lis25ba lis2de12 - lis2dh lis2dh12 lis2ds12 lis2dtw12 @@ -49,7 +50,6 @@ set(stmems_pids lis3de lis3dh lis3dhh - lis3dsh lis3mdl lps22ch lps22df @@ -59,12 +59,9 @@ set(stmems_pids lps27hhtw lps27hhw lps28dfw - lps33hw lps33k - lps33w lsm303agr lsm303ah - lsm6ds3 lsm6ds3tr-c lsm6dsl lsm6dsm @@ -75,10 +72,13 @@ set(stmems_pids lsm6dsox lsm6dsr lsm6dsrx + lsm6dsv16b lsm6dsv16bx lsm6dsv16x + lsm6dsv32x lsm6dsv lsm9ds1 + st1vafe6ax sths34pf80 stts22h stts751 diff --git a/sensor/stmemsc/README b/sensor/stmemsc/README index cd27cfcf..9f76ce97 100644 --- a/sensor/stmemsc/README +++ b/sensor/stmemsc/README @@ -6,7 +6,7 @@ Origin: https://www.st.com/en/embedded-software/c-driver-mems.html Status: - version v2.3 + version v2.6 Purpose: ST Microelectronics standard C platform-independent drivers for MEMS @@ -49,83 +49,83 @@ Description: Driver versions in this package: - - a3g4250d_STdC v1.1.0 - - ais25ba_STdC v1.1.0 - - ais2dw12_STdC v1.1.0 - - ais2ih_STdC v1.1.0 - - ais328dq_STdC v1.1.0 - - ais3624dq_STdC v1.1.0 - - asm330lhb_STdC v1.0.0 - - asm330lhh_STdC v2.1.0 - - asm330lhhx_STdC v1.1.1 - - h3lis100dl_STdC v1.1.0 - - h3lis331dl_STdC v1.1.0 - - hts221_STdC v1.1.0 - - i3g4250d_STdC v1.1.0 - - iis2dh_STdC v1.1.0 - - iis2dlpc_STdC v1.1.0 - - iis2iclx_STdC v1.1.0 - - iis2mdc_STdC v1.1.0 - - iis328dq_STdC v1.1.0 - - iis3dhhc_STdC v1.1.0 - - iis3dwb_STdC v1.1.1 - - ilps22qs_STdC v2.1.1 - - ilps28qsw_STdC v1.0.1 - - ism303dac_STdC v1.1.0 - - ism330dhcx_STdC v1.1.0 - - ism330dlc_STdC v1.1.0 - - ism330is_STdC v2.1.0 - - l20g20is_STdC v1.1.0 - - l3gd20h_STdC v1.1.0 - - lis25ba_STdC v1.1.0 - - lis2de12_STdC v1.1.0 - - lis2dh12_STdC v1.1.0 - - lis2dh_STdC v1.1.0 - - lis2ds12_STdC v1.1.0 - - lis2dtw12_STdC v1.1.0 - - lis2du12_STdC v1.1.3 - - lis2dux12_STdC v1.1.4 - - lis2duxs12_STdC v1.1.5 - - lis2dw12_STdC v1.1.0 - - lis2hh12_STdC v1.1.0 - - lis2mdl_STdC v1.1.0 - - lis331dlh_STdC v1.1.0 - - lis3de_STdC v1.1.0 - - lis3dh_STdC v1.1.0 - - lis3dhh_STdC v1.1.0 - - lis3dsh_STdC v1.1.0 - - lis3mdl_STdC v1.1.0 - - lps22ch_STdC v1.1.0 - - lps22df_STdC v1.1.0 - - lps22hb_STdC v1.1.0 - - lps22hh_STdC v1.1.0 - - lps25hb_STdC v1.1.0 - - lps27hhtw_STdC v1.1.0 - - lps27hhw_STdC v1.1.0 - - lps28dfw_STdC v1.1.0 - - lps33hw_STdC v1.1.0 - - lps33k_STdC v1.1.0 - - lps33w_STdC v1.1.0 - - lsm303agr_STdC v1.1.0 - - lsm303ah_STdC v1.1.0 - - lsm6ds3_STdC v1.1.1 - - lsm6ds3tr-c_STdC v1.1.0 - - lsm6dsl_STdC v1.1.0 - - lsm6dsm_STdC v1.1.0 - - lsm6dso16is_STdC v2.1.1 - - lsm6dso32_STdC v1.1.0 - - lsm6dso32x_STdC v1.1.0 - - lsm6dso_STdC v2.1.0 - - lsm6dsox_STdC v2.0.1 - - lsm6dsr_STdC v1.1.0 - - lsm6dsrx_STdC v1.1.0 - - lsm6dsv16bx_STdC v2.1.2 - - lsm6dsv16x_STdC v2.2.1 - - lsm6dsv_STdC v1.2.1 - - lsm9ds1_STdC v1.1.0 - - sths34pf80_STdC v1.0.0 - - stts22h_STdC v1.1.0 - - stts751_STdC v1.1.0 + - a3g4250d_STdC v2.0.1 + - ais25ba_STdC v2.0.1 + - ais2dw12_STdC v2.0.1 + - ais2ih_STdC v2.0.1 + - ais328dq_STdC v2.0.1 + - ais3624dq_STdC v2.0.1 + - asm330lhb_STdC v2.0.1 + - asm330lhbg1_STdC v1.0.0 + - asm330lhh_STdC v3.1.0 + - asm330lhhx_STdC v2.0.0 + - asm330lhhxg1_STdC v2.0.1 + - h3lis100dl_STdC v2.0.1 + - h3lis331dl_STdC v2.0.1 + - hts221_STdC v2.0.1 + - i3g4250d_STdC v2.0.1 + - iis2dh_STdC v2.0.1 + - iis2dlpc_STdC v2.0.1 + - iis2iclx_STdC v2.0.1 + - iis2mdc_STdC v2.0.2 + - iis328dq_STdC v2.0.1 + - iis3dhhc_STdC v2.0.1 + - iis3dwb_STdC v2.0.1 + - ilps22qs_STdC v3.1.0 + - ilps28qsw_STdC v2.1.0 + - ism303dac_STdC v2.0.1 + - ism330bx_STdC v3.0.0 + - ism330dhcx_STdC v2.0.2 + - ism330dlc_STdC v2.0.1 + - ism330is_STdC v3.0.1 + - l3gd20h_STdC v2.0.1 + - lis25ba_STdC v2.0.1 + - lis2de12_STdC v2.0.1 + - lis2dh12_STdC v2.0.1 + - lis2ds12_STdC v2.0.1 + - lis2dtw12_STdC v2.0.1 + - lis2du12_STdC v2.0.1 + - lis2dux12_STdC v2.2.0 + - lis2duxs12_STdC v2.2.0 + - lis2dw12_STdC v2.0.1 + - lis2hh12_STdC v2.0.1 + - lis2mdl_STdC v2.0.1 + - lis331dlh_STdC v2.0.1 + - lis3de_STdC v2.0.1 + - lis3dh_STdC v2.0.1 + - lis3dhh_STdC v2.0.1 + - lis3mdl_STdC v2.0.1 + - lps22ch_STdC v2.0.1 + - lps22df_STdC v2.1.0 + - lps22hb_STdC v2.0.1 + - lps22hh_STdC v3.0.1 + - lps25hb_STdC v2.0.1 + - lps27hhtw_STdC v2.0.1 + - lps27hhw_STdC v2.0.1 + - lps28dfw_STdC v2.1.0 + - lps33k_STdC v2.0.1 + - lsm303agr_STdC v2.0.1 + - lsm303ah_STdC v2.0.1 + - lsm6ds3tr-c_STdC v2.0.1 + - lsm6dsl_STdC v2.0.1 + - lsm6dsm_STdC v2.0.1 + - lsm6dso16is_STdC v3.0.1 + - lsm6dso32_STdC v2.0.1 + - lsm6dso32x_STdC v2.0.1 + - lsm6dso_STdC v3.0.2 + - lsm6dsox_STdC v3.0.1 + - lsm6dsr_STdC v2.0.1 + - lsm6dsrx_STdC v2.0.1 + - lsm6dsv16b_STdC v3.0.0 + - lsm6dsv16bx_STdC v5.0.0 + - lsm6dsv16x_STdC v4.0.0 + - lsm6dsv32x_STdC v2.0.0 + - lsm6dsv_STdC v3.0.0 + - lsm9ds1_STdC v2.0.1 + - st1vafe6ax_STdC v2.0.0 + - sths34pf80_STdC v3.0.1 + - stts22h_STdC v2.1.0 + - stts751_STdC v2.0.1 Dependencies: None. diff --git a/sensor/stmemsc/_resources/FIFO_Utility_Tool/main.c b/sensor/stmemsc/_resources/FIFO_Utility_Tool/main.c deleted file mode 100644 index 3f7dc37d..00000000 --- a/sensor/stmemsc/_resources/FIFO_Utility_Tool/main.c +++ /dev/null @@ -1,101 +0,0 @@ -#include -#include -#include - -#include "st_fifo.h" - -uint16_t out_slot_size; - -int main(int argc, char *argv[]) -{ - if (argc != 3) { - printf("Error: please specify input and output as commandline args\n"); - return -1; - } - - FILE *fp; - char *line = NULL; - fp = fopen(argv[1], "r"); - - size_t len = 0; - ssize_t read; - - FILE *out_file; - out_file = fopen(argv[2], "w"); - - int lines = 0; - size_t pos = ftell(fp); - while(!feof(fp)) { - char ch = fgetc(fp); - if(ch == '\n') { - lines++; - } - } - fseek(fp, pos, SEEK_SET); - - printf("File length: %d\n", lines); - - st_fifo_conf conf; - conf.device = ST_FIFO_LSM6DSV16X; - conf.bdr_xl = 0; - conf.bdr_gy = 0; - conf.bdr_vsens = 0; - - st_fifo_init(&conf); - st_fifo_raw_slot *raw_slot; - st_fifo_out_slot *out_slot; - - raw_slot = malloc(lines * sizeof(st_fifo_raw_slot)); - out_slot = malloc(lines * 3 * sizeof(st_fifo_out_slot)); - - int i = 0; - - printf("Running test...\n"); - - while((read = getline(&line, &len, fp)) != -1) { - - int data_in[7]; - - sscanf(line, "%d\t%d\t%d\t%d\t%d\t%d\t%d\r\n", &data_in[0], &data_in[1], &data_in[2], &data_in[3], &data_in[4], &data_in[5], &data_in[6]); - - for (uint8_t j = 0; j < 7; j++) - raw_slot[i].fifo_data_out[j] = data_in[j]; - - i++; - } - - st_fifo_decode(out_slot, raw_slot, &out_slot_size, lines); - st_fifo_sort(out_slot, out_slot_size); - - uint16_t acc_samples = st_fifo_get_sensor_occurrence(out_slot, out_slot_size, ST_FIFO_ACCELEROMETER); - uint16_t gyr_samples = st_fifo_get_sensor_occurrence(out_slot, out_slot_size, ST_FIFO_GYROSCOPE); - - printf("acc samples: %d\n", acc_samples); - printf("gyr samples: %d\n", gyr_samples); - - st_fifo_out_slot *acc_slot = malloc(acc_samples * sizeof(st_fifo_out_slot)); - st_fifo_out_slot *gyr_slot = malloc(gyr_samples * sizeof(st_fifo_out_slot)); - - st_fifo_extract_sensor(acc_slot, out_slot, out_slot_size, ST_FIFO_ACCELEROMETER); - st_fifo_extract_sensor(gyr_slot, out_slot, out_slot_size, ST_FIFO_GYROSCOPE); - - for (int i = 0; i < out_slot_size; i++) { - fprintf(out_file, "%u\t%d\t%d\t%d\t%d\r\n", out_slot[i].timestamp, out_slot[i].sensor_tag, out_slot[i].sensor_data.data[0], out_slot[i].sensor_data.data[1], out_slot[i].sensor_data.data[2]); - } - /* - for (int i = 0; i < acc_samples; i++) { - printf("ACC SLOT:\t%lld\t%d\t%d\t%d\t%d\r\n", acc_slot[i].timestamp, acc_slot[i].sensor_tag, acc_slot[i].data[0], acc_slot[i].data[1], acc_slot[i].data[2]); - } - - for (int i = 0; i < gyr_samples; i++) { - printf("GYR SLOT:\t%lld\t%d\t%d\t%d\t%d\r\n", gyr_slot[i].timestamp, gyr_slot[i].sensor_tag, gyr_slot[i].data[0], gyr_slot[i].data[1], gyr_slot[i].data[2]); - } - */ - - printf("Test finished: see %s file\n", argv[2]); - - fclose(fp); - fclose(out_file); - - return 0; -} diff --git a/sensor/stmemsc/_resources/FIFO_Utility_Tool/makefile b/sensor/stmemsc/_resources/FIFO_Utility_Tool/makefile deleted file mode 100644 index 52e82424..00000000 --- a/sensor/stmemsc/_resources/FIFO_Utility_Tool/makefile +++ /dev/null @@ -1,11 +0,0 @@ -CC = gcc -SRC = main.c st_fifo.c - -CFLAGS = -Wall -Wextra -Werror -std=gnu99 - -default: - $(CC) $(CFLAGS) $(SRC) -o st_fifo.run - -clean: - rm -fr *.o - rm -fr st_fifo.run diff --git a/sensor/stmemsc/_resources/FIFO_Utility_Tool/st_fifo.c b/sensor/stmemsc/_resources/FIFO_Utility_Tool/st_fifo.c deleted file mode 100644 index 2fb42341..00000000 --- a/sensor/stmemsc/_resources/FIFO_Utility_Tool/st_fifo.c +++ /dev/null @@ -1,937 +0,0 @@ -/* - ****************************************************************************** - * @file fifo_utility.c - * @author Sensor Solutions Software Team - * @brief Utility for managing FIFO data decoding and decompression. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2022 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include -#include -#include -#include "st_fifo.h" - -/** - * @defgroup FIFO utility - * @brief This file provides a set of functions needed to manage FIFO data - * decoding and decompression. - * @{ - * - */ - -/* Private constants --------------------------------------------------------*/ -#define BDR_XL_MASK (0x0Fu) -#define BDR_XL_SHIFT (0x00u) - -#define BDR_GY_MASK (0xF0u) -#define BDR_GY_SHIFT (0x04u) - -#define BDR_VSENS_MASK (0x0Fu) -#define BDR_VSENS_SHIFT (0x00u) - -#define TAG_COUNTER_MASK (0x06u) -#define TAG_SENSOR_MASK (0xF8u) -#define TAG_COUNTER_SHIFT (0x01u) -#define TAG_SENSOR_SHIFT (0x03u) - -#define TAG_EMPTY (0x00u) -#define TAG_GY (0x01u) -#define TAG_XL (0x02u) -#define TAG_TEMP (0x03u) -#define TAG_TS (0x04u) -#define TAG_ODRCHG (0x05u) -#define TAG_XL_UNCOMPRESSED_T_2 (0x06u) -#define TAG_XL_UNCOMPRESSED_T_1 (0x07u) -#define TAG_XL_COMPRESSED_2X (0x08u) -#define TAG_XL_COMPRESSED_3X (0x09u) -#define TAG_GY_UNCOMPRESSED_T_2 (0x0Au) -#define TAG_GY_UNCOMPRESSED_T_1 (0x0Bu) -#define TAG_GY_COMPRESSED_2X (0x0Cu) -#define TAG_GY_COMPRESSED_3X (0x0Du) -#define TAG_EXT_SENS_0 (0x0Eu) -#define TAG_EXT_SENS_1 (0x0Fu) -#define TAG_EXT_SENS_2 (0x10u) -#define TAG_EXT_SENS_3 (0x11u) -#define TAG_STEP_COUNTER (0x12u) -#define TAG_GAME_RV (0x13u) -#define TAG_GEOM_RV (0x14u) -#define TAG_NORM_RV (0x15u) -#define TAG_GYRO_BIAS (0x16u) -#define TAG_GRAVITIY (0x17u) -#define TAG_MAG_CAL (0x18u) -#define TAG_EXT_SENS_NACK (0x19u) -#define TAG_MLC_RESULT (0x1Au) -#define TAG_MLC_FILTER (0x1Bu) -#define TAG_MLC_FEATURE (0x1Cu) -#define TAG_DUALC_XL (0x1Du) -#define TAG_EIS_GY (0x1Eu) - -#define MAX(a, b) ((a) > (b) ? (a) : (b)) -#define MIN(a, b) ((a) < (b) ? (a) : (b)) - -/* Private typedef -----------------------------------------------------------*/ -typedef enum -{ - ST_FIFO_COMPRESSION_NC, - ST_FIFO_COMPRESSION_NC_T_1, - ST_FIFO_COMPRESSION_NC_T_2, - ST_FIFO_COMPRESSION_2X, - ST_FIFO_COMPRESSION_3X -} st_fifo_compression_type; - -/* Private functions ---------------------------------------------------------*/ -/* Functions declare in this section are defined at the end of this file. */ -static uint8_t bdr_get_index(const float *bdr, float n); -static uint8_t has_even_parity(uint8_t x); -static st_fifo_sensor_type get_sensor_type(uint8_t tag); -static st_fifo_compression_type get_compression_type(uint8_t tag); -static uint8_t is_tag_valid(uint8_t tag); -static void get_diff_2x(int16_t diff[6], uint8_t input[6]); -static void get_diff_3x(int16_t diff[9], uint8_t input[6]); - -/* Private variables ---------------------------------------------------------*/ -static const struct -{ - float bdr_acc[16]; - float bdr_gyr[16]; - float bdr_vsens[16]; - uint32_t dtime[16]; - uint8_t tag_valid_limit; -} device[] = -{ - { - .bdr_acc = { 0, 13, 26, 52, 104, 208, 416, 833, 1666, 3333, 6666, 1.625, 0, 0, 0, 0 }, - .bdr_gyr = { 0, 13, 26, 52, 104, 208, 416, 833, 1666, 3333, 6666, 0, 0, 0, 0, 0 }, - .bdr_vsens = { 0, 13, 26, 52, 104, 208, 416, 0, 0, 0, 0, 1.625, 0, 0, 0, 0 }, - .dtime = { 0, 3072, 1536, 768, 384, 192, 96, 48, 24, 12, 6, 24576, 0, 0, 0, 0 }, - .tag_valid_limit = 0x19, - }, - { - .bdr_acc = { 0, 1.875, 7.5, 15, 30, 60, 120, 240, 480, 960, 1920, 3840, 7680, 0, 0, 0 }, - .bdr_gyr = { 0, 1.875, 7.5, 15, 30, 60, 120, 240, 480, 960, 1920, 3840, 7680, 0, 0, 0 }, - .bdr_vsens = { 0, 1.875, 7.5, 15, 30, 60, 120, 240, 480, 960, 0, 0, 0, 0, 0, 0 }, - .dtime = { 0, 24576, 6144, 3072, 1536, 768, 384, 192, 96, 48, 24, 12, 6, 0, 0, 0 }, - .tag_valid_limit = 0x1E, - }, -}; - -static uint8_t fifo_ver; -static uint8_t tag_counter_old; -static uint32_t dtime_xl; -static uint32_t dtime_gy; -static uint32_t dtime_min; -static uint32_t dtime_xl_old; -static uint32_t dtime_gy_old; -static uint32_t timestamp; -static uint32_t last_timestamp_xl; -static uint32_t last_timestamp_gy; -static uint8_t bdr_chg_xl_flag; -static uint8_t bdr_chg_gy_flag; -static int16_t last_data_xl[3]; -static int16_t last_data_gy[3]; - -/** - * @defgroup FIFO public functions - * @brief This section provide a set of APIs for managing FIFO data - * decoding and decompression. - * @{ - * - */ - -/** - * @brief Initialize the FIFO utility library. - * - * @param conf library configuration to set (BDR parameters - * can be set to 0 Hz if ODR_CHG_EN is enabled - * or timestamp sensor is batched in FIFO). - * - * @retval st_fifo_status ST_FIFO_OK / ST_FIFO_ERR - * - */ -st_fifo_status st_fifo_init(st_fifo_conf *conf) -{ - float bdr_xl, bdr_gy, bdr_vsens, bdr_max; - - if (conf->bdr_xl < 0.0f || conf->bdr_gy < 0.0f || conf->bdr_vsens < 0.0f) - { - return ST_FIFO_ERR; - } - - if (conf->device < ST_FIFO_LSM6DSV) - { - fifo_ver = 0; - } - else - { - fifo_ver = 1; - } - - tag_counter_old = 0; - bdr_xl = conf->bdr_xl; - bdr_gy = conf->bdr_gy; - bdr_vsens = conf->bdr_vsens; - bdr_max = MAX(bdr_xl, bdr_gy); - bdr_max = MAX(bdr_max, bdr_vsens); - dtime_min = device[fifo_ver].dtime[bdr_get_index(device[fifo_ver].bdr_acc, bdr_max)]; - dtime_xl = device[fifo_ver].dtime[bdr_get_index(device[fifo_ver].bdr_acc, bdr_xl)]; - dtime_gy = device[fifo_ver].dtime[bdr_get_index(device[fifo_ver].bdr_gyr, bdr_gy)]; - dtime_xl_old = dtime_xl; - dtime_gy_old = dtime_gy; - timestamp = 0; - bdr_chg_xl_flag = 0; - bdr_chg_gy_flag = 0; - last_timestamp_xl = 0; - last_timestamp_gy = 0; - - for (uint8_t i = 0; i < 3u; i++) - { - last_data_xl[i] = 0; - last_data_gy[i] = 0; - } - - return ST_FIFO_OK; -} - -/** - * @brief Decode and decompress a raw FIFO stream. - * - * @param fifo_out_slot decoded output stream.(ptr) - * @param fifo_raw_slot compressed raw input data stream.(ptr) - * @param out_slot_size decoded stream size.(ptr) - * @param stream_size raw input stream size. - * - * @retval st_fifo_status ST_FIFO_OK / ST_FIFO_ERR - * - */ -st_fifo_status st_fifo_decode(st_fifo_out_slot *fifo_out_slot, - st_fifo_raw_slot *fifo_raw_slot, uint16_t *out_slot_size, uint16_t stream_size) -{ - uint16_t j = 0; - - for (uint16_t i = 0; i < stream_size; i++) - { - - uint8_t tag = (fifo_raw_slot[i].fifo_data_out[0] & TAG_SENSOR_MASK) >> TAG_SENSOR_SHIFT; - uint8_t tag_counter = (fifo_raw_slot[i].fifo_data_out[0] & TAG_COUNTER_MASK) >> TAG_COUNTER_SHIFT; - - if (fifo_ver == 0u && has_even_parity(fifo_raw_slot[i].fifo_data_out[0]) == 0u) - { - return ST_FIFO_ERR; - } - - if (is_tag_valid(tag) == 0u) - { - return ST_FIFO_ERR; - } - - if ((tag_counter != (tag_counter_old)) && dtime_min != 0u) - { - - uint8_t diff_tag_counter; - - if (tag_counter < tag_counter_old) - { - diff_tag_counter = tag_counter + 4u - tag_counter_old; - } - else - { - diff_tag_counter = tag_counter - tag_counter_old; - } - - timestamp += dtime_min * diff_tag_counter; - } - - if (tag == TAG_ODRCHG) - { - - uint8_t bdr_acc_cfg = (fifo_raw_slot[i].fifo_data_out[6] & BDR_XL_MASK) >> BDR_XL_SHIFT; - uint8_t bdr_gyr_cfg = (fifo_raw_slot[i].fifo_data_out[6] & BDR_GY_MASK) >> BDR_GY_SHIFT; - uint8_t bdr_vsens_cfg = (fifo_raw_slot[i].fifo_data_out[4] & BDR_VSENS_MASK) >> BDR_VSENS_SHIFT; - - float bdr_xl = device[fifo_ver].bdr_acc[bdr_acc_cfg]; - float bdr_gy = device[fifo_ver].bdr_gyr[bdr_gyr_cfg]; - float bdr_vsens = device[fifo_ver].bdr_vsens[bdr_vsens_cfg]; - float bdr_max = MAX(bdr_xl, bdr_gy); - bdr_max = MAX(bdr_max, bdr_vsens); - - dtime_xl_old = dtime_xl; - dtime_gy_old = dtime_gy; - dtime_min = device[fifo_ver].dtime[bdr_get_index(device[fifo_ver].bdr_acc, bdr_max)]; - dtime_xl = device[fifo_ver].dtime[bdr_get_index(device[fifo_ver].bdr_acc, bdr_xl)]; - dtime_gy = device[fifo_ver].dtime[bdr_get_index(device[fifo_ver].bdr_gyr, bdr_gy)]; - - bdr_chg_xl_flag = 1; - bdr_chg_gy_flag = 1; - - } - else if (tag == TAG_TS) - { - - (void)memcpy(×tamp, &fifo_raw_slot[i].fifo_data_out[1], 4); - - } - else - { - - st_fifo_compression_type compression_type = get_compression_type(tag); - st_fifo_sensor_type sensor_type = get_sensor_type(tag); - - if (compression_type == ST_FIFO_COMPRESSION_NC) - { - - if (tag == TAG_EMPTY) - { - continue; - } - - if (tag == TAG_STEP_COUNTER || tag == TAG_MLC_RESULT) - { - (void)memcpy(&fifo_out_slot[j].timestamp, &fifo_raw_slot[i].fifo_data_out[3], - 4); - } - else - { - fifo_out_slot[j].timestamp = timestamp; - } - - fifo_out_slot[j].sensor_tag = sensor_type; - (void)memcpy(fifo_out_slot[j].sensor_data.raw_data, - &fifo_raw_slot[i].fifo_data_out[1], 6); - - if (sensor_type == ST_FIFO_ACCELEROMETER) - { - (void)memcpy(last_data_xl, fifo_out_slot[j].sensor_data.raw_data, 6); - last_timestamp_xl = timestamp; - bdr_chg_xl_flag = 0; - } - - if (sensor_type == ST_FIFO_GYROSCOPE) - { - (void)memcpy(last_data_gy, fifo_out_slot[j].sensor_data.raw_data, 6); - last_timestamp_gy = timestamp; - bdr_chg_gy_flag = 0; - } - - j++; - - } - else if (compression_type == ST_FIFO_COMPRESSION_NC_T_1) - { - - fifo_out_slot[j].sensor_tag = get_sensor_type(tag); - (void)memcpy(fifo_out_slot[j].sensor_data.raw_data, - &fifo_raw_slot[i].fifo_data_out[1], 6); - - if (sensor_type == ST_FIFO_ACCELEROMETER) - { - uint32_t last_timestamp; - - if (bdr_chg_xl_flag == 1u) - { - last_timestamp = last_timestamp_xl + dtime_xl_old; - } - else - { - last_timestamp = timestamp - dtime_xl; - } - - fifo_out_slot[j].timestamp = last_timestamp; - (void)memcpy(last_data_xl, fifo_out_slot[j].sensor_data.raw_data, 6); - last_timestamp_xl = last_timestamp; - } - - if (sensor_type == ST_FIFO_GYROSCOPE) - { - uint32_t last_timestamp; - - if (bdr_chg_gy_flag == 1u) - { - last_timestamp = last_timestamp_gy + dtime_gy_old; - } - else - { - last_timestamp = timestamp - dtime_gy; - } - - fifo_out_slot[j].timestamp = last_timestamp; - (void)memcpy(last_data_gy, fifo_out_slot[j].sensor_data.raw_data, 6); - last_timestamp_gy = last_timestamp; - } - - j++; - - } - else if (compression_type == ST_FIFO_COMPRESSION_NC_T_2) - { - - fifo_out_slot[j].sensor_tag = get_sensor_type(tag); - (void)memcpy(fifo_out_slot[j].sensor_data.raw_data, - &fifo_raw_slot[i].fifo_data_out[1], 6); - - if (sensor_type == ST_FIFO_ACCELEROMETER) - { - uint32_t last_timestamp; - - if (bdr_chg_xl_flag == 1u) - { - last_timestamp = last_timestamp_xl + dtime_xl_old; - } - else - { - last_timestamp = timestamp - 2u * dtime_xl; - } - - fifo_out_slot[j].timestamp = last_timestamp; - (void)memcpy(last_data_xl, fifo_out_slot[j].sensor_data.raw_data, 6); - last_timestamp_xl = last_timestamp; - } - if (sensor_type == ST_FIFO_GYROSCOPE) - { - uint32_t last_timestamp; - - if (bdr_chg_gy_flag == 1u) - { - last_timestamp = last_timestamp_gy + dtime_gy_old; - } - else - { - last_timestamp = timestamp - 2u * dtime_gy; - } - - fifo_out_slot[j].timestamp = last_timestamp; - (void)memcpy(last_data_gy, fifo_out_slot[j].sensor_data.raw_data, 6); - last_timestamp_gy = last_timestamp; - } - - j++; - - } - else if (compression_type == ST_FIFO_COMPRESSION_2X) - { - - int16_t diff[6]; - get_diff_2x(diff, &fifo_raw_slot[i].fifo_data_out[1]); - - fifo_out_slot[j].sensor_tag = sensor_type; - - if (sensor_type == ST_FIFO_ACCELEROMETER) - { - fifo_out_slot[j].sensor_data.data[0] = last_data_xl[0] + diff[0]; - fifo_out_slot[j].sensor_data.data[1] = last_data_xl[1] + diff[1]; - fifo_out_slot[j].sensor_data.data[2] = last_data_xl[2] + diff[2]; - fifo_out_slot[j].timestamp = timestamp - 2u * dtime_xl; - (void)memcpy(last_data_xl, fifo_out_slot[j].sensor_data.raw_data, 6); - } - - if (sensor_type == ST_FIFO_GYROSCOPE) - { - fifo_out_slot[j].sensor_data.data[0] = last_data_gy[0] + diff[0]; - fifo_out_slot[j].sensor_data.data[1] = last_data_gy[1] + diff[1]; - fifo_out_slot[j].sensor_data.data[2] = last_data_gy[2] + diff[2]; - fifo_out_slot[j].timestamp = timestamp - 2u * dtime_gy; - (void)memcpy(last_data_gy, fifo_out_slot[j].sensor_data.raw_data, 6); - } - - j++; - - fifo_out_slot[j].sensor_tag = sensor_type; - - if (sensor_type == ST_FIFO_ACCELEROMETER) - { - uint32_t last_timestamp = timestamp - dtime_xl; - fifo_out_slot[j].sensor_data.data[0] = last_data_xl[0] + diff[3]; - fifo_out_slot[j].sensor_data.data[1] = last_data_xl[1] + diff[4]; - fifo_out_slot[j].sensor_data.data[2] = last_data_xl[2] + diff[5]; - fifo_out_slot[j].timestamp = last_timestamp; - (void)memcpy(last_data_xl, fifo_out_slot[j].sensor_data.raw_data, 6); - last_timestamp_xl = last_timestamp; - } - - if (sensor_type == ST_FIFO_GYROSCOPE) - { - uint32_t last_timestamp = timestamp - dtime_gy; - fifo_out_slot[j].sensor_data.data[0] = last_data_gy[0] + diff[3]; - fifo_out_slot[j].sensor_data.data[1] = last_data_gy[1] + diff[4]; - fifo_out_slot[j].sensor_data.data[2] = last_data_gy[2] + diff[5]; - fifo_out_slot[j].timestamp = last_timestamp; - (void)memcpy(last_data_gy, fifo_out_slot[j].sensor_data.raw_data, 6); - last_timestamp_gy = last_timestamp; - } - - j++; - - } - else /* compression_type == ST_FIFO_COMPRESSION_3X */ - { - int16_t diff[9]; - get_diff_3x(diff, &fifo_raw_slot[i].fifo_data_out[1]); - - fifo_out_slot[j].sensor_tag = sensor_type; - - if (sensor_type == ST_FIFO_ACCELEROMETER) - { - fifo_out_slot[j].sensor_data.data[0] = last_data_xl[0] + diff[0]; - fifo_out_slot[j].sensor_data.data[1] = last_data_xl[1] + diff[1]; - fifo_out_slot[j].sensor_data.data[2] = last_data_xl[2] + diff[2]; - fifo_out_slot[j].timestamp = timestamp - 2u * dtime_xl; - (void)memcpy(last_data_xl, fifo_out_slot[j].sensor_data.raw_data, 6); - } - - if (sensor_type == ST_FIFO_GYROSCOPE) - { - fifo_out_slot[j].sensor_data.data[0] = last_data_gy[0] + diff[0]; - fifo_out_slot[j].sensor_data.data[1] = last_data_gy[1] + diff[1]; - fifo_out_slot[j].sensor_data.data[2] = last_data_gy[2] + diff[2]; - fifo_out_slot[j].timestamp = timestamp - 2u * dtime_gy; - (void)memcpy(last_data_gy, fifo_out_slot[j].sensor_data.raw_data, 6); - } - - j++; - - fifo_out_slot[j].sensor_tag = sensor_type; - - if (sensor_type == ST_FIFO_ACCELEROMETER) - { - fifo_out_slot[j].sensor_data.data[0] = last_data_xl[0] + diff[3]; - fifo_out_slot[j].sensor_data.data[1] = last_data_xl[1] + diff[4]; - fifo_out_slot[j].sensor_data.data[2] = last_data_xl[2] + diff[5]; - fifo_out_slot[j].timestamp = timestamp - dtime_xl; - (void)memcpy(last_data_xl, fifo_out_slot[j].sensor_data.raw_data, 6); - } - - if (sensor_type == ST_FIFO_GYROSCOPE) - { - fifo_out_slot[j].sensor_data.data[0] = last_data_gy[0] + diff[3]; - fifo_out_slot[j].sensor_data.data[1] = last_data_gy[1] + diff[4]; - fifo_out_slot[j].sensor_data.data[2] = last_data_gy[2] + diff[5]; - fifo_out_slot[j].timestamp = timestamp - dtime_gy; - (void)memcpy(last_data_gy, fifo_out_slot[j].sensor_data.raw_data, 6); - } - - j++; - - fifo_out_slot[j].timestamp = timestamp; - fifo_out_slot[j].sensor_tag = sensor_type; - - if (sensor_type == ST_FIFO_ACCELEROMETER) - { - fifo_out_slot[j].sensor_data.data[0] = last_data_xl[0] + diff[6]; - fifo_out_slot[j].sensor_data.data[1] = last_data_xl[1] + diff[7]; - fifo_out_slot[j].sensor_data.data[2] = last_data_xl[2] + diff[8]; - (void)memcpy(last_data_xl, fifo_out_slot[j].sensor_data.raw_data, 6); - last_timestamp_xl = timestamp; - } - - if (sensor_type == ST_FIFO_GYROSCOPE) - { - fifo_out_slot[j].sensor_data.data[0] = last_data_gy[0] + diff[6]; - fifo_out_slot[j].sensor_data.data[1] = last_data_gy[1] + diff[7]; - fifo_out_slot[j].sensor_data.data[2] = last_data_gy[2] + diff[8]; - (void)memcpy(last_data_gy, fifo_out_slot[j].sensor_data.raw_data, 6); - last_timestamp_gy = timestamp; - } - - j++; - } - - *out_slot_size = j; - } - - tag_counter_old = tag_counter; - } - - return ST_FIFO_OK; -} - -/** - * @brief Sort FIFO stream from older to newer timestamp. - * - * @param fifo_out_slot decoded output stream to sort.(ptr) - * @param out_slot_size decoded stream size. - * - */ -void st_fifo_sort(st_fifo_out_slot *fifo_out_slot, uint16_t out_slot_size) -{ - int32_t i; - int32_t j; - st_fifo_out_slot temp; - - for (i = 1; i < (int32_t)out_slot_size; i++) - { - (void)memcpy(&temp, &fifo_out_slot[i], sizeof(st_fifo_out_slot)); - - j = i - 1; - - while (j >= 0 && fifo_out_slot[j].timestamp > temp.timestamp) - { - (void)memcpy(&fifo_out_slot[j + 1], &fifo_out_slot[j], - sizeof(st_fifo_out_slot)); - j--; - } - - (void)memcpy(&fifo_out_slot[j + 1], &temp, sizeof(st_fifo_out_slot)); - } - - return; -} - -/** - * @brief Return the number of a sensor tag occurrencies in a - * decoded FIFO stream. - * - * @param fifo_out_slot decoded output stream.(ptr) - * @param out_slot_size decoded stream size. - * @param sensor_type sensor type for the number of occurrencies count. - * - * @retval uint16_t the number of a sensor tag occurrencies in a - * decoded FIFO stream. - * - */ -uint16_t st_fifo_get_sensor_occurrence(st_fifo_out_slot *fifo_out_slot, - uint16_t out_slot_size, st_fifo_sensor_type sensor_type) -{ - uint16_t occurrence = 0; - - for (uint16_t i = 0; i < out_slot_size; i++) - { - if (fifo_out_slot[i].sensor_tag == sensor_type) - { - occurrence++; - } - } - - return occurrence; -} - -/** - * @brief This function extracts all the data of a specific sensor - * from a decoded FIFO stream. - * - * @param sensor_out_slot data of a specific sensor.(ptr) - * @param fifo_out_slot decoded output stream.(ptr) - * @param out_slot_size decoded stream size. - * @param sensor_type sensor type for the number of occurrencies count. - * - */ -void st_fifo_extract_sensor(st_fifo_out_slot *sensor_out_slot, - st_fifo_out_slot *fifo_out_slot, uint16_t out_slot_size, - st_fifo_sensor_type sensor_type) -{ - uint16_t temp_i = 0; - - for (uint16_t i = 0; i < out_slot_size; i++) - { - if (fifo_out_slot[i].sensor_tag == sensor_type) - { - (void)memcpy(&sensor_out_slot[temp_i], &fifo_out_slot[i], - sizeof(st_fifo_out_slot)); - temp_i++; - } - } -} - -/** - * @} - * - */ - -/** - * @defgroup FIFO private functions - * @brief This section provide a set of private functions - * used by the public APIs. - * @{ - * - */ - -/** - * @brief This function indicate if a raw tag is valid or not. - * - * @param tag tag to be analyzed. - * - * @retval uint8_t valid (1) or invalid (0) tag. - * - */ -static uint8_t is_tag_valid(uint8_t tag) -{ - if (tag > device[fifo_ver].tag_valid_limit) - { - return 0; - } - else - { - return 1; - } -} - -/** - * @brief This function convert a raw tag in a sensor type. - * - * @param tag tag to be analyzed. - * - * @retval st_fifo_sensor_type sensor type. - * - */ -static st_fifo_sensor_type get_sensor_type(uint8_t tag) -{ - st_fifo_sensor_type type; - - switch (tag) - { - case TAG_GY: - type = ST_FIFO_GYROSCOPE; - break; - case TAG_XL: - type = ST_FIFO_ACCELEROMETER; - break; - case TAG_TEMP: - type = ST_FIFO_TEMPERATURE; - break; - case TAG_EXT_SENS_0: - type = ST_FIFO_EXT_SENSOR0; - break; - case TAG_EXT_SENS_1: - type = ST_FIFO_EXT_SENSOR1; - break; - case TAG_EXT_SENS_2: - type = ST_FIFO_EXT_SENSOR2; - break; - case TAG_EXT_SENS_3: - type = ST_FIFO_EXT_SENSOR3; - break; - case TAG_STEP_COUNTER: - type = ST_FIFO_STEP_COUNTER; - break; - case TAG_XL_UNCOMPRESSED_T_2: - type = ST_FIFO_ACCELEROMETER; - break; - case TAG_XL_UNCOMPRESSED_T_1: - type = ST_FIFO_ACCELEROMETER; - break; - case TAG_XL_COMPRESSED_2X: - type = ST_FIFO_ACCELEROMETER; - break; - case TAG_XL_COMPRESSED_3X: - type = ST_FIFO_ACCELEROMETER; - break; - case TAG_GY_UNCOMPRESSED_T_2: - type = ST_FIFO_GYROSCOPE; - break; - case TAG_GY_UNCOMPRESSED_T_1: - type = ST_FIFO_GYROSCOPE; - break; - case TAG_GY_COMPRESSED_2X: - type = ST_FIFO_GYROSCOPE; - break; - case TAG_GY_COMPRESSED_3X: - type = ST_FIFO_GYROSCOPE; - break; - case TAG_GAME_RV: - type = ST_FIFO_6X_GAME_RV; - break; - case TAG_GEOM_RV: - type = ST_FIFO_6X_GEOM_RV; - break; - case TAG_NORM_RV: - type = ST_FIFO_9X_RV; - break; - case TAG_GYRO_BIAS: - type = ST_FIFO_GYRO_BIAS; - break; - case TAG_GRAVITIY: - type = ST_FIFO_GRAVITY; - break; - case TAG_MAG_CAL: - type = ST_FIFO_MAGNETOMETER_CALIB; - break; - case TAG_EXT_SENS_NACK: - type = ST_FIFO_EXT_SENSOR_NACK; - break; - case TAG_MLC_RESULT: - type = ST_FIFO_MLC_RESULT; - break; - case TAG_MLC_FILTER: - type = ST_FIFO_MLC_FILTER; - break; - case TAG_MLC_FEATURE: - type = ST_FIFO_MLC_FEATURE; - break; - case TAG_DUALC_XL: - type = ST_FIFO_DUALC_ACCELEROMETER; - break; - case TAG_EIS_GY: - type = ST_FIFO_EIS_GYROSCOPE; - break; - default: - type = ST_FIFO_NONE; - break; - } - - return type; -} - -/** - * @brief This function convert a raw tag in a type of compression. - * - * @param tag tag to be analyzed. - * - * @retval st_fifo_compression_type compression type. - * - */ -static st_fifo_compression_type get_compression_type(uint8_t tag) -{ - st_fifo_compression_type type; - - switch (tag) - { - case TAG_XL_UNCOMPRESSED_T_2: - type = ST_FIFO_COMPRESSION_NC_T_2; - break; - case TAG_XL_UNCOMPRESSED_T_1: - type = ST_FIFO_COMPRESSION_NC_T_1; - break; - case TAG_XL_COMPRESSED_2X: - type = ST_FIFO_COMPRESSION_2X; - break; - case TAG_XL_COMPRESSED_3X: - type = ST_FIFO_COMPRESSION_3X; - break; - case TAG_GY_UNCOMPRESSED_T_2: - type = ST_FIFO_COMPRESSION_NC_T_2; - break; - case TAG_GY_UNCOMPRESSED_T_1: - type = ST_FIFO_COMPRESSION_NC_T_1; - break; - case TAG_GY_COMPRESSED_2X: - type = ST_FIFO_COMPRESSION_2X; - break; - case TAG_GY_COMPRESSED_3X: - type = ST_FIFO_COMPRESSION_3X; - break; - default: - type = ST_FIFO_COMPRESSION_NC; - break; - } - - return type; -} - -/** - * @brief This function get the index of the nearest BDR. - * - * @param bdr array with the BDR values.(ptr) - * @param n input value to be considered - * - * @retval uint8_t index of the nearest BDR. - * - */ -static uint8_t bdr_get_index(const float *bdr, float n) -{ - float diff[16], min = FLT_MAX; - uint8_t idx = 0; - - for (uint8_t i = 0; i < 16u; i++) - { - diff[i] = fabsf(bdr[i] - n); - } - - for (uint8_t i = 0; i < 16u; i++) - { - if (diff[i] < min) - { - min = diff[i]; - idx = i; - } - } - - return idx; -} - -/** - * @brief This function check the parity of a byte. - * - * @param x byte to be analyzed. - * - * @retval uint8_t the byte has even parity (1) or not (0). - * - */ -static uint8_t has_even_parity(uint8_t x) -{ - uint8_t count = 0x00, b = 0x01; - - for (uint8_t i = 0; i < 8u; i++) - { - if ((x & (b << i)) != 0x00u) - { - count++; - } - } - - if ((count & 0x01u) == 0x01u) - { - return 0; - } - - return 1; -} - -/** - * @brief Convert raw data FIFO into compressed data (2x). - * - * @param diff[6] compressed data (2x). - * @param input[6] FIFO raw word without tag. - * - */ -static void get_diff_2x(int16_t diff[6], uint8_t input[6]) -{ - for (uint8_t i = 0; i < 6u; i++) - { - diff[i] = input[i] < 128u ? (int16_t)input[i] : (int16_t)input[i] - 256; - } -} - -/** - * @brief Convert raw data FIFO into compressed data (3x). - * - * @param diff[6] compressed data (3x). - * @param input[6] FIFO raw word without tag. - * - */ -static void get_diff_3x(int16_t diff[9], uint8_t input[6]) -{ - uint16_t decode_tmp; - - for (uint8_t i = 0; i < 3u; i++) - { - - (void)memcpy(&decode_tmp, &input[2u * i], 2); - - for (uint8_t j = 0; j < 3u; j++) - { - uint16_t utmp = (decode_tmp & ((uint16_t)0x1Fu << (5u * j))) >> (5u * j); - int16_t tmp = (int16_t)utmp; - diff[j + 3u * i] = tmp < 16 ? tmp : (tmp - 32); - } - } -} - -/** - * @} - * - */ - -/** - * @} - * - */ diff --git a/sensor/stmemsc/_resources/FIFO_Utility_Tool/st_fifo.h b/sensor/stmemsc/_resources/FIFO_Utility_Tool/st_fifo.h deleted file mode 100644 index 10c534d6..00000000 --- a/sensor/stmemsc/_resources/FIFO_Utility_Tool/st_fifo.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - ****************************************************************************** - * @file st_fifo.h - * @author Sensor Solutions Software Team - * @brief Utility for managing FIFO data decoding and decompression. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2022 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef ST_FIFO_H -#define ST_FIFO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include - -/** @addtogroup FIFO utility - * @{ - * - */ - -/** @defgroup FIFO public definitions - * @{ - * - */ - -typedef enum -{ - ST_FIFO_OK, - ST_FIFO_ERR -} st_fifo_status; - -typedef enum -{ - ST_FIFO_GYROSCOPE, - ST_FIFO_ACCELEROMETER, - ST_FIFO_TEMPERATURE, - ST_FIFO_EXT_SENSOR0, - ST_FIFO_EXT_SENSOR1, - ST_FIFO_EXT_SENSOR2, - ST_FIFO_EXT_SENSOR3, - ST_FIFO_STEP_COUNTER, - ST_FIFO_6X_GAME_RV, - ST_FIFO_6X_GEOM_RV, - ST_FIFO_9X_RV, - ST_FIFO_GYRO_BIAS, - ST_FIFO_GRAVITY, - ST_FIFO_MAGNETOMETER_CALIB, - ST_FIFO_EXT_SENSOR_NACK, - ST_FIFO_MLC_RESULT, - ST_FIFO_MLC_FILTER, - ST_FIFO_MLC_FEATURE, - ST_FIFO_DUALC_ACCELEROMETER, - ST_FIFO_EIS_GYROSCOPE, - ST_FIFO_NONE -} st_fifo_sensor_type; - -typedef struct -{ - uint8_t fifo_data_out[7]; /* registers from mems (78h -> 7Dh) */ -} st_fifo_raw_slot; - -typedef struct -{ - uint32_t timestamp; - st_fifo_sensor_type sensor_tag; - union - { - uint8_t raw_data[6]; /* bytes */ - int16_t data[3]; /* 3-axis mems */ - struct - { - int16_t x; - int16_t y; - int16_t z; - }; /* 3-axis mems */ - struct - { - int16_t temp; - }; /* temperature sensor */ - struct - { - uint16_t steps; - uint8_t steps_t[4]; - }; /* step counter */ - struct - { - uint16_t qx; - uint16_t qy; - uint16_t qz; - }; /* quaternion */ - struct - { - uint8_t nack; - }; /* ext sensor nack index */ - struct - { - uint8_t mlc_res; - uint8_t mlc_idx; - uint8_t mlc_t[4]; - }; /* mlc result */ - struct - { - uint16_t mlc_value; - uint16_t mlc_id; - uint16_t reserved; - }; /* mlc filter / feature */ - } sensor_data; -} st_fifo_out_slot; - -typedef enum -{ - ST_FIFO_LSM6DSR, - ST_FIFO_LSM6DSRX, - ST_FIFO_ASM330LHH, - ST_FIFO_ASM330LHHX, - ST_FIFO_ISM330DHCX, - ST_FIFO_LSM6DSO, - ST_FIFO_LSM6DSOX, - ST_FIFO_LSM6DSO32, - ST_FIFO_LSM6DSO32X, - ST_FIFO_LSM6DSV, - ST_FIFO_LSM6DSV16X, - ST_FIFO_LSM6DSV32X, -} st_fifo_device; - -typedef struct -{ - st_fifo_device device; /* device to select */ - float bdr_xl; /* accelerometer batch data rate in Hz */ - float bdr_gy; /* gyroscope batch data rate in Hz */ - float bdr_vsens; /* virtual sensor batch data rate in Hz */ -} st_fifo_conf; - -/** - * @} - * - */ - -st_fifo_status st_fifo_init(st_fifo_conf *conf); -st_fifo_status st_fifo_decode(st_fifo_out_slot *fifo_out_slot, - st_fifo_raw_slot *fifo_raw_slot, uint16_t *out_slot_size, uint16_t stream_size); -void st_fifo_sort(st_fifo_out_slot *fifo_out_slot, uint16_t out_slot_size); -uint16_t st_fifo_get_sensor_occurrence(st_fifo_out_slot *fifo_out_slot, - uint16_t out_slot_size, st_fifo_sensor_type sensor_type); -void st_fifo_extract_sensor(st_fifo_out_slot *sensor_out_slot, - st_fifo_out_slot *fifo_out_slot, uint16_t out_slot_size, - st_fifo_sensor_type sensor_type); - -#ifdef __cplusplus -} -#endif - -#endif /* ST_FIFO_H */ - -/** - * @} - * - */ diff --git a/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.c b/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.c index 564c07ac..af3100f7 100644 --- a/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.c +++ b/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.c @@ -46,12 +46,14 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak a3g4250d_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak a3g4250d_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +69,14 @@ int32_t __weak a3g4250d_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak a3g4250d_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak a3g4250d_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -121,7 +125,7 @@ float_t a3g4250d_from_lsb_to_celsius(int16_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_data_rate_set(stmdev_ctx_t *ctx, a3g4250d_dr_t val) +int32_t a3g4250d_data_rate_set(const stmdev_ctx_t *ctx, a3g4250d_dr_t val) { a3g4250d_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -148,7 +152,7 @@ int32_t a3g4250d_data_rate_set(stmdev_ctx_t *ctx, a3g4250d_dr_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_data_rate_get(stmdev_ctx_t *ctx, a3g4250d_dr_t *val) +int32_t a3g4250d_data_rate_get(const stmdev_ctx_t *ctx, a3g4250d_dr_t *val) { a3g4250d_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -198,7 +202,7 @@ int32_t a3g4250d_data_rate_get(stmdev_ctx_t *ctx, a3g4250d_dr_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_status_reg_get(stmdev_ctx_t *ctx, a3g4250d_status_reg_t *val) +int32_t a3g4250d_status_reg_get(const stmdev_ctx_t *ctx, a3g4250d_status_reg_t *val) { int32_t ret; @@ -215,7 +219,7 @@ int32_t a3g4250d_status_reg_get(stmdev_ctx_t *ctx, a3g4250d_status_reg_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t a3g4250d_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { a3g4250d_status_reg_t status_reg; int32_t ret; @@ -246,7 +250,7 @@ int32_t a3g4250d_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t a3g4250d_temperature_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -264,7 +268,7 @@ int32_t a3g4250d_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t a3g4250d_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -300,7 +304,7 @@ int32_t a3g4250d_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t a3g4250d_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -317,7 +321,7 @@ int32_t a3g4250d_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_self_test_set(stmdev_ctx_t *ctx, a3g4250d_st_t val) +int32_t a3g4250d_self_test_set(const stmdev_ctx_t *ctx, a3g4250d_st_t val) { a3g4250d_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -343,7 +347,7 @@ int32_t a3g4250d_self_test_set(stmdev_ctx_t *ctx, a3g4250d_st_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_self_test_get(stmdev_ctx_t *ctx, a3g4250d_st_t *val) +int32_t a3g4250d_self_test_get(const stmdev_ctx_t *ctx, a3g4250d_st_t *val) { a3g4250d_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -381,7 +385,7 @@ int32_t a3g4250d_self_test_get(stmdev_ctx_t *ctx, a3g4250d_st_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_data_format_set(stmdev_ctx_t *ctx, a3g4250d_ble_t val) +int32_t a3g4250d_data_format_set(const stmdev_ctx_t *ctx, a3g4250d_ble_t val) { a3g4250d_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -407,7 +411,7 @@ int32_t a3g4250d_data_format_set(stmdev_ctx_t *ctx, a3g4250d_ble_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_data_format_get(stmdev_ctx_t *ctx, a3g4250d_ble_t *val) +int32_t a3g4250d_data_format_get(const stmdev_ctx_t *ctx, a3g4250d_ble_t *val) { a3g4250d_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -441,7 +445,7 @@ int32_t a3g4250d_data_format_get(stmdev_ctx_t *ctx, a3g4250d_ble_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t a3g4250d_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { a3g4250d_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -467,7 +471,7 @@ int32_t a3g4250d_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t a3g4250d_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { a3g4250d_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -500,7 +504,7 @@ int32_t a3g4250d_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_lp_bandwidth_set(stmdev_ctx_t *ctx, a3g4250d_bw_t val) +int32_t a3g4250d_lp_bandwidth_set(const stmdev_ctx_t *ctx, a3g4250d_bw_t val) { a3g4250d_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -526,7 +530,7 @@ int32_t a3g4250d_lp_bandwidth_set(stmdev_ctx_t *ctx, a3g4250d_bw_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_lp_bandwidth_get(stmdev_ctx_t *ctx, a3g4250d_bw_t *val) +int32_t a3g4250d_lp_bandwidth_get(const stmdev_ctx_t *ctx, a3g4250d_bw_t *val) { a3g4250d_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -568,7 +572,7 @@ int32_t a3g4250d_lp_bandwidth_get(stmdev_ctx_t *ctx, a3g4250d_bw_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_hp_bandwidth_set(stmdev_ctx_t *ctx, a3g4250d_hpcf_t val) +int32_t a3g4250d_hp_bandwidth_set(const stmdev_ctx_t *ctx, a3g4250d_hpcf_t val) { a3g4250d_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -594,7 +598,7 @@ int32_t a3g4250d_hp_bandwidth_set(stmdev_ctx_t *ctx, a3g4250d_hpcf_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_hp_bandwidth_get(stmdev_ctx_t *ctx, a3g4250d_hpcf_t *val) +int32_t a3g4250d_hp_bandwidth_get(const stmdev_ctx_t *ctx, a3g4250d_hpcf_t *val) { a3g4250d_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -660,7 +664,7 @@ int32_t a3g4250d_hp_bandwidth_get(stmdev_ctx_t *ctx, a3g4250d_hpcf_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_hp_mode_set(stmdev_ctx_t *ctx, a3g4250d_hpm_t val) +int32_t a3g4250d_hp_mode_set(const stmdev_ctx_t *ctx, a3g4250d_hpm_t val) { a3g4250d_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -686,7 +690,7 @@ int32_t a3g4250d_hp_mode_set(stmdev_ctx_t *ctx, a3g4250d_hpm_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_hp_mode_get(stmdev_ctx_t *ctx, a3g4250d_hpm_t *val) +int32_t a3g4250d_hp_mode_get(const stmdev_ctx_t *ctx, a3g4250d_hpm_t *val) { a3g4250d_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -728,7 +732,7 @@ int32_t a3g4250d_hp_mode_get(stmdev_ctx_t *ctx, a3g4250d_hpm_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_filter_path_set(stmdev_ctx_t *ctx, a3g4250d_out_sel_t val) +int32_t a3g4250d_filter_path_set(const stmdev_ctx_t *ctx, a3g4250d_out_sel_t val) { a3g4250d_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -755,7 +759,7 @@ int32_t a3g4250d_filter_path_set(stmdev_ctx_t *ctx, a3g4250d_out_sel_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_filter_path_get(stmdev_ctx_t *ctx, a3g4250d_out_sel_t *val) +int32_t a3g4250d_filter_path_get(const stmdev_ctx_t *ctx, a3g4250d_out_sel_t *val) { a3g4250d_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -797,7 +801,7 @@ int32_t a3g4250d_filter_path_get(stmdev_ctx_t *ctx, a3g4250d_out_sel_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_filter_path_internal_set(stmdev_ctx_t *ctx, +int32_t a3g4250d_filter_path_internal_set(const stmdev_ctx_t *ctx, a3g4250d_int1_sel_t val) { a3g4250d_ctrl_reg5_t ctrl_reg5; @@ -825,7 +829,7 @@ int32_t a3g4250d_filter_path_internal_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_filter_path_internal_get(stmdev_ctx_t *ctx, +int32_t a3g4250d_filter_path_internal_get(const stmdev_ctx_t *ctx, a3g4250d_int1_sel_t *val) { a3g4250d_ctrl_reg5_t ctrl_reg5; @@ -868,7 +872,7 @@ int32_t a3g4250d_filter_path_internal_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_hp_reference_value_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t a3g4250d_hp_reference_value_set(const stmdev_ctx_t *ctx, uint8_t val) { a3g4250d_reference_t reference; int32_t ret; @@ -894,7 +898,7 @@ int32_t a3g4250d_hp_reference_value_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_hp_reference_value_get(stmdev_ctx_t *ctx, +int32_t a3g4250d_hp_reference_value_get(const stmdev_ctx_t *ctx, uint8_t *val) { a3g4250d_reference_t reference; @@ -928,7 +932,7 @@ int32_t a3g4250d_hp_reference_value_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_spi_mode_set(stmdev_ctx_t *ctx, a3g4250d_sim_t val) +int32_t a3g4250d_spi_mode_set(const stmdev_ctx_t *ctx, a3g4250d_sim_t val) { a3g4250d_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -954,7 +958,7 @@ int32_t a3g4250d_spi_mode_set(stmdev_ctx_t *ctx, a3g4250d_sim_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_spi_mode_get(stmdev_ctx_t *ctx, a3g4250d_sim_t *val) +int32_t a3g4250d_spi_mode_get(const stmdev_ctx_t *ctx, a3g4250d_sim_t *val) { a3g4250d_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -1002,7 +1006,7 @@ int32_t a3g4250d_spi_mode_get(stmdev_ctx_t *ctx, a3g4250d_sim_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t a3g4250d_pin_int1_route_set(const stmdev_ctx_t *ctx, a3g4250d_int1_route_t val) { a3g4250d_ctrl_reg3_t ctrl_reg3; @@ -1031,7 +1035,7 @@ int32_t a3g4250d_pin_int1_route_set(stmdev_ctx_t *ctx, * */ -int32_t a3g4250d_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t a3g4250d_pin_int1_route_get(const stmdev_ctx_t *ctx, a3g4250d_int1_route_t *val) { a3g4250d_ctrl_reg3_t ctrl_reg3; @@ -1052,7 +1056,7 @@ int32_t a3g4250d_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t a3g4250d_pin_int2_route_set(const stmdev_ctx_t *ctx, a3g4250d_int2_route_t val) { a3g4250d_ctrl_reg3_t ctrl_reg3; @@ -1082,7 +1086,7 @@ int32_t a3g4250d_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t a3g4250d_pin_int2_route_get(const stmdev_ctx_t *ctx, a3g4250d_int2_route_t *val) { a3g4250d_ctrl_reg3_t ctrl_reg3; @@ -1106,7 +1110,7 @@ int32_t a3g4250d_pin_int2_route_get(stmdev_ctx_t *ctx, * */ -int32_t a3g4250d_pin_mode_set(stmdev_ctx_t *ctx, a3g4250d_pp_od_t val) +int32_t a3g4250d_pin_mode_set(const stmdev_ctx_t *ctx, a3g4250d_pp_od_t val) { a3g4250d_ctrl_reg3_t ctrl_reg3; int32_t ret; @@ -1132,7 +1136,7 @@ int32_t a3g4250d_pin_mode_set(stmdev_ctx_t *ctx, a3g4250d_pp_od_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_pin_mode_get(stmdev_ctx_t *ctx, +int32_t a3g4250d_pin_mode_get(const stmdev_ctx_t *ctx, a3g4250d_pp_od_t *val) { a3g4250d_ctrl_reg3_t ctrl_reg3; @@ -1167,7 +1171,7 @@ int32_t a3g4250d_pin_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t a3g4250d_pin_polarity_set(const stmdev_ctx_t *ctx, a3g4250d_h_lactive_t val) { a3g4250d_ctrl_reg3_t ctrl_reg3; @@ -1194,7 +1198,7 @@ int32_t a3g4250d_pin_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t a3g4250d_pin_polarity_get(const stmdev_ctx_t *ctx, a3g4250d_h_lactive_t *val) { a3g4250d_ctrl_reg3_t ctrl_reg3; @@ -1229,7 +1233,7 @@ int32_t a3g4250d_pin_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_int_notification_set(stmdev_ctx_t *ctx, a3g4250d_lir_t val) +int32_t a3g4250d_int_notification_set(const stmdev_ctx_t *ctx, a3g4250d_lir_t val) { a3g4250d_int1_cfg_t int1_cfg; int32_t ret; @@ -1253,7 +1257,7 @@ int32_t a3g4250d_int_notification_set(stmdev_ctx_t *ctx, a3g4250d_lir_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_int_notification_get(stmdev_ctx_t *ctx, a3g4250d_lir_t *val) +int32_t a3g4250d_int_notification_get(const stmdev_ctx_t *ctx, a3g4250d_lir_t *val) { a3g4250d_int1_cfg_t int1_cfg; int32_t ret; @@ -1299,7 +1303,7 @@ int32_t a3g4250d_int_notification_get(stmdev_ctx_t *ctx, a3g4250d_lir_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_int_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t a3g4250d_int_on_threshold_conf_set(const stmdev_ctx_t *ctx, a3g4250d_int1_cfg_t *val) { int32_t ret; @@ -1317,7 +1321,7 @@ int32_t a3g4250d_int_on_threshold_conf_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_int_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t a3g4250d_int_on_threshold_conf_get(const stmdev_ctx_t *ctx, a3g4250d_int1_cfg_t *val) { int32_t ret; @@ -1334,7 +1338,7 @@ int32_t a3g4250d_int_on_threshold_conf_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_int_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t a3g4250d_int_on_threshold_mode_set(const stmdev_ctx_t *ctx, a3g4250d_and_or_t val) { a3g4250d_int1_cfg_t int1_cfg; @@ -1359,7 +1363,7 @@ int32_t a3g4250d_int_on_threshold_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_int_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t a3g4250d_int_on_threshold_mode_get(const stmdev_ctx_t *ctx, a3g4250d_and_or_t *val) { a3g4250d_int1_cfg_t int1_cfg; @@ -1393,7 +1397,7 @@ int32_t a3g4250d_int_on_threshold_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_int_on_threshold_src_get(stmdev_ctx_t *ctx, +int32_t a3g4250d_int_on_threshold_src_get(const stmdev_ctx_t *ctx, a3g4250d_int1_src_t *val) { int32_t ret; @@ -1411,7 +1415,7 @@ int32_t a3g4250d_int_on_threshold_src_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_int_x_treshold_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t a3g4250d_int_x_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { a3g4250d_int1_tsh_xh_t int1_tsh_xh; a3g4250d_int1_tsh_xl_t int1_tsh_xl; @@ -1451,7 +1455,7 @@ int32_t a3g4250d_int_x_treshold_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_int_x_treshold_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t a3g4250d_int_x_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { a3g4250d_int1_tsh_xh_t int1_tsh_xh; a3g4250d_int1_tsh_xl_t int1_tsh_xl; @@ -1480,7 +1484,7 @@ int32_t a3g4250d_int_x_treshold_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_int_y_treshold_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t a3g4250d_int_y_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { a3g4250d_int1_tsh_yh_t int1_tsh_yh; a3g4250d_int1_tsh_yl_t int1_tsh_yl; @@ -1520,7 +1524,7 @@ int32_t a3g4250d_int_y_treshold_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_int_y_treshold_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t a3g4250d_int_y_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { a3g4250d_int1_tsh_yh_t int1_tsh_yh; a3g4250d_int1_tsh_yl_t int1_tsh_yl; @@ -1549,7 +1553,7 @@ int32_t a3g4250d_int_y_treshold_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_int_z_treshold_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t a3g4250d_int_z_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { a3g4250d_int1_tsh_zh_t int1_tsh_zh; a3g4250d_int1_tsh_zl_t int1_tsh_zl; @@ -1589,7 +1593,7 @@ int32_t a3g4250d_int_z_treshold_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_int_z_treshold_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t a3g4250d_int_z_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { a3g4250d_int1_tsh_zh_t int1_tsh_zh; a3g4250d_int1_tsh_zl_t int1_tsh_zl; @@ -1618,7 +1622,7 @@ int32_t a3g4250d_int_z_treshold_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_int_on_threshold_dur_set(stmdev_ctx_t *ctx, +int32_t a3g4250d_int_on_threshold_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { a3g4250d_int1_duration_t int1_duration; @@ -1656,7 +1660,7 @@ int32_t a3g4250d_int_on_threshold_dur_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_int_on_threshold_dur_get(stmdev_ctx_t *ctx, +int32_t a3g4250d_int_on_threshold_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { a3g4250d_int1_duration_t int1_duration; @@ -1689,7 +1693,7 @@ int32_t a3g4250d_int_on_threshold_dur_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_fifo_enable_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t a3g4250d_fifo_enable_set(const stmdev_ctx_t *ctx, uint8_t val) { a3g4250d_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1715,7 +1719,7 @@ int32_t a3g4250d_fifo_enable_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_fifo_enable_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t a3g4250d_fifo_enable_get(const stmdev_ctx_t *ctx, uint8_t *val) { a3g4250d_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1735,7 +1739,7 @@ int32_t a3g4250d_fifo_enable_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t a3g4250d_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { a3g4250d_fifo_ctrl_reg_t fifo_ctrl_reg; int32_t ret; @@ -1761,7 +1765,7 @@ int32_t a3g4250d_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t a3g4250d_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { a3g4250d_fifo_ctrl_reg_t fifo_ctrl_reg; int32_t ret; @@ -1781,7 +1785,7 @@ int32_t a3g4250d_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t a3g4250d_fifo_mode_set(const stmdev_ctx_t *ctx, a3g4250d_fifo_mode_t val) { a3g4250d_fifo_ctrl_reg_t fifo_ctrl_reg; @@ -1808,7 +1812,7 @@ int32_t a3g4250d_fifo_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t a3g4250d_fifo_mode_get(const stmdev_ctx_t *ctx, a3g4250d_fifo_mode_t *val) { a3g4250d_fifo_ctrl_reg_t fifo_ctrl_reg; @@ -1847,7 +1851,7 @@ int32_t a3g4250d_fifo_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t a3g4250d_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) { a3g4250d_fifo_src_reg_t fifo_src_reg; int32_t ret; @@ -1867,7 +1871,7 @@ int32_t a3g4250d_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t a3g4250d_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { a3g4250d_fifo_src_reg_t fifo_src_reg; int32_t ret; @@ -1887,7 +1891,7 @@ int32_t a3g4250d_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t a3g4250d_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t a3g4250d_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { a3g4250d_fifo_src_reg_t fifo_src_reg; int32_t ret; @@ -1910,7 +1914,7 @@ int32_t a3g4250d_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * */ -int32_t a3g4250d_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t a3g4250d_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { a3g4250d_fifo_src_reg_t fifo_src_reg; int32_t ret; diff --git a/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.h b/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.h index 40a2e089..37156ae0 100644 --- a/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.h +++ b/sensor/stmemsc/a3g4250d_STdC/driver/a3g4250d_reg.h @@ -503,24 +503,24 @@ typedef union * them with a custom implementation. */ -int32_t a3g4250d_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t a3g4250d_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t a3g4250d_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t a3g4250d_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); float_t a3g4250d_from_fs245dps_to_mdps(int16_t lsb); float_t a3g4250d_from_lsb_to_celsius(int16_t lsb); -int32_t a3g4250d_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t a3g4250d_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t a3g4250d_axis_x_data_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t a3g4250d_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t a3g4250d_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t a3g4250d_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t a3g4250d_axis_y_data_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t a3g4250d_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t a3g4250d_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t a3g4250d_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t a3g4250d_axis_z_data_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t a3g4250d_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -531,19 +531,19 @@ typedef enum A3G4250D_ODR_400Hz = 0x2F, A3G4250D_ODR_800Hz = 0x3F, } a3g4250d_dr_t; -int32_t a3g4250d_data_rate_set(stmdev_ctx_t *ctx, a3g4250d_dr_t val); -int32_t a3g4250d_data_rate_get(stmdev_ctx_t *ctx, a3g4250d_dr_t *val); +int32_t a3g4250d_data_rate_set(const stmdev_ctx_t *ctx, a3g4250d_dr_t val); +int32_t a3g4250d_data_rate_get(const stmdev_ctx_t *ctx, a3g4250d_dr_t *val); -int32_t a3g4250d_status_reg_get(stmdev_ctx_t *ctx, +int32_t a3g4250d_status_reg_get(const stmdev_ctx_t *ctx, a3g4250d_status_reg_t *val); -int32_t a3g4250d_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t a3g4250d_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t a3g4250d_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t a3g4250d_temperature_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t a3g4250d_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t a3g4250d_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t a3g4250d_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t a3g4250d_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); typedef enum { @@ -551,19 +551,19 @@ typedef enum A3G4250D_GY_ST_POSITIVE = 1, A3G4250D_GY_ST_NEGATIVE = 3, } a3g4250d_st_t; -int32_t a3g4250d_self_test_set(stmdev_ctx_t *ctx, a3g4250d_st_t val); -int32_t a3g4250d_self_test_get(stmdev_ctx_t *ctx, a3g4250d_st_t *val); +int32_t a3g4250d_self_test_set(const stmdev_ctx_t *ctx, a3g4250d_st_t val); +int32_t a3g4250d_self_test_get(const stmdev_ctx_t *ctx, a3g4250d_st_t *val); typedef enum { A3G4250D_AUX_LSB_AT_LOW_ADD = 0, A3G4250D_AUX_MSB_AT_LOW_ADD = 1, } a3g4250d_ble_t; -int32_t a3g4250d_data_format_set(stmdev_ctx_t *ctx, a3g4250d_ble_t val); -int32_t a3g4250d_data_format_get(stmdev_ctx_t *ctx, a3g4250d_ble_t *val); +int32_t a3g4250d_data_format_set(const stmdev_ctx_t *ctx, a3g4250d_ble_t val); +int32_t a3g4250d_data_format_get(const stmdev_ctx_t *ctx, a3g4250d_ble_t *val); -int32_t a3g4250d_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t a3g4250d_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t a3g4250d_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t a3g4250d_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -572,8 +572,8 @@ typedef enum A3G4250D_CUT_OFF_HIGH = 2, A3G4250D_CUT_OFF_VERY_HIGH = 3, } a3g4250d_bw_t; -int32_t a3g4250d_lp_bandwidth_set(stmdev_ctx_t *ctx, a3g4250d_bw_t val); -int32_t a3g4250d_lp_bandwidth_get(stmdev_ctx_t *ctx, a3g4250d_bw_t *val); +int32_t a3g4250d_lp_bandwidth_set(const stmdev_ctx_t *ctx, a3g4250d_bw_t val); +int32_t a3g4250d_lp_bandwidth_get(const stmdev_ctx_t *ctx, a3g4250d_bw_t *val); typedef enum { @@ -588,8 +588,8 @@ typedef enum A3G4250D_HP_LEVEL_8 = 8, A3G4250D_HP_LEVEL_9 = 9, } a3g4250d_hpcf_t; -int32_t a3g4250d_hp_bandwidth_set(stmdev_ctx_t *ctx, a3g4250d_hpcf_t val); -int32_t a3g4250d_hp_bandwidth_get(stmdev_ctx_t *ctx, a3g4250d_hpcf_t *val); +int32_t a3g4250d_hp_bandwidth_set(const stmdev_ctx_t *ctx, a3g4250d_hpcf_t val); +int32_t a3g4250d_hp_bandwidth_get(const stmdev_ctx_t *ctx, a3g4250d_hpcf_t *val); typedef enum { @@ -598,8 +598,8 @@ typedef enum A3G4250D_HP_NORMAL_MODE = 2, A3G4250D_HP_AUTO_RESET_ON_INT = 3, } a3g4250d_hpm_t; -int32_t a3g4250d_hp_mode_set(stmdev_ctx_t *ctx, a3g4250d_hpm_t val); -int32_t a3g4250d_hp_mode_get(stmdev_ctx_t *ctx, a3g4250d_hpm_t *val); +int32_t a3g4250d_hp_mode_set(const stmdev_ctx_t *ctx, a3g4250d_hpm_t val); +int32_t a3g4250d_hp_mode_get(const stmdev_ctx_t *ctx, a3g4250d_hpm_t *val); typedef enum { @@ -608,8 +608,8 @@ typedef enum A3G4250D_LPF1_LPF2_ON_OUT = 2, A3G4250D_LPF1_HP_LPF2_ON_OUT = 6, } a3g4250d_out_sel_t; -int32_t a3g4250d_filter_path_set(stmdev_ctx_t *ctx, a3g4250d_out_sel_t val); -int32_t a3g4250d_filter_path_get(stmdev_ctx_t *ctx, a3g4250d_out_sel_t *val); +int32_t a3g4250d_filter_path_set(const stmdev_ctx_t *ctx, a3g4250d_out_sel_t val); +int32_t a3g4250d_filter_path_get(const stmdev_ctx_t *ctx, a3g4250d_out_sel_t *val); typedef enum { @@ -618,30 +618,30 @@ typedef enum A3G4250D_LPF1_LPF2_ON_INT = 2, A3G4250D_LPF1_HP_LPF2_ON_INT = 6, } a3g4250d_int1_sel_t; -int32_t a3g4250d_filter_path_internal_set(stmdev_ctx_t *ctx, +int32_t a3g4250d_filter_path_internal_set(const stmdev_ctx_t *ctx, a3g4250d_int1_sel_t val); -int32_t a3g4250d_filter_path_internal_get(stmdev_ctx_t *ctx, +int32_t a3g4250d_filter_path_internal_get(const stmdev_ctx_t *ctx, a3g4250d_int1_sel_t *val); -int32_t a3g4250d_hp_reference_value_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t a3g4250d_hp_reference_value_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t a3g4250d_hp_reference_value_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t a3g4250d_hp_reference_value_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { A3G4250D_SPI_4_WIRE = 0, A3G4250D_SPI_3_WIRE = 1, } a3g4250d_sim_t; -int32_t a3g4250d_spi_mode_set(stmdev_ctx_t *ctx, a3g4250d_sim_t val); -int32_t a3g4250d_spi_mode_get(stmdev_ctx_t *ctx, a3g4250d_sim_t *val); +int32_t a3g4250d_spi_mode_set(const stmdev_ctx_t *ctx, a3g4250d_sim_t val); +int32_t a3g4250d_spi_mode_get(const stmdev_ctx_t *ctx, a3g4250d_sim_t *val); typedef struct { uint8_t i1_int1 : 1; uint8_t i1_boot : 1; } a3g4250d_int1_route_t; -int32_t a3g4250d_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t a3g4250d_pin_int1_route_set(const stmdev_ctx_t *ctx, a3g4250d_int1_route_t val); -int32_t a3g4250d_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t a3g4250d_pin_int1_route_get(const stmdev_ctx_t *ctx, a3g4250d_int1_route_t *val); typedef struct @@ -651,9 +651,9 @@ typedef struct uint8_t i2_wtm : 1; uint8_t i2_drdy : 1; } a3g4250d_int2_route_t; -int32_t a3g4250d_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t a3g4250d_pin_int2_route_set(const stmdev_ctx_t *ctx, a3g4250d_int2_route_t val); -int32_t a3g4250d_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t a3g4250d_pin_int2_route_get(const stmdev_ctx_t *ctx, a3g4250d_int2_route_t *val); typedef enum @@ -661,17 +661,17 @@ typedef enum A3G4250D_PUSH_PULL = 0, A3G4250D_OPEN_DRAIN = 1, } a3g4250d_pp_od_t; -int32_t a3g4250d_pin_mode_set(stmdev_ctx_t *ctx, a3g4250d_pp_od_t val); -int32_t a3g4250d_pin_mode_get(stmdev_ctx_t *ctx, a3g4250d_pp_od_t *val); +int32_t a3g4250d_pin_mode_set(const stmdev_ctx_t *ctx, a3g4250d_pp_od_t val); +int32_t a3g4250d_pin_mode_get(const stmdev_ctx_t *ctx, a3g4250d_pp_od_t *val); typedef enum { A3G4250D_ACTIVE_HIGH = 0, A3G4250D_ACTIVE_LOW = 1, } a3g4250d_h_lactive_t; -int32_t a3g4250d_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t a3g4250d_pin_polarity_set(const stmdev_ctx_t *ctx, a3g4250d_h_lactive_t val); -int32_t a3g4250d_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t a3g4250d_pin_polarity_get(const stmdev_ctx_t *ctx, a3g4250d_h_lactive_t *val); typedef enum @@ -679,12 +679,12 @@ typedef enum A3G4250D_INT_PULSED = 0, A3G4250D_INT_LATCHED = 1, } a3g4250d_lir_t; -int32_t a3g4250d_int_notification_set(stmdev_ctx_t *ctx, a3g4250d_lir_t val); -int32_t a3g4250d_int_notification_get(stmdev_ctx_t *ctx, a3g4250d_lir_t *val); +int32_t a3g4250d_int_notification_set(const stmdev_ctx_t *ctx, a3g4250d_lir_t val); +int32_t a3g4250d_int_notification_get(const stmdev_ctx_t *ctx, a3g4250d_lir_t *val); -int32_t a3g4250d_int_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t a3g4250d_int_on_threshold_conf_set(const stmdev_ctx_t *ctx, a3g4250d_int1_cfg_t *val); -int32_t a3g4250d_int_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t a3g4250d_int_on_threshold_conf_get(const stmdev_ctx_t *ctx, a3g4250d_int1_cfg_t *val); typedef enum @@ -692,31 +692,31 @@ typedef enum A3G4250D_INT1_ON_TH_AND = 1, A3G4250D_INT1_ON_TH_OR = 0, } a3g4250d_and_or_t; -int32_t a3g4250d_int_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t a3g4250d_int_on_threshold_mode_set(const stmdev_ctx_t *ctx, a3g4250d_and_or_t val); -int32_t a3g4250d_int_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t a3g4250d_int_on_threshold_mode_get(const stmdev_ctx_t *ctx, a3g4250d_and_or_t *val); -int32_t a3g4250d_int_on_threshold_src_get(stmdev_ctx_t *ctx, +int32_t a3g4250d_int_on_threshold_src_get(const stmdev_ctx_t *ctx, a3g4250d_int1_src_t *val); -int32_t a3g4250d_int_x_treshold_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t a3g4250d_int_x_treshold_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t a3g4250d_int_x_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t a3g4250d_int_x_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t a3g4250d_int_y_treshold_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t a3g4250d_int_y_treshold_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t a3g4250d_int_y_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t a3g4250d_int_y_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t a3g4250d_int_z_treshold_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t a3g4250d_int_z_treshold_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t a3g4250d_int_z_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t a3g4250d_int_z_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t a3g4250d_int_on_threshold_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t a3g4250d_int_on_threshold_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t a3g4250d_int_on_threshold_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t a3g4250d_int_on_threshold_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t a3g4250d_fifo_enable_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t a3g4250d_fifo_enable_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t a3g4250d_fifo_enable_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t a3g4250d_fifo_enable_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t a3g4250d_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t a3g4250d_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t a3g4250d_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t a3g4250d_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -724,16 +724,16 @@ typedef enum A3G4250D_FIFO_MODE = 0x01, A3G4250D_FIFO_STREAM_MODE = 0x02, } a3g4250d_fifo_mode_t; -int32_t a3g4250d_fifo_mode_set(stmdev_ctx_t *ctx, a3g4250d_fifo_mode_t val); -int32_t a3g4250d_fifo_mode_get(stmdev_ctx_t *ctx, a3g4250d_fifo_mode_t *val); +int32_t a3g4250d_fifo_mode_set(const stmdev_ctx_t *ctx, a3g4250d_fifo_mode_t val); +int32_t a3g4250d_fifo_mode_get(const stmdev_ctx_t *ctx, a3g4250d_fifo_mode_t *val); -int32_t a3g4250d_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t a3g4250d_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t a3g4250d_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t a3g4250d_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t a3g4250d_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t a3g4250d_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t a3g4250d_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t a3g4250d_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); /** * @} diff --git a/sensor/stmemsc/ais25ba_STdC/driver/ais25ba_reg.c b/sensor/stmemsc/ais25ba_STdC/driver/ais25ba_reg.c index d9f014bb..37f33e96 100644 --- a/sensor/stmemsc/ais25ba_STdC/driver/ais25ba_reg.c +++ b/sensor/stmemsc/ais25ba_STdC/driver/ais25ba_reg.c @@ -46,12 +46,14 @@ * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t __weak ais25ba_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak ais25ba_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +69,14 @@ int32_t __weak ais25ba_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t __weak ais25ba_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak ais25ba_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -136,7 +140,7 @@ float_t ais25ba_from_raw_to_mg(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ais25ba_id_get(stmdev_ctx_t *ctx, ais25ba_id_t *val) +int32_t ais25ba_id_get(const stmdev_ctx_t *ctx, ais25ba_id_t *val) { int32_t ret = 0; @@ -157,7 +161,7 @@ int32_t ais25ba_id_get(stmdev_ctx_t *ctx, ais25ba_id_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ais25ba_bus_mode_set(stmdev_ctx_t *ctx, +int32_t ais25ba_bus_mode_set(const stmdev_ctx_t *ctx, ais25ba_bus_mode_t *val) { ais25ba_tdm_ctrl_reg_t tdm_ctrl_reg; @@ -207,7 +211,7 @@ int32_t ais25ba_bus_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ais25ba_bus_mode_get(stmdev_ctx_t *ctx, +int32_t ais25ba_bus_mode_get(const stmdev_ctx_t *ctx, ais25ba_bus_mode_t *val) { ais25ba_tdm_ctrl_reg_t tdm_ctrl_reg; @@ -246,7 +250,7 @@ int32_t ais25ba_bus_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ais25ba_mode_set(stmdev_ctx_t *ctx, ais25ba_md_t *val) +int32_t ais25ba_mode_set(const stmdev_ctx_t *ctx, ais25ba_md_t *val) { ais25ba_axes_ctrl_reg_t axes_ctrl_reg; ais25ba_tdm_ctrl_reg_t tdm_ctrl_reg; @@ -294,7 +298,7 @@ int32_t ais25ba_mode_set(stmdev_ctx_t *ctx, ais25ba_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ais25ba_mode_get(stmdev_ctx_t *ctx, ais25ba_md_t *val) +int32_t ais25ba_mode_get(const stmdev_ctx_t *ctx, ais25ba_md_t *val) { ais25ba_axes_ctrl_reg_t axes_ctrl_reg; ais25ba_tdm_ctrl_reg_t tdm_ctrl_reg; @@ -387,7 +391,7 @@ int32_t ais25ba_data_get(uint16_t *tdm_stream, ais25ba_bus_mode_t *md, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ais25ba_self_test_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais25ba_self_test_set(const stmdev_ctx_t *ctx, uint8_t val) { ais25ba_test_reg_t test_reg; int32_t ret; @@ -412,7 +416,7 @@ int32_t ais25ba_self_test_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ais25ba_self_test_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais25ba_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais25ba_test_reg_t test_reg; int32_t ret; diff --git a/sensor/stmemsc/ais25ba_STdC/driver/ais25ba_reg.h b/sensor/stmemsc/ais25ba_STdC/driver/ais25ba_reg.h index 2c8a2e81..1d47d56d 100644 --- a/sensor/stmemsc/ais25ba_STdC/driver/ais25ba_reg.h +++ b/sensor/stmemsc/ais25ba_STdC/driver/ais25ba_reg.h @@ -304,10 +304,10 @@ typedef union * them with a custom implementation. */ -int32_t ais25ba_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t ais25ba_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t ais25ba_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t ais25ba_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -317,7 +317,7 @@ typedef struct { uint8_t id; } ais25ba_id_t; -int32_t ais25ba_id_get(stmdev_ctx_t *ctx, ais25ba_id_t *val); +int32_t ais25ba_id_get(const stmdev_ctx_t *ctx, ais25ba_id_t *val); typedef struct { @@ -330,9 +330,9 @@ typedef struct uint16_t cmax : 1; /* BCLK in a WCLK (unused if odr=_XL_HW_SEL) */ } tdm; } ais25ba_bus_mode_t; -int32_t ais25ba_bus_mode_set(stmdev_ctx_t *ctx, +int32_t ais25ba_bus_mode_set(const stmdev_ctx_t *ctx, ais25ba_bus_mode_t *val); -int32_t ais25ba_bus_mode_get(stmdev_ctx_t *ctx, +int32_t ais25ba_bus_mode_get(const stmdev_ctx_t *ctx, ais25ba_bus_mode_t *val); typedef struct @@ -349,8 +349,8 @@ typedef struct } odr; } xl; } ais25ba_md_t; -int32_t ais25ba_mode_set(stmdev_ctx_t *ctx, ais25ba_md_t *val); -int32_t ais25ba_mode_get(stmdev_ctx_t *ctx, ais25ba_md_t *val); +int32_t ais25ba_mode_set(const stmdev_ctx_t *ctx, ais25ba_md_t *val); +int32_t ais25ba_mode_get(const stmdev_ctx_t *ctx, ais25ba_md_t *val); typedef struct { @@ -363,8 +363,8 @@ typedef struct int32_t ais25ba_data_get(uint16_t *tdm_stream, ais25ba_bus_mode_t *md, ais25ba_data_t *data); -int32_t ais25ba_self_test_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais25ba_self_test_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais25ba_self_test_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais25ba_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val); /** * @} diff --git a/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.c b/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.c index cc6c4787..d4fa4f11 100644 --- a/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.c +++ b/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.c @@ -46,12 +46,14 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak ais2dw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak ais2dw12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +69,14 @@ int32_t __weak ais2dw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak ais2dw12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak ais2dw12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -157,7 +161,7 @@ float_t ais2dw12_from_lsb_to_celsius(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_power_mode_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_power_mode_set(const stmdev_ctx_t *ctx, ais2dw12_mode_t val) { ais2dw12_ctrl1_t ctrl1; @@ -184,7 +188,7 @@ int32_t ais2dw12_power_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_power_mode_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_power_mode_get(const stmdev_ctx_t *ctx, ais2dw12_mode_t *val) { ais2dw12_ctrl1_t ctrl1; @@ -242,7 +246,7 @@ int32_t ais2dw12_power_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_data_rate_set(stmdev_ctx_t *ctx, ais2dw12_odr_t val) +int32_t ais2dw12_data_rate_set(const stmdev_ctx_t *ctx, ais2dw12_odr_t val) { ais2dw12_ctrl1_t ctrl1; ais2dw12_ctrl3_t ctrl3; @@ -278,7 +282,7 @@ int32_t ais2dw12_data_rate_set(stmdev_ctx_t *ctx, ais2dw12_odr_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_data_rate_get(stmdev_ctx_t *ctx, ais2dw12_odr_t *val) +int32_t ais2dw12_data_rate_get(const stmdev_ctx_t *ctx, ais2dw12_odr_t *val) { ais2dw12_ctrl1_t ctrl1; ais2dw12_ctrl3_t ctrl3; @@ -337,7 +341,7 @@ int32_t ais2dw12_data_rate_get(stmdev_ctx_t *ctx, ais2dw12_odr_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2dw12_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2dw12_ctrl2_t reg; int32_t ret; @@ -361,7 +365,7 @@ int32_t ais2dw12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_block_data_update_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2dw12_ctrl2_t reg; @@ -381,7 +385,7 @@ int32_t ais2dw12_block_data_update_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_full_scale_set(stmdev_ctx_t *ctx, ais2dw12_fs_t val) +int32_t ais2dw12_full_scale_set(const stmdev_ctx_t *ctx, ais2dw12_fs_t val) { ais2dw12_ctrl6_t reg; int32_t ret; @@ -405,7 +409,7 @@ int32_t ais2dw12_full_scale_set(stmdev_ctx_t *ctx, ais2dw12_fs_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_full_scale_get(stmdev_ctx_t *ctx, ais2dw12_fs_t *val) +int32_t ais2dw12_full_scale_get(const stmdev_ctx_t *ctx, ais2dw12_fs_t *val) { ais2dw12_ctrl6_t reg; int32_t ret; @@ -438,7 +442,7 @@ int32_t ais2dw12_full_scale_get(stmdev_ctx_t *ctx, ais2dw12_fs_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_status_reg_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_status_reg_get(const stmdev_ctx_t *ctx, ais2dw12_status_t *val) { int32_t ret; @@ -456,7 +460,7 @@ int32_t ais2dw12_status_reg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2dw12_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2dw12_status_t reg; int32_t ret; @@ -475,7 +479,7 @@ int32_t ais2dw12_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_all_sources_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_all_sources_get(const stmdev_ctx_t *ctx, ais2dw12_all_sources_t *val) { uint8_t reg[5]; @@ -500,7 +504,7 @@ int32_t ais2dw12_all_sources_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ais2dw12_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -519,7 +523,7 @@ int32_t ais2dw12_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ais2dw12_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -538,7 +542,7 @@ int32_t ais2dw12_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ais2dw12_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -557,7 +561,7 @@ int32_t ais2dw12_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ais2dw12_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -576,7 +580,7 @@ int32_t ais2dw12_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ais2dw12_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -595,7 +599,7 @@ int32_t ais2dw12_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ais2dw12_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -614,7 +618,7 @@ int32_t ais2dw12_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_offset_weight_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_offset_weight_set(const stmdev_ctx_t *ctx, ais2dw12_usr_off_w_t val) { ais2dw12_ctrl7_t reg; @@ -640,7 +644,7 @@ int32_t ais2dw12_offset_weight_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_offset_weight_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_offset_weight_get(const stmdev_ctx_t *ctx, ais2dw12_usr_off_w_t *val) { ais2dw12_ctrl7_t reg; @@ -687,7 +691,7 @@ int32_t ais2dw12_offset_weight_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t ais2dw12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -708,7 +712,7 @@ int32_t ais2dw12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t ais2dw12_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -744,7 +748,7 @@ int32_t ais2dw12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ais2dw12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -762,7 +766,7 @@ int32_t ais2dw12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2dw12_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2dw12_ctrl2_t reg; int32_t ret; @@ -787,7 +791,7 @@ int32_t ais2dw12_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2dw12_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2dw12_ctrl2_t reg; int32_t ret; @@ -806,7 +810,7 @@ int32_t ais2dw12_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2dw12_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2dw12_ctrl2_t reg; int32_t ret; @@ -830,7 +834,7 @@ int32_t ais2dw12_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2dw12_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2dw12_ctrl2_t reg; int32_t ret; @@ -849,7 +853,7 @@ int32_t ais2dw12_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2dw12_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2dw12_ctrl2_t reg; int32_t ret; @@ -873,7 +877,7 @@ int32_t ais2dw12_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2dw12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2dw12_ctrl2_t reg; int32_t ret; @@ -892,7 +896,7 @@ int32_t ais2dw12_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_self_test_set(stmdev_ctx_t *ctx, ais2dw12_st_t val) +int32_t ais2dw12_self_test_set(const stmdev_ctx_t *ctx, ais2dw12_st_t val) { ais2dw12_ctrl3_t reg; int32_t ret; @@ -916,7 +920,7 @@ int32_t ais2dw12_self_test_set(stmdev_ctx_t *ctx, ais2dw12_st_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_self_test_get(stmdev_ctx_t *ctx, ais2dw12_st_t *val) +int32_t ais2dw12_self_test_get(const stmdev_ctx_t *ctx, ais2dw12_st_t *val) { ais2dw12_ctrl3_t reg; int32_t ret; @@ -953,7 +957,7 @@ int32_t ais2dw12_self_test_get(stmdev_ctx_t *ctx, ais2dw12_st_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_data_ready_mode_set(const stmdev_ctx_t *ctx, ais2dw12_drdy_pulsed_t val) { ais2dw12_ctrl7_t reg; @@ -978,7 +982,7 @@ int32_t ais2dw12_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_data_ready_mode_get(const stmdev_ctx_t *ctx, ais2dw12_drdy_pulsed_t *val) { ais2dw12_ctrl7_t reg; @@ -1025,7 +1029,7 @@ int32_t ais2dw12_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_filter_path_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_filter_path_set(const stmdev_ctx_t *ctx, ais2dw12_fds_t val) { ais2dw12_ctrl6_t ctrl6; @@ -1062,7 +1066,7 @@ int32_t ais2dw12_filter_path_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_filter_path_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_filter_path_get(const stmdev_ctx_t *ctx, ais2dw12_fds_t *val) { ais2dw12_ctrl6_t ctrl6; @@ -1107,7 +1111,7 @@ int32_t ais2dw12_filter_path_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_filter_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_filter_bandwidth_set(const stmdev_ctx_t *ctx, ais2dw12_bw_filt_t val) { ais2dw12_ctrl6_t reg; @@ -1133,7 +1137,7 @@ int32_t ais2dw12_filter_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_filter_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_filter_bandwidth_get(const stmdev_ctx_t *ctx, ais2dw12_bw_filt_t *val) { ais2dw12_ctrl6_t reg; @@ -1175,7 +1179,7 @@ int32_t ais2dw12_filter_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2dw12_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2dw12_ctrl7_t reg; int32_t ret; @@ -1199,7 +1203,7 @@ int32_t ais2dw12_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2dw12_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2dw12_ctrl7_t reg; int32_t ret; @@ -1231,7 +1235,7 @@ int32_t ais2dw12_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_spi_mode_set(stmdev_ctx_t *ctx, ais2dw12_sim_t val) +int32_t ais2dw12_spi_mode_set(const stmdev_ctx_t *ctx, ais2dw12_sim_t val) { ais2dw12_ctrl2_t reg; int32_t ret; @@ -1255,7 +1259,7 @@ int32_t ais2dw12_spi_mode_set(stmdev_ctx_t *ctx, ais2dw12_sim_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_spi_mode_get(stmdev_ctx_t *ctx, ais2dw12_sim_t *val) +int32_t ais2dw12_spi_mode_get(const stmdev_ctx_t *ctx, ais2dw12_sim_t *val) { ais2dw12_ctrl2_t reg; int32_t ret; @@ -1289,7 +1293,7 @@ int32_t ais2dw12_spi_mode_get(stmdev_ctx_t *ctx, ais2dw12_sim_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_i2c_interface_set(const stmdev_ctx_t *ctx, ais2dw12_i2c_disable_t val) { ais2dw12_ctrl2_t reg; @@ -1314,7 +1318,7 @@ int32_t ais2dw12_i2c_interface_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_i2c_interface_get(const stmdev_ctx_t *ctx, ais2dw12_i2c_disable_t *val) { ais2dw12_ctrl2_t reg; @@ -1348,7 +1352,7 @@ int32_t ais2dw12_i2c_interface_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_cs_mode_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_cs_mode_set(const stmdev_ctx_t *ctx, ais2dw12_cs_pu_disc_t val) { ais2dw12_ctrl2_t reg; @@ -1373,7 +1377,7 @@ int32_t ais2dw12_cs_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_cs_mode_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_cs_mode_get(const stmdev_ctx_t *ctx, ais2dw12_cs_pu_disc_t *val) { ais2dw12_ctrl2_t reg; @@ -1419,7 +1423,7 @@ int32_t ais2dw12_cs_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_pin_polarity_set(const stmdev_ctx_t *ctx, ais2dw12_h_lactive_t val) { ais2dw12_ctrl3_t reg; @@ -1444,7 +1448,7 @@ int32_t ais2dw12_pin_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_pin_polarity_get(const stmdev_ctx_t *ctx, ais2dw12_h_lactive_t *val) { ais2dw12_ctrl3_t reg; @@ -1478,7 +1482,7 @@ int32_t ais2dw12_pin_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_int_notification_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_int_notification_set(const stmdev_ctx_t *ctx, ais2dw12_lir_t val) { ais2dw12_ctrl3_t reg; @@ -1503,7 +1507,7 @@ int32_t ais2dw12_int_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_int_notification_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_int_notification_get(const stmdev_ctx_t *ctx, ais2dw12_lir_t *val) { ais2dw12_ctrl3_t reg; @@ -1537,7 +1541,7 @@ int32_t ais2dw12_int_notification_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_pin_mode_set(stmdev_ctx_t *ctx, ais2dw12_pp_od_t val) +int32_t ais2dw12_pin_mode_set(const stmdev_ctx_t *ctx, ais2dw12_pp_od_t val) { ais2dw12_ctrl3_t reg; int32_t ret; @@ -1561,7 +1565,7 @@ int32_t ais2dw12_pin_mode_set(stmdev_ctx_t *ctx, ais2dw12_pp_od_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_pin_mode_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_pin_mode_get(const stmdev_ctx_t *ctx, ais2dw12_pp_od_t *val) { ais2dw12_ctrl3_t reg; @@ -1595,7 +1599,7 @@ int32_t ais2dw12_pin_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_pin_int1_route_set(const stmdev_ctx_t *ctx, ais2dw12_ctrl4_int1_t *val) { ais2dw12_ctrl5_int2_t ctrl5_int2_pad_ctrl; @@ -1646,7 +1650,7 @@ int32_t ais2dw12_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_pin_int1_route_get(const stmdev_ctx_t *ctx, ais2dw12_ctrl4_int1_t *val) { int32_t ret; @@ -1665,7 +1669,7 @@ int32_t ais2dw12_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_pin_int2_route_set(const stmdev_ctx_t *ctx, ais2dw12_ctrl5_int2_t *val) { ais2dw12_ctrl4_int1_t ctrl4_int1_pad_ctrl; @@ -1715,7 +1719,7 @@ int32_t ais2dw12_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_pin_int2_route_get(const stmdev_ctx_t *ctx, ais2dw12_ctrl5_int2_t *val) { int32_t ret; @@ -1733,7 +1737,7 @@ int32_t ais2dw12_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2dw12_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2dw12_ctrl7_t reg; int32_t ret; @@ -1757,7 +1761,7 @@ int32_t ais2dw12_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2dw12_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2dw12_ctrl7_t reg; int32_t ret; @@ -1789,7 +1793,7 @@ int32_t ais2dw12_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2dw12_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2dw12_wake_up_ths_t reg; int32_t ret; @@ -1813,7 +1817,7 @@ int32_t ais2dw12_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2dw12_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2dw12_wake_up_ths_t reg; int32_t ret; @@ -1832,7 +1836,7 @@ int32_t ais2dw12_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2dw12_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2dw12_wake_up_dur_t reg; int32_t ret; @@ -1856,7 +1860,7 @@ int32_t ais2dw12_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2dw12_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2dw12_wake_up_dur_t reg; int32_t ret; @@ -1875,7 +1879,7 @@ int32_t ais2dw12_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_wkup_feed_data_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_wkup_feed_data_set(const stmdev_ctx_t *ctx, ais2dw12_usr_off_on_wu_t val) { ais2dw12_ctrl7_t reg; @@ -1900,7 +1904,7 @@ int32_t ais2dw12_wkup_feed_data_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_wkup_feed_data_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_wkup_feed_data_get(const stmdev_ctx_t *ctx, ais2dw12_usr_off_on_wu_t *val) { ais2dw12_ctrl7_t reg; @@ -1949,7 +1953,7 @@ int32_t ais2dw12_wkup_feed_data_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_act_mode_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_act_mode_set(const stmdev_ctx_t *ctx, ais2dw12_sleep_on_t val) { ais2dw12_wake_up_ths_t wake_up_ths; @@ -1991,7 +1995,7 @@ int32_t ais2dw12_act_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_act_mode_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_act_mode_get(const stmdev_ctx_t *ctx, ais2dw12_sleep_on_t *val) { ais2dw12_wake_up_ths_t wake_up_ths; @@ -2037,7 +2041,7 @@ int32_t ais2dw12_act_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2dw12_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2dw12_wake_up_dur_t reg; int32_t ret; @@ -2061,7 +2065,7 @@ int32_t ais2dw12_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2dw12_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2dw12_wake_up_dur_t reg; int32_t ret; @@ -2093,7 +2097,7 @@ int32_t ais2dw12_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2dw12_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2dw12_sixd_ths_t reg; int32_t ret; @@ -2117,7 +2121,7 @@ int32_t ais2dw12_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2dw12_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2dw12_sixd_ths_t reg; int32_t ret; @@ -2136,7 +2140,7 @@ int32_t ais2dw12_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2dw12_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2dw12_sixd_ths_t reg; int32_t ret; @@ -2160,7 +2164,7 @@ int32_t ais2dw12_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2dw12_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2dw12_sixd_ths_t reg; int32_t ret; @@ -2179,7 +2183,7 @@ int32_t ais2dw12_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_6d_src_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_6d_src_get(const stmdev_ctx_t *ctx, ais2dw12_sixd_src_t *val) { int32_t ret; @@ -2196,7 +2200,7 @@ int32_t ais2dw12_6d_src_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_6d_feed_data_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_6d_feed_data_set(const stmdev_ctx_t *ctx, ais2dw12_lpass_on6d_t val) { ais2dw12_ctrl7_t reg; @@ -2221,7 +2225,7 @@ int32_t ais2dw12_6d_feed_data_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_6d_feed_data_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_6d_feed_data_get(const stmdev_ctx_t *ctx, ais2dw12_lpass_on6d_t *val) { ais2dw12_ctrl7_t reg; @@ -2269,7 +2273,7 @@ int32_t ais2dw12_6d_feed_data_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2dw12_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2dw12_wake_up_dur_t wake_up_dur; ais2dw12_free_fall_t free_fall; @@ -2310,7 +2314,7 @@ int32_t ais2dw12_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2dw12_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2dw12_wake_up_dur_t wake_up_dur; ais2dw12_free_fall_t free_fall; @@ -2337,7 +2341,7 @@ int32_t ais2dw12_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_ff_threshold_set(const stmdev_ctx_t *ctx, ais2dw12_ff_ths_t val) { ais2dw12_free_fall_t reg; @@ -2362,7 +2366,7 @@ int32_t ais2dw12_ff_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_ff_threshold_get(const stmdev_ctx_t *ctx, ais2dw12_ff_ths_t *val) { ais2dw12_free_fall_t reg; @@ -2432,7 +2436,7 @@ int32_t ais2dw12_ff_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2dw12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2dw12_fifo_ctrl_t reg; int32_t ret; @@ -2456,7 +2460,7 @@ int32_t ais2dw12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2dw12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2dw12_fifo_ctrl_t reg; int32_t ret; @@ -2475,7 +2479,7 @@ int32_t ais2dw12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_fifo_mode_set(const stmdev_ctx_t *ctx, ais2dw12_fmode_t val) { ais2dw12_fifo_ctrl_t reg; @@ -2500,7 +2504,7 @@ int32_t ais2dw12_fifo_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_fifo_mode_get(const stmdev_ctx_t *ctx, ais2dw12_fmode_t *val) { ais2dw12_fifo_ctrl_t reg; @@ -2546,7 +2550,7 @@ int32_t ais2dw12_fifo_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2dw12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2dw12_fifo_samples_t reg; int32_t ret; @@ -2564,7 +2568,7 @@ int32_t ais2dw12_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2dw12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2dw12_fifo_samples_t reg; int32_t ret; @@ -2582,7 +2586,7 @@ int32_t ais2dw12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2dw12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2dw12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2dw12_fifo_samples_t reg; int32_t ret; diff --git a/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.h b/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.h index df17ccc5..a974be82 100644 --- a/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.h +++ b/sensor/stmemsc/ais2dw12_STdC/driver/ais2dw12_reg.h @@ -592,10 +592,10 @@ typedef union * them with a custom implementation. */ -int32_t ais2dw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t ais2dw12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t ais2dw12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t ais2dw12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -617,9 +617,9 @@ typedef enum AIS2DW12_SINGLE_PWR_MD_2 = 0x09, AIS2DW12_SINGLE_PWR_MD_12bit = 0x08, } ais2dw12_mode_t; -int32_t ais2dw12_power_mode_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_power_mode_set(const stmdev_ctx_t *ctx, ais2dw12_mode_t val); -int32_t ais2dw12_power_mode_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_power_mode_get(const stmdev_ctx_t *ctx, ais2dw12_mode_t *val); typedef enum @@ -633,13 +633,13 @@ typedef enum AIS2DW12_XL_SET_SW_TRIG = 0x12, /* Use this only in SINGLE mode */ AIS2DW12_XL_SET_PIN_TRIG = 0x22, /* Use this only in SINGLE mode */ } ais2dw12_odr_t; -int32_t ais2dw12_data_rate_set(stmdev_ctx_t *ctx, ais2dw12_odr_t val); -int32_t ais2dw12_data_rate_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_data_rate_set(const stmdev_ctx_t *ctx, ais2dw12_odr_t val); +int32_t ais2dw12_data_rate_get(const stmdev_ctx_t *ctx, ais2dw12_odr_t *val); -int32_t ais2dw12_block_data_update_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2dw12_block_data_update_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -647,14 +647,14 @@ typedef enum AIS2DW12_2g = 0, AIS2DW12_4g = 1, } ais2dw12_fs_t; -int32_t ais2dw12_full_scale_set(stmdev_ctx_t *ctx, ais2dw12_fs_t val); -int32_t ais2dw12_full_scale_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_full_scale_set(const stmdev_ctx_t *ctx, ais2dw12_fs_t val); +int32_t ais2dw12_full_scale_get(const stmdev_ctx_t *ctx, ais2dw12_fs_t *val); -int32_t ais2dw12_status_reg_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_status_reg_get(const stmdev_ctx_t *ctx, ais2dw12_status_t *val); -int32_t ais2dw12_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2dw12_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -663,43 +663,43 @@ typedef struct ais2dw12_sixd_src_t sixd_src; ais2dw12_all_int_src_t all_int_src; } ais2dw12_all_sources_t; -int32_t ais2dw12_all_sources_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_all_sources_get(const stmdev_ctx_t *ctx, ais2dw12_all_sources_t *val); -int32_t ais2dw12_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ais2dw12_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t ais2dw12_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t ais2dw12_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ais2dw12_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ais2dw12_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t ais2dw12_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t ais2dw12_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ais2dw12_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ais2dw12_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t ais2dw12_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t ais2dw12_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff); typedef enum { AIS2DW12_LSb_977ug = 0, AIS2DW12_LSb_15mg6 = 1, } ais2dw12_usr_off_w_t; -int32_t ais2dw12_offset_weight_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_offset_weight_set(const stmdev_ctx_t *ctx, ais2dw12_usr_off_w_t val); -int32_t ais2dw12_offset_weight_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_offset_weight_get(const stmdev_ctx_t *ctx, ais2dw12_usr_off_w_t *val); -int32_t ais2dw12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t ais2dw12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t ais2dw12_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t ais2dw12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t ais2dw12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ais2dw12_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2dw12_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2dw12_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2dw12_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais2dw12_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2dw12_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2dw12_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2dw12_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais2dw12_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2dw12_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2dw12_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2dw12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -707,17 +707,17 @@ typedef enum AIS2DW12_XL_ST_POSITIVE = 1, AIS2DW12_XL_ST_NEGATIVE = 2, } ais2dw12_st_t; -int32_t ais2dw12_self_test_set(stmdev_ctx_t *ctx, ais2dw12_st_t val); -int32_t ais2dw12_self_test_get(stmdev_ctx_t *ctx, ais2dw12_st_t *val); +int32_t ais2dw12_self_test_set(const stmdev_ctx_t *ctx, ais2dw12_st_t val); +int32_t ais2dw12_self_test_get(const stmdev_ctx_t *ctx, ais2dw12_st_t *val); typedef enum { AIS2DW12_DRDY_LATCHED = 0, AIS2DW12_DRDY_PULSED = 1, } ais2dw12_drdy_pulsed_t; -int32_t ais2dw12_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_data_ready_mode_set(const stmdev_ctx_t *ctx, ais2dw12_drdy_pulsed_t val); -int32_t ais2dw12_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_data_ready_mode_get(const stmdev_ctx_t *ctx, ais2dw12_drdy_pulsed_t *val); typedef enum @@ -726,9 +726,9 @@ typedef enum AIS2DW12_USER_OFFSET_ON_OUT = 0x01, AIS2DW12_HIGH_PASS_ON_OUT = 0x10, } ais2dw12_fds_t; -int32_t ais2dw12_filter_path_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_filter_path_set(const stmdev_ctx_t *ctx, ais2dw12_fds_t val); -int32_t ais2dw12_filter_path_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_filter_path_get(const stmdev_ctx_t *ctx, ais2dw12_fds_t *val); typedef enum @@ -738,30 +738,30 @@ typedef enum AIS2DW12_ODR_DIV_10 = 2, AIS2DW12_ODR_DIV_20 = 3, } ais2dw12_bw_filt_t; -int32_t ais2dw12_filter_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_filter_bandwidth_set(const stmdev_ctx_t *ctx, ais2dw12_bw_filt_t val); -int32_t ais2dw12_filter_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_filter_bandwidth_get(const stmdev_ctx_t *ctx, ais2dw12_bw_filt_t *val); -int32_t ais2dw12_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2dw12_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2dw12_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2dw12_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { AIS2DW12_SPI_4_WIRE = 0, AIS2DW12_SPI_3_WIRE = 1, } ais2dw12_sim_t; -int32_t ais2dw12_spi_mode_set(stmdev_ctx_t *ctx, ais2dw12_sim_t val); -int32_t ais2dw12_spi_mode_get(stmdev_ctx_t *ctx, ais2dw12_sim_t *val); +int32_t ais2dw12_spi_mode_set(const stmdev_ctx_t *ctx, ais2dw12_sim_t val); +int32_t ais2dw12_spi_mode_get(const stmdev_ctx_t *ctx, ais2dw12_sim_t *val); typedef enum { AIS2DW12_I2C_ENABLE = 0, AIS2DW12_I2C_DISABLE = 1, } ais2dw12_i2c_disable_t; -int32_t ais2dw12_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_i2c_interface_set(const stmdev_ctx_t *ctx, ais2dw12_i2c_disable_t val); -int32_t ais2dw12_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_i2c_interface_get(const stmdev_ctx_t *ctx, ais2dw12_i2c_disable_t *val); typedef enum @@ -769,9 +769,9 @@ typedef enum AIS2DW12_PULL_UP_CONNECT = 0, AIS2DW12_PULL_UP_DISCONNECT = 1, } ais2dw12_cs_pu_disc_t; -int32_t ais2dw12_cs_mode_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_cs_mode_set(const stmdev_ctx_t *ctx, ais2dw12_cs_pu_disc_t val); -int32_t ais2dw12_cs_mode_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_cs_mode_get(const stmdev_ctx_t *ctx, ais2dw12_cs_pu_disc_t *val); typedef enum @@ -779,9 +779,9 @@ typedef enum AIS2DW12_ACTIVE_HIGH = 0, AIS2DW12_ACTIVE_LOW = 1, } ais2dw12_h_lactive_t; -int32_t ais2dw12_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_pin_polarity_set(const stmdev_ctx_t *ctx, ais2dw12_h_lactive_t val); -int32_t ais2dw12_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_pin_polarity_get(const stmdev_ctx_t *ctx, ais2dw12_h_lactive_t *val); typedef enum @@ -789,9 +789,9 @@ typedef enum AIS2DW12_INT_PULSED = 0, AIS2DW12_INT_LATCHED = 1, } ais2dw12_lir_t; -int32_t ais2dw12_int_notification_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_int_notification_set(const stmdev_ctx_t *ctx, ais2dw12_lir_t val); -int32_t ais2dw12_int_notification_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_int_notification_get(const stmdev_ctx_t *ctx, ais2dw12_lir_t *val); typedef enum @@ -799,38 +799,38 @@ typedef enum AIS2DW12_PUSH_PULL = 0, AIS2DW12_OPEN_DRAIN = 1, } ais2dw12_pp_od_t; -int32_t ais2dw12_pin_mode_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_pin_mode_set(const stmdev_ctx_t *ctx, ais2dw12_pp_od_t val); -int32_t ais2dw12_pin_mode_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_pin_mode_get(const stmdev_ctx_t *ctx, ais2dw12_pp_od_t *val); -int32_t ais2dw12_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_pin_int1_route_set(const stmdev_ctx_t *ctx, ais2dw12_ctrl4_int1_t *val); -int32_t ais2dw12_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_pin_int1_route_get(const stmdev_ctx_t *ctx, ais2dw12_ctrl4_int1_t *val); -int32_t ais2dw12_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_pin_int2_route_set(const stmdev_ctx_t *ctx, ais2dw12_ctrl5_int2_t *val); -int32_t ais2dw12_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_pin_int2_route_get(const stmdev_ctx_t *ctx, ais2dw12_ctrl5_int2_t *val); -int32_t ais2dw12_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2dw12_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2dw12_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2dw12_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais2dw12_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2dw12_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2dw12_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2dw12_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais2dw12_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2dw12_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2dw12_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2dw12_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { AIS2DW12_HP_FEED = 0, AIS2DW12_USER_OFFSET_FEED = 1, } ais2dw12_usr_off_on_wu_t; -int32_t ais2dw12_wkup_feed_data_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_wkup_feed_data_set(const stmdev_ctx_t *ctx, ais2dw12_usr_off_on_wu_t val); -int32_t ais2dw12_wkup_feed_data_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_wkup_feed_data_get(const stmdev_ctx_t *ctx, ais2dw12_usr_off_on_wu_t *val); typedef enum @@ -839,21 +839,21 @@ typedef enum AIS2DW12_DETECT_ACT_INACT = 1, AIS2DW12_DETECT_STAT_MOTION = 3, } ais2dw12_sleep_on_t; -int32_t ais2dw12_act_mode_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_act_mode_set(const stmdev_ctx_t *ctx, ais2dw12_sleep_on_t val); -int32_t ais2dw12_act_mode_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_act_mode_get(const stmdev_ctx_t *ctx, ais2dw12_sleep_on_t *val); -int32_t ais2dw12_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2dw12_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2dw12_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2dw12_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais2dw12_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2dw12_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2dw12_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2dw12_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais2dw12_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2dw12_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2dw12_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2dw12_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais2dw12_6d_src_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_6d_src_get(const stmdev_ctx_t *ctx, ais2dw12_sixd_src_t *val); typedef enum @@ -861,13 +861,13 @@ typedef enum AIS2DW12_ODR_DIV_2_FEED = 0, AIS2DW12_LPF2_FEED = 1, } ais2dw12_lpass_on6d_t; -int32_t ais2dw12_6d_feed_data_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_6d_feed_data_set(const stmdev_ctx_t *ctx, ais2dw12_lpass_on6d_t val); -int32_t ais2dw12_6d_feed_data_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_6d_feed_data_get(const stmdev_ctx_t *ctx, ais2dw12_lpass_on6d_t *val); -int32_t ais2dw12_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2dw12_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2dw12_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2dw12_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -880,13 +880,13 @@ typedef enum AIS2DW12_FF_TSH_15LSb_FS2g = 6, AIS2DW12_FF_TSH_16LSb_FS2g = 7, } ais2dw12_ff_ths_t; -int32_t ais2dw12_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_ff_threshold_set(const stmdev_ctx_t *ctx, ais2dw12_ff_ths_t val); -int32_t ais2dw12_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_ff_threshold_get(const stmdev_ctx_t *ctx, ais2dw12_ff_ths_t *val); -int32_t ais2dw12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2dw12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2dw12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2dw12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -896,16 +896,16 @@ typedef enum AIS2DW12_BYPASS_TO_STREAM_MODE = 4, AIS2DW12_STREAM_MODE = 6, } ais2dw12_fmode_t; -int32_t ais2dw12_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t ais2dw12_fifo_mode_set(const stmdev_ctx_t *ctx, ais2dw12_fmode_t val); -int32_t ais2dw12_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t ais2dw12_fifo_mode_get(const stmdev_ctx_t *ctx, ais2dw12_fmode_t *val); -int32_t ais2dw12_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2dw12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais2dw12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2dw12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais2dw12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2dw12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); /** * @} diff --git a/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.c b/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.c index 8fa9ebee..b22b3da2 100644 --- a/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.c +++ b/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.c @@ -46,11 +46,13 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak ais2ih_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, +int32_t __weak ais2ih_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -66,12 +68,14 @@ int32_t __weak ais2ih_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak ais2ih_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak ais2ih_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -156,7 +160,7 @@ float_t ais2ih_from_lsb_to_celsius(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_power_mode_set(stmdev_ctx_t *ctx, ais2ih_mode_t val) +int32_t ais2ih_power_mode_set(const stmdev_ctx_t *ctx, ais2ih_mode_t val) { ais2ih_ctrl1_t ctrl1; ais2ih_ctrl6_t ctrl6; @@ -194,7 +198,7 @@ int32_t ais2ih_power_mode_set(stmdev_ctx_t *ctx, ais2ih_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_power_mode_get(stmdev_ctx_t *ctx, ais2ih_mode_t *val) +int32_t ais2ih_power_mode_get(const stmdev_ctx_t *ctx, ais2ih_mode_t *val) { ais2ih_ctrl1_t ctrl1; ais2ih_ctrl6_t ctrl6; @@ -298,7 +302,7 @@ int32_t ais2ih_power_mode_get(stmdev_ctx_t *ctx, ais2ih_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_data_rate_set(stmdev_ctx_t *ctx, ais2ih_odr_t val) +int32_t ais2ih_data_rate_set(const stmdev_ctx_t *ctx, ais2ih_odr_t val) { ais2ih_ctrl1_t ctrl1; ais2ih_ctrl3_t ctrl3; @@ -334,7 +338,7 @@ int32_t ais2ih_data_rate_set(stmdev_ctx_t *ctx, ais2ih_odr_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_data_rate_get(stmdev_ctx_t *ctx, ais2ih_odr_t *val) +int32_t ais2ih_data_rate_get(const stmdev_ctx_t *ctx, ais2ih_odr_t *val) { ais2ih_ctrl1_t ctrl1; ais2ih_ctrl3_t ctrl3; @@ -413,7 +417,7 @@ int32_t ais2ih_data_rate_get(stmdev_ctx_t *ctx, ais2ih_odr_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2ih_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2ih_ctrl2_t reg; int32_t ret; @@ -437,7 +441,7 @@ int32_t ais2ih_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2ih_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2ih_ctrl2_t reg; int32_t ret; @@ -456,7 +460,7 @@ int32_t ais2ih_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_full_scale_set(stmdev_ctx_t *ctx, ais2ih_fs_t val) +int32_t ais2ih_full_scale_set(const stmdev_ctx_t *ctx, ais2ih_fs_t val) { ais2ih_ctrl6_t reg; int32_t ret; @@ -480,7 +484,7 @@ int32_t ais2ih_full_scale_set(stmdev_ctx_t *ctx, ais2ih_fs_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_full_scale_get(stmdev_ctx_t *ctx, ais2ih_fs_t *val) +int32_t ais2ih_full_scale_get(const stmdev_ctx_t *ctx, ais2ih_fs_t *val) { ais2ih_ctrl6_t reg; int32_t ret; @@ -521,7 +525,7 @@ int32_t ais2ih_full_scale_get(stmdev_ctx_t *ctx, ais2ih_fs_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_status_reg_get(stmdev_ctx_t *ctx, ais2ih_status_t *val) +int32_t ais2ih_status_reg_get(const stmdev_ctx_t *ctx, ais2ih_status_t *val) { int32_t ret; @@ -538,7 +542,7 @@ int32_t ais2ih_status_reg_get(stmdev_ctx_t *ctx, ais2ih_status_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2ih_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2ih_status_t reg; int32_t ret; @@ -557,7 +561,7 @@ int32_t ais2ih_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_all_sources_get(stmdev_ctx_t *ctx, +int32_t ais2ih_all_sources_get(const stmdev_ctx_t *ctx, ais2ih_all_sources_t *val) { int32_t ret; @@ -577,7 +581,7 @@ int32_t ais2ih_all_sources_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ais2ih_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -596,7 +600,7 @@ int32_t ais2ih_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ais2ih_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -615,7 +619,7 @@ int32_t ais2ih_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ais2ih_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -634,7 +638,7 @@ int32_t ais2ih_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ais2ih_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -653,7 +657,7 @@ int32_t ais2ih_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ais2ih_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -672,7 +676,7 @@ int32_t ais2ih_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ais2ih_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -691,7 +695,7 @@ int32_t ais2ih_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_offset_weight_set(stmdev_ctx_t *ctx, +int32_t ais2ih_offset_weight_set(const stmdev_ctx_t *ctx, ais2ih_usr_off_w_t val) { ais2ih_ctrl_reg7_t reg; @@ -717,7 +721,7 @@ int32_t ais2ih_offset_weight_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_offset_weight_get(stmdev_ctx_t *ctx, +int32_t ais2ih_offset_weight_get(const stmdev_ctx_t *ctx, ais2ih_usr_off_w_t *val) { ais2ih_ctrl_reg7_t reg; @@ -764,7 +768,7 @@ int32_t ais2ih_offset_weight_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t ais2ih_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -785,7 +789,7 @@ int32_t ais2ih_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t ais2ih_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -821,7 +825,7 @@ int32_t ais2ih_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ais2ih_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -839,7 +843,7 @@ int32_t ais2ih_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2ih_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2ih_ctrl2_t reg; int32_t ret; @@ -864,7 +868,7 @@ int32_t ais2ih_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2ih_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2ih_ctrl2_t reg; int32_t ret; @@ -883,7 +887,7 @@ int32_t ais2ih_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2ih_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2ih_ctrl2_t reg; int32_t ret; @@ -907,7 +911,7 @@ int32_t ais2ih_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2ih_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2ih_ctrl2_t reg; int32_t ret; @@ -926,7 +930,7 @@ int32_t ais2ih_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2ih_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2ih_ctrl2_t reg; int32_t ret; @@ -950,7 +954,7 @@ int32_t ais2ih_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2ih_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2ih_ctrl2_t reg; int32_t ret; @@ -969,7 +973,7 @@ int32_t ais2ih_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_self_test_set(stmdev_ctx_t *ctx, ais2ih_st_t val) +int32_t ais2ih_self_test_set(const stmdev_ctx_t *ctx, ais2ih_st_t val) { ais2ih_ctrl3_t reg; int32_t ret; @@ -993,7 +997,7 @@ int32_t ais2ih_self_test_set(stmdev_ctx_t *ctx, ais2ih_st_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_self_test_get(stmdev_ctx_t *ctx, ais2ih_st_t *val) +int32_t ais2ih_self_test_get(const stmdev_ctx_t *ctx, ais2ih_st_t *val) { ais2ih_ctrl3_t reg; int32_t ret; @@ -1030,7 +1034,7 @@ int32_t ais2ih_self_test_get(stmdev_ctx_t *ctx, ais2ih_st_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t ais2ih_data_ready_mode_set(const stmdev_ctx_t *ctx, ais2ih_drdy_pulsed_t val) { ais2ih_ctrl_reg7_t reg; @@ -1055,7 +1059,7 @@ int32_t ais2ih_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t ais2ih_data_ready_mode_get(const stmdev_ctx_t *ctx, ais2ih_drdy_pulsed_t *val) { ais2ih_ctrl_reg7_t reg; @@ -1102,7 +1106,7 @@ int32_t ais2ih_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_filter_path_set(stmdev_ctx_t *ctx, ais2ih_fds_t val) +int32_t ais2ih_filter_path_set(const stmdev_ctx_t *ctx, ais2ih_fds_t val) { ais2ih_ctrl6_t ctrl6; ais2ih_ctrl_reg7_t ctrl_reg7; @@ -1138,7 +1142,7 @@ int32_t ais2ih_filter_path_set(stmdev_ctx_t *ctx, ais2ih_fds_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_filter_path_get(stmdev_ctx_t *ctx, ais2ih_fds_t *val) +int32_t ais2ih_filter_path_get(const stmdev_ctx_t *ctx, ais2ih_fds_t *val) { ais2ih_ctrl6_t ctrl6; ais2ih_ctrl_reg7_t ctrl_reg7; @@ -1182,7 +1186,7 @@ int32_t ais2ih_filter_path_get(stmdev_ctx_t *ctx, ais2ih_fds_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_filter_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ais2ih_filter_bandwidth_set(const stmdev_ctx_t *ctx, ais2ih_bw_filt_t val) { ais2ih_ctrl6_t reg; @@ -1208,7 +1212,7 @@ int32_t ais2ih_filter_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_filter_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ais2ih_filter_bandwidth_get(const stmdev_ctx_t *ctx, ais2ih_bw_filt_t *val) { ais2ih_ctrl6_t reg; @@ -1250,7 +1254,7 @@ int32_t ais2ih_filter_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2ih_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2ih_ctrl_reg7_t reg; int32_t ret; @@ -1274,7 +1278,7 @@ int32_t ais2ih_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2ih_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2ih_ctrl_reg7_t reg; int32_t ret; @@ -1306,7 +1310,7 @@ int32_t ais2ih_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_spi_mode_set(stmdev_ctx_t *ctx, ais2ih_sim_t val) +int32_t ais2ih_spi_mode_set(const stmdev_ctx_t *ctx, ais2ih_sim_t val) { ais2ih_ctrl2_t reg; int32_t ret; @@ -1330,7 +1334,7 @@ int32_t ais2ih_spi_mode_set(stmdev_ctx_t *ctx, ais2ih_sim_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_spi_mode_get(stmdev_ctx_t *ctx, ais2ih_sim_t *val) +int32_t ais2ih_spi_mode_get(const stmdev_ctx_t *ctx, ais2ih_sim_t *val) { ais2ih_ctrl2_t reg; int32_t ret; @@ -1364,7 +1368,7 @@ int32_t ais2ih_spi_mode_get(stmdev_ctx_t *ctx, ais2ih_sim_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t ais2ih_i2c_interface_set(const stmdev_ctx_t *ctx, ais2ih_i2c_disable_t val) { ais2ih_ctrl2_t reg; @@ -1389,7 +1393,7 @@ int32_t ais2ih_i2c_interface_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t ais2ih_i2c_interface_get(const stmdev_ctx_t *ctx, ais2ih_i2c_disable_t *val) { ais2ih_ctrl2_t reg; @@ -1423,7 +1427,7 @@ int32_t ais2ih_i2c_interface_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_cs_mode_set(stmdev_ctx_t *ctx, ais2ih_cs_pu_disc_t val) +int32_t ais2ih_cs_mode_set(const stmdev_ctx_t *ctx, ais2ih_cs_pu_disc_t val) { ais2ih_ctrl2_t reg; int32_t ret; @@ -1447,7 +1451,7 @@ int32_t ais2ih_cs_mode_set(stmdev_ctx_t *ctx, ais2ih_cs_pu_disc_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_cs_mode_get(stmdev_ctx_t *ctx, +int32_t ais2ih_cs_mode_get(const stmdev_ctx_t *ctx, ais2ih_cs_pu_disc_t *val) { ais2ih_ctrl2_t reg; @@ -1493,7 +1497,7 @@ int32_t ais2ih_cs_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t ais2ih_pin_polarity_set(const stmdev_ctx_t *ctx, ais2ih_h_lactive_t val) { ais2ih_ctrl3_t reg; @@ -1518,7 +1522,7 @@ int32_t ais2ih_pin_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t ais2ih_pin_polarity_get(const stmdev_ctx_t *ctx, ais2ih_h_lactive_t *val) { ais2ih_ctrl3_t reg; @@ -1552,7 +1556,7 @@ int32_t ais2ih_pin_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_int_notification_set(stmdev_ctx_t *ctx, +int32_t ais2ih_int_notification_set(const stmdev_ctx_t *ctx, ais2ih_lir_t val) { ais2ih_ctrl3_t reg; @@ -1577,7 +1581,7 @@ int32_t ais2ih_int_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_int_notification_get(stmdev_ctx_t *ctx, +int32_t ais2ih_int_notification_get(const stmdev_ctx_t *ctx, ais2ih_lir_t *val) { ais2ih_ctrl3_t reg; @@ -1611,7 +1615,7 @@ int32_t ais2ih_int_notification_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_pin_mode_set(stmdev_ctx_t *ctx, ais2ih_pp_od_t val) +int32_t ais2ih_pin_mode_set(const stmdev_ctx_t *ctx, ais2ih_pp_od_t val) { ais2ih_ctrl3_t reg; int32_t ret; @@ -1635,7 +1639,7 @@ int32_t ais2ih_pin_mode_set(stmdev_ctx_t *ctx, ais2ih_pp_od_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_pin_mode_get(stmdev_ctx_t *ctx, ais2ih_pp_od_t *val) +int32_t ais2ih_pin_mode_get(const stmdev_ctx_t *ctx, ais2ih_pp_od_t *val) { ais2ih_ctrl3_t reg; int32_t ret; @@ -1668,7 +1672,7 @@ int32_t ais2ih_pin_mode_get(stmdev_ctx_t *ctx, ais2ih_pp_od_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t ais2ih_pin_int1_route_set(const stmdev_ctx_t *ctx, ais2ih_ctrl4_int1_pad_ctrl_t *val) { ais2ih_ctrl5_int2_pad_ctrl_t ctrl5_int2_pad_ctrl; @@ -1721,7 +1725,7 @@ int32_t ais2ih_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t ais2ih_pin_int1_route_get(const stmdev_ctx_t *ctx, ais2ih_ctrl4_int1_pad_ctrl_t *val) { int32_t ret; @@ -1740,7 +1744,7 @@ int32_t ais2ih_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t ais2ih_pin_int2_route_set(const stmdev_ctx_t *ctx, ais2ih_ctrl5_int2_pad_ctrl_t *val) { ais2ih_ctrl4_int1_pad_ctrl_t ctrl4_int1_pad_ctrl; @@ -1792,7 +1796,7 @@ int32_t ais2ih_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t ais2ih_pin_int2_route_get(const stmdev_ctx_t *ctx, ais2ih_ctrl5_int2_pad_ctrl_t *val) { int32_t ret; @@ -1810,7 +1814,7 @@ int32_t ais2ih_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2ih_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2ih_ctrl_reg7_t reg; int32_t ret; @@ -1834,7 +1838,7 @@ int32_t ais2ih_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2ih_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2ih_ctrl_reg7_t reg; int32_t ret; @@ -1866,7 +1870,7 @@ int32_t ais2ih_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2ih_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2ih_wake_up_ths_t reg; int32_t ret; @@ -1890,7 +1894,7 @@ int32_t ais2ih_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2ih_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2ih_wake_up_ths_t reg; int32_t ret; @@ -1909,7 +1913,7 @@ int32_t ais2ih_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2ih_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2ih_wake_up_dur_t reg; int32_t ret; @@ -1933,7 +1937,7 @@ int32_t ais2ih_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2ih_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2ih_wake_up_dur_t reg; int32_t ret; @@ -1952,7 +1956,7 @@ int32_t ais2ih_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_wkup_feed_data_set(stmdev_ctx_t *ctx, +int32_t ais2ih_wkup_feed_data_set(const stmdev_ctx_t *ctx, ais2ih_usr_off_on_wu_t val) { ais2ih_ctrl_reg7_t reg; @@ -1977,7 +1981,7 @@ int32_t ais2ih_wkup_feed_data_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_wkup_feed_data_get(stmdev_ctx_t *ctx, +int32_t ais2ih_wkup_feed_data_get(const stmdev_ctx_t *ctx, ais2ih_usr_off_on_wu_t *val) { ais2ih_ctrl_reg7_t reg; @@ -2026,7 +2030,7 @@ int32_t ais2ih_wkup_feed_data_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_act_mode_set(stmdev_ctx_t *ctx, ais2ih_sleep_on_t val) +int32_t ais2ih_act_mode_set(const stmdev_ctx_t *ctx, ais2ih_sleep_on_t val) { ais2ih_wake_up_ths_t wake_up_ths; ais2ih_wake_up_dur_t wake_up_dur; @@ -2067,7 +2071,7 @@ int32_t ais2ih_act_mode_set(stmdev_ctx_t *ctx, ais2ih_sleep_on_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_act_mode_get(stmdev_ctx_t *ctx, ais2ih_sleep_on_t *val) +int32_t ais2ih_act_mode_get(const stmdev_ctx_t *ctx, ais2ih_sleep_on_t *val) { ais2ih_wake_up_ths_t wake_up_ths; ais2ih_wake_up_dur_t wake_up_dur;; @@ -2112,7 +2116,7 @@ int32_t ais2ih_act_mode_get(stmdev_ctx_t *ctx, ais2ih_sleep_on_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2ih_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2ih_wake_up_dur_t reg; int32_t ret; @@ -2136,7 +2140,7 @@ int32_t ais2ih_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2ih_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2ih_wake_up_dur_t reg; int32_t ret; @@ -2168,7 +2172,7 @@ int32_t ais2ih_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2ih_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2ih_tap_ths_x_t reg; int32_t ret; @@ -2192,7 +2196,7 @@ int32_t ais2ih_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2ih_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2ih_tap_ths_x_t reg; int32_t ret; @@ -2211,7 +2215,7 @@ int32_t ais2ih_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2ih_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2ih_tap_ths_y_t reg; int32_t ret; @@ -2235,7 +2239,7 @@ int32_t ais2ih_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2ih_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2ih_tap_ths_y_t reg; int32_t ret; @@ -2254,7 +2258,7 @@ int32_t ais2ih_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t ais2ih_tap_axis_priority_set(const stmdev_ctx_t *ctx, ais2ih_tap_prior_t val) { ais2ih_tap_ths_y_t reg; @@ -2279,7 +2283,7 @@ int32_t ais2ih_tap_axis_priority_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t ais2ih_tap_axis_priority_get(const stmdev_ctx_t *ctx, ais2ih_tap_prior_t *val) { ais2ih_tap_ths_y_t reg; @@ -2329,7 +2333,7 @@ int32_t ais2ih_tap_axis_priority_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2ih_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2ih_tap_ths_z_t reg; int32_t ret; @@ -2353,7 +2357,7 @@ int32_t ais2ih_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2ih_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2ih_tap_ths_z_t reg; int32_t ret; @@ -2372,7 +2376,7 @@ int32_t ais2ih_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2ih_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2ih_tap_ths_z_t reg; int32_t ret; @@ -2396,7 +2400,7 @@ int32_t ais2ih_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2ih_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2ih_tap_ths_z_t reg; int32_t ret; @@ -2415,7 +2419,7 @@ int32_t ais2ih_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2ih_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2ih_tap_ths_z_t reg; int32_t ret; @@ -2439,7 +2443,7 @@ int32_t ais2ih_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2ih_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2ih_tap_ths_z_t reg; int32_t ret; @@ -2458,7 +2462,7 @@ int32_t ais2ih_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2ih_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2ih_tap_ths_z_t reg; int32_t ret; @@ -2482,7 +2486,7 @@ int32_t ais2ih_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2ih_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2ih_tap_ths_z_t reg; int32_t ret; @@ -2505,7 +2509,7 @@ int32_t ais2ih_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2ih_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2ih_int_dur_t reg; int32_t ret; @@ -2533,7 +2537,7 @@ int32_t ais2ih_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2ih_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2ih_int_dur_t reg; int32_t ret; @@ -2556,7 +2560,7 @@ int32_t ais2ih_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2ih_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2ih_int_dur_t reg; int32_t ret; @@ -2584,7 +2588,7 @@ int32_t ais2ih_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2ih_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2ih_int_dur_t reg; int32_t ret; @@ -2608,7 +2612,7 @@ int32_t ais2ih_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2ih_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2ih_int_dur_t reg; int32_t ret; @@ -2637,7 +2641,7 @@ int32_t ais2ih_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2ih_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2ih_int_dur_t reg; int32_t ret; @@ -2656,7 +2660,7 @@ int32_t ais2ih_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_tap_mode_set(stmdev_ctx_t *ctx, +int32_t ais2ih_tap_mode_set(const stmdev_ctx_t *ctx, ais2ih_single_double_tap_t val) { ais2ih_wake_up_ths_t reg; @@ -2681,7 +2685,7 @@ int32_t ais2ih_tap_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_tap_mode_get(stmdev_ctx_t *ctx, +int32_t ais2ih_tap_mode_get(const stmdev_ctx_t *ctx, ais2ih_single_double_tap_t *val) { ais2ih_wake_up_ths_t reg; @@ -2715,7 +2719,7 @@ int32_t ais2ih_tap_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_tap_src_get(stmdev_ctx_t *ctx, ais2ih_tap_src_t *val) +int32_t ais2ih_tap_src_get(const stmdev_ctx_t *ctx, ais2ih_tap_src_t *val) { int32_t ret; @@ -2745,7 +2749,7 @@ int32_t ais2ih_tap_src_get(stmdev_ctx_t *ctx, ais2ih_tap_src_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2ih_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2ih_tap_ths_x_t reg; int32_t ret; @@ -2769,7 +2773,7 @@ int32_t ais2ih_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2ih_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2ih_tap_ths_x_t reg; int32_t ret; @@ -2788,7 +2792,7 @@ int32_t ais2ih_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2ih_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2ih_tap_ths_x_t reg; int32_t ret; @@ -2812,7 +2816,7 @@ int32_t ais2ih_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2ih_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2ih_tap_ths_x_t reg; int32_t ret; @@ -2831,7 +2835,7 @@ int32_t ais2ih_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_6d_src_get(stmdev_ctx_t *ctx, ais2ih_sixd_src_t *val) +int32_t ais2ih_6d_src_get(const stmdev_ctx_t *ctx, ais2ih_sixd_src_t *val) { int32_t ret; @@ -2847,7 +2851,7 @@ int32_t ais2ih_6d_src_get(stmdev_ctx_t *ctx, ais2ih_sixd_src_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_6d_feed_data_set(stmdev_ctx_t *ctx, +int32_t ais2ih_6d_feed_data_set(const stmdev_ctx_t *ctx, ais2ih_lpass_on6d_t val) { ais2ih_ctrl_reg7_t reg; @@ -2872,7 +2876,7 @@ int32_t ais2ih_6d_feed_data_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_6d_feed_data_get(stmdev_ctx_t *ctx, +int32_t ais2ih_6d_feed_data_get(const stmdev_ctx_t *ctx, ais2ih_lpass_on6d_t *val) { ais2ih_ctrl_reg7_t reg; @@ -2920,7 +2924,7 @@ int32_t ais2ih_6d_feed_data_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2ih_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2ih_wake_up_dur_t wake_up_dur; ais2ih_free_fall_t free_fall; @@ -2959,7 +2963,7 @@ int32_t ais2ih_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2ih_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2ih_wake_up_dur_t wake_up_dur; ais2ih_free_fall_t free_fall; @@ -2985,7 +2989,7 @@ int32_t ais2ih_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t ais2ih_ff_threshold_set(const stmdev_ctx_t *ctx, ais2ih_ff_ths_t val) { ais2ih_free_fall_t reg; @@ -3010,7 +3014,7 @@ int32_t ais2ih_ff_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t ais2ih_ff_threshold_get(const stmdev_ctx_t *ctx, ais2ih_ff_ths_t *val) { ais2ih_free_fall_t reg; @@ -3080,7 +3084,7 @@ int32_t ais2ih_ff_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais2ih_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { ais2ih_fifo_ctrl_t reg; int32_t ret; @@ -3104,7 +3108,7 @@ int32_t ais2ih_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2ih_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2ih_fifo_ctrl_t reg; int32_t ret; @@ -3123,7 +3127,7 @@ int32_t ais2ih_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_fifo_mode_set(stmdev_ctx_t *ctx, ais2ih_fmode_t val) +int32_t ais2ih_fifo_mode_set(const stmdev_ctx_t *ctx, ais2ih_fmode_t val) { ais2ih_fifo_ctrl_t reg; int32_t ret; @@ -3147,7 +3151,7 @@ int32_t ais2ih_fifo_mode_set(stmdev_ctx_t *ctx, ais2ih_fmode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_fifo_mode_get(stmdev_ctx_t *ctx, ais2ih_fmode_t *val) +int32_t ais2ih_fifo_mode_get(const stmdev_ctx_t *ctx, ais2ih_fmode_t *val) { ais2ih_fifo_ctrl_t reg; int32_t ret; @@ -3192,7 +3196,7 @@ int32_t ais2ih_fifo_mode_get(stmdev_ctx_t *ctx, ais2ih_fmode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2ih_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2ih_fifo_samples_t reg; int32_t ret; @@ -3210,7 +3214,7 @@ int32_t ais2ih_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2ih_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2ih_fifo_samples_t reg; int32_t ret; @@ -3228,7 +3232,7 @@ int32_t ais2ih_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais2ih_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais2ih_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais2ih_fifo_samples_t reg; int32_t ret; diff --git a/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.h b/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.h index 45ad9705..f5a7abce 100644 --- a/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.h +++ b/sensor/stmemsc/ais2ih_STdC/driver/ais2ih_reg.h @@ -665,9 +665,9 @@ typedef union * them with a custom implementation. */ -int32_t ais2ih_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, +int32_t ais2ih_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t ais2ih_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t ais2ih_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -702,8 +702,8 @@ typedef enum AIS2IH_SINGLE_LOW_PWR_LOW_NOISE_2 = 0x19, AIS2IH_SINGLE_LOW_LOW_NOISE_PWR_12bit = 0x18, } ais2ih_mode_t; -int32_t ais2ih_power_mode_set(stmdev_ctx_t *ctx, ais2ih_mode_t val); -int32_t ais2ih_power_mode_get(stmdev_ctx_t *ctx, ais2ih_mode_t *val); +int32_t ais2ih_power_mode_set(const stmdev_ctx_t *ctx, ais2ih_mode_t val); +int32_t ais2ih_power_mode_get(const stmdev_ctx_t *ctx, ais2ih_mode_t *val); typedef enum { @@ -720,11 +720,11 @@ typedef enum AIS2IH_XL_SET_SW_TRIG = 0x32, /* Use this only in SINGLE mode */ AIS2IH_XL_SET_PIN_TRIG = 0x12, /* Use this only in SINGLE mode */ } ais2ih_odr_t; -int32_t ais2ih_data_rate_set(stmdev_ctx_t *ctx, ais2ih_odr_t val); -int32_t ais2ih_data_rate_get(stmdev_ctx_t *ctx, ais2ih_odr_t *val); +int32_t ais2ih_data_rate_set(const stmdev_ctx_t *ctx, ais2ih_odr_t val); +int32_t ais2ih_data_rate_get(const stmdev_ctx_t *ctx, ais2ih_odr_t *val); -int32_t ais2ih_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2ih_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2ih_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2ih_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -733,13 +733,13 @@ typedef enum AIS2IH_8g = 2, AIS2IH_16g = 3, } ais2ih_fs_t; -int32_t ais2ih_full_scale_set(stmdev_ctx_t *ctx, ais2ih_fs_t val); -int32_t ais2ih_full_scale_get(stmdev_ctx_t *ctx, ais2ih_fs_t *val); +int32_t ais2ih_full_scale_set(const stmdev_ctx_t *ctx, ais2ih_fs_t val); +int32_t ais2ih_full_scale_get(const stmdev_ctx_t *ctx, ais2ih_fs_t *val); -int32_t ais2ih_status_reg_get(stmdev_ctx_t *ctx, +int32_t ais2ih_status_reg_get(const stmdev_ctx_t *ctx, ais2ih_status_t *val); -int32_t ais2ih_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2ih_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -749,42 +749,42 @@ typedef struct ais2ih_sixd_src_t sixd_src; ais2ih_all_int_src_t all_int_src; } ais2ih_all_sources_t; -int32_t ais2ih_all_sources_get(stmdev_ctx_t *ctx, +int32_t ais2ih_all_sources_get(const stmdev_ctx_t *ctx, ais2ih_all_sources_t *val); -int32_t ais2ih_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ais2ih_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t ais2ih_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t ais2ih_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ais2ih_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ais2ih_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t ais2ih_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t ais2ih_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ais2ih_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ais2ih_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t ais2ih_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t ais2ih_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff); typedef enum { AIS2IH_LSb_977ug = 0, AIS2IH_LSb_15mg6 = 1, } ais2ih_usr_off_w_t; -int32_t ais2ih_offset_weight_set(stmdev_ctx_t *ctx, +int32_t ais2ih_offset_weight_set(const stmdev_ctx_t *ctx, ais2ih_usr_off_w_t val); -int32_t ais2ih_offset_weight_get(stmdev_ctx_t *ctx, +int32_t ais2ih_offset_weight_get(const stmdev_ctx_t *ctx, ais2ih_usr_off_w_t *val); -int32_t ais2ih_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t ais2ih_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t ais2ih_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t ais2ih_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t ais2ih_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t ais2ih_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ais2ih_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2ih_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2ih_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2ih_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais2ih_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2ih_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2ih_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2ih_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais2ih_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2ih_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2ih_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2ih_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -792,17 +792,17 @@ typedef enum AIS2IH_XL_ST_POSITIVE = 1, AIS2IH_XL_ST_NEGATIVE = 2, } ais2ih_st_t; -int32_t ais2ih_self_test_set(stmdev_ctx_t *ctx, ais2ih_st_t val); -int32_t ais2ih_self_test_get(stmdev_ctx_t *ctx, ais2ih_st_t *val); +int32_t ais2ih_self_test_set(const stmdev_ctx_t *ctx, ais2ih_st_t val); +int32_t ais2ih_self_test_get(const stmdev_ctx_t *ctx, ais2ih_st_t *val); typedef enum { AIS2IH_DRDY_LATCHED = 0, AIS2IH_DRDY_PULSED = 1, } ais2ih_drdy_pulsed_t; -int32_t ais2ih_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t ais2ih_data_ready_mode_set(const stmdev_ctx_t *ctx, ais2ih_drdy_pulsed_t val); -int32_t ais2ih_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t ais2ih_data_ready_mode_get(const stmdev_ctx_t *ctx, ais2ih_drdy_pulsed_t *val); typedef enum @@ -811,8 +811,8 @@ typedef enum AIS2IH_USER_OFFSET_ON_OUT = 0x01, AIS2IH_HIGH_PASS_ON_OUT = 0x10, } ais2ih_fds_t; -int32_t ais2ih_filter_path_set(stmdev_ctx_t *ctx, ais2ih_fds_t val); -int32_t ais2ih_filter_path_get(stmdev_ctx_t *ctx, ais2ih_fds_t *val); +int32_t ais2ih_filter_path_set(const stmdev_ctx_t *ctx, ais2ih_fds_t val); +int32_t ais2ih_filter_path_get(const stmdev_ctx_t *ctx, ais2ih_fds_t *val); typedef enum { @@ -821,30 +821,30 @@ typedef enum AIS2IH_ODR_DIV_10 = 2, AIS2IH_ODR_DIV_20 = 3, } ais2ih_bw_filt_t; -int32_t ais2ih_filter_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ais2ih_filter_bandwidth_set(const stmdev_ctx_t *ctx, ais2ih_bw_filt_t val); -int32_t ais2ih_filter_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ais2ih_filter_bandwidth_get(const stmdev_ctx_t *ctx, ais2ih_bw_filt_t *val); -int32_t ais2ih_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2ih_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2ih_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2ih_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { AIS2IH_SPI_4_WIRE = 0, AIS2IH_SPI_3_WIRE = 1, } ais2ih_sim_t; -int32_t ais2ih_spi_mode_set(stmdev_ctx_t *ctx, ais2ih_sim_t val); -int32_t ais2ih_spi_mode_get(stmdev_ctx_t *ctx, ais2ih_sim_t *val); +int32_t ais2ih_spi_mode_set(const stmdev_ctx_t *ctx, ais2ih_sim_t val); +int32_t ais2ih_spi_mode_get(const stmdev_ctx_t *ctx, ais2ih_sim_t *val); typedef enum { AIS2IH_I2C_ENABLE = 0, AIS2IH_I2C_DISABLE = 1, } ais2ih_i2c_disable_t; -int32_t ais2ih_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t ais2ih_i2c_interface_set(const stmdev_ctx_t *ctx, ais2ih_i2c_disable_t val); -int32_t ais2ih_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t ais2ih_i2c_interface_get(const stmdev_ctx_t *ctx, ais2ih_i2c_disable_t *val); typedef enum @@ -852,9 +852,9 @@ typedef enum AIS2IH_PULL_UP_CONNECT = 0, AIS2IH_PULL_UP_DISCONNECT = 1, } ais2ih_cs_pu_disc_t; -int32_t ais2ih_cs_mode_set(stmdev_ctx_t *ctx, +int32_t ais2ih_cs_mode_set(const stmdev_ctx_t *ctx, ais2ih_cs_pu_disc_t val); -int32_t ais2ih_cs_mode_get(stmdev_ctx_t *ctx, +int32_t ais2ih_cs_mode_get(const stmdev_ctx_t *ctx, ais2ih_cs_pu_disc_t *val); typedef enum @@ -862,9 +862,9 @@ typedef enum AIS2IH_ACTIVE_HIGH = 0, AIS2IH_ACTIVE_LOW = 1, } ais2ih_h_lactive_t; -int32_t ais2ih_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t ais2ih_pin_polarity_set(const stmdev_ctx_t *ctx, ais2ih_h_lactive_t val); -int32_t ais2ih_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t ais2ih_pin_polarity_get(const stmdev_ctx_t *ctx, ais2ih_h_lactive_t *val); typedef enum @@ -872,9 +872,9 @@ typedef enum AIS2IH_INT_PULSED = 0, AIS2IH_INT_LATCHED = 1, } ais2ih_lir_t; -int32_t ais2ih_int_notification_set(stmdev_ctx_t *ctx, +int32_t ais2ih_int_notification_set(const stmdev_ctx_t *ctx, ais2ih_lir_t val); -int32_t ais2ih_int_notification_get(stmdev_ctx_t *ctx, +int32_t ais2ih_int_notification_get(const stmdev_ctx_t *ctx, ais2ih_lir_t *val); typedef enum @@ -882,36 +882,36 @@ typedef enum AIS2IH_PUSH_PULL = 0, AIS2IH_OPEN_DRAIN = 1, } ais2ih_pp_od_t; -int32_t ais2ih_pin_mode_set(stmdev_ctx_t *ctx, ais2ih_pp_od_t val); -int32_t ais2ih_pin_mode_get(stmdev_ctx_t *ctx, ais2ih_pp_od_t *val); +int32_t ais2ih_pin_mode_set(const stmdev_ctx_t *ctx, ais2ih_pp_od_t val); +int32_t ais2ih_pin_mode_get(const stmdev_ctx_t *ctx, ais2ih_pp_od_t *val); -int32_t ais2ih_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t ais2ih_pin_int1_route_set(const stmdev_ctx_t *ctx, ais2ih_ctrl4_int1_pad_ctrl_t *val); -int32_t ais2ih_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t ais2ih_pin_int1_route_get(const stmdev_ctx_t *ctx, ais2ih_ctrl4_int1_pad_ctrl_t *val); -int32_t ais2ih_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t ais2ih_pin_int2_route_set(const stmdev_ctx_t *ctx, ais2ih_ctrl5_int2_pad_ctrl_t *val); -int32_t ais2ih_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t ais2ih_pin_int2_route_get(const stmdev_ctx_t *ctx, ais2ih_ctrl5_int2_pad_ctrl_t *val); -int32_t ais2ih_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2ih_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2ih_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2ih_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais2ih_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2ih_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2ih_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2ih_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais2ih_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2ih_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2ih_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2ih_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { AIS2IH_HP_FEED = 0, AIS2IH_USER_OFFSET_FEED = 1, } ais2ih_usr_off_on_wu_t; -int32_t ais2ih_wkup_feed_data_set(stmdev_ctx_t *ctx, +int32_t ais2ih_wkup_feed_data_set(const stmdev_ctx_t *ctx, ais2ih_usr_off_on_wu_t val); -int32_t ais2ih_wkup_feed_data_get(stmdev_ctx_t *ctx, +int32_t ais2ih_wkup_feed_data_get(const stmdev_ctx_t *ctx, ais2ih_usr_off_on_wu_t *val); typedef enum @@ -920,18 +920,18 @@ typedef enum AIS2IH_DETECT_ACT_INACT = 1, AIS2IH_DETECT_STAT_MOTION = 3, } ais2ih_sleep_on_t; -int32_t ais2ih_act_mode_set(stmdev_ctx_t *ctx, ais2ih_sleep_on_t val); -int32_t ais2ih_act_mode_get(stmdev_ctx_t *ctx, +int32_t ais2ih_act_mode_set(const stmdev_ctx_t *ctx, ais2ih_sleep_on_t val); +int32_t ais2ih_act_mode_get(const stmdev_ctx_t *ctx, ais2ih_sleep_on_t *val); -int32_t ais2ih_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2ih_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2ih_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2ih_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais2ih_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2ih_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2ih_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2ih_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais2ih_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2ih_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2ih_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2ih_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -942,67 +942,67 @@ typedef enum AIS2IH_YZX = 5, AIS2IH_ZXY = 6, } ais2ih_tap_prior_t; -int32_t ais2ih_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t ais2ih_tap_axis_priority_set(const stmdev_ctx_t *ctx, ais2ih_tap_prior_t val); -int32_t ais2ih_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t ais2ih_tap_axis_priority_get(const stmdev_ctx_t *ctx, ais2ih_tap_prior_t *val); -int32_t ais2ih_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2ih_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2ih_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2ih_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais2ih_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2ih_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t ais2ih_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2ih_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais2ih_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2ih_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t ais2ih_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2ih_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais2ih_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2ih_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t ais2ih_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2ih_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais2ih_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2ih_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2ih_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2ih_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais2ih_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2ih_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2ih_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2ih_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais2ih_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2ih_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2ih_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2ih_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { AIS2IH_ONLY_SINGLE = 0, AIS2IH_BOTH_SINGLE_DOUBLE = 1, } ais2ih_single_double_tap_t; -int32_t ais2ih_tap_mode_set(stmdev_ctx_t *ctx, +int32_t ais2ih_tap_mode_set(const stmdev_ctx_t *ctx, ais2ih_single_double_tap_t val); -int32_t ais2ih_tap_mode_get(stmdev_ctx_t *ctx, +int32_t ais2ih_tap_mode_get(const stmdev_ctx_t *ctx, ais2ih_single_double_tap_t *val); -int32_t ais2ih_tap_src_get(stmdev_ctx_t *ctx, ais2ih_tap_src_t *val); +int32_t ais2ih_tap_src_get(const stmdev_ctx_t *ctx, ais2ih_tap_src_t *val); -int32_t ais2ih_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2ih_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2ih_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2ih_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais2ih_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2ih_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2ih_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2ih_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais2ih_6d_src_get(stmdev_ctx_t *ctx, ais2ih_sixd_src_t *val); +int32_t ais2ih_6d_src_get(const stmdev_ctx_t *ctx, ais2ih_sixd_src_t *val); typedef enum { AIS2IH_ODR_DIV_2_FEED = 0, AIS2IH_LPF2_FEED = 1, } ais2ih_lpass_on6d_t; -int32_t ais2ih_6d_feed_data_set(stmdev_ctx_t *ctx, +int32_t ais2ih_6d_feed_data_set(const stmdev_ctx_t *ctx, ais2ih_lpass_on6d_t val); -int32_t ais2ih_6d_feed_data_get(stmdev_ctx_t *ctx, +int32_t ais2ih_6d_feed_data_get(const stmdev_ctx_t *ctx, ais2ih_lpass_on6d_t *val); -int32_t ais2ih_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2ih_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2ih_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2ih_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -1015,13 +1015,13 @@ typedef enum AIS2IH_FF_TSH_15LSb_FS2g = 6, AIS2IH_FF_TSH_16LSb_FS2g = 7, } ais2ih_ff_ths_t; -int32_t ais2ih_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t ais2ih_ff_threshold_set(const stmdev_ctx_t *ctx, ais2ih_ff_ths_t val); -int32_t ais2ih_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t ais2ih_ff_threshold_get(const stmdev_ctx_t *ctx, ais2ih_ff_ths_t *val); -int32_t ais2ih_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais2ih_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2ih_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais2ih_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -1031,14 +1031,14 @@ typedef enum AIS2IH_BYPASS_TO_STREAM_MODE = 4, AIS2IH_STREAM_MODE = 6, } ais2ih_fmode_t; -int32_t ais2ih_fifo_mode_set(stmdev_ctx_t *ctx, ais2ih_fmode_t val); -int32_t ais2ih_fifo_mode_get(stmdev_ctx_t *ctx, ais2ih_fmode_t *val); +int32_t ais2ih_fifo_mode_set(const stmdev_ctx_t *ctx, ais2ih_fmode_t val); +int32_t ais2ih_fifo_mode_get(const stmdev_ctx_t *ctx, ais2ih_fmode_t *val); -int32_t ais2ih_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2ih_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais2ih_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2ih_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais2ih_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais2ih_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); /** * @} diff --git a/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.c b/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.c index 2af88d3f..54fd6a18 100644 --- a/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.c +++ b/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.c @@ -46,12 +46,14 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak ais328dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak ais328dq_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +69,14 @@ int32_t __weak ais328dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak ais328dq_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak ais328dq_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -126,7 +130,7 @@ float_t ais328dq_from_fs8_to_mg(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais328dq_axis_x_data_set(const stmdev_ctx_t *ctx, uint8_t val) { ais328dq_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -152,7 +156,7 @@ int32_t ais328dq_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais328dq_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais328dq_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -172,7 +176,7 @@ int32_t ais328dq_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais328dq_axis_y_data_set(const stmdev_ctx_t *ctx, uint8_t val) { ais328dq_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -198,7 +202,7 @@ int32_t ais328dq_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais328dq_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais328dq_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -218,7 +222,7 @@ int32_t ais328dq_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais328dq_axis_z_data_set(const stmdev_ctx_t *ctx, uint8_t val) { ais328dq_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -244,7 +248,7 @@ int32_t ais328dq_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais328dq_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais328dq_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -264,7 +268,7 @@ int32_t ais328dq_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_data_rate_set(stmdev_ctx_t *ctx, ais328dq_dr_t val) +int32_t ais328dq_data_rate_set(const stmdev_ctx_t *ctx, ais328dq_dr_t val) { ais328dq_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -291,7 +295,7 @@ int32_t ais328dq_data_rate_set(stmdev_ctx_t *ctx, ais328dq_dr_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_data_rate_get(stmdev_ctx_t *ctx, ais328dq_dr_t *val) +int32_t ais328dq_data_rate_get(const stmdev_ctx_t *ctx, ais328dq_dr_t *val) { ais328dq_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -313,8 +317,8 @@ int32_t ais328dq_data_rate_get(stmdev_ctx_t *ctx, ais328dq_dr_t *val) *val = AIS328DQ_ODR_1Hz; break; - case AIS328DQ_ODR_5Hz2: - *val = AIS328DQ_ODR_5Hz2; + case AIS328DQ_ODR_2Hz: + *val = AIS328DQ_ODR_2Hz; break; case AIS328DQ_ODR_5Hz: @@ -357,7 +361,7 @@ int32_t ais328dq_data_rate_get(stmdev_ctx_t *ctx, ais328dq_dr_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_reference_mode_set(stmdev_ctx_t *ctx, +int32_t ais328dq_reference_mode_set(const stmdev_ctx_t *ctx, ais328dq_hpm_t val) { ais328dq_ctrl_reg2_t ctrl_reg2; @@ -384,7 +388,7 @@ int32_t ais328dq_reference_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_reference_mode_get(stmdev_ctx_t *ctx, +int32_t ais328dq_reference_mode_get(const stmdev_ctx_t *ctx, ais328dq_hpm_t *val) { ais328dq_ctrl_reg2_t ctrl_reg2; @@ -419,7 +423,7 @@ int32_t ais328dq_reference_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_full_scale_set(stmdev_ctx_t *ctx, ais328dq_fs_t val) +int32_t ais328dq_full_scale_set(const stmdev_ctx_t *ctx, ais328dq_fs_t val) { ais328dq_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -445,7 +449,7 @@ int32_t ais328dq_full_scale_set(stmdev_ctx_t *ctx, ais328dq_fs_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_full_scale_get(stmdev_ctx_t *ctx, ais328dq_fs_t *val) +int32_t ais328dq_full_scale_get(const stmdev_ctx_t *ctx, ais328dq_fs_t *val) { ais328dq_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -483,7 +487,7 @@ int32_t ais328dq_full_scale_get(stmdev_ctx_t *ctx, ais328dq_fs_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais328dq_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { ais328dq_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -509,7 +513,7 @@ int32_t ais328dq_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_block_data_update_get(stmdev_ctx_t *ctx, +int32_t ais328dq_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais328dq_ctrl_reg4_t ctrl_reg4; @@ -530,7 +534,7 @@ int32_t ais328dq_block_data_update_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_status_reg_get(stmdev_ctx_t *ctx, +int32_t ais328dq_status_reg_get(const stmdev_ctx_t *ctx, ais328dq_status_reg_t *val) { int32_t ret; @@ -548,7 +552,7 @@ int32_t ais328dq_status_reg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais328dq_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais328dq_status_reg_t status_reg; int32_t ret; @@ -581,7 +585,7 @@ int32_t ais328dq_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t ais328dq_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -617,7 +621,7 @@ int32_t ais328dq_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ais328dq_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -634,7 +638,7 @@ int32_t ais328dq_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais328dq_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { ais328dq_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -660,7 +664,7 @@ int32_t ais328dq_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais328dq_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais328dq_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -680,7 +684,7 @@ int32_t ais328dq_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_self_test_set(stmdev_ctx_t *ctx, ais328dq_st_t val) +int32_t ais328dq_self_test_set(const stmdev_ctx_t *ctx, ais328dq_st_t val) { ais328dq_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -706,7 +710,7 @@ int32_t ais328dq_self_test_set(stmdev_ctx_t *ctx, ais328dq_st_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_self_test_get(stmdev_ctx_t *ctx, ais328dq_st_t *val) +int32_t ais328dq_self_test_get(const stmdev_ctx_t *ctx, ais328dq_st_t *val) { ais328dq_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -744,7 +748,7 @@ int32_t ais328dq_self_test_get(stmdev_ctx_t *ctx, ais328dq_st_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_data_format_set(stmdev_ctx_t *ctx, +int32_t ais328dq_data_format_set(const stmdev_ctx_t *ctx, ais328dq_ble_t val) { ais328dq_ctrl_reg4_t ctrl_reg4; @@ -771,7 +775,7 @@ int32_t ais328dq_data_format_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_data_format_get(stmdev_ctx_t *ctx, +int32_t ais328dq_data_format_get(const stmdev_ctx_t *ctx, ais328dq_ble_t *val) { ais328dq_ctrl_reg4_t ctrl_reg4; @@ -819,7 +823,7 @@ int32_t ais328dq_data_format_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ais328dq_hp_bandwidth_set(const stmdev_ctx_t *ctx, ais328dq_hpcf_t val) { ais328dq_ctrl_reg2_t ctrl_reg2; @@ -846,7 +850,7 @@ int32_t ais328dq_hp_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ais328dq_hp_bandwidth_get(const stmdev_ctx_t *ctx, ais328dq_hpcf_t *val) { ais328dq_ctrl_reg2_t ctrl_reg2; @@ -889,7 +893,7 @@ int32_t ais328dq_hp_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_hp_path_set(stmdev_ctx_t *ctx, ais328dq_hpen_t val) +int32_t ais328dq_hp_path_set(const stmdev_ctx_t *ctx, ais328dq_hpen_t val) { ais328dq_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -916,7 +920,7 @@ int32_t ais328dq_hp_path_set(stmdev_ctx_t *ctx, ais328dq_hpen_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_hp_path_get(stmdev_ctx_t *ctx, ais328dq_hpen_t *val) +int32_t ais328dq_hp_path_get(const stmdev_ctx_t *ctx, ais328dq_hpen_t *val) { ais328dq_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -997,7 +1001,7 @@ int32_t ais328dq_hp_reset_get(stmdev_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_hp_reference_value_set(stmdev_ctx_t *ctx, +int32_t ais328dq_hp_reference_value_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; @@ -1015,7 +1019,7 @@ int32_t ais328dq_hp_reference_value_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_hp_reference_value_get(stmdev_ctx_t *ctx, +int32_t ais328dq_hp_reference_value_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -1046,7 +1050,7 @@ int32_t ais328dq_hp_reference_value_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_spi_mode_set(stmdev_ctx_t *ctx, ais328dq_sim_t val) +int32_t ais328dq_spi_mode_set(const stmdev_ctx_t *ctx, ais328dq_sim_t val) { ais328dq_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -1072,7 +1076,7 @@ int32_t ais328dq_spi_mode_set(stmdev_ctx_t *ctx, ais328dq_sim_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_spi_mode_get(stmdev_ctx_t *ctx, ais328dq_sim_t *val) +int32_t ais328dq_spi_mode_get(const stmdev_ctx_t *ctx, ais328dq_sim_t *val) { ais328dq_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -1119,7 +1123,7 @@ int32_t ais328dq_spi_mode_get(stmdev_ctx_t *ctx, ais328dq_sim_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t ais328dq_pin_int1_route_set(const stmdev_ctx_t *ctx, ais328dq_i1_cfg_t val) { ais328dq_ctrl_reg3_t ctrl_reg3; @@ -1146,7 +1150,7 @@ int32_t ais328dq_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t ais328dq_pin_int1_route_get(const stmdev_ctx_t *ctx, ais328dq_i1_cfg_t *val) { ais328dq_ctrl_reg3_t ctrl_reg3; @@ -1190,7 +1194,7 @@ int32_t ais328dq_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int1_notification_set(stmdev_ctx_t *ctx, +int32_t ais328dq_int1_notification_set(const stmdev_ctx_t *ctx, ais328dq_lir1_t val) { ais328dq_ctrl_reg3_t ctrl_reg3; @@ -1218,7 +1222,7 @@ int32_t ais328dq_int1_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int1_notification_get(stmdev_ctx_t *ctx, +int32_t ais328dq_int1_notification_get(const stmdev_ctx_t *ctx, ais328dq_lir1_t *val) { ais328dq_ctrl_reg3_t ctrl_reg3; @@ -1253,7 +1257,7 @@ int32_t ais328dq_int1_notification_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t ais328dq_pin_int2_route_set(const stmdev_ctx_t *ctx, ais328dq_i2_cfg_t val) { ais328dq_ctrl_reg3_t ctrl_reg3; @@ -1280,7 +1284,7 @@ int32_t ais328dq_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t ais328dq_pin_int2_route_get(const stmdev_ctx_t *ctx, ais328dq_i2_cfg_t *val) { ais328dq_ctrl_reg3_t ctrl_reg3; @@ -1324,7 +1328,7 @@ int32_t ais328dq_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int2_notification_set(stmdev_ctx_t *ctx, +int32_t ais328dq_int2_notification_set(const stmdev_ctx_t *ctx, ais328dq_lir2_t val) { ais328dq_ctrl_reg3_t ctrl_reg3; @@ -1352,7 +1356,7 @@ int32_t ais328dq_int2_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int2_notification_get(stmdev_ctx_t *ctx, +int32_t ais328dq_int2_notification_get(const stmdev_ctx_t *ctx, ais328dq_lir2_t *val) { ais328dq_ctrl_reg3_t ctrl_reg3; @@ -1387,7 +1391,7 @@ int32_t ais328dq_int2_notification_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_pin_mode_set(stmdev_ctx_t *ctx, ais328dq_pp_od_t val) +int32_t ais328dq_pin_mode_set(const stmdev_ctx_t *ctx, ais328dq_pp_od_t val) { ais328dq_ctrl_reg3_t ctrl_reg3; int32_t ret; @@ -1413,7 +1417,7 @@ int32_t ais328dq_pin_mode_set(stmdev_ctx_t *ctx, ais328dq_pp_od_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_pin_mode_get(stmdev_ctx_t *ctx, +int32_t ais328dq_pin_mode_get(const stmdev_ctx_t *ctx, ais328dq_pp_od_t *val) { ais328dq_ctrl_reg3_t ctrl_reg3; @@ -1448,7 +1452,7 @@ int32_t ais328dq_pin_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t ais328dq_pin_polarity_set(const stmdev_ctx_t *ctx, ais328dq_ihl_t val) { ais328dq_ctrl_reg3_t ctrl_reg3; @@ -1475,7 +1479,7 @@ int32_t ais328dq_pin_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t ais328dq_pin_polarity_get(const stmdev_ctx_t *ctx, ais328dq_ihl_t *val) { ais328dq_ctrl_reg3_t ctrl_reg3; @@ -1523,7 +1527,7 @@ int32_t ais328dq_pin_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int1_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t ais328dq_int1_on_threshold_conf_set(const stmdev_ctx_t *ctx, ais328dq_int1_on_th_conf_t val) { ais328dq_int1_cfg_t int1_cfg; @@ -1554,7 +1558,7 @@ int32_t ais328dq_int1_on_threshold_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int1_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t ais328dq_int1_on_threshold_conf_get(const stmdev_ctx_t *ctx, ais328dq_int1_on_th_conf_t *val) { ais328dq_int1_cfg_t int1_cfg; @@ -1579,7 +1583,7 @@ int32_t ais328dq_int1_on_threshold_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int1_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t ais328dq_int1_on_threshold_mode_set(const stmdev_ctx_t *ctx, ais328dq_int1_aoi_t val) { ais328dq_int1_cfg_t int1_cfg; @@ -1605,7 +1609,7 @@ int32_t ais328dq_int1_on_threshold_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int1_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t ais328dq_int1_on_threshold_mode_get(const stmdev_ctx_t *ctx, ais328dq_int1_aoi_t *val) { ais328dq_int1_cfg_t int1_cfg; @@ -1639,7 +1643,7 @@ int32_t ais328dq_int1_on_threshold_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int1_src_get(stmdev_ctx_t *ctx, +int32_t ais328dq_int1_src_get(const stmdev_ctx_t *ctx, ais328dq_int1_src_t *val) { int32_t ret; @@ -1657,7 +1661,7 @@ int32_t ais328dq_int1_src_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais328dq_int1_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { ais328dq_int1_ths_t int1_ths; int32_t ret; @@ -1682,7 +1686,7 @@ int32_t ais328dq_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais328dq_int1_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais328dq_int1_ths_t int1_ths; int32_t ret; @@ -1701,7 +1705,7 @@ int32_t ais328dq_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais328dq_int1_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { ais328dq_int1_duration_t int1_duration; int32_t ret; @@ -1727,7 +1731,7 @@ int32_t ais328dq_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais328dq_int1_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais328dq_int1_duration_t int1_duration; int32_t ret; @@ -1747,7 +1751,7 @@ int32_t ais328dq_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int2_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t ais328dq_int2_on_threshold_conf_set(const stmdev_ctx_t *ctx, ais328dq_int2_on_th_conf_t val) { ais328dq_int2_cfg_t int2_cfg; @@ -1779,7 +1783,7 @@ int32_t ais328dq_int2_on_threshold_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int2_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t ais328dq_int2_on_threshold_conf_get(const stmdev_ctx_t *ctx, ais328dq_int2_on_th_conf_t *val) { ais328dq_int2_cfg_t int2_cfg; @@ -1804,7 +1808,7 @@ int32_t ais328dq_int2_on_threshold_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int2_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t ais328dq_int2_on_threshold_mode_set(const stmdev_ctx_t *ctx, ais328dq_int2_aoi_t val) { ais328dq_int2_cfg_t int2_cfg; @@ -1830,7 +1834,7 @@ int32_t ais328dq_int2_on_threshold_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int2_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t ais328dq_int2_on_threshold_mode_get(const stmdev_ctx_t *ctx, ais328dq_int2_aoi_t *val) { ais328dq_int2_cfg_t int2_cfg; @@ -1864,7 +1868,7 @@ int32_t ais328dq_int2_on_threshold_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int2_src_get(stmdev_ctx_t *ctx, +int32_t ais328dq_int2_src_get(const stmdev_ctx_t *ctx, ais328dq_int2_src_t *val) { int32_t ret; @@ -1882,7 +1886,7 @@ int32_t ais328dq_int2_src_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais328dq_int2_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { ais328dq_int2_ths_t int2_ths; int32_t ret; @@ -1907,7 +1911,7 @@ int32_t ais328dq_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais328dq_int2_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais328dq_int2_ths_t int2_ths; int32_t ret; @@ -1926,7 +1930,7 @@ int32_t ais328dq_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais328dq_int2_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { ais328dq_int2_duration_t int2_duration; int32_t ret; @@ -1952,7 +1956,7 @@ int32_t ais328dq_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais328dq_int2_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais328dq_int2_duration_t int2_duration; int32_t ret; @@ -1985,7 +1989,7 @@ int32_t ais328dq_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais328dq_wkup_to_sleep_set(const stmdev_ctx_t *ctx, uint8_t val) { ais328dq_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -2011,7 +2015,7 @@ int32_t ais328dq_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais328dq_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais328dq_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -2044,7 +2048,7 @@ int32_t ais328dq_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int1_6d_mode_set(stmdev_ctx_t *ctx, +int32_t ais328dq_int1_6d_mode_set(const stmdev_ctx_t *ctx, ais328dq_int1_6d_t val) { ais328dq_int1_cfg_t int1_cfg; @@ -2070,7 +2074,7 @@ int32_t ais328dq_int1_6d_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int1_6d_mode_get(stmdev_ctx_t *ctx, +int32_t ais328dq_int1_6d_mode_get(const stmdev_ctx_t *ctx, ais328dq_int1_6d_t *val) { ais328dq_int1_cfg_t int1_cfg; @@ -2108,7 +2112,7 @@ int32_t ais328dq_int1_6d_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int1_6d_src_get(stmdev_ctx_t *ctx, +int32_t ais328dq_int1_6d_src_get(const stmdev_ctx_t *ctx, ais328dq_int1_src_t *val) { int32_t ret; @@ -2126,7 +2130,7 @@ int32_t ais328dq_int1_6d_src_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int1_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais328dq_int1_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { ais328dq_int1_ths_t int1_ths; int32_t ret; @@ -2150,7 +2154,7 @@ int32_t ais328dq_int1_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int1_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais328dq_int1_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais328dq_int1_ths_t int1_ths; int32_t ret; @@ -2169,7 +2173,7 @@ int32_t ais328dq_int1_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int2_6d_mode_set(stmdev_ctx_t *ctx, +int32_t ais328dq_int2_6d_mode_set(const stmdev_ctx_t *ctx, ais328dq_int2_6d_t val) { ais328dq_int2_cfg_t int2_cfg; @@ -2196,7 +2200,7 @@ int32_t ais328dq_int2_6d_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int2_6d_mode_get(stmdev_ctx_t *ctx, +int32_t ais328dq_int2_6d_mode_get(const stmdev_ctx_t *ctx, ais328dq_int2_6d_t *val) { ais328dq_int2_cfg_t int2_cfg; @@ -2234,7 +2238,7 @@ int32_t ais328dq_int2_6d_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int2_6d_src_get(stmdev_ctx_t *ctx, +int32_t ais328dq_int2_6d_src_get(const stmdev_ctx_t *ctx, ais328dq_int2_src_t *val) { int32_t ret; @@ -2252,7 +2256,7 @@ int32_t ais328dq_int2_6d_src_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int2_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais328dq_int2_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { ais328dq_int2_ths_t int2_ths; int32_t ret; @@ -2277,7 +2281,7 @@ int32_t ais328dq_int2_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais328dq_int2_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais328dq_int2_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais328dq_int2_ths_t int2_ths; int32_t ret; diff --git a/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.h b/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.h index fbbbd151..367fe994 100644 --- a/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.h +++ b/sensor/stmemsc/ais328dq_STdC/driver/ais328dq_reg.h @@ -517,10 +517,10 @@ typedef union * them with a custom implementation. */ -int32_t ais328dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t ais328dq_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t ais328dq_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t ais328dq_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -528,21 +528,21 @@ float_t ais328dq_from_fs2_to_mg(int16_t lsb); float_t ais328dq_from_fs4_to_mg(int16_t lsb); float_t ais328dq_from_fs8_to_mg(int16_t lsb); -int32_t ais328dq_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais328dq_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais328dq_axis_x_data_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais328dq_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais328dq_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais328dq_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais328dq_axis_y_data_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais328dq_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais328dq_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais328dq_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais328dq_axis_z_data_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais328dq_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { AIS328DQ_ODR_OFF = 0x00, AIS328DQ_ODR_Hz5 = 0x02, AIS328DQ_ODR_1Hz = 0x03, - AIS328DQ_ODR_5Hz2 = 0x04, + AIS328DQ_ODR_2Hz = 0x04, AIS328DQ_ODR_5Hz = 0x05, AIS328DQ_ODR_10Hz = 0x06, AIS328DQ_ODR_50Hz = 0x01, @@ -550,17 +550,17 @@ typedef enum AIS328DQ_ODR_400Hz = 0x21, AIS328DQ_ODR_1kHz = 0x31, } ais328dq_dr_t; -int32_t ais328dq_data_rate_set(stmdev_ctx_t *ctx, ais328dq_dr_t val); -int32_t ais328dq_data_rate_get(stmdev_ctx_t *ctx, ais328dq_dr_t *val); +int32_t ais328dq_data_rate_set(const stmdev_ctx_t *ctx, ais328dq_dr_t val); +int32_t ais328dq_data_rate_get(const stmdev_ctx_t *ctx, ais328dq_dr_t *val); typedef enum { AIS328DQ_NORMAL_MODE = 0, AIS328DQ_REF_MODE_ENABLE = 1, } ais328dq_hpm_t; -int32_t ais328dq_reference_mode_set(stmdev_ctx_t *ctx, +int32_t ais328dq_reference_mode_set(const stmdev_ctx_t *ctx, ais328dq_hpm_t val); -int32_t ais328dq_reference_mode_get(stmdev_ctx_t *ctx, +int32_t ais328dq_reference_mode_get(const stmdev_ctx_t *ctx, ais328dq_hpm_t *val); typedef enum @@ -569,28 +569,28 @@ typedef enum AIS328DQ_4g = 1, AIS328DQ_8g = 3, } ais328dq_fs_t; -int32_t ais328dq_full_scale_set(stmdev_ctx_t *ctx, ais328dq_fs_t val); -int32_t ais328dq_full_scale_get(stmdev_ctx_t *ctx, +int32_t ais328dq_full_scale_set(const stmdev_ctx_t *ctx, ais328dq_fs_t val); +int32_t ais328dq_full_scale_get(const stmdev_ctx_t *ctx, ais328dq_fs_t *val); -int32_t ais328dq_block_data_update_set(stmdev_ctx_t *ctx, +int32_t ais328dq_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ais328dq_block_data_update_get(stmdev_ctx_t *ctx, +int32_t ais328dq_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais328dq_status_reg_get(stmdev_ctx_t *ctx, +int32_t ais328dq_status_reg_get(const stmdev_ctx_t *ctx, ais328dq_status_reg_t *val); -int32_t ais328dq_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ais328dq_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais328dq_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t ais328dq_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t ais328dq_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t ais328dq_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ais328dq_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais328dq_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais328dq_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais328dq_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -598,17 +598,17 @@ typedef enum AIS328DQ_ST_POSITIVE = 1, AIS328DQ_ST_NEGATIVE = 5, } ais328dq_st_t; -int32_t ais328dq_self_test_set(stmdev_ctx_t *ctx, ais328dq_st_t val); -int32_t ais328dq_self_test_get(stmdev_ctx_t *ctx, ais328dq_st_t *val); +int32_t ais328dq_self_test_set(const stmdev_ctx_t *ctx, ais328dq_st_t val); +int32_t ais328dq_self_test_get(const stmdev_ctx_t *ctx, ais328dq_st_t *val); typedef enum { AIS328DQ_LSB_AT_LOW_ADD = 0, AIS328DQ_MSB_AT_LOW_ADD = 1, } ais328dq_ble_t; -int32_t ais328dq_data_format_set(stmdev_ctx_t *ctx, +int32_t ais328dq_data_format_set(const stmdev_ctx_t *ctx, ais328dq_ble_t val); -int32_t ais328dq_data_format_get(stmdev_ctx_t *ctx, +int32_t ais328dq_data_format_get(const stmdev_ctx_t *ctx, ais328dq_ble_t *val); typedef enum @@ -618,9 +618,9 @@ typedef enum AIS328DQ_CUT_OFF_32Hz = 2, AIS328DQ_CUT_OFF_64Hz = 3, } ais328dq_hpcf_t; -int32_t ais328dq_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ais328dq_hp_bandwidth_set(const stmdev_ctx_t *ctx, ais328dq_hpcf_t val); -int32_t ais328dq_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ais328dq_hp_bandwidth_get(const stmdev_ctx_t *ctx, ais328dq_hpcf_t *val); typedef enum @@ -634,14 +634,14 @@ typedef enum AIS328DQ_HP_ON_INT2_OUT = 6, AIS328DQ_HP_ON_INT1_OUT = 5, } ais328dq_hpen_t; -int32_t ais328dq_hp_path_set(stmdev_ctx_t *ctx, ais328dq_hpen_t val); -int32_t ais328dq_hp_path_get(stmdev_ctx_t *ctx, ais328dq_hpen_t *val); +int32_t ais328dq_hp_path_set(const stmdev_ctx_t *ctx, ais328dq_hpen_t val); +int32_t ais328dq_hp_path_get(const stmdev_ctx_t *ctx, ais328dq_hpen_t *val); int32_t ais328dq_hp_reset_get(stmdev_ctx_t *ctx); -int32_t ais328dq_hp_reference_value_set(stmdev_ctx_t *ctx, +int32_t ais328dq_hp_reference_value_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ais328dq_hp_reference_value_get(stmdev_ctx_t *ctx, +int32_t ais328dq_hp_reference_value_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -649,8 +649,8 @@ typedef enum AIS328DQ_SPI_4_WIRE = 0, AIS328DQ_SPI_3_WIRE = 1, } ais328dq_sim_t; -int32_t ais328dq_spi_mode_set(stmdev_ctx_t *ctx, ais328dq_sim_t val); -int32_t ais328dq_spi_mode_get(stmdev_ctx_t *ctx, ais328dq_sim_t *val); +int32_t ais328dq_spi_mode_set(const stmdev_ctx_t *ctx, ais328dq_sim_t val); +int32_t ais328dq_spi_mode_get(const stmdev_ctx_t *ctx, ais328dq_sim_t *val); typedef enum { @@ -659,9 +659,9 @@ typedef enum AIS328DQ_PAD1_DRDY = 2, AIS328DQ_PAD1_BOOT = 3, } ais328dq_i1_cfg_t; -int32_t ais328dq_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t ais328dq_pin_int1_route_set(const stmdev_ctx_t *ctx, ais328dq_i1_cfg_t val); -int32_t ais328dq_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t ais328dq_pin_int1_route_get(const stmdev_ctx_t *ctx, ais328dq_i1_cfg_t *val); typedef enum @@ -669,9 +669,9 @@ typedef enum AIS328DQ_INT1_PULSED = 0, AIS328DQ_INT1_LATCHED = 1, } ais328dq_lir1_t; -int32_t ais328dq_int1_notification_set(stmdev_ctx_t *ctx, +int32_t ais328dq_int1_notification_set(const stmdev_ctx_t *ctx, ais328dq_lir1_t val); -int32_t ais328dq_int1_notification_get(stmdev_ctx_t *ctx, +int32_t ais328dq_int1_notification_get(const stmdev_ctx_t *ctx, ais328dq_lir1_t *val); typedef enum @@ -681,9 +681,9 @@ typedef enum AIS328DQ_PAD2_DRDY = 2, AIS328DQ_PAD2_BOOT = 3, } ais328dq_i2_cfg_t; -int32_t ais328dq_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t ais328dq_pin_int2_route_set(const stmdev_ctx_t *ctx, ais328dq_i2_cfg_t val); -int32_t ais328dq_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t ais328dq_pin_int2_route_get(const stmdev_ctx_t *ctx, ais328dq_i2_cfg_t *val); typedef enum @@ -691,9 +691,9 @@ typedef enum AIS328DQ_INT2_PULSED = 0, AIS328DQ_INT2_LATCHED = 1, } ais328dq_lir2_t; -int32_t ais328dq_int2_notification_set(stmdev_ctx_t *ctx, +int32_t ais328dq_int2_notification_set(const stmdev_ctx_t *ctx, ais328dq_lir2_t val); -int32_t ais328dq_int2_notification_get(stmdev_ctx_t *ctx, +int32_t ais328dq_int2_notification_get(const stmdev_ctx_t *ctx, ais328dq_lir2_t *val); typedef enum @@ -701,9 +701,9 @@ typedef enum AIS328DQ_PUSH_PULL = 0, AIS328DQ_OPEN_DRAIN = 1, } ais328dq_pp_od_t; -int32_t ais328dq_pin_mode_set(stmdev_ctx_t *ctx, +int32_t ais328dq_pin_mode_set(const stmdev_ctx_t *ctx, ais328dq_pp_od_t val); -int32_t ais328dq_pin_mode_get(stmdev_ctx_t *ctx, +int32_t ais328dq_pin_mode_get(const stmdev_ctx_t *ctx, ais328dq_pp_od_t *val); typedef enum @@ -711,9 +711,9 @@ typedef enum AIS328DQ_ACTIVE_HIGH = 0, AIS328DQ_ACTIVE_LOW = 1, } ais328dq_ihl_t; -int32_t ais328dq_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t ais328dq_pin_polarity_set(const stmdev_ctx_t *ctx, ais328dq_ihl_t val); -int32_t ais328dq_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t ais328dq_pin_polarity_get(const stmdev_ctx_t *ctx, ais328dq_ihl_t *val); typedef struct @@ -725,9 +725,9 @@ typedef struct uint8_t int1_zlie : 1; uint8_t int1_zhie : 1; } ais328dq_int1_on_th_conf_t; -int32_t ais328dq_int1_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t ais328dq_int1_on_threshold_conf_set(const stmdev_ctx_t *ctx, ais328dq_int1_on_th_conf_t val); -int32_t ais328dq_int1_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t ais328dq_int1_on_threshold_conf_get(const stmdev_ctx_t *ctx, ais328dq_int1_on_th_conf_t *val); typedef enum @@ -735,19 +735,19 @@ typedef enum AIS328DQ_INT1_ON_THRESHOLD_OR = 0, AIS328DQ_INT1_ON_THRESHOLD_AND = 1, } ais328dq_int1_aoi_t; -int32_t ais328dq_int1_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t ais328dq_int1_on_threshold_mode_set(const stmdev_ctx_t *ctx, ais328dq_int1_aoi_t val); -int32_t ais328dq_int1_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t ais328dq_int1_on_threshold_mode_get(const stmdev_ctx_t *ctx, ais328dq_int1_aoi_t *val); -int32_t ais328dq_int1_src_get(stmdev_ctx_t *ctx, +int32_t ais328dq_int1_src_get(const stmdev_ctx_t *ctx, ais328dq_int1_src_t *val); -int32_t ais328dq_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais328dq_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais328dq_int1_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais328dq_int1_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais328dq_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais328dq_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais328dq_int1_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais328dq_int1_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -758,9 +758,9 @@ typedef struct uint8_t int2_zlie : 1; uint8_t int2_zhie : 1; } ais328dq_int2_on_th_conf_t; -int32_t ais328dq_int2_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t ais328dq_int2_on_threshold_conf_set(const stmdev_ctx_t *ctx, ais328dq_int2_on_th_conf_t val); -int32_t ais328dq_int2_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t ais328dq_int2_on_threshold_conf_get(const stmdev_ctx_t *ctx, ais328dq_int2_on_th_conf_t *val); typedef enum @@ -768,22 +768,22 @@ typedef enum AIS328DQ_INT2_ON_THRESHOLD_OR = 0, AIS328DQ_INT2_ON_THRESHOLD_AND = 1, } ais328dq_int2_aoi_t; -int32_t ais328dq_int2_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t ais328dq_int2_on_threshold_mode_set(const stmdev_ctx_t *ctx, ais328dq_int2_aoi_t val); -int32_t ais328dq_int2_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t ais328dq_int2_on_threshold_mode_get(const stmdev_ctx_t *ctx, ais328dq_int2_aoi_t *val); -int32_t ais328dq_int2_src_get(stmdev_ctx_t *ctx, +int32_t ais328dq_int2_src_get(const stmdev_ctx_t *ctx, ais328dq_int2_src_t *val); -int32_t ais328dq_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais328dq_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais328dq_int2_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais328dq_int2_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais328dq_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais328dq_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais328dq_int2_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais328dq_int2_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais328dq_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais328dq_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais328dq_wkup_to_sleep_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais328dq_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -791,16 +791,16 @@ typedef enum AIS328DQ_6D_INT1_MOVEMENT = 1, AIS328DQ_6D_INT1_POSITION = 3, } ais328dq_int1_6d_t; -int32_t ais328dq_int1_6d_mode_set(stmdev_ctx_t *ctx, +int32_t ais328dq_int1_6d_mode_set(const stmdev_ctx_t *ctx, ais328dq_int1_6d_t val); -int32_t ais328dq_int1_6d_mode_get(stmdev_ctx_t *ctx, +int32_t ais328dq_int1_6d_mode_get(const stmdev_ctx_t *ctx, ais328dq_int1_6d_t *val); -int32_t ais328dq_int1_6d_src_get(stmdev_ctx_t *ctx, +int32_t ais328dq_int1_6d_src_get(const stmdev_ctx_t *ctx, ais328dq_int1_src_t *val); -int32_t ais328dq_int1_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais328dq_int1_6d_treshold_get(stmdev_ctx_t *ctx, +int32_t ais328dq_int1_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais328dq_int1_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -809,16 +809,16 @@ typedef enum AIS328DQ_6D_INT2_MOVEMENT = 1, AIS328DQ_6D_INT2_POSITION = 3, } ais328dq_int2_6d_t; -int32_t ais328dq_int2_6d_mode_set(stmdev_ctx_t *ctx, +int32_t ais328dq_int2_6d_mode_set(const stmdev_ctx_t *ctx, ais328dq_int2_6d_t val); -int32_t ais328dq_int2_6d_mode_get(stmdev_ctx_t *ctx, +int32_t ais328dq_int2_6d_mode_get(const stmdev_ctx_t *ctx, ais328dq_int2_6d_t *val); -int32_t ais328dq_int2_6d_src_get(stmdev_ctx_t *ctx, +int32_t ais328dq_int2_6d_src_get(const stmdev_ctx_t *ctx, ais328dq_int2_src_t *val); -int32_t ais328dq_int2_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais328dq_int2_6d_treshold_get(stmdev_ctx_t *ctx, +int32_t ais328dq_int2_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais328dq_int2_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); /** diff --git a/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.c b/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.c index 66962db6..c51fd64e 100644 --- a/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.c +++ b/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.c @@ -46,12 +46,14 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak ais3624dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak ais3624dq_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +69,14 @@ int32_t __weak ais3624dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak ais3624dq_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak ais3624dq_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -126,7 +130,7 @@ float_t ais3624dq_from_fs24_to_mg(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais3624dq_axis_x_data_set(const stmdev_ctx_t *ctx, uint8_t val) { ais3624dq_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -152,7 +156,7 @@ int32_t ais3624dq_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais3624dq_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais3624dq_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -172,7 +176,7 @@ int32_t ais3624dq_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais3624dq_axis_y_data_set(const stmdev_ctx_t *ctx, uint8_t val) { ais3624dq_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -198,7 +202,7 @@ int32_t ais3624dq_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais3624dq_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais3624dq_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -218,7 +222,7 @@ int32_t ais3624dq_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais3624dq_axis_z_data_set(const stmdev_ctx_t *ctx, uint8_t val) { ais3624dq_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -244,7 +248,7 @@ int32_t ais3624dq_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais3624dq_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais3624dq_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -264,7 +268,7 @@ int32_t ais3624dq_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_data_rate_set(stmdev_ctx_t *ctx, ais3624dq_dr_t val) +int32_t ais3624dq_data_rate_set(const stmdev_ctx_t *ctx, ais3624dq_dr_t val) { ais3624dq_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -291,7 +295,7 @@ int32_t ais3624dq_data_rate_set(stmdev_ctx_t *ctx, ais3624dq_dr_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_data_rate_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_data_rate_get(const stmdev_ctx_t *ctx, ais3624dq_dr_t *val) { ais3624dq_ctrl_reg1_t ctrl_reg1; @@ -314,8 +318,8 @@ int32_t ais3624dq_data_rate_get(stmdev_ctx_t *ctx, *val = AIS3624DQ_ODR_1Hz; break; - case AIS3624DQ_ODR_5Hz2: - *val = AIS3624DQ_ODR_5Hz2; + case AIS3624DQ_ODR_2Hz: + *val = AIS3624DQ_ODR_2Hz; break; case AIS3624DQ_ODR_5Hz: @@ -358,7 +362,7 @@ int32_t ais3624dq_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_reference_mode_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_reference_mode_set(const stmdev_ctx_t *ctx, ais3624dq_hpm_t val) { ais3624dq_ctrl_reg2_t ctrl_reg2; @@ -385,7 +389,7 @@ int32_t ais3624dq_reference_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_reference_mode_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_reference_mode_get(const stmdev_ctx_t *ctx, ais3624dq_hpm_t *val) { ais3624dq_ctrl_reg2_t ctrl_reg2; @@ -420,7 +424,7 @@ int32_t ais3624dq_reference_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_full_scale_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_full_scale_set(const stmdev_ctx_t *ctx, ais3624dq_fs_t val) { ais3624dq_ctrl_reg4_t ctrl_reg4; @@ -447,7 +451,7 @@ int32_t ais3624dq_full_scale_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_full_scale_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_full_scale_get(const stmdev_ctx_t *ctx, ais3624dq_fs_t *val) { ais3624dq_ctrl_reg4_t ctrl_reg4; @@ -486,7 +490,7 @@ int32_t ais3624dq_full_scale_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_block_data_update_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { ais3624dq_ctrl_reg4_t ctrl_reg4; @@ -513,7 +517,7 @@ int32_t ais3624dq_block_data_update_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_block_data_update_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais3624dq_ctrl_reg4_t ctrl_reg4; @@ -534,7 +538,7 @@ int32_t ais3624dq_block_data_update_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_status_reg_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_status_reg_get(const stmdev_ctx_t *ctx, ais3624dq_status_reg_t *val) { int32_t ret; @@ -552,7 +556,7 @@ int32_t ais3624dq_status_reg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais3624dq_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais3624dq_status_reg_t status_reg; int32_t ret; @@ -585,7 +589,7 @@ int32_t ais3624dq_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -622,7 +626,7 @@ int32_t ais3624dq_acceleration_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ais3624dq_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -639,7 +643,7 @@ int32_t ais3624dq_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais3624dq_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { ais3624dq_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -665,7 +669,7 @@ int32_t ais3624dq_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais3624dq_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais3624dq_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -685,7 +689,7 @@ int32_t ais3624dq_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_self_test_set(stmdev_ctx_t *ctx, ais3624dq_st_t val) +int32_t ais3624dq_self_test_set(const stmdev_ctx_t *ctx, ais3624dq_st_t val) { ais3624dq_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -711,7 +715,7 @@ int32_t ais3624dq_self_test_set(stmdev_ctx_t *ctx, ais3624dq_st_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_self_test_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_self_test_get(const stmdev_ctx_t *ctx, ais3624dq_st_t *val) { ais3624dq_ctrl_reg4_t ctrl_reg4; @@ -750,7 +754,7 @@ int32_t ais3624dq_self_test_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_data_format_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_data_format_set(const stmdev_ctx_t *ctx, ais3624dq_ble_t val) { ais3624dq_ctrl_reg4_t ctrl_reg4; @@ -777,7 +781,7 @@ int32_t ais3624dq_data_format_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_data_format_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_data_format_get(const stmdev_ctx_t *ctx, ais3624dq_ble_t *val) { ais3624dq_ctrl_reg4_t ctrl_reg4; @@ -825,7 +829,7 @@ int32_t ais3624dq_data_format_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_hp_bandwidth_set(const stmdev_ctx_t *ctx, ais3624dq_hpcf_t val) { ais3624dq_ctrl_reg2_t ctrl_reg2; @@ -852,7 +856,7 @@ int32_t ais3624dq_hp_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_hp_bandwidth_get(const stmdev_ctx_t *ctx, ais3624dq_hpcf_t *val) { ais3624dq_ctrl_reg2_t ctrl_reg2; @@ -895,7 +899,7 @@ int32_t ais3624dq_hp_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_hp_path_set(stmdev_ctx_t *ctx, ais3624dq_hpen_t val) +int32_t ais3624dq_hp_path_set(const stmdev_ctx_t *ctx, ais3624dq_hpen_t val) { ais3624dq_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -922,7 +926,7 @@ int32_t ais3624dq_hp_path_set(stmdev_ctx_t *ctx, ais3624dq_hpen_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_hp_path_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_hp_path_get(const stmdev_ctx_t *ctx, ais3624dq_hpen_t *val) { ais3624dq_ctrl_reg2_t ctrl_reg2; @@ -985,7 +989,7 @@ int32_t ais3624dq_hp_path_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_hp_reset_get(stmdev_ctx_t *ctx) +int32_t ais3624dq_hp_reset_get(const stmdev_ctx_t *ctx) { uint8_t dummy; int32_t ret; @@ -1004,7 +1008,7 @@ int32_t ais3624dq_hp_reset_get(stmdev_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_hp_reference_value_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_hp_reference_value_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; @@ -1022,7 +1026,7 @@ int32_t ais3624dq_hp_reference_value_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_hp_reference_value_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_hp_reference_value_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -1053,7 +1057,7 @@ int32_t ais3624dq_hp_reference_value_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_spi_mode_set(stmdev_ctx_t *ctx, ais3624dq_sim_t val) +int32_t ais3624dq_spi_mode_set(const stmdev_ctx_t *ctx, ais3624dq_sim_t val) { ais3624dq_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -1079,7 +1083,7 @@ int32_t ais3624dq_spi_mode_set(stmdev_ctx_t *ctx, ais3624dq_sim_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_spi_mode_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_spi_mode_get(const stmdev_ctx_t *ctx, ais3624dq_sim_t *val) { ais3624dq_ctrl_reg4_t ctrl_reg4; @@ -1127,7 +1131,7 @@ int32_t ais3624dq_spi_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_pin_int1_route_set(const stmdev_ctx_t *ctx, ais3624dq_i1_cfg_t val) { ais3624dq_ctrl_reg3_t ctrl_reg3; @@ -1154,7 +1158,7 @@ int32_t ais3624dq_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_pin_int1_route_get(const stmdev_ctx_t *ctx, ais3624dq_i1_cfg_t *val) { ais3624dq_ctrl_reg3_t ctrl_reg3; @@ -1198,7 +1202,7 @@ int32_t ais3624dq_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int1_notification_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_int1_notification_set(const stmdev_ctx_t *ctx, ais3624dq_lir1_t val) { ais3624dq_ctrl_reg3_t ctrl_reg3; @@ -1226,7 +1230,7 @@ int32_t ais3624dq_int1_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int1_notification_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int1_notification_get(const stmdev_ctx_t *ctx, ais3624dq_lir1_t *val) { ais3624dq_ctrl_reg3_t ctrl_reg3; @@ -1261,7 +1265,7 @@ int32_t ais3624dq_int1_notification_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_pin_int2_route_set(const stmdev_ctx_t *ctx, ais3624dq_i2_cfg_t val) { ais3624dq_ctrl_reg3_t ctrl_reg3; @@ -1288,7 +1292,7 @@ int32_t ais3624dq_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_pin_int2_route_get(const stmdev_ctx_t *ctx, ais3624dq_i2_cfg_t *val) { ais3624dq_ctrl_reg3_t ctrl_reg3; @@ -1332,7 +1336,7 @@ int32_t ais3624dq_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int2_notification_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_int2_notification_set(const stmdev_ctx_t *ctx, ais3624dq_lir2_t val) { ais3624dq_ctrl_reg3_t ctrl_reg3; @@ -1360,7 +1364,7 @@ int32_t ais3624dq_int2_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int2_notification_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int2_notification_get(const stmdev_ctx_t *ctx, ais3624dq_lir2_t *val) { ais3624dq_ctrl_reg3_t ctrl_reg3; @@ -1395,7 +1399,7 @@ int32_t ais3624dq_int2_notification_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_pin_mode_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_pin_mode_set(const stmdev_ctx_t *ctx, ais3624dq_pp_od_t val) { ais3624dq_ctrl_reg3_t ctrl_reg3; @@ -1422,7 +1426,7 @@ int32_t ais3624dq_pin_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_pin_mode_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_pin_mode_get(const stmdev_ctx_t *ctx, ais3624dq_pp_od_t *val) { ais3624dq_ctrl_reg3_t ctrl_reg3; @@ -1457,7 +1461,7 @@ int32_t ais3624dq_pin_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_pin_polarity_set(const stmdev_ctx_t *ctx, ais3624dq_ihl_t val) { ais3624dq_ctrl_reg3_t ctrl_reg3; @@ -1484,7 +1488,7 @@ int32_t ais3624dq_pin_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_pin_polarity_get(const stmdev_ctx_t *ctx, ais3624dq_ihl_t *val) { ais3624dq_ctrl_reg3_t ctrl_reg3; @@ -1532,7 +1536,7 @@ int32_t ais3624dq_pin_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int1_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_int1_on_threshold_conf_set(const stmdev_ctx_t *ctx, ais3624dq_int1_on_th_conf_t val) { ais3624dq_int1_cfg_t int1_cfg; @@ -1564,7 +1568,7 @@ int32_t ais3624dq_int1_on_threshold_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int1_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int1_on_threshold_conf_get(const stmdev_ctx_t *ctx, ais3624dq_int1_on_th_conf_t *val) { ais3624dq_int1_cfg_t int1_cfg; @@ -1590,7 +1594,7 @@ int32_t ais3624dq_int1_on_threshold_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int1_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_int1_on_threshold_mode_set(const stmdev_ctx_t *ctx, ais3624dq_int1_aoi_t val) { ais3624dq_int1_cfg_t int1_cfg; @@ -1617,7 +1621,7 @@ int32_t ais3624dq_int1_on_threshold_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int1_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int1_on_threshold_mode_get(const stmdev_ctx_t *ctx, ais3624dq_int1_aoi_t *val) { ais3624dq_int1_cfg_t int1_cfg; @@ -1652,7 +1656,7 @@ int32_t ais3624dq_int1_on_threshold_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int1_src_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int1_src_get(const stmdev_ctx_t *ctx, ais3624dq_int1_src_t *val) { int32_t ret; @@ -1670,7 +1674,7 @@ int32_t ais3624dq_int1_src_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais3624dq_int1_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { ais3624dq_int1_ths_t int1_ths; int32_t ret; @@ -1696,7 +1700,7 @@ int32_t ais3624dq_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais3624dq_int1_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais3624dq_int1_ths_t int1_ths; int32_t ret; @@ -1716,7 +1720,7 @@ int32_t ais3624dq_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais3624dq_int1_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { ais3624dq_int1_duration_t int1_duration; int32_t ret; @@ -1742,7 +1746,7 @@ int32_t ais3624dq_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais3624dq_int1_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais3624dq_int1_duration_t int1_duration; int32_t ret; @@ -1762,7 +1766,7 @@ int32_t ais3624dq_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int2_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_int2_on_threshold_conf_set(const stmdev_ctx_t *ctx, ais3624dq_int2_on_th_conf_t val) { ais3624dq_int2_cfg_t int2_cfg; @@ -1794,7 +1798,7 @@ int32_t ais3624dq_int2_on_threshold_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int2_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int2_on_threshold_conf_get(const stmdev_ctx_t *ctx, ais3624dq_int2_on_th_conf_t *val) { ais3624dq_int2_cfg_t int2_cfg; @@ -1820,7 +1824,7 @@ int32_t ais3624dq_int2_on_threshold_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int2_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_int2_on_threshold_mode_set(const stmdev_ctx_t *ctx, ais3624dq_int2_aoi_t val) { ais3624dq_int2_cfg_t int2_cfg; @@ -1847,7 +1851,7 @@ int32_t ais3624dq_int2_on_threshold_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int2_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int2_on_threshold_mode_get(const stmdev_ctx_t *ctx, ais3624dq_int2_aoi_t *val) { ais3624dq_int2_cfg_t int2_cfg; @@ -1882,7 +1886,7 @@ int32_t ais3624dq_int2_on_threshold_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int2_src_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int2_src_get(const stmdev_ctx_t *ctx, ais3624dq_int2_src_t *val) { int32_t ret; @@ -1900,7 +1904,7 @@ int32_t ais3624dq_int2_src_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais3624dq_int2_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { ais3624dq_int2_ths_t int2_ths; int32_t ret; @@ -1926,7 +1930,7 @@ int32_t ais3624dq_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais3624dq_int2_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais3624dq_int2_ths_t int2_ths; int32_t ret; @@ -1946,7 +1950,7 @@ int32_t ais3624dq_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais3624dq_int2_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { ais3624dq_int2_duration_t int2_duration; int32_t ret; @@ -1972,7 +1976,7 @@ int32_t ais3624dq_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais3624dq_int2_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais3624dq_int2_duration_t int2_duration; int32_t ret; @@ -2005,7 +2009,7 @@ int32_t ais3624dq_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais3624dq_wkup_to_sleep_set(const stmdev_ctx_t *ctx, uint8_t val) { ais3624dq_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -2031,7 +2035,7 @@ int32_t ais3624dq_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ais3624dq_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais3624dq_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -2064,7 +2068,7 @@ int32_t ais3624dq_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int1_6d_mode_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_int1_6d_mode_set(const stmdev_ctx_t *ctx, ais3624dq_int1_6d_t val) { ais3624dq_int1_cfg_t int1_cfg; @@ -2092,7 +2096,7 @@ int32_t ais3624dq_int1_6d_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int1_6d_mode_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int1_6d_mode_get(const stmdev_ctx_t *ctx, ais3624dq_int1_6d_t *val) { ais3624dq_int1_cfg_t int1_cfg; @@ -2131,7 +2135,7 @@ int32_t ais3624dq_int1_6d_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int1_6d_src_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int1_6d_src_get(const stmdev_ctx_t *ctx, ais3624dq_int1_src_t *val) { int32_t ret; @@ -2149,7 +2153,7 @@ int32_t ais3624dq_int1_6d_src_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int1_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais3624dq_int1_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { ais3624dq_int1_ths_t int1_ths; int32_t ret; @@ -2175,7 +2179,7 @@ int32_t ais3624dq_int1_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int1_6d_treshold_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int1_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais3624dq_int1_ths_t int1_ths; @@ -2196,7 +2200,7 @@ int32_t ais3624dq_int1_6d_treshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int2_6d_mode_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_int2_6d_mode_set(const stmdev_ctx_t *ctx, ais3624dq_int2_6d_t val) { ais3624dq_int2_cfg_t int2_cfg; @@ -2224,7 +2228,7 @@ int32_t ais3624dq_int2_6d_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int2_6d_mode_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int2_6d_mode_get(const stmdev_ctx_t *ctx, ais3624dq_int2_6d_t *val) { ais3624dq_int2_cfg_t int2_cfg; @@ -2263,7 +2267,7 @@ int32_t ais3624dq_int2_6d_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int2_6d_src_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int2_6d_src_get(const stmdev_ctx_t *ctx, ais3624dq_int2_src_t *val) { int32_t ret; @@ -2281,7 +2285,7 @@ int32_t ais3624dq_int2_6d_src_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int2_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ais3624dq_int2_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { ais3624dq_int2_ths_t int2_ths; int32_t ret; @@ -2307,7 +2311,7 @@ int32_t ais3624dq_int2_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ais3624dq_int2_6d_treshold_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int2_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { ais3624dq_int2_ths_t int2_ths; diff --git a/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.h b/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.h index 3ba16a95..2a39de99 100644 --- a/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.h +++ b/sensor/stmemsc/ais3624dq_STdC/driver/ais3624dq_reg.h @@ -496,10 +496,10 @@ typedef union * them with a custom implementation. */ -int32_t ais3624dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t ais3624dq_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t ais3624dq_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t ais3624dq_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -507,21 +507,21 @@ float_t ais3624dq_from_fs6_to_mg(int16_t lsb); float_t ais3624dq_from_fs12_to_mg(int16_t lsb); float_t ais3624dq_from_fs24_to_mg(int16_t lsb); -int32_t ais3624dq_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais3624dq_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais3624dq_axis_x_data_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais3624dq_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais3624dq_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais3624dq_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais3624dq_axis_y_data_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais3624dq_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais3624dq_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais3624dq_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais3624dq_axis_z_data_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais3624dq_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { AIS3624DQ_ODR_OFF = 0x00, AIS3624DQ_ODR_Hz5 = 0x02, AIS3624DQ_ODR_1Hz = 0x03, - AIS3624DQ_ODR_5Hz2 = 0x04, + AIS3624DQ_ODR_2Hz = 0x04, AIS3624DQ_ODR_5Hz = 0x05, AIS3624DQ_ODR_10Hz = 0x06, AIS3624DQ_ODR_50Hz = 0x01, @@ -529,9 +529,9 @@ typedef enum AIS3624DQ_ODR_400Hz = 0x21, AIS3624DQ_ODR_1kHz = 0x31, } ais3624dq_dr_t; -int32_t ais3624dq_data_rate_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_data_rate_set(const stmdev_ctx_t *ctx, ais3624dq_dr_t val); -int32_t ais3624dq_data_rate_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_data_rate_get(const stmdev_ctx_t *ctx, ais3624dq_dr_t *val); typedef enum @@ -539,9 +539,9 @@ typedef enum AIS3624DQ_NORMAL_MODE = 0, AIS3624DQ_REF_MODE_ENABLE = 1, } ais3624dq_hpm_t; -int32_t ais3624dq_reference_mode_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_reference_mode_set(const stmdev_ctx_t *ctx, ais3624dq_hpm_t val); -int32_t ais3624dq_reference_mode_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_reference_mode_get(const stmdev_ctx_t *ctx, ais3624dq_hpm_t *val); typedef enum @@ -550,29 +550,29 @@ typedef enum AIS3624DQ_12g = 1, AIS3624DQ_24g = 3, } ais3624dq_fs_t; -int32_t ais3624dq_full_scale_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_full_scale_set(const stmdev_ctx_t *ctx, ais3624dq_fs_t val); -int32_t ais3624dq_full_scale_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_full_scale_get(const stmdev_ctx_t *ctx, ais3624dq_fs_t *val); -int32_t ais3624dq_block_data_update_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ais3624dq_block_data_update_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais3624dq_status_reg_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_status_reg_get(const stmdev_ctx_t *ctx, ais3624dq_status_reg_t *val); -int32_t ais3624dq_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais3624dq_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t ais3624dq_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t ais3624dq_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ais3624dq_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais3624dq_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais3624dq_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais3624dq_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -580,9 +580,9 @@ typedef enum AIS3624DQ_ST_POSITIVE = 1, AIS3624DQ_ST_NEGATIVE = 5, } ais3624dq_st_t; -int32_t ais3624dq_self_test_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_self_test_set(const stmdev_ctx_t *ctx, ais3624dq_st_t val); -int32_t ais3624dq_self_test_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_self_test_get(const stmdev_ctx_t *ctx, ais3624dq_st_t *val); typedef enum @@ -590,9 +590,9 @@ typedef enum AIS3624DQ_LSB_AT_LOW_ADD = 0, AIS3624DQ_MSB_AT_LOW_ADD = 1, } ais3624dq_ble_t; -int32_t ais3624dq_data_format_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_data_format_set(const stmdev_ctx_t *ctx, ais3624dq_ble_t val); -int32_t ais3624dq_data_format_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_data_format_get(const stmdev_ctx_t *ctx, ais3624dq_ble_t *val); typedef enum @@ -602,9 +602,9 @@ typedef enum AIS3624DQ_CUT_OFF_32Hz = 2, AIS3624DQ_CUT_OFF_64Hz = 3, } ais3624dq_hpcf_t; -int32_t ais3624dq_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_hp_bandwidth_set(const stmdev_ctx_t *ctx, ais3624dq_hpcf_t val); -int32_t ais3624dq_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_hp_bandwidth_get(const stmdev_ctx_t *ctx, ais3624dq_hpcf_t *val); typedef enum @@ -618,16 +618,16 @@ typedef enum AIS3624DQ_HP_ON_INT2_OUT = 6, AIS3624DQ_HP_ON_INT1_OUT = 5, } ais3624dq_hpen_t; -int32_t ais3624dq_hp_path_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_hp_path_set(const stmdev_ctx_t *ctx, ais3624dq_hpen_t val); -int32_t ais3624dq_hp_path_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_hp_path_get(const stmdev_ctx_t *ctx, ais3624dq_hpen_t *val); -int32_t ais3624dq_hp_reset_get(stmdev_ctx_t *ctx); +int32_t ais3624dq_hp_reset_get(const stmdev_ctx_t *ctx); -int32_t ais3624dq_hp_reference_value_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_hp_reference_value_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ais3624dq_hp_reference_value_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_hp_reference_value_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -635,9 +635,9 @@ typedef enum AIS3624DQ_SPI_4_WIRE = 0, AIS3624DQ_SPI_3_WIRE = 1, } ais3624dq_sim_t; -int32_t ais3624dq_spi_mode_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_spi_mode_set(const stmdev_ctx_t *ctx, ais3624dq_sim_t val); -int32_t ais3624dq_spi_mode_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_spi_mode_get(const stmdev_ctx_t *ctx, ais3624dq_sim_t *val); typedef enum @@ -647,9 +647,9 @@ typedef enum AIS3624DQ_PAD1_DRDY = 2, AIS3624DQ_PAD1_BOOT = 3, } ais3624dq_i1_cfg_t; -int32_t ais3624dq_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_pin_int1_route_set(const stmdev_ctx_t *ctx, ais3624dq_i1_cfg_t val); -int32_t ais3624dq_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_pin_int1_route_get(const stmdev_ctx_t *ctx, ais3624dq_i1_cfg_t *val); typedef enum @@ -657,9 +657,9 @@ typedef enum AIS3624DQ_INT1_PULSED = 0, AIS3624DQ_INT1_LATCHED = 1, } ais3624dq_lir1_t; -int32_t ais3624dq_int1_notification_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_int1_notification_set(const stmdev_ctx_t *ctx, ais3624dq_lir1_t val); -int32_t ais3624dq_int1_notification_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int1_notification_get(const stmdev_ctx_t *ctx, ais3624dq_lir1_t *val); typedef enum @@ -669,9 +669,9 @@ typedef enum AIS3624DQ_PAD2_DRDY = 2, AIS3624DQ_PAD2_BOOT = 3, } ais3624dq_i2_cfg_t; -int32_t ais3624dq_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_pin_int2_route_set(const stmdev_ctx_t *ctx, ais3624dq_i2_cfg_t val); -int32_t ais3624dq_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_pin_int2_route_get(const stmdev_ctx_t *ctx, ais3624dq_i2_cfg_t *val); typedef enum @@ -679,9 +679,9 @@ typedef enum AIS3624DQ_INT2_PULSED = 0, AIS3624DQ_INT2_LATCHED = 1, } ais3624dq_lir2_t; -int32_t ais3624dq_int2_notification_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_int2_notification_set(const stmdev_ctx_t *ctx, ais3624dq_lir2_t val); -int32_t ais3624dq_int2_notification_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int2_notification_get(const stmdev_ctx_t *ctx, ais3624dq_lir2_t *val); typedef enum @@ -689,9 +689,9 @@ typedef enum AIS3624DQ_PUSH_PULL = 0, AIS3624DQ_OPEN_DRAIN = 1, } ais3624dq_pp_od_t; -int32_t ais3624dq_pin_mode_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_pin_mode_set(const stmdev_ctx_t *ctx, ais3624dq_pp_od_t val); -int32_t ais3624dq_pin_mode_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_pin_mode_get(const stmdev_ctx_t *ctx, ais3624dq_pp_od_t *val); typedef enum @@ -699,9 +699,9 @@ typedef enum AIS3624DQ_ACTIVE_HIGH = 0, AIS3624DQ_ACTIVE_LOW = 1, } ais3624dq_ihl_t; -int32_t ais3624dq_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_pin_polarity_set(const stmdev_ctx_t *ctx, ais3624dq_ihl_t val); -int32_t ais3624dq_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_pin_polarity_get(const stmdev_ctx_t *ctx, ais3624dq_ihl_t *val); typedef struct @@ -713,9 +713,9 @@ typedef struct uint8_t int1_zlie : 1; uint8_t int1_zhie : 1; } ais3624dq_int1_on_th_conf_t; -int32_t ais3624dq_int1_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_int1_on_threshold_conf_set(const stmdev_ctx_t *ctx, ais3624dq_int1_on_th_conf_t val); -int32_t ais3624dq_int1_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int1_on_threshold_conf_get(const stmdev_ctx_t *ctx, ais3624dq_int1_on_th_conf_t *val); typedef enum @@ -723,19 +723,19 @@ typedef enum AIS3624DQ_INT1_ON_THRESHOLD_OR = 0, AIS3624DQ_INT1_ON_THRESHOLD_AND = 1, } ais3624dq_int1_aoi_t; -int32_t ais3624dq_int1_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_int1_on_threshold_mode_set(const stmdev_ctx_t *ctx, ais3624dq_int1_aoi_t val); -int32_t ais3624dq_int1_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int1_on_threshold_mode_get(const stmdev_ctx_t *ctx, ais3624dq_int1_aoi_t *val); -int32_t ais3624dq_int1_src_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int1_src_get(const stmdev_ctx_t *ctx, ais3624dq_int1_src_t *val); -int32_t ais3624dq_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais3624dq_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais3624dq_int1_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais3624dq_int1_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais3624dq_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais3624dq_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais3624dq_int1_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais3624dq_int1_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -746,9 +746,9 @@ typedef struct uint8_t int2_zlie : 1; uint8_t int2_zhie : 1; } ais3624dq_int2_on_th_conf_t; -int32_t ais3624dq_int2_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_int2_on_threshold_conf_set(const stmdev_ctx_t *ctx, ais3624dq_int2_on_th_conf_t val); -int32_t ais3624dq_int2_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int2_on_threshold_conf_get(const stmdev_ctx_t *ctx, ais3624dq_int2_on_th_conf_t *val); typedef enum @@ -756,22 +756,22 @@ typedef enum AIS3624DQ_INT2_ON_THRESHOLD_OR = 0, AIS3624DQ_INT2_ON_THRESHOLD_AND = 1, } ais3624dq_int2_aoi_t; -int32_t ais3624dq_int2_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_int2_on_threshold_mode_set(const stmdev_ctx_t *ctx, ais3624dq_int2_aoi_t val); -int32_t ais3624dq_int2_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int2_on_threshold_mode_get(const stmdev_ctx_t *ctx, ais3624dq_int2_aoi_t *val); -int32_t ais3624dq_int2_src_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int2_src_get(const stmdev_ctx_t *ctx, ais3624dq_int2_src_t *val); -int32_t ais3624dq_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais3624dq_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais3624dq_int2_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais3624dq_int2_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais3624dq_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais3624dq_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais3624dq_int2_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais3624dq_int2_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ais3624dq_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ais3624dq_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ais3624dq_wkup_to_sleep_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ais3624dq_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -779,17 +779,17 @@ typedef enum AIS3624DQ_6D_INT1_MOVEMENT = 1, AIS3624DQ_6D_INT1_POSITION = 3, } ais3624dq_int1_6d_t; -int32_t ais3624dq_int1_6d_mode_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_int1_6d_mode_set(const stmdev_ctx_t *ctx, ais3624dq_int1_6d_t val); -int32_t ais3624dq_int1_6d_mode_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int1_6d_mode_get(const stmdev_ctx_t *ctx, ais3624dq_int1_6d_t *val); -int32_t ais3624dq_int1_6d_src_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int1_6d_src_get(const stmdev_ctx_t *ctx, ais3624dq_int1_src_t *val); -int32_t ais3624dq_int1_6d_treshold_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_int1_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ais3624dq_int1_6d_treshold_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int1_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -798,17 +798,17 @@ typedef enum AIS3624DQ_6D_INT2_MOVEMENT = 1, AIS3624DQ_6D_INT2_POSITION = 3, } ais3624dq_int2_6d_t; -int32_t ais3624dq_int2_6d_mode_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_int2_6d_mode_set(const stmdev_ctx_t *ctx, ais3624dq_int2_6d_t val); -int32_t ais3624dq_int2_6d_mode_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int2_6d_mode_get(const stmdev_ctx_t *ctx, ais3624dq_int2_6d_t *val); -int32_t ais3624dq_int2_6d_src_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int2_6d_src_get(const stmdev_ctx_t *ctx, ais3624dq_int2_src_t *val); -int32_t ais3624dq_int2_6d_treshold_set(stmdev_ctx_t *ctx, +int32_t ais3624dq_int2_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ais3624dq_int2_6d_treshold_get(stmdev_ctx_t *ctx, +int32_t ais3624dq_int2_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); /** diff --git a/sensor/stmemsc/asm330lhb_STdC/driver/asm330lhb_reg.c b/sensor/stmemsc/asm330lhb_STdC/driver/asm330lhb_reg.c index d2f87190..86b5dbd8 100644 --- a/sensor/stmemsc/asm330lhb_STdC/driver/asm330lhb_reg.c +++ b/sensor/stmemsc/asm330lhb_STdC/driver/asm330lhb_reg.c @@ -46,11 +46,18 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak asm330lhb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, - uint16_t len) +int32_t __weak asm330lhb_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len) { int32_t ret; + + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); + return ret; } @@ -64,11 +71,18 @@ int32_t __weak asm330lhb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak asm330lhb_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, - uint16_t len) +int32_t __weak asm330lhb_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len) { int32_t ret; + + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); + return ret; } @@ -165,8 +179,8 @@ float_t asm330lhb_from_lsb_to_nsec(int32_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_full_scale_set(stmdev_ctx_t *ctx, - asm330lhb_fs_xl_t val) +int32_t asm330lhb_xl_full_scale_set(const stmdev_ctx_t *ctx, + asm330lhb_fs_xl_t val) { asm330lhb_ctrl1_xl_t ctrl1_xl; int32_t ret; @@ -176,7 +190,7 @@ int32_t asm330lhb_xl_full_scale_set(stmdev_ctx_t *ctx, { ctrl1_xl.fs_xl = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL1_XL, - (uint8_t *)&ctrl1_xl, 1); + (uint8_t *)&ctrl1_xl, 1); } return ret; } @@ -189,8 +203,8 @@ int32_t asm330lhb_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_full_scale_get(stmdev_ctx_t *ctx, - asm330lhb_fs_xl_t *val) +int32_t asm330lhb_xl_full_scale_get(const stmdev_ctx_t *ctx, + asm330lhb_fs_xl_t *val) { asm330lhb_ctrl1_xl_t ctrl1_xl; int32_t ret; @@ -225,8 +239,8 @@ int32_t asm330lhb_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_data_rate_set(stmdev_ctx_t *ctx, - asm330lhb_odr_xl_t val) +int32_t asm330lhb_xl_data_rate_set(const stmdev_ctx_t *ctx, + asm330lhb_odr_xl_t val) { asm330lhb_odr_xl_t odr_xl = val; asm330lhb_emb_fsm_enable_t fsm_enable; @@ -454,7 +468,7 @@ int32_t asm330lhb_xl_data_rate_set(stmdev_ctx_t *ctx, { ctrl1_xl.odr_xl = (uint8_t)odr_xl; ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL1_XL, - (uint8_t *)&ctrl1_xl, 1); + (uint8_t *)&ctrl1_xl, 1); } return ret; } @@ -467,8 +481,8 @@ int32_t asm330lhb_xl_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_data_rate_get(stmdev_ctx_t *ctx, - asm330lhb_odr_xl_t *val) +int32_t asm330lhb_xl_data_rate_get(const stmdev_ctx_t *ctx, + asm330lhb_odr_xl_t *val) { asm330lhb_ctrl1_xl_t ctrl1_xl; int32_t ret; @@ -521,8 +535,8 @@ int32_t asm330lhb_xl_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_gy_full_scale_set(stmdev_ctx_t *ctx, - asm330lhb_fs_g_t val) +int32_t asm330lhb_gy_full_scale_set(const stmdev_ctx_t *ctx, + asm330lhb_fs_g_t val) { asm330lhb_ctrl2_g_t ctrl2_g; int32_t ret; @@ -544,8 +558,8 @@ int32_t asm330lhb_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_gy_full_scale_get(stmdev_ctx_t *ctx, - asm330lhb_fs_g_t *val) +int32_t asm330lhb_gy_full_scale_get(const stmdev_ctx_t *ctx, + asm330lhb_fs_g_t *val) { asm330lhb_ctrl2_g_t ctrl2_g; int32_t ret; @@ -586,8 +600,8 @@ int32_t asm330lhb_gy_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_gy_data_rate_set(stmdev_ctx_t *ctx, - asm330lhb_odr_g_t val) +int32_t asm330lhb_gy_data_rate_set(const stmdev_ctx_t *ctx, + asm330lhb_odr_g_t val) { asm330lhb_odr_g_t odr_gy = val; asm330lhb_emb_fsm_enable_t fsm_enable; @@ -829,8 +843,8 @@ int32_t asm330lhb_gy_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_gy_data_rate_get(stmdev_ctx_t *ctx, - asm330lhb_odr_g_t *val) +int32_t asm330lhb_gy_data_rate_get(const stmdev_ctx_t *ctx, + asm330lhb_odr_g_t *val) { asm330lhb_ctrl2_g_t ctrl2_g; int32_t ret; @@ -880,7 +894,7 @@ int32_t asm330lhb_gy_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_ctrl3_c_t ctrl3_c; int32_t ret; @@ -902,7 +916,7 @@ int32_t asm330lhb_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_ctrl3_c_t ctrl3_c; int32_t ret; @@ -922,8 +936,8 @@ int32_t asm330lhb_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_offset_weight_set(stmdev_ctx_t *ctx, - asm330lhb_usr_off_w_t val) +int32_t asm330lhb_xl_offset_weight_set(const stmdev_ctx_t *ctx, + asm330lhb_usr_off_w_t val) { asm330lhb_ctrl6_c_t ctrl6_c; int32_t ret; @@ -946,8 +960,8 @@ int32_t asm330lhb_xl_offset_weight_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_offset_weight_get(stmdev_ctx_t *ctx, - asm330lhb_usr_off_w_t *val) +int32_t asm330lhb_xl_offset_weight_get(const stmdev_ctx_t *ctx, + asm330lhb_usr_off_w_t *val) { asm330lhb_ctrl6_c_t ctrl6_c; int32_t ret; @@ -977,8 +991,8 @@ int32_t asm330lhb_xl_offset_weight_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_power_mode_set(stmdev_ctx_t *ctx, - asm330lhb_xl_hm_mode_t val) +int32_t asm330lhb_xl_power_mode_set(const stmdev_ctx_t *ctx, + asm330lhb_xl_hm_mode_t val) { asm330lhb_ctrl6_c_t ctrl6_c; int32_t ret; @@ -1000,8 +1014,8 @@ int32_t asm330lhb_xl_power_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_power_mode_get(stmdev_ctx_t *ctx, - asm330lhb_xl_hm_mode_t *val) +int32_t asm330lhb_xl_power_mode_get(const stmdev_ctx_t *ctx, + asm330lhb_xl_hm_mode_t *val) { asm330lhb_ctrl6_c_t ctrl6_c; int32_t ret; @@ -1030,8 +1044,8 @@ int32_t asm330lhb_xl_power_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_gy_power_mode_set(stmdev_ctx_t *ctx, - asm330lhb_g_hm_mode_t val) +int32_t asm330lhb_gy_power_mode_set(const stmdev_ctx_t *ctx, + asm330lhb_g_hm_mode_t val) { asm330lhb_ctrl7_g_t ctrl7_g; int32_t ret; @@ -1053,8 +1067,8 @@ int32_t asm330lhb_gy_power_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_gy_power_mode_get(stmdev_ctx_t *ctx, - asm330lhb_g_hm_mode_t *val) +int32_t asm330lhb_gy_power_mode_get(const stmdev_ctx_t *ctx, + asm330lhb_g_hm_mode_t *val) { asm330lhb_ctrl7_g_t ctrl7_g; int32_t ret; @@ -1085,27 +1099,27 @@ int32_t asm330lhb_gy_power_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_all_sources_get(stmdev_ctx_t *ctx, - asm330lhb_all_sources_t *val) +int32_t asm330lhb_all_sources_get(const stmdev_ctx_t *ctx, + asm330lhb_all_sources_t *val) { int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_ALL_INT_SRC, - (uint8_t *)&val->all_int_src, 1); + (uint8_t *)&val->all_int_src, 1); if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_SRC, - (uint8_t *)&val->wake_up_src, 1); + (uint8_t *)&val->wake_up_src, 1); } if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_D6D_SRC, - (uint8_t *)&val->d6d_src, 1); + (uint8_t *)&val->d6d_src, 1); } if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG, - (uint8_t *)&val->status_reg, 1); + (uint8_t *)&val->status_reg, 1); } if (ret == 0) { @@ -1114,22 +1128,22 @@ int32_t asm330lhb_all_sources_get(stmdev_ctx_t *ctx, if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_STATUS, - (uint8_t *)&val->emb_func_status, 1); + (uint8_t *)&val->emb_func_status, 1); } if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_STATUS_A, - (uint8_t *)&val->fsm_status_a, 1); + (uint8_t *)&val->fsm_status_a, 1); } if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_STATUS_B, - (uint8_t *)&val->fsm_status_b, 1); + (uint8_t *)&val->fsm_status_b, 1); } if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_MLC_STATUS, - (uint8_t *)&val->mlc_status, 1); + (uint8_t *)&val->mlc_status, 1); } if (ret == 0) { @@ -1147,8 +1161,8 @@ int32_t asm330lhb_all_sources_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_status_reg_get(stmdev_ctx_t *ctx, - asm330lhb_status_reg_t *val) +int32_t asm330lhb_status_reg_get(const stmdev_ctx_t *ctx, + asm330lhb_status_reg_t *val) { int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG, (uint8_t *) val, 1); @@ -1163,13 +1177,13 @@ int32_t asm330lhb_status_reg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_status_reg_t status_reg; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG, - (uint8_t *)&status_reg, 1); + (uint8_t *)&status_reg, 1); *val = status_reg.xlda; return ret; @@ -1183,13 +1197,13 @@ int32_t asm330lhb_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_status_reg_t status_reg; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG, - (uint8_t *)&status_reg, 1); + (uint8_t *)&status_reg, 1); *val = status_reg.gda; return ret; @@ -1203,13 +1217,13 @@ int32_t asm330lhb_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_status_reg_t status_reg; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG, - (uint8_t *)&status_reg, 1); + (uint8_t *)&status_reg, 1); *val = status_reg.tda; return ret; @@ -1224,13 +1238,13 @@ int32_t asm330lhb_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_boot_device_status_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_boot_device_status_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_status_reg_t status_reg; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG, - (uint8_t *)&status_reg, 1); + (uint8_t *)&status_reg, 1); *val = status_reg.boot_check_fail; return ret; @@ -1246,7 +1260,7 @@ int32_t asm330lhb_boot_device_status_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t asm330lhb_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; ret = asm330lhb_write_reg(ctx, ASM330LHB_X_OFS_USR, buff, 1); @@ -1263,7 +1277,7 @@ int32_t asm330lhb_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t asm330lhb_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_X_OFS_USR, buff, 1); @@ -1280,7 +1294,7 @@ int32_t asm330lhb_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t asm330lhb_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; ret = asm330lhb_write_reg(ctx, ASM330LHB_Y_OFS_USR, buff, 1); @@ -1297,7 +1311,7 @@ int32_t asm330lhb_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t asm330lhb_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_Y_OFS_USR, buff, 1); @@ -1314,7 +1328,7 @@ int32_t asm330lhb_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t asm330lhb_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; ret = asm330lhb_write_reg(ctx, ASM330LHB_Z_OFS_USR, buff, 1); @@ -1331,7 +1345,7 @@ int32_t asm330lhb_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t asm330lhb_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_Z_OFS_USR, buff, 1); @@ -1346,7 +1360,7 @@ int32_t asm330lhb_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_ctrl7_g_t ctrl7_g; int32_t ret; @@ -1368,7 +1382,7 @@ int32_t asm330lhb_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_ctrl7_g_t ctrl7_g; int32_t ret; @@ -1399,7 +1413,7 @@ int32_t asm330lhb_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_timestamp_rst(stmdev_ctx_t *ctx) +int32_t asm330lhb_timestamp_rst(const stmdev_ctx_t *ctx) { uint8_t rst_val = 0xAA; @@ -1414,7 +1428,7 @@ int32_t asm330lhb_timestamp_rst(stmdev_ctx_t *ctx) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_ctrl10_c_t ctrl10_c; int32_t ret; @@ -1424,7 +1438,7 @@ int32_t asm330lhb_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) { ctrl10_c.timestamp_en = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL10_C, - (uint8_t *)&ctrl10_c, 1); + (uint8_t *)&ctrl10_c, 1); } return ret; } @@ -1437,7 +1451,7 @@ int32_t asm330lhb_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_ctrl10_c_t ctrl10_c; int32_t ret; @@ -1458,7 +1472,7 @@ int32_t asm330lhb_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t asm330lhb_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; @@ -1492,8 +1506,8 @@ int32_t asm330lhb_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_rounding_mode_set(stmdev_ctx_t *ctx, - asm330lhb_rounding_t val) +int32_t asm330lhb_rounding_mode_set(const stmdev_ctx_t *ctx, + asm330lhb_rounding_t val) { asm330lhb_ctrl5_c_t ctrl5_c; int32_t ret; @@ -1515,8 +1529,8 @@ int32_t asm330lhb_rounding_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_rounding_mode_get(stmdev_ctx_t *ctx, - asm330lhb_rounding_t *val) +int32_t asm330lhb_rounding_mode_get(const stmdev_ctx_t *ctx, + asm330lhb_rounding_t *val) { asm330lhb_ctrl5_c_t ctrl5_c; int32_t ret; @@ -1553,7 +1567,7 @@ int32_t asm330lhb_rounding_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t asm330lhb_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1574,7 +1588,7 @@ int32_t asm330lhb_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t asm330lhb_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1599,7 +1613,7 @@ int32_t asm330lhb_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t asm330lhb_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1623,7 +1637,7 @@ int32_t asm330lhb_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_DATA_OUT_X_L, val, 6); @@ -1652,18 +1666,18 @@ int32_t asm330lhb_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_internal_freq_fine_t internal_freq_fine; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_INTERNAL_FREQ_FINE, - (uint8_t *)&internal_freq_fine, 1); + (uint8_t *)&internal_freq_fine, 1); if (ret == 0) { internal_freq_fine.freq_fine = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_INTERNAL_FREQ_FINE, - (uint8_t *)&internal_freq_fine, 1); + (uint8_t *)&internal_freq_fine, 1); } return ret; } @@ -1678,13 +1692,13 @@ int32_t asm330lhb_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_internal_freq_fine_t internal_freq_fine; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_INTERNAL_FREQ_FINE, - (uint8_t *)&internal_freq_fine, 1); + (uint8_t *)&internal_freq_fine, 1); *val = internal_freq_fine.freq_fine; return ret; @@ -1699,19 +1713,19 @@ int32_t asm330lhb_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_mem_bank_set(stmdev_ctx_t *ctx, - asm330lhb_reg_access_t val) +int32_t asm330lhb_mem_bank_set(const stmdev_ctx_t *ctx, + asm330lhb_reg_access_t val) { asm330lhb_func_cfg_access_t func_cfg_access; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_FUNC_CFG_ACCESS, - (uint8_t *)&func_cfg_access, 1); + (uint8_t *)&func_cfg_access, 1); if (ret == 0) { func_cfg_access.reg_access = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_FUNC_CFG_ACCESS, - (uint8_t *)&func_cfg_access, 1); + (uint8_t *)&func_cfg_access, 1); } return ret; } @@ -1725,14 +1739,14 @@ int32_t asm330lhb_mem_bank_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_mem_bank_get(stmdev_ctx_t *ctx, - asm330lhb_reg_access_t *val) +int32_t asm330lhb_mem_bank_get(const stmdev_ctx_t *ctx, + asm330lhb_reg_access_t *val) { asm330lhb_func_cfg_access_t func_cfg_access; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_FUNC_CFG_ACCESS, - (uint8_t *)&func_cfg_access, 1); + (uint8_t *)&func_cfg_access, 1); switch (func_cfg_access.reg_access) { case ASM330LHB_USER_BANK: @@ -1757,8 +1771,8 @@ int32_t asm330lhb_mem_bank_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add, - uint8_t *val) +int32_t asm330lhb_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t add, + uint8_t *val) { asm330lhb_page_rw_t page_rw; asm330lhb_page_sel_t page_sel; @@ -1784,13 +1798,13 @@ int32_t asm330lhb_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add, page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); page_sel.not_used_01 = 1; ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL, - (uint8_t *)&page_sel, 1); + (uint8_t *)&page_sel, 1); } if (ret == 0) { page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); + (uint8_t *)&page_address, 1); } if (ret == 0) { @@ -1822,8 +1836,8 @@ int32_t asm330lhb_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add, - uint8_t *buf, uint8_t len) +int32_t asm330lhb_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t add, + uint8_t *buf, uint8_t len) { asm330lhb_page_rw_t page_rw; asm330lhb_page_sel_t page_sel; @@ -1854,13 +1868,13 @@ int32_t asm330lhb_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add, page_sel.page_sel = msb; page_sel.not_used_01 = 1; ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL, - (uint8_t *)&page_sel, 1); + (uint8_t *)&page_sel, 1); } if (ret == 0) { page_address.page_addr = lsb; ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); + (uint8_t *)&page_address, 1); } for (i = 0; i < len; i++) { @@ -1874,7 +1888,7 @@ int32_t asm330lhb_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add, { msb++; ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL, - (uint8_t *)&page_sel, 1); + (uint8_t *)&page_sel, 1); } lsb++; } @@ -1883,7 +1897,7 @@ int32_t asm330lhb_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add, page_sel.page_sel = msb; page_sel.not_used_01 = 1; ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL, - (uint8_t *)&page_sel, 1); + (uint8_t *)&page_sel, 1); } } } @@ -1893,7 +1907,7 @@ int32_t asm330lhb_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add, page_sel.page_sel = 0; page_sel.not_used_01 = 1; ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL, - (uint8_t *)&page_sel, 1); + (uint8_t *)&page_sel, 1); } if (ret == 0) { @@ -1920,8 +1934,8 @@ int32_t asm330lhb_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add, - uint8_t *val) +int32_t asm330lhb_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, + uint8_t *val) { asm330lhb_page_rw_t page_rw; asm330lhb_page_sel_t page_sel; @@ -1947,13 +1961,13 @@ int32_t asm330lhb_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add, page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); page_sel.not_used_01 = 1; ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL, - (uint8_t *)&page_sel, 1); + (uint8_t *)&page_sel, 1); } if (ret == 0) { page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); + (uint8_t *)&page_address, 1); } if (ret == 0) { @@ -1984,19 +1998,19 @@ int32_t asm330lhb_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_data_ready_mode_set(stmdev_ctx_t *ctx, - asm330lhb_dataready_pulsed_t val) +int32_t asm330lhb_data_ready_mode_set(const stmdev_ctx_t *ctx, + asm330lhb_dataready_pulsed_t val) { asm330lhb_counter_bdr_reg1_t counter_bdr_reg1; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, - (uint8_t *)&counter_bdr_reg1, 1); + (uint8_t *)&counter_bdr_reg1, 1); if (ret == 0) { counter_bdr_reg1.dataready_pulsed = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, - (uint8_t *)&counter_bdr_reg1, 1); + (uint8_t *)&counter_bdr_reg1, 1); } return ret; } @@ -2010,14 +2024,14 @@ int32_t asm330lhb_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_data_ready_mode_get(stmdev_ctx_t *ctx, - asm330lhb_dataready_pulsed_t *val) +int32_t asm330lhb_data_ready_mode_get(const stmdev_ctx_t *ctx, + asm330lhb_dataready_pulsed_t *val) { asm330lhb_counter_bdr_reg1_t counter_bdr_reg1; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, - (uint8_t *)&counter_bdr_reg1, 1); + (uint8_t *)&counter_bdr_reg1, 1); switch (counter_bdr_reg1.dataready_pulsed) { case ASM330LHB_DRDY_LATCHED: @@ -2041,7 +2055,7 @@ int32_t asm330lhb_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t asm330lhb_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_WHO_AM_I, buff, 1); @@ -2056,7 +2070,7 @@ int32_t asm330lhb_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2078,7 +2092,7 @@ int32_t asm330lhb_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2098,7 +2112,7 @@ int32_t asm330lhb_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2121,7 +2135,7 @@ int32_t asm330lhb_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2140,7 +2154,7 @@ int32_t asm330lhb_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2162,7 +2176,7 @@ int32_t asm330lhb_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2183,8 +2197,8 @@ int32_t asm330lhb_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_self_test_set(stmdev_ctx_t *ctx, - asm330lhb_st_xl_t val) +int32_t asm330lhb_xl_self_test_set(const stmdev_ctx_t *ctx, + asm330lhb_st_xl_t val) { asm330lhb_ctrl5_c_t ctrl5_c; int32_t ret; @@ -2206,8 +2220,8 @@ int32_t asm330lhb_xl_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_self_test_get(stmdev_ctx_t *ctx, - asm330lhb_st_xl_t *val) +int32_t asm330lhb_xl_self_test_get(const stmdev_ctx_t *ctx, + asm330lhb_st_xl_t *val) { asm330lhb_ctrl5_c_t ctrl5_c; int32_t ret; @@ -2240,8 +2254,8 @@ int32_t asm330lhb_xl_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_gy_self_test_set(stmdev_ctx_t *ctx, - asm330lhb_st_g_t val) +int32_t asm330lhb_gy_self_test_set(const stmdev_ctx_t *ctx, + asm330lhb_st_g_t val) { asm330lhb_ctrl5_c_t ctrl5_c; int32_t ret; @@ -2263,8 +2277,8 @@ int32_t asm330lhb_gy_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_gy_self_test_get(stmdev_ctx_t *ctx, - asm330lhb_st_g_t *val) +int32_t asm330lhb_gy_self_test_get(const stmdev_ctx_t *ctx, + asm330lhb_st_g_t *val) { asm330lhb_ctrl5_c_t ctrl5_c; int32_t ret; @@ -2310,7 +2324,7 @@ int32_t asm330lhb_gy_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_ctrl1_xl_t ctrl1_xl; int32_t ret; @@ -2320,7 +2334,7 @@ int32_t asm330lhb_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val) { ctrl1_xl.lpf2_xl_en = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL1_XL, - (uint8_t *)&ctrl1_xl, 1); + (uint8_t *)&ctrl1_xl, 1); } return ret; } @@ -2333,7 +2347,7 @@ int32_t asm330lhb_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_ctrl1_xl_t ctrl1_xl; int32_t ret; @@ -2353,7 +2367,7 @@ int32_t asm330lhb_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_ctrl4_c_t ctrl4_c; int32_t ret; @@ -2376,7 +2390,7 @@ int32_t asm330lhb_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_ctrl4_c_t ctrl4_c; int32_t ret; @@ -2396,7 +2410,7 @@ int32_t asm330lhb_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_ctrl4_c_t ctrl4_c; int32_t ret; @@ -2419,8 +2433,8 @@ int32_t asm330lhb_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_filter_settling_mask_get(stmdev_ctx_t *ctx, - uint8_t *val) +int32_t asm330lhb_filter_settling_mask_get(const stmdev_ctx_t *ctx, + uint8_t *val) { asm330lhb_ctrl4_c_t ctrl4_c; int32_t ret; @@ -2439,8 +2453,8 @@ int32_t asm330lhb_filter_settling_mask_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, - asm330lhb_ftype_t val) +int32_t asm330lhb_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, + asm330lhb_ftype_t val) { asm330lhb_ctrl6_c_t ctrl6_c; int32_t ret; @@ -2462,8 +2476,8 @@ int32_t asm330lhb_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, - asm330lhb_ftype_t *val) +int32_t asm330lhb_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, + asm330lhb_ftype_t *val) { asm330lhb_ctrl6_c_t ctrl6_c; int32_t ret; @@ -2511,7 +2525,7 @@ int32_t asm330lhb_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -2521,7 +2535,7 @@ int32_t asm330lhb_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val) { ctrl8_xl.low_pass_on_6d = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL8_XL, - (uint8_t *)&ctrl8_xl, 1); + (uint8_t *)&ctrl8_xl, 1); } return ret; } @@ -2534,7 +2548,7 @@ int32_t asm330lhb_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -2554,8 +2568,8 @@ int32_t asm330lhb_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, - asm330lhb_hp_slope_xl_en_t val) +int32_t asm330lhb_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, + asm330lhb_hp_slope_xl_en_t val) { asm330lhb_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -2567,7 +2581,7 @@ int32_t asm330lhb_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, ctrl8_xl.hp_ref_mode_xl = (((uint8_t)val & 0x20U) >> 5); ctrl8_xl.hpcf_xl = (uint8_t)val & 0x07U; ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL8_XL, - (uint8_t *)&ctrl8_xl, 1); + (uint8_t *)&ctrl8_xl, 1); } return ret; } @@ -2581,8 +2595,8 @@ int32_t asm330lhb_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, - asm330lhb_hp_slope_xl_en_t *val) +int32_t asm330lhb_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, + asm330lhb_hp_slope_xl_en_t *val) { asm330lhb_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -2677,7 +2691,7 @@ int32_t asm330lhb_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -2687,7 +2701,7 @@ int32_t asm330lhb_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) { ctrl8_xl.fastsettl_mode_xl = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL8_XL, - (uint8_t *)&ctrl8_xl, 1); + (uint8_t *)&ctrl8_xl, 1); } return ret; } @@ -2702,7 +2716,7 @@ int32_t asm330lhb_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -2722,8 +2736,8 @@ int32_t asm330lhb_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_hp_path_internal_set(stmdev_ctx_t *ctx, - asm330lhb_slope_fds_t val) +int32_t asm330lhb_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, + asm330lhb_slope_fds_t val) { asm330lhb_int_cfg0_t int_cfg0; int32_t ret; @@ -2733,7 +2747,7 @@ int32_t asm330lhb_xl_hp_path_internal_set(stmdev_ctx_t *ctx, { int_cfg0.slope_fds = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_INT_CFG0, - (uint8_t *)&int_cfg0, 1); + (uint8_t *)&int_cfg0, 1); } return ret; } @@ -2747,8 +2761,8 @@ int32_t asm330lhb_xl_hp_path_internal_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_hp_path_internal_get(stmdev_ctx_t *ctx, - asm330lhb_slope_fds_t *val) +int32_t asm330lhb_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, + asm330lhb_slope_fds_t *val) { asm330lhb_int_cfg0_t int_cfg0; int32_t ret; @@ -2778,8 +2792,8 @@ int32_t asm330lhb_xl_hp_path_internal_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_gy_hp_path_internal_set(stmdev_ctx_t *ctx, - asm330lhb_hpm_g_t val) +int32_t asm330lhb_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, + asm330lhb_hpm_g_t val) { asm330lhb_ctrl7_g_t ctrl7_g; int32_t ret; @@ -2803,8 +2817,8 @@ int32_t asm330lhb_gy_hp_path_internal_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_gy_hp_path_internal_get(stmdev_ctx_t *ctx, - asm330lhb_hpm_g_t *val) +int32_t asm330lhb_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, + asm330lhb_hpm_g_t *val) { asm330lhb_ctrl7_g_t ctrl7_g; int32_t ret; @@ -2856,8 +2870,8 @@ int32_t asm330lhb_gy_hp_path_internal_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_sdo_sa0_mode_set(stmdev_ctx_t *ctx, - asm330lhb_sdo_pu_en_t val) +int32_t asm330lhb_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, + asm330lhb_sdo_pu_en_t val) { asm330lhb_pin_ctrl_t pin_ctrl; int32_t ret; @@ -2879,8 +2893,8 @@ int32_t asm330lhb_sdo_sa0_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_sdo_sa0_mode_get(stmdev_ctx_t *ctx, - asm330lhb_sdo_pu_en_t *val) +int32_t asm330lhb_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, + asm330lhb_sdo_pu_en_t *val) { asm330lhb_pin_ctrl_t pin_ctrl; int32_t ret; @@ -2910,8 +2924,8 @@ int32_t asm330lhb_sdo_sa0_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_int1_mode_set(stmdev_ctx_t *ctx, - asm330lhb_pd_dis_int1_t val) +int32_t asm330lhb_int1_mode_set(const stmdev_ctx_t *ctx, + asm330lhb_pd_dis_int1_t val) { asm330lhb_i3c_bus_avb_t i3c_bus_avb; int32_t ret; @@ -2921,7 +2935,7 @@ int32_t asm330lhb_int1_mode_set(stmdev_ctx_t *ctx, { i3c_bus_avb.pd_dis_int1 = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_I3C_BUS_AVB, - (uint8_t *)&i3c_bus_avb, 1); + (uint8_t *)&i3c_bus_avb, 1); } return ret; } @@ -2934,8 +2948,8 @@ int32_t asm330lhb_int1_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_int1_mode_get(stmdev_ctx_t *ctx, - asm330lhb_pd_dis_int1_t *val) +int32_t asm330lhb_int1_mode_get(const stmdev_ctx_t *ctx, + asm330lhb_pd_dis_int1_t *val) { asm330lhb_i3c_bus_avb_t i3c_bus_avb; int32_t ret; @@ -2965,7 +2979,7 @@ int32_t asm330lhb_int1_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_spi_mode_set(stmdev_ctx_t *ctx, asm330lhb_sim_t val) +int32_t asm330lhb_spi_mode_set(const stmdev_ctx_t *ctx, asm330lhb_sim_t val) { asm330lhb_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2987,7 +3001,7 @@ int32_t asm330lhb_spi_mode_set(stmdev_ctx_t *ctx, asm330lhb_sim_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_spi_mode_get(stmdev_ctx_t *ctx, asm330lhb_sim_t *val) +int32_t asm330lhb_spi_mode_get(const stmdev_ctx_t *ctx, asm330lhb_sim_t *val) { asm330lhb_ctrl3_c_t ctrl3_c; int32_t ret; @@ -3017,8 +3031,8 @@ int32_t asm330lhb_spi_mode_get(stmdev_ctx_t *ctx, asm330lhb_sim_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_i2c_interface_set(stmdev_ctx_t *ctx, - asm330lhb_i2c_disable_t val) +int32_t asm330lhb_i2c_interface_set(const stmdev_ctx_t *ctx, + asm330lhb_i2c_disable_t val) { asm330lhb_ctrl4_c_t ctrl4_c; int32_t ret; @@ -3040,8 +3054,8 @@ int32_t asm330lhb_i2c_interface_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_i2c_interface_get(stmdev_ctx_t *ctx, - asm330lhb_i2c_disable_t *val) +int32_t asm330lhb_i2c_interface_get(const stmdev_ctx_t *ctx, + asm330lhb_i2c_disable_t *val) { asm330lhb_ctrl4_c_t ctrl4_c; int32_t ret; @@ -3071,8 +3085,8 @@ int32_t asm330lhb_i2c_interface_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_i3c_disable_set(stmdev_ctx_t *ctx, - asm330lhb_i3c_disable_t val) +int32_t asm330lhb_i3c_disable_set(const stmdev_ctx_t *ctx, + asm330lhb_i3c_disable_t val) { asm330lhb_ctrl9_xl_t ctrl9_xl; asm330lhb_i3c_bus_avb_t i3c_bus_avb; @@ -3083,18 +3097,18 @@ int32_t asm330lhb_i3c_disable_set(stmdev_ctx_t *ctx, { ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7; ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL9_XL, - (uint8_t *)&ctrl9_xl, 1); + (uint8_t *)&ctrl9_xl, 1); } if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_I3C_BUS_AVB, - (uint8_t *)&i3c_bus_avb, 1); + (uint8_t *)&i3c_bus_avb, 1); } if (ret == 0) { i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U; ret = asm330lhb_write_reg(ctx, ASM330LHB_I3C_BUS_AVB, - (uint8_t *)&i3c_bus_avb, 1); + (uint8_t *)&i3c_bus_avb, 1); } return ret; } @@ -3107,8 +3121,8 @@ int32_t asm330lhb_i3c_disable_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_i3c_disable_get(stmdev_ctx_t *ctx, - asm330lhb_i3c_disable_t *val) +int32_t asm330lhb_i3c_disable_get(const stmdev_ctx_t *ctx, + asm330lhb_i3c_disable_t *val) { asm330lhb_ctrl9_xl_t ctrl9_xl; asm330lhb_i3c_bus_avb_t i3c_bus_avb; @@ -3118,7 +3132,7 @@ int32_t asm330lhb_i3c_disable_get(stmdev_ctx_t *ctx, if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_I3C_BUS_AVB, - (uint8_t *)&i3c_bus_avb, 1); + (uint8_t *)&i3c_bus_avb, 1); } switch ((ctrl9_xl.i3c_disable << 7) + i3c_bus_avb.i3c_bus_avb_sel) { @@ -3166,8 +3180,8 @@ int32_t asm330lhb_i3c_disable_get(stmdev_ctx_t *ctx, * FSM_INT1_B * */ -int32_t asm330lhb_pin_int1_route_set(stmdev_ctx_t *ctx, - asm330lhb_pin_int1_route_t *val) +int32_t asm330lhb_pin_int1_route_set(const stmdev_ctx_t *ctx, + asm330lhb_pin_int1_route_t *val) { asm330lhb_pin_int2_route_t pin_int2_route; asm330lhb_int_cfg1_t int_cfg1; @@ -3177,22 +3191,22 @@ int32_t asm330lhb_pin_int1_route_set(stmdev_ctx_t *ctx, if (ret == 0) { ret = asm330lhb_write_reg(ctx, ASM330LHB_MLC_INT1, - (uint8_t *)&val->mlc_int1, 1); + (uint8_t *)&val->mlc_int1, 1); } if (ret == 0) { ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_INT1, - (uint8_t *)&val->emb_func_int1, 1); + (uint8_t *)&val->emb_func_int1, 1); } if (ret == 0) { ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_INT1_A, - (uint8_t *)&val->fsm_int1_a, 1); + (uint8_t *)&val->fsm_int1_a, 1); } if (ret == 0) { ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_INT1_B, - (uint8_t *)&val->fsm_int1_b, 1); + (uint8_t *)&val->fsm_int1_b, 1); } if (ret == 0) { @@ -3234,7 +3248,7 @@ int32_t asm330lhb_pin_int1_route_set(stmdev_ctx_t *ctx, val->md1_cfg.int1_emb_func = PROPERTY_DISABLE; } ret = asm330lhb_write_reg(ctx, ASM330LHB_INT1_CTRL, - (uint8_t *)&val->int1_ctrl, 1); + (uint8_t *)&val->int1_ctrl, 1); } if (ret == 0) { @@ -3294,8 +3308,8 @@ int32_t asm330lhb_pin_int1_route_set(stmdev_ctx_t *ctx, * EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B * */ -int32_t asm330lhb_pin_int1_route_get(stmdev_ctx_t *ctx, - asm330lhb_pin_int1_route_t *val) +int32_t asm330lhb_pin_int1_route_get(const stmdev_ctx_t *ctx, + asm330lhb_pin_int1_route_t *val) { int32_t ret; @@ -3303,22 +3317,22 @@ int32_t asm330lhb_pin_int1_route_get(stmdev_ctx_t *ctx, if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_MLC_INT1, - (uint8_t *)&val->mlc_int1, 1); + (uint8_t *)&val->mlc_int1, 1); } if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INT1, - (uint8_t *)&val->emb_func_int1, 1); + (uint8_t *)&val->emb_func_int1, 1); } if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_INT1_A, - (uint8_t *)&val->fsm_int1_a, 1); + (uint8_t *)&val->fsm_int1_a, 1); } if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_INT1_B, - (uint8_t *)&val->fsm_int1_b, 1); + (uint8_t *)&val->fsm_int1_b, 1); } if (ret == 0) { @@ -3328,7 +3342,7 @@ int32_t asm330lhb_pin_int1_route_get(stmdev_ctx_t *ctx, { ret = asm330lhb_read_reg(ctx, ASM330LHB_INT1_CTRL, - (uint8_t *)&val->int1_ctrl, 1); + (uint8_t *)&val->int1_ctrl, 1); } if (ret == 0) { @@ -3346,8 +3360,8 @@ int32_t asm330lhb_pin_int1_route_get(stmdev_ctx_t *ctx, * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B * */ -int32_t asm330lhb_pin_int2_route_set(stmdev_ctx_t *ctx, - asm330lhb_pin_int2_route_t *val) +int32_t asm330lhb_pin_int2_route_set(const stmdev_ctx_t *ctx, + asm330lhb_pin_int2_route_t *val) { asm330lhb_pin_int1_route_t pin_int1_route; asm330lhb_int_cfg1_t int_cfg1; @@ -3357,22 +3371,22 @@ int32_t asm330lhb_pin_int2_route_set(stmdev_ctx_t *ctx, if (ret == 0) { ret = asm330lhb_write_reg(ctx, ASM330LHB_MLC_INT2, - (uint8_t *)&val->mlc_int2, 1); + (uint8_t *)&val->mlc_int2, 1); } if (ret == 0) { ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_INT2, - (uint8_t *)&val->emb_func_int2, 1); + (uint8_t *)&val->emb_func_int2, 1); } if (ret == 0) { ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_INT2_A, - (uint8_t *)&val->fsm_int2_a, 1); + (uint8_t *)&val->fsm_int2_a, 1); } if (ret == 0) { ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_INT2_B, - (uint8_t *)&val->fsm_int2_b, 1); + (uint8_t *)&val->fsm_int2_b, 1); } if (ret == 0) { @@ -3414,7 +3428,7 @@ int32_t asm330lhb_pin_int2_route_set(stmdev_ctx_t *ctx, val->md2_cfg.int2_emb_func = PROPERTY_DISABLE; } ret = asm330lhb_write_reg(ctx, ASM330LHB_INT2_CTRL, - (uint8_t *)&val->int2_ctrl, 1); + (uint8_t *)&val->int2_ctrl, 1); } if (ret == 0) { @@ -3475,8 +3489,8 @@ int32_t asm330lhb_pin_int2_route_set(stmdev_ctx_t *ctx, * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B * */ -int32_t asm330lhb_pin_int2_route_get(stmdev_ctx_t *ctx, - asm330lhb_pin_int2_route_t *val) +int32_t asm330lhb_pin_int2_route_get(const stmdev_ctx_t *ctx, + asm330lhb_pin_int2_route_t *val) { int32_t ret; @@ -3484,22 +3498,22 @@ int32_t asm330lhb_pin_int2_route_get(stmdev_ctx_t *ctx, if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_MLC_INT2, - (uint8_t *)&val->mlc_int2, 1); + (uint8_t *)&val->mlc_int2, 1); } if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INT2, - (uint8_t *)&val->emb_func_int2, 1); + (uint8_t *)&val->emb_func_int2, 1); } if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_INT2_A, - (uint8_t *)&val->fsm_int2_a, 1); + (uint8_t *)&val->fsm_int2_a, 1); } if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_INT2_B, - (uint8_t *)&val->fsm_int2_b, 1); + (uint8_t *)&val->fsm_int2_b, 1); } if (ret == 0) { @@ -3509,7 +3523,7 @@ int32_t asm330lhb_pin_int2_route_get(stmdev_ctx_t *ctx, { ret = asm330lhb_read_reg(ctx, ASM330LHB_INT2_CTRL, - (uint8_t *)&val->int2_ctrl, 1); + (uint8_t *)&val->int2_ctrl, 1); } if (ret == 0) { @@ -3526,7 +3540,7 @@ int32_t asm330lhb_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_pin_mode_set(stmdev_ctx_t *ctx, asm330lhb_pp_od_t val) +int32_t asm330lhb_pin_mode_set(const stmdev_ctx_t *ctx, asm330lhb_pp_od_t val) { asm330lhb_ctrl3_c_t ctrl3_c; int32_t ret; @@ -3548,7 +3562,7 @@ int32_t asm330lhb_pin_mode_set(stmdev_ctx_t *ctx, asm330lhb_pp_od_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_pin_mode_get(stmdev_ctx_t *ctx, asm330lhb_pp_od_t *val) +int32_t asm330lhb_pin_mode_get(const stmdev_ctx_t *ctx, asm330lhb_pp_od_t *val) { asm330lhb_ctrl3_c_t ctrl3_c; int32_t ret; @@ -3578,8 +3592,8 @@ int32_t asm330lhb_pin_mode_get(stmdev_ctx_t *ctx, asm330lhb_pp_od_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_pin_polarity_set(stmdev_ctx_t *ctx, - asm330lhb_h_lactive_t val) +int32_t asm330lhb_pin_polarity_set(const stmdev_ctx_t *ctx, + asm330lhb_h_lactive_t val) { asm330lhb_ctrl3_c_t ctrl3_c; int32_t ret; @@ -3601,8 +3615,8 @@ int32_t asm330lhb_pin_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_pin_polarity_get(stmdev_ctx_t *ctx, - asm330lhb_h_lactive_t *val) +int32_t asm330lhb_pin_polarity_get(const stmdev_ctx_t *ctx, + asm330lhb_h_lactive_t *val) { asm330lhb_ctrl3_c_t ctrl3_c; int32_t ret; @@ -3632,7 +3646,7 @@ int32_t asm330lhb_pin_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_ctrl4_c_t ctrl4_c; int32_t ret; @@ -3654,7 +3668,7 @@ int32_t asm330lhb_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_ctrl4_c_t ctrl4_c; int32_t ret; @@ -3673,8 +3687,8 @@ int32_t asm330lhb_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_int_notification_set(stmdev_ctx_t *ctx, - asm330lhb_lir_t val) +int32_t asm330lhb_int_notification_set(const stmdev_ctx_t *ctx, + asm330lhb_lir_t val) { asm330lhb_int_cfg0_t int_cfg0; asm330lhb_page_rw_t page_rw; @@ -3686,7 +3700,7 @@ int32_t asm330lhb_int_notification_set(stmdev_ctx_t *ctx, int_cfg0.lir = (uint8_t)val & 0x01U; int_cfg0.int_clr_on_read = (uint8_t)val & 0x01U; ret = asm330lhb_write_reg(ctx, ASM330LHB_INT_CFG0, - (uint8_t *)&int_cfg0, 1); + (uint8_t *)&int_cfg0, 1); } if (ret == 0) { @@ -3716,8 +3730,8 @@ int32_t asm330lhb_int_notification_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_int_notification_get(stmdev_ctx_t *ctx, - asm330lhb_lir_t *val) +int32_t asm330lhb_int_notification_get(const stmdev_ctx_t *ctx, + asm330lhb_lir_t *val) { asm330lhb_int_cfg0_t int_cfg0; asm330lhb_page_rw_t page_rw; @@ -3782,19 +3796,19 @@ int32_t asm330lhb_int_notification_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_wkup_ths_weight_set(stmdev_ctx_t *ctx, - asm330lhb_wake_ths_w_t val) +int32_t asm330lhb_wkup_ths_weight_set(const stmdev_ctx_t *ctx, + asm330lhb_wake_ths_w_t val) { asm330lhb_wake_up_dur_t wake_up_dur; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR, - (uint8_t *)&wake_up_dur, 1); + (uint8_t *)&wake_up_dur, 1); if (ret == 0) { wake_up_dur.wake_ths_w = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_WAKE_UP_DUR, - (uint8_t *)&wake_up_dur, 1); + (uint8_t *)&wake_up_dur, 1); } return ret; } @@ -3809,14 +3823,14 @@ int32_t asm330lhb_wkup_ths_weight_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_wkup_ths_weight_get(stmdev_ctx_t *ctx, - asm330lhb_wake_ths_w_t *val) +int32_t asm330lhb_wkup_ths_weight_get(const stmdev_ctx_t *ctx, + asm330lhb_wake_ths_w_t *val) { asm330lhb_wake_up_dur_t wake_up_dur; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR, - (uint8_t *)&wake_up_dur, 1); + (uint8_t *)&wake_up_dur, 1); switch (wake_up_dur.wake_ths_w) { @@ -3842,18 +3856,18 @@ int32_t asm330lhb_wkup_ths_weight_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_wake_up_ths_t wake_up_ths; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_THS, - (uint8_t *)&wake_up_ths, 1); + (uint8_t *)&wake_up_ths, 1); if (ret == 0) { wake_up_ths.wk_ths = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_WAKE_UP_THS, - (uint8_t *)&wake_up_ths, 1); + (uint8_t *)&wake_up_ths, 1); } return ret; } @@ -3867,13 +3881,13 @@ int32_t asm330lhb_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_wake_up_ths_t wake_up_ths; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_THS, - (uint8_t *)&wake_up_ths, 1); + (uint8_t *)&wake_up_ths, 1); *val = wake_up_ths.wk_ths; return ret; @@ -3887,18 +3901,18 @@ int32_t asm330lhb_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_wake_up_ths_t wake_up_ths; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_THS, - (uint8_t *)&wake_up_ths, 1); + (uint8_t *)&wake_up_ths, 1); if (ret == 0) { wake_up_ths.usr_off_on_wu = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_WAKE_UP_THS, - (uint8_t *)&wake_up_ths, 1); + (uint8_t *)&wake_up_ths, 1); } return ret; } @@ -3911,14 +3925,14 @@ int32_t asm330lhb_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, - uint8_t *val) +int32_t asm330lhb_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, + uint8_t *val) { asm330lhb_wake_up_ths_t wake_up_ths; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_THS, - (uint8_t *)&wake_up_ths, 1); + (uint8_t *)&wake_up_ths, 1); *val = wake_up_ths.usr_off_on_wu; return ret; @@ -3932,18 +3946,18 @@ int32_t asm330lhb_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_wake_up_dur_t wake_up_dur; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR, - (uint8_t *)&wake_up_dur, 1); + (uint8_t *)&wake_up_dur, 1); if (ret == 0) { wake_up_dur.wake_dur = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_WAKE_UP_DUR, - (uint8_t *)&wake_up_dur, 1); + (uint8_t *)&wake_up_dur, 1); } return ret; } @@ -3956,13 +3970,13 @@ int32_t asm330lhb_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_wake_up_dur_t wake_up_dur; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR, - (uint8_t *)&wake_up_dur, 1); + (uint8_t *)&wake_up_dur, 1); *val = wake_up_dur.wake_dur; return ret; @@ -3989,7 +4003,7 @@ int32_t asm330lhb_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_ctrl4_c_t ctrl4_c; int32_t ret; @@ -4011,7 +4025,7 @@ int32_t asm330lhb_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_ctrl4_c_t ctrl4_c; int32_t ret; @@ -4032,8 +4046,8 @@ int32_t asm330lhb_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_act_pin_notification_set(stmdev_ctx_t *ctx, - asm330lhb_sleep_status_on_int_t val) +int32_t asm330lhb_act_pin_notification_set(const stmdev_ctx_t *ctx, + asm330lhb_sleep_status_on_int_t val) { asm330lhb_int_cfg0_t int_cfg0; int32_t ret; @@ -4043,7 +4057,7 @@ int32_t asm330lhb_act_pin_notification_set(stmdev_ctx_t *ctx, { int_cfg0. sleep_status_on_int = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_INT_CFG0, - (uint8_t *)&int_cfg0, 1); + (uint8_t *)&int_cfg0, 1); } return ret; } @@ -4058,8 +4072,8 @@ int32_t asm330lhb_act_pin_notification_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_act_pin_notification_get(stmdev_ctx_t *ctx, - asm330lhb_sleep_status_on_int_t *val) +int32_t asm330lhb_act_pin_notification_get(const stmdev_ctx_t *ctx, + asm330lhb_sleep_status_on_int_t *val) { asm330lhb_int_cfg0_t int_cfg0; int32_t ret; @@ -4088,7 +4102,7 @@ int32_t asm330lhb_act_pin_notification_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_act_mode_set(stmdev_ctx_t *ctx, asm330lhb_inact_en_t val) +int32_t asm330lhb_act_mode_set(const stmdev_ctx_t *ctx, asm330lhb_inact_en_t val) { asm330lhb_int_cfg1_t int_cfg1; int32_t ret; @@ -4110,8 +4124,8 @@ int32_t asm330lhb_act_mode_set(stmdev_ctx_t *ctx, asm330lhb_inact_en_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_act_mode_get(stmdev_ctx_t *ctx, - asm330lhb_inact_en_t *val) +int32_t asm330lhb_act_mode_get(const stmdev_ctx_t *ctx, + asm330lhb_inact_en_t *val) { asm330lhb_int_cfg1_t int_cfg1; int32_t ret; @@ -4147,18 +4161,18 @@ int32_t asm330lhb_act_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_wake_up_dur_t wake_up_dur; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR, - (uint8_t *)&wake_up_dur, 1); + (uint8_t *)&wake_up_dur, 1); if (ret == 0) { wake_up_dur.sleep_dur = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_WAKE_UP_DUR, - (uint8_t *)&wake_up_dur, 1); + (uint8_t *)&wake_up_dur, 1); } return ret; } @@ -4171,13 +4185,13 @@ int32_t asm330lhb_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_wake_up_dur_t wake_up_dur; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR, - (uint8_t *)&wake_up_dur, 1); + (uint8_t *)&wake_up_dur, 1); *val = wake_up_dur.sleep_dur; return ret; @@ -4204,19 +4218,19 @@ int32_t asm330lhb_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_6d_threshold_set(stmdev_ctx_t *ctx, - asm330lhb_sixd_ths_t val) +int32_t asm330lhb_6d_threshold_set(const stmdev_ctx_t *ctx, + asm330lhb_sixd_ths_t val) { asm330lhb_ths_6d_t ths_6d; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_THS_6D, - (uint8_t *)&ths_6d, 1); + (uint8_t *)&ths_6d, 1); if (ret == 0) { ths_6d.sixd_ths = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_THS_6D, - (uint8_t *)&ths_6d, 1); + (uint8_t *)&ths_6d, 1); } return ret; } @@ -4229,14 +4243,14 @@ int32_t asm330lhb_6d_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_6d_threshold_get(stmdev_ctx_t *ctx, - asm330lhb_sixd_ths_t *val) +int32_t asm330lhb_6d_threshold_get(const stmdev_ctx_t *ctx, + asm330lhb_sixd_ths_t *val) { asm330lhb_ths_6d_t ths_6d; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_THS_6D, - (uint8_t *)&ths_6d, 1); + (uint8_t *)&ths_6d, 1); switch (ths_6d.sixd_ths) { @@ -4267,18 +4281,18 @@ int32_t asm330lhb_6d_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_ths_6d_t ths_6d; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_THS_6D, - (uint8_t *)&ths_6d, 1); + (uint8_t *)&ths_6d, 1); if (ret == 0) { ths_6d.d4d_en = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_THS_6D, - (uint8_t *)&ths_6d, 1); + (uint8_t *)&ths_6d, 1); } return ret; } @@ -4291,13 +4305,13 @@ int32_t asm330lhb_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_ths_6d_t ths_6d; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_THS_6D, - (uint8_t *)&ths_6d, 1); + (uint8_t *)&ths_6d, 1); *val = ths_6d.d4d_en; return ret; @@ -4324,8 +4338,8 @@ int32_t asm330lhb_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_ff_threshold_set(stmdev_ctx_t *ctx, - asm330lhb_ff_ths_t val) +int32_t asm330lhb_ff_threshold_set(const stmdev_ctx_t *ctx, + asm330lhb_ff_ths_t val) { asm330lhb_free_fall_t free_fall; int32_t ret; @@ -4335,7 +4349,7 @@ int32_t asm330lhb_ff_threshold_set(stmdev_ctx_t *ctx, { free_fall.ff_ths = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_FREE_FALL, - (uint8_t *)&free_fall, 1); + (uint8_t *)&free_fall, 1); } return ret; } @@ -4348,8 +4362,8 @@ int32_t asm330lhb_ff_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_ff_threshold_get(stmdev_ctx_t *ctx, - asm330lhb_ff_ths_t *val) +int32_t asm330lhb_ff_threshold_get(const stmdev_ctx_t *ctx, + asm330lhb_ff_ths_t *val) { asm330lhb_free_fall_t free_fall; int32_t ret; @@ -4397,30 +4411,30 @@ int32_t asm330lhb_ff_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_wake_up_dur_t wake_up_dur; asm330lhb_free_fall_t free_fall; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR, - (uint8_t *)&wake_up_dur, 1); + (uint8_t *)&wake_up_dur, 1); if (ret == 0) { wake_up_dur.ff_dur = (val & 0x20U) >> 5; ret = asm330lhb_write_reg(ctx, ASM330LHB_WAKE_UP_DUR, - (uint8_t *)&wake_up_dur, 1); + (uint8_t *)&wake_up_dur, 1); } if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_FREE_FALL, - (uint8_t *)&free_fall, 1); + (uint8_t *)&free_fall, 1); } if (ret == 0) { free_fall.ff_dur = val & 0x1FU; ret = asm330lhb_write_reg(ctx, ASM330LHB_FREE_FALL, - (uint8_t *)&free_fall, 1); + (uint8_t *)&free_fall, 1); } return ret; } @@ -4433,19 +4447,19 @@ int32_t asm330lhb_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_wake_up_dur_t wake_up_dur; asm330lhb_free_fall_t free_fall; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR, - (uint8_t *)&wake_up_dur, 1); + (uint8_t *)&wake_up_dur, 1); if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_FREE_FALL, - (uint8_t *)&free_fall, 1); + (uint8_t *)&free_fall, 1); } *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; @@ -4473,25 +4487,25 @@ int32_t asm330lhb_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t asm330lhb_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val) { asm330lhb_fifo_ctrl1_t fifo_ctrl1; asm330lhb_fifo_ctrl2_t fifo_ctrl2; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2, - (uint8_t *)&fifo_ctrl2, 1); + (uint8_t *)&fifo_ctrl2, 1); if (ret == 0) { fifo_ctrl2.wtm = (uint8_t)((val / 256U) & 0x01U); ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL2, - (uint8_t *)&fifo_ctrl2, 1); + (uint8_t *)&fifo_ctrl2, 1); } if (ret == 0) { fifo_ctrl1.wtm = (uint8_t)(val - (fifo_ctrl2.wtm * 256U)); ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL1, - (uint8_t *)&fifo_ctrl1, 1); + (uint8_t *)&fifo_ctrl1, 1); } return ret; @@ -4505,18 +4519,18 @@ int32_t asm330lhb_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t asm330lhb_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) { asm330lhb_fifo_ctrl1_t fifo_ctrl1; asm330lhb_fifo_ctrl2_t fifo_ctrl2; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2, - (uint8_t *)&fifo_ctrl2, 1); + (uint8_t *)&fifo_ctrl2, 1); if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL1, - (uint8_t *)&fifo_ctrl1, 1); + (uint8_t *)&fifo_ctrl1, 1); } *val = fifo_ctrl2.wtm; *val = (*val * 256U) + fifo_ctrl1.wtm; @@ -4531,19 +4545,19 @@ int32_t asm330lhb_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, - uint8_t val) +int32_t asm330lhb_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, + uint8_t val) { asm330lhb_fifo_ctrl2_t fifo_ctrl2; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2, - (uint8_t *)&fifo_ctrl2, 1); + (uint8_t *)&fifo_ctrl2, 1); if (ret == 0) { fifo_ctrl2.odrchg_en = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL2, - (uint8_t *)&fifo_ctrl2, 1); + (uint8_t *)&fifo_ctrl2, 1); } return ret; @@ -4557,14 +4571,14 @@ int32_t asm330lhb_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, - uint8_t *val) +int32_t asm330lhb_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, + uint8_t *val) { asm330lhb_fifo_ctrl2_t fifo_ctrl2; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2, - (uint8_t *)&fifo_ctrl2, 1); + (uint8_t *)&fifo_ctrl2, 1); *val = fifo_ctrl2.odrchg_en; return ret; @@ -4579,18 +4593,18 @@ int32_t asm330lhb_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_fifo_ctrl2_t fifo_ctrl2; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2, - (uint8_t *)&fifo_ctrl2, 1); + (uint8_t *)&fifo_ctrl2, 1); if (ret == 0) { fifo_ctrl2.stop_on_wtm = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL2, - (uint8_t *)&fifo_ctrl2, 1); + (uint8_t *)&fifo_ctrl2, 1); } return ret; } @@ -4604,13 +4618,13 @@ int32_t asm330lhb_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_fifo_ctrl2_t fifo_ctrl2; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2, - (uint8_t *)&fifo_ctrl2, 1); + (uint8_t *)&fifo_ctrl2, 1); *val = fifo_ctrl2.stop_on_wtm; return ret; @@ -4625,19 +4639,19 @@ int32_t asm330lhb_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fifo_xl_batch_set(stmdev_ctx_t *ctx, - asm330lhb_bdr_xl_t val) +int32_t asm330lhb_fifo_xl_batch_set(const stmdev_ctx_t *ctx, + asm330lhb_bdr_xl_t val) { asm330lhb_fifo_ctrl3_t fifo_ctrl3; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL3, - (uint8_t *)&fifo_ctrl3, 1); + (uint8_t *)&fifo_ctrl3, 1); if (ret == 0) { fifo_ctrl3.bdr_xl = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL3, - (uint8_t *)&fifo_ctrl3, 1); + (uint8_t *)&fifo_ctrl3, 1); } return ret; } @@ -4651,14 +4665,14 @@ int32_t asm330lhb_fifo_xl_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fifo_xl_batch_get(stmdev_ctx_t *ctx, - asm330lhb_bdr_xl_t *val) +int32_t asm330lhb_fifo_xl_batch_get(const stmdev_ctx_t *ctx, + asm330lhb_bdr_xl_t *val) { asm330lhb_fifo_ctrl3_t fifo_ctrl3; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL3, - (uint8_t *)&fifo_ctrl3, 1); + (uint8_t *)&fifo_ctrl3, 1); switch (fifo_ctrl3.bdr_xl) { @@ -4708,19 +4722,19 @@ int32_t asm330lhb_fifo_xl_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fifo_gy_batch_set(stmdev_ctx_t *ctx, - asm330lhb_bdr_gy_t val) +int32_t asm330lhb_fifo_gy_batch_set(const stmdev_ctx_t *ctx, + asm330lhb_bdr_gy_t val) { asm330lhb_fifo_ctrl3_t fifo_ctrl3; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL3, - (uint8_t *)&fifo_ctrl3, 1); + (uint8_t *)&fifo_ctrl3, 1); if (ret == 0) { fifo_ctrl3.bdr_gy = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL3, - (uint8_t *)&fifo_ctrl3, 1); + (uint8_t *)&fifo_ctrl3, 1); } return ret; } @@ -4734,14 +4748,14 @@ int32_t asm330lhb_fifo_gy_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fifo_gy_batch_get(stmdev_ctx_t *ctx, - asm330lhb_bdr_gy_t *val) +int32_t asm330lhb_fifo_gy_batch_get(const stmdev_ctx_t *ctx, + asm330lhb_bdr_gy_t *val) { asm330lhb_fifo_ctrl3_t fifo_ctrl3; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL3, - (uint8_t *)&fifo_ctrl3, 1); + (uint8_t *)&fifo_ctrl3, 1); switch (fifo_ctrl3.bdr_gy) { @@ -4790,19 +4804,19 @@ int32_t asm330lhb_fifo_gy_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fifo_mode_set(stmdev_ctx_t *ctx, - asm330lhb_fifo_mode_t val) +int32_t asm330lhb_fifo_mode_set(const stmdev_ctx_t *ctx, + asm330lhb_fifo_mode_t val) { asm330lhb_fifo_ctrl4_t fifo_ctrl4; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL4, - (uint8_t *)&fifo_ctrl4, 1); + (uint8_t *)&fifo_ctrl4, 1); if (ret == 0) { fifo_ctrl4.fifo_mode = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL4, - (uint8_t *)&fifo_ctrl4, 1); + (uint8_t *)&fifo_ctrl4, 1); } return ret; } @@ -4815,14 +4829,14 @@ int32_t asm330lhb_fifo_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fifo_mode_get(stmdev_ctx_t *ctx, - asm330lhb_fifo_mode_t *val) +int32_t asm330lhb_fifo_mode_get(const stmdev_ctx_t *ctx, + asm330lhb_fifo_mode_t *val) { asm330lhb_fifo_ctrl4_t fifo_ctrl4; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL4, - (uint8_t *)&fifo_ctrl4, 1); + (uint8_t *)&fifo_ctrl4, 1); switch (fifo_ctrl4.fifo_mode) { @@ -4860,19 +4874,19 @@ int32_t asm330lhb_fifo_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fifo_temp_batch_set(stmdev_ctx_t *ctx, - asm330lhb_odr_t_batch_t val) +int32_t asm330lhb_fifo_temp_batch_set(const stmdev_ctx_t *ctx, + asm330lhb_odr_t_batch_t val) { asm330lhb_fifo_ctrl4_t fifo_ctrl4; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL4, - (uint8_t *)&fifo_ctrl4, 1); + (uint8_t *)&fifo_ctrl4, 1); if (ret == 0) { fifo_ctrl4.odr_t_batch = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL4, - (uint8_t *)&fifo_ctrl4, 1); + (uint8_t *)&fifo_ctrl4, 1); } return ret; } @@ -4886,14 +4900,14 @@ int32_t asm330lhb_fifo_temp_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fifo_temp_batch_get(stmdev_ctx_t *ctx, - asm330lhb_odr_t_batch_t *val) +int32_t asm330lhb_fifo_temp_batch_get(const stmdev_ctx_t *ctx, + asm330lhb_odr_t_batch_t *val) { asm330lhb_fifo_ctrl4_t fifo_ctrl4; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL4, - (uint8_t *)&fifo_ctrl4, 1); + (uint8_t *)&fifo_ctrl4, 1); switch (fifo_ctrl4.odr_t_batch) { @@ -4926,19 +4940,19 @@ int32_t asm330lhb_fifo_temp_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, - asm330lhb_dec_ts_batch_t val) +int32_t asm330lhb_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, + asm330lhb_dec_ts_batch_t val) { asm330lhb_fifo_ctrl4_t fifo_ctrl4; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL4, - (uint8_t *)&fifo_ctrl4, 1); + (uint8_t *)&fifo_ctrl4, 1); if (ret == 0) { fifo_ctrl4.dec_ts_batch = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL4, - (uint8_t *)&fifo_ctrl4, 1); + (uint8_t *)&fifo_ctrl4, 1); } return ret; } @@ -4954,14 +4968,14 @@ int32_t asm330lhb_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, - asm330lhb_dec_ts_batch_t *val) +int32_t asm330lhb_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, + asm330lhb_dec_ts_batch_t *val) { asm330lhb_fifo_ctrl4_t fifo_ctrl4; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL4, - (uint8_t *)&fifo_ctrl4, 1); + (uint8_t *)&fifo_ctrl4, 1); switch (fifo_ctrl4.dec_ts_batch) { @@ -4994,19 +5008,19 @@ int32_t asm330lhb_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, - asm330lhb_trig_counter_bdr_t val) +int32_t asm330lhb_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, + asm330lhb_trig_counter_bdr_t val) { asm330lhb_counter_bdr_reg1_t counter_bdr_reg1; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, - (uint8_t *)&counter_bdr_reg1, 1); + (uint8_t *)&counter_bdr_reg1, 1); if (ret == 0) { counter_bdr_reg1.trig_counter_bdr = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, - (uint8_t *)&counter_bdr_reg1, 1); + (uint8_t *)&counter_bdr_reg1, 1); } return ret; } @@ -5021,14 +5035,14 @@ int32_t asm330lhb_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, - asm330lhb_trig_counter_bdr_t *val) +int32_t asm330lhb_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, + asm330lhb_trig_counter_bdr_t *val) { asm330lhb_counter_bdr_reg1_t counter_bdr_reg1; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, - (uint8_t *)&counter_bdr_reg1, 1); + (uint8_t *)&counter_bdr_reg1, 1); switch (counter_bdr_reg1.trig_counter_bdr) { @@ -5054,18 +5068,18 @@ int32_t asm330lhb_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_counter_bdr_reg1_t counter_bdr_reg1; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, - (uint8_t *)&counter_bdr_reg1, 1); + (uint8_t *)&counter_bdr_reg1, 1); if (ret == 0) { counter_bdr_reg1.rst_counter_bdr = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, - (uint8_t *)&counter_bdr_reg1, 1); + (uint8_t *)&counter_bdr_reg1, 1); } return ret; } @@ -5079,13 +5093,13 @@ int32_t asm330lhb_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_counter_bdr_reg1_t counter_bdr_reg1; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, - (uint8_t *)&counter_bdr_reg1, 1); + (uint8_t *)&counter_bdr_reg1, 1); *val = counter_bdr_reg1.rst_counter_bdr; return ret; @@ -5100,25 +5114,25 @@ int32_t asm330lhb_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_batch_counter_threshold_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t asm330lhb_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { asm330lhb_counter_bdr_reg2_t counter_bdr_reg1; asm330lhb_counter_bdr_reg2_t counter_bdr_reg2; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, - (uint8_t *)&counter_bdr_reg1, 1); + (uint8_t *)&counter_bdr_reg1, 1); if (ret == 0) { counter_bdr_reg1.cnt_bdr_th = (uint8_t)((val / 256U) & 0x07U); ret = asm330lhb_write_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, - (uint8_t *)&counter_bdr_reg1, 1); + (uint8_t *)&counter_bdr_reg1, 1); } if (ret == 0) { counter_bdr_reg2.cnt_bdr_th = (uint8_t)(val - (counter_bdr_reg1.cnt_bdr_th * 256U)); ret = asm330lhb_write_reg(ctx, ASM330LHB_COUNTER_BDR_REG2, - (uint8_t *)&counter_bdr_reg2, 1); + (uint8_t *)&counter_bdr_reg2, 1); } return ret; } @@ -5132,19 +5146,19 @@ int32_t asm330lhb_batch_counter_threshold_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_batch_counter_threshold_get(stmdev_ctx_t *ctx, - uint16_t *val) +int32_t asm330lhb_batch_counter_threshold_get(const stmdev_ctx_t *ctx, + uint16_t *val) { asm330lhb_counter_bdr_reg1_t counter_bdr_reg1; asm330lhb_counter_bdr_reg2_t counter_bdr_reg2; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1, - (uint8_t *)&counter_bdr_reg1, 1); + (uint8_t *)&counter_bdr_reg1, 1); if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG2, - (uint8_t *)&counter_bdr_reg2, 1); + (uint8_t *)&counter_bdr_reg2, 1); } *val = counter_bdr_reg1.cnt_bdr_th; @@ -5160,18 +5174,18 @@ int32_t asm330lhb_batch_counter_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t asm330lhb_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) { asm330lhb_fifo_status1_t fifo_status1; asm330lhb_fifo_status2_t fifo_status2; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS1, - (uint8_t *)&fifo_status1, 1); + (uint8_t *)&fifo_status1, 1); if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS2, - (uint8_t *)&fifo_status2, 1); + (uint8_t *)&fifo_status2, 1); *val = fifo_status2.diff_fifo; *val = (*val * 256U) + fifo_status1.diff_fifo; @@ -5187,8 +5201,8 @@ int32_t asm330lhb_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fifo_status_get(stmdev_ctx_t *ctx, - asm330lhb_fifo_status2_t *val) +int32_t asm330lhb_fifo_status_get(const stmdev_ctx_t *ctx, + asm330lhb_fifo_status2_t *val) { int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS2, (uint8_t *)val, 1); @@ -5203,13 +5217,13 @@ int32_t asm330lhb_fifo_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_fifo_status2_t fifo_status2; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS2, - (uint8_t *)&fifo_status2, 1); + (uint8_t *)&fifo_status2, 1); *val = fifo_status2.fifo_full_ia; return ret; @@ -5224,13 +5238,13 @@ int32_t asm330lhb_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_fifo_status2_t fifo_status2; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS2, - (uint8_t *)&fifo_status2, 1); + (uint8_t *)&fifo_status2, 1); *val = fifo_status2. fifo_ovr_ia; return ret; @@ -5244,13 +5258,13 @@ int32_t asm330lhb_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_fifo_status2_t fifo_status2; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS2, - (uint8_t *)&fifo_status2, 1); + (uint8_t *)&fifo_status2, 1); *val = fifo_status2.fifo_wtm_ia; return ret; @@ -5264,14 +5278,14 @@ int32_t asm330lhb_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fifo_sensor_tag_get(stmdev_ctx_t *ctx, - asm330lhb_fifo_tag_t *val) +int32_t asm330lhb_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, + asm330lhb_fifo_tag_t *val) { asm330lhb_fifo_data_out_tag_t fifo_data_out_tag; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_DATA_OUT_TAG, - (uint8_t *)&fifo_data_out_tag, 1); + (uint8_t *)&fifo_data_out_tag, 1); switch (fifo_data_out_tag.tag_sensor) { @@ -5318,7 +5332,7 @@ int32_t asm330lhb_fifo_sensor_tag_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_den_mode_set(stmdev_ctx_t *ctx, asm330lhb_den_mode_t val) +int32_t asm330lhb_den_mode_set(const stmdev_ctx_t *ctx, asm330lhb_den_mode_t val) { asm330lhb_ctrl6_c_t ctrl6_c; int32_t ret; @@ -5340,8 +5354,8 @@ int32_t asm330lhb_den_mode_set(stmdev_ctx_t *ctx, asm330lhb_den_mode_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_den_mode_get(stmdev_ctx_t *ctx, - asm330lhb_den_mode_t *val) +int32_t asm330lhb_den_mode_get(const stmdev_ctx_t *ctx, + asm330lhb_den_mode_t *val) { asm330lhb_ctrl6_c_t ctrl6_c; int32_t ret; @@ -5380,8 +5394,8 @@ int32_t asm330lhb_den_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_den_polarity_set(stmdev_ctx_t *ctx, - asm330lhb_den_lh_t val) +int32_t asm330lhb_den_polarity_set(const stmdev_ctx_t *ctx, + asm330lhb_den_lh_t val) { asm330lhb_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -5391,7 +5405,7 @@ int32_t asm330lhb_den_polarity_set(stmdev_ctx_t *ctx, { ctrl9_xl.den_lh = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL9_XL, - (uint8_t *)&ctrl9_xl, 1); + (uint8_t *)&ctrl9_xl, 1); } return ret; } @@ -5404,8 +5418,8 @@ int32_t asm330lhb_den_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_den_polarity_get(stmdev_ctx_t *ctx, - asm330lhb_den_lh_t *val) +int32_t asm330lhb_den_polarity_get(const stmdev_ctx_t *ctx, + asm330lhb_den_lh_t *val) { asm330lhb_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -5435,8 +5449,8 @@ int32_t asm330lhb_den_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_den_enable_set(stmdev_ctx_t *ctx, - asm330lhb_den_xl_g_t val) +int32_t asm330lhb_den_enable_set(const stmdev_ctx_t *ctx, + asm330lhb_den_xl_g_t val) { asm330lhb_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -5446,7 +5460,7 @@ int32_t asm330lhb_den_enable_set(stmdev_ctx_t *ctx, { ctrl9_xl.den_xl_g = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL9_XL, - (uint8_t *)&ctrl9_xl, 1); + (uint8_t *)&ctrl9_xl, 1); } return ret; } @@ -5459,8 +5473,8 @@ int32_t asm330lhb_den_enable_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_den_enable_get(stmdev_ctx_t *ctx, - asm330lhb_den_xl_g_t *val) +int32_t asm330lhb_den_enable_get(const stmdev_ctx_t *ctx, + asm330lhb_den_xl_g_t *val) { asm330lhb_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -5493,7 +5507,7 @@ int32_t asm330lhb_den_enable_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -5503,7 +5517,7 @@ int32_t asm330lhb_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) { ctrl9_xl.den_z = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL9_XL, - (uint8_t *)&ctrl9_xl, 1); + (uint8_t *)&ctrl9_xl, 1); } return ret; } @@ -5516,7 +5530,7 @@ int32_t asm330lhb_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -5535,7 +5549,7 @@ int32_t asm330lhb_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -5545,7 +5559,7 @@ int32_t asm330lhb_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) { ctrl9_xl.den_y = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL9_XL, - (uint8_t *)&ctrl9_xl, 1); + (uint8_t *)&ctrl9_xl, 1); } return ret; } @@ -5558,7 +5572,7 @@ int32_t asm330lhb_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -5577,7 +5591,7 @@ int32_t asm330lhb_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -5599,7 +5613,7 @@ int32_t asm330lhb_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -5631,17 +5645,17 @@ int32_t asm330lhb_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val) * ASM330LHB_FSM_STATUS_B_MAINPAGE * */ -int32_t asm330lhb_fsm_status_get(stmdev_ctx_t *ctx, - asm330lhb_fsm_status_t *val) +int32_t asm330lhb_fsm_status_get(const stmdev_ctx_t *ctx, + asm330lhb_fsm_status_t *val) { asm330lhb_fsm_status_a_mainpage_t status_a; asm330lhb_fsm_status_b_mainpage_t status_b; int32_t ret; ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_STATUS_A_MAINPAGE, - (uint8_t *)&status_a, 1); + (uint8_t *)&status_a, 1); ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_STATUS_B_MAINPAGE, - (uint8_t *)&status_b, 1); + (uint8_t *)&status_b, 1); val->fsm1 = status_a.is_fsm1; val->fsm2 = status_a.is_fsm2; @@ -5669,7 +5683,7 @@ int32_t asm330lhb_fsm_status_get(stmdev_ctx_t *ctx, * @param uint8_t * : buffer that stores data read * */ -int32_t asm330lhb_fsm_out_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t asm330lhb_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); @@ -5693,8 +5707,8 @@ int32_t asm330lhb_fsm_out_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, - uint8_t *val) +int32_t asm330lhb_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, + uint8_t *val) { asm330lhb_emb_func_status_t emb_func_status; int32_t ret; @@ -5703,7 +5717,7 @@ int32_t asm330lhb_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_STATUS, - (uint8_t *)&emb_func_status, 1); + (uint8_t *)&emb_func_status, 1); } if (ret == 0) { @@ -5713,7 +5727,7 @@ int32_t asm330lhb_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, return ret; } -int32_t asm330lhb_emb_func_clk_dis_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_emb_func_clk_dis_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_page_sel_t page_sel; int32_t ret; @@ -5722,7 +5736,7 @@ int32_t asm330lhb_emb_func_clk_dis_set(stmdev_ctx_t *ctx, uint8_t val) if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL, - (uint8_t *)&page_sel, 1); + (uint8_t *)&page_sel, 1); page_sel.emb_func_clk_dis = val; } @@ -5732,7 +5746,7 @@ int32_t asm330lhb_emb_func_clk_dis_set(stmdev_ctx_t *ctx, uint8_t val) return ret; } -int32_t asm330lhb_emb_func_clk_dis_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_emb_func_clk_dis_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_page_sel_t page_sel; int32_t ret; @@ -5741,7 +5755,7 @@ int32_t asm330lhb_emb_func_clk_dis_get(stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL, - (uint8_t *)&page_sel, 1); + (uint8_t *)&page_sel, 1); *val = page_sel.emb_func_clk_dis; } @@ -5759,7 +5773,7 @@ int32_t asm330lhb_emb_func_clk_dis_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; asm330lhb_emb_func_en_b_t emb_func_en_b; @@ -5769,13 +5783,13 @@ int32_t asm330lhb_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val) if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); + (uint8_t *)&emb_func_en_b, 1); } if (ret == 0) { emb_func_en_b.fsm_en = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); + (uint8_t *)&emb_func_en_b, 1); } if (ret == 0) { @@ -5792,7 +5806,7 @@ int32_t asm330lhb_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; asm330lhb_emb_func_en_b_t emb_func_en_b; @@ -5801,13 +5815,13 @@ int32_t asm330lhb_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); + (uint8_t *)&emb_func_en_b, 1); } if (ret == 0) { *val = emb_func_en_b.fsm_en; ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); + (uint8_t *)&emb_func_en_b, 1); } if (ret == 0) { @@ -5824,8 +5838,8 @@ int32_t asm330lhb_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fsm_enable_set(stmdev_ctx_t *ctx, - asm330lhb_emb_fsm_enable_t *val) +int32_t asm330lhb_fsm_enable_set(const stmdev_ctx_t *ctx, + asm330lhb_emb_fsm_enable_t *val) { asm330lhb_emb_func_en_b_t emb_func_en_b; int32_t ret; @@ -5834,17 +5848,17 @@ int32_t asm330lhb_fsm_enable_set(stmdev_ctx_t *ctx, if (ret == 0) { ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_ENABLE_A, - (uint8_t *)&val->fsm_enable_a, 1); + (uint8_t *)&val->fsm_enable_a, 1); } if (ret == 0) { ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_ENABLE_B, - (uint8_t *)&val->fsm_enable_b, 1); + (uint8_t *)&val->fsm_enable_b, 1); } if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); + (uint8_t *)&emb_func_en_b, 1); } if (ret == 0) { @@ -5875,7 +5889,7 @@ int32_t asm330lhb_fsm_enable_set(stmdev_ctx_t *ctx, if (ret == 0) { ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); + (uint8_t *)&emb_func_en_b, 1); } if (ret == 0) { @@ -5892,8 +5906,8 @@ int32_t asm330lhb_fsm_enable_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fsm_enable_get(stmdev_ctx_t *ctx, - asm330lhb_emb_fsm_enable_t *val) +int32_t asm330lhb_fsm_enable_get(const stmdev_ctx_t *ctx, + asm330lhb_emb_fsm_enable_t *val) { int32_t ret; @@ -5901,12 +5915,12 @@ int32_t asm330lhb_fsm_enable_get(stmdev_ctx_t *ctx, if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_ENABLE_A, - (uint8_t *)&val->fsm_enable_a, 1); + (uint8_t *)&val->fsm_enable_a, 1); } if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_ENABLE_B, - (uint8_t *)&val->fsm_enable_b, 1); + (uint8_t *)&val->fsm_enable_b, 1); } if (ret == 0) { @@ -5924,7 +5938,7 @@ int32_t asm330lhb_fsm_enable_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t asm330lhb_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -5953,7 +5967,7 @@ int32_t asm330lhb_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t asm330lhb_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -5981,8 +5995,8 @@ int32_t asm330lhb_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_long_clr_set(stmdev_ctx_t *ctx, - asm330lhb_fsm_lc_clr_t val) +int32_t asm330lhb_long_clr_set(const stmdev_ctx_t *ctx, + asm330lhb_fsm_lc_clr_t val) { asm330lhb_fsm_long_counter_clear_t fsm_long_counter_clear; int32_t ret; @@ -5991,13 +6005,13 @@ int32_t asm330lhb_long_clr_set(stmdev_ctx_t *ctx, if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_LONG_COUNTER_CLEAR, - (uint8_t *)&fsm_long_counter_clear, 1); + (uint8_t *)&fsm_long_counter_clear, 1); } if (ret == 0) { fsm_long_counter_clear.fsm_lc_clr = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_LONG_COUNTER_CLEAR, - (uint8_t *)&fsm_long_counter_clear, 1); + (uint8_t *)&fsm_long_counter_clear, 1); } if (ret == 0) { @@ -6014,8 +6028,8 @@ int32_t asm330lhb_long_clr_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_long_clr_get(stmdev_ctx_t *ctx, - asm330lhb_fsm_lc_clr_t *val) +int32_t asm330lhb_long_clr_get(const stmdev_ctx_t *ctx, + asm330lhb_fsm_lc_clr_t *val) { asm330lhb_fsm_long_counter_clear_t fsm_long_counter_clear; int32_t ret; @@ -6025,7 +6039,7 @@ int32_t asm330lhb_long_clr_get(stmdev_ctx_t *ctx, if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_LONG_COUNTER_CLEAR, - (uint8_t *)&fsm_long_counter_clear, 1); + (uint8_t *)&fsm_long_counter_clear, 1); } if (ret == 0) { @@ -6057,8 +6071,8 @@ int32_t asm330lhb_long_clr_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fsm_data_rate_set(stmdev_ctx_t *ctx, - asm330lhb_fsm_odr_t val) +int32_t asm330lhb_fsm_data_rate_set(const stmdev_ctx_t *ctx, + asm330lhb_fsm_odr_t val) { asm330lhb_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; int32_t ret; @@ -6068,7 +6082,7 @@ int32_t asm330lhb_fsm_data_rate_set(stmdev_ctx_t *ctx, if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_B, - (uint8_t *)&emb_func_odr_cfg_b, 1); + (uint8_t *)&emb_func_odr_cfg_b, 1); } if (ret == 0) { @@ -6076,7 +6090,7 @@ int32_t asm330lhb_fsm_data_rate_set(stmdev_ctx_t *ctx, emb_func_odr_cfg_b.not_used_02 = 1; /* set default values */ emb_func_odr_cfg_b.fsm_odr = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_B, - (uint8_t *)&emb_func_odr_cfg_b, 1); + (uint8_t *)&emb_func_odr_cfg_b, 1); } if (ret == 0) { @@ -6093,8 +6107,8 @@ int32_t asm330lhb_fsm_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fsm_data_rate_get(stmdev_ctx_t *ctx, - asm330lhb_fsm_odr_t *val) +int32_t asm330lhb_fsm_data_rate_get(const stmdev_ctx_t *ctx, + asm330lhb_fsm_odr_t *val) { asm330lhb_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; int32_t ret; @@ -6104,7 +6118,7 @@ int32_t asm330lhb_fsm_data_rate_get(stmdev_ctx_t *ctx, if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_B, - (uint8_t *)&emb_func_odr_cfg_b, 1); + (uint8_t *)&emb_func_odr_cfg_b, 1); } if (ret == 0) { @@ -6139,7 +6153,7 @@ int32_t asm330lhb_fsm_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_emb_func_init_b_t emb_func_init_b; int32_t ret; @@ -6149,13 +6163,13 @@ int32_t asm330lhb_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B, - (uint8_t *)&emb_func_init_b, 1); + (uint8_t *)&emb_func_init_b, 1); } if (ret == 0) { emb_func_init_b.fsm_init = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B, - (uint8_t *)&emb_func_init_b, 1); + (uint8_t *)&emb_func_init_b, 1); } if (ret == 0) { @@ -6172,7 +6186,7 @@ int32_t asm330lhb_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_emb_func_init_b_t emb_func_init_b; int32_t ret; @@ -6181,7 +6195,7 @@ int32_t asm330lhb_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B, - (uint8_t *)&emb_func_init_b, 1); + (uint8_t *)&emb_func_init_b, 1); } if (ret == 0) { @@ -6202,7 +6216,7 @@ int32_t asm330lhb_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t asm330lhb_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -6214,7 +6228,7 @@ int32_t asm330lhb_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint16_t val) if (ret == 0) { ret = asm330lhb_ln_pg_write_byte(ctx, ASM330LHB_FSM_LC_TIMEOUT_H, - &buff[1]); + &buff[1]); } return ret; } @@ -6230,7 +6244,7 @@ int32_t asm330lhb_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t asm330lhb_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -6240,7 +6254,7 @@ int32_t asm330lhb_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint16_t *val) if (ret == 0) { ret = asm330lhb_ln_pg_read_byte(ctx, ASM330LHB_FSM_LC_TIMEOUT_H, - &buff[1]); + &buff[1]); *val = buff[1]; *val = (*val * 256U) + buff[0]; } @@ -6255,7 +6269,7 @@ int32_t asm330lhb_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t asm330lhb_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -6264,7 +6278,7 @@ int32_t asm330lhb_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t *buff) if (ret == 0) { ret = asm330lhb_ln_pg_write_byte(ctx, ASM330LHB_FSM_PROGRAMS + 0x01U, - buff); + buff); } return ret; } @@ -6277,7 +6291,7 @@ int32_t asm330lhb_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t asm330lhb_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -6295,7 +6309,7 @@ int32_t asm330lhb_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t asm330lhb_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -6320,7 +6334,7 @@ int32_t asm330lhb_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t asm330lhb_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -6357,7 +6371,7 @@ int32_t asm330lhb_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val) * in EMB_FUNC_INIT_B * */ -int32_t asm330lhb_mlc_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_mlc_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_emb_func_en_b_t reg; int32_t ret; @@ -6375,12 +6389,12 @@ int32_t asm330lhb_mlc_set(stmdev_ctx_t *ctx, uint8_t val) if ((val != PROPERTY_DISABLE) && (ret == 0)) { ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B, - (uint8_t *)®, 1); + (uint8_t *)®, 1); if (ret == 0) { reg.mlc_en = val; ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B, - (uint8_t *)®, 1); + (uint8_t *)®, 1); } } if (ret == 0) @@ -6398,7 +6412,7 @@ int32_t asm330lhb_mlc_set(stmdev_ctx_t *ctx, uint8_t val) * reg EMB_FUNC_EN_B * */ -int32_t asm330lhb_mlc_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_emb_func_en_b_t reg; int32_t ret; @@ -6423,11 +6437,11 @@ int32_t asm330lhb_mlc_get(stmdev_ctx_t *ctx, uint8_t *val) * @param val register MLC_STATUS_MAINPAGE * */ -int32_t asm330lhb_mlc_status_get(stmdev_ctx_t *ctx, - asm330lhb_mlc_status_mainpage_t *val) +int32_t asm330lhb_mlc_status_get(const stmdev_ctx_t *ctx, + asm330lhb_mlc_status_mainpage_t *val) { return asm330lhb_read_reg(ctx, ASM330LHB_MLC_STATUS_MAINPAGE, - (uint8_t *) val, 1); + (uint8_t *) val, 1); } /** @@ -6438,8 +6452,8 @@ int32_t asm330lhb_mlc_status_get(stmdev_ctx_t *ctx, * reg EMB_FUNC_ODR_CFG_C * */ -int32_t asm330lhb_mlc_data_rate_set(stmdev_ctx_t *ctx, - asm330lhb_mlc_odr_t val) +int32_t asm330lhb_mlc_data_rate_set(const stmdev_ctx_t *ctx, + asm330lhb_mlc_odr_t val) { asm330lhb_emb_func_odr_cfg_c_t reg; int32_t ret; @@ -6448,13 +6462,13 @@ int32_t asm330lhb_mlc_data_rate_set(stmdev_ctx_t *ctx, if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_C, - (uint8_t *)®, 1); + (uint8_t *)®, 1); } if (ret == 0) { reg.mlc_odr = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_C, - (uint8_t *)®, 1); + (uint8_t *)®, 1); } if (ret == 0) { @@ -6472,8 +6486,8 @@ int32_t asm330lhb_mlc_data_rate_set(stmdev_ctx_t *ctx, * reg EMB_FUNC_ODR_CFG_C * */ -int32_t asm330lhb_mlc_data_rate_get(stmdev_ctx_t *ctx, - asm330lhb_mlc_odr_t *val) +int32_t asm330lhb_mlc_data_rate_get(const stmdev_ctx_t *ctx, + asm330lhb_mlc_odr_t *val) { asm330lhb_emb_func_odr_cfg_c_t reg; int32_t ret; @@ -6482,7 +6496,7 @@ int32_t asm330lhb_mlc_data_rate_get(stmdev_ctx_t *ctx, if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_C, - (uint8_t *)®, 1); + (uint8_t *)®, 1); } if (ret == 0) { @@ -6517,7 +6531,7 @@ int32_t asm330lhb_mlc_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_mlc_init_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhb_mlc_init_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhb_emb_func_init_b_t emb_func_init_b; int32_t ret; @@ -6527,13 +6541,13 @@ int32_t asm330lhb_mlc_init_set(stmdev_ctx_t *ctx, uint8_t val) if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B, - (uint8_t *)&emb_func_init_b, 1); + (uint8_t *)&emb_func_init_b, 1); } if (ret == 0) { emb_func_init_b.mlc_init = (uint8_t)val; ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B, - (uint8_t *)&emb_func_init_b, 1); + (uint8_t *)&emb_func_init_b, 1); } ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK); @@ -6549,7 +6563,7 @@ int32_t asm330lhb_mlc_init_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhb_mlc_init_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhb_mlc_init_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhb_emb_func_init_b_t emb_func_init_b; int32_t ret; @@ -6558,7 +6572,7 @@ int32_t asm330lhb_mlc_init_get(stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B, - (uint8_t *)&emb_func_init_b, 1); + (uint8_t *)&emb_func_init_b, 1); } if (ret == 0) { @@ -6577,7 +6591,7 @@ int32_t asm330lhb_mlc_init_get(stmdev_ctx_t *ctx, uint8_t *val) * @param uint8_t * : buffer that stores data read * */ -int32_t asm330lhb_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t asm330lhb_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK); diff --git a/sensor/stmemsc/asm330lhb_STdC/driver/asm330lhb_reg.h b/sensor/stmemsc/asm330lhb_STdC/driver/asm330lhb_reg.h index 4aaa1ddd..92f57c19 100644 --- a/sensor/stmemsc/asm330lhb_STdC/driver/asm330lhb_reg.h +++ b/sensor/stmemsc/asm330lhb_STdC/driver/asm330lhb_reg.h @@ -28,6 +28,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include +#include #include /** @addtogroup ASM330LHB @@ -1846,10 +1847,10 @@ typedef union * them with a custom implementation. */ -int32_t asm330lhb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, +int32_t asm330lhb_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len); +int32_t asm330lhb_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t asm330lhb_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, - uint16_t len); float_t asm330lhb_from_fs2g_to_mg(int16_t lsb); float_t asm330lhb_from_fs4g_to_mg(int16_t lsb); @@ -1871,9 +1872,9 @@ typedef enum ASM330LHB_4g = 2, ASM330LHB_8g = 3, } asm330lhb_fs_xl_t; -int32_t asm330lhb_xl_full_scale_set(stmdev_ctx_t *ctx, asm330lhb_fs_xl_t val); -int32_t asm330lhb_xl_full_scale_get(stmdev_ctx_t *ctx, - asm330lhb_fs_xl_t *val); +int32_t asm330lhb_xl_full_scale_set(const stmdev_ctx_t *ctx, asm330lhb_fs_xl_t val); +int32_t asm330lhb_xl_full_scale_get(const stmdev_ctx_t *ctx, + asm330lhb_fs_xl_t *val); typedef enum { @@ -1888,9 +1889,9 @@ typedef enum ASM330LHB_XL_ODR_1667Hz = 8, ASM330LHB_XL_ODR_1Hz6 = 11, /* (low power only) */ } asm330lhb_odr_xl_t; -int32_t asm330lhb_xl_data_rate_set(stmdev_ctx_t *ctx, asm330lhb_odr_xl_t val); -int32_t asm330lhb_xl_data_rate_get(stmdev_ctx_t *ctx, - asm330lhb_odr_xl_t *val); +int32_t asm330lhb_xl_data_rate_set(const stmdev_ctx_t *ctx, asm330lhb_odr_xl_t val); +int32_t asm330lhb_xl_data_rate_get(const stmdev_ctx_t *ctx, + asm330lhb_odr_xl_t *val); typedef enum { @@ -1901,8 +1902,8 @@ typedef enum ASM330LHB_2000dps = 12, ASM330LHB_4000dps = 1, } asm330lhb_fs_g_t; -int32_t asm330lhb_gy_full_scale_set(stmdev_ctx_t *ctx, asm330lhb_fs_g_t val); -int32_t asm330lhb_gy_full_scale_get(stmdev_ctx_t *ctx, asm330lhb_fs_g_t *val); +int32_t asm330lhb_gy_full_scale_set(const stmdev_ctx_t *ctx, asm330lhb_fs_g_t val); +int32_t asm330lhb_gy_full_scale_get(const stmdev_ctx_t *ctx, asm330lhb_fs_g_t *val); typedef enum { @@ -1916,43 +1917,43 @@ typedef enum ASM330LHB_GY_ODR_833Hz = 7, ASM330LHB_GY_ODR_1667Hz = 8, } asm330lhb_odr_g_t; -int32_t asm330lhb_gy_data_rate_set(stmdev_ctx_t *ctx, - asm330lhb_odr_g_t val); -int32_t asm330lhb_gy_data_rate_get(stmdev_ctx_t *ctx, - asm330lhb_odr_g_t *val); +int32_t asm330lhb_gy_data_rate_set(const stmdev_ctx_t *ctx, + asm330lhb_odr_g_t val); +int32_t asm330lhb_gy_data_rate_get(const stmdev_ctx_t *ctx, + asm330lhb_odr_g_t *val); -int32_t asm330lhb_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { ASM330LHB_LSb_1mg = 0, ASM330LHB_LSb_16mg = 1, } asm330lhb_usr_off_w_t; -int32_t asm330lhb_xl_offset_weight_set(stmdev_ctx_t *ctx, - asm330lhb_usr_off_w_t val); -int32_t asm330lhb_xl_offset_weight_get(stmdev_ctx_t *ctx, - asm330lhb_usr_off_w_t *val); +int32_t asm330lhb_xl_offset_weight_set(const stmdev_ctx_t *ctx, + asm330lhb_usr_off_w_t val); +int32_t asm330lhb_xl_offset_weight_get(const stmdev_ctx_t *ctx, + asm330lhb_usr_off_w_t *val); typedef enum { ASM330LHB_HIGH_PERFORMANCE_MD = 0, ASM330LHB_LOW_NORMAL_POWER_MD = 1, } asm330lhb_xl_hm_mode_t; -int32_t asm330lhb_xl_power_mode_set(stmdev_ctx_t *ctx, - asm330lhb_xl_hm_mode_t val); -int32_t asm330lhb_xl_power_mode_get(stmdev_ctx_t *ctx, - asm330lhb_xl_hm_mode_t *val); +int32_t asm330lhb_xl_power_mode_set(const stmdev_ctx_t *ctx, + asm330lhb_xl_hm_mode_t val); +int32_t asm330lhb_xl_power_mode_get(const stmdev_ctx_t *ctx, + asm330lhb_xl_hm_mode_t *val); typedef enum { ASM330LHB_GY_HIGH_PERFORMANCE = 0, ASM330LHB_GY_NORMAL = 1, } asm330lhb_g_hm_mode_t; -int32_t asm330lhb_gy_power_mode_set(stmdev_ctx_t *ctx, - asm330lhb_g_hm_mode_t val); -int32_t asm330lhb_gy_power_mode_get(stmdev_ctx_t *ctx, - asm330lhb_g_hm_mode_t *val); +int32_t asm330lhb_gy_power_mode_set(const stmdev_ctx_t *ctx, + asm330lhb_g_hm_mode_t val); +int32_t asm330lhb_gy_power_mode_get(const stmdev_ctx_t *ctx, + asm330lhb_g_hm_mode_t *val); typedef struct { @@ -1965,38 +1966,38 @@ typedef struct asm330lhb_fsm_status_b_t fsm_status_b; asm330lhb_mlc_status_mainpage_t mlc_status; } asm330lhb_all_sources_t; -int32_t asm330lhb_all_sources_get(stmdev_ctx_t *ctx, - asm330lhb_all_sources_t *val); +int32_t asm330lhb_all_sources_get(const stmdev_ctx_t *ctx, + asm330lhb_all_sources_t *val); -int32_t asm330lhb_status_reg_get(stmdev_ctx_t *ctx, - asm330lhb_status_reg_t *val); +int32_t asm330lhb_status_reg_get(const stmdev_ctx_t *ctx, + asm330lhb_status_reg_t *val); -int32_t asm330lhb_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhb_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhb_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhb_boot_device_status_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_boot_device_status_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhb_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t asm330lhb_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhb_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhb_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t asm330lhb_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t asm330lhb_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhb_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhb_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t asm330lhb_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t asm330lhb_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhb_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhb_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t asm330lhb_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhb_timestamp_rst(stmdev_ctx_t *ctx); +int32_t asm330lhb_timestamp_rst(const stmdev_ctx_t *ctx); -int32_t asm330lhb_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhb_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); +int32_t asm330lhb_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); typedef enum { @@ -2005,60 +2006,60 @@ typedef enum ASM330LHB_ROUND_GY = 2, ASM330LHB_ROUND_GY_XL = 3, } asm330lhb_rounding_t; -int32_t asm330lhb_rounding_mode_set(stmdev_ctx_t *ctx, - asm330lhb_rounding_t val); -int32_t asm330lhb_rounding_mode_get(stmdev_ctx_t *ctx, - asm330lhb_rounding_t *val); +int32_t asm330lhb_rounding_mode_set(const stmdev_ctx_t *ctx, + asm330lhb_rounding_t val); +int32_t asm330lhb_rounding_mode_get(const stmdev_ctx_t *ctx, + asm330lhb_rounding_t *val); -int32_t asm330lhb_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t asm330lhb_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t asm330lhb_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t asm330lhb_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t asm330lhb_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t asm330lhb_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t asm330lhb_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhb_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { ASM330LHB_USER_BANK = 0, ASM330LHB_EMBEDDED_FUNC_BANK = 1, } asm330lhb_reg_access_t; -int32_t asm330lhb_mem_bank_set(stmdev_ctx_t *ctx, asm330lhb_reg_access_t val); -int32_t asm330lhb_mem_bank_get(stmdev_ctx_t *ctx, - asm330lhb_reg_access_t *val); - -int32_t asm330lhb_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address, - uint8_t *val); -int32_t asm330lhb_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, - uint8_t *buf, uint8_t len); -int32_t asm330lhb_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add, +int32_t asm330lhb_mem_bank_set(const stmdev_ctx_t *ctx, asm330lhb_reg_access_t val); +int32_t asm330lhb_mem_bank_get(const stmdev_ctx_t *ctx, + asm330lhb_reg_access_t *val); + +int32_t asm330lhb_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val); -int32_t asm330lhb_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, - uint8_t *val); +int32_t asm330lhb_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len); +int32_t asm330lhb_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, + uint8_t *val); +int32_t asm330lhb_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, + uint8_t *val); typedef enum { ASM330LHB_DRDY_LATCHED = 0, ASM330LHB_DRDY_PULSED = 1, } asm330lhb_dataready_pulsed_t; -int32_t asm330lhb_data_ready_mode_set(stmdev_ctx_t *ctx, - asm330lhb_dataready_pulsed_t val); -int32_t asm330lhb_data_ready_mode_get(stmdev_ctx_t *ctx, - asm330lhb_dataready_pulsed_t *val); +int32_t asm330lhb_data_ready_mode_set(const stmdev_ctx_t *ctx, + asm330lhb_dataready_pulsed_t val); +int32_t asm330lhb_data_ready_mode_get(const stmdev_ctx_t *ctx, + asm330lhb_dataready_pulsed_t *val); -int32_t asm330lhb_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhb_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t asm330lhb_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhb_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhb_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2066,8 +2067,8 @@ typedef enum ASM330LHB_XL_ST_POSITIVE = 1, ASM330LHB_XL_ST_NEGATIVE = 2, } asm330lhb_st_xl_t; -int32_t asm330lhb_xl_self_test_set(stmdev_ctx_t *ctx, asm330lhb_st_xl_t val); -int32_t asm330lhb_xl_self_test_get(stmdev_ctx_t *ctx, asm330lhb_st_xl_t *val); +int32_t asm330lhb_xl_self_test_set(const stmdev_ctx_t *ctx, asm330lhb_st_xl_t val); +int32_t asm330lhb_xl_self_test_get(const stmdev_ctx_t *ctx, asm330lhb_st_xl_t *val); typedef enum { @@ -2075,17 +2076,17 @@ typedef enum ASM330LHB_GY_ST_POSITIVE = 1, ASM330LHB_GY_ST_NEGATIVE = 3, } asm330lhb_st_g_t; -int32_t asm330lhb_gy_self_test_set(stmdev_ctx_t *ctx, asm330lhb_st_g_t val); -int32_t asm330lhb_gy_self_test_get(stmdev_ctx_t *ctx, asm330lhb_st_g_t *val); +int32_t asm330lhb_gy_self_test_set(const stmdev_ctx_t *ctx, asm330lhb_st_g_t val); +int32_t asm330lhb_gy_self_test_get(const stmdev_ctx_t *ctx, asm330lhb_st_g_t *val); -int32_t asm330lhb_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhb_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhb_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2098,13 +2099,13 @@ typedef enum ASM330LHB_AGGRESSIVE = 6, ASM330LHB_XTREME = 7, } asm330lhb_ftype_t; -int32_t asm330lhb_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, - asm330lhb_ftype_t val); -int32_t asm330lhb_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, - asm330lhb_ftype_t *val); +int32_t asm330lhb_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, + asm330lhb_ftype_t val); +int32_t asm330lhb_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, + asm330lhb_ftype_t *val); -int32_t asm330lhb_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2132,23 +2133,23 @@ typedef enum ASM330LHB_LP_ODR_DIV_400 = 0x06, ASM330LHB_LP_ODR_DIV_800 = 0x07, } asm330lhb_hp_slope_xl_en_t; -int32_t asm330lhb_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, - asm330lhb_hp_slope_xl_en_t val); -int32_t asm330lhb_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, - asm330lhb_hp_slope_xl_en_t *val); +int32_t asm330lhb_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, + asm330lhb_hp_slope_xl_en_t val); +int32_t asm330lhb_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, + asm330lhb_hp_slope_xl_en_t *val); -int32_t asm330lhb_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { ASM330LHB_USE_SLOPE = 0, ASM330LHB_USE_HPF = 1, } asm330lhb_slope_fds_t; -int32_t asm330lhb_xl_hp_path_internal_set(stmdev_ctx_t *ctx, - asm330lhb_slope_fds_t val); -int32_t asm330lhb_xl_hp_path_internal_get(stmdev_ctx_t *ctx, - asm330lhb_slope_fds_t *val); +int32_t asm330lhb_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, + asm330lhb_slope_fds_t val); +int32_t asm330lhb_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, + asm330lhb_slope_fds_t *val); typedef enum { @@ -2158,48 +2159,48 @@ typedef enum ASM330LHB_HP_FILTER_260mHz = 0x82, ASM330LHB_HP_FILTER_1Hz04 = 0x83, } asm330lhb_hpm_g_t; -int32_t asm330lhb_gy_hp_path_internal_set(stmdev_ctx_t *ctx, - asm330lhb_hpm_g_t val); -int32_t asm330lhb_gy_hp_path_internal_get(stmdev_ctx_t *ctx, - asm330lhb_hpm_g_t *val); +int32_t asm330lhb_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, + asm330lhb_hpm_g_t val); +int32_t asm330lhb_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, + asm330lhb_hpm_g_t *val); typedef enum { ASM330LHB_PULL_UP_DISC = 0, ASM330LHB_PULL_UP_CONNECT = 1, } asm330lhb_sdo_pu_en_t; -int32_t asm330lhb_sdo_sa0_mode_set(stmdev_ctx_t *ctx, - asm330lhb_sdo_pu_en_t val); -int32_t asm330lhb_sdo_sa0_mode_get(stmdev_ctx_t *ctx, - asm330lhb_sdo_pu_en_t *val); +int32_t asm330lhb_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, + asm330lhb_sdo_pu_en_t val); +int32_t asm330lhb_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, + asm330lhb_sdo_pu_en_t *val); typedef enum { ASM330LHB_PULL_DOWN_CONNECT = 0, ASM330LHB_PULL_DOWN_DISC = 1, } asm330lhb_pd_dis_int1_t; -int32_t asm330lhb_int1_mode_set(stmdev_ctx_t *ctx, - asm330lhb_pd_dis_int1_t val); -int32_t asm330lhb_int1_mode_get(stmdev_ctx_t *ctx, - asm330lhb_pd_dis_int1_t *val); +int32_t asm330lhb_int1_mode_set(const stmdev_ctx_t *ctx, + asm330lhb_pd_dis_int1_t val); +int32_t asm330lhb_int1_mode_get(const stmdev_ctx_t *ctx, + asm330lhb_pd_dis_int1_t *val); typedef enum { ASM330LHB_SPI_4_WIRE = 0, ASM330LHB_SPI_3_WIRE = 1, } asm330lhb_sim_t; -int32_t asm330lhb_spi_mode_set(stmdev_ctx_t *ctx, asm330lhb_sim_t val); -int32_t asm330lhb_spi_mode_get(stmdev_ctx_t *ctx, asm330lhb_sim_t *val); +int32_t asm330lhb_spi_mode_set(const stmdev_ctx_t *ctx, asm330lhb_sim_t val); +int32_t asm330lhb_spi_mode_get(const stmdev_ctx_t *ctx, asm330lhb_sim_t *val); typedef enum { ASM330LHB_I2C_ENABLE = 0, ASM330LHB_I2C_DISABLE = 1, } asm330lhb_i2c_disable_t; -int32_t asm330lhb_i2c_interface_set(stmdev_ctx_t *ctx, - asm330lhb_i2c_disable_t val); -int32_t asm330lhb_i2c_interface_get(stmdev_ctx_t *ctx, - asm330lhb_i2c_disable_t *val); +int32_t asm330lhb_i2c_interface_set(const stmdev_ctx_t *ctx, + asm330lhb_i2c_disable_t val); +int32_t asm330lhb_i2c_interface_get(const stmdev_ctx_t *ctx, + asm330lhb_i2c_disable_t *val); typedef enum { @@ -2209,10 +2210,10 @@ typedef enum ASM330LHB_I3C_ENABLE_T_1ms = 0x02, ASM330LHB_I3C_ENABLE_T_25ms = 0x03, } asm330lhb_i3c_disable_t; -int32_t asm330lhb_i3c_disable_set(stmdev_ctx_t *ctx, - asm330lhb_i3c_disable_t val); -int32_t asm330lhb_i3c_disable_get(stmdev_ctx_t *ctx, - asm330lhb_i3c_disable_t *val); +int32_t asm330lhb_i3c_disable_set(const stmdev_ctx_t *ctx, + asm330lhb_i3c_disable_t val); +int32_t asm330lhb_i3c_disable_get(const stmdev_ctx_t *ctx, + asm330lhb_i3c_disable_t *val); typedef struct { @@ -2223,10 +2224,10 @@ typedef struct asm330lhb_fsm_int1_b_t fsm_int1_b; asm330lhb_mlc_int1_t mlc_int1; } asm330lhb_pin_int1_route_t; -int32_t asm330lhb_pin_int1_route_set(stmdev_ctx_t *ctx, - asm330lhb_pin_int1_route_t *val); -int32_t asm330lhb_pin_int1_route_get(stmdev_ctx_t *ctx, - asm330lhb_pin_int1_route_t *val); +int32_t asm330lhb_pin_int1_route_set(const stmdev_ctx_t *ctx, + asm330lhb_pin_int1_route_t *val); +int32_t asm330lhb_pin_int1_route_get(const stmdev_ctx_t *ctx, + asm330lhb_pin_int1_route_t *val); typedef struct { @@ -2237,31 +2238,31 @@ typedef struct asm330lhb_fsm_int2_b_t fsm_int2_b; asm330lhb_mlc_int2_t mlc_int2; } asm330lhb_pin_int2_route_t; -int32_t asm330lhb_pin_int2_route_set(stmdev_ctx_t *ctx, - asm330lhb_pin_int2_route_t *val); -int32_t asm330lhb_pin_int2_route_get(stmdev_ctx_t *ctx, - asm330lhb_pin_int2_route_t *val); +int32_t asm330lhb_pin_int2_route_set(const stmdev_ctx_t *ctx, + asm330lhb_pin_int2_route_t *val); +int32_t asm330lhb_pin_int2_route_get(const stmdev_ctx_t *ctx, + asm330lhb_pin_int2_route_t *val); typedef enum { ASM330LHB_PUSH_PULL = 0, ASM330LHB_OPEN_DRAIN = 1, } asm330lhb_pp_od_t; -int32_t asm330lhb_pin_mode_set(stmdev_ctx_t *ctx, asm330lhb_pp_od_t val); -int32_t asm330lhb_pin_mode_get(stmdev_ctx_t *ctx, asm330lhb_pp_od_t *val); +int32_t asm330lhb_pin_mode_set(const stmdev_ctx_t *ctx, asm330lhb_pp_od_t val); +int32_t asm330lhb_pin_mode_get(const stmdev_ctx_t *ctx, asm330lhb_pp_od_t *val); typedef enum { ASM330LHB_ACTIVE_HIGH = 0, ASM330LHB_ACTIVE_LOW = 1, } asm330lhb_h_lactive_t; -int32_t asm330lhb_pin_polarity_set(stmdev_ctx_t *ctx, - asm330lhb_h_lactive_t val); -int32_t asm330lhb_pin_polarity_get(stmdev_ctx_t *ctx, - asm330lhb_h_lactive_t *val); +int32_t asm330lhb_pin_polarity_set(const stmdev_ctx_t *ctx, + asm330lhb_h_lactive_t val); +int32_t asm330lhb_pin_polarity_get(const stmdev_ctx_t *ctx, + asm330lhb_h_lactive_t *val); -int32_t asm330lhb_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2270,44 +2271,44 @@ typedef enum ASM330LHB_BASE_PULSED_EMB_LATCHED = 2, ASM330LHB_ALL_INT_LATCHED = 3, } asm330lhb_lir_t; -int32_t asm330lhb_int_notification_set(stmdev_ctx_t *ctx, - asm330lhb_lir_t val); -int32_t asm330lhb_int_notification_get(stmdev_ctx_t *ctx, - asm330lhb_lir_t *val); +int32_t asm330lhb_int_notification_set(const stmdev_ctx_t *ctx, + asm330lhb_lir_t val); +int32_t asm330lhb_int_notification_get(const stmdev_ctx_t *ctx, + asm330lhb_lir_t *val); typedef enum { ASM330LHB_LSb_FS_DIV_64 = 0, ASM330LHB_LSb_FS_DIV_256 = 1, } asm330lhb_wake_ths_w_t; -int32_t asm330lhb_wkup_ths_weight_set(stmdev_ctx_t *ctx, - asm330lhb_wake_ths_w_t val); -int32_t asm330lhb_wkup_ths_weight_get(stmdev_ctx_t *ctx, - asm330lhb_wake_ths_w_t *val); +int32_t asm330lhb_wkup_ths_weight_set(const stmdev_ctx_t *ctx, + asm330lhb_wake_ths_w_t val); +int32_t asm330lhb_wkup_ths_weight_get(const stmdev_ctx_t *ctx, + asm330lhb_wake_ths_w_t *val); -int32_t asm330lhb_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhb_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, - uint8_t val); -int32_t asm330lhb_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, - uint8_t *val); +int32_t asm330lhb_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, + uint8_t val); +int32_t asm330lhb_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, + uint8_t *val); -int32_t asm330lhb_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhb_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { ASM330LHB_DRIVE_SLEEP_CHG_EVENT = 0, ASM330LHB_DRIVE_SLEEP_STATUS = 1, } asm330lhb_sleep_status_on_int_t; -int32_t asm330lhb_act_pin_notification_set(stmdev_ctx_t *ctx, - asm330lhb_sleep_status_on_int_t val); -int32_t asm330lhb_act_pin_notification_get(stmdev_ctx_t *ctx, - asm330lhb_sleep_status_on_int_t *val); +int32_t asm330lhb_act_pin_notification_set(const stmdev_ctx_t *ctx, + asm330lhb_sleep_status_on_int_t val); +int32_t asm330lhb_act_pin_notification_get(const stmdev_ctx_t *ctx, + asm330lhb_sleep_status_on_int_t *val); typedef enum { @@ -2316,13 +2317,13 @@ typedef enum ASM330LHB_XL_12Hz5_GY_SLEEP = 2, ASM330LHB_XL_12Hz5_GY_PD = 3, } asm330lhb_inact_en_t; -int32_t asm330lhb_act_mode_set(stmdev_ctx_t *ctx, - asm330lhb_inact_en_t val); -int32_t asm330lhb_act_mode_get(stmdev_ctx_t *ctx, - asm330lhb_inact_en_t *val); +int32_t asm330lhb_act_mode_set(const stmdev_ctx_t *ctx, + asm330lhb_inact_en_t val); +int32_t asm330lhb_act_mode_get(const stmdev_ctx_t *ctx, + asm330lhb_inact_en_t *val); -int32_t asm330lhb_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2331,13 +2332,13 @@ typedef enum ASM330LHB_DEG_60 = 2, ASM330LHB_DEG_50 = 3, } asm330lhb_sixd_ths_t; -int32_t asm330lhb_6d_threshold_set(stmdev_ctx_t *ctx, - asm330lhb_sixd_ths_t val); -int32_t asm330lhb_6d_threshold_get(stmdev_ctx_t *ctx, - asm330lhb_sixd_ths_t *val); +int32_t asm330lhb_6d_threshold_set(const stmdev_ctx_t *ctx, + asm330lhb_sixd_ths_t val); +int32_t asm330lhb_6d_threshold_get(const stmdev_ctx_t *ctx, + asm330lhb_sixd_ths_t *val); -int32_t asm330lhb_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2350,24 +2351,24 @@ typedef enum ASM330LHB_FF_TSH_469mg = 6, ASM330LHB_FF_TSH_500mg = 7, } asm330lhb_ff_ths_t; -int32_t asm330lhb_ff_threshold_set(stmdev_ctx_t *ctx, - asm330lhb_ff_ths_t val); -int32_t asm330lhb_ff_threshold_get(stmdev_ctx_t *ctx, - asm330lhb_ff_ths_t *val); +int32_t asm330lhb_ff_threshold_set(const stmdev_ctx_t *ctx, + asm330lhb_ff_ths_t val); +int32_t asm330lhb_ff_threshold_get(const stmdev_ctx_t *ctx, + asm330lhb_ff_ths_t *val); -int32_t asm330lhb_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhb_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t asm330lhb_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t asm330lhb_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhb_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t asm330lhb_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, - uint8_t val); -int32_t asm330lhb_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, - uint8_t *val); +int32_t asm330lhb_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, + uint8_t val); +int32_t asm330lhb_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, + uint8_t *val); -int32_t asm330lhb_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2382,10 +2383,10 @@ typedef enum ASM330LHB_XL_BATCHED_AT_1667Hz = 8, ASM330LHB_XL_BATCHED_AT_1Hz6 = 11, } asm330lhb_bdr_xl_t; -int32_t asm330lhb_fifo_xl_batch_set(stmdev_ctx_t *ctx, - asm330lhb_bdr_xl_t val); -int32_t asm330lhb_fifo_xl_batch_get(stmdev_ctx_t *ctx, - asm330lhb_bdr_xl_t *val); +int32_t asm330lhb_fifo_xl_batch_set(const stmdev_ctx_t *ctx, + asm330lhb_bdr_xl_t val); +int32_t asm330lhb_fifo_xl_batch_get(const stmdev_ctx_t *ctx, + asm330lhb_bdr_xl_t *val); typedef enum { @@ -2400,10 +2401,10 @@ typedef enum ASM330LHB_GY_BATCHED_AT_1667Hz = 8, ASM330LHB_GY_BATCHED_AT_6Hz5 = 11, } asm330lhb_bdr_gy_t; -int32_t asm330lhb_fifo_gy_batch_set(stmdev_ctx_t *ctx, - asm330lhb_bdr_gy_t val); -int32_t asm330lhb_fifo_gy_batch_get(stmdev_ctx_t *ctx, - asm330lhb_bdr_gy_t *val); +int32_t asm330lhb_fifo_gy_batch_set(const stmdev_ctx_t *ctx, + asm330lhb_bdr_gy_t val); +int32_t asm330lhb_fifo_gy_batch_get(const stmdev_ctx_t *ctx, + asm330lhb_bdr_gy_t *val); typedef enum { @@ -2414,9 +2415,9 @@ typedef enum ASM330LHB_STREAM_MODE = 6, ASM330LHB_BYPASS_TO_FIFO_MODE = 7, } asm330lhb_fifo_mode_t; -int32_t asm330lhb_fifo_mode_set(stmdev_ctx_t *ctx, asm330lhb_fifo_mode_t val); -int32_t asm330lhb_fifo_mode_get(stmdev_ctx_t *ctx, - asm330lhb_fifo_mode_t *val); +int32_t asm330lhb_fifo_mode_set(const stmdev_ctx_t *ctx, asm330lhb_fifo_mode_t val); +int32_t asm330lhb_fifo_mode_get(const stmdev_ctx_t *ctx, + asm330lhb_fifo_mode_t *val); typedef enum { @@ -2425,10 +2426,10 @@ typedef enum ASM330LHB_TEMP_BATCHED_AT_12Hz5 = 2, ASM330LHB_TEMP_BATCHED_AT_1Hz6 = 3, } asm330lhb_odr_t_batch_t; -int32_t asm330lhb_fifo_temp_batch_set(stmdev_ctx_t *ctx, - asm330lhb_odr_t_batch_t val); -int32_t asm330lhb_fifo_temp_batch_get(stmdev_ctx_t *ctx, - asm330lhb_odr_t_batch_t *val); +int32_t asm330lhb_fifo_temp_batch_set(const stmdev_ctx_t *ctx, + asm330lhb_odr_t_batch_t val); +int32_t asm330lhb_fifo_temp_batch_get(const stmdev_ctx_t *ctx, + asm330lhb_odr_t_batch_t *val); typedef enum { @@ -2437,39 +2438,39 @@ typedef enum ASM330LHB_DEC_8 = 2, ASM330LHB_DEC_32 = 3, } asm330lhb_dec_ts_batch_t; -int32_t asm330lhb_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, - asm330lhb_dec_ts_batch_t val); -int32_t asm330lhb_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, - asm330lhb_dec_ts_batch_t *val); +int32_t asm330lhb_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, + asm330lhb_dec_ts_batch_t val); +int32_t asm330lhb_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, + asm330lhb_dec_ts_batch_t *val); typedef enum { ASM330LHB_XL_BATCH_EVENT = 0, ASM330LHB_GYRO_BATCH_EVENT = 1, } asm330lhb_trig_counter_bdr_t; -int32_t asm330lhb_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, - asm330lhb_trig_counter_bdr_t val); -int32_t asm330lhb_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, - asm330lhb_trig_counter_bdr_t *val); +int32_t asm330lhb_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, + asm330lhb_trig_counter_bdr_t val); +int32_t asm330lhb_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, + asm330lhb_trig_counter_bdr_t *val); -int32_t asm330lhb_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhb_batch_counter_threshold_set(stmdev_ctx_t *ctx, - uint16_t val); -int32_t asm330lhb_batch_counter_threshold_get(stmdev_ctx_t *ctx, - uint16_t *val); +int32_t asm330lhb_batch_counter_threshold_set(const stmdev_ctx_t *ctx, + uint16_t val); +int32_t asm330lhb_batch_counter_threshold_get(const stmdev_ctx_t *ctx, + uint16_t *val); -int32_t asm330lhb_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t asm330lhb_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t asm330lhb_fifo_status_get(stmdev_ctx_t *ctx, - asm330lhb_fifo_status2_t *val); +int32_t asm330lhb_fifo_status_get(const stmdev_ctx_t *ctx, + asm330lhb_fifo_status2_t *val); -int32_t asm330lhb_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhb_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhb_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2479,8 +2480,8 @@ typedef enum ASM330LHB_TIMESTAMP_TAG = 0x04, ASM330LHB_CFG_CHANGE_TAG = 0x05, } asm330lhb_fifo_tag_t; -int32_t asm330lhb_fifo_sensor_tag_get(stmdev_ctx_t *ctx, - asm330lhb_fifo_tag_t *val); +int32_t asm330lhb_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, + asm330lhb_fifo_tag_t *val); typedef enum { @@ -2490,20 +2491,20 @@ typedef enum ASM330LHB_LEVEL_TRIGGER = 2, ASM330LHB_EDGE_TRIGGER = 4, } asm330lhb_den_mode_t; -int32_t asm330lhb_den_mode_set(stmdev_ctx_t *ctx, - asm330lhb_den_mode_t val); -int32_t asm330lhb_den_mode_get(stmdev_ctx_t *ctx, - asm330lhb_den_mode_t *val); +int32_t asm330lhb_den_mode_set(const stmdev_ctx_t *ctx, + asm330lhb_den_mode_t val); +int32_t asm330lhb_den_mode_get(const stmdev_ctx_t *ctx, + asm330lhb_den_mode_t *val); typedef enum { ASM330LHB_DEN_ACT_LOW = 0, ASM330LHB_DEN_ACT_HIGH = 1, } asm330lhb_den_lh_t; -int32_t asm330lhb_den_polarity_set(stmdev_ctx_t *ctx, - asm330lhb_den_lh_t val); -int32_t asm330lhb_den_polarity_get(stmdev_ctx_t *ctx, - asm330lhb_den_lh_t *val); +int32_t asm330lhb_den_polarity_set(const stmdev_ctx_t *ctx, + asm330lhb_den_lh_t val); +int32_t asm330lhb_den_polarity_get(const stmdev_ctx_t *ctx, + asm330lhb_den_lh_t *val); typedef enum { @@ -2511,28 +2512,28 @@ typedef enum ASM330LHB_STAMP_IN_XL_DATA = 1, ASM330LHB_STAMP_IN_GY_XL_DATA = 2, } asm330lhb_den_xl_g_t; -int32_t asm330lhb_den_enable_set(stmdev_ctx_t *ctx, - asm330lhb_den_xl_g_t val); -int32_t asm330lhb_den_enable_get(stmdev_ctx_t *ctx, - asm330lhb_den_xl_g_t *val); +int32_t asm330lhb_den_enable_set(const stmdev_ctx_t *ctx, + asm330lhb_den_xl_g_t val); +int32_t asm330lhb_den_enable_get(const stmdev_ctx_t *ctx, + asm330lhb_den_xl_g_t *val); -int32_t asm330lhb_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhb_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhb_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhb_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t asm330lhb_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t asm330lhb_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhb_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t asm330lhb_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val); -int32_t asm330lhb_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t asm330lhb_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val); +int32_t asm330lhb_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t asm330lhb_mag_soft_iron_set(stmdev_ctx_t *ctx, uint16_t *val); -int32_t asm330lhb_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t asm330lhb_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint16_t *val); +int32_t asm330lhb_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum { @@ -2543,10 +2544,10 @@ typedef enum ASM330LHB_Z_EQ_MIN_Z = 4, ASM330LHB_Z_EQ_Z = 5, } asm330lhb_mag_z_axis_t; -int32_t asm330lhb_mag_z_orient_set(stmdev_ctx_t *ctx, - asm330lhb_mag_z_axis_t val); -int32_t asm330lhb_mag_z_orient_get(stmdev_ctx_t *ctx, - asm330lhb_mag_z_axis_t *val); +int32_t asm330lhb_mag_z_orient_set(const stmdev_ctx_t *ctx, + asm330lhb_mag_z_axis_t val); +int32_t asm330lhb_mag_z_orient_get(const stmdev_ctx_t *ctx, + asm330lhb_mag_z_axis_t *val); typedef enum { @@ -2557,10 +2558,10 @@ typedef enum ASM330LHB_Y_EQ_MIN_Z = 4, ASM330LHB_Y_EQ_Z = 5, } asm330lhb_mag_y_axis_t; -int32_t asm330lhb_mag_y_orient_set(stmdev_ctx_t *ctx, - asm330lhb_mag_y_axis_t val); -int32_t asm330lhb_mag_y_orient_get(stmdev_ctx_t *ctx, - asm330lhb_mag_y_axis_t *val); +int32_t asm330lhb_mag_y_orient_set(const stmdev_ctx_t *ctx, + asm330lhb_mag_y_axis_t val); +int32_t asm330lhb_mag_y_orient_get(const stmdev_ctx_t *ctx, + asm330lhb_mag_y_axis_t *val); typedef enum { @@ -2571,10 +2572,10 @@ typedef enum ASM330LHB_X_EQ_MIN_Z = 4, ASM330LHB_X_EQ_Z = 5, } asm330lhb_mag_x_axis_t; -int32_t asm330lhb_mag_x_orient_set(stmdev_ctx_t *ctx, - asm330lhb_mag_x_axis_t val); -int32_t asm330lhb_mag_x_orient_get(stmdev_ctx_t *ctx, - asm330lhb_mag_x_axis_t *val); +int32_t asm330lhb_mag_x_orient_set(const stmdev_ctx_t *ctx, + asm330lhb_mag_x_axis_t val); +int32_t asm330lhb_mag_x_orient_get(const stmdev_ctx_t *ctx, + asm330lhb_mag_x_axis_t *val); typedef struct { @@ -2595,31 +2596,31 @@ typedef struct uint16_t fsm15 : 1; uint16_t fsm16 : 1; } asm330lhb_fsm_status_t; -int32_t asm330lhb_fsm_status_get(stmdev_ctx_t *ctx, - asm330lhb_fsm_status_t *val); -int32_t asm330lhb_fsm_out_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhb_fsm_status_get(const stmdev_ctx_t *ctx, + asm330lhb_fsm_status_t *val); +int32_t asm330lhb_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t asm330lhb_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, - uint8_t *val); +int32_t asm330lhb_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, + uint8_t *val); -int32_t asm330lhb_emb_func_clk_dis_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_emb_func_clk_dis_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_emb_func_clk_dis_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_emb_func_clk_dis_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhb_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { asm330lhb_fsm_enable_a_t fsm_enable_a; asm330lhb_fsm_enable_b_t fsm_enable_b; } asm330lhb_emb_fsm_enable_t; -int32_t asm330lhb_fsm_enable_set(stmdev_ctx_t *ctx, - asm330lhb_emb_fsm_enable_t *val); -int32_t asm330lhb_fsm_enable_get(stmdev_ctx_t *ctx, - asm330lhb_emb_fsm_enable_t *val); +int32_t asm330lhb_fsm_enable_set(const stmdev_ctx_t *ctx, + asm330lhb_emb_fsm_enable_t *val); +int32_t asm330lhb_fsm_enable_get(const stmdev_ctx_t *ctx, + asm330lhb_emb_fsm_enable_t *val); -int32_t asm330lhb_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t asm330lhb_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t asm330lhb_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhb_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum { @@ -2627,10 +2628,10 @@ typedef enum ASM330LHB_LC_CLEAR = 1, ASM330LHB_LC_CLEAR_DONE = 2, } asm330lhb_fsm_lc_clr_t; -int32_t asm330lhb_long_clr_set(stmdev_ctx_t *ctx, - asm330lhb_fsm_lc_clr_t val); -int32_t asm330lhb_long_clr_get(stmdev_ctx_t *ctx, - asm330lhb_fsm_lc_clr_t *val); +int32_t asm330lhb_long_clr_set(const stmdev_ctx_t *ctx, + asm330lhb_fsm_lc_clr_t val); +int32_t asm330lhb_long_clr_get(const stmdev_ctx_t *ctx, + asm330lhb_fsm_lc_clr_t *val); typedef enum { @@ -2639,30 +2640,30 @@ typedef enum ASM330LHB_ODR_FSM_52Hz = 2, ASM330LHB_ODR_FSM_104Hz = 3, } asm330lhb_fsm_odr_t; -int32_t asm330lhb_fsm_data_rate_set(stmdev_ctx_t *ctx, - asm330lhb_fsm_odr_t val); -int32_t asm330lhb_fsm_data_rate_get(stmdev_ctx_t *ctx, - asm330lhb_fsm_odr_t *val); +int32_t asm330lhb_fsm_data_rate_set(const stmdev_ctx_t *ctx, + asm330lhb_fsm_odr_t val); +int32_t asm330lhb_fsm_data_rate_get(const stmdev_ctx_t *ctx, + asm330lhb_fsm_odr_t *val); -int32_t asm330lhb_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhb_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t asm330lhb_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t asm330lhb_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhb_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t asm330lhb_fsm_number_of_programs_set(stmdev_ctx_t *ctx, - uint8_t *buff); -int32_t asm330lhb_fsm_number_of_programs_get(stmdev_ctx_t *ctx, - uint8_t *buff); +int32_t asm330lhb_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, + uint8_t *buff); +int32_t asm330lhb_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, + uint8_t *buff); -int32_t asm330lhb_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t asm330lhb_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t asm330lhb_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhb_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t asm330lhb_mlc_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_mlc_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_mlc_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhb_mlc_status_get(stmdev_ctx_t *ctx, - asm330lhb_mlc_status_mainpage_t *val); +int32_t asm330lhb_mlc_status_get(const stmdev_ctx_t *ctx, + asm330lhb_mlc_status_mainpage_t *val); typedef enum { @@ -2671,18 +2672,18 @@ typedef enum ASM330LHB_ODR_PRGS_52Hz = 2, ASM330LHB_ODR_PRGS_104Hz = 3, } asm330lhb_mlc_odr_t; -int32_t asm330lhb_mlc_data_rate_set(stmdev_ctx_t *ctx, - asm330lhb_mlc_odr_t val); -int32_t asm330lhb_mlc_data_rate_get(stmdev_ctx_t *ctx, - asm330lhb_mlc_odr_t *val); +int32_t asm330lhb_mlc_data_rate_set(const stmdev_ctx_t *ctx, + asm330lhb_mlc_odr_t val); +int32_t asm330lhb_mlc_data_rate_get(const stmdev_ctx_t *ctx, + asm330lhb_mlc_odr_t *val); -int32_t asm330lhb_mlc_init_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhb_mlc_init_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhb_mlc_init_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhb_mlc_init_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhb_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhb_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t asm330lhb_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t asm330lhb_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t asm330lhb_mlc_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhb_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); /** *@} diff --git a/sensor/stmemsc/asm330lhbg1_STdC/driver/asm330lhbg1_reg.c b/sensor/stmemsc/asm330lhbg1_STdC/driver/asm330lhbg1_reg.c new file mode 100644 index 00000000..14ba4fb4 --- /dev/null +++ b/sensor/stmemsc/asm330lhbg1_STdC/driver/asm330lhbg1_reg.c @@ -0,0 +1,6619 @@ +/* + ****************************************************************************** + * @file asm330lhbg1_reg.c + * @author Sensors Software Solution Team + * @brief ASM330LHBG1 driver file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2023 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "asm330lhbg1_reg.h" + +/** + * @defgroup ASM330LHBG1 + * @brief This file provides a set of functions needed to drive the + * asm330lhbg1 enhanced inertial module. + * @{ + * + */ + +/** + * @defgroup ASM330LHBG1_Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +/** + * @brief Read generic device register + * + * @param ctx read / write interface definitions(ptr) + * @param reg register to read + * @param data pointer to buffer that store the data read(ptr) + * @param len number of consecutive register to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak asm330lhbg1_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len) +{ + int32_t ret; + + if (ctx == NULL) + { + return -1; + } + + ret = ctx->read_reg(ctx->handle, reg, data, len); + + return ret; +} + +/** + * @brief Write generic device register + * + * @param ctx read / write interface definitions(ptr) + * @param reg register to write + * @param data pointer to data to write in register reg(ptr) + * @param len number of consecutive register to write + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak asm330lhbg1_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len) +{ + int32_t ret; + + if (ctx == NULL) + { + return -1; + } + + ret = ctx->write_reg(ctx->handle, reg, data, len); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHBG1_Sensitivity + * @brief These functions convert raw-data into engineering units. + * @{ + * + */ + +float_t asm330lhbg1_from_fs2g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.061f); +} + +float_t asm330lhbg1_from_fs4g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.122f); +} + +float_t asm330lhbg1_from_fs8g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.244f); +} + +float_t asm330lhbg1_from_fs16g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.488f); +} + +float_t asm330lhbg1_from_fs125dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 4.375f); +} + +float_t asm330lhbg1_from_fs250dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 8.75f); +} + +float_t asm330lhbg1_from_fs500dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 17.50f); +} + +float_t asm330lhbg1_from_fs1000dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 35.0f); +} + +float_t asm330lhbg1_from_fs2000dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 70.0f); +} + +float_t asm330lhbg1_from_fs4000dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 140.0f); +} + +float_t asm330lhbg1_from_lsb_to_celsius(int16_t lsb) +{ + return (((float_t)lsb / 256.0f) + 25.0f); +} + +float_t asm330lhbg1_from_lsb_to_nsec(int32_t lsb) +{ + return ((float_t)lsb * 25000.0f); +} + +/** + * @} + * + */ + +/** + * @defgroup LSM9DS1_Data_generation + * @brief This section groups all the functions concerning data + * generation + * @{ + * + */ + +/** + * @brief Accelerometer full-scale selection[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fs_xl in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_full_scale_set(const stmdev_ctx_t *ctx, + asm330lhbg1_fs_xl_t val) +{ + asm330lhbg1_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret == 0) + { + ctrl1_xl.fs_xl = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL1_XL, + (uint8_t *)&ctrl1_xl, 1); + } + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of fs_xl in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_full_scale_get(const stmdev_ctx_t *ctx, + asm330lhbg1_fs_xl_t *val) +{ + asm330lhbg1_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + switch (ctrl1_xl.fs_xl) + { + case ASM330LHBG1_2g: + *val = ASM330LHBG1_2g; + break; + case ASM330LHBG1_16g: + *val = ASM330LHBG1_16g; + break; + case ASM330LHBG1_4g: + *val = ASM330LHBG1_4g; + break; + case ASM330LHBG1_8g: + *val = ASM330LHBG1_8g; + break; + default: + *val = ASM330LHBG1_2g; + break; + } + return ret; +} + +/** + * @brief Accelerometer UI data rate selection.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of odr_xl in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_data_rate_set(const stmdev_ctx_t *ctx, + asm330lhbg1_odr_xl_t val) +{ + asm330lhbg1_odr_xl_t odr_xl = val; + asm330lhbg1_emb_fsm_enable_t fsm_enable; + asm330lhbg1_fsm_odr_t fsm_odr; + asm330lhbg1_ctrl1_xl_t ctrl1_xl; + asm330lhbg1_mlc_odr_t mlc_odr; + uint8_t mlc_enable; + int32_t ret; + + /* Check the Finite State Machine data rate constraints */ + ret = asm330lhbg1_fsm_enable_get(ctx, &fsm_enable); + if (ret == 0) + { + if ((fsm_enable.fsm_enable_a.fsm1_en | + fsm_enable.fsm_enable_a.fsm2_en | + fsm_enable.fsm_enable_a.fsm3_en | + fsm_enable.fsm_enable_a.fsm4_en | + fsm_enable.fsm_enable_a.fsm5_en | + fsm_enable.fsm_enable_a.fsm6_en | + fsm_enable.fsm_enable_a.fsm7_en | + fsm_enable.fsm_enable_a.fsm8_en | + fsm_enable.fsm_enable_b.fsm9_en | + fsm_enable.fsm_enable_b.fsm10_en | + fsm_enable.fsm_enable_b.fsm11_en | + fsm_enable.fsm_enable_b.fsm12_en | + fsm_enable.fsm_enable_b.fsm13_en | + fsm_enable.fsm_enable_b.fsm14_en | + fsm_enable.fsm_enable_b.fsm15_en | + fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE) + { + + ret = asm330lhbg1_fsm_data_rate_get(ctx, &fsm_odr); + if (ret == 0) + { + switch (fsm_odr) + { + case ASM330LHBG1_ODR_FSM_12Hz5: + + if (val == ASM330LHBG1_XL_ODR_OFF) + { + odr_xl = ASM330LHBG1_XL_ODR_12Hz5; + + } + else + { + odr_xl = val; + } + break; + case ASM330LHBG1_ODR_FSM_26Hz: + + if (val == ASM330LHBG1_XL_ODR_OFF) + { + odr_xl = ASM330LHBG1_XL_ODR_26Hz; + + } + else if (val == ASM330LHBG1_XL_ODR_12Hz5) + { + odr_xl = ASM330LHBG1_XL_ODR_26Hz; + + } + else + { + odr_xl = val; + } + break; + case ASM330LHBG1_ODR_FSM_52Hz: + + if (val == ASM330LHBG1_XL_ODR_OFF) + { + odr_xl = ASM330LHBG1_XL_ODR_52Hz; + + } + else if (val == ASM330LHBG1_XL_ODR_12Hz5) + { + odr_xl = ASM330LHBG1_XL_ODR_52Hz; + + } + else if (val == ASM330LHBG1_XL_ODR_26Hz) + { + odr_xl = ASM330LHBG1_XL_ODR_52Hz; + + } + else + { + odr_xl = val; + } + break; + case ASM330LHBG1_ODR_FSM_104Hz: + + if (val == ASM330LHBG1_XL_ODR_OFF) + { + odr_xl = ASM330LHBG1_XL_ODR_104Hz; + + } + else if (val == ASM330LHBG1_XL_ODR_12Hz5) + { + odr_xl = ASM330LHBG1_XL_ODR_104Hz; + + } + else if (val == ASM330LHBG1_XL_ODR_26Hz) + { + odr_xl = ASM330LHBG1_XL_ODR_104Hz; + + } + else if (val == ASM330LHBG1_XL_ODR_52Hz) + { + odr_xl = ASM330LHBG1_XL_ODR_104Hz; + + } + else + { + odr_xl = val; + } + break; + default: + odr_xl = val; + break; + } + } + } + } + + /* Check the Machine Learning Core data rate constraints */ + mlc_enable = PROPERTY_DISABLE; + if (ret == 0) + { + ret = asm330lhbg1_mlc_get(ctx, &mlc_enable); + if (mlc_enable == PROPERTY_ENABLE) + { + + ret = asm330lhbg1_mlc_data_rate_get(ctx, &mlc_odr); + if (ret == 0) + { + switch (mlc_odr) + { + case ASM330LHBG1_ODR_PRGS_12Hz5: + + if (val == ASM330LHBG1_XL_ODR_OFF) + { + odr_xl = ASM330LHBG1_XL_ODR_12Hz5; + + } + else + { + odr_xl = val; + } + break; + case ASM330LHBG1_ODR_PRGS_26Hz: + if (val == ASM330LHBG1_XL_ODR_OFF) + { + odr_xl = ASM330LHBG1_XL_ODR_26Hz; + + } + else if (val == ASM330LHBG1_XL_ODR_12Hz5) + { + odr_xl = ASM330LHBG1_XL_ODR_26Hz; + + } + else + { + odr_xl = val; + } + break; + case ASM330LHBG1_ODR_PRGS_52Hz: + + if (val == ASM330LHBG1_XL_ODR_OFF) + { + odr_xl = ASM330LHBG1_XL_ODR_52Hz; + + } + else if (val == ASM330LHBG1_XL_ODR_12Hz5) + { + odr_xl = ASM330LHBG1_XL_ODR_52Hz; + + } + else if (val == ASM330LHBG1_XL_ODR_26Hz) + { + odr_xl = ASM330LHBG1_XL_ODR_52Hz; + + } + else + { + odr_xl = val; + } + break; + case ASM330LHBG1_ODR_PRGS_104Hz: + if (val == ASM330LHBG1_XL_ODR_OFF) + { + odr_xl = ASM330LHBG1_XL_ODR_104Hz; + + } + else if (val == ASM330LHBG1_XL_ODR_12Hz5) + { + odr_xl = ASM330LHBG1_XL_ODR_104Hz; + + } + else if (val == ASM330LHBG1_XL_ODR_26Hz) + { + odr_xl = ASM330LHBG1_XL_ODR_104Hz; + + } + else if (val == ASM330LHBG1_XL_ODR_52Hz) + { + odr_xl = ASM330LHBG1_XL_ODR_104Hz; + + } + else + { + odr_xl = val; + } + break; + default: + odr_xl = val; + break; + } + } + } + } + + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + } + if (ret == 0) + { + ctrl1_xl.odr_xl = (uint8_t)odr_xl; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL1_XL, + (uint8_t *)&ctrl1_xl, 1); + } + return ret; +} + +/** + * @brief Accelerometer UI data rate selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of odr_xl in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_data_rate_get(const stmdev_ctx_t *ctx, + asm330lhbg1_odr_xl_t *val) +{ + asm330lhbg1_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + switch (ctrl1_xl.odr_xl) + { + case ASM330LHBG1_XL_ODR_OFF: + *val = ASM330LHBG1_XL_ODR_OFF; + break; + case ASM330LHBG1_XL_ODR_12Hz5: + *val = ASM330LHBG1_XL_ODR_12Hz5; + break; + case ASM330LHBG1_XL_ODR_26Hz: + *val = ASM330LHBG1_XL_ODR_26Hz; + break; + case ASM330LHBG1_XL_ODR_52Hz: + *val = ASM330LHBG1_XL_ODR_52Hz; + break; + case ASM330LHBG1_XL_ODR_104Hz: + *val = ASM330LHBG1_XL_ODR_104Hz; + break; + case ASM330LHBG1_XL_ODR_208Hz: + *val = ASM330LHBG1_XL_ODR_208Hz; + break; + case ASM330LHBG1_XL_ODR_417Hz: + *val = ASM330LHBG1_XL_ODR_417Hz; + break; + case ASM330LHBG1_XL_ODR_833Hz: + *val = ASM330LHBG1_XL_ODR_833Hz; + break; + case ASM330LHBG1_XL_ODR_1667Hz: + *val = ASM330LHBG1_XL_ODR_1667Hz; + break; + case ASM330LHBG1_XL_ODR_1Hz6: + *val = ASM330LHBG1_XL_ODR_1Hz6; + break; + default: + *val = ASM330LHBG1_XL_ODR_OFF; + break; + } + return ret; +} + +/** + * @brief Gyroscope UI chain full-scale selection.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fs_g in reg CTRL2_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_gy_full_scale_set(const stmdev_ctx_t *ctx, + asm330lhbg1_fs_g_t val) +{ + asm330lhbg1_ctrl2_g_t ctrl2_g; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret == 0) + { + ctrl2_g.fs_g = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + } + return ret; +} + +/** + * @brief Gyroscope UI chain full-scale selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of fs_g in reg CTRL2_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_gy_full_scale_get(const stmdev_ctx_t *ctx, + asm330lhbg1_fs_g_t *val) +{ + asm330lhbg1_ctrl2_g_t ctrl2_g; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + switch (ctrl2_g.fs_g) + { + case ASM330LHBG1_125dps: + *val = ASM330LHBG1_125dps; + break; + case ASM330LHBG1_250dps: + *val = ASM330LHBG1_250dps; + break; + case ASM330LHBG1_500dps: + *val = ASM330LHBG1_500dps; + break; + case ASM330LHBG1_1000dps: + *val = ASM330LHBG1_1000dps; + break; + case ASM330LHBG1_2000dps: + *val = ASM330LHBG1_2000dps; + break; + case ASM330LHBG1_4000dps: + *val = ASM330LHBG1_4000dps; + break; + default: + *val = ASM330LHBG1_125dps; + break; + } + return ret; +} + +/** + * @brief Gyroscope data rate.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of odr_g in reg CTRL2_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_gy_data_rate_set(const stmdev_ctx_t *ctx, + asm330lhbg1_odr_g_t val) +{ + asm330lhbg1_odr_g_t odr_gy = val; + asm330lhbg1_emb_fsm_enable_t fsm_enable; + asm330lhbg1_fsm_odr_t fsm_odr; + asm330lhbg1_ctrl2_g_t ctrl2_g; + asm330lhbg1_mlc_odr_t mlc_odr; + uint8_t mlc_enable; + int32_t ret; + + /* Check the Finite State Machine data rate constraints */ + ret = asm330lhbg1_fsm_enable_get(ctx, &fsm_enable); + if (ret == 0) + { + if ((fsm_enable.fsm_enable_a.fsm1_en | + fsm_enable.fsm_enable_a.fsm2_en | + fsm_enable.fsm_enable_a.fsm3_en | + fsm_enable.fsm_enable_a.fsm4_en | + fsm_enable.fsm_enable_a.fsm5_en | + fsm_enable.fsm_enable_a.fsm6_en | + fsm_enable.fsm_enable_a.fsm7_en | + fsm_enable.fsm_enable_a.fsm8_en | + fsm_enable.fsm_enable_b.fsm9_en | + fsm_enable.fsm_enable_b.fsm10_en | + fsm_enable.fsm_enable_b.fsm11_en | + fsm_enable.fsm_enable_b.fsm12_en | + fsm_enable.fsm_enable_b.fsm13_en | + fsm_enable.fsm_enable_b.fsm14_en | + fsm_enable.fsm_enable_b.fsm15_en | + fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE) + { + + ret = asm330lhbg1_fsm_data_rate_get(ctx, &fsm_odr); + if (ret == 0) + { + switch (fsm_odr) + { + case ASM330LHBG1_ODR_FSM_12Hz5: + + if (val == ASM330LHBG1_GY_ODR_OFF) + { + odr_gy = ASM330LHBG1_GY_ODR_12Hz5; + + } + else + { + odr_gy = val; + } + break; + case ASM330LHBG1_ODR_FSM_26Hz: + + if (val == ASM330LHBG1_GY_ODR_OFF) + { + odr_gy = ASM330LHBG1_GY_ODR_26Hz; + + } + else if (val == ASM330LHBG1_GY_ODR_12Hz5) + { + odr_gy = ASM330LHBG1_GY_ODR_26Hz; + + } + else + { + odr_gy = val; + } + break; + case ASM330LHBG1_ODR_FSM_52Hz: + + if (val == ASM330LHBG1_GY_ODR_OFF) + { + odr_gy = ASM330LHBG1_GY_ODR_52Hz; + + } + else if (val == ASM330LHBG1_GY_ODR_12Hz5) + { + odr_gy = ASM330LHBG1_GY_ODR_52Hz; + + } + else if (val == ASM330LHBG1_GY_ODR_26Hz) + { + odr_gy = ASM330LHBG1_GY_ODR_52Hz; + + } + else + { + odr_gy = val; + } + break; + case ASM330LHBG1_ODR_FSM_104Hz: + + if (val == ASM330LHBG1_GY_ODR_OFF) + { + odr_gy = ASM330LHBG1_GY_ODR_104Hz; + + } + else if (val == ASM330LHBG1_GY_ODR_12Hz5) + { + odr_gy = ASM330LHBG1_GY_ODR_104Hz; + + } + else if (val == ASM330LHBG1_GY_ODR_26Hz) + { + odr_gy = ASM330LHBG1_GY_ODR_104Hz; + + } + else if (val == ASM330LHBG1_GY_ODR_52Hz) + { + odr_gy = ASM330LHBG1_GY_ODR_104Hz; + + } + else + { + odr_gy = val; + } + break; + default: + odr_gy = val; + break; + } + } + } + } + + /* Check the Machine Learning Core data rate constraints */ + mlc_enable = PROPERTY_DISABLE; + if (ret == 0) + { + ret = asm330lhbg1_mlc_get(ctx, &mlc_enable); + if (mlc_enable == PROPERTY_ENABLE) + { + + ret = asm330lhbg1_mlc_data_rate_get(ctx, &mlc_odr); + if (ret == 0) + { + switch (mlc_odr) + { + case ASM330LHBG1_ODR_PRGS_12Hz5: + + if (val == ASM330LHBG1_GY_ODR_OFF) + { + odr_gy = ASM330LHBG1_GY_ODR_12Hz5; + + } + else + { + odr_gy = val; + } + break; + case ASM330LHBG1_ODR_PRGS_26Hz: + + if (val == ASM330LHBG1_GY_ODR_OFF) + { + odr_gy = ASM330LHBG1_GY_ODR_26Hz; + + } + else if (val == ASM330LHBG1_GY_ODR_12Hz5) + { + odr_gy = ASM330LHBG1_GY_ODR_26Hz; + + } + else + { + odr_gy = val; + } + break; + case ASM330LHBG1_ODR_PRGS_52Hz: + + if (val == ASM330LHBG1_GY_ODR_OFF) + { + odr_gy = ASM330LHBG1_GY_ODR_52Hz; + + } + else if (val == ASM330LHBG1_GY_ODR_12Hz5) + { + odr_gy = ASM330LHBG1_GY_ODR_52Hz; + + } + else if (val == ASM330LHBG1_GY_ODR_26Hz) + { + odr_gy = ASM330LHBG1_GY_ODR_52Hz; + + } + else + { + odr_gy = val; + } + break; + case ASM330LHBG1_ODR_PRGS_104Hz: + + if (val == ASM330LHBG1_GY_ODR_OFF) + { + odr_gy = ASM330LHBG1_GY_ODR_104Hz; + + } + else if (val == ASM330LHBG1_GY_ODR_12Hz5) + { + odr_gy = ASM330LHBG1_GY_ODR_104Hz; + + } + else if (val == ASM330LHBG1_GY_ODR_26Hz) + { + odr_gy = ASM330LHBG1_GY_ODR_104Hz; + + } + else if (val == ASM330LHBG1_GY_ODR_52Hz) + { + odr_gy = ASM330LHBG1_GY_ODR_104Hz; + + } + else + { + odr_gy = val; + } + break; + default: + odr_gy = val; + break; + } + } + } + } + + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + } + if (ret == 0) + { + ctrl2_g.odr_g = (uint8_t)odr_gy; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + } + return ret; +} + +/** + * @brief Gyroscope data rate.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of odr_g in reg CTRL2_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_gy_data_rate_get(const stmdev_ctx_t *ctx, + asm330lhbg1_odr_g_t *val) +{ + asm330lhbg1_ctrl2_g_t ctrl2_g; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + switch (ctrl2_g.odr_g) + { + case ASM330LHBG1_GY_ODR_OFF: + *val = ASM330LHBG1_GY_ODR_OFF; + break; + case ASM330LHBG1_GY_ODR_12Hz5: + *val = ASM330LHBG1_GY_ODR_12Hz5; + break; + case ASM330LHBG1_GY_ODR_26Hz: + *val = ASM330LHBG1_GY_ODR_26Hz; + break; + case ASM330LHBG1_GY_ODR_52Hz: + *val = ASM330LHBG1_GY_ODR_52Hz; + break; + case ASM330LHBG1_GY_ODR_104Hz: + *val = ASM330LHBG1_GY_ODR_104Hz; + break; + case ASM330LHBG1_GY_ODR_208Hz: + *val = ASM330LHBG1_GY_ODR_208Hz; + break; + case ASM330LHBG1_GY_ODR_417Hz: + *val = ASM330LHBG1_GY_ODR_417Hz; + break; + case ASM330LHBG1_GY_ODR_833Hz: + *val = ASM330LHBG1_GY_ODR_833Hz; + break; + case ASM330LHBG1_GY_ODR_1667Hz: + *val = ASM330LHBG1_GY_ODR_1667Hz; + break; + default: + *val = ASM330LHBG1_GY_ODR_OFF; + break; + } + return ret; +} + +/** + * @brief Block data update.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of bdu in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret == 0) + { + ctrl3_c.bdu = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Block data update.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of bdu in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + *val = ctrl3_c.bdu; + + return ret; +} + +/** + * @brief Weight of XL user offset bits of registers X_OFS_USR (73h), + * Y_OFS_USR (74h), Z_OFS_USR (75h).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of usr_off_w in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_offset_weight_set(const stmdev_ctx_t *ctx, + asm330lhbg1_usr_off_w_t val) +{ + asm330lhbg1_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret == 0) + { + ctrl6_c.usr_off_w = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + } + return ret; +} + +/** + * @brief Weight of XL user offset bits of registers X_OFS_USR (73h), + * Y_OFS_USR (74h), Z_OFS_USR (75h).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of usr_off_w in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_offset_weight_get(const stmdev_ctx_t *ctx, + asm330lhbg1_usr_off_w_t *val) +{ + asm330lhbg1_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + + switch (ctrl6_c.usr_off_w) + { + case ASM330LHBG1_LSb_1mg: + *val = ASM330LHBG1_LSb_1mg; + break; + case ASM330LHBG1_LSb_16mg: + *val = ASM330LHBG1_LSb_16mg; + break; + default: + *val = ASM330LHBG1_LSb_1mg; + break; + } + return ret; +} + +/** + * @brief Accelerometer power mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of xl_hm_mode in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_power_mode_set(const stmdev_ctx_t *ctx, + asm330lhbg1_xl_hm_mode_t val) +{ + asm330lhbg1_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret == 0) + { + ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + } + return ret; +} + +/** + * @brief Accelerometer power mode[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of xl_hm_mode in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_power_mode_get(const stmdev_ctx_t *ctx, + asm330lhbg1_xl_hm_mode_t *val) +{ + asm330lhbg1_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + switch (ctrl6_c.xl_hm_mode) + { + case ASM330LHBG1_HIGH_PERFORMANCE_MD: + *val = ASM330LHBG1_HIGH_PERFORMANCE_MD; + break; + case ASM330LHBG1_LOW_NORMAL_POWER_MD: + *val = ASM330LHBG1_LOW_NORMAL_POWER_MD; + break; + default: + *val = ASM330LHBG1_HIGH_PERFORMANCE_MD; + break; + } + return ret; +} + +/** + * @brief Operating mode for gyroscope.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of g_hm_mode in reg CTRL7_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_gy_power_mode_set(const stmdev_ctx_t *ctx, + asm330lhbg1_g_hm_mode_t val) +{ + asm330lhbg1_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret == 0) + { + ctrl7_g.g_hm_mode = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + } + return ret; +} + +/** + * @brief gy_power_mode: [get] Operating mode for gyroscope. + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of g_hm_mode in reg CTRL7_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_gy_power_mode_get(const stmdev_ctx_t *ctx, + asm330lhbg1_g_hm_mode_t *val) +{ + asm330lhbg1_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + switch (ctrl7_g.g_hm_mode) + { + case ASM330LHBG1_GY_HIGH_PERFORMANCE: + *val = ASM330LHBG1_GY_HIGH_PERFORMANCE; + break; + case ASM330LHBG1_GY_NORMAL: + *val = ASM330LHBG1_GY_NORMAL; + break; + default: + *val = ASM330LHBG1_GY_HIGH_PERFORMANCE; + break; + } + return ret; +} + +/** + * @brief Read all the interrupt flag of the device. + *[get] + * @param ctx Read / write interface definitions.(ptr) + * @param val Get registers ALL_INT_SRC; WAKE_UP_SRC; + * TAP_SRC; D6D_SRC; STATUS_REG; + * EMB_FUNC_STATUS; FSM_STATUS_A/B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_all_sources_get(const stmdev_ctx_t *ctx, + asm330lhbg1_all_sources_t *val) +{ + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_ALL_INT_SRC, + (uint8_t *)&val->all_int_src, 1); + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_WAKE_UP_SRC, + (uint8_t *)&val->wake_up_src, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_D6D_SRC, + (uint8_t *)&val->d6d_src, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_STATUS_REG, + (uint8_t *)&val->status_reg, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_EMB_FUNC_STATUS, + (uint8_t *)&val->emb_func_status, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_STATUS_A, + (uint8_t *)&val->fsm_status_a, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_STATUS_B, + (uint8_t *)&val->fsm_status_b, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_MLC_STATUS, + (uint8_t *)&val->mlc_status, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + + return ret; +} + +/** + * @brief The STATUS_REG register is read by the primary interface.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get register STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_status_reg_get(const stmdev_ctx_t *ctx, + asm330lhbg1_status_reg_t *val) +{ + int32_t ret; + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_STATUS_REG, (uint8_t *) val, 1); + return ret; +} + +/** + * @brief Accelerometer new data available.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of xlda in reg STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_status_reg_t status_reg; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_STATUS_REG, + (uint8_t *)&status_reg, 1); + *val = status_reg.xlda; + + return ret; +} + +/** + * @brief Gyroscope new data available.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of gda in reg STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_status_reg_t status_reg; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_STATUS_REG, + (uint8_t *)&status_reg, 1); + *val = status_reg.gda; + + return ret; +} + +/** + * @brief Temperature new data available.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of tda in reg STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_status_reg_t status_reg; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_STATUS_REG, + (uint8_t *)&status_reg, 1); + *val = status_reg.tda; + + return ret; +} + +/** + * @brief Device boot status.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the device boot status in reg STATUS_REG. + * 0: OK, 1: FAIL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_boot_device_status_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_status_reg_t status_reg; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_STATUS_REG, + (uint8_t *)&status_reg, 1); + *val = status_reg.boot_check_fail; + + return ret; +} + +/** + * @brief Accelerometer X-axis user offset correction expressed in two’s + * complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * The value must be in the range [-127 127].[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_X_OFS_USR, buff, 1); + return ret; +} + +/** + * @brief Accelerometer X-axis user offset correction expressed in two’s + * complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * The value must be in the range [-127 127].[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_X_OFS_USR, buff, 1); + return ret; +} + +/** + * @brief Accelerometer Y-axis user offset correction expressed in two’s + * complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * The value must be in the range [-127 127].[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_Y_OFS_USR, buff, 1); + return ret; +} + +/** + * @brief Accelerometer Y-axis user offset correction expressed in two’s + * complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * The value must be in the range [-127 127].[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_Y_OFS_USR, buff, 1); + return ret; +} + +/** + * @brief Accelerometer Z-axis user offset correction expressed in two’s + * complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * The value must be in the range [-127 127].[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_Z_OFS_USR, buff, 1); + return ret; +} + +/** + * @brief Accelerometer X-axis user offset correction expressed in two’s + * complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * The value must be in the range [-127 127].[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_Z_OFS_USR, buff, 1); + return ret; +} + +/** + * @brief Enables user offset on out.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of usr_off_on_out in reg CTRL7_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret == 0) + { + ctrl7_g.usr_off_on_out = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + } + return ret; +} + +/** + * @brief Get user offset on out flag.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get values of usr_off_on_out in reg CTRL7_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + *val = ctrl7_g.usr_off_on_out; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHBG1_Timestamp + * @brief This section groups all the functions that manage the + * timestamp generation. + * @{ + * + */ + +/** + * @brief Reset timestamp counter.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_timestamp_rst(const stmdev_ctx_t *ctx) +{ + uint8_t rst_val = 0xAA; + + return asm330lhbg1_write_reg(ctx, ASM330LHBG1_TIMESTAMP2, &rst_val, 1); +} + +/** + * @brief Enables timestamp counter.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of timestamp_en in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + if (ret == 0) + { + ctrl10_c.timestamp_en = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL10_C, + (uint8_t *)&ctrl10_c, 1); + } + return ret; +} + +/** + * @brief Enables timestamp counter.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of timestamp_en in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + *val = ctrl10_c.timestamp_en; + + return ret; +} + +/** + * @brief Timestamp first data output register (r). + * The value is expressed as a 32-bit word and the bit resolution + * is 25 μs.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) +{ + uint8_t buff[4]; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_TIMESTAMP0, buff, 4); + *val = buff[3]; + *val = (*val * 256U) + buff[2]; + *val = (*val * 256U) + buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHBG1_Data output + * @brief This section groups all the data output functions. + * @{ + * + */ + +/** + * @brief Circular burst-mode (rounding) read of the output registers.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of rounding in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_rounding_mode_set(const stmdev_ctx_t *ctx, + asm330lhbg1_rounding_t val) +{ + asm330lhbg1_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret == 0) + { + ctrl5_c.rounding = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + } + return ret; +} + +/** + * @brief Gyroscope UI chain full-scale selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of rounding in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_rounding_mode_get(const stmdev_ctx_t *ctx, + asm330lhbg1_rounding_t *val) +{ + asm330lhbg1_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + switch (ctrl5_c.rounding) + { + case ASM330LHBG1_NO_ROUND: + *val = ASM330LHBG1_NO_ROUND; + break; + case ASM330LHBG1_ROUND_XL: + *val = ASM330LHBG1_ROUND_XL; + break; + case ASM330LHBG1_ROUND_GY: + *val = ASM330LHBG1_ROUND_GY; + break; + case ASM330LHBG1_ROUND_GY_XL: + *val = ASM330LHBG1_ROUND_GY_XL; + break; + default: + *val = ASM330LHBG1_NO_ROUND; + break; + } + return ret; +} + +/** + * @brief Temperature data output register (r). + * L and H registers together express a 16-bit word in two’s + * complement.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_OUT_TEMP_L, buff, 2); + *val = (int16_t)buff[1]; + *val = (*val * 256) + (int16_t)buff[0]; + + return ret; +} + +/** + * @brief Angular rate sensor. The value is expressed as a 16-bit + * word in two’s complement.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_OUTX_L_G, buff, 6); + + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Linear acceleration output register. The value is expressed as a + * 16-bit word in two’s complement.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_OUTX_L_A, buff, 6); + + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief FIFO data output.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + int32_t ret; + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_DATA_OUT_X_L, val, 6); + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHBG1_common + * @brief This section groups common useful functions. + * @{ + * + */ + +/** + * @brief Difference in percentage of the effective ODR (and timestamp rate) + * with respect to the typical.[set] + * Step: 0.15%. 8-bit format, 2's complement. + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_internal_freq_fine_t internal_freq_fine; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_INTERNAL_FREQ_FINE, + (uint8_t *)&internal_freq_fine, 1); + if (ret == 0) + { + internal_freq_fine.freq_fine = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_INTERNAL_FREQ_FINE, + (uint8_t *)&internal_freq_fine, 1); + } + return ret; +} + +/** + * @brief Difference in percentage of the effective ODR (and timestamp rate) + * with respect to the typical.[get] + * Step: 0.15%. 8-bit format, 2's complement. + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_internal_freq_fine_t internal_freq_fine; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_INTERNAL_FREQ_FINE, + (uint8_t *)&internal_freq_fine, 1); + *val = internal_freq_fine.freq_fine; + + return ret; +} + +/** + * @brief Enable access to the embedded functions/sensor hub configuration + * registers.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of reg_access in reg FUNC_CFG_ACCESS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_mem_bank_set(const stmdev_ctx_t *ctx, + asm330lhbg1_reg_access_t val) +{ + asm330lhbg1_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FUNC_CFG_ACCESS, + (uint8_t *)&func_cfg_access, 1); + if (ret == 0) + { + func_cfg_access.reg_access = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FUNC_CFG_ACCESS, + (uint8_t *)&func_cfg_access, 1); + } + return ret; +} + +/** + * @brief Enable access to the embedded functions/sensor hub configuration + * registers.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of reg_access in reg FUNC_CFG_ACCESS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_mem_bank_get(const stmdev_ctx_t *ctx, + asm330lhbg1_reg_access_t *val) +{ + asm330lhbg1_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FUNC_CFG_ACCESS, + (uint8_t *)&func_cfg_access, 1); + switch (func_cfg_access.reg_access) + { + case ASM330LHBG1_USER_BANK: + *val = ASM330LHBG1_USER_BANK; + break; + case ASM330LHBG1_EMBEDDED_FUNC_BANK: + *val = ASM330LHBG1_EMBEDDED_FUNC_BANK; + break; + default: + *val = ASM330LHBG1_USER_BANK; + break; + } + return ret; +} + +/** + * @brief Write a line(byte) in a page.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param add Page line address + * @param val Value to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t add, + uint8_t *val) +{ + asm330lhbg1_page_rw_t page_rw; + asm330lhbg1_page_sel_t page_sel; + asm330lhbg1_page_address_t page_address; + int32_t ret; + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + page_rw.page_rw = 0x02U; /* page_write enable */ + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_SEL, (uint8_t *)&page_sel, 1); + } + if (ret == 0) + { + page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); + page_sel.not_used_01 = 1; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + } + if (ret == 0) + { + page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_VALUE, val, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + page_rw.page_rw = 0x00; /* page_write disable */ + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + return ret; +} + +/** + * @brief Write buffer in a page.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buf Page line address.(ptr) + * @param val Value to write. + * @param len buffer lenght. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t add, + uint8_t *buf, uint8_t len) +{ + asm330lhbg1_page_rw_t page_rw; + asm330lhbg1_page_sel_t page_sel; + asm330lhbg1_page_address_t page_address; + int32_t ret; + uint8_t msb, lsb; + uint8_t i ; + + msb = (uint8_t)(add / 256U); + lsb = (uint8_t)(add - (msb * 256U)); + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + page_rw.page_rw = 0x02U; /* page_write enable*/ + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_SEL, (uint8_t *)&page_sel, 1); + } + if (ret == 0) + { + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + } + if (ret == 0) + { + page_address.page_addr = lsb; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + } + for (i = 0; i < len; i++) + { + if (ret == 0) + { + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_VALUE, &buf[i], 1); + if (ret == 0) + { + /* Check if page wrap */ + if (lsb == 0x00U) + { + msb++; + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + } + lsb++; + } + if (ret == 0) + { + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + } + } + } + + if (ret == 0) + { + page_sel.page_sel = 0; + page_sel.not_used_01 = 1; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + page_rw.page_rw = 0x00U; /* page_write disable */ + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + return ret; +} + +/** + * @brief Read a line(byte) in a page.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param add Page line address. + * @param val Read value.(ptr) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, + uint8_t *val) +{ + asm330lhbg1_page_rw_t page_rw; + asm330lhbg1_page_sel_t page_sel; + asm330lhbg1_page_address_t page_address; + int32_t ret; + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + page_rw.page_rw = 0x01U; /* page_read enable*/ + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_SEL, (uint8_t *)&page_sel, 1); + } + if (ret == 0) + { + page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); + page_sel.not_used_01 = 1; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + } + if (ret == 0) + { + page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_VALUE, val, 2); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + page_rw.page_rw = 0x00U; /* page_read disable */ + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + return ret; +} + +/** + * @brief Data-ready pulsed / letched mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of dataready_pulsed in + * reg COUNTER_BDR_REG1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_data_ready_mode_set(const stmdev_ctx_t *ctx, + asm330lhbg1_dataready_pulsed_t val) +{ + asm330lhbg1_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + if (ret == 0) + { + counter_bdr_reg1.dataready_pulsed = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + } + return ret; +} + +/** + * @brief Data-ready pulsed / letched mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of dataready_pulsed in + * reg COUNTER_BDR_REG1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_data_ready_mode_get(const stmdev_ctx_t *ctx, + asm330lhbg1_dataready_pulsed_t *val) +{ + asm330lhbg1_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + switch (counter_bdr_reg1.dataready_pulsed) + { + case ASM330LHBG1_DRDY_LATCHED: + *val = ASM330LHBG1_DRDY_LATCHED; + break; + case ASM330LHBG1_DRDY_PULSED: + *val = ASM330LHBG1_DRDY_PULSED; + break; + default: + *val = ASM330LHBG1_DRDY_LATCHED; + break; + } + return ret; +} + +/** + * @brief Device Who am I.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_WHO_AM_I, buff, 1); + return ret; +} + +/** + * @brief Software reset. Restore the default values in user registers.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sw_reset in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_reset_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret == 0) + { + ctrl3_c.sw_reset = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Software reset. Restore the default values in user registers.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sw_reset in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + *val = ctrl3_c.sw_reset; + + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte + * access with a serial interface.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of if_inc in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret == 0) + { + ctrl3_c.if_inc = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte + * access with a serial interface.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of if_inc in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + *val = ctrl3_c.if_inc; + + return ret; +} + +/** + * @brief Reboot memory content. Reload the calibration parameters.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of boot in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_boot_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret == 0) + { + ctrl3_c.boot = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Reboot memory content. Reload the calibration parameters.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of boot in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + *val = ctrl3_c.boot; + + return ret; +} + + + +/** + * @brief Linear acceleration sensor self-test enable.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of st_xl in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_self_test_set(const stmdev_ctx_t *ctx, + asm330lhbg1_st_xl_t val) +{ + asm330lhbg1_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret == 0) + { + ctrl5_c.st_xl = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + } + return ret; +} + +/** + * @brief Linear acceleration sensor self-test enable.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of st_xl in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_self_test_get(const stmdev_ctx_t *ctx, + asm330lhbg1_st_xl_t *val) +{ + asm330lhbg1_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + + switch (ctrl5_c.st_xl) + { + case ASM330LHBG1_XL_ST_DISABLE: + *val = ASM330LHBG1_XL_ST_DISABLE; + break; + case ASM330LHBG1_XL_ST_POSITIVE: + *val = ASM330LHBG1_XL_ST_POSITIVE; + break; + case ASM330LHBG1_XL_ST_NEGATIVE: + *val = ASM330LHBG1_XL_ST_NEGATIVE; + break; + default: + *val = ASM330LHBG1_XL_ST_DISABLE; + break; + } + return ret; +} + +/** + * @brief Angular rate sensor self-test enable.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of st_g in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_gy_self_test_set(const stmdev_ctx_t *ctx, + asm330lhbg1_st_g_t val) +{ + asm330lhbg1_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret == 0) + { + ctrl5_c.st_g = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + } + return ret; +} + +/** + * @brief Angular rate sensor self-test enable.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of st_g in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_gy_self_test_get(const stmdev_ctx_t *ctx, + asm330lhbg1_st_g_t *val) +{ + asm330lhbg1_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + + switch (ctrl5_c.st_g) + { + case ASM330LHBG1_GY_ST_DISABLE: + *val = ASM330LHBG1_GY_ST_DISABLE; + break; + case ASM330LHBG1_GY_ST_POSITIVE: + *val = ASM330LHBG1_GY_ST_POSITIVE; + break; + case ASM330LHBG1_GY_ST_NEGATIVE: + *val = ASM330LHBG1_GY_ST_NEGATIVE; + break; + default: + *val = ASM330LHBG1_GY_ST_DISABLE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHBG1_filters + * @brief This section group all the functions concerning the + * filters configuration + * @{ + * + */ + +/** + * @brief Accelerometer output from LPF2 filtering stage selection.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of lpf2_xl_en in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret == 0) + { + ctrl1_xl.lpf2_xl_en = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL1_XL, + (uint8_t *)&ctrl1_xl, 1); + } + return ret; +} + +/** + * @brief Accelerometer output from LPF2 filtering stage selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of lpf2_xl_en in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + *val = ctrl1_xl.lpf2_xl_en; + + return ret; +} + +/** + * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled; + * the bandwidth can be selected through FTYPE [2:0] in CTRL6_C.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of lpf1_sel_g in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret == 0) + { + ctrl4_c.lpf1_sel_g = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + } + return ret; +} + +/** + * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled; + * the bandwidth can be selected through FTYPE [2:0] in CTRL6_C.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of lpf1_sel_g in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + *val = ctrl4_c.lpf1_sel_g; + + return ret; +} + +/** + * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends + * (XL and Gyro independently masked).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of drdy_mask in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret == 0) + { + ctrl4_c.drdy_mask = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + } + return ret; +} + +/** + * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends + * (XL and Gyro independently masked).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of drdy_mask in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_filter_settling_mask_get(const stmdev_ctx_t *ctx, + uint8_t *val) +{ + asm330lhbg1_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + *val = ctrl4_c.drdy_mask; + + return ret; +} + +/** + * @brief Gyroscope low pass filter 1 bandwidth.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of ftype in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, + asm330lhbg1_ftype_t val) +{ + asm330lhbg1_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret == 0) + { + ctrl6_c.ftype = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + } + return ret; +} + +/** + * @brief Gyroscope low pass filter 1 bandwidth.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of ftype in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, + asm330lhbg1_ftype_t *val) +{ + asm330lhbg1_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + + switch (ctrl6_c.ftype) + { + case ASM330LHBG1_ULTRA_LIGHT: + *val = ASM330LHBG1_ULTRA_LIGHT; + break; + case ASM330LHBG1_VERY_LIGHT: + *val = ASM330LHBG1_VERY_LIGHT; + break; + case ASM330LHBG1_LIGHT: + *val = ASM330LHBG1_LIGHT; + break; + case ASM330LHBG1_MEDIUM: + *val = ASM330LHBG1_MEDIUM; + break; + case ASM330LHBG1_STRONG: + *val = ASM330LHBG1_STRONG; + break; + case ASM330LHBG1_VERY_STRONG: + *val = ASM330LHBG1_VERY_STRONG; + break; + case ASM330LHBG1_AGGRESSIVE: + *val = ASM330LHBG1_AGGRESSIVE; + break; + case ASM330LHBG1_XTREME: + *val = ASM330LHBG1_XTREME; + break; + default: + *val = ASM330LHBG1_ULTRA_LIGHT; + break; + } + return ret; +} + +/** + * @brief Low pass filter 2 on 6D function selection.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of low_pass_on_6d in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret == 0) + { + ctrl8_xl.low_pass_on_6d = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL8_XL, + (uint8_t *)&ctrl8_xl, 1); + } + return ret; +} + +/** + * @brief Low pass filter 2 on 6D function selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of low_pass_on_6d in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + *val = ctrl8_xl.low_pass_on_6d; + + return ret; +} + +/** + * @brief Accelerometer slope filter / high-pass filter selection + * on output.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of hp_slope_xl_en in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, + asm330lhbg1_hp_slope_xl_en_t val) +{ + asm330lhbg1_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret == 0) + { + ctrl8_xl.hp_slope_xl_en = (((uint8_t)val & 0x10U) >> 4); + ctrl8_xl.hp_ref_mode_xl = (((uint8_t)val & 0x20U) >> 5); + ctrl8_xl.hpcf_xl = (uint8_t)val & 0x07U; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL8_XL, + (uint8_t *)&ctrl8_xl, 1); + } + return ret; +} + +/** + * @brief Accelerometer slope filter / high-pass filter selection on + * output.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of hp_slope_xl_en in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, + asm330lhbg1_hp_slope_xl_en_t *val) +{ + asm330lhbg1_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + switch (((ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.hp_slope_xl_en << 4) + + ctrl8_xl.hpcf_xl)) + { + case ASM330LHBG1_HP_PATH_DISABLE_ON_OUT: + *val = ASM330LHBG1_HP_PATH_DISABLE_ON_OUT; + break; + case ASM330LHBG1_SLOPE_ODR_DIV_4: + *val = ASM330LHBG1_SLOPE_ODR_DIV_4; + break; + case ASM330LHBG1_HP_ODR_DIV_10: + *val = ASM330LHBG1_HP_ODR_DIV_10; + break; + case ASM330LHBG1_HP_ODR_DIV_20: + *val = ASM330LHBG1_HP_ODR_DIV_20; + break; + case ASM330LHBG1_HP_ODR_DIV_45: + *val = ASM330LHBG1_HP_ODR_DIV_45; + break; + case ASM330LHBG1_HP_ODR_DIV_100: + *val = ASM330LHBG1_HP_ODR_DIV_100; + break; + case ASM330LHBG1_HP_ODR_DIV_200: + *val = ASM330LHBG1_HP_ODR_DIV_200; + break; + case ASM330LHBG1_HP_ODR_DIV_400: + *val = ASM330LHBG1_HP_ODR_DIV_400; + break; + case ASM330LHBG1_HP_ODR_DIV_800: + *val = ASM330LHBG1_HP_ODR_DIV_800; + break; + case ASM330LHBG1_HP_REF_MD_ODR_DIV_10: + *val = ASM330LHBG1_HP_REF_MD_ODR_DIV_10; + break; + case ASM330LHBG1_HP_REF_MD_ODR_DIV_20: + *val = ASM330LHBG1_HP_REF_MD_ODR_DIV_20; + break; + case ASM330LHBG1_HP_REF_MD_ODR_DIV_45: + *val = ASM330LHBG1_HP_REF_MD_ODR_DIV_45; + break; + case ASM330LHBG1_HP_REF_MD_ODR_DIV_100: + *val = ASM330LHBG1_HP_REF_MD_ODR_DIV_100; + break; + case ASM330LHBG1_HP_REF_MD_ODR_DIV_200: + *val = ASM330LHBG1_HP_REF_MD_ODR_DIV_200; + break; + case ASM330LHBG1_HP_REF_MD_ODR_DIV_400: + *val = ASM330LHBG1_HP_REF_MD_ODR_DIV_400; + break; + case ASM330LHBG1_HP_REF_MD_ODR_DIV_800: + *val = ASM330LHBG1_HP_REF_MD_ODR_DIV_800; + break; + case ASM330LHBG1_LP_ODR_DIV_10: + *val = ASM330LHBG1_LP_ODR_DIV_10; + break; + case ASM330LHBG1_LP_ODR_DIV_20: + *val = ASM330LHBG1_LP_ODR_DIV_20; + break; + case ASM330LHBG1_LP_ODR_DIV_45: + *val = ASM330LHBG1_LP_ODR_DIV_45; + break; + case ASM330LHBG1_LP_ODR_DIV_100: + *val = ASM330LHBG1_LP_ODR_DIV_100; + break; + case ASM330LHBG1_LP_ODR_DIV_200: + *val = ASM330LHBG1_LP_ODR_DIV_200; + break; + case ASM330LHBG1_LP_ODR_DIV_400: + *val = ASM330LHBG1_LP_ODR_DIV_400; + break; + case ASM330LHBG1_LP_ODR_DIV_800: + *val = ASM330LHBG1_LP_ODR_DIV_800; + break; + default: + *val = ASM330LHBG1_HP_PATH_DISABLE_ON_OUT; + break; + } + return ret; +} + +/** + * @brief Enables accelerometer LPF2 and HPF fast-settling mode. + * The filter sets the second samples after writing this bit. + * Active only during device exit from powerdown mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fastsettl_mode_xl in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret == 0) + { + ctrl8_xl.fastsettl_mode_xl = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL8_XL, + (uint8_t *)&ctrl8_xl, 1); + } + return ret; +} + +/** + * @brief Enables accelerometer LPF2 and HPF fast-settling mode. + * The filter sets the second samples after writing + * this bit. Active only during device exit from powerdown mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fastsettl_mode_xl in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + *val = ctrl8_xl.fastsettl_mode_xl; + + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity + * functions.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of slope_fds in reg INT_CFG0 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, + asm330lhbg1_slope_fds_t val) +{ + asm330lhbg1_int_cfg0_t int_cfg0; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_INT_CFG0, (uint8_t *)&int_cfg0, 1); + if (ret == 0) + { + int_cfg0.slope_fds = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_INT_CFG0, + (uint8_t *)&int_cfg0, 1); + } + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity + * functions.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of slope_fds in reg INT_CFG0 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, + asm330lhbg1_slope_fds_t *val) +{ + asm330lhbg1_int_cfg0_t int_cfg0; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_INT_CFG0, (uint8_t *)&int_cfg0, 1); + switch (int_cfg0.slope_fds) + { + case ASM330LHBG1_USE_SLOPE: + *val = ASM330LHBG1_USE_SLOPE; + break; + case ASM330LHBG1_USE_HPF: + *val = ASM330LHBG1_USE_HPF; + break; + default: + *val = ASM330LHBG1_USE_SLOPE; + break; + } + return ret; +} + +/** + * @brief Enables gyroscope digital high-pass filter. The filter is enabled + * only if the gyro is in HP mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, + asm330lhbg1_hpm_g_t val) +{ + asm330lhbg1_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret == 0) + { + ctrl7_g.hp_en_g = (((uint8_t)val & 0x80U) >> 7); + ctrl7_g.hpm_g = (uint8_t)val & 0x03U; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + } + return ret; +} + +/** + * @brief Enables gyroscope digital high-pass filter. The filter is + * enabled only if the gyro is in HP mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, + asm330lhbg1_hpm_g_t *val) +{ + asm330lhbg1_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + + switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g) + { + case ASM330LHBG1_HP_FILTER_NONE: + *val = ASM330LHBG1_HP_FILTER_NONE; + break; + case ASM330LHBG1_HP_FILTER_16mHz: + *val = ASM330LHBG1_HP_FILTER_16mHz; + break; + case ASM330LHBG1_HP_FILTER_65mHz: + *val = ASM330LHBG1_HP_FILTER_65mHz; + break; + case ASM330LHBG1_HP_FILTER_260mHz: + *val = ASM330LHBG1_HP_FILTER_260mHz; + break; + case ASM330LHBG1_HP_FILTER_1Hz04: + *val = ASM330LHBG1_HP_FILTER_1Hz04; + break; + default: + *val = ASM330LHBG1_HP_FILTER_NONE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHBG1_ serial_interface + * @brief This section groups all the functions concerning main + * serial interface management (not auxiliary) + * @{ + * + */ + +/** + * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sdo_pu_en in reg PIN_CTRL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, + asm330lhbg1_sdo_pu_en_t val) +{ + asm330lhbg1_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret == 0) + { + pin_ctrl.sdo_pu_en = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + return ret; +} + +/** + * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of sdo_pu_en in reg PIN_CTRL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, + asm330lhbg1_sdo_pu_en_t *val) +{ + asm330lhbg1_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + + switch (pin_ctrl.sdo_pu_en) + { + case ASM330LHBG1_PULL_UP_DISC: + *val = ASM330LHBG1_PULL_UP_DISC; + break; + case ASM330LHBG1_PULL_UP_CONNECT: + *val = ASM330LHBG1_PULL_UP_CONNECT; + break; + default: + *val = ASM330LHBG1_PULL_UP_DISC; + break; + } + return ret; +} + +/** + * @brief Connect/Disconnect INT1 pull-down.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of pd_dis_int1 in reg I3C_BUS_AVB + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_int1_mode_set(const stmdev_ctx_t *ctx, + asm330lhbg1_pd_dis_int1_t val) +{ + asm330lhbg1_i3c_bus_avb_t i3c_bus_avb; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_I3C_BUS_AVB, (uint8_t *)&i3c_bus_avb, 1); + if (ret == 0) + { + i3c_bus_avb.pd_dis_int1 = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_I3C_BUS_AVB, + (uint8_t *)&i3c_bus_avb, 1); + } + return ret; +} + +/** + * @brief Connect/Disconnect INT1 pull-down.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of pd_dis_int1 in reg I3C_BUS_AVB + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_int1_mode_get(const stmdev_ctx_t *ctx, + asm330lhbg1_pd_dis_int1_t *val) +{ + asm330lhbg1_i3c_bus_avb_t i3c_bus_avb; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_I3C_BUS_AVB, (uint8_t *)&i3c_bus_avb, 1); + + switch (i3c_bus_avb.pd_dis_int1) + { + case ASM330LHBG1_PULL_DOWN_CONNECT: + *val = ASM330LHBG1_PULL_DOWN_CONNECT; + break; + case ASM330LHBG1_PULL_DOWN_DISC: + *val = ASM330LHBG1_PULL_DOWN_DISC; + break; + default: + *val = ASM330LHBG1_PULL_DOWN_CONNECT; + break; + } + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sim in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_spi_mode_set(const stmdev_ctx_t *ctx, asm330lhbg1_sim_t val) +{ + asm330lhbg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret == 0) + { + ctrl3_c.sim = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of sim in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_spi_mode_get(const stmdev_ctx_t *ctx, asm330lhbg1_sim_t *val) +{ + asm330lhbg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + switch (ctrl3_c.sim) + { + case ASM330LHBG1_SPI_4_WIRE: + *val = ASM330LHBG1_SPI_4_WIRE; + break; + case ASM330LHBG1_SPI_3_WIRE: + *val = ASM330LHBG1_SPI_3_WIRE; + break; + default: + *val = ASM330LHBG1_SPI_4_WIRE; + break; + } + return ret; +} + +/** + * @brief Disable / Enable I2C interface.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of i2c_disable in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_i2c_interface_set(const stmdev_ctx_t *ctx, + asm330lhbg1_i2c_disable_t val) +{ + asm330lhbg1_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret == 0) + { + ctrl4_c.i2c_disable = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + } + return ret; +} + +/** + * @brief Disable / Enable I2C interface.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of i2c reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_i2c_interface_get(const stmdev_ctx_t *ctx, + asm330lhbg1_i2c_disable_t *val) +{ + asm330lhbg1_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + switch (ctrl4_c.i2c_disable) + { + case ASM330LHBG1_I2C_ENABLE: + *val = ASM330LHBG1_I2C_ENABLE; + break; + case ASM330LHBG1_I2C_DISABLE: + *val = ASM330LHBG1_I2C_DISABLE; + break; + default: + *val = ASM330LHBG1_I2C_ENABLE; + break; + } + return ret; +} + +/** + * @brief I3C Enable/Disable communication protocol.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of i3c_disable in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_i3c_disable_set(const stmdev_ctx_t *ctx, + asm330lhbg1_i3c_disable_t val) +{ + asm330lhbg1_ctrl9_xl_t ctrl9_xl; + asm330lhbg1_i3c_bus_avb_t i3c_bus_avb; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret == 0) + { + ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL9_XL, + (uint8_t *)&ctrl9_xl, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_I3C_BUS_AVB, + (uint8_t *)&i3c_bus_avb, 1); + } + if (ret == 0) + { + i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_I3C_BUS_AVB, + (uint8_t *)&i3c_bus_avb, 1); + } + return ret; +} + +/** + * @brief I3C Enable/Disable communication protocol.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of i3c_disable in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_i3c_disable_get(const stmdev_ctx_t *ctx, + asm330lhbg1_i3c_disable_t *val) +{ + asm330lhbg1_ctrl9_xl_t ctrl9_xl; + asm330lhbg1_i3c_bus_avb_t i3c_bus_avb; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_I3C_BUS_AVB, + (uint8_t *)&i3c_bus_avb, 1); + } + switch ((ctrl9_xl.i3c_disable << 7) + i3c_bus_avb.i3c_bus_avb_sel) + { + case ASM330LHBG1_I3C_DISABLE: + *val = ASM330LHBG1_I3C_DISABLE; + break; + case ASM330LHBG1_I3C_ENABLE_T_50us: + *val = ASM330LHBG1_I3C_ENABLE_T_50us; + break; + case ASM330LHBG1_I3C_ENABLE_T_2us: + *val = ASM330LHBG1_I3C_ENABLE_T_2us; + break; + case ASM330LHBG1_I3C_ENABLE_T_1ms: + *val = ASM330LHBG1_I3C_ENABLE_T_1ms; + break; + case ASM330LHBG1_I3C_ENABLE_T_25ms: + *val = ASM330LHBG1_I3C_ENABLE_T_25ms; + break; + default: + *val = ASM330LHBG1_I3C_DISABLE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHBG1_interrupt_pins + * @brief This section groups all the functions that manage + * interrupt pins + * @{ + * + */ + +/** + * @brief Select the signal that need to route on int1 pad.[set] + * + * @param ctx read / write interface definitions + * @param val struct of registers: INT1_CTRL, + * MD1_CFG, EMB_FUNC_INT1, FSM_INT1_A, + * FSM_INT1_B + * + */ +int32_t asm330lhbg1_pin_int1_route_set(const stmdev_ctx_t *ctx, + asm330lhbg1_pin_int1_route_t *val) +{ + asm330lhbg1_pin_int2_route_t pin_int2_route; + asm330lhbg1_int_cfg1_t int_cfg1; + int32_t ret; + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_MLC_INT1, + (uint8_t *)&val->mlc_int1, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_EMB_FUNC_INT1, + (uint8_t *)&val->emb_func_int1, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FSM_INT1_A, + (uint8_t *)&val->fsm_int1_a, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FSM_INT1_B, + (uint8_t *)&val->fsm_int1_b, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + + if (ret == 0) + { + if ((val->emb_func_int1.int1_fsm_lc + | val->fsm_int1_a.int1_fsm1 + | val->fsm_int1_a.int1_fsm2 + | val->fsm_int1_a.int1_fsm3 + | val->fsm_int1_a.int1_fsm4 + | val->fsm_int1_a.int1_fsm5 + | val->fsm_int1_a.int1_fsm6 + | val->fsm_int1_a.int1_fsm7 + | val->fsm_int1_a.int1_fsm8 + | val->fsm_int1_b.int1_fsm9 + | val->fsm_int1_b.int1_fsm10 + | val->fsm_int1_b.int1_fsm11 + | val->fsm_int1_b.int1_fsm12 + | val->fsm_int1_b.int1_fsm13 + | val->fsm_int1_b.int1_fsm14 + | val->fsm_int1_b.int1_fsm15 + | val->fsm_int1_b.int1_fsm16 + | val->mlc_int1.int1_mlc1 + | val->mlc_int1.int1_mlc2 + | val->mlc_int1.int1_mlc3 + | val->mlc_int1.int1_mlc4 + | val->mlc_int1.int1_mlc5 + | val->mlc_int1.int1_mlc6 + | val->mlc_int1.int1_mlc7 + | val->mlc_int1.int1_mlc8) != PROPERTY_DISABLE) + { + val->md1_cfg.int1_emb_func = PROPERTY_ENABLE; + } + else + { + val->md1_cfg.int1_emb_func = PROPERTY_DISABLE; + } + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_INT1_CTRL, + (uint8_t *)&val->int1_ctrl, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_MD1_CFG, (uint8_t *)&val->md1_cfg, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_INT_CFG1, (uint8_t *) &int_cfg1, 1); + } + + if (ret == 0) + { + ret = asm330lhbg1_pin_int2_route_get(ctx, &pin_int2_route); + } + if (ret == 0) + { + if ((pin_int2_route.int2_ctrl.int2_cnt_bdr + | pin_int2_route.int2_ctrl.int2_drdy_g + | pin_int2_route.int2_ctrl.int2_drdy_temp + | pin_int2_route.int2_ctrl.int2_drdy_xl + | pin_int2_route.int2_ctrl.int2_fifo_full + | pin_int2_route.int2_ctrl.int2_fifo_ovr + | pin_int2_route.int2_ctrl.int2_fifo_th + | pin_int2_route.md2_cfg.int2_6d + | pin_int2_route.md2_cfg.int2_ff + | pin_int2_route.md2_cfg.int2_wu + | pin_int2_route.md2_cfg.int2_sleep_change + | val->int1_ctrl.den_drdy_flag + | val->int1_ctrl.int1_boot + | val->int1_ctrl.int1_cnt_bdr + | val->int1_ctrl.int1_drdy_g + | val->int1_ctrl.int1_drdy_xl + | val->int1_ctrl.int1_fifo_full + | val->int1_ctrl.int1_fifo_ovr + | val->int1_ctrl.int1_fifo_th + | val->md1_cfg.int1_6d + | val->md1_cfg.int1_ff + | val->md1_cfg.int1_wu + | val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE) + { + int_cfg1.interrupts_enable = PROPERTY_ENABLE; + } + else + { + int_cfg1.interrupts_enable = PROPERTY_DISABLE; + } + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_INT_CFG1, (uint8_t *) &int_cfg1, 1); + } + return ret; +} + +/** + * @brief Select the signal that need to route on int1 pad.[get] + * + * @param ctx read / write interface definitions + * @param val struct of registers: INT1_CTRL, MD1_CFG, + * EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B + * + */ +int32_t asm330lhbg1_pin_int1_route_get(const stmdev_ctx_t *ctx, + asm330lhbg1_pin_int1_route_t *val) +{ + int32_t ret; + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_MLC_INT1, + (uint8_t *)&val->mlc_int1, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_EMB_FUNC_INT1, + (uint8_t *)&val->emb_func_int1, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_INT1_A, + (uint8_t *)&val->fsm_int1_a, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_INT1_B, + (uint8_t *)&val->fsm_int1_b, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + if (ret == 0) + { + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_INT1_CTRL, + (uint8_t *)&val->int1_ctrl, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_MD1_CFG, (uint8_t *)&val->md1_cfg, 1); + } + + return ret; +} + +/** + * @brief Select the signal that need to route on int2 pad.[set] + * + * @param ctx read / write interface definitions + * @param val union of registers INT2_CTRL, MD2_CFG, + * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B + * + */ +int32_t asm330lhbg1_pin_int2_route_set(const stmdev_ctx_t *ctx, + asm330lhbg1_pin_int2_route_t *val) +{ + asm330lhbg1_pin_int1_route_t pin_int1_route; + asm330lhbg1_int_cfg1_t int_cfg1; + int32_t ret; + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_MLC_INT2, + (uint8_t *)&val->mlc_int2, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_EMB_FUNC_INT2, + (uint8_t *)&val->emb_func_int2, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FSM_INT2_A, + (uint8_t *)&val->fsm_int2_a, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FSM_INT2_B, + (uint8_t *)&val->fsm_int2_b, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + + if (ret == 0) + { + if ((val->emb_func_int2.int2_fsm_lc + | val->fsm_int2_a.int2_fsm1 + | val->fsm_int2_a.int2_fsm2 + | val->fsm_int2_a.int2_fsm3 + | val->fsm_int2_a.int2_fsm4 + | val->fsm_int2_a.int2_fsm5 + | val->fsm_int2_a.int2_fsm6 + | val->fsm_int2_a.int2_fsm7 + | val->fsm_int2_a.int2_fsm8 + | val->fsm_int2_b.int2_fsm9 + | val->fsm_int2_b.int2_fsm10 + | val->fsm_int2_b.int2_fsm11 + | val->fsm_int2_b.int2_fsm12 + | val->fsm_int2_b.int2_fsm13 + | val->fsm_int2_b.int2_fsm14 + | val->fsm_int2_b.int2_fsm15 + | val->fsm_int2_b.int2_fsm16 + | val->mlc_int2.int2_mlc1 + | val->mlc_int2.int2_mlc2 + | val->mlc_int2.int2_mlc3 + | val->mlc_int2.int2_mlc4 + | val->mlc_int2.int2_mlc5 + | val->mlc_int2.int2_mlc6 + | val->mlc_int2.int2_mlc7 + | val->mlc_int2.int2_mlc8) != PROPERTY_DISABLE) + { + val->md2_cfg.int2_emb_func = PROPERTY_ENABLE; + } + else + { + val->md2_cfg.int2_emb_func = PROPERTY_DISABLE; + } + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_INT2_CTRL, + (uint8_t *)&val->int2_ctrl, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_MD2_CFG, (uint8_t *)&val->md2_cfg, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_INT_CFG1, (uint8_t *) &int_cfg1, 1); + } + + if (ret == 0) + { + ret = asm330lhbg1_pin_int1_route_get(ctx, &pin_int1_route); + } + + if (ret == 0) + { + if ((val->int2_ctrl.int2_cnt_bdr + | val->int2_ctrl.int2_drdy_g + | val->int2_ctrl.int2_drdy_temp + | val->int2_ctrl.int2_drdy_xl + | val->int2_ctrl.int2_fifo_full + | val->int2_ctrl.int2_fifo_ovr + | val->int2_ctrl.int2_fifo_th + | val->md2_cfg.int2_6d + | val->md2_cfg.int2_ff + | val->md2_cfg.int2_wu + | val->md2_cfg.int2_sleep_change + | pin_int1_route.int1_ctrl.den_drdy_flag + | pin_int1_route.int1_ctrl.int1_boot + | pin_int1_route.int1_ctrl.int1_cnt_bdr + | pin_int1_route.int1_ctrl.int1_drdy_g + | pin_int1_route.int1_ctrl.int1_drdy_xl + | pin_int1_route.int1_ctrl.int1_fifo_full + | pin_int1_route.int1_ctrl.int1_fifo_ovr + | pin_int1_route.int1_ctrl.int1_fifo_th + | pin_int1_route.md1_cfg.int1_6d + | pin_int1_route.md1_cfg.int1_ff + | pin_int1_route.md1_cfg.int1_wu + | pin_int1_route.md1_cfg.int1_sleep_change) != PROPERTY_DISABLE) + { + int_cfg1.interrupts_enable = PROPERTY_ENABLE; + } + else + { + int_cfg1.interrupts_enable = PROPERTY_DISABLE; + } + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_INT_CFG1, (uint8_t *) &int_cfg1, 1); + } + return ret; +} + +/** + * @brief Select the signal that need to route on int2 pad.[get] + * + * @param ctx read / write interface definitions + * @param val union of registers INT2_CTRL, MD2_CFG, + * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B + * + */ +int32_t asm330lhbg1_pin_int2_route_get(const stmdev_ctx_t *ctx, + asm330lhbg1_pin_int2_route_t *val) +{ + int32_t ret; + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_MLC_INT2, + (uint8_t *)&val->mlc_int2, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_EMB_FUNC_INT2, + (uint8_t *)&val->emb_func_int2, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_INT2_A, + (uint8_t *)&val->fsm_int2_a, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_INT2_B, + (uint8_t *)&val->fsm_int2_b, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + if (ret == 0) + { + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_INT2_CTRL, + (uint8_t *)&val->int2_ctrl, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_MD2_CFG, (uint8_t *)&val->md2_cfg, 1); + } + return ret; +} + +/** + * @brief Push-pull/open drain selection on interrupt pads.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of pp_od in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_pin_mode_set(const stmdev_ctx_t *ctx, asm330lhbg1_pp_od_t val) +{ + asm330lhbg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret == 0) + { + ctrl3_c.pp_od = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Push-pull/open drain selection on interrupt pads.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of pp_od in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_pin_mode_get(const stmdev_ctx_t *ctx, asm330lhbg1_pp_od_t *val) +{ + asm330lhbg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + switch (ctrl3_c.pp_od) + { + case ASM330LHBG1_PUSH_PULL: + *val = ASM330LHBG1_PUSH_PULL; + break; + case ASM330LHBG1_OPEN_DRAIN: + *val = ASM330LHBG1_OPEN_DRAIN; + break; + default: + *val = ASM330LHBG1_PUSH_PULL; + break; + } + return ret; +} + +/** + * @brief Interrupt active-high/low.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of h_lactive in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_pin_polarity_set(const stmdev_ctx_t *ctx, + asm330lhbg1_h_lactive_t val) +{ + asm330lhbg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret == 0) + { + ctrl3_c.h_lactive = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Interrupt active-high/low.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of h_lactive in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_pin_polarity_get(const stmdev_ctx_t *ctx, + asm330lhbg1_h_lactive_t *val) +{ + asm330lhbg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + switch (ctrl3_c.h_lactive) + { + case ASM330LHBG1_ACTIVE_HIGH: + *val = ASM330LHBG1_ACTIVE_HIGH; + break; + case ASM330LHBG1_ACTIVE_LOW: + *val = ASM330LHBG1_ACTIVE_LOW; + break; + default: + *val = ASM330LHBG1_ACTIVE_HIGH; + break; + } + return ret; +} + +/** + * @brief All interrupt signals become available on INT1 pin.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of int2_on_int1 in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret == 0) + { + ctrl4_c.int2_on_int1 = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + } + return ret; +} + +/** + * @brief All interrupt signals become available on INT1 pin.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of int2_on_int1 in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + *val = ctrl4_c.int2_on_int1; + + return ret; +} + +/** + * @brief All interrupt signals notification mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of lir in reg INT_CFG0 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_int_notification_set(const stmdev_ctx_t *ctx, + asm330lhbg1_lir_t val) +{ + asm330lhbg1_int_cfg0_t int_cfg0; + asm330lhbg1_page_rw_t page_rw; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_INT_CFG0, (uint8_t *)&int_cfg0, 1); + if (ret == 0) + { + int_cfg0.lir = (uint8_t)val & 0x01U; + int_cfg0.int_clr_on_read = (uint8_t)val & 0x01U; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_INT_CFG0, + (uint8_t *)&int_cfg0, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + return ret; +} + +/** + * @brief All interrupt signals notification mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of lir in reg INT_CFG0 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_int_notification_get(const stmdev_ctx_t *ctx, + asm330lhbg1_lir_t *val) +{ + asm330lhbg1_int_cfg0_t int_cfg0; + asm330lhbg1_page_rw_t page_rw; + int32_t ret; + + *val = ASM330LHBG1_ALL_INT_PULSED; + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_INT_CFG0, (uint8_t *)&int_cfg0, 1); + + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + switch ((page_rw.emb_func_lir << 1) + int_cfg0.lir) + { + case ASM330LHBG1_ALL_INT_PULSED: + *val = ASM330LHBG1_ALL_INT_PULSED; + break; + case ASM330LHBG1_BASE_LATCHED_EMB_PULSED: + *val = ASM330LHBG1_BASE_LATCHED_EMB_PULSED; + break; + case ASM330LHBG1_BASE_PULSED_EMB_LATCHED: + *val = ASM330LHBG1_BASE_PULSED_EMB_LATCHED; + break; + case ASM330LHBG1_ALL_INT_LATCHED: + *val = ASM330LHBG1_ALL_INT_LATCHED; + break; + default: + *val = ASM330LHBG1_ALL_INT_PULSED; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHBG1_Wake_Up_event + * @brief This section groups all the functions that manage the + * Wake Up event generation. + * @{ + * + */ + +/** + * @brief Weight of 1 LSB of wakeup threshold.[set] + * 0: 1 LSB =FS_XL / 64 + * 1: 1 LSB = FS_XL / 256 + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of wake_ths_w in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_wkup_ths_weight_set(const stmdev_ctx_t *ctx, + asm330lhbg1_wake_ths_w_t val) +{ + asm330lhbg1_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + wake_up_dur.wake_ths_w = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + } + return ret; +} + +/** + * @brief Weight of 1 LSB of wakeup threshold.[get] + * 0: 1 LSB =FS_XL / 64 + * 1: 1 LSB = FS_XL / 256 + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of wake_ths_w in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_wkup_ths_weight_get(const stmdev_ctx_t *ctx, + asm330lhbg1_wake_ths_w_t *val) +{ + asm330lhbg1_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + + switch (wake_up_dur.wake_ths_w) + { + case ASM330LHBG1_LSb_FS_DIV_64: + *val = ASM330LHBG1_LSb_FS_DIV_64; + break; + case ASM330LHBG1_LSb_FS_DIV_256: + *val = ASM330LHBG1_LSb_FS_DIV_256; + break; + default: + *val = ASM330LHBG1_LSb_FS_DIV_64; + break; + } + return ret; +} + +/** + * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in + * WAKE_UP_DUR.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of wk_ths in reg WAKE_UP_THS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_WAKE_UP_THS, + (uint8_t *)&wake_up_ths, 1); + if (ret == 0) + { + wake_up_ths.wk_ths = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_WAKE_UP_THS, + (uint8_t *)&wake_up_ths, 1); + } + return ret; +} + +/** + * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in + * WAKE_UP_DUR.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of wk_ths in reg WAKE_UP_THS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_WAKE_UP_THS, + (uint8_t *)&wake_up_ths, 1); + *val = wake_up_ths.wk_ths; + + return ret; +} + +/** + * @brief Wake up duration event( 1LSb = 1 / ODR ).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of usr_off_on_wu in reg WAKE_UP_THS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_WAKE_UP_THS, + (uint8_t *)&wake_up_ths, 1); + if (ret == 0) + { + wake_up_ths.usr_off_on_wu = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_WAKE_UP_THS, + (uint8_t *)&wake_up_ths, 1); + } + return ret; +} + +/** + * @brief Wake up duration event( 1LSb = 1 / ODR ).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of usr_off_on_wu in reg WAKE_UP_THS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, + uint8_t *val) +{ + asm330lhbg1_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_WAKE_UP_THS, + (uint8_t *)&wake_up_ths, 1); + *val = wake_up_ths.usr_off_on_wu; + + return ret; +} + +/** + * @brief Wake up duration event(1LSb = 1 / ODR).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of wake_dur in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + wake_up_dur.wake_dur = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + } + return ret; +} + +/** + * @brief Wake up duration event(1LSb = 1 / ODR).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of wake_dur in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + *val = wake_up_dur.wake_dur; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHBG1_ Activity/Inactivity_detection + * @brief This section groups all the functions concerning + * activity/inactivity detection. + * @{ + * + */ + +/** + * @brief Enables gyroscope Sleep mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sleep_g in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret == 0) + { + ctrl4_c.sleep_g = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + } + return ret; +} + +/** + * @brief Enables gyroscope Sleep mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sleep_g in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + *val = ctrl4_c.sleep_g; + + return ret; +} + +/** + * @brief Drives the sleep status instead of sleep change on INT pins + * (only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits + * are enabled).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sleep_status_on_int in reg INT_CFG0 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_act_pin_notification_set(const stmdev_ctx_t *ctx, + asm330lhbg1_sleep_status_on_int_t val) +{ + asm330lhbg1_int_cfg0_t int_cfg0; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_INT_CFG0, (uint8_t *)&int_cfg0, 1); + if (ret == 0) + { + int_cfg0. sleep_status_on_int = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_INT_CFG0, + (uint8_t *)&int_cfg0, 1); + } + return ret; +} + +/** + * @brief Drives the sleep status instead of sleep change on INT pins + * (only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits + * are enabled).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of sleep_status_on_int in reg INT_CFG0 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_act_pin_notification_get(const stmdev_ctx_t *ctx, + asm330lhbg1_sleep_status_on_int_t *val) +{ + asm330lhbg1_int_cfg0_t int_cfg0; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_INT_CFG0, (uint8_t *)&int_cfg0, 1); + switch (int_cfg0. sleep_status_on_int) + { + case ASM330LHBG1_DRIVE_SLEEP_CHG_EVENT: + *val = ASM330LHBG1_DRIVE_SLEEP_CHG_EVENT; + break; + case ASM330LHBG1_DRIVE_SLEEP_STATUS: + *val = ASM330LHBG1_DRIVE_SLEEP_STATUS; + break; + default: + *val = ASM330LHBG1_DRIVE_SLEEP_CHG_EVENT; + break; + } + return ret; +} + +/** + * @brief Enable inactivity function.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of inact_en in reg INT_CFG1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_act_mode_set(const stmdev_ctx_t *ctx, asm330lhbg1_inact_en_t val) +{ + asm330lhbg1_int_cfg1_t int_cfg1; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_INT_CFG1, (uint8_t *)&int_cfg1, 1); + if (ret == 0) + { + int_cfg1.inact_en = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_INT_CFG1, (uint8_t *)&int_cfg1, 1); + } + return ret; +} + +/** + * @brief Enable inactivity function.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of inact_en in reg INT_CFG1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_act_mode_get(const stmdev_ctx_t *ctx, + asm330lhbg1_inact_en_t *val) +{ + asm330lhbg1_int_cfg1_t int_cfg1; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_INT_CFG1, (uint8_t *)&int_cfg1, 1); + + switch (int_cfg1.inact_en) + { + case ASM330LHBG1_XL_AND_GY_NOT_AFFECTED: + *val = ASM330LHBG1_XL_AND_GY_NOT_AFFECTED; + break; + case ASM330LHBG1_XL_12Hz5_GY_NOT_AFFECTED: + *val = ASM330LHBG1_XL_12Hz5_GY_NOT_AFFECTED; + break; + case ASM330LHBG1_XL_12Hz5_GY_SLEEP: + *val = ASM330LHBG1_XL_12Hz5_GY_SLEEP; + break; + case ASM330LHBG1_XL_12Hz5_GY_PD: + *val = ASM330LHBG1_XL_12Hz5_GY_PD; + break; + default: + *val = ASM330LHBG1_XL_AND_GY_NOT_AFFECTED; + break; + } + return ret; +} + +/** + * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sleep_dur in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + wake_up_dur.sleep_dur = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + } + return ret; +} + +/** + * @brief Duration to go in sleep mode.(1 LSb = 512 / ODR).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sleep_dur in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + *val = wake_up_dur.sleep_dur; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHBG1_ Six_position_detection(6D/4D) + * @brief This section groups all the functions concerning six + * position detection (6D). + * @{ + * + */ + +/** + * @brief Threshold for 4D/6D function.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sixd_ths in reg TAP_THS_6D + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_6d_threshold_set(const stmdev_ctx_t *ctx, + asm330lhbg1_sixd_ths_t val) +{ + asm330lhbg1_ths_6d_t ths_6d; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_THS_6D, + (uint8_t *)&ths_6d, 1); + if (ret == 0) + { + ths_6d.sixd_ths = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_THS_6D, + (uint8_t *)&ths_6d, 1); + } + return ret; +} + +/** + * @brief Threshold for 4D/6D function.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of sixd_ths in reg TAP_THS_6D + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_6d_threshold_get(const stmdev_ctx_t *ctx, + asm330lhbg1_sixd_ths_t *val) +{ + asm330lhbg1_ths_6d_t ths_6d; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_THS_6D, + (uint8_t *)&ths_6d, 1); + + switch (ths_6d.sixd_ths) + { + case ASM330LHBG1_DEG_80: + *val = ASM330LHBG1_DEG_80; + break; + case ASM330LHBG1_DEG_70: + *val = ASM330LHBG1_DEG_70; + break; + case ASM330LHBG1_DEG_60: + *val = ASM330LHBG1_DEG_60; + break; + case ASM330LHBG1_DEG_50: + *val = ASM330LHBG1_DEG_50; + break; + default: + *val = ASM330LHBG1_DEG_80; + break; + } + return ret; +} + +/** + * @brief 4D orientation detection enable.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of d4d_en in reg TAP_THS_6D + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_ths_6d_t ths_6d; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_THS_6D, + (uint8_t *)&ths_6d, 1); + if (ret == 0) + { + ths_6d.d4d_en = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_THS_6D, + (uint8_t *)&ths_6d, 1); + } + return ret; +} + +/** + * @brief 4D orientation detection enable.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of d4d_en in reg TAP_THS_6D + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_ths_6d_t ths_6d; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_THS_6D, + (uint8_t *)&ths_6d, 1); + *val = ths_6d.d4d_en; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHBG1_free_fall + * @brief This section group all the functions concerning the free + * fall detection. + * @{ + * + */ + +/** + * @brief Free fall threshold setting.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of ff_ths in reg FREE_FALL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_ff_threshold_set(const stmdev_ctx_t *ctx, + asm330lhbg1_ff_ths_t val) +{ + asm330lhbg1_free_fall_t free_fall; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret == 0) + { + free_fall.ff_ths = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FREE_FALL, + (uint8_t *)&free_fall, 1); + } + return ret; +} + +/** + * @brief Free fall threshold setting.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of ff_ths in reg FREE_FALL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_ff_threshold_get(const stmdev_ctx_t *ctx, + asm330lhbg1_ff_ths_t *val) +{ + asm330lhbg1_free_fall_t free_fall; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FREE_FALL, (uint8_t *)&free_fall, 1); + + switch (free_fall.ff_ths) + { + case ASM330LHBG1_FF_TSH_156mg: + *val = ASM330LHBG1_FF_TSH_156mg; + break; + case ASM330LHBG1_FF_TSH_219mg: + *val = ASM330LHBG1_FF_TSH_219mg; + break; + case ASM330LHBG1_FF_TSH_250mg: + *val = ASM330LHBG1_FF_TSH_250mg; + break; + case ASM330LHBG1_FF_TSH_312mg: + *val = ASM330LHBG1_FF_TSH_312mg; + break; + case ASM330LHBG1_FF_TSH_344mg: + *val = ASM330LHBG1_FF_TSH_344mg; + break; + case ASM330LHBG1_FF_TSH_406mg: + *val = ASM330LHBG1_FF_TSH_406mg; + break; + case ASM330LHBG1_FF_TSH_469mg: + *val = ASM330LHBG1_FF_TSH_469mg; + break; + case ASM330LHBG1_FF_TSH_500mg: + *val = ASM330LHBG1_FF_TSH_500mg; + break; + default: + *val = ASM330LHBG1_FF_TSH_156mg; + break; + } + return ret; +} + +/** + * @brief Free-fall duration event(1LSb = 1 / ODR).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of ff_dur in reg FREE_FALL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_wake_up_dur_t wake_up_dur; + asm330lhbg1_free_fall_t free_fall; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + wake_up_dur.ff_dur = (val & 0x20U) >> 5; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FREE_FALL, + (uint8_t *)&free_fall, 1); + } + if (ret == 0) + { + free_fall.ff_dur = val & 0x1FU; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FREE_FALL, + (uint8_t *)&free_fall, 1); + } + return ret; +} + +/** + * @brief Free-fall duration event(1LSb = 1 / ODR).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of ff_dur in reg FREE_FALL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_wake_up_dur_t wake_up_dur; + asm330lhbg1_free_fall_t free_fall; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FREE_FALL, + (uint8_t *)&free_fall, 1); + } + *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHBG1_fifo + * @brief This section group all the functions concerning + * the fifo usage + * @{ + * + */ + +/** + * @brief FIFO watermark level selection.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of wtm in reg FIFO_CTRL1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + asm330lhbg1_fifo_ctrl1_t fifo_ctrl1; + asm330lhbg1_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.wtm = (uint8_t)((val / 256U) & 0x01U); + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + } + if (ret == 0) + { + fifo_ctrl1.wtm = (uint8_t)(val - (fifo_ctrl2.wtm * 256U)); + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FIFO_CTRL1, + (uint8_t *)&fifo_ctrl1, 1); + } + + return ret; +} + +/** + * @brief FIFO watermark level selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of wtm in reg FIFO_CTRL1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + asm330lhbg1_fifo_ctrl1_t fifo_ctrl1; + asm330lhbg1_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL1, + (uint8_t *)&fifo_ctrl1, 1); + } + *val = fifo_ctrl2.wtm; + *val = (*val * 256U) + fifo_ctrl1.wtm; + return ret; +} + +/** + * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of odrchg_en in reg FIFO_CTRL2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, + uint8_t val) +{ + asm330lhbg1_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.odrchg_en = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of odrchg_en in reg FIFO_CTRL2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, + uint8_t *val) +{ + asm330lhbg1_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.odrchg_en; + + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at threshold + * level.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of stop_on_wtm in reg FIFO_CTRL2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.stop_on_wtm = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + } + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at threshold + * level.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of stop_on_wtm in reg FIFO_CTRL2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.stop_on_wtm; + + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for accelerometer data.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of bdr_xl in reg FIFO_CTRL3 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fifo_xl_batch_set(const stmdev_ctx_t *ctx, + asm330lhbg1_bdr_xl_t val) +{ + asm330lhbg1_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL3, + (uint8_t *)&fifo_ctrl3, 1); + if (ret == 0) + { + fifo_ctrl3.bdr_xl = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FIFO_CTRL3, + (uint8_t *)&fifo_ctrl3, 1); + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for accelerometer data.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of bdr_xl in reg FIFO_CTRL3 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fifo_xl_batch_get(const stmdev_ctx_t *ctx, + asm330lhbg1_bdr_xl_t *val) +{ + asm330lhbg1_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL3, + (uint8_t *)&fifo_ctrl3, 1); + + switch (fifo_ctrl3.bdr_xl) + { + case ASM330LHBG1_XL_NOT_BATCHED: + *val = ASM330LHBG1_XL_NOT_BATCHED; + break; + case ASM330LHBG1_XL_BATCHED_AT_12Hz5: + *val = ASM330LHBG1_XL_BATCHED_AT_12Hz5; + break; + case ASM330LHBG1_XL_BATCHED_AT_26Hz: + *val = ASM330LHBG1_XL_BATCHED_AT_26Hz; + break; + case ASM330LHBG1_XL_BATCHED_AT_52Hz: + *val = ASM330LHBG1_XL_BATCHED_AT_52Hz; + break; + case ASM330LHBG1_XL_BATCHED_AT_104Hz: + *val = ASM330LHBG1_XL_BATCHED_AT_104Hz; + break; + case ASM330LHBG1_XL_BATCHED_AT_208Hz: + *val = ASM330LHBG1_XL_BATCHED_AT_208Hz; + break; + case ASM330LHBG1_XL_BATCHED_AT_417Hz: + *val = ASM330LHBG1_XL_BATCHED_AT_417Hz; + break; + case ASM330LHBG1_XL_BATCHED_AT_833Hz: + *val = ASM330LHBG1_XL_BATCHED_AT_833Hz; + break; + case ASM330LHBG1_XL_BATCHED_AT_1667Hz: + *val = ASM330LHBG1_XL_BATCHED_AT_1667Hz; + break; + case ASM330LHBG1_XL_BATCHED_AT_1Hz6: + *val = ASM330LHBG1_XL_BATCHED_AT_1Hz6; + break; + default: + *val = ASM330LHBG1_XL_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for gyroscope data.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of bdr_gy in reg FIFO_CTRL3 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fifo_gy_batch_set(const stmdev_ctx_t *ctx, + asm330lhbg1_bdr_gy_t val) +{ + asm330lhbg1_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL3, + (uint8_t *)&fifo_ctrl3, 1); + if (ret == 0) + { + fifo_ctrl3.bdr_gy = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FIFO_CTRL3, + (uint8_t *)&fifo_ctrl3, 1); + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for gyroscope data.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of bdr_gy in reg FIFO_CTRL3 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fifo_gy_batch_get(const stmdev_ctx_t *ctx, + asm330lhbg1_bdr_gy_t *val) +{ + asm330lhbg1_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL3, + (uint8_t *)&fifo_ctrl3, 1); + + switch (fifo_ctrl3.bdr_gy) + { + case ASM330LHBG1_GY_NOT_BATCHED: + *val = ASM330LHBG1_GY_NOT_BATCHED; + break; + case ASM330LHBG1_GY_BATCHED_AT_12Hz5: + *val = ASM330LHBG1_GY_BATCHED_AT_12Hz5; + break; + case ASM330LHBG1_GY_BATCHED_AT_26Hz: + *val = ASM330LHBG1_GY_BATCHED_AT_26Hz; + break; + case ASM330LHBG1_GY_BATCHED_AT_52Hz: + *val = ASM330LHBG1_GY_BATCHED_AT_52Hz; + break; + case ASM330LHBG1_GY_BATCHED_AT_104Hz: + *val = ASM330LHBG1_GY_BATCHED_AT_104Hz; + break; + case ASM330LHBG1_GY_BATCHED_AT_208Hz: + *val = ASM330LHBG1_GY_BATCHED_AT_208Hz; + break; + case ASM330LHBG1_GY_BATCHED_AT_417Hz: + *val = ASM330LHBG1_GY_BATCHED_AT_417Hz; + break; + case ASM330LHBG1_GY_BATCHED_AT_833Hz: + *val = ASM330LHBG1_GY_BATCHED_AT_833Hz; + break; + case ASM330LHBG1_GY_BATCHED_AT_1667Hz: + *val = ASM330LHBG1_GY_BATCHED_AT_1667Hz; + break; + case ASM330LHBG1_GY_BATCHED_AT_6Hz5: + *val = ASM330LHBG1_GY_BATCHED_AT_6Hz5; + break; + default: + *val = ASM330LHBG1_GY_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief FIFO mode selection.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fifo_mode in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fifo_mode_set(const stmdev_ctx_t *ctx, + asm330lhbg1_fifo_mode_t val) +{ + asm330lhbg1_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.fifo_mode = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + } + return ret; +} + +/** + * @brief FIFO mode selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of fifo_mode in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fifo_mode_get(const stmdev_ctx_t *ctx, + asm330lhbg1_fifo_mode_t *val) +{ + asm330lhbg1_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + + switch (fifo_ctrl4.fifo_mode) + { + case ASM330LHBG1_BYPASS_MODE: + *val = ASM330LHBG1_BYPASS_MODE; + break; + case ASM330LHBG1_FIFO_MODE: + *val = ASM330LHBG1_FIFO_MODE; + break; + case ASM330LHBG1_STREAM_TO_FIFO_MODE: + *val = ASM330LHBG1_STREAM_TO_FIFO_MODE; + break; + case ASM330LHBG1_BYPASS_TO_STREAM_MODE: + *val = ASM330LHBG1_BYPASS_TO_STREAM_MODE; + break; + case ASM330LHBG1_STREAM_MODE: + *val = ASM330LHBG1_STREAM_MODE; + break; + case ASM330LHBG1_BYPASS_TO_FIFO_MODE: + *val = ASM330LHBG1_BYPASS_TO_FIFO_MODE; + break; + default: + *val = ASM330LHBG1_BYPASS_MODE; + break; + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for temperature data.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of odr_t_batch in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fifo_temp_batch_set(const stmdev_ctx_t *ctx, + asm330lhbg1_odr_t_batch_t val) +{ + asm330lhbg1_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.odr_t_batch = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for temperature data.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of odr_t_batch in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fifo_temp_batch_get(const stmdev_ctx_t *ctx, + asm330lhbg1_odr_t_batch_t *val) +{ + asm330lhbg1_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + + switch (fifo_ctrl4.odr_t_batch) + { + case ASM330LHBG1_TEMP_NOT_BATCHED: + *val = ASM330LHBG1_TEMP_NOT_BATCHED; + break; + case ASM330LHBG1_TEMP_BATCHED_AT_52Hz: + *val = ASM330LHBG1_TEMP_BATCHED_AT_52Hz; + break; + case ASM330LHBG1_TEMP_BATCHED_AT_12Hz5: + *val = ASM330LHBG1_TEMP_BATCHED_AT_12Hz5; + break; + case ASM330LHBG1_TEMP_BATCHED_AT_1Hz6: + *val = ASM330LHBG1_TEMP_BATCHED_AT_1Hz6; + break; + default: + *val = ASM330LHBG1_TEMP_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief Selects decimation for timestamp batching in FIFO. + * Writing rate will be the maximum rate between XL and + * GYRO BDR divided by decimation decoder.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of dec_ts_batch in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, + asm330lhbg1_dec_ts_batch_t val) +{ + asm330lhbg1_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.dec_ts_batch = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + } + return ret; +} + +/** + * @brief Selects decimation for timestamp batching in FIFO. + * Writing rate will be the maximum rate between XL and + * GYRO BDR divided by decimation decoder.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of dec_ts_batch in reg + * FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, + asm330lhbg1_dec_ts_batch_t *val) +{ + asm330lhbg1_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + + switch (fifo_ctrl4.dec_ts_batch) + { + case ASM330LHBG1_NO_DECIMATION: + *val = ASM330LHBG1_NO_DECIMATION; + break; + case ASM330LHBG1_DEC_1: + *val = ASM330LHBG1_DEC_1; + break; + case ASM330LHBG1_DEC_8: + *val = ASM330LHBG1_DEC_8; + break; + case ASM330LHBG1_DEC_32: + *val = ASM330LHBG1_DEC_32; + break; + default: + *val = ASM330LHBG1_NO_DECIMATION; + break; + } + return ret; +} + +/** + * @brief Selects the trigger for the internal counter of batching events + * between XL and gyro.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of trig_counter_bdr in + * reg COUNTER_BDR_REG1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, + asm330lhbg1_trig_counter_bdr_t val) +{ + asm330lhbg1_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + if (ret == 0) + { + counter_bdr_reg1.trig_counter_bdr = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + } + return ret; +} + +/** + * @brief Selects the trigger for the internal counter of batching events + * between XL and gyro.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of trig_counter_bdr + * in reg COUNTER_BDR_REG1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, + asm330lhbg1_trig_counter_bdr_t *val) +{ + asm330lhbg1_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + + switch (counter_bdr_reg1.trig_counter_bdr) + { + case ASM330LHBG1_XL_BATCH_EVENT: + *val = ASM330LHBG1_XL_BATCH_EVENT; + break; + case ASM330LHBG1_GYRO_BATCH_EVENT: + *val = ASM330LHBG1_GYRO_BATCH_EVENT; + break; + default: + *val = ASM330LHBG1_XL_BATCH_EVENT; + break; + } + return ret; +} + +/** + * @brief Resets the internal counter of batching events for a single sensor. + * This bit is automatically reset to zero if it was set to ‘1’.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of rst_counter_bdr in reg COUNTER_BDR_REG1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + if (ret == 0) + { + counter_bdr_reg1.rst_counter_bdr = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + } + return ret; +} + +/** + * @brief Resets the internal counter of batching events for a single sensor. + * This bit is automatically reset to zero if it was set to ‘1’.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of rst_counter_bdr in reg COUNTER_BDR_REG1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + *val = counter_bdr_reg1.rst_counter_bdr; + + return ret; +} + +/** + * @brief Batch data rate counter.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of cnt_bdr_th in reg COUNTER_BDR_REG2 + * and COUNTER_BDR_REG1. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + asm330lhbg1_counter_bdr_reg2_t counter_bdr_reg1; + asm330lhbg1_counter_bdr_reg2_t counter_bdr_reg2; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + if (ret == 0) + { + counter_bdr_reg1.cnt_bdr_th = (uint8_t)((val / 256U) & 0x07U); + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + } + if (ret == 0) + { + counter_bdr_reg2.cnt_bdr_th = (uint8_t)(val - (counter_bdr_reg1.cnt_bdr_th * 256U)); + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_COUNTER_BDR_REG2, + (uint8_t *)&counter_bdr_reg2, 1); + } + return ret; +} + +/** + * @brief Batch data rate counter.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of cnt_bdr_th in reg COUNTER_BDR_REG2 + * and COUNTER_BDR_REG1. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_batch_counter_threshold_get(const stmdev_ctx_t *ctx, + uint16_t *val) +{ + asm330lhbg1_counter_bdr_reg1_t counter_bdr_reg1; + asm330lhbg1_counter_bdr_reg2_t counter_bdr_reg2; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_COUNTER_BDR_REG2, + (uint8_t *)&counter_bdr_reg2, 1); + } + + *val = counter_bdr_reg1.cnt_bdr_th; + *val = (*val * 256U) + counter_bdr_reg2.cnt_bdr_th; + return ret; +} + +/** + * @brief Number of unread sensor data (TAG + 6 bytes) stored in FIFO.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of diff_fifo in reg FIFO_STATUS1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + asm330lhbg1_fifo_status1_t fifo_status1; + asm330lhbg1_fifo_status2_t fifo_status2; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_STATUS1, + (uint8_t *)&fifo_status1, 1); + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_STATUS2, + (uint8_t *)&fifo_status2, 1); + + *val = fifo_status2.diff_fifo; + *val = (*val * 256U) + fifo_status1.diff_fifo; + } + return ret; +} + +/** + * @brief Smart FIFO status.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Registers FIFO_STATUS2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fifo_status_get(const stmdev_ctx_t *ctx, + asm330lhbg1_fifo_status2_t *val) +{ + int32_t ret; + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_STATUS2, (uint8_t *)val, 1); + return ret; +} + +/** + * @brief Smart FIFO full status.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fifo_full_ia in reg FIFO_STATUS2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_fifo_status2_t fifo_status2; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_STATUS2, + (uint8_t *)&fifo_status2, 1); + *val = fifo_status2.fifo_full_ia; + + return ret; +} + +/** + * @brief FIFO overrun status.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fifo_over_run_latched in + * reg FIFO_STATUS2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_fifo_status2_t fifo_status2; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_STATUS2, + (uint8_t *)&fifo_status2, 1); + *val = fifo_status2. fifo_ovr_ia; + + return ret; +} + +/** + * @brief FIFO watermark status.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fifo_wtm_ia in reg FIFO_STATUS2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_fifo_status2_t fifo_status2; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_STATUS2, + (uint8_t *)&fifo_status2, 1); + *val = fifo_status2.fifo_wtm_ia; + + return ret; +} + +/** + * @brief Identifies the sensor in FIFO_DATA_OUT.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of tag_sensor in reg FIFO_DATA_OUT_TAG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, + asm330lhbg1_fifo_tag_t *val) +{ + asm330lhbg1_fifo_data_out_tag_t fifo_data_out_tag; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FIFO_DATA_OUT_TAG, + (uint8_t *)&fifo_data_out_tag, 1); + + switch (fifo_data_out_tag.tag_sensor) + { + case ASM330LHBG1_GYRO_NC_TAG: + *val = ASM330LHBG1_GYRO_NC_TAG; + break; + case ASM330LHBG1_XL_NC_TAG: + *val = ASM330LHBG1_XL_NC_TAG; + break; + case ASM330LHBG1_TEMPERATURE_TAG: + *val = ASM330LHBG1_TEMPERATURE_TAG; + break; + case ASM330LHBG1_TIMESTAMP_TAG: + *val = ASM330LHBG1_TIMESTAMP_TAG; + break; + case ASM330LHBG1_CFG_CHANGE_TAG: + *val = ASM330LHBG1_CFG_CHANGE_TAG; + break; + default: + *val = ASM330LHBG1_XL_NC_TAG; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHBG1_DEN_functionality + * @brief This section groups all the functions concerning + * DEN functionality. + * @{ + * + */ + +/** + * @brief DEN functionality marking mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of den_mode in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_den_mode_set(const stmdev_ctx_t *ctx, asm330lhbg1_den_mode_t val) +{ + asm330lhbg1_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret == 0) + { + ctrl6_c.den_mode = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + } + return ret; +} + +/** + * @brief DEN functionality marking mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of den_mode in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_den_mode_get(const stmdev_ctx_t *ctx, + asm330lhbg1_den_mode_t *val) +{ + asm330lhbg1_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + + switch (ctrl6_c.den_mode) + { + case ASM330LHBG1_DEN_DISABLE: + *val = ASM330LHBG1_DEN_DISABLE; + break; + case ASM330LHBG1_LEVEL_FIFO: + *val = ASM330LHBG1_LEVEL_FIFO; + break; + case ASM330LHBG1_LEVEL_LETCHED: + *val = ASM330LHBG1_LEVEL_LETCHED; + break; + case ASM330LHBG1_LEVEL_TRIGGER: + *val = ASM330LHBG1_LEVEL_TRIGGER; + break; + case ASM330LHBG1_EDGE_TRIGGER: + *val = ASM330LHBG1_EDGE_TRIGGER; + break; + default: + *val = ASM330LHBG1_DEN_DISABLE; + break; + } + return ret; +} + +/** + * @brief DEN active level configuration.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of den_lh in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_den_polarity_set(const stmdev_ctx_t *ctx, + asm330lhbg1_den_lh_t val) +{ + asm330lhbg1_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret == 0) + { + ctrl9_xl.den_lh = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL9_XL, + (uint8_t *)&ctrl9_xl, 1); + } + return ret; +} + +/** + * @brief DEN active level configuration.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of den_lh in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_den_polarity_get(const stmdev_ctx_t *ctx, + asm330lhbg1_den_lh_t *val) +{ + asm330lhbg1_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + + switch (ctrl9_xl.den_lh) + { + case ASM330LHBG1_DEN_ACT_LOW: + *val = ASM330LHBG1_DEN_ACT_LOW; + break; + case ASM330LHBG1_DEN_ACT_HIGH: + *val = ASM330LHBG1_DEN_ACT_HIGH; + break; + default: + *val = ASM330LHBG1_DEN_ACT_LOW; + break; + } + return ret; +} + +/** + * @brief DEN configuration.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of den_xl_g in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_den_enable_set(const stmdev_ctx_t *ctx, + asm330lhbg1_den_xl_g_t val) +{ + asm330lhbg1_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret == 0) + { + ctrl9_xl.den_xl_g = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL9_XL, + (uint8_t *)&ctrl9_xl, 1); + } + return ret; +} + +/** + * @brief DEN configuration.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of den_xl_g in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_den_enable_get(const stmdev_ctx_t *ctx, + asm330lhbg1_den_xl_g_t *val) +{ + asm330lhbg1_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + + switch (ctrl9_xl.den_xl_g) + { + case ASM330LHBG1_STAMP_IN_GY_DATA: + *val = ASM330LHBG1_STAMP_IN_GY_DATA; + break; + case ASM330LHBG1_STAMP_IN_XL_DATA: + *val = ASM330LHBG1_STAMP_IN_XL_DATA; + break; + case ASM330LHBG1_STAMP_IN_GY_XL_DATA: + *val = ASM330LHBG1_STAMP_IN_GY_XL_DATA; + break; + default: + *val = ASM330LHBG1_STAMP_IN_GY_DATA; + break; + } + return ret; +} + +/** + * @brief DEN value stored in LSB of X-axis.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of den_z in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret == 0) + { + ctrl9_xl.den_z = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL9_XL, + (uint8_t *)&ctrl9_xl, 1); + } + return ret; +} + +/** + * @brief DEN value stored in LSB of X-axis.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of den_z in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + *val = ctrl9_xl.den_z; + + return ret; +} + +/** + * @brief DEN value stored in LSB of Y-axis.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of den_y in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret == 0) + { + ctrl9_xl.den_y = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL9_XL, + (uint8_t *)&ctrl9_xl, 1); + } + return ret; +} + +/** + * @brief DEN value stored in LSB of Y-axis.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of den_y in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + *val = ctrl9_xl.den_y; + + return ret; +} + +/** + * @brief DEN value stored in LSB of Z-axis.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of den_x in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret == 0) + { + ctrl9_xl.den_x = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + } + return ret; +} + +/** + * @brief DEN value stored in LSB of Z-axis.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of den_x in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + *val = ctrl9_xl.den_x; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHBG1_finite_state_machine + * @brief This section groups all the functions that manage the + * state_machine. + * @{ + * + */ + +/** + * @brief FSM status register[get] + * + * @param ctx read / write interface definitions + * @param val register ASM330LHBG1_FSM_STATUS_A_MAINPAGE, + * ASM330LHBG1_FSM_STATUS_B_MAINPAGE + * + */ +int32_t asm330lhbg1_fsm_status_get(const stmdev_ctx_t *ctx, + asm330lhbg1_fsm_status_t *val) +{ + asm330lhbg1_fsm_status_a_mainpage_t status_a; + asm330lhbg1_fsm_status_b_mainpage_t status_b; + int32_t ret; + + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_STATUS_A_MAINPAGE, + (uint8_t *)&status_a, 1); + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_STATUS_B_MAINPAGE, + (uint8_t *)&status_b, 1); + + val->fsm1 = status_a.is_fsm1; + val->fsm2 = status_a.is_fsm2; + val->fsm3 = status_a.is_fsm3; + val->fsm4 = status_a.is_fsm4; + val->fsm5 = status_a.is_fsm5; + val->fsm6 = status_a.is_fsm6; + val->fsm7 = status_a.is_fsm7; + val->fsm8 = status_a.is_fsm8; + val->fsm9 = status_b.is_fsm9; + val->fsm10 = status_b.is_fsm10; + val->fsm11 = status_b.is_fsm11; + val->fsm12 = status_b.is_fsm12; + val->fsm13 = status_b.is_fsm13; + val->fsm14 = status_b.is_fsm14; + val->fsm15 = status_b.is_fsm15; + val->fsm16 = status_b.is_fsm16; + return ret; +} + +/** + * @brief prgsens_out: [get] Output value of all FSMs. + * + * @param ctx_t *ctx: read / write interface definitions + * @param uint8_t * : buffer that stores data read + * + */ +int32_t asm330lhbg1_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_OUTS1, buff, 16); + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + return ret; +} + +/** + * @brief Interrupt status bit for FSM long counter timeout interrupt + * event.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of is_fsm_lc in reg EMB_FUNC_STATUS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, + uint8_t *val) +{ + asm330lhbg1_emb_func_status_t emb_func_status; + int32_t ret; + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_EMB_FUNC_STATUS, + (uint8_t *)&emb_func_status, 1); + } + if (ret == 0) + { + *val = emb_func_status.is_fsm_lc; + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + return ret; +} + +int32_t asm330lhbg1_emb_func_clk_dis_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_page_sel_t page_sel; + int32_t ret; + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + + page_sel.emb_func_clk_dis = val; + } + + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + + return ret; +} + +int32_t asm330lhbg1_emb_func_clk_dis_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_page_sel_t page_sel; + int32_t ret; + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + + *val = page_sel.emb_func_clk_dis; + } + + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + + return ret; +} + +/** + * @brief Embedded final state machine functions mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fsm_en in reg EMB_FUNC_EN_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + int32_t ret; + asm330lhbg1_emb_func_en_b_t emb_func_en_b; + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + emb_func_en_b.fsm_en = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + return ret; +} + +/** + * @brief Embedded final state machine functions mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of fsm_en in reg EMB_FUNC_EN_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + int32_t ret; + asm330lhbg1_emb_func_en_b_t emb_func_en_b; + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + *val = emb_func_en_b.fsm_en; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + return ret; +} + +/** + * @brief Embedded final state machine functions mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fsm_enable_set(const stmdev_ctx_t *ctx, + asm330lhbg1_emb_fsm_enable_t *val) +{ + asm330lhbg1_emb_func_en_b_t emb_func_en_b; + int32_t ret; + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FSM_ENABLE_A, + (uint8_t *)&val->fsm_enable_a, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FSM_ENABLE_B, + (uint8_t *)&val->fsm_enable_b, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + if ((val->fsm_enable_a.fsm1_en | + val->fsm_enable_a.fsm2_en | + val->fsm_enable_a.fsm3_en | + val->fsm_enable_a.fsm4_en | + val->fsm_enable_a.fsm5_en | + val->fsm_enable_a.fsm6_en | + val->fsm_enable_a.fsm7_en | + val->fsm_enable_a.fsm8_en | + val->fsm_enable_b.fsm9_en | + val->fsm_enable_b.fsm10_en | + val->fsm_enable_b.fsm11_en | + val->fsm_enable_b.fsm12_en | + val->fsm_enable_b.fsm13_en | + val->fsm_enable_b.fsm14_en | + val->fsm_enable_b.fsm15_en | + val->fsm_enable_b.fsm16_en) != PROPERTY_DISABLE) + { + emb_func_en_b.fsm_en = PROPERTY_ENABLE; + } + else + { + emb_func_en_b.fsm_en = PROPERTY_DISABLE; + } + } + if (ret == 0) + { + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + return ret; +} + +/** + * @brief Embedded final state machine functions mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fsm_enable_get(const stmdev_ctx_t *ctx, + asm330lhbg1_emb_fsm_enable_t *val) +{ + int32_t ret; + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_ENABLE_A, + (uint8_t *)&val->fsm_enable_a, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_ENABLE_B, + (uint8_t *)&val->fsm_enable_b, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an + * unsigned integer value (16-bit format).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FSM_LONG_COUNTER_L, buff, 2); + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an + * unsigned integer value (16-bit format).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_LONG_COUNTER_L, buff, 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + return ret; +} + +/** + * @brief Clear FSM long counter value.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fsm_lc_clr in reg + * FSM_LONG_COUNTER_CLEAR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_long_clr_set(const stmdev_ctx_t *ctx, + asm330lhbg1_fsm_lc_clr_t val) +{ + asm330lhbg1_fsm_long_counter_clear_t fsm_long_counter_clear; + int32_t ret; + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_LONG_COUNTER_CLEAR, + (uint8_t *)&fsm_long_counter_clear, 1); + } + if (ret == 0) + { + fsm_long_counter_clear.fsm_lc_clr = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_FSM_LONG_COUNTER_CLEAR, + (uint8_t *)&fsm_long_counter_clear, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + return ret; +} + +/** + * @brief Clear FSM long counter value.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of fsm_lc_clr in reg FSM_LONG_COUNTER_CLEAR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_long_clr_get(const stmdev_ctx_t *ctx, + asm330lhbg1_fsm_lc_clr_t *val) +{ + asm330lhbg1_fsm_long_counter_clear_t fsm_long_counter_clear; + int32_t ret; + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_FSM_LONG_COUNTER_CLEAR, + (uint8_t *)&fsm_long_counter_clear, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + switch (fsm_long_counter_clear.fsm_lc_clr) + { + case ASM330LHBG1_LC_NORMAL: + *val = ASM330LHBG1_LC_NORMAL; + break; + case ASM330LHBG1_LC_CLEAR: + *val = ASM330LHBG1_LC_CLEAR; + break; + case ASM330LHBG1_LC_CLEAR_DONE: + *val = ASM330LHBG1_LC_CLEAR_DONE; + break; + default: + *val = ASM330LHBG1_LC_NORMAL; + break; + } + return ret; +} + +/** + * @brief Finite State Machine ODR configuration.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fsm_data_rate_set(const stmdev_ctx_t *ctx, + asm330lhbg1_fsm_odr_t val) +{ + asm330lhbg1_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; + int32_t ret; + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_EMB_FUNC_ODR_CFG_B, + (uint8_t *)&emb_func_odr_cfg_b, 1); + } + if (ret == 0) + { + emb_func_odr_cfg_b.not_used_01 = 3; /* set default values */ + emb_func_odr_cfg_b.not_used_02 = 1; /* set default values */ + emb_func_odr_cfg_b.fsm_odr = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_EMB_FUNC_ODR_CFG_B, + (uint8_t *)&emb_func_odr_cfg_b, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + return ret; +} + +/** + * @brief Finite State Machine ODR configuration.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fsm_data_rate_get(const stmdev_ctx_t *ctx, + asm330lhbg1_fsm_odr_t *val) +{ + asm330lhbg1_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; + int32_t ret; + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_EMB_FUNC_ODR_CFG_B, + (uint8_t *)&emb_func_odr_cfg_b, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + switch (emb_func_odr_cfg_b.fsm_odr) + { + case ASM330LHBG1_ODR_FSM_12Hz5: + *val = ASM330LHBG1_ODR_FSM_12Hz5; + break; + case ASM330LHBG1_ODR_FSM_26Hz: + *val = ASM330LHBG1_ODR_FSM_26Hz; + break; + case ASM330LHBG1_ODR_FSM_52Hz: + *val = ASM330LHBG1_ODR_FSM_52Hz; + break; + case ASM330LHBG1_ODR_FSM_104Hz: + *val = ASM330LHBG1_ODR_FSM_104Hz; + break; + default: + *val = ASM330LHBG1_ODR_FSM_12Hz5; + break; + } + return ret; +} + +/** + * @brief FSM initialization request.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fsm_init in reg FSM_INIT + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_emb_func_init_b_t emb_func_init_b; + int32_t ret; + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); + } + if (ret == 0) + { + emb_func_init_b.fsm_init = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + return ret; +} + +/** + * @brief FSM initialization request.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fsm_init in reg FSM_INIT + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_emb_func_init_b_t emb_func_init_b; + int32_t ret; + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); + } + if (ret == 0) + { + *val = emb_func_init_b.fsm_init; + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + return ret; +} + +/** + * @brief FSM long counter timeout register (r/w). The long counter + * timeout value is an unsigned integer value (16-bit format). + * When the long counter value reached this value, the FSM + * generates an interrupt.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = asm330lhbg1_ln_pg_write_byte(ctx, ASM330LHBG1_FSM_LC_TIMEOUT_L, &buff[0]); + + if (ret == 0) + { + ret = asm330lhbg1_ln_pg_write_byte(ctx, ASM330LHBG1_FSM_LC_TIMEOUT_H, + &buff[1]); + } + return ret; +} + +/** + * @brief FSM long counter timeout register (r/w). The long counter + * timeout value is an unsigned integer value (16-bit format). + * When the long counter value reached this value, the FSM generates + * an interrupt.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = asm330lhbg1_ln_pg_read_byte(ctx, ASM330LHBG1_FSM_LC_TIMEOUT_L, &buff[0]); + + if (ret == 0) + { + ret = asm330lhbg1_ln_pg_read_byte(ctx, ASM330LHBG1_FSM_LC_TIMEOUT_H, + &buff[1]); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } + return ret; +} + +/** + * @brief FSM number of programs register.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = asm330lhbg1_ln_pg_write_byte(ctx, ASM330LHBG1_FSM_PROGRAMS, buff); + + if (ret == 0) + { + ret = asm330lhbg1_ln_pg_write_byte(ctx, ASM330LHBG1_FSM_PROGRAMS + 0x01U, + buff); + } + return ret; +} + +/** + * @brief FSM number of programs register.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = asm330lhbg1_ln_pg_read_byte(ctx, ASM330LHBG1_FSM_PROGRAMS, buff); + + return ret; +} + +/** + * @brief FSM start address register (r/w). First available address is + * 0x033C.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + + ret = asm330lhbg1_ln_pg_write_byte(ctx, ASM330LHBG1_FSM_START_ADD_L, &buff[0]); + if (ret == 0) + { + ret = asm330lhbg1_ln_pg_write_byte(ctx, ASM330LHBG1_FSM_START_ADD_H, &buff[1]); + } + return ret; +} + +/** + * @brief FSM start address register (r/w). First available address + * is 0x033C.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = asm330lhbg1_ln_pg_read_byte(ctx, ASM330LHBG1_FSM_START_ADD_L, &buff[0]); + if (ret == 0) + { + ret = asm330lhbg1_ln_pg_read_byte(ctx, ASM330LHBG1_FSM_START_ADD_H, &buff[1]); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @addtogroup Machine Learning Core + * @brief This section group all the functions concerning the + * usage of Machine Learning Core + * @{ + * + */ + +/** + * @brief Enable Machine Learning Core.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of mlc_en in + * reg EMB_FUNC_EN_B and mlc_init + * in EMB_FUNC_INIT_B + * + */ +int32_t asm330lhbg1_mlc_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_emb_func_en_b_t reg; + int32_t ret; + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_EMB_FUNC_EN_B, (uint8_t *)®, 1); + } + if (ret == 0) + { + reg.mlc_en = val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_EMB_FUNC_EN_B, (uint8_t *)®, 1); + } + if ((val != PROPERTY_DISABLE) && (ret == 0)) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_EMB_FUNC_INIT_B, + (uint8_t *)®, 1); + if (ret == 0) + { + reg.mlc_en = val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_EMB_FUNC_INIT_B, + (uint8_t *)®, 1); + } + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + return ret; +} + +/** + * @brief Enable Machine Learning Core.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of mlc_en in + * reg EMB_FUNC_EN_B + * + */ +int32_t asm330lhbg1_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_emb_func_en_b_t reg; + int32_t ret; + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_EMB_FUNC_EN_B, (uint8_t *)®, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + *val = reg.mlc_en; + } + return ret; +} + +/** + * @brief Machine Learning Core status register[get] + * + * @param ctx read / write interface definitions + * @param val register MLC_STATUS_MAINPAGE + * + */ +int32_t asm330lhbg1_mlc_status_get(const stmdev_ctx_t *ctx, + asm330lhbg1_mlc_status_mainpage_t *val) +{ + return asm330lhbg1_read_reg(ctx, ASM330LHBG1_MLC_STATUS_MAINPAGE, + (uint8_t *) val, 1); +} + +/** + * @brief Machine Learning Core data rate selection.[set] + * + * @param ctx read / write interface definitions + * @param val get the values of mlc_odr in + * reg EMB_FUNC_ODR_CFG_C + * + */ +int32_t asm330lhbg1_mlc_data_rate_set(const stmdev_ctx_t *ctx, + asm330lhbg1_mlc_odr_t val) +{ + asm330lhbg1_emb_func_odr_cfg_c_t reg; + int32_t ret; + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_EMB_FUNC_ODR_CFG_C, + (uint8_t *)®, 1); + } + if (ret == 0) + { + reg.mlc_odr = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_EMB_FUNC_ODR_CFG_C, + (uint8_t *)®, 1); + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + + return ret; +} + +/** + * @brief Machine Learning Core data rate selection.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of mlc_odr in + * reg EMB_FUNC_ODR_CFG_C + * + */ +int32_t asm330lhbg1_mlc_data_rate_get(const stmdev_ctx_t *ctx, + asm330lhbg1_mlc_odr_t *val) +{ + asm330lhbg1_emb_func_odr_cfg_c_t reg; + int32_t ret; + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_EMB_FUNC_ODR_CFG_C, + (uint8_t *)®, 1); + } + if (ret == 0) + { + switch (reg.mlc_odr) + { + case ASM330LHBG1_ODR_PRGS_12Hz5: + *val = ASM330LHBG1_ODR_PRGS_12Hz5; + break; + case ASM330LHBG1_ODR_PRGS_26Hz: + *val = ASM330LHBG1_ODR_PRGS_26Hz; + break; + case ASM330LHBG1_ODR_PRGS_52Hz: + *val = ASM330LHBG1_ODR_PRGS_52Hz; + break; + case ASM330LHBG1_ODR_PRGS_104Hz: + *val = ASM330LHBG1_ODR_PRGS_104Hz; + break; + default: + *val = ASM330LHBG1_ODR_PRGS_12Hz5; + break; + } + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + return ret; +} + +/** + * @brief MLC initialization request.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of mlc_init + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_mlc_init_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhbg1_emb_func_init_b_t emb_func_init_b; + int32_t ret; + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); + } + if (ret == 0) + { + emb_func_init_b.mlc_init = (uint8_t)val; + ret = asm330lhbg1_write_reg(ctx, ASM330LHBG1_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); + } + + ret += asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + + return ret; +} + +/** + * @brief MLC initialization request.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of mlc_init + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhbg1_mlc_init_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhbg1_emb_func_init_b_t emb_func_init_b; + int32_t ret; + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); + } + if (ret == 0) + { + *val = emb_func_init_b.mlc_init; + } + + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + + return ret; +} + +/** + * @brief prgsens_out: [get] Output value of all MLCx decision trees. + * + * @param ctx_t *ctx: read / write interface definitions + * @param uint8_t * : buffer that stores data read + * + */ +int32_t asm330lhbg1_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhbg1_read_reg(ctx, ASM330LHBG1_MLC0_SRC, buff, 8); + } + if (ret == 0) + { + ret = asm330lhbg1_mem_bank_set(ctx, ASM330LHBG1_USER_BANK); + } + return ret; +} + +/** + * @} + * + */ + +/** + * @} + * + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/asm330lhbg1_STdC/driver/asm330lhbg1_reg.h b/sensor/stmemsc/asm330lhbg1_STdC/driver/asm330lhbg1_reg.h new file mode 100644 index 00000000..ac1961ca --- /dev/null +++ b/sensor/stmemsc/asm330lhbg1_STdC/driver/asm330lhbg1_reg.h @@ -0,0 +1,2699 @@ +/* + ****************************************************************************** + * @file asm330lhbg1_reg.h + * @author Sensor Solutions Software Team + * @brief This file contains all the functions prototypes for the + * asm330lhbg1_reg.c driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2023 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef ASM330LHBG1_REGS_H +#define ASM330LHBG1_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include + +/** @addtogroup ASM330LHBG1 + * @{ + * + */ + +/** @defgroup Endianness definitions + * @{ + * + */ + +#ifndef DRV_BYTE_ORDER +#ifndef __BYTE_ORDER__ + +#define DRV_LITTLE_ENDIAN 1234 +#define DRV_BIG_ENDIAN 4321 + +/** if _BYTE_ORDER is not defined, choose the endianness of your architecture + * by uncommenting the define which fits your platform endianness + */ +//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN +#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN + +#else /* defined __BYTE_ORDER__ */ + +#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ +#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ +#define DRV_BYTE_ORDER __BYTE_ORDER__ + +#endif /* __BYTE_ORDER__*/ +#endif /* DRV_BYTE_ORDER */ + +/** + * @} + * + */ + +/** @defgroup STMicroelectronics sensors common types + * @{ + * + */ + +#ifndef MEMS_SHARED_TYPES +#define MEMS_SHARED_TYPES + +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} bitwise_t; + +#define PROPERTY_DISABLE (0U) +#define PROPERTY_ENABLE (1U) + +/** @addtogroup Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); +typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); + +typedef struct +{ + /** Component mandatory fields **/ + stmdev_write_ptr write_reg; + stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; + /** Customizable optional pointer **/ + void *handle; +} stmdev_ctx_t; + +/** + * @} + * + */ + +#endif /* MEMS_SHARED_TYPES */ + +#ifndef MEMS_UCF_SHARED_TYPES +#define MEMS_UCF_SHARED_TYPES + +/** @defgroup Generic address-data structure definition + * @brief This structure is useful to load a predefined configuration + * of a sensor. + * You can create a sensor configuration by your own or using + * Unico / Unicleo tools available on STMicroelectronics + * web site. + * + * @{ + * + */ + +typedef struct +{ + uint8_t address; + uint8_t data; +} ucf_line_t; + +/** + * @} + * + */ + +#endif /* MEMS_UCF_SHARED_TYPES */ + +/** + * @} + * + */ + +/** @defgroup ASM330LHBG1 Infos + * @{ + * + */ + +/** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ +#define ASM330LHBG1_I2C_ADD_L 0xD5U +#define ASM330LHBG1_I2C_ADD_H 0xD7U + +/** Device Identification (Who am I) **/ +#define ASM330LHBG1_ID 0x6BU + +/** + * @} + * + */ + +#define ASM330LHBG1_FUNC_CFG_ACCESS 0x01U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 7; + uint8_t reg_access : 1; /* func_cfg_access */ +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t reg_access : 1; /* func_cfg_access */ + uint8_t not_used_01 : 7; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_func_cfg_access_t; + +#define ASM330LHBG1_PIN_CTRL 0x02U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 6; + uint8_t sdo_pu_en : 1; + uint8_t not_used_02 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 1; + uint8_t sdo_pu_en : 1; + uint8_t not_used_01 : 6; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_pin_ctrl_t; + +#define ASM330LHBG1_FIFO_CTRL1 0x07U +typedef struct +{ + uint8_t wtm : 8; +} asm330lhbg1_fifo_ctrl1_t; + +#define ASM330LHBG1_FIFO_CTRL2 0x08U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wtm : 1; + uint8_t not_used_01 : 3; + uint8_t odrchg_en : 1; + uint8_t not_used_02 : 2; + uint8_t stop_on_wtm : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t stop_on_wtm : 1; + uint8_t not_used_02 : 2; + uint8_t odrchg_en : 1; + uint8_t not_used_01 : 3; + uint8_t wtm : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fifo_ctrl2_t; + +#define ASM330LHBG1_FIFO_CTRL3 0x09U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bdr_xl : 4; + uint8_t bdr_gy : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bdr_gy : 4; + uint8_t bdr_xl : 4; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fifo_ctrl3_t; + +#define ASM330LHBG1_FIFO_CTRL4 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_mode : 3; + uint8_t not_used_01 : 1; + uint8_t odr_t_batch : 2; + uint8_t dec_ts_batch : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dec_ts_batch : 2; + uint8_t odr_t_batch : 2; + uint8_t not_used_01 : 1; + uint8_t fifo_mode : 3; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fifo_ctrl4_t; + +#define ASM330LHBG1_COUNTER_BDR_REG1 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t cnt_bdr_th : 3; + uint8_t not_used_01 : 2; + uint8_t trig_counter_bdr : 1; + uint8_t rst_counter_bdr : 1; + uint8_t dataready_pulsed : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dataready_pulsed : 1; + uint8_t rst_counter_bdr : 1; + uint8_t trig_counter_bdr : 1; + uint8_t not_used_01 : 2; + uint8_t cnt_bdr_th : 3; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_counter_bdr_reg1_t; + +#define ASM330LHBG1_COUNTER_BDR_REG2 0x0CU +typedef struct +{ + uint8_t cnt_bdr_th : 8; +} asm330lhbg1_counter_bdr_reg2_t; + +#define ASM330LHBG1_INT1_CTRL 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_drdy_xl : 1; + uint8_t int1_drdy_g : 1; + uint8_t int1_boot : 1; + uint8_t int1_fifo_th : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_fifo_full : 1; + uint8_t int1_cnt_bdr : 1; + uint8_t den_drdy_flag : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t den_drdy_flag : 1; + uint8_t int1_cnt_bdr : 1; + uint8_t int1_fifo_full : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_fifo_th : 1; + uint8_t int1_boot : 1; + uint8_t int1_drdy_g : 1; + uint8_t int1_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_int1_ctrl_t; + +#define ASM330LHBG1_INT2_CTRL 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_drdy_xl : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_temp : 1; + uint8_t int2_fifo_th : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_fifo_full : 1; + uint8_t int2_cnt_bdr : 1; + uint8_t not_used_01 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 1; + uint8_t int2_cnt_bdr : 1; + uint8_t int2_fifo_full : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_fifo_th : 1; + uint8_t int2_drdy_temp : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_int2_ctrl_t; + +#define ASM330LHBG1_WHO_AM_I 0x0FU + +#define ASM330LHBG1_CTRL1_XL 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 1; + uint8_t lpf2_xl_en : 1; + uint8_t fs_xl : 2; + uint8_t odr_xl : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t odr_xl : 4; + uint8_t fs_xl : 2; + uint8_t lpf2_xl_en : 1; + uint8_t not_used_01 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_ctrl1_xl_t; + +#define ASM330LHBG1_CTRL2_G 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */ + uint8_t odr_g : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t odr_g : 4; + uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */ +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_ctrl2_g_t; + +#define ASM330LHBG1_CTRL3_C 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sw_reset : 1; + uint8_t not_used_01 : 1; + uint8_t if_inc : 1; + uint8_t sim : 1; + uint8_t pp_od : 1; + uint8_t h_lactive : 1; + uint8_t bdu : 1; + uint8_t boot : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t boot : 1; + uint8_t bdu : 1; + uint8_t h_lactive : 1; + uint8_t pp_od : 1; + uint8_t sim : 1; + uint8_t if_inc : 1; + uint8_t not_used_01 : 1; + uint8_t sw_reset : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_ctrl3_c_t; + +#define ASM330LHBG1_CTRL4_C 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 1; + uint8_t lpf1_sel_g : 1; + uint8_t i2c_disable : 1; + uint8_t drdy_mask : 1; + uint8_t not_used_02 : 1; + uint8_t int2_on_int1 : 1; + uint8_t sleep_g : 1; + uint8_t not_used_03 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_03 : 1; + uint8_t sleep_g : 1; + uint8_t int2_on_int1 : 1; + uint8_t not_used_02 : 1; + uint8_t drdy_mask : 1; + uint8_t i2c_disable : 1; + uint8_t lpf1_sel_g : 1; + uint8_t not_used_01 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_ctrl4_c_t; + +#define ASM330LHBG1_CTRL5_C 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t st_xl : 2; + uint8_t st_g : 2; + uint8_t not_used_01 : 1; + uint8_t rounding : 2; + uint8_t not_used_02 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 1; + uint8_t rounding : 2; + uint8_t not_used_01 : 1; + uint8_t st_g : 2; + uint8_t st_xl : 2; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_ctrl5_c_t; + +#define ASM330LHBG1_CTRL6_C 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ftype : 3; + uint8_t usr_off_w : 1; + uint8_t xl_hm_mode : 1; + uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ + uint8_t xl_hm_mode : 1; + uint8_t usr_off_w : 1; + uint8_t ftype : 3; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_ctrl6_c_t; + +#define ASM330LHBG1_CTRL7_G 0x16U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_00 : 1; + uint8_t usr_off_on_out : 1; + uint8_t not_used_01 : 2; + uint8_t hpm_g : 2; + uint8_t hp_en_g : 1; + uint8_t g_hm_mode : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t g_hm_mode : 1; + uint8_t hp_en_g : 1; + uint8_t hpm_g : 2; + uint8_t not_used_01 : 2; + uint8_t usr_off_on_out : 1; + uint8_t not_used_00 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_ctrl7_g_t; + +#define ASM330LHBG1_CTRL8_XL 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t low_pass_on_6d : 1; + uint8_t not_used_01 : 1; + uint8_t hp_slope_xl_en : 1; + uint8_t fastsettl_mode_xl : 1; + uint8_t hp_ref_mode_xl : 1; + uint8_t hpcf_xl : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t hpcf_xl : 3; + uint8_t hp_ref_mode_xl : 1; + uint8_t fastsettl_mode_xl : 1; + uint8_t hp_slope_xl_en : 1; + uint8_t not_used_01 : 1; + uint8_t low_pass_on_6d : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_ctrl8_xl_t; + +#define ASM330LHBG1_CTRL9_XL 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 1; + uint8_t i3c_disable : 1; + uint8_t den_lh : 1; + uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ + uint8_t den_z : 1; + uint8_t den_y : 1; + uint8_t den_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t den_x : 1; + uint8_t den_y : 1; + uint8_t den_z : 1; + uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ + uint8_t den_lh : 1; + uint8_t i3c_disable : 1; + uint8_t not_used_01 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_ctrl9_xl_t; + +#define ASM330LHBG1_CTRL10_C 0x19U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 5; + uint8_t timestamp_en : 1; + uint8_t not_used_02 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 2; + uint8_t timestamp_en : 1; + uint8_t not_used_01 : 5; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_ctrl10_c_t; + +#define ASM330LHBG1_ALL_INT_SRC 0x1AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ia : 1; + uint8_t wu_ia : 1; + uint8_t not_used_00 : 2; + uint8_t d6d_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t not_used_01 : 1; + uint8_t timestamp_endcount : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp_endcount : 1; + uint8_t not_used_01 : 1; + uint8_t sleep_change_ia : 1; + uint8_t d6d_ia : 1; + uint8_t not_used_00 : 2; + uint8_t wu_ia : 1; + uint8_t ff_ia : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_all_int_src_t; + +#define ASM330LHBG1_WAKE_UP_SRC 0x1BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t z_wu : 1; + uint8_t y_wu : 1; + uint8_t x_wu : 1; + uint8_t wu_ia : 1; + uint8_t sleep_state : 1; + uint8_t ff_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t not_used_01 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 1; + uint8_t sleep_change_ia : 1; + uint8_t ff_ia : 1; + uint8_t sleep_state : 1; + uint8_t wu_ia : 1; + uint8_t x_wu : 1; + uint8_t y_wu : 1; + uint8_t z_wu : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_wake_up_src_t; + +#define ASM330LHBG1_D6D_SRC 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xl : 1; + uint8_t xh : 1; + uint8_t yl : 1; + uint8_t yh : 1; + uint8_t zl : 1; + uint8_t zh : 1; + uint8_t d6d_ia : 1; + uint8_t den_drdy : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t den_drdy : 1; + uint8_t d6d_ia : 1; + uint8_t zh : 1; + uint8_t zl : 1; + uint8_t yh : 1; + uint8_t yl : 1; + uint8_t xh : 1; + uint8_t xl : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_d6d_src_t; + +#define ASM330LHBG1_STATUS_REG 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xlda : 1; + uint8_t gda : 1; + uint8_t tda : 1; + uint8_t boot_check_fail : 1; + uint8_t not_used_01 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 4; + uint8_t boot_check_fail : 1; + uint8_t tda : 1; + uint8_t gda : 1; + uint8_t xlda : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_status_reg_t; + +#define ASM330LHBG1_OUT_TEMP_L 0x20U +#define ASM330LHBG1_OUT_TEMP_H 0x21U +#define ASM330LHBG1_OUTX_L_G 0x22U +#define ASM330LHBG1_OUTX_H_G 0x23U +#define ASM330LHBG1_OUTY_L_G 0x24U +#define ASM330LHBG1_OUTY_H_G 0x25U +#define ASM330LHBG1_OUTZ_L_G 0x26U +#define ASM330LHBG1_OUTZ_H_G 0x27U +#define ASM330LHBG1_OUTX_L_A 0x28U +#define ASM330LHBG1_OUTX_H_A 0x29U +#define ASM330LHBG1_OUTY_L_A 0x2AU +#define ASM330LHBG1_OUTY_H_A 0x2BU +#define ASM330LHBG1_OUTZ_L_A 0x2CU +#define ASM330LHBG1_OUTZ_H_A 0x2DU +#define ASM330LHBG1_EMB_FUNC_STATUS_MAINPAGE 0x35U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 7; + uint8_t is_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm_lc : 1; + uint8_t not_used_01 : 7; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_emb_func_status_mainpage_t; + +#define ASM330LHBG1_FSM_STATUS_A_MAINPAGE 0x36U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm8 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fsm_status_a_mainpage_t; + +#define ASM330LHBG1_FSM_STATUS_B_MAINPAGE 0x37U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm9 : 1; + uint8_t is_fsm10 : 1; + uint8_t is_fsm11 : 1; + uint8_t is_fsm12 : 1; + uint8_t is_fsm13 : 1; + uint8_t is_fsm14 : 1; + uint8_t is_fsm15 : 1; + uint8_t is_fsm16 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm16 : 1; + uint8_t is_fsm15 : 1; + uint8_t is_fsm14 : 1; + uint8_t is_fsm13 : 1; + uint8_t is_fsm12 : 1; + uint8_t is_fsm11 : 1; + uint8_t is_fsm10 : 1; + uint8_t is_fsm9 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fsm_status_b_mainpage_t; + +#define ASM330LHBG1_MLC_STATUS_MAINPAGE 0x38U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_mlc1 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc4 : 1; + uint8_t is_mlc5 : 1; + uint8_t is_mlc6 : 1; + uint8_t is_mlc7 : 1; + uint8_t is_mlc8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_mlc8 : 1; + uint8_t is_mlc7 : 1; + uint8_t is_mlc6 : 1; + uint8_t is_mlc5 : 1; + uint8_t is_mlc4 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_mlc_status_mainpage_t; + +#define ASM330LHBG1_FIFO_STATUS1 0x3AU +typedef struct +{ + uint8_t diff_fifo : 8; +} asm330lhbg1_fifo_status1_t; + +#define ASM330LHBG1_FIFO_STATUS2 0x3BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t diff_fifo : 2; + uint8_t not_used_01 : 1; + uint8_t over_run_latched : 1; + uint8_t counter_bdr_ia : 1; + uint8_t fifo_full_ia : 1; + uint8_t fifo_ovr_ia : 1; + uint8_t fifo_wtm_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_wtm_ia : 1; + uint8_t fifo_ovr_ia : 1; + uint8_t fifo_full_ia : 1; + uint8_t counter_bdr_ia : 1; + uint8_t over_run_latched : 1; + uint8_t not_used_01 : 1; + uint8_t diff_fifo : 2; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fifo_status2_t; + +#define ASM330LHBG1_TIMESTAMP0 0x40U +#define ASM330LHBG1_TIMESTAMP1 0x41U +#define ASM330LHBG1_TIMESTAMP2 0x42U +#define ASM330LHBG1_TIMESTAMP3 0x43U +#define ASM330LHBG1_INT_CFG0 0x56U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t lir : 1; + uint8_t not_used_01 : 3; + uint8_t slope_fds : 1; + uint8_t sleep_status_on_int : 1; + uint8_t int_clr_on_read : 1; + uint8_t not_used_02 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 1; + uint8_t int_clr_on_read : 1; + uint8_t sleep_status_on_int : 1; + uint8_t slope_fds : 1; + uint8_t not_used_01 : 3; + uint8_t lir : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_int_cfg0_t; + +#define ASM330LHBG1_INT_CFG1 0x58U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 5; + uint8_t inact_en : 2; + uint8_t interrupts_enable : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t interrupts_enable : 1; + uint8_t inact_en : 2; + uint8_t not_used_01 : 5; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_int_cfg1_t; + +#define ASM330LHBG1_THS_6D 0x59U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 5; + uint8_t sixd_ths : 2; + uint8_t d4d_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t d4d_en : 1; + uint8_t sixd_ths : 2; + uint8_t not_used_01 : 5; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_ths_6d_t; + +#define ASM330LHBG1_WAKE_UP_THS 0x5BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wk_ths : 6; + uint8_t usr_off_on_wu : 1; + uint8_t not_used_01 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 1; + uint8_t usr_off_on_wu : 1; + uint8_t wk_ths : 6; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_wake_up_ths_t; + +#define ASM330LHBG1_WAKE_UP_DUR 0x5CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sleep_dur : 4; + uint8_t wake_ths_w : 1; + uint8_t wake_dur : 2; + uint8_t ff_dur : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 1; + uint8_t wake_dur : 2; + uint8_t wake_ths_w : 1; + uint8_t sleep_dur : 4; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_wake_up_dur_t; + +#define ASM330LHBG1_FREE_FALL 0x5DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ths : 3; + uint8_t ff_dur : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 5; + uint8_t ff_ths : 3; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_free_fall_t; + +#define ASM330LHBG1_MD1_CFG 0x5EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_00 : 1; + uint8_t int1_emb_func : 1; + uint8_t int1_6d : 1; + uint8_t not_used_01 : 1; + uint8_t int1_ff : 1; + uint8_t int1_wu : 1; + uint8_t not_used_02 : 1; + uint8_t int1_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_sleep_change : 1; + uint8_t not_used_02 : 1; + uint8_t int1_wu : 1; + uint8_t int1_ff : 1; + uint8_t not_used_01 : 1; + uint8_t int1_6d : 1; + uint8_t int1_emb_func : 1; + uint8_t not_used_00 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_md1_cfg_t; + +#define ASM330LHBG1_MD2_CFG 0x5FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_timestamp : 1; + uint8_t int2_emb_func : 1; + uint8_t int2_6d : 1; + uint8_t not_used_01 : 1; + uint8_t int2_ff : 1; + uint8_t int2_wu : 1; + uint8_t not_used_02 : 1; + uint8_t int2_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_sleep_change : 1; + uint8_t not_used_02 : 1; + uint8_t int2_wu : 1; + uint8_t int2_ff : 1; + uint8_t not_used_01 : 1; + uint8_t int2_6d : 1; + uint8_t int2_emb_func : 1; + uint8_t int2_timestamp : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_md2_cfg_t; + +#define ASM330LHBG1_I3C_BUS_AVB 0x62U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t pd_dis_int1 : 1; + uint8_t not_used_01 : 2; + uint8_t i3c_bus_avb_sel : 2; + uint8_t not_used_02 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 3; + uint8_t i3c_bus_avb_sel : 2; + uint8_t not_used_01 : 2; + uint8_t pd_dis_int1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_i3c_bus_avb_t; + +#define ASM330LHBG1_INTERNAL_FREQ_FINE 0x63U +typedef struct +{ + uint8_t freq_fine : 8; +} asm330lhbg1_internal_freq_fine_t; + +#define ASM330LHBG1_X_OFS_USR 0x73U +#define ASM330LHBG1_Y_OFS_USR 0x74U +#define ASM330LHBG1_Z_OFS_USR 0x75U +#define ASM330LHBG1_FIFO_DATA_OUT_TAG 0x78U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tag_parity : 1; + uint8_t tag_cnt : 2; + uint8_t tag_sensor : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tag_sensor : 5; + uint8_t tag_cnt : 2; + uint8_t tag_parity : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fifo_data_out_tag_t; + +#define ASM330LHBG1_FIFO_DATA_OUT_X_L 0x79U +#define ASM330LHBG1_FIFO_DATA_OUT_X_H 0x7AU +#define ASM330LHBG1_FIFO_DATA_OUT_Y_L 0x7BU +#define ASM330LHBG1_FIFO_DATA_OUT_Y_H 0x7CU +#define ASM330LHBG1_FIFO_DATA_OUT_Z_L 0x7DU +#define ASM330LHBG1_FIFO_DATA_OUT_Z_H 0x7EU + +#define ASM330LHBG1_PAGE_SEL 0x02U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 1; + uint8_t emb_func_clk_dis : 1; + uint8_t not_used_02 : 2; + uint8_t page_sel : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_sel : 4; + uint8_t not_used_02 : 2; + uint8_t emb_func_clk_dis : 1; + uint8_t not_used_01 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_page_sel_t; + +#define ASM330LHBG1_EMB_FUNC_EN_B 0x05U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_en : 1; + uint8_t not_used_01 : 3; + uint8_t mlc_en : 1; + uint8_t not_used_02 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 3; + uint8_t mlc_en : 1; + uint8_t not_used_01 : 3; + uint8_t fsm_en : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_emb_func_en_b_t; + +#define ASM330LHBG1_PAGE_ADDRESS 0x08U +typedef struct +{ + uint8_t page_addr : 8; +} asm330lhbg1_page_address_t; + +#define ASM330LHBG1_PAGE_VALUE 0x09U +typedef struct +{ + uint8_t page_value : 8; +} asm330lhbg1_page_value_t; + +#define ASM330LHBG1_EMB_FUNC_INT1 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 7; + uint8_t int1_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm_lc : 1; + uint8_t not_used_01 : 7; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_emb_func_int1_t; + +#define ASM330LHBG1_FSM_INT1_A 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_fsm1 : 1; + uint8_t int1_fsm2 : 1; + uint8_t int1_fsm3 : 1; + uint8_t int1_fsm4 : 1; + uint8_t int1_fsm5 : 1; + uint8_t int1_fsm6 : 1; + uint8_t int1_fsm7 : 1; + uint8_t int1_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm8 : 1; + uint8_t int1_fsm7 : 1; + uint8_t int1_fsm6 : 1; + uint8_t int1_fsm5 : 1; + uint8_t int1_fsm4 : 1; + uint8_t int1_fsm3 : 1; + uint8_t int1_fsm2 : 1; + uint8_t int1_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fsm_int1_a_t; + +#define ASM330LHBG1_FSM_INT1_B 0x0CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_fsm9 : 1; + uint8_t int1_fsm10 : 1; + uint8_t int1_fsm11 : 1; + uint8_t int1_fsm12 : 1; + uint8_t int1_fsm13 : 1; + uint8_t int1_fsm14 : 1; + uint8_t int1_fsm15 : 1; + uint8_t int1_fsm16 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm16 : 1; + uint8_t int1_fsm15 : 1; + uint8_t int1_fsm14 : 1; + uint8_t int1_fsm13 : 1; + uint8_t int1_fsm12 : 1; + uint8_t int1_fsm11 : 1; + uint8_t int1_fsm10 : 1; + uint8_t int1_fsm9 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fsm_int1_b_t; + +#define ASM330LHBG1_MLC_INT1 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_mlc1 : 1; + uint8_t int1_mlc2 : 1; + uint8_t int1_mlc3 : 1; + uint8_t int1_mlc4 : 1; + uint8_t int1_mlc5 : 1; + uint8_t int1_mlc6 : 1; + uint8_t int1_mlc7 : 1; + uint8_t int1_mlc8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_mlc8 : 1; + uint8_t int1_mlc7 : 1; + uint8_t int1_mlc6 : 1; + uint8_t int1_mlc5 : 1; + uint8_t int1_mlc4 : 1; + uint8_t int1_mlc3 : 1; + uint8_t int1_mlc2 : 1; + uint8_t int1_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_mlc_int1_t; + +#define ASM330LHBG1_EMB_FUNC_INT2 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 7; + uint8_t int2_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm_lc : 1; + uint8_t not_used_01 : 7; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_emb_func_int2_t; + +#define ASM330LHBG1_FSM_INT2_A 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_fsm1 : 1; + uint8_t int2_fsm2 : 1; + uint8_t int2_fsm3 : 1; + uint8_t int2_fsm4 : 1; + uint8_t int2_fsm5 : 1; + uint8_t int2_fsm6 : 1; + uint8_t int2_fsm7 : 1; + uint8_t int2_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm8 : 1; + uint8_t int2_fsm7 : 1; + uint8_t int2_fsm6 : 1; + uint8_t int2_fsm5 : 1; + uint8_t int2_fsm4 : 1; + uint8_t int2_fsm3 : 1; + uint8_t int2_fsm2 : 1; + uint8_t int2_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fsm_int2_a_t; + +#define ASM330LHBG1_FSM_INT2_B 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_fsm9 : 1; + uint8_t int2_fsm10 : 1; + uint8_t int2_fsm11 : 1; + uint8_t int2_fsm12 : 1; + uint8_t int2_fsm13 : 1; + uint8_t int2_fsm14 : 1; + uint8_t int2_fsm15 : 1; + uint8_t int2_fsm16 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm16 : 1; + uint8_t int2_fsm15 : 1; + uint8_t int2_fsm14 : 1; + uint8_t int2_fsm13 : 1; + uint8_t int2_fsm12 : 1; + uint8_t int2_fsm11 : 1; + uint8_t int2_fsm10 : 1; + uint8_t int2_fsm9 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fsm_int2_b_t; + +#define ASM330LHBG1_MLC_INT2 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_mlc1 : 1; + uint8_t int2_mlc2 : 1; + uint8_t int2_mlc3 : 1; + uint8_t int2_mlc4 : 1; + uint8_t int2_mlc5 : 1; + uint8_t int2_mlc6 : 1; + uint8_t int2_mlc7 : 1; + uint8_t int2_mlc8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_mlc8 : 1; + uint8_t int2_mlc7 : 1; + uint8_t int2_mlc6 : 1; + uint8_t int2_mlc5 : 1; + uint8_t int2_mlc4 : 1; + uint8_t int2_mlc3 : 1; + uint8_t int2_mlc2 : 1; + uint8_t int2_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_mlc_int2_t; + +#define ASM330LHBG1_EMB_FUNC_STATUS 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 7; + uint8_t is_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm_lc : 1; + uint8_t not_used_01 : 7; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_emb_func_status_t; + +#define ASM330LHBG1_FSM_STATUS_A 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm8 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fsm_status_a_t; + +#define ASM330LHBG1_FSM_STATUS_B 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm9 : 1; + uint8_t is_fsm10 : 1; + uint8_t is_fsm11 : 1; + uint8_t is_fsm12 : 1; + uint8_t is_fsm13 : 1; + uint8_t is_fsm14 : 1; + uint8_t is_fsm15 : 1; + uint8_t is_fsm16 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm16 : 1; + uint8_t is_fsm15 : 1; + uint8_t is_fsm14 : 1; + uint8_t is_fsm13 : 1; + uint8_t is_fsm12 : 1; + uint8_t is_fsm11 : 1; + uint8_t is_fsm10 : 1; + uint8_t is_fsm9 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fsm_status_b_t; + +#define ASM330LHBG1_MLC_STATUS 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_mlc1 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc4 : 1; + uint8_t is_mlc5 : 1; + uint8_t is_mlc6 : 1; + uint8_t is_mlc7 : 1; + uint8_t is_mlc8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_mlc8 : 1; + uint8_t is_mlc7 : 1; + uint8_t is_mlc6 : 1; + uint8_t is_mlc5 : 1; + uint8_t is_mlc4 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_mlc_status_t; + +#define ASM330LHBG1_PAGE_RW 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 5; + uint8_t page_rw : 2; /* page_write + page_read */ + uint8_t emb_func_lir : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_lir : 1; + uint8_t page_rw : 2; /* page_write + page_read */ + uint8_t not_used_01 : 5; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_page_rw_t; + +#define ASM330LHBG1_FSM_ENABLE_A 0x46U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm1_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm8_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm8_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm1_en : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fsm_enable_a_t; + +#define ASM330LHBG1_FSM_ENABLE_B 0x47U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm9_en : 1; + uint8_t fsm10_en : 1; + uint8_t fsm11_en : 1; + uint8_t fsm12_en : 1; + uint8_t fsm13_en : 1; + uint8_t fsm14_en : 1; + uint8_t fsm15_en : 1; + uint8_t fsm16_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm16_en : 1; + uint8_t fsm15_en : 1; + uint8_t fsm14_en : 1; + uint8_t fsm13_en : 1; + uint8_t fsm12_en : 1; + uint8_t fsm11_en : 1; + uint8_t fsm10_en : 1; + uint8_t fsm9_en : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fsm_enable_b_t; + +#define ASM330LHBG1_FSM_LONG_COUNTER_L 0x48U +#define ASM330LHBG1_FSM_LONG_COUNTER_H 0x49U +#define ASM330LHBG1_FSM_LONG_COUNTER_CLEAR 0x4AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ + uint8_t not_used_01 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 6; + uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fsm_long_counter_clear_t; + +#define ASM330LHBG1_FSM_OUTS1 0x4CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fsm_outs1_t; + +#define ASM330LHBG1_FSM_OUTS2 0x4DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fsm_outs2_t; + +#define ASM330LHBG1_FSM_OUTS3 0x4EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fsm_outs3_t; + +#define ASM330LHBG1_FSM_OUTS4 0x4FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fsm_outs4_t; + +#define ASM330LHBG1_FSM_OUTS5 0x50U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fsm_outs5_t; + +#define ASM330LHBG1_FSM_OUTS6 0x51U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fsm_outs6_t; + +#define ASM330LHBG1_FSM_OUTS7 0x52U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fsm_outs7_t; + +#define ASM330LHBG1_FSM_OUTS8 0x53U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fsm_outs8_t; + +#define ASM330LHBG1_FSM_OUTS9 0x54U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fsm_outs9_t; + +#define ASM330LHBG1_FSM_OUTS10 0x55U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fsm_outs10_t; + +#define ASM330LHBG1_FSM_OUTS11 0x56U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fsm_outs11_t; + +#define ASM330LHBG1_FSM_OUTS12 0x57U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fsm_outs12_t; + +#define ASM330LHBG1_FSM_OUTS13 0x58U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fsm_outs13_t; + +#define ASM330LHBG1_FSM_OUTS14 0x59U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fsm_outs14_t; + +#define ASM330LHBG1_FSM_OUTS15 0x5AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fsm_outs15_t; + +#define ASM330LHBG1_FSM_OUTS16 0x5BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_fsm_outs16_t; + +#define ASM330LHBG1_EMB_FUNC_ODR_CFG_B 0x5FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 3; + uint8_t fsm_odr : 2; + uint8_t not_used_02 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 3; + uint8_t fsm_odr : 2; + uint8_t not_used_01 : 3; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_emb_func_odr_cfg_b_t; + +#define ASM330LHBG1_EMB_FUNC_ODR_CFG_C 0x60U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 4; + uint8_t mlc_odr : 2; + uint8_t not_used_02 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 2; + uint8_t mlc_odr : 2; + uint8_t not_used_01 : 4; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_emb_func_odr_cfg_c_t; + +#define ASM330LHBG1_EMB_FUNC_INIT_B 0x67U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_init : 1; + uint8_t not_used_01 : 3; + uint8_t mlc_init : 1; + uint8_t not_used_02 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 3; + uint8_t mlc_init : 1; + uint8_t not_used_01 : 3; + uint8_t fsm_init : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhbg1_emb_func_init_b_t; + +#define ASM330LHBG1_MLC0_SRC 0x70U +#define ASM330LHBG1_MLC1_SRC 0x71U +#define ASM330LHBG1_MLC2_SRC 0x72U +#define ASM330LHBG1_MLC3_SRC 0x73U +#define ASM330LHBG1_MLC4_SRC 0x74U +#define ASM330LHBG1_MLC5_SRC 0x75U +#define ASM330LHBG1_MLC6_SRC 0x76U +#define ASM330LHBG1_MLC7_SRC 0x77U + +#define ASM330LHBG1_FSM_LC_TIMEOUT_L 0x17AU +#define ASM330LHBG1_FSM_LC_TIMEOUT_H 0x17BU +#define ASM330LHBG1_FSM_PROGRAMS 0x17CU +#define ASM330LHBG1_FSM_START_ADD_L 0x17EU +#define ASM330LHBG1_FSM_START_ADD_H 0x17FU + +/** + * @defgroup ASM330LHBG1_Register_Union + * @brief This union group all the registers that has a bit-field + * description. + * This union is useful but not need by the driver. + * + * REMOVING this union you are compliant with: + * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " + * + * @{ + * + */ +typedef union +{ + asm330lhbg1_func_cfg_access_t func_cfg_access; + asm330lhbg1_pin_ctrl_t pin_ctrl; + asm330lhbg1_fifo_ctrl1_t fifo_ctrl1; + asm330lhbg1_fifo_ctrl2_t fifo_ctrl2; + asm330lhbg1_fifo_ctrl3_t fifo_ctrl3; + asm330lhbg1_fifo_ctrl4_t fifo_ctrl4; + asm330lhbg1_counter_bdr_reg1_t counter_bdr_reg1; + asm330lhbg1_counter_bdr_reg2_t counter_bdr_reg2; + asm330lhbg1_int1_ctrl_t int1_ctrl; + asm330lhbg1_int2_ctrl_t int2_ctrl; + asm330lhbg1_ctrl1_xl_t ctrl1_xl; + asm330lhbg1_ctrl2_g_t ctrl2_g; + asm330lhbg1_ctrl3_c_t ctrl3_c; + asm330lhbg1_ctrl4_c_t ctrl4_c; + asm330lhbg1_ctrl5_c_t ctrl5_c; + asm330lhbg1_ctrl6_c_t ctrl6_c; + asm330lhbg1_ctrl7_g_t ctrl7_g; + asm330lhbg1_ctrl8_xl_t ctrl8_xl; + asm330lhbg1_ctrl9_xl_t ctrl9_xl; + asm330lhbg1_ctrl10_c_t ctrl10_c; + asm330lhbg1_all_int_src_t all_int_src; + asm330lhbg1_wake_up_src_t wake_up_src; + asm330lhbg1_d6d_src_t d6d_src; + asm330lhbg1_status_reg_t status_reg; + asm330lhbg1_fifo_status1_t fifo_status1; + asm330lhbg1_fifo_status2_t fifo_status2; + asm330lhbg1_int_cfg0_t int_cfg0; + asm330lhbg1_int_cfg1_t int_cfg1; + asm330lhbg1_ths_6d_t ths_6d; + asm330lhbg1_wake_up_ths_t wake_up_ths; + asm330lhbg1_wake_up_dur_t wake_up_dur; + asm330lhbg1_free_fall_t free_fall; + asm330lhbg1_md1_cfg_t md1_cfg; + asm330lhbg1_md2_cfg_t md2_cfg; + asm330lhbg1_i3c_bus_avb_t i3c_bus_avb; + asm330lhbg1_internal_freq_fine_t internal_freq_fine; + asm330lhbg1_fifo_data_out_tag_t fifo_data_out_tag; + asm330lhbg1_page_sel_t page_sel; + asm330lhbg1_emb_func_en_b_t emb_func_en_b; + asm330lhbg1_page_address_t page_address; + asm330lhbg1_page_value_t page_value; + asm330lhbg1_emb_func_int1_t emb_func_int1; + asm330lhbg1_fsm_int1_a_t fsm_int1_a; + asm330lhbg1_fsm_int1_b_t fsm_int1_b; + asm330lhbg1_mlc_int1_t mlc_int1; + asm330lhbg1_emb_func_int2_t emb_func_int2; + asm330lhbg1_fsm_int2_a_t fsm_int2_a; + asm330lhbg1_fsm_int2_b_t fsm_int2_b; + asm330lhbg1_mlc_int2_t mlc_int2; + asm330lhbg1_emb_func_status_t emb_func_status; + asm330lhbg1_fsm_status_a_t fsm_status_a; + asm330lhbg1_fsm_status_b_t fsm_status_b; + asm330lhbg1_mlc_status_mainpage_t mlc_status_mainpage; + asm330lhbg1_emb_func_odr_cfg_c_t emb_func_odr_cfg_c; + asm330lhbg1_page_rw_t page_rw; + asm330lhbg1_fsm_enable_a_t fsm_enable_a; + asm330lhbg1_fsm_enable_b_t fsm_enable_b; + asm330lhbg1_fsm_long_counter_clear_t fsm_long_counter_clear; + asm330lhbg1_fsm_outs1_t fsm_outs1; + asm330lhbg1_fsm_outs2_t fsm_outs2; + asm330lhbg1_fsm_outs3_t fsm_outs3; + asm330lhbg1_fsm_outs4_t fsm_outs4; + asm330lhbg1_fsm_outs5_t fsm_outs5; + asm330lhbg1_fsm_outs6_t fsm_outs6; + asm330lhbg1_fsm_outs7_t fsm_outs7; + asm330lhbg1_fsm_outs8_t fsm_outs8; + asm330lhbg1_fsm_outs9_t fsm_outs9; + asm330lhbg1_fsm_outs10_t fsm_outs10; + asm330lhbg1_fsm_outs11_t fsm_outs11; + asm330lhbg1_fsm_outs12_t fsm_outs12; + asm330lhbg1_fsm_outs13_t fsm_outs13; + asm330lhbg1_fsm_outs14_t fsm_outs14; + asm330lhbg1_fsm_outs15_t fsm_outs15; + asm330lhbg1_fsm_outs16_t fsm_outs16; + asm330lhbg1_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; + asm330lhbg1_emb_func_init_b_t emb_func_init_b; + bitwise_t bitwise; + uint8_t byte; +} asm330lhbg1_reg_t; + +/** + * @} + * + */ + +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + +int32_t asm330lhbg1_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len); +int32_t asm330lhbg1_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len); + +float_t asm330lhbg1_from_fs2g_to_mg(int16_t lsb); +float_t asm330lhbg1_from_fs4g_to_mg(int16_t lsb); +float_t asm330lhbg1_from_fs8g_to_mg(int16_t lsb); +float_t asm330lhbg1_from_fs16g_to_mg(int16_t lsb); +float_t asm330lhbg1_from_fs125dps_to_mdps(int16_t lsb); +float_t asm330lhbg1_from_fs250dps_to_mdps(int16_t lsb); +float_t asm330lhbg1_from_fs500dps_to_mdps(int16_t lsb); +float_t asm330lhbg1_from_fs1000dps_to_mdps(int16_t lsb); +float_t asm330lhbg1_from_fs2000dps_to_mdps(int16_t lsb); +float_t asm330lhbg1_from_fs4000dps_to_mdps(int16_t lsb); +float_t asm330lhbg1_from_lsb_to_celsius(int16_t lsb); +float_t asm330lhbg1_from_lsb_to_nsec(int32_t lsb); + +typedef enum +{ + ASM330LHBG1_2g = 0, + ASM330LHBG1_16g = 1, /* if XL_FS_MODE = '1' -> ASM330LHBG1_2g */ + ASM330LHBG1_4g = 2, + ASM330LHBG1_8g = 3, +} asm330lhbg1_fs_xl_t; +int32_t asm330lhbg1_xl_full_scale_set(const stmdev_ctx_t *ctx, asm330lhbg1_fs_xl_t val); +int32_t asm330lhbg1_xl_full_scale_get(const stmdev_ctx_t *ctx, + asm330lhbg1_fs_xl_t *val); + +typedef enum +{ + ASM330LHBG1_XL_ODR_OFF = 0, + ASM330LHBG1_XL_ODR_12Hz5 = 1, + ASM330LHBG1_XL_ODR_26Hz = 2, + ASM330LHBG1_XL_ODR_52Hz = 3, + ASM330LHBG1_XL_ODR_104Hz = 4, + ASM330LHBG1_XL_ODR_208Hz = 5, + ASM330LHBG1_XL_ODR_417Hz = 6, + ASM330LHBG1_XL_ODR_833Hz = 7, + ASM330LHBG1_XL_ODR_1667Hz = 8, + ASM330LHBG1_XL_ODR_1Hz6 = 11, /* (low power only) */ +} asm330lhbg1_odr_xl_t; +int32_t asm330lhbg1_xl_data_rate_set(const stmdev_ctx_t *ctx, asm330lhbg1_odr_xl_t val); +int32_t asm330lhbg1_xl_data_rate_get(const stmdev_ctx_t *ctx, + asm330lhbg1_odr_xl_t *val); + +typedef enum +{ + ASM330LHBG1_125dps = 2, + ASM330LHBG1_250dps = 0, + ASM330LHBG1_500dps = 4, + ASM330LHBG1_1000dps = 8, + ASM330LHBG1_2000dps = 12, + ASM330LHBG1_4000dps = 1, +} asm330lhbg1_fs_g_t; +int32_t asm330lhbg1_gy_full_scale_set(const stmdev_ctx_t *ctx, asm330lhbg1_fs_g_t val); +int32_t asm330lhbg1_gy_full_scale_get(const stmdev_ctx_t *ctx, asm330lhbg1_fs_g_t *val); + +typedef enum +{ + ASM330LHBG1_GY_ODR_OFF = 0, + ASM330LHBG1_GY_ODR_12Hz5 = 1, + ASM330LHBG1_GY_ODR_26Hz = 2, + ASM330LHBG1_GY_ODR_52Hz = 3, + ASM330LHBG1_GY_ODR_104Hz = 4, + ASM330LHBG1_GY_ODR_208Hz = 5, + ASM330LHBG1_GY_ODR_417Hz = 6, + ASM330LHBG1_GY_ODR_833Hz = 7, + ASM330LHBG1_GY_ODR_1667Hz = 8, +} asm330lhbg1_odr_g_t; +int32_t asm330lhbg1_gy_data_rate_set(const stmdev_ctx_t *ctx, + asm330lhbg1_odr_g_t val); +int32_t asm330lhbg1_gy_data_rate_get(const stmdev_ctx_t *ctx, + asm330lhbg1_odr_g_t *val); + +int32_t asm330lhbg1_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHBG1_LSb_1mg = 0, + ASM330LHBG1_LSb_16mg = 1, +} asm330lhbg1_usr_off_w_t; +int32_t asm330lhbg1_xl_offset_weight_set(const stmdev_ctx_t *ctx, + asm330lhbg1_usr_off_w_t val); +int32_t asm330lhbg1_xl_offset_weight_get(const stmdev_ctx_t *ctx, + asm330lhbg1_usr_off_w_t *val); + +typedef enum +{ + ASM330LHBG1_HIGH_PERFORMANCE_MD = 0, + ASM330LHBG1_LOW_NORMAL_POWER_MD = 1, +} asm330lhbg1_xl_hm_mode_t; +int32_t asm330lhbg1_xl_power_mode_set(const stmdev_ctx_t *ctx, + asm330lhbg1_xl_hm_mode_t val); +int32_t asm330lhbg1_xl_power_mode_get(const stmdev_ctx_t *ctx, + asm330lhbg1_xl_hm_mode_t *val); + +typedef enum +{ + ASM330LHBG1_GY_HIGH_PERFORMANCE = 0, + ASM330LHBG1_GY_NORMAL = 1, +} asm330lhbg1_g_hm_mode_t; +int32_t asm330lhbg1_gy_power_mode_set(const stmdev_ctx_t *ctx, + asm330lhbg1_g_hm_mode_t val); +int32_t asm330lhbg1_gy_power_mode_get(const stmdev_ctx_t *ctx, + asm330lhbg1_g_hm_mode_t *val); + +typedef struct +{ + asm330lhbg1_all_int_src_t all_int_src; + asm330lhbg1_wake_up_src_t wake_up_src; + asm330lhbg1_d6d_src_t d6d_src; + asm330lhbg1_status_reg_t status_reg; + asm330lhbg1_emb_func_status_t emb_func_status; + asm330lhbg1_fsm_status_a_t fsm_status_a; + asm330lhbg1_fsm_status_b_t fsm_status_b; + asm330lhbg1_mlc_status_mainpage_t mlc_status; +} asm330lhbg1_all_sources_t; +int32_t asm330lhbg1_all_sources_get(const stmdev_ctx_t *ctx, + asm330lhbg1_all_sources_t *val); + +int32_t asm330lhbg1_status_reg_get(const stmdev_ctx_t *ctx, + asm330lhbg1_status_reg_t *val); + +int32_t asm330lhbg1_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhbg1_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhbg1_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhbg1_boot_device_status_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhbg1_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhbg1_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t asm330lhbg1_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhbg1_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t asm330lhbg1_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhbg1_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t asm330lhbg1_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhbg1_timestamp_rst(const stmdev_ctx_t *ctx); + +int32_t asm330lhbg1_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhbg1_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); + +typedef enum +{ + ASM330LHBG1_NO_ROUND = 0, + ASM330LHBG1_ROUND_XL = 1, + ASM330LHBG1_ROUND_GY = 2, + ASM330LHBG1_ROUND_GY_XL = 3, +} asm330lhbg1_rounding_t; +int32_t asm330lhbg1_rounding_mode_set(const stmdev_ctx_t *ctx, + asm330lhbg1_rounding_t val); +int32_t asm330lhbg1_rounding_mode_get(const stmdev_ctx_t *ctx, + asm330lhbg1_rounding_t *val); + +int32_t asm330lhbg1_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t asm330lhbg1_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t asm330lhbg1_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t asm330lhbg1_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhbg1_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHBG1_USER_BANK = 0, + ASM330LHBG1_EMBEDDED_FUNC_BANK = 1, +} asm330lhbg1_reg_access_t; +int32_t asm330lhbg1_mem_bank_set(const stmdev_ctx_t *ctx, asm330lhbg1_reg_access_t val); +int32_t asm330lhbg1_mem_bank_get(const stmdev_ctx_t *ctx, + asm330lhbg1_reg_access_t *val); + +int32_t asm330lhbg1_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t address, + uint8_t *val); +int32_t asm330lhbg1_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len); +int32_t asm330lhbg1_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, + uint8_t *val); +int32_t asm330lhbg1_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, + uint8_t *val); + +typedef enum +{ + ASM330LHBG1_DRDY_LATCHED = 0, + ASM330LHBG1_DRDY_PULSED = 1, +} asm330lhbg1_dataready_pulsed_t; +int32_t asm330lhbg1_data_ready_mode_set(const stmdev_ctx_t *ctx, + asm330lhbg1_dataready_pulsed_t val); +int32_t asm330lhbg1_data_ready_mode_get(const stmdev_ctx_t *ctx, + asm330lhbg1_dataready_pulsed_t *val); + +int32_t asm330lhbg1_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t asm330lhbg1_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhbg1_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhbg1_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHBG1_XL_ST_DISABLE = 0, + ASM330LHBG1_XL_ST_POSITIVE = 1, + ASM330LHBG1_XL_ST_NEGATIVE = 2, +} asm330lhbg1_st_xl_t; +int32_t asm330lhbg1_xl_self_test_set(const stmdev_ctx_t *ctx, asm330lhbg1_st_xl_t val); +int32_t asm330lhbg1_xl_self_test_get(const stmdev_ctx_t *ctx, asm330lhbg1_st_xl_t *val); + +typedef enum +{ + ASM330LHBG1_GY_ST_DISABLE = 0, + ASM330LHBG1_GY_ST_POSITIVE = 1, + ASM330LHBG1_GY_ST_NEGATIVE = 3, +} asm330lhbg1_st_g_t; +int32_t asm330lhbg1_gy_self_test_set(const stmdev_ctx_t *ctx, asm330lhbg1_st_g_t val); +int32_t asm330lhbg1_gy_self_test_get(const stmdev_ctx_t *ctx, asm330lhbg1_st_g_t *val); + +int32_t asm330lhbg1_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhbg1_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhbg1_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHBG1_ULTRA_LIGHT = 0, + ASM330LHBG1_VERY_LIGHT = 1, + ASM330LHBG1_LIGHT = 2, + ASM330LHBG1_MEDIUM = 3, + ASM330LHBG1_STRONG = 4, + ASM330LHBG1_VERY_STRONG = 5, + ASM330LHBG1_AGGRESSIVE = 6, + ASM330LHBG1_XTREME = 7, +} asm330lhbg1_ftype_t; +int32_t asm330lhbg1_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, + asm330lhbg1_ftype_t val); +int32_t asm330lhbg1_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, + asm330lhbg1_ftype_t *val); + +int32_t asm330lhbg1_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHBG1_HP_PATH_DISABLE_ON_OUT = 0x00, + ASM330LHBG1_SLOPE_ODR_DIV_4 = 0x10, + ASM330LHBG1_HP_ODR_DIV_10 = 0x11, + ASM330LHBG1_HP_ODR_DIV_20 = 0x12, + ASM330LHBG1_HP_ODR_DIV_45 = 0x13, + ASM330LHBG1_HP_ODR_DIV_100 = 0x14, + ASM330LHBG1_HP_ODR_DIV_200 = 0x15, + ASM330LHBG1_HP_ODR_DIV_400 = 0x16, + ASM330LHBG1_HP_ODR_DIV_800 = 0x17, + ASM330LHBG1_HP_REF_MD_ODR_DIV_10 = 0x31, + ASM330LHBG1_HP_REF_MD_ODR_DIV_20 = 0x32, + ASM330LHBG1_HP_REF_MD_ODR_DIV_45 = 0x33, + ASM330LHBG1_HP_REF_MD_ODR_DIV_100 = 0x34, + ASM330LHBG1_HP_REF_MD_ODR_DIV_200 = 0x35, + ASM330LHBG1_HP_REF_MD_ODR_DIV_400 = 0x36, + ASM330LHBG1_HP_REF_MD_ODR_DIV_800 = 0x37, + ASM330LHBG1_LP_ODR_DIV_10 = 0x01, + ASM330LHBG1_LP_ODR_DIV_20 = 0x02, + ASM330LHBG1_LP_ODR_DIV_45 = 0x03, + ASM330LHBG1_LP_ODR_DIV_100 = 0x04, + ASM330LHBG1_LP_ODR_DIV_200 = 0x05, + ASM330LHBG1_LP_ODR_DIV_400 = 0x06, + ASM330LHBG1_LP_ODR_DIV_800 = 0x07, +} asm330lhbg1_hp_slope_xl_en_t; +int32_t asm330lhbg1_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, + asm330lhbg1_hp_slope_xl_en_t val); +int32_t asm330lhbg1_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, + asm330lhbg1_hp_slope_xl_en_t *val); + +int32_t asm330lhbg1_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHBG1_USE_SLOPE = 0, + ASM330LHBG1_USE_HPF = 1, +} asm330lhbg1_slope_fds_t; +int32_t asm330lhbg1_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, + asm330lhbg1_slope_fds_t val); +int32_t asm330lhbg1_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, + asm330lhbg1_slope_fds_t *val); + +typedef enum +{ + ASM330LHBG1_HP_FILTER_NONE = 0x00, + ASM330LHBG1_HP_FILTER_16mHz = 0x80, + ASM330LHBG1_HP_FILTER_65mHz = 0x81, + ASM330LHBG1_HP_FILTER_260mHz = 0x82, + ASM330LHBG1_HP_FILTER_1Hz04 = 0x83, +} asm330lhbg1_hpm_g_t; +int32_t asm330lhbg1_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, + asm330lhbg1_hpm_g_t val); +int32_t asm330lhbg1_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, + asm330lhbg1_hpm_g_t *val); + +typedef enum +{ + ASM330LHBG1_PULL_UP_DISC = 0, + ASM330LHBG1_PULL_UP_CONNECT = 1, +} asm330lhbg1_sdo_pu_en_t; +int32_t asm330lhbg1_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, + asm330lhbg1_sdo_pu_en_t val); +int32_t asm330lhbg1_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, + asm330lhbg1_sdo_pu_en_t *val); + +typedef enum +{ + ASM330LHBG1_PULL_DOWN_CONNECT = 0, + ASM330LHBG1_PULL_DOWN_DISC = 1, +} asm330lhbg1_pd_dis_int1_t; +int32_t asm330lhbg1_int1_mode_set(const stmdev_ctx_t *ctx, + asm330lhbg1_pd_dis_int1_t val); +int32_t asm330lhbg1_int1_mode_get(const stmdev_ctx_t *ctx, + asm330lhbg1_pd_dis_int1_t *val); + +typedef enum +{ + ASM330LHBG1_SPI_4_WIRE = 0, + ASM330LHBG1_SPI_3_WIRE = 1, +} asm330lhbg1_sim_t; +int32_t asm330lhbg1_spi_mode_set(const stmdev_ctx_t *ctx, asm330lhbg1_sim_t val); +int32_t asm330lhbg1_spi_mode_get(const stmdev_ctx_t *ctx, asm330lhbg1_sim_t *val); + +typedef enum +{ + ASM330LHBG1_I2C_ENABLE = 0, + ASM330LHBG1_I2C_DISABLE = 1, +} asm330lhbg1_i2c_disable_t; +int32_t asm330lhbg1_i2c_interface_set(const stmdev_ctx_t *ctx, + asm330lhbg1_i2c_disable_t val); +int32_t asm330lhbg1_i2c_interface_get(const stmdev_ctx_t *ctx, + asm330lhbg1_i2c_disable_t *val); + +typedef enum +{ + ASM330LHBG1_I3C_DISABLE = 0x80, + ASM330LHBG1_I3C_ENABLE_T_50us = 0x00, + ASM330LHBG1_I3C_ENABLE_T_2us = 0x01, + ASM330LHBG1_I3C_ENABLE_T_1ms = 0x02, + ASM330LHBG1_I3C_ENABLE_T_25ms = 0x03, +} asm330lhbg1_i3c_disable_t; +int32_t asm330lhbg1_i3c_disable_set(const stmdev_ctx_t *ctx, + asm330lhbg1_i3c_disable_t val); +int32_t asm330lhbg1_i3c_disable_get(const stmdev_ctx_t *ctx, + asm330lhbg1_i3c_disable_t *val); + +typedef struct +{ + asm330lhbg1_int1_ctrl_t int1_ctrl; + asm330lhbg1_md1_cfg_t md1_cfg; + asm330lhbg1_emb_func_int1_t emb_func_int1; + asm330lhbg1_fsm_int1_a_t fsm_int1_a; + asm330lhbg1_fsm_int1_b_t fsm_int1_b; + asm330lhbg1_mlc_int1_t mlc_int1; +} asm330lhbg1_pin_int1_route_t; +int32_t asm330lhbg1_pin_int1_route_set(const stmdev_ctx_t *ctx, + asm330lhbg1_pin_int1_route_t *val); +int32_t asm330lhbg1_pin_int1_route_get(const stmdev_ctx_t *ctx, + asm330lhbg1_pin_int1_route_t *val); + +typedef struct +{ + asm330lhbg1_int2_ctrl_t int2_ctrl; + asm330lhbg1_md2_cfg_t md2_cfg; + asm330lhbg1_emb_func_int2_t emb_func_int2; + asm330lhbg1_fsm_int2_a_t fsm_int2_a; + asm330lhbg1_fsm_int2_b_t fsm_int2_b; + asm330lhbg1_mlc_int2_t mlc_int2; +} asm330lhbg1_pin_int2_route_t; +int32_t asm330lhbg1_pin_int2_route_set(const stmdev_ctx_t *ctx, + asm330lhbg1_pin_int2_route_t *val); +int32_t asm330lhbg1_pin_int2_route_get(const stmdev_ctx_t *ctx, + asm330lhbg1_pin_int2_route_t *val); + +typedef enum +{ + ASM330LHBG1_PUSH_PULL = 0, + ASM330LHBG1_OPEN_DRAIN = 1, +} asm330lhbg1_pp_od_t; +int32_t asm330lhbg1_pin_mode_set(const stmdev_ctx_t *ctx, asm330lhbg1_pp_od_t val); +int32_t asm330lhbg1_pin_mode_get(const stmdev_ctx_t *ctx, asm330lhbg1_pp_od_t *val); + +typedef enum +{ + ASM330LHBG1_ACTIVE_HIGH = 0, + ASM330LHBG1_ACTIVE_LOW = 1, +} asm330lhbg1_h_lactive_t; +int32_t asm330lhbg1_pin_polarity_set(const stmdev_ctx_t *ctx, + asm330lhbg1_h_lactive_t val); +int32_t asm330lhbg1_pin_polarity_get(const stmdev_ctx_t *ctx, + asm330lhbg1_h_lactive_t *val); + +int32_t asm330lhbg1_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHBG1_ALL_INT_PULSED = 0, + ASM330LHBG1_BASE_LATCHED_EMB_PULSED = 1, + ASM330LHBG1_BASE_PULSED_EMB_LATCHED = 2, + ASM330LHBG1_ALL_INT_LATCHED = 3, +} asm330lhbg1_lir_t; +int32_t asm330lhbg1_int_notification_set(const stmdev_ctx_t *ctx, + asm330lhbg1_lir_t val); +int32_t asm330lhbg1_int_notification_get(const stmdev_ctx_t *ctx, + asm330lhbg1_lir_t *val); + +typedef enum +{ + ASM330LHBG1_LSb_FS_DIV_64 = 0, + ASM330LHBG1_LSb_FS_DIV_256 = 1, +} asm330lhbg1_wake_ths_w_t; +int32_t asm330lhbg1_wkup_ths_weight_set(const stmdev_ctx_t *ctx, + asm330lhbg1_wake_ths_w_t val); +int32_t asm330lhbg1_wkup_ths_weight_get(const stmdev_ctx_t *ctx, + asm330lhbg1_wake_ths_w_t *val); + +int32_t asm330lhbg1_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhbg1_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, + uint8_t val); +int32_t asm330lhbg1_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t asm330lhbg1_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhbg1_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHBG1_DRIVE_SLEEP_CHG_EVENT = 0, + ASM330LHBG1_DRIVE_SLEEP_STATUS = 1, +} asm330lhbg1_sleep_status_on_int_t; +int32_t asm330lhbg1_act_pin_notification_set(const stmdev_ctx_t *ctx, + asm330lhbg1_sleep_status_on_int_t val); +int32_t asm330lhbg1_act_pin_notification_get(const stmdev_ctx_t *ctx, + asm330lhbg1_sleep_status_on_int_t *val); + +typedef enum +{ + ASM330LHBG1_XL_AND_GY_NOT_AFFECTED = 0, + ASM330LHBG1_XL_12Hz5_GY_NOT_AFFECTED = 1, + ASM330LHBG1_XL_12Hz5_GY_SLEEP = 2, + ASM330LHBG1_XL_12Hz5_GY_PD = 3, +} asm330lhbg1_inact_en_t; +int32_t asm330lhbg1_act_mode_set(const stmdev_ctx_t *ctx, + asm330lhbg1_inact_en_t val); +int32_t asm330lhbg1_act_mode_get(const stmdev_ctx_t *ctx, + asm330lhbg1_inact_en_t *val); + +int32_t asm330lhbg1_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHBG1_DEG_80 = 0, + ASM330LHBG1_DEG_70 = 1, + ASM330LHBG1_DEG_60 = 2, + ASM330LHBG1_DEG_50 = 3, +} asm330lhbg1_sixd_ths_t; +int32_t asm330lhbg1_6d_threshold_set(const stmdev_ctx_t *ctx, + asm330lhbg1_sixd_ths_t val); +int32_t asm330lhbg1_6d_threshold_get(const stmdev_ctx_t *ctx, + asm330lhbg1_sixd_ths_t *val); + +int32_t asm330lhbg1_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHBG1_FF_TSH_156mg = 0, + ASM330LHBG1_FF_TSH_219mg = 1, + ASM330LHBG1_FF_TSH_250mg = 2, + ASM330LHBG1_FF_TSH_312mg = 3, + ASM330LHBG1_FF_TSH_344mg = 4, + ASM330LHBG1_FF_TSH_406mg = 5, + ASM330LHBG1_FF_TSH_469mg = 6, + ASM330LHBG1_FF_TSH_500mg = 7, +} asm330lhbg1_ff_ths_t; +int32_t asm330lhbg1_ff_threshold_set(const stmdev_ctx_t *ctx, + asm330lhbg1_ff_ths_t val); +int32_t asm330lhbg1_ff_threshold_get(const stmdev_ctx_t *ctx, + asm330lhbg1_ff_ths_t *val); + +int32_t asm330lhbg1_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhbg1_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhbg1_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t asm330lhbg1_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, + uint8_t val); +int32_t asm330lhbg1_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t asm330lhbg1_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHBG1_XL_NOT_BATCHED = 0, + ASM330LHBG1_XL_BATCHED_AT_12Hz5 = 1, + ASM330LHBG1_XL_BATCHED_AT_26Hz = 2, + ASM330LHBG1_XL_BATCHED_AT_52Hz = 3, + ASM330LHBG1_XL_BATCHED_AT_104Hz = 4, + ASM330LHBG1_XL_BATCHED_AT_208Hz = 5, + ASM330LHBG1_XL_BATCHED_AT_417Hz = 6, + ASM330LHBG1_XL_BATCHED_AT_833Hz = 7, + ASM330LHBG1_XL_BATCHED_AT_1667Hz = 8, + ASM330LHBG1_XL_BATCHED_AT_1Hz6 = 11, +} asm330lhbg1_bdr_xl_t; +int32_t asm330lhbg1_fifo_xl_batch_set(const stmdev_ctx_t *ctx, + asm330lhbg1_bdr_xl_t val); +int32_t asm330lhbg1_fifo_xl_batch_get(const stmdev_ctx_t *ctx, + asm330lhbg1_bdr_xl_t *val); + +typedef enum +{ + ASM330LHBG1_GY_NOT_BATCHED = 0, + ASM330LHBG1_GY_BATCHED_AT_12Hz5 = 1, + ASM330LHBG1_GY_BATCHED_AT_26Hz = 2, + ASM330LHBG1_GY_BATCHED_AT_52Hz = 3, + ASM330LHBG1_GY_BATCHED_AT_104Hz = 4, + ASM330LHBG1_GY_BATCHED_AT_208Hz = 5, + ASM330LHBG1_GY_BATCHED_AT_417Hz = 6, + ASM330LHBG1_GY_BATCHED_AT_833Hz = 7, + ASM330LHBG1_GY_BATCHED_AT_1667Hz = 8, + ASM330LHBG1_GY_BATCHED_AT_6Hz5 = 11, +} asm330lhbg1_bdr_gy_t; +int32_t asm330lhbg1_fifo_gy_batch_set(const stmdev_ctx_t *ctx, + asm330lhbg1_bdr_gy_t val); +int32_t asm330lhbg1_fifo_gy_batch_get(const stmdev_ctx_t *ctx, + asm330lhbg1_bdr_gy_t *val); + +typedef enum +{ + ASM330LHBG1_BYPASS_MODE = 0, + ASM330LHBG1_FIFO_MODE = 1, + ASM330LHBG1_STREAM_TO_FIFO_MODE = 3, + ASM330LHBG1_BYPASS_TO_STREAM_MODE = 4, + ASM330LHBG1_STREAM_MODE = 6, + ASM330LHBG1_BYPASS_TO_FIFO_MODE = 7, +} asm330lhbg1_fifo_mode_t; +int32_t asm330lhbg1_fifo_mode_set(const stmdev_ctx_t *ctx, asm330lhbg1_fifo_mode_t val); +int32_t asm330lhbg1_fifo_mode_get(const stmdev_ctx_t *ctx, + asm330lhbg1_fifo_mode_t *val); + +typedef enum +{ + ASM330LHBG1_TEMP_NOT_BATCHED = 0, + ASM330LHBG1_TEMP_BATCHED_AT_52Hz = 1, + ASM330LHBG1_TEMP_BATCHED_AT_12Hz5 = 2, + ASM330LHBG1_TEMP_BATCHED_AT_1Hz6 = 3, +} asm330lhbg1_odr_t_batch_t; +int32_t asm330lhbg1_fifo_temp_batch_set(const stmdev_ctx_t *ctx, + asm330lhbg1_odr_t_batch_t val); +int32_t asm330lhbg1_fifo_temp_batch_get(const stmdev_ctx_t *ctx, + asm330lhbg1_odr_t_batch_t *val); + +typedef enum +{ + ASM330LHBG1_NO_DECIMATION = 0, + ASM330LHBG1_DEC_1 = 1, + ASM330LHBG1_DEC_8 = 2, + ASM330LHBG1_DEC_32 = 3, +} asm330lhbg1_dec_ts_batch_t; +int32_t asm330lhbg1_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, + asm330lhbg1_dec_ts_batch_t val); +int32_t asm330lhbg1_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, + asm330lhbg1_dec_ts_batch_t *val); + +typedef enum +{ + ASM330LHBG1_XL_BATCH_EVENT = 0, + ASM330LHBG1_GYRO_BATCH_EVENT = 1, +} asm330lhbg1_trig_counter_bdr_t; +int32_t asm330lhbg1_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, + asm330lhbg1_trig_counter_bdr_t val); +int32_t asm330lhbg1_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, + asm330lhbg1_trig_counter_bdr_t *val); + +int32_t asm330lhbg1_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhbg1_batch_counter_threshold_set(const stmdev_ctx_t *ctx, + uint16_t val); +int32_t asm330lhbg1_batch_counter_threshold_get(const stmdev_ctx_t *ctx, + uint16_t *val); + +int32_t asm330lhbg1_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t asm330lhbg1_fifo_status_get(const stmdev_ctx_t *ctx, + asm330lhbg1_fifo_status2_t *val); + +int32_t asm330lhbg1_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhbg1_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhbg1_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHBG1_GYRO_NC_TAG = 0x01, + ASM330LHBG1_XL_NC_TAG = 0x02, + ASM330LHBG1_TEMPERATURE_TAG = 0x03, + ASM330LHBG1_TIMESTAMP_TAG = 0x04, + ASM330LHBG1_CFG_CHANGE_TAG = 0x05, +} asm330lhbg1_fifo_tag_t; +int32_t asm330lhbg1_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, + asm330lhbg1_fifo_tag_t *val); + +typedef enum +{ + ASM330LHBG1_DEN_DISABLE = 0, + ASM330LHBG1_LEVEL_FIFO = 6, + ASM330LHBG1_LEVEL_LETCHED = 3, + ASM330LHBG1_LEVEL_TRIGGER = 2, + ASM330LHBG1_EDGE_TRIGGER = 4, +} asm330lhbg1_den_mode_t; +int32_t asm330lhbg1_den_mode_set(const stmdev_ctx_t *ctx, + asm330lhbg1_den_mode_t val); +int32_t asm330lhbg1_den_mode_get(const stmdev_ctx_t *ctx, + asm330lhbg1_den_mode_t *val); + +typedef enum +{ + ASM330LHBG1_DEN_ACT_LOW = 0, + ASM330LHBG1_DEN_ACT_HIGH = 1, +} asm330lhbg1_den_lh_t; +int32_t asm330lhbg1_den_polarity_set(const stmdev_ctx_t *ctx, + asm330lhbg1_den_lh_t val); +int32_t asm330lhbg1_den_polarity_get(const stmdev_ctx_t *ctx, + asm330lhbg1_den_lh_t *val); + +typedef enum +{ + ASM330LHBG1_STAMP_IN_GY_DATA = 0, + ASM330LHBG1_STAMP_IN_XL_DATA = 1, + ASM330LHBG1_STAMP_IN_GY_XL_DATA = 2, +} asm330lhbg1_den_xl_g_t; +int32_t asm330lhbg1_den_enable_set(const stmdev_ctx_t *ctx, + asm330lhbg1_den_xl_g_t val); +int32_t asm330lhbg1_den_enable_get(const stmdev_ctx_t *ctx, + asm330lhbg1_den_xl_g_t *val); + +int32_t asm330lhbg1_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhbg1_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhbg1_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhbg1_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhbg1_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t asm330lhbg1_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val); +int32_t asm330lhbg1_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t asm330lhbg1_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint16_t *val); +int32_t asm330lhbg1_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val); + +typedef enum +{ + ASM330LHBG1_Z_EQ_Y = 0, + ASM330LHBG1_Z_EQ_MIN_Y = 1, + ASM330LHBG1_Z_EQ_X = 2, + ASM330LHBG1_Z_EQ_MIN_X = 3, + ASM330LHBG1_Z_EQ_MIN_Z = 4, + ASM330LHBG1_Z_EQ_Z = 5, +} asm330lhbg1_mag_z_axis_t; +int32_t asm330lhbg1_mag_z_orient_set(const stmdev_ctx_t *ctx, + asm330lhbg1_mag_z_axis_t val); +int32_t asm330lhbg1_mag_z_orient_get(const stmdev_ctx_t *ctx, + asm330lhbg1_mag_z_axis_t *val); + +typedef enum +{ + ASM330LHBG1_Y_EQ_Y = 0, + ASM330LHBG1_Y_EQ_MIN_Y = 1, + ASM330LHBG1_Y_EQ_X = 2, + ASM330LHBG1_Y_EQ_MIN_X = 3, + ASM330LHBG1_Y_EQ_MIN_Z = 4, + ASM330LHBG1_Y_EQ_Z = 5, +} asm330lhbg1_mag_y_axis_t; +int32_t asm330lhbg1_mag_y_orient_set(const stmdev_ctx_t *ctx, + asm330lhbg1_mag_y_axis_t val); +int32_t asm330lhbg1_mag_y_orient_get(const stmdev_ctx_t *ctx, + asm330lhbg1_mag_y_axis_t *val); + +typedef enum +{ + ASM330LHBG1_X_EQ_Y = 0, + ASM330LHBG1_X_EQ_MIN_Y = 1, + ASM330LHBG1_X_EQ_X = 2, + ASM330LHBG1_X_EQ_MIN_X = 3, + ASM330LHBG1_X_EQ_MIN_Z = 4, + ASM330LHBG1_X_EQ_Z = 5, +} asm330lhbg1_mag_x_axis_t; +int32_t asm330lhbg1_mag_x_orient_set(const stmdev_ctx_t *ctx, + asm330lhbg1_mag_x_axis_t val); +int32_t asm330lhbg1_mag_x_orient_get(const stmdev_ctx_t *ctx, + asm330lhbg1_mag_x_axis_t *val); + +typedef struct +{ + uint16_t fsm1 : 1; + uint16_t fsm2 : 1; + uint16_t fsm3 : 1; + uint16_t fsm4 : 1; + uint16_t fsm5 : 1; + uint16_t fsm6 : 1; + uint16_t fsm7 : 1; + uint16_t fsm8 : 1; + uint16_t fsm9 : 1; + uint16_t fsm10 : 1; + uint16_t fsm11 : 1; + uint16_t fsm12 : 1; + uint16_t fsm13 : 1; + uint16_t fsm14 : 1; + uint16_t fsm15 : 1; + uint16_t fsm16 : 1; +} asm330lhbg1_fsm_status_t; +int32_t asm330lhbg1_fsm_status_get(const stmdev_ctx_t *ctx, + asm330lhbg1_fsm_status_t *val); +int32_t asm330lhbg1_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t asm330lhbg1_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t asm330lhbg1_emb_func_clk_dis_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_emb_func_clk_dis_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhbg1_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + asm330lhbg1_fsm_enable_a_t fsm_enable_a; + asm330lhbg1_fsm_enable_b_t fsm_enable_b; +} asm330lhbg1_emb_fsm_enable_t; +int32_t asm330lhbg1_fsm_enable_set(const stmdev_ctx_t *ctx, + asm330lhbg1_emb_fsm_enable_t *val); +int32_t asm330lhbg1_fsm_enable_get(const stmdev_ctx_t *ctx, + asm330lhbg1_emb_fsm_enable_t *val); + +int32_t asm330lhbg1_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhbg1_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); + +typedef enum +{ + ASM330LHBG1_LC_NORMAL = 0, + ASM330LHBG1_LC_CLEAR = 1, + ASM330LHBG1_LC_CLEAR_DONE = 2, +} asm330lhbg1_fsm_lc_clr_t; +int32_t asm330lhbg1_long_clr_set(const stmdev_ctx_t *ctx, + asm330lhbg1_fsm_lc_clr_t val); +int32_t asm330lhbg1_long_clr_get(const stmdev_ctx_t *ctx, + asm330lhbg1_fsm_lc_clr_t *val); + +typedef enum +{ + ASM330LHBG1_ODR_FSM_12Hz5 = 0, + ASM330LHBG1_ODR_FSM_26Hz = 1, + ASM330LHBG1_ODR_FSM_52Hz = 2, + ASM330LHBG1_ODR_FSM_104Hz = 3, +} asm330lhbg1_fsm_odr_t; +int32_t asm330lhbg1_fsm_data_rate_set(const stmdev_ctx_t *ctx, + asm330lhbg1_fsm_odr_t val); +int32_t asm330lhbg1_fsm_data_rate_get(const stmdev_ctx_t *ctx, + asm330lhbg1_fsm_odr_t *val); + +int32_t asm330lhbg1_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhbg1_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhbg1_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t asm330lhbg1_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, + uint8_t *buff); +int32_t asm330lhbg1_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, + uint8_t *buff); + +int32_t asm330lhbg1_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhbg1_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t asm330lhbg1_mlc_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhbg1_mlc_status_get(const stmdev_ctx_t *ctx, + asm330lhbg1_mlc_status_mainpage_t *val); + +typedef enum +{ + ASM330LHBG1_ODR_PRGS_12Hz5 = 0, + ASM330LHBG1_ODR_PRGS_26Hz = 1, + ASM330LHBG1_ODR_PRGS_52Hz = 2, + ASM330LHBG1_ODR_PRGS_104Hz = 3, +} asm330lhbg1_mlc_odr_t; +int32_t asm330lhbg1_mlc_data_rate_set(const stmdev_ctx_t *ctx, + asm330lhbg1_mlc_odr_t val); +int32_t asm330lhbg1_mlc_data_rate_get(const stmdev_ctx_t *ctx, + asm330lhbg1_mlc_odr_t *val); + +int32_t asm330lhbg1_mlc_init_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhbg1_mlc_init_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhbg1_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t asm330lhbg1_mlc_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhbg1_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); + +/** + *@} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ASM330LHBG1_REGS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.c b/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.c index 4a8a5b44..dc69d7e2 100644 --- a/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.c +++ b/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.c @@ -46,12 +46,14 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak asm330lhh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak asm330lhh_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +69,14 @@ int32_t __weak asm330lhh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak asm330lhh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak asm330lhh_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -171,7 +175,7 @@ float_t asm330lhh_from_lsb_to_nsec(int32_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_full_scale_set(const stmdev_ctx_t *ctx, asm330lhh_fs_xl_t val) { asm330lhh_ctrl1_xl_t ctrl1_xl; @@ -198,7 +202,7 @@ int32_t asm330lhh_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_full_scale_get(const stmdev_ctx_t *ctx, asm330lhh_fs_xl_t *val) { asm330lhh_ctrl1_xl_t ctrl1_xl; @@ -241,7 +245,7 @@ int32_t asm330lhh_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_data_rate_set(const stmdev_ctx_t *ctx, asm330lhh_odr_xl_t val) { asm330lhh_ctrl1_xl_t ctrl1_xl; @@ -268,7 +272,7 @@ int32_t asm330lhh_xl_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_data_rate_get(const stmdev_ctx_t *ctx, asm330lhh_odr_xl_t *val) { asm330lhh_ctrl1_xl_t ctrl1_xl; @@ -339,7 +343,7 @@ int32_t asm330lhh_xl_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_gy_full_scale_set(const stmdev_ctx_t *ctx, asm330lhh_fs_g_t val) { asm330lhh_ctrl2_g_t ctrl2_g; @@ -364,7 +368,7 @@ int32_t asm330lhh_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_gy_full_scale_get(const stmdev_ctx_t *ctx, asm330lhh_fs_g_t *val) { asm330lhh_ctrl2_g_t ctrl2_g; @@ -414,7 +418,7 @@ int32_t asm330lhh_gy_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_gy_data_rate_set(const stmdev_ctx_t *ctx, asm330lhh_odr_g_t val) { asm330lhh_ctrl2_g_t ctrl2_g; @@ -439,7 +443,7 @@ int32_t asm330lhh_gy_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_gy_data_rate_get(const stmdev_ctx_t *ctx, asm330lhh_odr_g_t *val) { asm330lhh_ctrl2_g_t ctrl2_g; @@ -509,7 +513,7 @@ int32_t asm330lhh_gy_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_block_data_update_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhh_ctrl3_c_t ctrl3_c; @@ -534,7 +538,7 @@ int32_t asm330lhh_block_data_update_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_block_data_update_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_ctrl3_c_t ctrl3_c; @@ -555,7 +559,7 @@ int32_t asm330lhh_block_data_update_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_offset_weight_set(const stmdev_ctx_t *ctx, asm330lhh_usr_off_w_t val) { asm330lhh_ctrl6_c_t ctrl6_c; @@ -581,7 +585,7 @@ int32_t asm330lhh_xl_offset_weight_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_offset_weight_get(const stmdev_ctx_t *ctx, asm330lhh_usr_off_w_t *val) { asm330lhh_ctrl6_c_t ctrl6_c; @@ -617,7 +621,7 @@ int32_t asm330lhh_xl_offset_weight_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_all_sources_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_all_sources_get(const stmdev_ctx_t *ctx, asm330lhh_all_sources_t *val) { int32_t ret; @@ -654,7 +658,7 @@ int32_t asm330lhh_all_sources_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_status_reg_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_status_reg_get(const stmdev_ctx_t *ctx, asm330lhh_status_reg_t *val) { int32_t ret; @@ -672,7 +676,7 @@ int32_t asm330lhh_status_reg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_status_reg_t status_reg; @@ -693,7 +697,7 @@ int32_t asm330lhh_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_status_reg_t status_reg; @@ -714,7 +718,7 @@ int32_t asm330lhh_gy_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_status_reg_t status_reg; @@ -737,7 +741,7 @@ int32_t asm330lhh_temp_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_usr_offset_x_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -757,7 +761,7 @@ int32_t asm330lhh_xl_usr_offset_x_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_usr_offset_x_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -777,7 +781,7 @@ int32_t asm330lhh_xl_usr_offset_x_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_usr_offset_y_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -797,7 +801,7 @@ int32_t asm330lhh_xl_usr_offset_y_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_usr_offset_y_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -817,7 +821,7 @@ int32_t asm330lhh_xl_usr_offset_y_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_usr_offset_z_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -837,7 +841,7 @@ int32_t asm330lhh_xl_usr_offset_z_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_usr_offset_z_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -855,7 +859,7 @@ int32_t asm330lhh_xl_usr_offset_z_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhh_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhh_ctrl7_g_t ctrl7_g; int32_t ret; @@ -879,7 +883,7 @@ int32_t asm330lhh_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhh_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_ctrl7_g_t ctrl7_g; int32_t ret; @@ -910,7 +914,7 @@ int32_t asm330lhh_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_timestamp_rst(stmdev_ctx_t *ctx) +int32_t asm330lhh_timestamp_rst(const stmdev_ctx_t *ctx) { uint8_t rst_val = 0xAA; return asm330lhh_write_reg(ctx, ASM330LHH_TIMESTAMP2, &rst_val, 1); @@ -924,7 +928,7 @@ int32_t asm330lhh_timestamp_rst(stmdev_ctx_t *ctx) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhh_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhh_ctrl10_c_t ctrl10_c; int32_t ret; @@ -950,7 +954,7 @@ int32_t asm330lhh_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhh_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_ctrl10_c_t ctrl10_c; int32_t ret; @@ -972,7 +976,7 @@ int32_t asm330lhh_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t asm330lhh_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; @@ -1006,7 +1010,7 @@ int32_t asm330lhh_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_rounding_mode_set(const stmdev_ctx_t *ctx, asm330lhh_rounding_t val) { asm330lhh_ctrl5_c_t ctrl5_c; @@ -1031,7 +1035,7 @@ int32_t asm330lhh_rounding_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_rounding_mode_get(const stmdev_ctx_t *ctx, asm330lhh_rounding_t *val) { asm330lhh_ctrl5_c_t ctrl5_c; @@ -1075,7 +1079,7 @@ int32_t asm330lhh_rounding_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t asm330lhh_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1096,7 +1100,7 @@ int32_t asm330lhh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_angular_rate_raw_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -1122,7 +1126,7 @@ int32_t asm330lhh_angular_rate_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -1147,7 +1151,7 @@ int32_t asm330lhh_acceleration_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhh_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -1176,7 +1180,7 @@ int32_t asm330lhh_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_device_conf_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhh_device_conf_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhh_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -1202,7 +1206,7 @@ int32_t asm330lhh_device_conf_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_device_conf_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhh_device_conf_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -1224,7 +1228,7 @@ int32_t asm330lhh_device_conf_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhh_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhh_internal_freq_fine_t internal_freq_fine; int32_t ret; @@ -1252,7 +1256,7 @@ int32_t asm330lhh_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhh_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_internal_freq_fine_t internal_freq_fine; int32_t ret; @@ -1273,7 +1277,7 @@ int32_t asm330lhh_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_data_ready_mode_set(const stmdev_ctx_t *ctx, asm330lhh_dataready_pulsed_t val) { asm330lhh_counter_bdr_reg1_t counter_bdr_reg1; @@ -1301,7 +1305,7 @@ int32_t asm330lhh_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_data_ready_mode_get(const stmdev_ctx_t *ctx, asm330lhh_dataready_pulsed_t *val) { asm330lhh_counter_bdr_reg1_t counter_bdr_reg1; @@ -1336,7 +1340,7 @@ int32_t asm330lhh_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t asm330lhh_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1353,7 +1357,7 @@ int32_t asm330lhh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhh_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhh_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1377,7 +1381,7 @@ int32_t asm330lhh_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1397,7 +1401,7 @@ int32_t asm330lhh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhh_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhh_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1422,7 +1426,7 @@ int32_t asm330lhh_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhh_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1441,7 +1445,7 @@ int32_t asm330lhh_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhh_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhh_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1465,7 +1469,7 @@ int32_t asm330lhh_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhh_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1486,7 +1490,7 @@ int32_t asm330lhh_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_self_test_set(const stmdev_ctx_t *ctx, asm330lhh_st_xl_t val) { asm330lhh_ctrl5_c_t ctrl5_c; @@ -1511,7 +1515,7 @@ int32_t asm330lhh_xl_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_self_test_get(const stmdev_ctx_t *ctx, asm330lhh_st_xl_t *val) { asm330lhh_ctrl5_c_t ctrl5_c; @@ -1549,7 +1553,7 @@ int32_t asm330lhh_xl_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_gy_self_test_set(const stmdev_ctx_t *ctx, asm330lhh_st_g_t val) { asm330lhh_ctrl5_c_t ctrl5_c; @@ -1574,7 +1578,7 @@ int32_t asm330lhh_gy_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_gy_self_test_get(const stmdev_ctx_t *ctx, asm330lhh_st_g_t *val) { asm330lhh_ctrl5_c_t ctrl5_c; @@ -1625,7 +1629,7 @@ int32_t asm330lhh_gy_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhh_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhh_ctrl1_xl_t ctrl1_xl; int32_t ret; @@ -1651,7 +1655,7 @@ int32_t asm330lhh_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhh_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_ctrl1_xl_t ctrl1_xl; int32_t ret; @@ -1672,7 +1676,7 @@ int32_t asm330lhh_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhh_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhh_ctrl4_c_t ctrl4_c; int32_t ret; @@ -1697,7 +1701,7 @@ int32_t asm330lhh_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhh_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_ctrl4_c_t ctrl4_c; int32_t ret; @@ -1717,7 +1721,7 @@ int32_t asm330lhh_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhh_ctrl4_c_t ctrl4_c; @@ -1743,7 +1747,7 @@ int32_t asm330lhh_filter_settling_mask_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_ctrl4_c_t ctrl4_c; @@ -1763,7 +1767,7 @@ int32_t asm330lhh_filter_settling_mask_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, asm330lhh_ftype_t val) { asm330lhh_ctrl6_c_t ctrl6_c; @@ -1788,7 +1792,7 @@ int32_t asm330lhh_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, asm330lhh_ftype_t *val) { asm330lhh_ctrl6_c_t ctrl6_c; @@ -1846,7 +1850,7 @@ int32_t asm330lhh_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhh_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhh_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -1872,7 +1876,7 @@ int32_t asm330lhh_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhh_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -1893,7 +1897,7 @@ int32_t asm330lhh_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, asm330lhh_hp_slope_xl_en_t val) { asm330lhh_ctrl8_xl_t ctrl8_xl; @@ -1923,7 +1927,7 @@ int32_t asm330lhh_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, asm330lhh_hp_slope_xl_en_t *val) { asm330lhh_ctrl8_xl_t ctrl8_xl; @@ -2046,7 +2050,7 @@ int32_t asm330lhh_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhh_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhh_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -2074,7 +2078,7 @@ int32_t asm330lhh_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_fast_settling_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_ctrl8_xl_t ctrl8_xl; @@ -2096,7 +2100,7 @@ int32_t asm330lhh_xl_fast_settling_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, asm330lhh_slope_fds_t val) { asm330lhh_int_cfg0_t int_cfg0; @@ -2124,7 +2128,7 @@ int32_t asm330lhh_xl_hp_path_internal_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, asm330lhh_slope_fds_t *val) { asm330lhh_int_cfg0_t int_cfg0; @@ -2160,7 +2164,7 @@ int32_t asm330lhh_xl_hp_path_internal_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_gy_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, asm330lhh_hpm_g_t val) { asm330lhh_ctrl7_g_t ctrl7_g; @@ -2187,7 +2191,7 @@ int32_t asm330lhh_gy_hp_path_internal_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_gy_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, asm330lhh_hpm_g_t *val) { asm330lhh_ctrl7_g_t ctrl7_g; @@ -2246,7 +2250,7 @@ int32_t asm330lhh_gy_hp_path_internal_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, asm330lhh_sdo_pu_en_t val) { asm330lhh_pin_ctrl_t pin_ctrl; @@ -2273,7 +2277,7 @@ int32_t asm330lhh_sdo_sa0_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, asm330lhh_sdo_pu_en_t *val) { asm330lhh_pin_ctrl_t pin_ctrl; @@ -2308,7 +2312,7 @@ int32_t asm330lhh_sdo_sa0_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_spi_mode_set(stmdev_ctx_t *ctx, asm330lhh_sim_t val) +int32_t asm330lhh_spi_mode_set(const stmdev_ctx_t *ctx, asm330lhh_sim_t val) { asm330lhh_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2332,7 +2336,7 @@ int32_t asm330lhh_spi_mode_set(stmdev_ctx_t *ctx, asm330lhh_sim_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_spi_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_spi_mode_get(const stmdev_ctx_t *ctx, asm330lhh_sim_t *val) { asm330lhh_ctrl3_c_t ctrl3_c; @@ -2366,7 +2370,7 @@ int32_t asm330lhh_spi_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_i2c_interface_set(const stmdev_ctx_t *ctx, asm330lhh_i2c_disable_t val) { asm330lhh_ctrl4_c_t ctrl4_c; @@ -2391,7 +2395,7 @@ int32_t asm330lhh_i2c_interface_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_i2c_interface_get(const stmdev_ctx_t *ctx, asm330lhh_i2c_disable_t *val) { asm330lhh_ctrl4_c_t ctrl4_c; @@ -2439,7 +2443,7 @@ int32_t asm330lhh_i2c_interface_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_pin_int1_route_set(const stmdev_ctx_t *ctx, asm330lhh_pin_int1_route_t *val) { asm330lhh_int_cfg1_t tap_cfg2; @@ -2499,7 +2503,7 @@ int32_t asm330lhh_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_pin_int1_route_get(const stmdev_ctx_t *ctx, asm330lhh_pin_int1_route_t *val) { int32_t ret; @@ -2525,7 +2529,7 @@ int32_t asm330lhh_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_pin_int2_route_set(const stmdev_ctx_t *ctx, asm330lhh_pin_int2_route_t *val) { asm330lhh_int_cfg1_t tap_cfg2; @@ -2584,7 +2588,7 @@ int32_t asm330lhh_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_pin_int2_route_get(const stmdev_ctx_t *ctx, asm330lhh_pin_int2_route_t *val) { int32_t ret; @@ -2609,7 +2613,7 @@ int32_t asm330lhh_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_pin_mode_set(const stmdev_ctx_t *ctx, asm330lhh_pp_od_t val) { asm330lhh_ctrl3_c_t ctrl3_c; @@ -2634,7 +2638,7 @@ int32_t asm330lhh_pin_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_pin_mode_get(const stmdev_ctx_t *ctx, asm330lhh_pp_od_t *val) { asm330lhh_ctrl3_c_t ctrl3_c; @@ -2668,7 +2672,7 @@ int32_t asm330lhh_pin_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_pin_polarity_set(const stmdev_ctx_t *ctx, asm330lhh_h_lactive_t val) { asm330lhh_ctrl3_c_t ctrl3_c; @@ -2693,7 +2697,7 @@ int32_t asm330lhh_pin_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_pin_polarity_get(const stmdev_ctx_t *ctx, asm330lhh_h_lactive_t *val) { asm330lhh_ctrl3_c_t ctrl3_c; @@ -2727,7 +2731,7 @@ int32_t asm330lhh_pin_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhh_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhh_ctrl4_c_t ctrl4_c; int32_t ret; @@ -2751,7 +2755,7 @@ int32_t asm330lhh_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhh_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_ctrl4_c_t ctrl4_c; int32_t ret; @@ -2770,7 +2774,7 @@ int32_t asm330lhh_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_int_notification_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_int_notification_set(const stmdev_ctx_t *ctx, asm330lhh_lir_t val) { asm330lhh_int_cfg0_t int_cfg0; @@ -2798,7 +2802,7 @@ int32_t asm330lhh_int_notification_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_int_notification_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_int_notification_get(const stmdev_ctx_t *ctx, asm330lhh_lir_t *val) { asm330lhh_int_cfg0_t int_cfg0; @@ -2849,7 +2853,7 @@ int32_t asm330lhh_int_notification_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_wkup_ths_weight_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_wkup_ths_weight_set(const stmdev_ctx_t *ctx, asm330lhh_wake_ths_w_t val) { asm330lhh_wake_up_dur_t wake_up_dur; @@ -2878,7 +2882,7 @@ int32_t asm330lhh_wkup_ths_weight_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_wkup_ths_weight_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_wkup_ths_weight_get(const stmdev_ctx_t *ctx, asm330lhh_wake_ths_w_t *val) { asm330lhh_wake_up_dur_t wake_up_dur; @@ -2914,7 +2918,7 @@ int32_t asm330lhh_wkup_ths_weight_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhh_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhh_wake_up_ths_t wake_up_ths; int32_t ret; @@ -2941,7 +2945,7 @@ int32_t asm330lhh_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhh_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_wake_up_ths_t wake_up_ths; int32_t ret; @@ -2961,7 +2965,7 @@ int32_t asm330lhh_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhh_wake_up_ths_t wake_up_ths; @@ -2988,7 +2992,7 @@ int32_t asm330lhh_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_wake_up_ths_t wake_up_ths; @@ -3009,7 +3013,7 @@ int32_t asm330lhh_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhh_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhh_wake_up_dur_t wake_up_dur; int32_t ret; @@ -3035,7 +3039,7 @@ int32_t asm330lhh_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhh_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_wake_up_dur_t wake_up_dur; int32_t ret; @@ -3068,7 +3072,7 @@ int32_t asm330lhh_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhh_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhh_ctrl4_c_t ctrl4_c; int32_t ret; @@ -3092,7 +3096,7 @@ int32_t asm330lhh_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhh_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_ctrl4_c_t ctrl4_c; int32_t ret; @@ -3113,7 +3117,7 @@ int32_t asm330lhh_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_act_pin_notification_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_act_pin_notification_set(const stmdev_ctx_t *ctx, asm330lhh_sleep_status_on_int_t val) { asm330lhh_int_cfg0_t int_cfg0; @@ -3142,7 +3146,7 @@ int32_t asm330lhh_act_pin_notification_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_act_pin_notification_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_act_pin_notification_get(const stmdev_ctx_t *ctx, asm330lhh_sleep_status_on_int_t *val) { asm330lhh_int_cfg0_t int_cfg0; @@ -3177,7 +3181,7 @@ int32_t asm330lhh_act_pin_notification_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_act_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_act_mode_set(const stmdev_ctx_t *ctx, asm330lhh_inact_en_t val) { asm330lhh_int_cfg1_t int_cfg1; @@ -3204,7 +3208,7 @@ int32_t asm330lhh_act_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_act_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_act_mode_get(const stmdev_ctx_t *ctx, asm330lhh_inact_en_t *val) { asm330lhh_int_cfg1_t int_cfg1; @@ -3247,7 +3251,7 @@ int32_t asm330lhh_act_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhh_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhh_wake_up_dur_t wake_up_dur; int32_t ret; @@ -3273,7 +3277,7 @@ int32_t asm330lhh_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhh_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_wake_up_dur_t wake_up_dur; int32_t ret; @@ -3306,7 +3310,7 @@ int32_t asm330lhh_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_6d_threshold_set(const stmdev_ctx_t *ctx, asm330lhh_sixd_ths_t val) { asm330lhh_ths_6d_t ths_6d; @@ -3333,7 +3337,7 @@ int32_t asm330lhh_6d_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_6d_threshold_get(const stmdev_ctx_t *ctx, asm330lhh_sixd_ths_t *val) { asm330lhh_ths_6d_t ths_6d; @@ -3376,7 +3380,7 @@ int32_t asm330lhh_6d_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhh_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhh_ths_6d_t ths_6d; int32_t ret; @@ -3402,7 +3406,7 @@ int32_t asm330lhh_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhh_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_ths_6d_t ths_6d; int32_t ret; @@ -3435,7 +3439,7 @@ int32_t asm330lhh_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_ff_threshold_set(const stmdev_ctx_t *ctx, asm330lhh_ff_ths_t val) { asm330lhh_free_fall_t free_fall; @@ -3462,7 +3466,7 @@ int32_t asm330lhh_ff_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_ff_threshold_get(const stmdev_ctx_t *ctx, asm330lhh_ff_ths_t *val) { asm330lhh_free_fall_t free_fall; @@ -3521,7 +3525,7 @@ int32_t asm330lhh_ff_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhh_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhh_wake_up_dur_t wake_up_dur; asm330lhh_free_fall_t free_fall; @@ -3561,7 +3565,7 @@ int32_t asm330lhh_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhh_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_wake_up_dur_t wake_up_dur; asm330lhh_free_fall_t free_fall; @@ -3602,7 +3606,7 @@ int32_t asm330lhh_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t asm330lhh_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val) { asm330lhh_fifo_ctrl1_t fifo_ctrl1; asm330lhh_fifo_ctrl2_t fifo_ctrl2; @@ -3636,7 +3640,7 @@ int32_t asm330lhh_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t asm330lhh_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) { asm330lhh_fifo_ctrl1_t fifo_ctrl1; asm330lhh_fifo_ctrl2_t fifo_ctrl2; @@ -3664,7 +3668,7 @@ int32_t asm330lhh_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhh_fifo_ctrl2_t fifo_ctrl2; @@ -3691,7 +3695,7 @@ int32_t asm330lhh_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_fifo_ctrl2_t fifo_ctrl2; @@ -3713,7 +3717,7 @@ int32_t asm330lhh_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhh_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhh_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -3740,7 +3744,7 @@ int32_t asm330lhh_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_fifo_ctrl2_t fifo_ctrl2; @@ -3762,7 +3766,7 @@ int32_t asm330lhh_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_xl_batch_set(const stmdev_ctx_t *ctx, asm330lhh_bdr_xl_t val) { asm330lhh_fifo_ctrl3_t fifo_ctrl3; @@ -3790,7 +3794,7 @@ int32_t asm330lhh_fifo_xl_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_xl_batch_get(const stmdev_ctx_t *ctx, asm330lhh_bdr_xl_t *val) { asm330lhh_fifo_ctrl3_t fifo_ctrl3; @@ -3866,7 +3870,7 @@ int32_t asm330lhh_fifo_xl_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_gy_batch_set(const stmdev_ctx_t *ctx, asm330lhh_bdr_gy_t val) { asm330lhh_fifo_ctrl3_t fifo_ctrl3; @@ -3894,7 +3898,7 @@ int32_t asm330lhh_fifo_gy_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_gy_batch_get(const stmdev_ctx_t *ctx, asm330lhh_bdr_gy_t *val) { asm330lhh_fifo_ctrl3_t fifo_ctrl3; @@ -3969,7 +3973,7 @@ int32_t asm330lhh_fifo_gy_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_mode_set(const stmdev_ctx_t *ctx, asm330lhh_fifo_mode_t val) { asm330lhh_fifo_ctrl4_t fifo_ctrl4; @@ -3996,7 +4000,7 @@ int32_t asm330lhh_fifo_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_mode_get(const stmdev_ctx_t *ctx, asm330lhh_fifo_mode_t *val) { asm330lhh_fifo_ctrl4_t fifo_ctrl4; @@ -4048,7 +4052,7 @@ int32_t asm330lhh_fifo_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_temp_batch_set(const stmdev_ctx_t *ctx, asm330lhh_odr_t_batch_t val) { asm330lhh_fifo_ctrl4_t fifo_ctrl4; @@ -4076,7 +4080,7 @@ int32_t asm330lhh_fifo_temp_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_temp_batch_get(const stmdev_ctx_t *ctx, asm330lhh_odr_t_batch_t *val) { asm330lhh_fifo_ctrl4_t fifo_ctrl4; @@ -4121,7 +4125,7 @@ int32_t asm330lhh_fifo_temp_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, asm330lhh_odr_ts_batch_t val) { asm330lhh_fifo_ctrl4_t fifo_ctrl4; @@ -4151,7 +4155,7 @@ int32_t asm330lhh_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, asm330lhh_odr_ts_batch_t *val) { asm330lhh_fifo_ctrl4_t fifo_ctrl4; @@ -4196,7 +4200,7 @@ int32_t asm330lhh_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, asm330lhh_trig_counter_bdr_t val) { asm330lhh_counter_bdr_reg1_t counter_bdr_reg1; @@ -4225,7 +4229,7 @@ int32_t asm330lhh_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, asm330lhh_trig_counter_bdr_t *val) { asm330lhh_counter_bdr_reg1_t counter_bdr_reg1; @@ -4261,7 +4265,7 @@ int32_t asm330lhh_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_rst_batch_counter_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhh_counter_bdr_reg1_t counter_bdr_reg1; @@ -4289,7 +4293,7 @@ int32_t asm330lhh_rst_batch_counter_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_rst_batch_counter_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_counter_bdr_reg1_t counter_bdr_reg1; @@ -4311,7 +4315,7 @@ int32_t asm330lhh_rst_batch_counter_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_batch_counter_threshold_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { asm330lhh_counter_bdr_reg2_t counter_bdr_reg1; @@ -4348,7 +4352,7 @@ int32_t asm330lhh_batch_counter_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { asm330lhh_counter_bdr_reg1_t counter_bdr_reg1; @@ -4378,7 +4382,7 @@ int32_t asm330lhh_batch_counter_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_fifo_data_level_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) { asm330lhh_fifo_status1_t fifo_status1; @@ -4407,7 +4411,7 @@ int32_t asm330lhh_fifo_data_level_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_fifo_status_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_status_get(const stmdev_ctx_t *ctx, asm330lhh_fifo_status2_t *val) { int32_t ret; @@ -4425,7 +4429,7 @@ int32_t asm330lhh_fifo_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhh_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_fifo_status2_t fifo_status2; int32_t ret; @@ -4446,7 +4450,7 @@ int32_t asm330lhh_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhh_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_fifo_status2_t fifo_status2; int32_t ret; @@ -4466,7 +4470,7 @@ int32_t asm330lhh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhh_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_fifo_status2_t fifo_status2; int32_t ret; @@ -4486,7 +4490,7 @@ int32_t asm330lhh_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_fifo_sensor_tag_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, asm330lhh_fifo_tag_t *val) { asm330lhh_fifo_data_out_tag_t fifo_data_out_tag; @@ -4546,7 +4550,7 @@ int32_t asm330lhh_fifo_sensor_tag_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_den_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_den_mode_set(const stmdev_ctx_t *ctx, asm330lhh_den_mode_t val) { asm330lhh_ctrl6_c_t ctrl6_c; @@ -4571,7 +4575,7 @@ int32_t asm330lhh_den_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_den_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_den_mode_get(const stmdev_ctx_t *ctx, asm330lhh_den_mode_t *val) { asm330lhh_ctrl6_c_t ctrl6_c; @@ -4617,7 +4621,7 @@ int32_t asm330lhh_den_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_den_polarity_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_den_polarity_set(const stmdev_ctx_t *ctx, asm330lhh_den_lh_t val) { asm330lhh_ctrl9_xl_t ctrl9_xl; @@ -4644,7 +4648,7 @@ int32_t asm330lhh_den_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_den_polarity_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_den_polarity_get(const stmdev_ctx_t *ctx, asm330lhh_den_lh_t *val) { asm330lhh_ctrl9_xl_t ctrl9_xl; @@ -4679,7 +4683,7 @@ int32_t asm330lhh_den_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_den_enable_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_den_enable_set(const stmdev_ctx_t *ctx, asm330lhh_den_xl_g_t val) { asm330lhh_ctrl9_xl_t ctrl9_xl; @@ -4706,7 +4710,7 @@ int32_t asm330lhh_den_enable_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_den_enable_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_den_enable_get(const stmdev_ctx_t *ctx, asm330lhh_den_xl_g_t *val) { asm330lhh_ctrl9_xl_t ctrl9_xl; @@ -4745,7 +4749,7 @@ int32_t asm330lhh_den_enable_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhh_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhh_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -4771,7 +4775,7 @@ int32_t asm330lhh_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhh_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -4791,7 +4795,7 @@ int32_t asm330lhh_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhh_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhh_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -4817,7 +4821,7 @@ int32_t asm330lhh_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhh_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -4837,7 +4841,7 @@ int32_t asm330lhh_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhh_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhh_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -4863,7 +4867,7 @@ int32_t asm330lhh_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhh_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhh_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhh_ctrl9_xl_t ctrl9_xl; int32_t ret; diff --git a/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.h b/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.h index 28cc0d98..4b2abcc6 100644 --- a/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.h +++ b/sensor/stmemsc/asm330lhh_STdC/driver/asm330lhh_reg.h @@ -874,10 +874,10 @@ typedef union * them with a custom implementation. */ -int32_t asm330lhh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t asm330lhh_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t asm330lhh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t asm330lhh_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -904,9 +904,9 @@ typedef enum ASM330LHH_4g = 2, ASM330LHH_8g = 3, } asm330lhh_fs_xl_t; -int32_t asm330lhh_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_full_scale_set(const stmdev_ctx_t *ctx, asm330lhh_fs_xl_t val); -int32_t asm330lhh_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_full_scale_get(const stmdev_ctx_t *ctx, asm330lhh_fs_xl_t *val); typedef enum @@ -923,9 +923,9 @@ typedef enum ASM330LHH_XL_ODR_3333Hz = 9, ASM330LHH_XL_ODR_6667Hz = 10, } asm330lhh_odr_xl_t; -int32_t asm330lhh_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_data_rate_set(const stmdev_ctx_t *ctx, asm330lhh_odr_xl_t val); -int32_t asm330lhh_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_data_rate_get(const stmdev_ctx_t *ctx, asm330lhh_odr_xl_t *val); typedef enum @@ -937,9 +937,9 @@ typedef enum ASM330LHH_2000dps = 12, ASM330LHH_4000dps = 1, } asm330lhh_fs_g_t; -int32_t asm330lhh_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_gy_full_scale_set(const stmdev_ctx_t *ctx, asm330lhh_fs_g_t val); -int32_t asm330lhh_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_gy_full_scale_get(const stmdev_ctx_t *ctx, asm330lhh_fs_g_t *val); typedef enum @@ -956,14 +956,14 @@ typedef enum ASM330LHH_GY_ODR_3333Hz = 9, ASM330LHH_GY_ODR_6667Hz = 10, } asm330lhh_odr_g_t; -int32_t asm330lhh_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_gy_data_rate_set(const stmdev_ctx_t *ctx, asm330lhh_odr_g_t val); -int32_t asm330lhh_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_gy_data_rate_get(const stmdev_ctx_t *ctx, asm330lhh_odr_g_t *val); -int32_t asm330lhh_block_data_update_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhh_block_data_update_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -971,9 +971,9 @@ typedef enum ASM330LHH_LSb_1mg = 0, ASM330LHH_LSb_16mg = 1, } asm330lhh_usr_off_w_t; -int32_t asm330lhh_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_offset_weight_set(const stmdev_ctx_t *ctx, asm330lhh_usr_off_w_t val); -int32_t asm330lhh_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_offset_weight_get(const stmdev_ctx_t *ctx, asm330lhh_usr_off_w_t *val); typedef struct @@ -983,45 +983,45 @@ typedef struct asm330lhh_d6d_src_t d6d_src; asm330lhh_status_reg_t status_reg; } asm330lhh_all_sources_t; -int32_t asm330lhh_all_sources_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_all_sources_get(const stmdev_ctx_t *ctx, asm330lhh_all_sources_t *val); -int32_t asm330lhh_status_reg_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_status_reg_get(const stmdev_ctx_t *ctx, asm330lhh_status_reg_t *val); -int32_t asm330lhh_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhh_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhh_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhh_xl_usr_offset_x_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t asm330lhh_xl_usr_offset_x_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t asm330lhh_xl_usr_offset_y_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t asm330lhh_xl_usr_offset_y_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t asm330lhh_xl_usr_offset_z_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t asm330lhh_xl_usr_offset_z_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t asm330lhh_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhh_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhh_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhh_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhh_timestamp_rst(stmdev_ctx_t *ctx); +int32_t asm330lhh_timestamp_rst(const stmdev_ctx_t *ctx); -int32_t asm330lhh_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhh_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhh_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhh_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhh_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); +int32_t asm330lhh_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); typedef enum { @@ -1030,48 +1030,48 @@ typedef enum ASM330LHH_ROUND_GY = 2, ASM330LHH_ROUND_GY_XL = 3, } asm330lhh_rounding_t; -int32_t asm330lhh_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_rounding_mode_set(const stmdev_ctx_t *ctx, asm330lhh_rounding_t val); -int32_t asm330lhh_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_rounding_mode_get(const stmdev_ctx_t *ctx, asm330lhh_rounding_t *val); -int32_t asm330lhh_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t asm330lhh_angular_rate_raw_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t asm330lhh_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t asm330lhh_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhh_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhh_device_conf_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhh_device_conf_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhh_device_conf_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhh_device_conf_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhh_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhh_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhh_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhh_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { ASM330LHH_DRDY_LATCHED = 0, ASM330LHH_DRDY_PULSED = 1, } asm330lhh_dataready_pulsed_t; -int32_t asm330lhh_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_data_ready_mode_set(const stmdev_ctx_t *ctx, asm330lhh_dataready_pulsed_t val); -int32_t asm330lhh_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_data_ready_mode_get(const stmdev_ctx_t *ctx, asm330lhh_dataready_pulsed_t *val); -int32_t asm330lhh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhh_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t asm330lhh_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhh_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhh_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhh_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhh_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhh_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhh_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhh_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhh_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhh_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -1079,9 +1079,9 @@ typedef enum ASM330LHH_XL_ST_POSITIVE = 1, ASM330LHH_XL_ST_NEGATIVE = 2, } asm330lhh_st_xl_t; -int32_t asm330lhh_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_self_test_set(const stmdev_ctx_t *ctx, asm330lhh_st_xl_t val); -int32_t asm330lhh_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_self_test_get(const stmdev_ctx_t *ctx, asm330lhh_st_xl_t *val); typedef enum @@ -1090,20 +1090,20 @@ typedef enum ASM330LHH_GY_ST_POSITIVE = 1, ASM330LHH_GY_ST_NEGATIVE = 3, } asm330lhh_st_g_t; -int32_t asm330lhh_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_gy_self_test_set(const stmdev_ctx_t *ctx, asm330lhh_st_g_t val); -int32_t asm330lhh_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_gy_self_test_get(const stmdev_ctx_t *ctx, asm330lhh_st_g_t *val); -int32_t asm330lhh_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhh_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhh_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhh_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhh_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhh_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhh_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhh_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhh_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhh_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -1117,13 +1117,13 @@ typedef enum ASM330LHH_AGGRESSIVE = 6, ASM330LHH_XTREME = 7, } asm330lhh_ftype_t; -int32_t asm330lhh_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, asm330lhh_ftype_t val); -int32_t asm330lhh_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, asm330lhh_ftype_t *val); -int32_t asm330lhh_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhh_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhh_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhh_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -1151,14 +1151,14 @@ typedef enum ASM330LHH_LP_ODR_DIV_400 = 0x06, ASM330LHH_LP_ODR_DIV_800 = 0x07, } asm330lhh_hp_slope_xl_en_t; -int32_t asm330lhh_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, asm330lhh_hp_slope_xl_en_t val); -int32_t asm330lhh_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, asm330lhh_hp_slope_xl_en_t *val); -int32_t asm330lhh_xl_fast_settling_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhh_xl_fast_settling_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -1166,9 +1166,9 @@ typedef enum ASM330LHH_USE_SLOPE = 0, ASM330LHH_USE_HPF = 1, } asm330lhh_slope_fds_t; -int32_t asm330lhh_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, asm330lhh_slope_fds_t val); -int32_t asm330lhh_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, asm330lhh_slope_fds_t *val); typedef enum @@ -1179,9 +1179,9 @@ typedef enum ASM330LHH_HP_FILTER_260mHz = 0x82, ASM330LHH_HP_FILTER_1Hz04 = 0x83, } asm330lhh_hpm_g_t; -int32_t asm330lhh_gy_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, asm330lhh_hpm_g_t val); -int32_t asm330lhh_gy_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, asm330lhh_hpm_g_t *val); typedef enum @@ -1189,9 +1189,9 @@ typedef enum ASM330LHH_PULL_UP_DISC = 0, ASM330LHH_PULL_UP_CONNECT = 1, } asm330lhh_sdo_pu_en_t; -int32_t asm330lhh_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, asm330lhh_sdo_pu_en_t val); -int32_t asm330lhh_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, asm330lhh_sdo_pu_en_t *val); typedef enum @@ -1199,9 +1199,9 @@ typedef enum ASM330LHH_SPI_4_WIRE = 0, ASM330LHH_SPI_3_WIRE = 1, } asm330lhh_sim_t; -int32_t asm330lhh_spi_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_spi_mode_set(const stmdev_ctx_t *ctx, asm330lhh_sim_t val); -int32_t asm330lhh_spi_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_spi_mode_get(const stmdev_ctx_t *ctx, asm330lhh_sim_t *val); typedef enum @@ -1209,9 +1209,9 @@ typedef enum ASM330LHH_I2C_ENABLE = 0, ASM330LHH_I2C_DISABLE = 1, } asm330lhh_i2c_disable_t; -int32_t asm330lhh_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_i2c_interface_set(const stmdev_ctx_t *ctx, asm330lhh_i2c_disable_t val); -int32_t asm330lhh_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_i2c_interface_get(const stmdev_ctx_t *ctx, asm330lhh_i2c_disable_t *val); typedef struct @@ -1219,9 +1219,9 @@ typedef struct asm330lhh_int1_ctrl_t int1_ctrl; asm330lhh_md1_cfg_t md1_cfg; } asm330lhh_pin_int1_route_t; -int32_t asm330lhh_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_pin_int1_route_set(const stmdev_ctx_t *ctx, asm330lhh_pin_int1_route_t *val); -int32_t asm330lhh_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_pin_int1_route_get(const stmdev_ctx_t *ctx, asm330lhh_pin_int1_route_t *val); typedef struct @@ -1229,9 +1229,9 @@ typedef struct asm330lhh_int2_ctrl_t int2_ctrl; asm330lhh_md2_cfg_t md2_cfg; } asm330lhh_pin_int2_route_t; -int32_t asm330lhh_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_pin_int2_route_set(const stmdev_ctx_t *ctx, asm330lhh_pin_int2_route_t *val); -int32_t asm330lhh_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_pin_int2_route_get(const stmdev_ctx_t *ctx, asm330lhh_pin_int2_route_t *val); typedef enum @@ -1239,9 +1239,9 @@ typedef enum ASM330LHH_PUSH_PULL = 0, ASM330LHH_OPEN_DRAIN = 1, } asm330lhh_pp_od_t; -int32_t asm330lhh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_pin_mode_set(const stmdev_ctx_t *ctx, asm330lhh_pp_od_t val); -int32_t asm330lhh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_pin_mode_get(const stmdev_ctx_t *ctx, asm330lhh_pp_od_t *val); typedef enum @@ -1249,22 +1249,22 @@ typedef enum ASM330LHH_ACTIVE_HIGH = 0, ASM330LHH_ACTIVE_LOW = 1, } asm330lhh_h_lactive_t; -int32_t asm330lhh_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_pin_polarity_set(const stmdev_ctx_t *ctx, asm330lhh_h_lactive_t val); -int32_t asm330lhh_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_pin_polarity_get(const stmdev_ctx_t *ctx, asm330lhh_h_lactive_t *val); -int32_t asm330lhh_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhh_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhh_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhh_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { ASM330LHH_ALL_INT_PULSED = 0, ASM330LHH_ALL_INT_LATCHED = 3, } asm330lhh_lir_t; -int32_t asm330lhh_int_notification_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_int_notification_set(const stmdev_ctx_t *ctx, asm330lhh_lir_t val); -int32_t asm330lhh_int_notification_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_int_notification_get(const stmdev_ctx_t *ctx, asm330lhh_lir_t *val); typedef enum @@ -1272,33 +1272,33 @@ typedef enum ASM330LHH_LSb_FS_DIV_64 = 0, ASM330LHH_LSb_FS_DIV_256 = 1, } asm330lhh_wake_ths_w_t; -int32_t asm330lhh_wkup_ths_weight_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_wkup_ths_weight_set(const stmdev_ctx_t *ctx, asm330lhh_wake_ths_w_t val); -int32_t asm330lhh_wkup_ths_weight_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_wkup_ths_weight_get(const stmdev_ctx_t *ctx, asm330lhh_wake_ths_w_t *val); -int32_t asm330lhh_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhh_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhh_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhh_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhh_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhh_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhh_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhh_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhh_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhh_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhh_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhh_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhh_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhh_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { ASM330LHH_DRIVE_SLEEP_CHG_EVENT = 0, ASM330LHH_DRIVE_SLEEP_STATUS = 1, } asm330lhh_sleep_status_on_int_t; -int32_t asm330lhh_act_pin_notification_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_act_pin_notification_set(const stmdev_ctx_t *ctx, asm330lhh_sleep_status_on_int_t val); -int32_t asm330lhh_act_pin_notification_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_act_pin_notification_get(const stmdev_ctx_t *ctx, asm330lhh_sleep_status_on_int_t *val); typedef enum @@ -1308,13 +1308,13 @@ typedef enum ASM330LHH_XL_12Hz5_GY_SLEEP = 2, ASM330LHH_XL_12Hz5_GY_PD = 3, } asm330lhh_inact_en_t; -int32_t asm330lhh_act_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_act_mode_set(const stmdev_ctx_t *ctx, asm330lhh_inact_en_t val); -int32_t asm330lhh_act_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_act_mode_get(const stmdev_ctx_t *ctx, asm330lhh_inact_en_t *val); -int32_t asm330lhh_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhh_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhh_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhh_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -1323,13 +1323,13 @@ typedef enum ASM330LHH_DEG_60 = 2, ASM330LHH_DEG_50 = 3, } asm330lhh_sixd_ths_t; -int32_t asm330lhh_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_6d_threshold_set(const stmdev_ctx_t *ctx, asm330lhh_sixd_ths_t val); -int32_t asm330lhh_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_6d_threshold_get(const stmdev_ctx_t *ctx, asm330lhh_sixd_ths_t *val); -int32_t asm330lhh_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhh_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhh_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhh_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -1342,26 +1342,26 @@ typedef enum ASM330LHH_FF_TSH_469mg = 6, ASM330LHH_FF_TSH_500mg = 7, } asm330lhh_ff_ths_t; -int32_t asm330lhh_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_ff_threshold_set(const stmdev_ctx_t *ctx, asm330lhh_ff_ths_t val); -int32_t asm330lhh_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_ff_threshold_get(const stmdev_ctx_t *ctx, asm330lhh_ff_ths_t *val); -int32_t asm330lhh_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhh_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhh_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhh_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhh_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t asm330lhh_fifo_watermark_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhh_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t asm330lhh_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhh_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhh_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhh_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -1379,9 +1379,9 @@ typedef enum ASM330LHH_XL_BATCHED_AT_6667Hz = 10, ASM330LHH_XL_BATCHED_AT_6Hz5 = 11, } asm330lhh_bdr_xl_t; -int32_t asm330lhh_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_xl_batch_set(const stmdev_ctx_t *ctx, asm330lhh_bdr_xl_t val); -int32_t asm330lhh_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_xl_batch_get(const stmdev_ctx_t *ctx, asm330lhh_bdr_xl_t *val); typedef enum @@ -1399,9 +1399,9 @@ typedef enum ASM330LHH_GY_BATCHED_AT_6667Hz = 10, ASM330LHH_GY_BATCHED_AT_6Hz5 = 11, } asm330lhh_bdr_gy_t; -int32_t asm330lhh_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_gy_batch_set(const stmdev_ctx_t *ctx, asm330lhh_bdr_gy_t val); -int32_t asm330lhh_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_gy_batch_get(const stmdev_ctx_t *ctx, asm330lhh_bdr_gy_t *val); typedef enum @@ -1413,9 +1413,9 @@ typedef enum ASM330LHH_STREAM_MODE = 6, ASM330LHH_BYPASS_TO_FIFO_MODE = 7, } asm330lhh_fifo_mode_t; -int32_t asm330lhh_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_mode_set(const stmdev_ctx_t *ctx, asm330lhh_fifo_mode_t val); -int32_t asm330lhh_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_mode_get(const stmdev_ctx_t *ctx, asm330lhh_fifo_mode_t *val); typedef enum @@ -1425,9 +1425,9 @@ typedef enum ASM330LHH_TEMP_BATCHED_AT_12Hz5 = 2, ASM330LHH_TEMP_BATCHED_AT_1Hz6 = 3, } asm330lhh_odr_t_batch_t; -int32_t asm330lhh_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_temp_batch_set(const stmdev_ctx_t *ctx, asm330lhh_odr_t_batch_t val); -int32_t asm330lhh_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_temp_batch_get(const stmdev_ctx_t *ctx, asm330lhh_odr_t_batch_t *val); typedef enum @@ -1437,9 +1437,9 @@ typedef enum ASM330LHH_DEC_8 = 2, ASM330LHH_DEC_32 = 3, } asm330lhh_odr_ts_batch_t; -int32_t asm330lhh_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, asm330lhh_odr_ts_batch_t val); -int32_t asm330lhh_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, asm330lhh_odr_ts_batch_t *val); typedef enum @@ -1447,32 +1447,32 @@ typedef enum ASM330LHH_XL_BATCH_EVENT = 0, ASM330LHH_GYRO_BATCH_EVENT = 1, } asm330lhh_trig_counter_bdr_t; -int32_t asm330lhh_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, asm330lhh_trig_counter_bdr_t val); -int32_t asm330lhh_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, asm330lhh_trig_counter_bdr_t *val); -int32_t asm330lhh_rst_batch_counter_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhh_rst_batch_counter_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhh_batch_counter_threshold_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t asm330lhh_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t asm330lhh_fifo_data_level_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t asm330lhh_fifo_status_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_status_get(const stmdev_ctx_t *ctx, asm330lhh_fifo_status2_t *val); -int32_t asm330lhh_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhh_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhh_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhh_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhh_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -1482,7 +1482,7 @@ typedef enum ASM330LHH_TIMESTAMP_TAG, ASM330LHH_CFG_CHANGE_TAG, } asm330lhh_fifo_tag_t; -int32_t asm330lhh_fifo_sensor_tag_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, asm330lhh_fifo_tag_t *val); typedef enum @@ -1493,9 +1493,9 @@ typedef enum ASM330LHH_LEVEL_TRIGGER = 2, ASM330LHH_EDGE_TRIGGER = 4, } asm330lhh_den_mode_t; -int32_t asm330lhh_den_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_den_mode_set(const stmdev_ctx_t *ctx, asm330lhh_den_mode_t val); -int32_t asm330lhh_den_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_den_mode_get(const stmdev_ctx_t *ctx, asm330lhh_den_mode_t *val); typedef enum @@ -1503,9 +1503,9 @@ typedef enum ASM330LHH_DEN_ACT_LOW = 0, ASM330LHH_DEN_ACT_HIGH = 1, } asm330lhh_den_lh_t; -int32_t asm330lhh_den_polarity_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_den_polarity_set(const stmdev_ctx_t *ctx, asm330lhh_den_lh_t val); -int32_t asm330lhh_den_polarity_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_den_polarity_get(const stmdev_ctx_t *ctx, asm330lhh_den_lh_t *val); typedef enum @@ -1514,21 +1514,21 @@ typedef enum ASM330LHH_STAMP_IN_XL_DATA = 1, ASM330LHH_STAMP_IN_GY_XL_DATA = 2, } asm330lhh_den_xl_g_t; -int32_t asm330lhh_den_enable_set(stmdev_ctx_t *ctx, +int32_t asm330lhh_den_enable_set(const stmdev_ctx_t *ctx, asm330lhh_den_xl_g_t val); -int32_t asm330lhh_den_enable_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_den_enable_get(const stmdev_ctx_t *ctx, asm330lhh_den_xl_g_t *val); -int32_t asm330lhh_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhh_den_mark_axis_x_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhh_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhh_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhh_den_mark_axis_y_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhh_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhh_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhh_den_mark_axis_z_get(stmdev_ctx_t *ctx, +int32_t asm330lhh_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhh_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val); /** diff --git a/sensor/stmemsc/asm330lhhx_STdC/driver/asm330lhhx_reg.c b/sensor/stmemsc/asm330lhhx_STdC/driver/asm330lhhx_reg.c index d368a06c..b1dc89e2 100644 --- a/sensor/stmemsc/asm330lhhx_STdC/driver/asm330lhhx_reg.c +++ b/sensor/stmemsc/asm330lhhx_STdC/driver/asm330lhhx_reg.c @@ -46,11 +46,15 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak asm330lhhx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, +int32_t __weak asm330lhhx_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + + if (ctx == NULL) return -1; + ret = ctx->read_reg(ctx->handle, reg, data, len); + return ret; } @@ -64,11 +68,15 @@ int32_t __weak asm330lhhx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak asm330lhhx_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, +int32_t __weak asm330lhhx_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + + if (ctx == NULL) return -1; + ret = ctx->write_reg(ctx->handle, reg, data, len); + return ret; } @@ -165,7 +173,7 @@ float_t asm330lhhx_from_lsb_to_nsec(int32_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_xl_full_scale_set(const stmdev_ctx_t *ctx, asm330lhhx_fs_xl_t val) { asm330lhhx_ctrl1_xl_t ctrl1_xl; @@ -189,7 +197,7 @@ int32_t asm330lhhx_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_xl_full_scale_get(const stmdev_ctx_t *ctx, asm330lhhx_fs_xl_t *val) { asm330lhhx_ctrl1_xl_t ctrl1_xl; @@ -225,7 +233,7 @@ int32_t asm330lhhx_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_xl_data_rate_set(const stmdev_ctx_t *ctx, asm330lhhx_odr_xl_t val) { asm330lhhx_odr_xl_t odr_xl = val; @@ -467,7 +475,7 @@ int32_t asm330lhhx_xl_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_xl_data_rate_get(const stmdev_ctx_t *ctx, asm330lhhx_odr_xl_t *val) { asm330lhhx_ctrl1_xl_t ctrl1_xl; @@ -527,7 +535,7 @@ int32_t asm330lhhx_xl_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_gy_full_scale_set(const stmdev_ctx_t *ctx, asm330lhhx_fs_g_t val) { asm330lhhx_ctrl2_g_t ctrl2_g; @@ -550,7 +558,7 @@ int32_t asm330lhhx_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_gy_full_scale_get(const stmdev_ctx_t *ctx, asm330lhhx_fs_g_t *val) { asm330lhhx_ctrl2_g_t ctrl2_g; @@ -592,7 +600,7 @@ int32_t asm330lhhx_gy_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_gy_data_rate_set(const stmdev_ctx_t *ctx, asm330lhhx_odr_g_t val) { asm330lhhx_odr_g_t odr_gy = val; @@ -835,7 +843,7 @@ int32_t asm330lhhx_gy_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_gy_data_rate_get(const stmdev_ctx_t *ctx, asm330lhhx_odr_g_t *val) { asm330lhhx_ctrl2_g_t ctrl2_g; @@ -892,7 +900,7 @@ int32_t asm330lhhx_gy_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -914,7 +922,7 @@ int32_t asm330lhhx_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -934,7 +942,7 @@ int32_t asm330lhhx_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_xl_offset_weight_set(const stmdev_ctx_t *ctx, asm330lhhx_usr_off_w_t val) { asm330lhhx_ctrl6_c_t ctrl6_c; @@ -958,7 +966,7 @@ int32_t asm330lhhx_xl_offset_weight_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_xl_offset_weight_get(const stmdev_ctx_t *ctx, asm330lhhx_usr_off_w_t *val) { asm330lhhx_ctrl6_c_t ctrl6_c; @@ -989,7 +997,7 @@ int32_t asm330lhhx_xl_offset_weight_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_power_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_xl_power_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_xl_hm_mode_t val) { asm330lhhx_ctrl6_c_t ctrl6_c; @@ -1012,7 +1020,7 @@ int32_t asm330lhhx_xl_power_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_power_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_xl_power_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_xl_hm_mode_t *val) { asm330lhhx_ctrl6_c_t ctrl6_c; @@ -1042,7 +1050,7 @@ int32_t asm330lhhx_xl_power_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_gy_power_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_gy_power_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_g_hm_mode_t val) { asm330lhhx_ctrl7_g_t ctrl7_g; @@ -1065,7 +1073,7 @@ int32_t asm330lhhx_gy_power_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_gy_power_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_gy_power_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_g_hm_mode_t *val) { asm330lhhx_ctrl7_g_t ctrl7_g; @@ -1097,7 +1105,7 @@ int32_t asm330lhhx_gy_power_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_all_sources_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_all_sources_get(const stmdev_ctx_t *ctx, asm330lhhx_all_sources_t *val) { int32_t ret; @@ -1159,7 +1167,7 @@ int32_t asm330lhhx_all_sources_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_status_reg_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_status_reg_get(const stmdev_ctx_t *ctx, asm330lhhx_status_reg_t *val) { int32_t ret; @@ -1175,7 +1183,7 @@ int32_t asm330lhhx_status_reg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_status_reg_t status_reg; int32_t ret; @@ -1195,7 +1203,7 @@ int32_t asm330lhhx_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_status_reg_t status_reg; int32_t ret; @@ -1215,7 +1223,7 @@ int32_t asm330lhhx_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_status_reg_t status_reg; int32_t ret; @@ -1237,7 +1245,7 @@ int32_t asm330lhhx_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t asm330lhhx_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; ret = asm330lhhx_write_reg(ctx, ASM330LHHX_X_OFS_USR, buff, 1); @@ -1254,7 +1262,7 @@ int32_t asm330lhhx_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t asm330lhhx_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_X_OFS_USR, buff, 1); @@ -1271,7 +1279,7 @@ int32_t asm330lhhx_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t asm330lhhx_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; ret = asm330lhhx_write_reg(ctx, ASM330LHHX_Y_OFS_USR, buff, 1); @@ -1288,7 +1296,7 @@ int32_t asm330lhhx_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t asm330lhhx_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_Y_OFS_USR, buff, 1); @@ -1305,7 +1313,7 @@ int32_t asm330lhhx_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t asm330lhhx_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; ret = asm330lhhx_write_reg(ctx, ASM330LHHX_Z_OFS_USR, buff, 1); @@ -1322,7 +1330,7 @@ int32_t asm330lhhx_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t asm330lhhx_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_Z_OFS_USR, buff, 1); @@ -1337,7 +1345,7 @@ int32_t asm330lhhx_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_ctrl7_g_t ctrl7_g; int32_t ret; @@ -1359,7 +1367,7 @@ int32_t asm330lhhx_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_ctrl7_g_t ctrl7_g; int32_t ret; @@ -1390,7 +1398,7 @@ int32_t asm330lhhx_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_timestamp_rst(stmdev_ctx_t *ctx) +int32_t asm330lhhx_timestamp_rst(const stmdev_ctx_t *ctx) { uint8_t rst_val = 0xAA; @@ -1405,7 +1413,7 @@ int32_t asm330lhhx_timestamp_rst(stmdev_ctx_t *ctx) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_ctrl10_c_t ctrl10_c; int32_t ret; @@ -1428,7 +1436,7 @@ int32_t asm330lhhx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_ctrl10_c_t ctrl10_c; int32_t ret; @@ -1449,7 +1457,7 @@ int32_t asm330lhhx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t asm330lhhx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; @@ -1483,7 +1491,7 @@ int32_t asm330lhhx_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_rounding_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_rounding_t val) { asm330lhhx_ctrl5_c_t ctrl5_c; @@ -1506,7 +1514,7 @@ int32_t asm330lhhx_rounding_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_rounding_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_rounding_t *val) { asm330lhhx_ctrl5_c_t ctrl5_c; @@ -1544,7 +1552,7 @@ int32_t asm330lhhx_rounding_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t asm330lhhx_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1565,7 +1573,7 @@ int32_t asm330lhhx_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t asm330lhhx_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1590,7 +1598,7 @@ int32_t asm330lhhx_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t asm330lhhx_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1614,7 +1622,7 @@ int32_t asm330lhhx_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_DATA_OUT_X_L, val, 6); @@ -1643,7 +1651,7 @@ int32_t asm330lhhx_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_internal_freq_fine_t internal_freq_fine; int32_t ret; @@ -1669,7 +1677,7 @@ int32_t asm330lhhx_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_internal_freq_fine_t internal_freq_fine; int32_t ret; @@ -1690,7 +1698,7 @@ int32_t asm330lhhx_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_mem_bank_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_mem_bank_set(const stmdev_ctx_t *ctx, asm330lhhx_reg_access_t val) { asm330lhhx_func_cfg_access_t func_cfg_access; @@ -1716,7 +1724,7 @@ int32_t asm330lhhx_mem_bank_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_mem_bank_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_mem_bank_get(const stmdev_ctx_t *ctx, asm330lhhx_reg_access_t *val) { asm330lhhx_func_cfg_access_t func_cfg_access; @@ -1751,7 +1759,7 @@ int32_t asm330lhhx_mem_bank_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add, +int32_t asm330lhhx_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t add, uint8_t *val) { asm330lhhx_page_rw_t page_rw; @@ -1816,7 +1824,7 @@ int32_t asm330lhhx_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add, +int32_t asm330lhhx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t add, uint8_t *buf, uint8_t len) { asm330lhhx_page_rw_t page_rw; @@ -1914,7 +1922,7 @@ int32_t asm330lhhx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add, +int32_t asm330lhhx_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, uint8_t *val) { asm330lhhx_page_rw_t page_rw; @@ -1978,7 +1986,7 @@ int32_t asm330lhhx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_data_ready_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_dataready_pulsed_t val) { asm330lhhx_counter_bdr_reg1_t counter_bdr_reg1; @@ -2004,7 +2012,7 @@ int32_t asm330lhhx_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_data_ready_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_dataready_pulsed_t *val) { asm330lhhx_counter_bdr_reg1_t counter_bdr_reg1; @@ -2035,7 +2043,7 @@ int32_t asm330lhhx_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t asm330lhhx_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; ret = asm330lhhx_read_reg(ctx, ASM330LHHX_WHO_AM_I, buff, 1); @@ -2050,7 +2058,7 @@ int32_t asm330lhhx_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2072,7 +2080,7 @@ int32_t asm330lhhx_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2092,7 +2100,7 @@ int32_t asm330lhhx_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2115,7 +2123,7 @@ int32_t asm330lhhx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2134,7 +2142,7 @@ int32_t asm330lhhx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2156,7 +2164,7 @@ int32_t asm330lhhx_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2177,7 +2185,7 @@ int32_t asm330lhhx_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_xl_self_test_set(const stmdev_ctx_t *ctx, asm330lhhx_st_xl_t val) { asm330lhhx_ctrl5_c_t ctrl5_c; @@ -2200,7 +2208,7 @@ int32_t asm330lhhx_xl_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_xl_self_test_get(const stmdev_ctx_t *ctx, asm330lhhx_st_xl_t *val) { asm330lhhx_ctrl5_c_t ctrl5_c; @@ -2234,7 +2242,7 @@ int32_t asm330lhhx_xl_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_gy_self_test_set(const stmdev_ctx_t *ctx, asm330lhhx_st_g_t val) { asm330lhhx_ctrl5_c_t ctrl5_c; @@ -2257,7 +2265,7 @@ int32_t asm330lhhx_gy_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_gy_self_test_get(const stmdev_ctx_t *ctx, asm330lhhx_st_g_t *val) { asm330lhhx_ctrl5_c_t ctrl5_c; @@ -2304,7 +2312,7 @@ int32_t asm330lhhx_gy_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_ctrl1_xl_t ctrl1_xl; int32_t ret; @@ -2327,7 +2335,7 @@ int32_t asm330lhhx_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_ctrl1_xl_t ctrl1_xl; int32_t ret; @@ -2347,7 +2355,7 @@ int32_t asm330lhhx_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_ctrl4_c_t ctrl4_c; int32_t ret; @@ -2370,7 +2378,7 @@ int32_t asm330lhhx_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_ctrl4_c_t ctrl4_c; int32_t ret; @@ -2390,7 +2398,7 @@ int32_t asm330lhhx_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_ctrl4_c_t ctrl4_c; int32_t ret; @@ -2413,7 +2421,7 @@ int32_t asm330lhhx_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_ctrl4_c_t ctrl4_c; @@ -2433,7 +2441,7 @@ int32_t asm330lhhx_filter_settling_mask_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, asm330lhhx_ftype_t val) { asm330lhhx_ctrl6_c_t ctrl6_c; @@ -2456,7 +2464,7 @@ int32_t asm330lhhx_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, asm330lhhx_ftype_t *val) { asm330lhhx_ctrl6_c_t ctrl6_c; @@ -2505,7 +2513,7 @@ int32_t asm330lhhx_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -2528,7 +2536,7 @@ int32_t asm330lhhx_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -2548,7 +2556,7 @@ int32_t asm330lhhx_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, asm330lhhx_hp_slope_xl_en_t val) { asm330lhhx_ctrl8_xl_t ctrl8_xl; @@ -2575,7 +2583,7 @@ int32_t asm330lhhx_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, asm330lhhx_hp_slope_xl_en_t *val) { asm330lhhx_ctrl8_xl_t ctrl8_xl; @@ -2671,7 +2679,7 @@ int32_t asm330lhhx_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -2696,7 +2704,7 @@ int32_t asm330lhhx_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -2716,7 +2724,7 @@ int32_t asm330lhhx_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, asm330lhhx_slope_fds_t val) { asm330lhhx_int_cfg0_t int_cfg0; @@ -2741,7 +2749,7 @@ int32_t asm330lhhx_xl_hp_path_internal_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, asm330lhhx_slope_fds_t *val) { asm330lhhx_int_cfg0_t int_cfg0; @@ -2772,7 +2780,7 @@ int32_t asm330lhhx_xl_hp_path_internal_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_gy_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, asm330lhhx_hpm_g_t val) { asm330lhhx_ctrl7_g_t ctrl7_g; @@ -2797,7 +2805,7 @@ int32_t asm330lhhx_gy_hp_path_internal_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_gy_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, asm330lhhx_hpm_g_t *val) { asm330lhhx_ctrl7_g_t ctrl7_g; @@ -2850,7 +2858,7 @@ int32_t asm330lhhx_gy_hp_path_internal_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_sdo_pu_en_t val) { asm330lhhx_pin_ctrl_t pin_ctrl; @@ -2873,7 +2881,7 @@ int32_t asm330lhhx_sdo_sa0_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_sdo_pu_en_t *val) { asm330lhhx_pin_ctrl_t pin_ctrl; @@ -2904,7 +2912,7 @@ int32_t asm330lhhx_sdo_sa0_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_int1_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_int1_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_pd_dis_int1_t val) { asm330lhhx_i3c_bus_avb_t i3c_bus_avb; @@ -2928,7 +2936,7 @@ int32_t asm330lhhx_int1_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_int1_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_int1_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_pd_dis_int1_t *val) { asm330lhhx_i3c_bus_avb_t i3c_bus_avb; @@ -2959,7 +2967,7 @@ int32_t asm330lhhx_int1_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_spi_mode_set(stmdev_ctx_t *ctx, asm330lhhx_sim_t val) +int32_t asm330lhhx_spi_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_sim_t val) { asm330lhhx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2981,7 +2989,7 @@ int32_t asm330lhhx_spi_mode_set(stmdev_ctx_t *ctx, asm330lhhx_sim_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_spi_mode_get(stmdev_ctx_t *ctx, asm330lhhx_sim_t *val) +int32_t asm330lhhx_spi_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_sim_t *val) { asm330lhhx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -3011,7 +3019,7 @@ int32_t asm330lhhx_spi_mode_get(stmdev_ctx_t *ctx, asm330lhhx_sim_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_i2c_interface_set(const stmdev_ctx_t *ctx, asm330lhhx_i2c_disable_t val) { asm330lhhx_ctrl4_c_t ctrl4_c; @@ -3034,7 +3042,7 @@ int32_t asm330lhhx_i2c_interface_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_i2c_interface_get(const stmdev_ctx_t *ctx, asm330lhhx_i2c_disable_t *val) { asm330lhhx_ctrl4_c_t ctrl4_c; @@ -3065,7 +3073,7 @@ int32_t asm330lhhx_i2c_interface_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_i3c_disable_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_i3c_disable_set(const stmdev_ctx_t *ctx, asm330lhhx_i3c_disable_t val) { asm330lhhx_ctrl9_xl_t ctrl9_xl; @@ -3101,7 +3109,7 @@ int32_t asm330lhhx_i3c_disable_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_i3c_disable_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_i3c_disable_get(const stmdev_ctx_t *ctx, asm330lhhx_i3c_disable_t *val) { asm330lhhx_ctrl9_xl_t ctrl9_xl; @@ -3160,7 +3168,7 @@ int32_t asm330lhhx_i3c_disable_get(stmdev_ctx_t *ctx, * FSM_INT1_B * */ -int32_t asm330lhhx_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_pin_int1_route_set(const stmdev_ctx_t *ctx, asm330lhhx_pin_int1_route_t *val) { asm330lhhx_pin_int2_route_t pin_int2_route; @@ -3289,7 +3297,7 @@ int32_t asm330lhhx_pin_int1_route_set(stmdev_ctx_t *ctx, * EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B * */ -int32_t asm330lhhx_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_pin_int1_route_get(const stmdev_ctx_t *ctx, asm330lhhx_pin_int1_route_t *val) { int32_t ret; @@ -3341,7 +3349,7 @@ int32_t asm330lhhx_pin_int1_route_get(stmdev_ctx_t *ctx, * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B * */ -int32_t asm330lhhx_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_pin_int2_route_set(const stmdev_ctx_t *ctx, asm330lhhx_pin_int2_route_t *val) { asm330lhhx_pin_int1_route_t pin_int1_route; @@ -3470,7 +3478,7 @@ int32_t asm330lhhx_pin_int2_route_set(stmdev_ctx_t *ctx, * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B * */ -int32_t asm330lhhx_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_pin_int2_route_get(const stmdev_ctx_t *ctx, asm330lhhx_pin_int2_route_t *val) { int32_t ret; @@ -3521,7 +3529,7 @@ int32_t asm330lhhx_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_pin_mode_set(stmdev_ctx_t *ctx, asm330lhhx_pp_od_t val) +int32_t asm330lhhx_pin_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_pp_od_t val) { asm330lhhx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -3543,7 +3551,7 @@ int32_t asm330lhhx_pin_mode_set(stmdev_ctx_t *ctx, asm330lhhx_pp_od_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_pin_mode_get(stmdev_ctx_t *ctx, asm330lhhx_pp_od_t *val) +int32_t asm330lhhx_pin_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_pp_od_t *val) { asm330lhhx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -3573,7 +3581,7 @@ int32_t asm330lhhx_pin_mode_get(stmdev_ctx_t *ctx, asm330lhhx_pp_od_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_pin_polarity_set(const stmdev_ctx_t *ctx, asm330lhhx_h_lactive_t val) { asm330lhhx_ctrl3_c_t ctrl3_c; @@ -3596,7 +3604,7 @@ int32_t asm330lhhx_pin_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_pin_polarity_get(const stmdev_ctx_t *ctx, asm330lhhx_h_lactive_t *val) { asm330lhhx_ctrl3_c_t ctrl3_c; @@ -3627,7 +3635,7 @@ int32_t asm330lhhx_pin_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_ctrl4_c_t ctrl4_c; int32_t ret; @@ -3649,7 +3657,7 @@ int32_t asm330lhhx_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_ctrl4_c_t ctrl4_c; int32_t ret; @@ -3668,7 +3676,7 @@ int32_t asm330lhhx_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_int_notification_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_int_notification_set(const stmdev_ctx_t *ctx, asm330lhhx_lir_t val) { asm330lhhx_int_cfg0_t int_cfg0; @@ -3711,7 +3719,7 @@ int32_t asm330lhhx_int_notification_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_int_notification_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_int_notification_get(const stmdev_ctx_t *ctx, asm330lhhx_lir_t *val) { asm330lhhx_int_cfg0_t int_cfg0; @@ -3777,7 +3785,7 @@ int32_t asm330lhhx_int_notification_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_wkup_ths_weight_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_wkup_ths_weight_set(const stmdev_ctx_t *ctx, asm330lhhx_wake_ths_w_t val) { asm330lhhx_wake_up_dur_t wake_up_dur; @@ -3804,7 +3812,7 @@ int32_t asm330lhhx_wkup_ths_weight_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_wkup_ths_weight_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_wkup_ths_weight_get(const stmdev_ctx_t *ctx, asm330lhhx_wake_ths_w_t *val) { asm330lhhx_wake_up_dur_t wake_up_dur; @@ -3837,7 +3845,7 @@ int32_t asm330lhhx_wkup_ths_weight_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_wake_up_ths_t wake_up_ths; int32_t ret; @@ -3862,7 +3870,7 @@ int32_t asm330lhhx_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_wake_up_ths_t wake_up_ths; int32_t ret; @@ -3882,7 +3890,7 @@ int32_t asm330lhhx_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_wake_up_ths_t wake_up_ths; int32_t ret; @@ -3906,7 +3914,7 @@ int32_t asm330lhhx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_wake_up_ths_t wake_up_ths; @@ -3927,7 +3935,7 @@ int32_t asm330lhhx_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_wake_up_dur_t wake_up_dur; int32_t ret; @@ -3951,7 +3959,7 @@ int32_t asm330lhhx_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_wake_up_dur_t wake_up_dur; int32_t ret; @@ -3984,7 +3992,7 @@ int32_t asm330lhhx_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_ctrl4_c_t ctrl4_c; int32_t ret; @@ -4006,7 +4014,7 @@ int32_t asm330lhhx_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_ctrl4_c_t ctrl4_c; int32_t ret; @@ -4027,7 +4035,7 @@ int32_t asm330lhhx_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_act_pin_notification_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_act_pin_notification_set(const stmdev_ctx_t *ctx, asm330lhhx_sleep_status_on_int_t val) { asm330lhhx_int_cfg0_t int_cfg0; @@ -4053,7 +4061,7 @@ int32_t asm330lhhx_act_pin_notification_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_act_pin_notification_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_act_pin_notification_get(const stmdev_ctx_t *ctx, asm330lhhx_sleep_status_on_int_t *val) { asm330lhhx_int_cfg0_t int_cfg0; @@ -4083,7 +4091,7 @@ int32_t asm330lhhx_act_pin_notification_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_act_mode_set(stmdev_ctx_t *ctx, asm330lhhx_inact_en_t val) +int32_t asm330lhhx_act_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_inact_en_t val) { asm330lhhx_int_cfg1_t int_cfg1; int32_t ret; @@ -4105,7 +4113,7 @@ int32_t asm330lhhx_act_mode_set(stmdev_ctx_t *ctx, asm330lhhx_inact_en_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_act_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_act_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_inact_en_t *val) { asm330lhhx_int_cfg1_t int_cfg1; @@ -4142,7 +4150,7 @@ int32_t asm330lhhx_act_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_wake_up_dur_t wake_up_dur; int32_t ret; @@ -4166,7 +4174,7 @@ int32_t asm330lhhx_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_wake_up_dur_t wake_up_dur; int32_t ret; @@ -4199,7 +4207,7 @@ int32_t asm330lhhx_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_6d_threshold_set(const stmdev_ctx_t *ctx, asm330lhhx_sixd_ths_t val) { asm330lhhx_ths_6d_t ths_6d; @@ -4224,7 +4232,7 @@ int32_t asm330lhhx_6d_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_6d_threshold_get(const stmdev_ctx_t *ctx, asm330lhhx_sixd_ths_t *val) { asm330lhhx_ths_6d_t ths_6d; @@ -4262,7 +4270,7 @@ int32_t asm330lhhx_6d_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_ths_6d_t ths_6d; int32_t ret; @@ -4286,7 +4294,7 @@ int32_t asm330lhhx_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_ths_6d_t ths_6d; int32_t ret; @@ -4319,7 +4327,7 @@ int32_t asm330lhhx_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_ff_threshold_set(const stmdev_ctx_t *ctx, asm330lhhx_ff_ths_t val) { asm330lhhx_free_fall_t free_fall; @@ -4343,7 +4351,7 @@ int32_t asm330lhhx_ff_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_ff_threshold_get(const stmdev_ctx_t *ctx, asm330lhhx_ff_ths_t *val) { asm330lhhx_free_fall_t free_fall; @@ -4392,7 +4400,7 @@ int32_t asm330lhhx_ff_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_wake_up_dur_t wake_up_dur; asm330lhhx_free_fall_t free_fall; @@ -4428,7 +4436,7 @@ int32_t asm330lhhx_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_wake_up_dur_t wake_up_dur; asm330lhhx_free_fall_t free_fall; @@ -4468,7 +4476,7 @@ int32_t asm330lhhx_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t asm330lhhx_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val) { asm330lhhx_fifo_ctrl1_t fifo_ctrl1; asm330lhhx_fifo_ctrl2_t fifo_ctrl2; @@ -4500,7 +4508,7 @@ int32_t asm330lhhx_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t asm330lhhx_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) { asm330lhhx_fifo_ctrl1_t fifo_ctrl1; asm330lhhx_fifo_ctrl2_t fifo_ctrl2; @@ -4526,7 +4534,7 @@ int32_t asm330lhhx_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_fifo_ctrl2_t fifo_ctrl2; @@ -4552,7 +4560,7 @@ int32_t asm330lhhx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_fifo_ctrl2_t fifo_ctrl2; @@ -4574,7 +4582,7 @@ int32_t asm330lhhx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -4599,7 +4607,7 @@ int32_t asm330lhhx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -4620,7 +4628,7 @@ int32_t asm330lhhx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_xl_batch_set(const stmdev_ctx_t *ctx, asm330lhhx_bdr_xl_t val) { asm330lhhx_fifo_ctrl3_t fifo_ctrl3; @@ -4646,7 +4654,7 @@ int32_t asm330lhhx_fifo_xl_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_xl_batch_get(const stmdev_ctx_t *ctx, asm330lhhx_bdr_xl_t *val) { asm330lhhx_fifo_ctrl3_t fifo_ctrl3; @@ -4709,7 +4717,7 @@ int32_t asm330lhhx_fifo_xl_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_gy_batch_set(const stmdev_ctx_t *ctx, asm330lhhx_bdr_gy_t val) { asm330lhhx_fifo_ctrl3_t fifo_ctrl3; @@ -4735,7 +4743,7 @@ int32_t asm330lhhx_fifo_gy_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_gy_batch_get(const stmdev_ctx_t *ctx, asm330lhhx_bdr_gy_t *val) { asm330lhhx_fifo_ctrl3_t fifo_ctrl3; @@ -4797,7 +4805,7 @@ int32_t asm330lhhx_fifo_gy_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_fifo_mode_t val) { asm330lhhx_fifo_ctrl4_t fifo_ctrl4; @@ -4822,7 +4830,7 @@ int32_t asm330lhhx_fifo_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_fifo_mode_t *val) { asm330lhhx_fifo_ctrl4_t fifo_ctrl4; @@ -4867,7 +4875,7 @@ int32_t asm330lhhx_fifo_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_temp_batch_set(const stmdev_ctx_t *ctx, asm330lhhx_odr_t_batch_t val) { asm330lhhx_fifo_ctrl4_t fifo_ctrl4; @@ -4893,7 +4901,7 @@ int32_t asm330lhhx_fifo_temp_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_temp_batch_get(const stmdev_ctx_t *ctx, asm330lhhx_odr_t_batch_t *val) { asm330lhhx_fifo_ctrl4_t fifo_ctrl4; @@ -4933,7 +4941,7 @@ int32_t asm330lhhx_fifo_temp_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, asm330lhhx_dec_ts_batch_t val) { asm330lhhx_fifo_ctrl4_t fifo_ctrl4; @@ -4961,7 +4969,7 @@ int32_t asm330lhhx_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, asm330lhhx_dec_ts_batch_t *val) { asm330lhhx_fifo_ctrl4_t fifo_ctrl4; @@ -5001,7 +5009,7 @@ int32_t asm330lhhx_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, asm330lhhx_trig_counter_bdr_t val) { asm330lhhx_counter_bdr_reg1_t counter_bdr_reg1; @@ -5028,7 +5036,7 @@ int32_t asm330lhhx_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, asm330lhhx_trig_counter_bdr_t *val) { asm330lhhx_counter_bdr_reg1_t counter_bdr_reg1; @@ -5061,7 +5069,7 @@ int32_t asm330lhhx_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_counter_bdr_reg1_t counter_bdr_reg1; int32_t ret; @@ -5086,7 +5094,7 @@ int32_t asm330lhhx_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_counter_bdr_reg1_t counter_bdr_reg1; int32_t ret; @@ -5107,7 +5115,7 @@ int32_t asm330lhhx_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_batch_counter_threshold_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t asm330lhhx_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { asm330lhhx_counter_bdr_reg2_t counter_bdr_reg1; asm330lhhx_counter_bdr_reg2_t counter_bdr_reg2; @@ -5139,7 +5147,7 @@ int32_t asm330lhhx_batch_counter_threshold_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { asm330lhhx_counter_bdr_reg1_t counter_bdr_reg1; @@ -5167,7 +5175,7 @@ int32_t asm330lhhx_batch_counter_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t asm330lhhx_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) { asm330lhhx_fifo_status1_t fifo_status1; asm330lhhx_fifo_status2_t fifo_status2; @@ -5194,7 +5202,7 @@ int32_t asm330lhhx_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fifo_status_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_status_get(const stmdev_ctx_t *ctx, asm330lhhx_fifo_status2_t *val) { int32_t ret; @@ -5210,7 +5218,7 @@ int32_t asm330lhhx_fifo_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_fifo_status2_t fifo_status2; int32_t ret; @@ -5231,7 +5239,7 @@ int32_t asm330lhhx_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_fifo_status2_t fifo_status2; int32_t ret; @@ -5251,7 +5259,7 @@ int32_t asm330lhhx_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_fifo_status2_t fifo_status2; int32_t ret; @@ -5271,7 +5279,7 @@ int32_t asm330lhhx_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fifo_sensor_tag_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, asm330lhhx_fifo_tag_t *val) { asm330lhhx_fifo_data_out_tag_t fifo_data_out_tag; @@ -5327,7 +5335,7 @@ int32_t asm330lhhx_fifo_sensor_tag_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_slv0_config_t slv0_config; int32_t ret; @@ -5361,7 +5369,7 @@ int32_t asm330lhhx_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_slv0_config_t slv0_config; int32_t ret; @@ -5390,7 +5398,7 @@ int32_t asm330lhhx_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_slv1_config_t slv1_config; int32_t ret; @@ -5423,7 +5431,7 @@ int32_t asm330lhhx_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_slv1_config_t slv1_config; int32_t ret; @@ -5452,7 +5460,7 @@ int32_t asm330lhhx_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_slv2_config_t slv2_config; int32_t ret; @@ -5486,7 +5494,7 @@ int32_t asm330lhhx_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_slv2_config_t slv2_config; int32_t ret; @@ -5514,7 +5522,7 @@ int32_t asm330lhhx_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_slv3_config_t slv3_config; int32_t ret; @@ -5547,7 +5555,7 @@ int32_t asm330lhhx_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_slv3_config_t slv3_config; int32_t ret; @@ -5588,7 +5596,7 @@ int32_t asm330lhhx_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_den_mode_set(stmdev_ctx_t *ctx, asm330lhhx_den_mode_t val) +int32_t asm330lhhx_den_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_den_mode_t val) { asm330lhhx_ctrl6_c_t ctrl6_c; int32_t ret; @@ -5610,7 +5618,7 @@ int32_t asm330lhhx_den_mode_set(stmdev_ctx_t *ctx, asm330lhhx_den_mode_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_den_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_den_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_den_mode_t *val) { asm330lhhx_ctrl6_c_t ctrl6_c; @@ -5650,7 +5658,7 @@ int32_t asm330lhhx_den_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_den_polarity_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_den_polarity_set(const stmdev_ctx_t *ctx, asm330lhhx_den_lh_t val) { asm330lhhx_ctrl9_xl_t ctrl9_xl; @@ -5674,7 +5682,7 @@ int32_t asm330lhhx_den_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_den_polarity_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_den_polarity_get(const stmdev_ctx_t *ctx, asm330lhhx_den_lh_t *val) { asm330lhhx_ctrl9_xl_t ctrl9_xl; @@ -5705,7 +5713,7 @@ int32_t asm330lhhx_den_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_den_enable_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_den_enable_set(const stmdev_ctx_t *ctx, asm330lhhx_den_xl_g_t val) { asm330lhhx_ctrl9_xl_t ctrl9_xl; @@ -5729,7 +5737,7 @@ int32_t asm330lhhx_den_enable_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_den_enable_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_den_enable_get(const stmdev_ctx_t *ctx, asm330lhhx_den_xl_g_t *val) { asm330lhhx_ctrl9_xl_t ctrl9_xl; @@ -5763,7 +5771,7 @@ int32_t asm330lhhx_den_enable_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -5786,7 +5794,7 @@ int32_t asm330lhhx_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -5805,7 +5813,7 @@ int32_t asm330lhhx_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -5828,7 +5836,7 @@ int32_t asm330lhhx_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -5847,7 +5855,7 @@ int32_t asm330lhhx_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -5869,7 +5877,7 @@ int32_t asm330lhhx_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -5901,7 +5909,7 @@ int32_t asm330lhhx_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t asm330lhhx_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -5924,7 +5932,7 @@ int32_t asm330lhhx_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t asm330lhhx_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -5947,7 +5955,7 @@ int32_t asm330lhhx_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val) +int32_t asm330lhhx_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -5998,7 +6006,7 @@ int32_t asm330lhhx_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t asm330lhhx_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -6055,7 +6063,7 @@ int32_t asm330lhhx_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_mag_soft_iron_set(stmdev_ctx_t *ctx, uint16_t *val) +int32_t asm330lhhx_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[12]; int32_t ret; @@ -6147,7 +6155,7 @@ int32_t asm330lhhx_mag_soft_iron_set(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t asm330lhhx_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[12]; int32_t ret; @@ -6236,7 +6244,7 @@ int32_t asm330lhhx_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_mag_z_orient_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_mag_z_orient_set(const stmdev_ctx_t *ctx, asm330lhhx_mag_z_axis_t val) { asm330lhhx_mag_cfg_a_t mag_cfg_a; @@ -6263,7 +6271,7 @@ int32_t asm330lhhx_mag_z_orient_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_mag_z_orient_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_mag_z_orient_get(const stmdev_ctx_t *ctx, asm330lhhx_mag_z_axis_t *val) { asm330lhhx_mag_cfg_a_t mag_cfg_a; @@ -6308,7 +6316,7 @@ int32_t asm330lhhx_mag_z_orient_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_mag_y_orient_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_mag_y_orient_set(const stmdev_ctx_t *ctx, asm330lhhx_mag_y_axis_t val) { asm330lhhx_mag_cfg_a_t mag_cfg_a; @@ -6334,7 +6342,7 @@ int32_t asm330lhhx_mag_y_orient_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_mag_y_orient_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_mag_y_orient_get(const stmdev_ctx_t *ctx, asm330lhhx_mag_y_axis_t *val) { asm330lhhx_mag_cfg_a_t mag_cfg_a; @@ -6379,7 +6387,7 @@ int32_t asm330lhhx_mag_y_orient_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_mag_x_orient_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_mag_x_orient_set(const stmdev_ctx_t *ctx, asm330lhhx_mag_x_axis_t val) { asm330lhhx_mag_cfg_b_t mag_cfg_b; @@ -6405,7 +6413,7 @@ int32_t asm330lhhx_mag_x_orient_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_mag_x_orient_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_mag_x_orient_get(const stmdev_ctx_t *ctx, asm330lhhx_mag_x_axis_t *val) { asm330lhhx_mag_cfg_b_t mag_cfg_b; @@ -6462,7 +6470,7 @@ int32_t asm330lhhx_mag_x_orient_get(stmdev_ctx_t *ctx, * ASM330LHHX_FSM_STATUS_B_MAINPAGE * */ -int32_t asm330lhhx_fsm_status_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fsm_status_get(const stmdev_ctx_t *ctx, asm330lhhx_fsm_status_t *val) { asm330lhhx_fsm_status_a_mainpage_t status_a; @@ -6500,7 +6508,7 @@ int32_t asm330lhhx_fsm_status_get(stmdev_ctx_t *ctx, * @param uint8_t * : buffer that stores data read * */ -int32_t asm330lhhx_fsm_out_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t asm330lhhx_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK); @@ -6524,7 +6532,7 @@ int32_t asm330lhhx_fsm_out_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_emb_func_status_t emb_func_status; @@ -6544,7 +6552,7 @@ int32_t asm330lhhx_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, return ret; } -int32_t asm330lhhx_emb_func_clk_dis_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_emb_func_clk_dis_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_page_sel_t page_sel; int32_t ret; @@ -6563,7 +6571,7 @@ int32_t asm330lhhx_emb_func_clk_dis_set(stmdev_ctx_t *ctx, uint8_t val) return ret; } -int32_t asm330lhhx_emb_func_clk_dis_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_emb_func_clk_dis_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_page_sel_t page_sel; int32_t ret; @@ -6590,7 +6598,7 @@ int32_t asm330lhhx_emb_func_clk_dis_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; asm330lhhx_emb_func_en_b_t emb_func_en_b; @@ -6623,7 +6631,7 @@ int32_t asm330lhhx_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; asm330lhhx_emb_func_en_b_t emb_func_en_b; @@ -6655,7 +6663,7 @@ int32_t asm330lhhx_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fsm_enable_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fsm_enable_set(const stmdev_ctx_t *ctx, asm330lhhx_emb_fsm_enable_t *val) { asm330lhhx_emb_func_en_b_t emb_func_en_b; @@ -6723,7 +6731,7 @@ int32_t asm330lhhx_fsm_enable_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fsm_enable_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fsm_enable_get(const stmdev_ctx_t *ctx, asm330lhhx_emb_fsm_enable_t *val) { int32_t ret; @@ -6755,7 +6763,7 @@ int32_t asm330lhhx_fsm_enable_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t asm330lhhx_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -6784,7 +6792,7 @@ int32_t asm330lhhx_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t asm330lhhx_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -6812,7 +6820,7 @@ int32_t asm330lhhx_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_long_clr_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_long_clr_set(const stmdev_ctx_t *ctx, asm330lhhx_fsm_lc_clr_t val) { asm330lhhx_fsm_long_counter_clear_t fsm_long_counter_clear; @@ -6845,7 +6853,7 @@ int32_t asm330lhhx_long_clr_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_long_clr_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_long_clr_get(const stmdev_ctx_t *ctx, asm330lhhx_fsm_lc_clr_t *val) { asm330lhhx_fsm_long_counter_clear_t fsm_long_counter_clear; @@ -6888,7 +6896,7 @@ int32_t asm330lhhx_long_clr_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fsm_data_rate_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fsm_data_rate_set(const stmdev_ctx_t *ctx, asm330lhhx_fsm_odr_t val) { asm330lhhx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; @@ -6924,7 +6932,7 @@ int32_t asm330lhhx_fsm_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fsm_data_rate_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fsm_data_rate_get(const stmdev_ctx_t *ctx, asm330lhhx_fsm_odr_t *val) { asm330lhhx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; @@ -6970,7 +6978,7 @@ int32_t asm330lhhx_fsm_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_emb_func_init_b_t emb_func_init_b; int32_t ret; @@ -7003,7 +7011,7 @@ int32_t asm330lhhx_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_emb_func_init_b_t emb_func_init_b; int32_t ret; @@ -7033,7 +7041,7 @@ int32_t asm330lhhx_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t asm330lhhx_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -7061,7 +7069,7 @@ int32_t asm330lhhx_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t asm330lhhx_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -7086,7 +7094,7 @@ int32_t asm330lhhx_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t asm330lhhx_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -7108,7 +7116,7 @@ int32_t asm330lhhx_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t asm330lhhx_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -7126,7 +7134,7 @@ int32_t asm330lhhx_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t asm330lhhx_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -7151,7 +7159,7 @@ int32_t asm330lhhx_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t asm330lhhx_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -7188,7 +7196,7 @@ int32_t asm330lhhx_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val) * in EMB_FUNC_INIT_B * */ -int32_t asm330lhhx_mlc_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_mlc_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_emb_func_en_b_t reg; int32_t ret; @@ -7229,7 +7237,7 @@ int32_t asm330lhhx_mlc_set(stmdev_ctx_t *ctx, uint8_t val) * reg EMB_FUNC_EN_B * */ -int32_t asm330lhhx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_emb_func_en_b_t reg; int32_t ret; @@ -7254,7 +7262,7 @@ int32_t asm330lhhx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val) * @param val register MLC_STATUS_MAINPAGE * */ -int32_t asm330lhhx_mlc_status_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_mlc_status_get(const stmdev_ctx_t *ctx, asm330lhhx_mlc_status_mainpage_t *val) { return asm330lhhx_read_reg(ctx, ASM330LHHX_MLC_STATUS_MAINPAGE, @@ -7269,7 +7277,7 @@ int32_t asm330lhhx_mlc_status_get(stmdev_ctx_t *ctx, * reg EMB_FUNC_ODR_CFG_C * */ -int32_t asm330lhhx_mlc_data_rate_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_mlc_data_rate_set(const stmdev_ctx_t *ctx, asm330lhhx_mlc_odr_t val) { asm330lhhx_emb_func_odr_cfg_c_t reg; @@ -7303,7 +7311,7 @@ int32_t asm330lhhx_mlc_data_rate_set(stmdev_ctx_t *ctx, * reg EMB_FUNC_ODR_CFG_C * */ -int32_t asm330lhhx_mlc_data_rate_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_mlc_data_rate_get(const stmdev_ctx_t *ctx, asm330lhhx_mlc_odr_t *val) { asm330lhhx_emb_func_odr_cfg_c_t reg; @@ -7348,7 +7356,7 @@ int32_t asm330lhhx_mlc_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_mlc_init_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_mlc_init_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_emb_func_init_b_t emb_func_init_b; int32_t ret; @@ -7380,7 +7388,7 @@ int32_t asm330lhhx_mlc_init_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_mlc_init_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_mlc_init_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_emb_func_init_b_t emb_func_init_b; int32_t ret; @@ -7408,7 +7416,7 @@ int32_t asm330lhhx_mlc_init_get(stmdev_ctx_t *ctx, uint8_t *val) * @param uint8_t * : buffer that stores data read * */ -int32_t asm330lhhx_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t asm330lhhx_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK); @@ -7431,7 +7439,7 @@ int32_t asm330lhhx_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff) * @param buff buffer that contains data to write * */ -int32_t asm330lhhx_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t asm330lhhx_mlc_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -7456,7 +7464,7 @@ int32_t asm330lhhx_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) * @param buff buffer that stores data read * */ -int32_t asm330lhhx_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t asm330lhhx_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -7494,7 +7502,7 @@ int32_t asm330lhhx_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_read_data_raw_get(const stmdev_ctx_t *ctx, asm330lhhx_emb_sh_read_t *val) { int32_t ret; @@ -7520,7 +7528,7 @@ int32_t asm330lhhx_sh_read_data_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_slave_connected_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_slave_connected_set(const stmdev_ctx_t *ctx, asm330lhhx_aux_sens_on_t val) { asm330lhhx_master_config_t master_config; @@ -7554,7 +7562,7 @@ int32_t asm330lhhx_sh_slave_connected_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_slave_connected_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_slave_connected_get(const stmdev_ctx_t *ctx, asm330lhhx_aux_sens_on_t *val) { asm330lhhx_master_config_t master_config; @@ -7600,7 +7608,7 @@ int32_t asm330lhhx_sh_slave_connected_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_master_config_t master_config; int32_t ret; @@ -7633,7 +7641,7 @@ int32_t asm330lhhx_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_master_config_t master_config; int32_t ret; @@ -7661,7 +7669,7 @@ int32_t asm330lhhx_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_pin_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_shub_pu_en_t val) { asm330lhhx_master_config_t master_config; @@ -7695,7 +7703,7 @@ int32_t asm330lhhx_sh_pin_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_pin_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_shub_pu_en_t *val) { asm330lhhx_master_config_t master_config; @@ -7734,7 +7742,7 @@ int32_t asm330lhhx_sh_pin_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t asm330lhhx_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) { asm330lhhx_master_config_t master_config; int32_t ret; @@ -7767,7 +7775,7 @@ int32_t asm330lhhx_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_master_config_t master_config; int32_t ret; @@ -7795,7 +7803,7 @@ int32_t asm330lhhx_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_syncro_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_start_config_t val) { asm330lhhx_master_config_t master_config; @@ -7829,7 +7837,7 @@ int32_t asm330lhhx_sh_syncro_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_syncro_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_start_config_t *val) { asm330lhhx_master_config_t master_config; @@ -7870,7 +7878,7 @@ int32_t asm330lhhx_sh_syncro_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_write_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_write_once_t val) { asm330lhhx_master_config_t master_config; @@ -7905,7 +7913,7 @@ int32_t asm330lhhx_sh_write_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_write_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_write_once_t *val) { asm330lhhx_master_config_t master_config; @@ -7944,7 +7952,7 @@ int32_t asm330lhhx_sh_write_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_reset_set(stmdev_ctx_t *ctx) +int32_t asm330lhhx_sh_reset_set(const stmdev_ctx_t *ctx) { asm330lhhx_master_config_t master_config; int32_t ret; @@ -7983,7 +7991,7 @@ int32_t asm330lhhx_sh_reset_set(stmdev_ctx_t *ctx) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t asm330lhhx_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { asm330lhhx_master_config_t master_config; int32_t ret; @@ -8011,7 +8019,7 @@ int32_t asm330lhhx_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_data_rate_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_data_rate_set(const stmdev_ctx_t *ctx, asm330lhhx_shub_odr_t val) { asm330lhhx_slv0_config_t slv0_config; @@ -8045,7 +8053,7 @@ int32_t asm330lhhx_sh_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_data_rate_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_data_rate_get(const stmdev_ctx_t *ctx, asm330lhhx_shub_odr_t *val) { asm330lhhx_slv0_config_t slv0_config; @@ -8094,7 +8102,7 @@ int32_t asm330lhhx_sh_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_cfg_write(const stmdev_ctx_t *ctx, asm330lhhx_sh_cfg_write_t *val) { asm330lhhx_slv0_add_t slv0_add; @@ -8137,7 +8145,7 @@ int32_t asm330lhhx_sh_cfg_write(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_slv0_cfg_read(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, asm330lhhx_sh_cfg_read_t *val) { asm330lhhx_slv0_config_t slv0_config; @@ -8187,7 +8195,7 @@ int32_t asm330lhhx_sh_slv0_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_slv1_cfg_read(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, asm330lhhx_sh_cfg_read_t *val) { asm330lhhx_slv1_config_t slv1_config; @@ -8235,7 +8243,7 @@ int32_t asm330lhhx_sh_slv1_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_slv2_cfg_read(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, asm330lhhx_sh_cfg_read_t *val) { asm330lhhx_slv2_config_t slv2_config; @@ -8285,7 +8293,7 @@ int32_t asm330lhhx_sh_slv2_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_slv3_cfg_read(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, asm330lhhx_sh_cfg_read_t *val) { asm330lhhx_slv3_config_t slv3_config; @@ -8332,7 +8340,7 @@ int32_t asm330lhhx_sh_slv3_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t asm330lhhx_sh_status_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_status_get(const stmdev_ctx_t *ctx, asm330lhhx_status_master_t *val) { int32_t ret; diff --git a/sensor/stmemsc/asm330lhhx_STdC/driver/asm330lhhx_reg.h b/sensor/stmemsc/asm330lhhx_STdC/driver/asm330lhhx_reg.h index 4473f84e..0c0c2273 100644 --- a/sensor/stmemsc/asm330lhhx_STdC/driver/asm330lhhx_reg.h +++ b/sensor/stmemsc/asm330lhhx_STdC/driver/asm330lhhx_reg.h @@ -28,6 +28,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include +#include #include /** @addtogroup ASM330LHHX @@ -2564,9 +2565,9 @@ typedef union * them with a custom implementation. */ -int32_t asm330lhhx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, +int32_t asm330lhhx_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t asm330lhhx_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, +int32_t asm330lhhx_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); float_t asm330lhhx_from_fs2g_to_mg(int16_t lsb); @@ -2589,8 +2590,8 @@ typedef enum ASM330LHHX_4g = 2, ASM330LHHX_8g = 3, } asm330lhhx_fs_xl_t; -int32_t asm330lhhx_xl_full_scale_set(stmdev_ctx_t *ctx, asm330lhhx_fs_xl_t val); -int32_t asm330lhhx_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_xl_full_scale_set(const stmdev_ctx_t *ctx, asm330lhhx_fs_xl_t val); +int32_t asm330lhhx_xl_full_scale_get(const stmdev_ctx_t *ctx, asm330lhhx_fs_xl_t *val); typedef enum @@ -2608,8 +2609,8 @@ typedef enum ASM330LHHX_XL_ODR_6667Hz = 10, ASM330LHHX_XL_ODR_1Hz6 = 11, /* (low power only) */ } asm330lhhx_odr_xl_t; -int32_t asm330lhhx_xl_data_rate_set(stmdev_ctx_t *ctx, asm330lhhx_odr_xl_t val); -int32_t asm330lhhx_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_xl_data_rate_set(const stmdev_ctx_t *ctx, asm330lhhx_odr_xl_t val); +int32_t asm330lhhx_xl_data_rate_get(const stmdev_ctx_t *ctx, asm330lhhx_odr_xl_t *val); typedef enum @@ -2621,8 +2622,8 @@ typedef enum ASM330LHHX_2000dps = 12, ASM330LHHX_4000dps = 1, } asm330lhhx_fs_g_t; -int32_t asm330lhhx_gy_full_scale_set(stmdev_ctx_t *ctx, asm330lhhx_fs_g_t val); -int32_t asm330lhhx_gy_full_scale_get(stmdev_ctx_t *ctx, asm330lhhx_fs_g_t *val); +int32_t asm330lhhx_gy_full_scale_set(const stmdev_ctx_t *ctx, asm330lhhx_fs_g_t val); +int32_t asm330lhhx_gy_full_scale_get(const stmdev_ctx_t *ctx, asm330lhhx_fs_g_t *val); typedef enum { @@ -2638,22 +2639,22 @@ typedef enum ASM330LHHX_GY_ODR_3333Hz = 9, ASM330LHHX_GY_ODR_6667Hz = 10, } asm330lhhx_odr_g_t; -int32_t asm330lhhx_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_gy_data_rate_set(const stmdev_ctx_t *ctx, asm330lhhx_odr_g_t val); -int32_t asm330lhhx_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_gy_data_rate_get(const stmdev_ctx_t *ctx, asm330lhhx_odr_g_t *val); -int32_t asm330lhhx_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { ASM330LHHX_LSb_1mg = 0, ASM330LHHX_LSb_16mg = 1, } asm330lhhx_usr_off_w_t; -int32_t asm330lhhx_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_xl_offset_weight_set(const stmdev_ctx_t *ctx, asm330lhhx_usr_off_w_t val); -int32_t asm330lhhx_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_xl_offset_weight_get(const stmdev_ctx_t *ctx, asm330lhhx_usr_off_w_t *val); typedef enum @@ -2661,9 +2662,9 @@ typedef enum ASM330LHHX_HIGH_PERFORMANCE_MD = 0, ASM330LHHX_LOW_NORMAL_POWER_MD = 1, } asm330lhhx_xl_hm_mode_t; -int32_t asm330lhhx_xl_power_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_xl_power_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_xl_hm_mode_t val); -int32_t asm330lhhx_xl_power_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_xl_power_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_xl_hm_mode_t *val); typedef enum @@ -2671,9 +2672,9 @@ typedef enum ASM330LHHX_GY_HIGH_PERFORMANCE = 0, ASM330LHHX_GY_NORMAL = 1, } asm330lhhx_g_hm_mode_t; -int32_t asm330lhhx_gy_power_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_gy_power_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_g_hm_mode_t val); -int32_t asm330lhhx_gy_power_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_gy_power_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_g_hm_mode_t *val); typedef struct @@ -2687,36 +2688,36 @@ typedef struct asm330lhhx_fsm_status_b_t fsm_status_b; asm330lhhx_mlc_status_mainpage_t mlc_status; } asm330lhhx_all_sources_t; -int32_t asm330lhhx_all_sources_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_all_sources_get(const stmdev_ctx_t *ctx, asm330lhhx_all_sources_t *val); -int32_t asm330lhhx_status_reg_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_status_reg_get(const stmdev_ctx_t *ctx, asm330lhhx_status_reg_t *val); -int32_t asm330lhhx_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t asm330lhhx_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhhx_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhhx_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t asm330lhhx_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t asm330lhhx_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhhx_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhhx_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t asm330lhhx_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t asm330lhhx_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhhx_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhhx_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t asm330lhhx_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_timestamp_rst(stmdev_ctx_t *ctx); +int32_t asm330lhhx_timestamp_rst(const stmdev_ctx_t *ctx); -int32_t asm330lhhx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); +int32_t asm330lhhx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); typedef enum { @@ -2725,21 +2726,21 @@ typedef enum ASM330LHHX_ROUND_GY = 2, ASM330LHHX_ROUND_GY_XL = 3, } asm330lhhx_rounding_t; -int32_t asm330lhhx_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_rounding_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_rounding_t val); -int32_t asm330lhhx_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_rounding_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_rounding_t *val); -int32_t asm330lhhx_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t asm330lhhx_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t asm330lhhx_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t asm330lhhx_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t asm330lhhx_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t asm330lhhx_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t asm330lhhx_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2747,17 +2748,17 @@ typedef enum ASM330LHHX_SENSOR_HUB_BANK = 1, ASM330LHHX_EMBEDDED_FUNC_BANK = 2, } asm330lhhx_reg_access_t; -int32_t asm330lhhx_mem_bank_set(stmdev_ctx_t *ctx, asm330lhhx_reg_access_t val); -int32_t asm330lhhx_mem_bank_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_mem_bank_set(const stmdev_ctx_t *ctx, asm330lhhx_reg_access_t val); +int32_t asm330lhhx_mem_bank_get(const stmdev_ctx_t *ctx, asm330lhhx_reg_access_t *val); -int32_t asm330lhhx_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address, +int32_t asm330lhhx_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val); -int32_t asm330lhhx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, +int32_t asm330lhhx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); -int32_t asm330lhhx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add, +int32_t asm330lhhx_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, uint8_t *val); -int32_t asm330lhhx_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, +int32_t asm330lhhx_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val); typedef enum @@ -2765,21 +2766,21 @@ typedef enum ASM330LHHX_DRDY_LATCHED = 0, ASM330LHHX_DRDY_PULSED = 1, } asm330lhhx_dataready_pulsed_t; -int32_t asm330lhhx_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_data_ready_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_dataready_pulsed_t val); -int32_t asm330lhhx_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_data_ready_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_dataready_pulsed_t *val); -int32_t asm330lhhx_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhhx_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t asm330lhhx_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2787,8 +2788,8 @@ typedef enum ASM330LHHX_XL_ST_POSITIVE = 1, ASM330LHHX_XL_ST_NEGATIVE = 2, } asm330lhhx_st_xl_t; -int32_t asm330lhhx_xl_self_test_set(stmdev_ctx_t *ctx, asm330lhhx_st_xl_t val); -int32_t asm330lhhx_xl_self_test_get(stmdev_ctx_t *ctx, asm330lhhx_st_xl_t *val); +int32_t asm330lhhx_xl_self_test_set(const stmdev_ctx_t *ctx, asm330lhhx_st_xl_t val); +int32_t asm330lhhx_xl_self_test_get(const stmdev_ctx_t *ctx, asm330lhhx_st_xl_t *val); typedef enum { @@ -2796,17 +2797,17 @@ typedef enum ASM330LHHX_GY_ST_POSITIVE = 1, ASM330LHHX_GY_ST_NEGATIVE = 3, } asm330lhhx_st_g_t; -int32_t asm330lhhx_gy_self_test_set(stmdev_ctx_t *ctx, asm330lhhx_st_g_t val); -int32_t asm330lhhx_gy_self_test_get(stmdev_ctx_t *ctx, asm330lhhx_st_g_t *val); +int32_t asm330lhhx_gy_self_test_set(const stmdev_ctx_t *ctx, asm330lhhx_st_g_t val); +int32_t asm330lhhx_gy_self_test_get(const stmdev_ctx_t *ctx, asm330lhhx_st_g_t *val); -int32_t asm330lhhx_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2819,13 +2820,13 @@ typedef enum ASM330LHHX_AGGRESSIVE = 6, ASM330LHHX_XTREME = 7, } asm330lhhx_ftype_t; -int32_t asm330lhhx_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, asm330lhhx_ftype_t val); -int32_t asm330lhhx_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, asm330lhhx_ftype_t *val); -int32_t asm330lhhx_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2853,22 +2854,22 @@ typedef enum ASM330LHHX_LP_ODR_DIV_400 = 0x06, ASM330LHHX_LP_ODR_DIV_800 = 0x07, } asm330lhhx_hp_slope_xl_en_t; -int32_t asm330lhhx_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, asm330lhhx_hp_slope_xl_en_t val); -int32_t asm330lhhx_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, asm330lhhx_hp_slope_xl_en_t *val); -int32_t asm330lhhx_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { ASM330LHHX_USE_SLOPE = 0, ASM330LHHX_USE_HPF = 1, } asm330lhhx_slope_fds_t; -int32_t asm330lhhx_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, asm330lhhx_slope_fds_t val); -int32_t asm330lhhx_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, asm330lhhx_slope_fds_t *val); typedef enum @@ -2879,9 +2880,9 @@ typedef enum ASM330LHHX_HP_FILTER_260mHz = 0x82, ASM330LHHX_HP_FILTER_1Hz04 = 0x83, } asm330lhhx_hpm_g_t; -int32_t asm330lhhx_gy_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, asm330lhhx_hpm_g_t val); -int32_t asm330lhhx_gy_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, asm330lhhx_hpm_g_t *val); typedef enum @@ -2889,9 +2890,9 @@ typedef enum ASM330LHHX_PULL_UP_DISC = 0, ASM330LHHX_PULL_UP_CONNECT = 1, } asm330lhhx_sdo_pu_en_t; -int32_t asm330lhhx_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_sdo_pu_en_t val); -int32_t asm330lhhx_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_sdo_pu_en_t *val); typedef enum @@ -2899,9 +2900,9 @@ typedef enum ASM330LHHX_PULL_DOWN_CONNECT = 0, ASM330LHHX_PULL_DOWN_DISC = 1, } asm330lhhx_pd_dis_int1_t; -int32_t asm330lhhx_int1_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_int1_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_pd_dis_int1_t val); -int32_t asm330lhhx_int1_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_int1_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_pd_dis_int1_t *val); typedef enum @@ -2909,17 +2910,17 @@ typedef enum ASM330LHHX_SPI_4_WIRE = 0, ASM330LHHX_SPI_3_WIRE = 1, } asm330lhhx_sim_t; -int32_t asm330lhhx_spi_mode_set(stmdev_ctx_t *ctx, asm330lhhx_sim_t val); -int32_t asm330lhhx_spi_mode_get(stmdev_ctx_t *ctx, asm330lhhx_sim_t *val); +int32_t asm330lhhx_spi_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_sim_t val); +int32_t asm330lhhx_spi_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_sim_t *val); typedef enum { ASM330LHHX_I2C_ENABLE = 0, ASM330LHHX_I2C_DISABLE = 1, } asm330lhhx_i2c_disable_t; -int32_t asm330lhhx_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_i2c_interface_set(const stmdev_ctx_t *ctx, asm330lhhx_i2c_disable_t val); -int32_t asm330lhhx_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_i2c_interface_get(const stmdev_ctx_t *ctx, asm330lhhx_i2c_disable_t *val); typedef enum @@ -2930,9 +2931,9 @@ typedef enum ASM330LHHX_I3C_ENABLE_T_1ms = 0x02, ASM330LHHX_I3C_ENABLE_T_25ms = 0x03, } asm330lhhx_i3c_disable_t; -int32_t asm330lhhx_i3c_disable_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_i3c_disable_set(const stmdev_ctx_t *ctx, asm330lhhx_i3c_disable_t val); -int32_t asm330lhhx_i3c_disable_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_i3c_disable_get(const stmdev_ctx_t *ctx, asm330lhhx_i3c_disable_t *val); typedef struct @@ -2944,9 +2945,9 @@ typedef struct asm330lhhx_fsm_int1_b_t fsm_int1_b; asm330lhhx_mlc_int1_t mlc_int1; } asm330lhhx_pin_int1_route_t; -int32_t asm330lhhx_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_pin_int1_route_set(const stmdev_ctx_t *ctx, asm330lhhx_pin_int1_route_t *val); -int32_t asm330lhhx_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_pin_int1_route_get(const stmdev_ctx_t *ctx, asm330lhhx_pin_int1_route_t *val); typedef struct @@ -2958,9 +2959,9 @@ typedef struct asm330lhhx_fsm_int2_b_t fsm_int2_b; asm330lhhx_mlc_int2_t mlc_int2; } asm330lhhx_pin_int2_route_t; -int32_t asm330lhhx_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_pin_int2_route_set(const stmdev_ctx_t *ctx, asm330lhhx_pin_int2_route_t *val); -int32_t asm330lhhx_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_pin_int2_route_get(const stmdev_ctx_t *ctx, asm330lhhx_pin_int2_route_t *val); typedef enum @@ -2968,21 +2969,21 @@ typedef enum ASM330LHHX_PUSH_PULL = 0, ASM330LHHX_OPEN_DRAIN = 1, } asm330lhhx_pp_od_t; -int32_t asm330lhhx_pin_mode_set(stmdev_ctx_t *ctx, asm330lhhx_pp_od_t val); -int32_t asm330lhhx_pin_mode_get(stmdev_ctx_t *ctx, asm330lhhx_pp_od_t *val); +int32_t asm330lhhx_pin_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_pp_od_t val); +int32_t asm330lhhx_pin_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_pp_od_t *val); typedef enum { ASM330LHHX_ACTIVE_HIGH = 0, ASM330LHHX_ACTIVE_LOW = 1, } asm330lhhx_h_lactive_t; -int32_t asm330lhhx_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_pin_polarity_set(const stmdev_ctx_t *ctx, asm330lhhx_h_lactive_t val); -int32_t asm330lhhx_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_pin_polarity_get(const stmdev_ctx_t *ctx, asm330lhhx_h_lactive_t *val); -int32_t asm330lhhx_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2991,9 +2992,9 @@ typedef enum ASM330LHHX_BASE_PULSED_EMB_LATCHED = 2, ASM330LHHX_ALL_INT_LATCHED = 3, } asm330lhhx_lir_t; -int32_t asm330lhhx_int_notification_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_int_notification_set(const stmdev_ctx_t *ctx, asm330lhhx_lir_t val); -int32_t asm330lhhx_int_notification_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_int_notification_get(const stmdev_ctx_t *ctx, asm330lhhx_lir_t *val); typedef enum @@ -3001,33 +3002,33 @@ typedef enum ASM330LHHX_LSb_FS_DIV_64 = 0, ASM330LHHX_LSb_FS_DIV_256 = 1, } asm330lhhx_wake_ths_w_t; -int32_t asm330lhhx_wkup_ths_weight_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_wkup_ths_weight_set(const stmdev_ctx_t *ctx, asm330lhhx_wake_ths_w_t val); -int32_t asm330lhhx_wkup_ths_weight_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_wkup_ths_weight_get(const stmdev_ctx_t *ctx, asm330lhhx_wake_ths_w_t *val); -int32_t asm330lhhx_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { ASM330LHHX_DRIVE_SLEEP_CHG_EVENT = 0, ASM330LHHX_DRIVE_SLEEP_STATUS = 1, } asm330lhhx_sleep_status_on_int_t; -int32_t asm330lhhx_act_pin_notification_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_act_pin_notification_set(const stmdev_ctx_t *ctx, asm330lhhx_sleep_status_on_int_t val); -int32_t asm330lhhx_act_pin_notification_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_act_pin_notification_get(const stmdev_ctx_t *ctx, asm330lhhx_sleep_status_on_int_t *val); typedef enum @@ -3037,13 +3038,13 @@ typedef enum ASM330LHHX_XL_12Hz5_GY_SLEEP = 2, ASM330LHHX_XL_12Hz5_GY_PD = 3, } asm330lhhx_inact_en_t; -int32_t asm330lhhx_act_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_act_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_inact_en_t val); -int32_t asm330lhhx_act_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_act_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_inact_en_t *val); -int32_t asm330lhhx_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3052,13 +3053,13 @@ typedef enum ASM330LHHX_DEG_60 = 2, ASM330LHHX_DEG_50 = 3, } asm330lhhx_sixd_ths_t; -int32_t asm330lhhx_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_6d_threshold_set(const stmdev_ctx_t *ctx, asm330lhhx_sixd_ths_t val); -int32_t asm330lhhx_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_6d_threshold_get(const stmdev_ctx_t *ctx, asm330lhhx_sixd_ths_t *val); -int32_t asm330lhhx_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3071,24 +3072,24 @@ typedef enum ASM330LHHX_FF_TSH_469mg = 6, ASM330LHHX_FF_TSH_500mg = 7, } asm330lhhx_ff_ths_t; -int32_t asm330lhhx_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_ff_threshold_set(const stmdev_ctx_t *ctx, asm330lhhx_ff_ths_t val); -int32_t asm330lhhx_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_ff_threshold_get(const stmdev_ctx_t *ctx, asm330lhhx_ff_ths_t *val); -int32_t asm330lhhx_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t asm330lhhx_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t asm330lhhx_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhhx_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t asm330lhhx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3105,9 +3106,9 @@ typedef enum ASM330LHHX_XL_BATCHED_AT_6667Hz = 10, ASM330LHHX_XL_BATCHED_AT_1Hz6 = 11, } asm330lhhx_bdr_xl_t; -int32_t asm330lhhx_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_xl_batch_set(const stmdev_ctx_t *ctx, asm330lhhx_bdr_xl_t val); -int32_t asm330lhhx_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_xl_batch_get(const stmdev_ctx_t *ctx, asm330lhhx_bdr_xl_t *val); typedef enum @@ -3125,9 +3126,9 @@ typedef enum ASM330LHHX_GY_BATCHED_AT_6667Hz = 10, ASM330LHHX_GY_BATCHED_AT_6Hz5 = 11, } asm330lhhx_bdr_gy_t; -int32_t asm330lhhx_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_gy_batch_set(const stmdev_ctx_t *ctx, asm330lhhx_bdr_gy_t val); -int32_t asm330lhhx_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_gy_batch_get(const stmdev_ctx_t *ctx, asm330lhhx_bdr_gy_t *val); typedef enum @@ -3139,8 +3140,8 @@ typedef enum ASM330LHHX_STREAM_MODE = 6, ASM330LHHX_BYPASS_TO_FIFO_MODE = 7, } asm330lhhx_fifo_mode_t; -int32_t asm330lhhx_fifo_mode_set(stmdev_ctx_t *ctx, asm330lhhx_fifo_mode_t val); -int32_t asm330lhhx_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_fifo_mode_t val); +int32_t asm330lhhx_fifo_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_fifo_mode_t *val); typedef enum @@ -3150,9 +3151,9 @@ typedef enum ASM330LHHX_TEMP_BATCHED_AT_12Hz5 = 2, ASM330LHHX_TEMP_BATCHED_AT_1Hz6 = 3, } asm330lhhx_odr_t_batch_t; -int32_t asm330lhhx_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_temp_batch_set(const stmdev_ctx_t *ctx, asm330lhhx_odr_t_batch_t val); -int32_t asm330lhhx_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_temp_batch_get(const stmdev_ctx_t *ctx, asm330lhhx_odr_t_batch_t *val); typedef enum @@ -3162,9 +3163,9 @@ typedef enum ASM330LHHX_DEC_8 = 2, ASM330LHHX_DEC_32 = 3, } asm330lhhx_dec_ts_batch_t; -int32_t asm330lhhx_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, asm330lhhx_dec_ts_batch_t val); -int32_t asm330lhhx_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, asm330lhhx_dec_ts_batch_t *val); typedef enum @@ -3172,29 +3173,29 @@ typedef enum ASM330LHHX_XL_BATCH_EVENT = 0, ASM330LHHX_GYRO_BATCH_EVENT = 1, } asm330lhhx_trig_counter_bdr_t; -int32_t asm330lhhx_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, asm330lhhx_trig_counter_bdr_t val); -int32_t asm330lhhx_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, asm330lhhx_trig_counter_bdr_t *val); -int32_t asm330lhhx_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_batch_counter_threshold_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t asm330lhhx_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t asm330lhhx_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t asm330lhhx_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t asm330lhhx_fifo_status_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_status_get(const stmdev_ctx_t *ctx, asm330lhhx_fifo_status2_t *val); -int32_t asm330lhhx_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3209,20 +3210,20 @@ typedef enum ASM330LHHX_SENSORHUB_SLAVE3_TAG = 0x11, ASM330LHHX_SENSORHUB_NACK_TAG = 0x19, } asm330lhhx_fifo_tag_t; -int32_t asm330lhhx_fifo_sensor_tag_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, asm330lhhx_fifo_tag_t *val); -int32_t asm330lhhx_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3232,9 +3233,9 @@ typedef enum ASM330LHHX_LEVEL_TRIGGER = 2, ASM330LHHX_EDGE_TRIGGER = 4, } asm330lhhx_den_mode_t; -int32_t asm330lhhx_den_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_den_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_den_mode_t val); -int32_t asm330lhhx_den_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_den_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_den_mode_t *val); typedef enum @@ -3242,9 +3243,9 @@ typedef enum ASM330LHHX_DEN_ACT_LOW = 0, ASM330LHHX_DEN_ACT_HIGH = 1, } asm330lhhx_den_lh_t; -int32_t asm330lhhx_den_polarity_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_den_polarity_set(const stmdev_ctx_t *ctx, asm330lhhx_den_lh_t val); -int32_t asm330lhhx_den_polarity_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_den_polarity_get(const stmdev_ctx_t *ctx, asm330lhhx_den_lh_t *val); typedef enum @@ -3253,28 +3254,28 @@ typedef enum ASM330LHHX_STAMP_IN_XL_DATA = 1, ASM330LHHX_STAMP_IN_GY_XL_DATA = 2, } asm330lhhx_den_xl_g_t; -int32_t asm330lhhx_den_enable_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_den_enable_set(const stmdev_ctx_t *ctx, asm330lhhx_den_xl_g_t val); -int32_t asm330lhhx_den_enable_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_den_enable_get(const stmdev_ctx_t *ctx, asm330lhhx_den_xl_g_t *val); -int32_t asm330lhhx_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t asm330lhhx_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t asm330lhhx_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhhx_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t asm330lhhx_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val); -int32_t asm330lhhx_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t asm330lhhx_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val); +int32_t asm330lhhx_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t asm330lhhx_mag_soft_iron_set(stmdev_ctx_t *ctx, uint16_t *val); -int32_t asm330lhhx_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t asm330lhhx_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint16_t *val); +int32_t asm330lhhx_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum { @@ -3285,9 +3286,9 @@ typedef enum ASM330LHHX_Z_EQ_MIN_Z = 4, ASM330LHHX_Z_EQ_Z = 5, } asm330lhhx_mag_z_axis_t; -int32_t asm330lhhx_mag_z_orient_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_mag_z_orient_set(const stmdev_ctx_t *ctx, asm330lhhx_mag_z_axis_t val); -int32_t asm330lhhx_mag_z_orient_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_mag_z_orient_get(const stmdev_ctx_t *ctx, asm330lhhx_mag_z_axis_t *val); typedef enum @@ -3299,9 +3300,9 @@ typedef enum ASM330LHHX_Y_EQ_MIN_Z = 4, ASM330LHHX_Y_EQ_Z = 5, } asm330lhhx_mag_y_axis_t; -int32_t asm330lhhx_mag_y_orient_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_mag_y_orient_set(const stmdev_ctx_t *ctx, asm330lhhx_mag_y_axis_t val); -int32_t asm330lhhx_mag_y_orient_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_mag_y_orient_get(const stmdev_ctx_t *ctx, asm330lhhx_mag_y_axis_t *val); typedef enum @@ -3313,9 +3314,9 @@ typedef enum ASM330LHHX_X_EQ_MIN_Z = 4, ASM330LHHX_X_EQ_Z = 5, } asm330lhhx_mag_x_axis_t; -int32_t asm330lhhx_mag_x_orient_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_mag_x_orient_set(const stmdev_ctx_t *ctx, asm330lhhx_mag_x_axis_t val); -int32_t asm330lhhx_mag_x_orient_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_mag_x_orient_get(const stmdev_ctx_t *ctx, asm330lhhx_mag_x_axis_t *val); typedef struct @@ -3337,31 +3338,31 @@ typedef struct uint16_t fsm15 : 1; uint16_t fsm16 : 1; } asm330lhhx_fsm_status_t; -int32_t asm330lhhx_fsm_status_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fsm_status_get(const stmdev_ctx_t *ctx, asm330lhhx_fsm_status_t *val); -int32_t asm330lhhx_fsm_out_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhhx_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t asm330lhhx_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_emb_func_clk_dis_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_emb_func_clk_dis_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_emb_func_clk_dis_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_emb_func_clk_dis_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { asm330lhhx_fsm_enable_a_t fsm_enable_a; asm330lhhx_fsm_enable_b_t fsm_enable_b; } asm330lhhx_emb_fsm_enable_t; -int32_t asm330lhhx_fsm_enable_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fsm_enable_set(const stmdev_ctx_t *ctx, asm330lhhx_emb_fsm_enable_t *val); -int32_t asm330lhhx_fsm_enable_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fsm_enable_get(const stmdev_ctx_t *ctx, asm330lhhx_emb_fsm_enable_t *val); -int32_t asm330lhhx_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t asm330lhhx_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t asm330lhhx_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhhx_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum { @@ -3369,9 +3370,9 @@ typedef enum ASM330LHHX_LC_CLEAR = 1, ASM330LHHX_LC_CLEAR_DONE = 2, } asm330lhhx_fsm_lc_clr_t; -int32_t asm330lhhx_long_clr_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_long_clr_set(const stmdev_ctx_t *ctx, asm330lhhx_fsm_lc_clr_t val); -int32_t asm330lhhx_long_clr_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_long_clr_get(const stmdev_ctx_t *ctx, asm330lhhx_fsm_lc_clr_t *val); typedef enum @@ -3381,29 +3382,29 @@ typedef enum ASM330LHHX_ODR_FSM_52Hz = 2, ASM330LHHX_ODR_FSM_104Hz = 3, } asm330lhhx_fsm_odr_t; -int32_t asm330lhhx_fsm_data_rate_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fsm_data_rate_set(const stmdev_ctx_t *ctx, asm330lhhx_fsm_odr_t val); -int32_t asm330lhhx_fsm_data_rate_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fsm_data_rate_get(const stmdev_ctx_t *ctx, asm330lhhx_fsm_odr_t *val); -int32_t asm330lhhx_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t asm330lhhx_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t asm330lhhx_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhhx_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t asm330lhhx_fsm_number_of_programs_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t asm330lhhx_fsm_number_of_programs_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t asm330lhhx_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t asm330lhhx_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t asm330lhhx_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhhx_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t asm330lhhx_mlc_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_mlc_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_mlc_status_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_mlc_status_get(const stmdev_ctx_t *ctx, asm330lhhx_mlc_status_mainpage_t *val); typedef enum @@ -3413,18 +3414,18 @@ typedef enum ASM330LHHX_ODR_PRGS_52Hz = 2, ASM330LHHX_ODR_PRGS_104Hz = 3, } asm330lhhx_mlc_odr_t; -int32_t asm330lhhx_mlc_data_rate_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_mlc_data_rate_set(const stmdev_ctx_t *ctx, asm330lhhx_mlc_odr_t val); -int32_t asm330lhhx_mlc_data_rate_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_mlc_data_rate_get(const stmdev_ctx_t *ctx, asm330lhhx_mlc_odr_t *val); -int32_t asm330lhhx_mlc_init_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_mlc_init_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_mlc_init_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_mlc_init_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t asm330lhhx_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhhx_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t asm330lhhx_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t asm330lhhx_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t asm330lhhx_mlc_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhhx_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef struct { @@ -3447,7 +3448,7 @@ typedef struct asm330lhhx_sensor_hub_17_t sh_byte_17; asm330lhhx_sensor_hub_18_t sh_byte_18; } asm330lhhx_emb_sh_read_t; -int32_t asm330lhhx_sh_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_read_data_raw_get(const stmdev_ctx_t *ctx, asm330lhhx_emb_sh_read_t *val); typedef enum @@ -3457,35 +3458,35 @@ typedef enum ASM330LHHX_SLV_0_1_2 = 2, ASM330LHHX_SLV_0_1_2_3 = 3, } asm330lhhx_aux_sens_on_t; -int32_t asm330lhhx_sh_slave_connected_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_slave_connected_set(const stmdev_ctx_t *ctx, asm330lhhx_aux_sens_on_t val); -int32_t asm330lhhx_sh_slave_connected_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_slave_connected_get(const stmdev_ctx_t *ctx, asm330lhhx_aux_sens_on_t *val); -int32_t asm330lhhx_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { ASM330LHHX_EXT_PULL_UP = 0, ASM330LHHX_INTERNAL_PULL_UP = 1, } asm330lhhx_shub_pu_en_t; -int32_t asm330lhhx_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_pin_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_shub_pu_en_t val); -int32_t asm330lhhx_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_pin_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_shub_pu_en_t *val); -int32_t asm330lhhx_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t asm330lhhx_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhx_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { ASM330LHHX_EXT_ON_INT2_PIN = 0, ASM330LHHX_XL_GY_DRDY = 1, } asm330lhhx_start_config_t; -int32_t asm330lhhx_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_syncro_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_start_config_t val); -int32_t asm330lhhx_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_syncro_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_start_config_t *val); typedef enum @@ -3493,13 +3494,13 @@ typedef enum ASM330LHHX_EACH_SH_CYCLE = 0, ASM330LHHX_ONLY_FIRST_CYCLE = 1, } asm330lhhx_write_once_t; -int32_t asm330lhhx_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_write_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_write_once_t val); -int32_t asm330lhhx_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_write_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_write_once_t *val); -int32_t asm330lhhx_sh_reset_set(stmdev_ctx_t *ctx); -int32_t asm330lhhx_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t asm330lhhx_sh_reset_set(const stmdev_ctx_t *ctx); +int32_t asm330lhhx_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3508,9 +3509,9 @@ typedef enum ASM330LHHX_SH_ODR_26Hz = 2, ASM330LHHX_SH_ODR_13Hz = 3, } asm330lhhx_shub_odr_t; -int32_t asm330lhhx_sh_data_rate_set(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_data_rate_set(const stmdev_ctx_t *ctx, asm330lhhx_shub_odr_t val); -int32_t asm330lhhx_sh_data_rate_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_data_rate_get(const stmdev_ctx_t *ctx, asm330lhhx_shub_odr_t *val); typedef struct @@ -3519,7 +3520,7 @@ typedef struct uint8_t slv0_subadd; uint8_t slv0_data; } asm330lhhx_sh_cfg_write_t; -int32_t asm330lhhx_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_cfg_write(const stmdev_ctx_t *ctx, asm330lhhx_sh_cfg_write_t *val); typedef struct @@ -3528,16 +3529,16 @@ typedef struct uint8_t slv_subadd; uint8_t slv_len; } asm330lhhx_sh_cfg_read_t; -int32_t asm330lhhx_sh_slv0_cfg_read(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, asm330lhhx_sh_cfg_read_t *val); -int32_t asm330lhhx_sh_slv1_cfg_read(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, asm330lhhx_sh_cfg_read_t *val); -int32_t asm330lhhx_sh_slv2_cfg_read(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, asm330lhhx_sh_cfg_read_t *val); -int32_t asm330lhhx_sh_slv3_cfg_read(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, asm330lhhx_sh_cfg_read_t *val); -int32_t asm330lhhx_sh_status_get(stmdev_ctx_t *ctx, +int32_t asm330lhhx_sh_status_get(const stmdev_ctx_t *ctx, asm330lhhx_status_master_t *val); /** diff --git a/sensor/stmemsc/asm330lhhxg1_STdC/driver/asm330lhhxg1_reg.c b/sensor/stmemsc/asm330lhhxg1_STdC/driver/asm330lhhxg1_reg.c new file mode 100644 index 00000000..c8ab86f9 --- /dev/null +++ b/sensor/stmemsc/asm330lhhxg1_STdC/driver/asm330lhhxg1_reg.c @@ -0,0 +1,8371 @@ +/* + ****************************************************************************** + * @file asm330lhhxg1_reg.c + * @author Sensors Software Solution Team + * @brief ASM330LHHXG1 driver file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "asm330lhhxg1_reg.h" + +/** + * @defgroup ASM330LHHXG1 + * @brief This file provides a set of functions needed to drive the + * asm330lhhxg1 enhanced inertial module. + * @{ + * + */ + +/** + * @defgroup ASM330LHHXG1_Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +/** + * @brief Read generic device register + * + * @param ctx read / write interface definitions(ptr) + * @param reg register to read + * @param data pointer to buffer that store the data read(ptr) + * @param len number of consecutive register to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak asm330lhhxg1_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len) +{ + int32_t ret; + + if (ctx == NULL) return -1; + + ret = ctx->read_reg(ctx->handle, reg, data, len); + + return ret; +} + +/** + * @brief Write generic device register + * + * @param ctx read / write interface definitions(ptr) + * @param reg register to write + * @param data pointer to data to write in register reg(ptr) + * @param len number of consecutive register to write + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak asm330lhhxg1_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len) +{ + int32_t ret; + + if (ctx == NULL) return -1; + + ret = ctx->write_reg(ctx->handle, reg, data, len); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHHXG1_Sensitivity + * @brief These functions convert raw-data into engineering units. + * @{ + * + */ + +float_t asm330lhhxg1_from_fs2g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.061f); +} + +float_t asm330lhhxg1_from_fs4g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.122f); +} + +float_t asm330lhhxg1_from_fs8g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.244f); +} + +float_t asm330lhhxg1_from_fs16g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.488f); +} + +float_t asm330lhhxg1_from_fs125dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 4.375f); +} + +float_t asm330lhhxg1_from_fs250dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 8.75f); +} + +float_t asm330lhhxg1_from_fs500dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 17.50f); +} + +float_t asm330lhhxg1_from_fs1000dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 35.0f); +} + +float_t asm330lhhxg1_from_fs2000dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 70.0f); +} + +float_t asm330lhhxg1_from_fs4000dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 140.0f); +} + +float_t asm330lhhxg1_from_lsb_to_celsius(int16_t lsb) +{ + return (((float_t)lsb / 256.0f) + 25.0f); +} + +float_t asm330lhhxg1_from_lsb_to_nsec(int32_t lsb) +{ + return ((float_t)lsb * 25000.0f); +} + +/** + * @} + * + */ + +/** + * @defgroup LSM9DS1_Data_generation + * @brief This section groups all the functions concerning data + * generation + * @{ + * + */ + +/** + * @brief Accelerometer full-scale selection[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fs_xl in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_full_scale_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_fs_xl_t val) +{ + asm330lhhxg1_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret == 0) + { + ctrl1_xl.fs_xl = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL1_XL, + (uint8_t *)&ctrl1_xl, 1); + } + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of fs_xl in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_full_scale_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_fs_xl_t *val) +{ + asm330lhhxg1_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + switch (ctrl1_xl.fs_xl) + { + case ASM330LHHXG1_2g: + *val = ASM330LHHXG1_2g; + break; + case ASM330LHHXG1_16g: + *val = ASM330LHHXG1_16g; + break; + case ASM330LHHXG1_4g: + *val = ASM330LHHXG1_4g; + break; + case ASM330LHHXG1_8g: + *val = ASM330LHHXG1_8g; + break; + default: + *val = ASM330LHHXG1_2g; + break; + } + return ret; +} + +/** + * @brief Accelerometer UI data rate selection.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of odr_xl in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_data_rate_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_odr_xl_t val) +{ + asm330lhhxg1_odr_xl_t odr_xl = val; + asm330lhhxg1_emb_fsm_enable_t fsm_enable; + asm330lhhxg1_fsm_odr_t fsm_odr; + asm330lhhxg1_ctrl1_xl_t ctrl1_xl; + asm330lhhxg1_mlc_odr_t mlc_odr; + uint8_t mlc_enable; + int32_t ret; + + /* Check the Finite State Machine data rate constraints */ + ret = asm330lhhxg1_fsm_enable_get(ctx, &fsm_enable); + if (ret == 0) + { + if ((fsm_enable.fsm_enable_a.fsm1_en | + fsm_enable.fsm_enable_a.fsm2_en | + fsm_enable.fsm_enable_a.fsm3_en | + fsm_enable.fsm_enable_a.fsm4_en | + fsm_enable.fsm_enable_a.fsm5_en | + fsm_enable.fsm_enable_a.fsm6_en | + fsm_enable.fsm_enable_a.fsm7_en | + fsm_enable.fsm_enable_a.fsm8_en | + fsm_enable.fsm_enable_b.fsm9_en | + fsm_enable.fsm_enable_b.fsm10_en | + fsm_enable.fsm_enable_b.fsm11_en | + fsm_enable.fsm_enable_b.fsm12_en | + fsm_enable.fsm_enable_b.fsm13_en | + fsm_enable.fsm_enable_b.fsm14_en | + fsm_enable.fsm_enable_b.fsm15_en | + fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE) + { + + ret = asm330lhhxg1_fsm_data_rate_get(ctx, &fsm_odr); + if (ret == 0) + { + switch (fsm_odr) + { + case ASM330LHHXG1_ODR_FSM_12Hz5: + + if (val == ASM330LHHXG1_XL_ODR_OFF) + { + odr_xl = ASM330LHHXG1_XL_ODR_12Hz5; + + } + else + { + odr_xl = val; + } + break; + case ASM330LHHXG1_ODR_FSM_26Hz: + + if (val == ASM330LHHXG1_XL_ODR_OFF) + { + odr_xl = ASM330LHHXG1_XL_ODR_26Hz; + + } + else if (val == ASM330LHHXG1_XL_ODR_12Hz5) + { + odr_xl = ASM330LHHXG1_XL_ODR_26Hz; + + } + else + { + odr_xl = val; + } + break; + case ASM330LHHXG1_ODR_FSM_52Hz: + + if (val == ASM330LHHXG1_XL_ODR_OFF) + { + odr_xl = ASM330LHHXG1_XL_ODR_52Hz; + + } + else if (val == ASM330LHHXG1_XL_ODR_12Hz5) + { + odr_xl = ASM330LHHXG1_XL_ODR_52Hz; + + } + else if (val == ASM330LHHXG1_XL_ODR_26Hz) + { + odr_xl = ASM330LHHXG1_XL_ODR_52Hz; + + } + else + { + odr_xl = val; + } + break; + case ASM330LHHXG1_ODR_FSM_104Hz: + + if (val == ASM330LHHXG1_XL_ODR_OFF) + { + odr_xl = ASM330LHHXG1_XL_ODR_104Hz; + + } + else if (val == ASM330LHHXG1_XL_ODR_12Hz5) + { + odr_xl = ASM330LHHXG1_XL_ODR_104Hz; + + } + else if (val == ASM330LHHXG1_XL_ODR_26Hz) + { + odr_xl = ASM330LHHXG1_XL_ODR_104Hz; + + } + else if (val == ASM330LHHXG1_XL_ODR_52Hz) + { + odr_xl = ASM330LHHXG1_XL_ODR_104Hz; + + } + else + { + odr_xl = val; + } + break; + default: + odr_xl = val; + break; + } + } + } + } + + /* Check the Machine Learning Core data rate constraints */ + mlc_enable = PROPERTY_DISABLE; + if (ret == 0) + { + ret = asm330lhhxg1_mlc_get(ctx, &mlc_enable); + if (mlc_enable == PROPERTY_ENABLE) + { + + ret = asm330lhhxg1_mlc_data_rate_get(ctx, &mlc_odr); + if (ret == 0) + { + switch (mlc_odr) + { + case ASM330LHHXG1_ODR_PRGS_12Hz5: + + if (val == ASM330LHHXG1_XL_ODR_OFF) + { + odr_xl = ASM330LHHXG1_XL_ODR_12Hz5; + + } + else + { + odr_xl = val; + } + break; + case ASM330LHHXG1_ODR_PRGS_26Hz: + if (val == ASM330LHHXG1_XL_ODR_OFF) + { + odr_xl = ASM330LHHXG1_XL_ODR_26Hz; + + } + else if (val == ASM330LHHXG1_XL_ODR_12Hz5) + { + odr_xl = ASM330LHHXG1_XL_ODR_26Hz; + + } + else + { + odr_xl = val; + } + break; + case ASM330LHHXG1_ODR_PRGS_52Hz: + + if (val == ASM330LHHXG1_XL_ODR_OFF) + { + odr_xl = ASM330LHHXG1_XL_ODR_52Hz; + + } + else if (val == ASM330LHHXG1_XL_ODR_12Hz5) + { + odr_xl = ASM330LHHXG1_XL_ODR_52Hz; + + } + else if (val == ASM330LHHXG1_XL_ODR_26Hz) + { + odr_xl = ASM330LHHXG1_XL_ODR_52Hz; + + } + else + { + odr_xl = val; + } + break; + case ASM330LHHXG1_ODR_PRGS_104Hz: + if (val == ASM330LHHXG1_XL_ODR_OFF) + { + odr_xl = ASM330LHHXG1_XL_ODR_104Hz; + + } + else if (val == ASM330LHHXG1_XL_ODR_12Hz5) + { + odr_xl = ASM330LHHXG1_XL_ODR_104Hz; + + } + else if (val == ASM330LHHXG1_XL_ODR_26Hz) + { + odr_xl = ASM330LHHXG1_XL_ODR_104Hz; + + } + else if (val == ASM330LHHXG1_XL_ODR_52Hz) + { + odr_xl = ASM330LHHXG1_XL_ODR_104Hz; + + } + else + { + odr_xl = val; + } + break; + default: + odr_xl = val; + break; + } + } + } + } + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + } + if (ret == 0) + { + ctrl1_xl.odr_xl = (uint8_t)odr_xl; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL1_XL, + (uint8_t *)&ctrl1_xl, 1); + } + return ret; +} + +/** + * @brief Accelerometer UI data rate selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of odr_xl in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_data_rate_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_odr_xl_t *val) +{ + asm330lhhxg1_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + switch (ctrl1_xl.odr_xl) + { + case ASM330LHHXG1_XL_ODR_OFF: + *val = ASM330LHHXG1_XL_ODR_OFF; + break; + case ASM330LHHXG1_XL_ODR_12Hz5: + *val = ASM330LHHXG1_XL_ODR_12Hz5; + break; + case ASM330LHHXG1_XL_ODR_26Hz: + *val = ASM330LHHXG1_XL_ODR_26Hz; + break; + case ASM330LHHXG1_XL_ODR_52Hz: + *val = ASM330LHHXG1_XL_ODR_52Hz; + break; + case ASM330LHHXG1_XL_ODR_104Hz: + *val = ASM330LHHXG1_XL_ODR_104Hz; + break; + case ASM330LHHXG1_XL_ODR_208Hz: + *val = ASM330LHHXG1_XL_ODR_208Hz; + break; + case ASM330LHHXG1_XL_ODR_417Hz: + *val = ASM330LHHXG1_XL_ODR_417Hz; + break; + case ASM330LHHXG1_XL_ODR_833Hz: + *val = ASM330LHHXG1_XL_ODR_833Hz; + break; + case ASM330LHHXG1_XL_ODR_1667Hz: + *val = ASM330LHHXG1_XL_ODR_1667Hz; + break; + case ASM330LHHXG1_XL_ODR_3333Hz: + *val = ASM330LHHXG1_XL_ODR_3333Hz; + break; + case ASM330LHHXG1_XL_ODR_6667Hz: + *val = ASM330LHHXG1_XL_ODR_6667Hz; + break; + case ASM330LHHXG1_XL_ODR_1Hz6: + *val = ASM330LHHXG1_XL_ODR_1Hz6; + break; + default: + *val = ASM330LHHXG1_XL_ODR_OFF; + break; + } + return ret; +} + +/** + * @brief Gyroscope UI chain full-scale selection.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fs_g in reg CTRL2_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_gy_full_scale_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_fs_g_t val) +{ + asm330lhhxg1_ctrl2_g_t ctrl2_g; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + if (ret == 0) + { + ctrl2_g.fs_g = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + } + return ret; +} + +/** + * @brief Gyroscope UI chain full-scale selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of fs_g in reg CTRL2_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_gy_full_scale_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_fs_g_t *val) +{ + asm330lhhxg1_ctrl2_g_t ctrl2_g; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + switch (ctrl2_g.fs_g) + { + case ASM330LHHXG1_125dps: + *val = ASM330LHHXG1_125dps; + break; + case ASM330LHHXG1_250dps: + *val = ASM330LHHXG1_250dps; + break; + case ASM330LHHXG1_500dps: + *val = ASM330LHHXG1_500dps; + break; + case ASM330LHHXG1_1000dps: + *val = ASM330LHHXG1_1000dps; + break; + case ASM330LHHXG1_2000dps: + *val = ASM330LHHXG1_2000dps; + break; + case ASM330LHHXG1_4000dps: + *val = ASM330LHHXG1_4000dps; + break; + default: + *val = ASM330LHHXG1_125dps; + break; + } + return ret; +} + +/** + * @brief Gyroscope data rate.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of odr_g in reg CTRL2_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_gy_data_rate_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_odr_g_t val) +{ + asm330lhhxg1_odr_g_t odr_gy = val; + asm330lhhxg1_emb_fsm_enable_t fsm_enable; + asm330lhhxg1_fsm_odr_t fsm_odr; + asm330lhhxg1_ctrl2_g_t ctrl2_g; + asm330lhhxg1_mlc_odr_t mlc_odr; + uint8_t mlc_enable; + int32_t ret; + + /* Check the Finite State Machine data rate constraints */ + ret = asm330lhhxg1_fsm_enable_get(ctx, &fsm_enable); + if (ret == 0) + { + if ((fsm_enable.fsm_enable_a.fsm1_en | + fsm_enable.fsm_enable_a.fsm2_en | + fsm_enable.fsm_enable_a.fsm3_en | + fsm_enable.fsm_enable_a.fsm4_en | + fsm_enable.fsm_enable_a.fsm5_en | + fsm_enable.fsm_enable_a.fsm6_en | + fsm_enable.fsm_enable_a.fsm7_en | + fsm_enable.fsm_enable_a.fsm8_en | + fsm_enable.fsm_enable_b.fsm9_en | + fsm_enable.fsm_enable_b.fsm10_en | + fsm_enable.fsm_enable_b.fsm11_en | + fsm_enable.fsm_enable_b.fsm12_en | + fsm_enable.fsm_enable_b.fsm13_en | + fsm_enable.fsm_enable_b.fsm14_en | + fsm_enable.fsm_enable_b.fsm15_en | + fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE) + { + + ret = asm330lhhxg1_fsm_data_rate_get(ctx, &fsm_odr); + if (ret == 0) + { + switch (fsm_odr) + { + case ASM330LHHXG1_ODR_FSM_12Hz5: + + if (val == ASM330LHHXG1_GY_ODR_OFF) + { + odr_gy = ASM330LHHXG1_GY_ODR_12Hz5; + + } + else + { + odr_gy = val; + } + break; + case ASM330LHHXG1_ODR_FSM_26Hz: + + if (val == ASM330LHHXG1_GY_ODR_OFF) + { + odr_gy = ASM330LHHXG1_GY_ODR_26Hz; + + } + else if (val == ASM330LHHXG1_GY_ODR_12Hz5) + { + odr_gy = ASM330LHHXG1_GY_ODR_26Hz; + + } + else + { + odr_gy = val; + } + break; + case ASM330LHHXG1_ODR_FSM_52Hz: + + if (val == ASM330LHHXG1_GY_ODR_OFF) + { + odr_gy = ASM330LHHXG1_GY_ODR_52Hz; + + } + else if (val == ASM330LHHXG1_GY_ODR_12Hz5) + { + odr_gy = ASM330LHHXG1_GY_ODR_52Hz; + + } + else if (val == ASM330LHHXG1_GY_ODR_26Hz) + { + odr_gy = ASM330LHHXG1_GY_ODR_52Hz; + + } + else + { + odr_gy = val; + } + break; + case ASM330LHHXG1_ODR_FSM_104Hz: + + if (val == ASM330LHHXG1_GY_ODR_OFF) + { + odr_gy = ASM330LHHXG1_GY_ODR_104Hz; + + } + else if (val == ASM330LHHXG1_GY_ODR_12Hz5) + { + odr_gy = ASM330LHHXG1_GY_ODR_104Hz; + + } + else if (val == ASM330LHHXG1_GY_ODR_26Hz) + { + odr_gy = ASM330LHHXG1_GY_ODR_104Hz; + + } + else if (val == ASM330LHHXG1_GY_ODR_52Hz) + { + odr_gy = ASM330LHHXG1_GY_ODR_104Hz; + + } + else + { + odr_gy = val; + } + break; + default: + odr_gy = val; + break; + } + } + } + } + + /* Check the Machine Learning Core data rate constraints */ + mlc_enable = PROPERTY_DISABLE; + if (ret == 0) + { + ret = asm330lhhxg1_mlc_get(ctx, &mlc_enable); + if (mlc_enable == PROPERTY_ENABLE) + { + + ret = asm330lhhxg1_mlc_data_rate_get(ctx, &mlc_odr); + if (ret == 0) + { + switch (mlc_odr) + { + case ASM330LHHXG1_ODR_PRGS_12Hz5: + + if (val == ASM330LHHXG1_GY_ODR_OFF) + { + odr_gy = ASM330LHHXG1_GY_ODR_12Hz5; + + } + else + { + odr_gy = val; + } + break; + case ASM330LHHXG1_ODR_PRGS_26Hz: + + if (val == ASM330LHHXG1_GY_ODR_OFF) + { + odr_gy = ASM330LHHXG1_GY_ODR_26Hz; + + } + else if (val == ASM330LHHXG1_GY_ODR_12Hz5) + { + odr_gy = ASM330LHHXG1_GY_ODR_26Hz; + + } + else + { + odr_gy = val; + } + break; + case ASM330LHHXG1_ODR_PRGS_52Hz: + + if (val == ASM330LHHXG1_GY_ODR_OFF) + { + odr_gy = ASM330LHHXG1_GY_ODR_52Hz; + + } + else if (val == ASM330LHHXG1_GY_ODR_12Hz5) + { + odr_gy = ASM330LHHXG1_GY_ODR_52Hz; + + } + else if (val == ASM330LHHXG1_GY_ODR_26Hz) + { + odr_gy = ASM330LHHXG1_GY_ODR_52Hz; + + } + else + { + odr_gy = val; + } + break; + case ASM330LHHXG1_ODR_PRGS_104Hz: + + if (val == ASM330LHHXG1_GY_ODR_OFF) + { + odr_gy = ASM330LHHXG1_GY_ODR_104Hz; + + } + else if (val == ASM330LHHXG1_GY_ODR_12Hz5) + { + odr_gy = ASM330LHHXG1_GY_ODR_104Hz; + + } + else if (val == ASM330LHHXG1_GY_ODR_26Hz) + { + odr_gy = ASM330LHHXG1_GY_ODR_104Hz; + + } + else if (val == ASM330LHHXG1_GY_ODR_52Hz) + { + odr_gy = ASM330LHHXG1_GY_ODR_104Hz; + + } + else + { + odr_gy = val; + } + break; + default: + odr_gy = val; + break; + } + } + } + } + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + } + if (ret == 0) + { + ctrl2_g.odr_g = (uint8_t)odr_gy; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + } + return ret; +} + +/** + * @brief Gyroscope data rate.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of odr_g in reg CTRL2_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_gy_data_rate_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_odr_g_t *val) +{ + asm330lhhxg1_ctrl2_g_t ctrl2_g; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL2_G, (uint8_t *)&ctrl2_g, 1); + switch (ctrl2_g.odr_g) + { + case ASM330LHHXG1_GY_ODR_OFF: + *val = ASM330LHHXG1_GY_ODR_OFF; + break; + case ASM330LHHXG1_GY_ODR_12Hz5: + *val = ASM330LHHXG1_GY_ODR_12Hz5; + break; + case ASM330LHHXG1_GY_ODR_26Hz: + *val = ASM330LHHXG1_GY_ODR_26Hz; + break; + case ASM330LHHXG1_GY_ODR_52Hz: + *val = ASM330LHHXG1_GY_ODR_52Hz; + break; + case ASM330LHHXG1_GY_ODR_104Hz: + *val = ASM330LHHXG1_GY_ODR_104Hz; + break; + case ASM330LHHXG1_GY_ODR_208Hz: + *val = ASM330LHHXG1_GY_ODR_208Hz; + break; + case ASM330LHHXG1_GY_ODR_417Hz: + *val = ASM330LHHXG1_GY_ODR_417Hz; + break; + case ASM330LHHXG1_GY_ODR_833Hz: + *val = ASM330LHHXG1_GY_ODR_833Hz; + break; + case ASM330LHHXG1_GY_ODR_1667Hz: + *val = ASM330LHHXG1_GY_ODR_1667Hz; + break; + case ASM330LHHXG1_GY_ODR_3333Hz: + *val = ASM330LHHXG1_GY_ODR_3333Hz; + break; + case ASM330LHHXG1_GY_ODR_6667Hz: + *val = ASM330LHHXG1_GY_ODR_6667Hz; + break; + default: + *val = ASM330LHHXG1_GY_ODR_OFF; + break; + } + return ret; +} + +/** + * @brief Block data update.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of bdu in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret == 0) + { + ctrl3_c.bdu = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Block data update.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of bdu in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + *val = ctrl3_c.bdu; + + return ret; +} + +/** + * @brief Weight of XL user offset bits of registers X_OFS_USR (73h), + * Y_OFS_USR (74h), Z_OFS_USR (75h).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of usr_off_w in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_offset_weight_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_usr_off_w_t val) +{ + asm330lhhxg1_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret == 0) + { + ctrl6_c.usr_off_w = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + } + return ret; +} + +/** + * @brief Weight of XL user offset bits of registers X_OFS_USR (73h), + * Y_OFS_USR (74h), Z_OFS_USR (75h).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of usr_off_w in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_offset_weight_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_usr_off_w_t *val) +{ + asm330lhhxg1_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + + switch (ctrl6_c.usr_off_w) + { + case ASM330LHHXG1_LSb_1mg: + *val = ASM330LHHXG1_LSb_1mg; + break; + case ASM330LHHXG1_LSb_16mg: + *val = ASM330LHHXG1_LSb_16mg; + break; + default: + *val = ASM330LHHXG1_LSb_1mg; + break; + } + return ret; +} + +/** + * @brief Accelerometer power mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of xl_hm_mode in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_power_mode_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_xl_hm_mode_t val) +{ + asm330lhhxg1_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret == 0) + { + ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + } + return ret; +} + +/** + * @brief Accelerometer power mode[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of xl_hm_mode in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_power_mode_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_xl_hm_mode_t *val) +{ + asm330lhhxg1_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + switch (ctrl6_c.xl_hm_mode) + { + case ASM330LHHXG1_HIGH_PERFORMANCE_MD: + *val = ASM330LHHXG1_HIGH_PERFORMANCE_MD; + break; + case ASM330LHHXG1_LOW_NORMAL_POWER_MD: + *val = ASM330LHHXG1_LOW_NORMAL_POWER_MD; + break; + default: + *val = ASM330LHHXG1_HIGH_PERFORMANCE_MD; + break; + } + return ret; +} + +/** + * @brief Operating mode for gyroscope.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of g_hm_mode in reg CTRL7_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_gy_power_mode_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_g_hm_mode_t val) +{ + asm330lhhxg1_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret == 0) + { + ctrl7_g.g_hm_mode = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + } + return ret; +} + +/** + * @brief gy_power_mode: [get] Operating mode for gyroscope. + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of g_hm_mode in reg CTRL7_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_gy_power_mode_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_g_hm_mode_t *val) +{ + asm330lhhxg1_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + switch (ctrl7_g.g_hm_mode) + { + case ASM330LHHXG1_GY_HIGH_PERFORMANCE: + *val = ASM330LHHXG1_GY_HIGH_PERFORMANCE; + break; + case ASM330LHHXG1_GY_NORMAL: + *val = ASM330LHHXG1_GY_NORMAL; + break; + default: + *val = ASM330LHHXG1_GY_HIGH_PERFORMANCE; + break; + } + return ret; +} + +/** + * @brief Read all the interrupt flag of the device. + *[get] + * @param ctx Read / write interface definitions.(ptr) + * @param val Get registers ALL_INT_SRC; WAKE_UP_SRC; + * TAP_SRC; D6D_SRC; STATUS_REG; + * EMB_FUNC_STATUS; FSM_STATUS_A/B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_all_sources_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_all_sources_t *val) +{ + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_ALL_INT_SRC, + (uint8_t *)&val->all_int_src, 1); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_SRC, + (uint8_t *)&val->wake_up_src, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_D6D_SRC, + (uint8_t *)&val->d6d_src, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_STATUS_REG, + (uint8_t *)&val->status_reg, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_STATUS, + (uint8_t *)&val->emb_func_status, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_STATUS_A, + (uint8_t *)&val->fsm_status_a, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_STATUS_B, + (uint8_t *)&val->fsm_status_b, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MLC_STATUS, + (uint8_t *)&val->mlc_status, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + + return ret; +} + +/** + * @brief The STATUS_REG register is read by the primary interface.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get register STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_status_reg_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_status_reg_t *val) +{ + int32_t ret; + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_STATUS_REG, (uint8_t *) val, 1); + return ret; +} + +/** + * @brief Accelerometer new data available.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of xlda in reg STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_status_reg_t status_reg; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_STATUS_REG, + (uint8_t *)&status_reg, 1); + *val = status_reg.xlda; + + return ret; +} + +/** + * @brief Gyroscope new data available.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of gda in reg STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_status_reg_t status_reg; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_STATUS_REG, + (uint8_t *)&status_reg, 1); + *val = status_reg.gda; + + return ret; +} + +/** + * @brief Temperature new data available.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of tda in reg STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_status_reg_t status_reg; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_STATUS_REG, + (uint8_t *)&status_reg, 1); + *val = status_reg.tda; + + return ret; +} + +/** + * @brief Accelerometer X-axis user offset correction expressed in two’s + * complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * The value must be in the range [-127 127].[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_X_OFS_USR, buff, 1); + return ret; +} + +/** + * @brief Accelerometer X-axis user offset correction expressed in two’s + * complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * The value must be in the range [-127 127].[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_X_OFS_USR, buff, 1); + return ret; +} + +/** + * @brief Accelerometer Y-axis user offset correction expressed in two’s + * complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * The value must be in the range [-127 127].[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_Y_OFS_USR, buff, 1); + return ret; +} + +/** + * @brief Accelerometer Y-axis user offset correction expressed in two’s + * complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * The value must be in the range [-127 127].[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_Y_OFS_USR, buff, 1); + return ret; +} + +/** + * @brief Accelerometer Z-axis user offset correction expressed in two’s + * complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * The value must be in the range [-127 127].[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_Z_OFS_USR, buff, 1); + return ret; +} + +/** + * @brief Accelerometer X-axis user offset correction expressed in two’s + * complement, weight depends on USR_OFF_W in CTRL6_C (15h). + * The value must be in the range [-127 127].[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_Z_OFS_USR, buff, 1); + return ret; +} + +/** + * @brief Enables user offset on out.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of usr_off_on_out in reg CTRL7_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret == 0) + { + ctrl7_g.usr_off_on_out = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + } + return ret; +} + +/** + * @brief Get user offset on out flag.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get values of usr_off_on_out in reg CTRL7_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + *val = ctrl7_g.usr_off_on_out; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHHXG1_Timestamp + * @brief This section groups all the functions that manage the + * timestamp generation. + * @{ + * + */ + +/** + * @brief Reset timestamp counter.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_timestamp_rst(const stmdev_ctx_t *ctx) +{ + uint8_t rst_val = 0xAA; + + return asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_TIMESTAMP2, &rst_val, 1); +} + +/** + * @brief Enables timestamp counter.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of timestamp_en in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + if (ret == 0) + { + ctrl10_c.timestamp_en = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL10_C, + (uint8_t *)&ctrl10_c, 1); + } + return ret; +} + +/** + * @brief Enables timestamp counter.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of timestamp_en in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL10_C, (uint8_t *)&ctrl10_c, 1); + *val = ctrl10_c.timestamp_en; + + return ret; +} + +/** + * @brief Timestamp first data output register (r). + * The value is expressed as a 32-bit word and the bit resolution + * is 25 μs.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) +{ + uint8_t buff[4]; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_TIMESTAMP0, buff, 4); + *val = buff[3]; + *val = (*val * 256U) + buff[2]; + *val = (*val * 256U) + buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHHXG1_Data output + * @brief This section groups all the data output functions. + * @{ + * + */ + +/** + * @brief Circular burst-mode (rounding) read of the output registers.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of rounding in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_rounding_mode_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_rounding_t val) +{ + asm330lhhxg1_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret == 0) + { + ctrl5_c.rounding = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + } + return ret; +} + +/** + * @brief Gyroscope UI chain full-scale selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of rounding in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_rounding_mode_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_rounding_t *val) +{ + asm330lhhxg1_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + switch (ctrl5_c.rounding) + { + case ASM330LHHXG1_NO_ROUND: + *val = ASM330LHHXG1_NO_ROUND; + break; + case ASM330LHHXG1_ROUND_XL: + *val = ASM330LHHXG1_ROUND_XL; + break; + case ASM330LHHXG1_ROUND_GY: + *val = ASM330LHHXG1_ROUND_GY; + break; + case ASM330LHHXG1_ROUND_GY_XL: + *val = ASM330LHHXG1_ROUND_GY_XL; + break; + default: + *val = ASM330LHHXG1_NO_ROUND; + break; + } + return ret; +} + +/** + * @brief Temperature data output register (r). + * L and H registers together express a 16-bit word in two’s + * complement.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_OUT_TEMP_L, buff, 2); + *val = (int16_t)buff[1]; + *val = (*val * 256) + (int16_t)buff[0]; + + return ret; +} + +/** + * @brief Angular rate sensor. The value is expressed as a 16-bit + * word in two’s complement.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_OUTX_L_G, buff, 6); + + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Linear acceleration output register. The value is expressed as a + * 16-bit word in two’s complement.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_OUTX_L_A, buff, 6); + + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief FIFO data output.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + int32_t ret; + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_DATA_OUT_X_L, val, 6); + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHHXG1_common + * @brief This section groups common useful functions. + * @{ + * + */ + +/** + * @brief Difference in percentage of the effective ODR (and timestamp rate) + * with respect to the typical.[set] + * Step: 0.15%. 8-bit format, 2's complement. + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_internal_freq_fine_t internal_freq_fine; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INTERNAL_FREQ_FINE, + (uint8_t *)&internal_freq_fine, 1); + if (ret == 0) + { + internal_freq_fine.freq_fine = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_INTERNAL_FREQ_FINE, + (uint8_t *)&internal_freq_fine, 1); + } + return ret; +} + +/** + * @brief Difference in percentage of the effective ODR (and timestamp rate) + * with respect to the typical.[get] + * Step: 0.15%. 8-bit format, 2's complement. + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_internal_freq_fine_t internal_freq_fine; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INTERNAL_FREQ_FINE, + (uint8_t *)&internal_freq_fine, 1); + *val = internal_freq_fine.freq_fine; + + return ret; +} + +/** + * @brief Enable access to the embedded functions/sensor hub configuration + * registers.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of reg_access in reg FUNC_CFG_ACCESS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_mem_bank_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_reg_access_t val) +{ + asm330lhhxg1_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FUNC_CFG_ACCESS, + (uint8_t *)&func_cfg_access, 1); + if (ret == 0) + { + func_cfg_access.reg_access = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FUNC_CFG_ACCESS, + (uint8_t *)&func_cfg_access, 1); + } + return ret; +} + +/** + * @brief Enable access to the embedded functions/sensor hub configuration + * registers.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of reg_access in reg FUNC_CFG_ACCESS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_mem_bank_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_reg_access_t *val) +{ + asm330lhhxg1_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FUNC_CFG_ACCESS, + (uint8_t *)&func_cfg_access, 1); + switch (func_cfg_access.reg_access) + { + case ASM330LHHXG1_USER_BANK: + *val = ASM330LHHXG1_USER_BANK; + break; + case ASM330LHHXG1_SENSOR_HUB_BANK: + *val = ASM330LHHXG1_SENSOR_HUB_BANK; + break; + case ASM330LHHXG1_EMBEDDED_FUNC_BANK: + *val = ASM330LHHXG1_EMBEDDED_FUNC_BANK; + break; + default: + *val = ASM330LHHXG1_USER_BANK; + break; + } + return ret; +} + +/** + * @brief Write a line(byte) in a page.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param add Page line address + * @param val Value to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t add, + uint8_t *val) +{ + asm330lhhxg1_page_rw_t page_rw; + asm330lhhxg1_page_sel_t page_sel; + asm330lhhxg1_page_address_t page_address; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + page_rw.page_rw = 0x02U; /* page_write enable */ + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_SEL, (uint8_t *)&page_sel, 1); + } + if (ret == 0) + { + page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); + page_sel.not_used_01 = 1; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + } + if (ret == 0) + { + page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_VALUE, val, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + page_rw.page_rw = 0x00; /* page_write disable */ + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Write buffer in a page.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buf Page line address.(ptr) + * @param val Value to write. + * @param len buffer lenght. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t add, + uint8_t *buf, uint8_t len) +{ + asm330lhhxg1_page_rw_t page_rw; + asm330lhhxg1_page_sel_t page_sel; + asm330lhhxg1_page_address_t page_address; + int32_t ret; + uint8_t msb, lsb; + uint8_t i ; + + msb = (uint8_t)(add / 256U); + lsb = (uint8_t)(add - (msb * 256U)); + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + page_rw.page_rw = 0x02U; /* page_write enable*/ + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_SEL, (uint8_t *)&page_sel, 1); + } + if (ret == 0) + { + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + } + if (ret == 0) + { + page_address.page_addr = lsb; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + } + for (i = 0; i < len; i++) + { + if (ret == 0) + { + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_VALUE, &buf[i], 1); + if (ret == 0) + { + /* Check if page wrap */ + if (lsb == 0x00U) + { + msb++; + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + } + lsb++; + } + if (ret == 0) + { + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + } + } + } + + if (ret == 0) + { + page_sel.page_sel = 0; + page_sel.not_used_01 = 1; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + page_rw.page_rw = 0x00U; /* page_write disable */ + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Read a line(byte) in a page.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param add Page line address. + * @param val Read value.(ptr) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, + uint8_t *val) +{ + asm330lhhxg1_page_rw_t page_rw; + asm330lhhxg1_page_sel_t page_sel; + asm330lhhxg1_page_address_t page_address; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + page_rw.page_rw = 0x01U; /* page_read enable*/ + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_SEL, (uint8_t *)&page_sel, 1); + } + if (ret == 0) + { + page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU); + page_sel.not_used_01 = 1; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + } + if (ret == 0) + { + page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U)); + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_VALUE, val, 2); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + page_rw.page_rw = 0x00U; /* page_read disable */ + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Data-ready pulsed / letched mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of dataready_pulsed in + * reg COUNTER_BDR_REG1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_data_ready_mode_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_dataready_pulsed_t val) +{ + asm330lhhxg1_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + if (ret == 0) + { + counter_bdr_reg1.dataready_pulsed = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + } + return ret; +} + +/** + * @brief Data-ready pulsed / letched mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of dataready_pulsed in + * reg COUNTER_BDR_REG1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_data_ready_mode_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_dataready_pulsed_t *val) +{ + asm330lhhxg1_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + switch (counter_bdr_reg1.dataready_pulsed) + { + case ASM330LHHXG1_DRDY_LATCHED: + *val = ASM330LHHXG1_DRDY_LATCHED; + break; + case ASM330LHHXG1_DRDY_PULSED: + *val = ASM330LHHXG1_DRDY_PULSED; + break; + default: + *val = ASM330LHHXG1_DRDY_LATCHED; + break; + } + return ret; +} + +/** + * @brief Device Who am I.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WHO_AM_I, buff, 1); + return ret; +} + +/** + * @brief Software reset. Restore the default values in user registers.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sw_reset in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_reset_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret == 0) + { + ctrl3_c.sw_reset = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Software reset. Restore the default values in user registers.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sw_reset in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + *val = ctrl3_c.sw_reset; + + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte + * access with a serial interface.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of if_inc in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret == 0) + { + ctrl3_c.if_inc = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte + * access with a serial interface.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of if_inc in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + *val = ctrl3_c.if_inc; + + return ret; +} + +/** + * @brief Reboot memory content. Reload the calibration parameters.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of boot in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_boot_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret == 0) + { + ctrl3_c.boot = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Reboot memory content. Reload the calibration parameters.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of boot in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + *val = ctrl3_c.boot; + + return ret; +} + + + +/** + * @brief Linear acceleration sensor self-test enable.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of st_xl in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_self_test_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_st_xl_t val) +{ + asm330lhhxg1_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret == 0) + { + ctrl5_c.st_xl = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + } + return ret; +} + +/** + * @brief Linear acceleration sensor self-test enable.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of st_xl in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_self_test_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_st_xl_t *val) +{ + asm330lhhxg1_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + + switch (ctrl5_c.st_xl) + { + case ASM330LHHXG1_XL_ST_DISABLE: + *val = ASM330LHHXG1_XL_ST_DISABLE; + break; + case ASM330LHHXG1_XL_ST_POSITIVE: + *val = ASM330LHHXG1_XL_ST_POSITIVE; + break; + case ASM330LHHXG1_XL_ST_NEGATIVE: + *val = ASM330LHHXG1_XL_ST_NEGATIVE; + break; + default: + *val = ASM330LHHXG1_XL_ST_DISABLE; + break; + } + return ret; +} + +/** + * @brief Angular rate sensor self-test enable.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of st_g in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_gy_self_test_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_st_g_t val) +{ + asm330lhhxg1_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + if (ret == 0) + { + ctrl5_c.st_g = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + } + return ret; +} + +/** + * @brief Angular rate sensor self-test enable.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of st_g in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_gy_self_test_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_st_g_t *val) +{ + asm330lhhxg1_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1); + + switch (ctrl5_c.st_g) + { + case ASM330LHHXG1_GY_ST_DISABLE: + *val = ASM330LHHXG1_GY_ST_DISABLE; + break; + case ASM330LHHXG1_GY_ST_POSITIVE: + *val = ASM330LHHXG1_GY_ST_POSITIVE; + break; + case ASM330LHHXG1_GY_ST_NEGATIVE: + *val = ASM330LHHXG1_GY_ST_NEGATIVE; + break; + default: + *val = ASM330LHHXG1_GY_ST_DISABLE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHHXG1_filters + * @brief This section group all the functions concerning the + * filters configuration + * @{ + * + */ + +/** + * @brief Accelerometer output from LPF2 filtering stage selection.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of lpf2_xl_en in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + if (ret == 0) + { + ctrl1_xl.lpf2_xl_en = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL1_XL, + (uint8_t *)&ctrl1_xl, 1); + } + return ret; +} + +/** + * @brief Accelerometer output from LPF2 filtering stage selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of lpf2_xl_en in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); + *val = ctrl1_xl.lpf2_xl_en; + + return ret; +} + +/** + * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled; + * the bandwidth can be selected through FTYPE [2:0] in CTRL6_C.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of lpf1_sel_g in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret == 0) + { + ctrl4_c.lpf1_sel_g = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + } + return ret; +} + +/** + * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled; + * the bandwidth can be selected through FTYPE [2:0] in CTRL6_C.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of lpf1_sel_g in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + *val = ctrl4_c.lpf1_sel_g; + + return ret; +} + +/** + * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends + * (XL and Gyro independently masked).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of drdy_mask in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret == 0) + { + ctrl4_c.drdy_mask = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + } + return ret; +} + +/** + * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends + * (XL and Gyro independently masked).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of drdy_mask in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_filter_settling_mask_get(const stmdev_ctx_t *ctx, + uint8_t *val) +{ + asm330lhhxg1_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + *val = ctrl4_c.drdy_mask; + + return ret; +} + +/** + * @brief Gyroscope low pass filter 1 bandwidth.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of ftype in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_ftype_t val) +{ + asm330lhhxg1_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret == 0) + { + ctrl6_c.ftype = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + } + return ret; +} + +/** + * @brief Gyroscope low pass filter 1 bandwidth.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of ftype in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_ftype_t *val) +{ + asm330lhhxg1_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + + switch (ctrl6_c.ftype) + { + case ASM330LHHXG1_ULTRA_LIGHT: + *val = ASM330LHHXG1_ULTRA_LIGHT; + break; + case ASM330LHHXG1_VERY_LIGHT: + *val = ASM330LHHXG1_VERY_LIGHT; + break; + case ASM330LHHXG1_LIGHT: + *val = ASM330LHHXG1_LIGHT; + break; + case ASM330LHHXG1_MEDIUM: + *val = ASM330LHHXG1_MEDIUM; + break; + case ASM330LHHXG1_STRONG: + *val = ASM330LHHXG1_STRONG; + break; + case ASM330LHHXG1_VERY_STRONG: + *val = ASM330LHHXG1_VERY_STRONG; + break; + case ASM330LHHXG1_AGGRESSIVE: + *val = ASM330LHHXG1_AGGRESSIVE; + break; + case ASM330LHHXG1_XTREME: + *val = ASM330LHHXG1_XTREME; + break; + default: + *val = ASM330LHHXG1_ULTRA_LIGHT; + break; + } + return ret; +} + +/** + * @brief Low pass filter 2 on 6D function selection.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of low_pass_on_6d in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret == 0) + { + ctrl8_xl.low_pass_on_6d = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL8_XL, + (uint8_t *)&ctrl8_xl, 1); + } + return ret; +} + +/** + * @brief Low pass filter 2 on 6D function selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of low_pass_on_6d in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + *val = ctrl8_xl.low_pass_on_6d; + + return ret; +} + +/** + * @brief Accelerometer slope filter / high-pass filter selection + * on output.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of hp_slope_xl_en in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_hp_slope_xl_en_t val) +{ + asm330lhhxg1_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret == 0) + { + ctrl8_xl.hp_slope_xl_en = (((uint8_t)val & 0x10U) >> 4); + ctrl8_xl.hp_ref_mode_xl = (((uint8_t)val & 0x20U) >> 5); + ctrl8_xl.hpcf_xl = (uint8_t)val & 0x07U; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL8_XL, + (uint8_t *)&ctrl8_xl, 1); + } + return ret; +} + +/** + * @brief Accelerometer slope filter / high-pass filter selection on + * output.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of hp_slope_xl_en in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_hp_slope_xl_en_t *val) +{ + asm330lhhxg1_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + switch (((ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.hp_slope_xl_en << 4) + + ctrl8_xl.hpcf_xl)) + { + case ASM330LHHXG1_HP_PATH_DISABLE_ON_OUT: + *val = ASM330LHHXG1_HP_PATH_DISABLE_ON_OUT; + break; + case ASM330LHHXG1_SLOPE_ODR_DIV_4: + *val = ASM330LHHXG1_SLOPE_ODR_DIV_4; + break; + case ASM330LHHXG1_HP_ODR_DIV_10: + *val = ASM330LHHXG1_HP_ODR_DIV_10; + break; + case ASM330LHHXG1_HP_ODR_DIV_20: + *val = ASM330LHHXG1_HP_ODR_DIV_20; + break; + case ASM330LHHXG1_HP_ODR_DIV_45: + *val = ASM330LHHXG1_HP_ODR_DIV_45; + break; + case ASM330LHHXG1_HP_ODR_DIV_100: + *val = ASM330LHHXG1_HP_ODR_DIV_100; + break; + case ASM330LHHXG1_HP_ODR_DIV_200: + *val = ASM330LHHXG1_HP_ODR_DIV_200; + break; + case ASM330LHHXG1_HP_ODR_DIV_400: + *val = ASM330LHHXG1_HP_ODR_DIV_400; + break; + case ASM330LHHXG1_HP_ODR_DIV_800: + *val = ASM330LHHXG1_HP_ODR_DIV_800; + break; + case ASM330LHHXG1_HP_REF_MD_ODR_DIV_10: + *val = ASM330LHHXG1_HP_REF_MD_ODR_DIV_10; + break; + case ASM330LHHXG1_HP_REF_MD_ODR_DIV_20: + *val = ASM330LHHXG1_HP_REF_MD_ODR_DIV_20; + break; + case ASM330LHHXG1_HP_REF_MD_ODR_DIV_45: + *val = ASM330LHHXG1_HP_REF_MD_ODR_DIV_45; + break; + case ASM330LHHXG1_HP_REF_MD_ODR_DIV_100: + *val = ASM330LHHXG1_HP_REF_MD_ODR_DIV_100; + break; + case ASM330LHHXG1_HP_REF_MD_ODR_DIV_200: + *val = ASM330LHHXG1_HP_REF_MD_ODR_DIV_200; + break; + case ASM330LHHXG1_HP_REF_MD_ODR_DIV_400: + *val = ASM330LHHXG1_HP_REF_MD_ODR_DIV_400; + break; + case ASM330LHHXG1_HP_REF_MD_ODR_DIV_800: + *val = ASM330LHHXG1_HP_REF_MD_ODR_DIV_800; + break; + case ASM330LHHXG1_LP_ODR_DIV_10: + *val = ASM330LHHXG1_LP_ODR_DIV_10; + break; + case ASM330LHHXG1_LP_ODR_DIV_20: + *val = ASM330LHHXG1_LP_ODR_DIV_20; + break; + case ASM330LHHXG1_LP_ODR_DIV_45: + *val = ASM330LHHXG1_LP_ODR_DIV_45; + break; + case ASM330LHHXG1_LP_ODR_DIV_100: + *val = ASM330LHHXG1_LP_ODR_DIV_100; + break; + case ASM330LHHXG1_LP_ODR_DIV_200: + *val = ASM330LHHXG1_LP_ODR_DIV_200; + break; + case ASM330LHHXG1_LP_ODR_DIV_400: + *val = ASM330LHHXG1_LP_ODR_DIV_400; + break; + case ASM330LHHXG1_LP_ODR_DIV_800: + *val = ASM330LHHXG1_LP_ODR_DIV_800; + break; + default: + *val = ASM330LHHXG1_HP_PATH_DISABLE_ON_OUT; + break; + } + return ret; +} + +/** + * @brief Enables accelerometer LPF2 and HPF fast-settling mode. + * The filter sets the second samples after writing this bit. + * Active only during device exit from powerdown mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fastsettl_mode_xl in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + if (ret == 0) + { + ctrl8_xl.fastsettl_mode_xl = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL8_XL, + (uint8_t *)&ctrl8_xl, 1); + } + return ret; +} + +/** + * @brief Enables accelerometer LPF2 and HPF fast-settling mode. + * The filter sets the second samples after writing + * this bit. Active only during device exit from powerdown mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fastsettl_mode_xl in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); + *val = ctrl8_xl.fastsettl_mode_xl; + + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity + * functions.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of slope_fds in reg INT_CFG0 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_slope_fds_t val) +{ + asm330lhhxg1_int_cfg0_t int_cfg0; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INT_CFG0, (uint8_t *)&int_cfg0, 1); + if (ret == 0) + { + int_cfg0.slope_fds = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_INT_CFG0, + (uint8_t *)&int_cfg0, 1); + } + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity + * functions.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of slope_fds in reg INT_CFG0 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_slope_fds_t *val) +{ + asm330lhhxg1_int_cfg0_t int_cfg0; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INT_CFG0, (uint8_t *)&int_cfg0, 1); + switch (int_cfg0.slope_fds) + { + case ASM330LHHXG1_USE_SLOPE: + *val = ASM330LHHXG1_USE_SLOPE; + break; + case ASM330LHHXG1_USE_HPF: + *val = ASM330LHHXG1_USE_HPF; + break; + default: + *val = ASM330LHHXG1_USE_SLOPE; + break; + } + return ret; +} + +/** + * @brief Enables gyroscope digital high-pass filter. The filter is enabled + * only if the gyro is in HP mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_hpm_g_t val) +{ + asm330lhhxg1_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + if (ret == 0) + { + ctrl7_g.hp_en_g = (((uint8_t)val & 0x80U) >> 7); + ctrl7_g.hpm_g = (uint8_t)val & 0x03U; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + } + return ret; +} + +/** + * @brief Enables gyroscope digital high-pass filter. The filter is + * enabled only if the gyro is in HP mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_hpm_g_t *val) +{ + asm330lhhxg1_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1); + + switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g) + { + case ASM330LHHXG1_HP_FILTER_NONE: + *val = ASM330LHHXG1_HP_FILTER_NONE; + break; + case ASM330LHHXG1_HP_FILTER_16mHz: + *val = ASM330LHHXG1_HP_FILTER_16mHz; + break; + case ASM330LHHXG1_HP_FILTER_65mHz: + *val = ASM330LHHXG1_HP_FILTER_65mHz; + break; + case ASM330LHHXG1_HP_FILTER_260mHz: + *val = ASM330LHHXG1_HP_FILTER_260mHz; + break; + case ASM330LHHXG1_HP_FILTER_1Hz04: + *val = ASM330LHHXG1_HP_FILTER_1Hz04; + break; + default: + *val = ASM330LHHXG1_HP_FILTER_NONE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHHXG1_ serial_interface + * @brief This section groups all the functions concerning main + * serial interface management (not auxiliary) + * @{ + * + */ + +/** + * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sdo_pu_en in reg PIN_CTRL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_sdo_pu_en_t val) +{ + asm330lhhxg1_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret == 0) + { + pin_ctrl.sdo_pu_en = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + return ret; +} + +/** + * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of sdo_pu_en in reg PIN_CTRL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_sdo_pu_en_t *val) +{ + asm330lhhxg1_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + + switch (pin_ctrl.sdo_pu_en) + { + case ASM330LHHXG1_PULL_UP_DISC: + *val = ASM330LHHXG1_PULL_UP_DISC; + break; + case ASM330LHHXG1_PULL_UP_CONNECT: + *val = ASM330LHHXG1_PULL_UP_CONNECT; + break; + default: + *val = ASM330LHHXG1_PULL_UP_DISC; + break; + } + return ret; +} + +/** + * @brief Connect/Disconnect INT1 pull-down.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of pd_dis_int1 in reg I3C_BUS_AVB + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_int1_mode_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_pd_dis_int1_t val) +{ + asm330lhhxg1_i3c_bus_avb_t i3c_bus_avb; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_I3C_BUS_AVB, (uint8_t *)&i3c_bus_avb, 1); + if (ret == 0) + { + i3c_bus_avb.pd_dis_int1 = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_I3C_BUS_AVB, + (uint8_t *)&i3c_bus_avb, 1); + } + return ret; +} + +/** + * @brief Connect/Disconnect INT1 pull-down.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of pd_dis_int1 in reg I3C_BUS_AVB + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_int1_mode_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_pd_dis_int1_t *val) +{ + asm330lhhxg1_i3c_bus_avb_t i3c_bus_avb; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_I3C_BUS_AVB, (uint8_t *)&i3c_bus_avb, 1); + + switch (i3c_bus_avb.pd_dis_int1) + { + case ASM330LHHXG1_PULL_DOWN_CONNECT: + *val = ASM330LHHXG1_PULL_DOWN_CONNECT; + break; + case ASM330LHHXG1_PULL_DOWN_DISC: + *val = ASM330LHHXG1_PULL_DOWN_DISC; + break; + default: + *val = ASM330LHHXG1_PULL_DOWN_CONNECT; + break; + } + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sim in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_spi_mode_set(const stmdev_ctx_t *ctx, asm330lhhxg1_sim_t val) +{ + asm330lhhxg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret == 0) + { + ctrl3_c.sim = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of sim in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_spi_mode_get(const stmdev_ctx_t *ctx, asm330lhhxg1_sim_t *val) +{ + asm330lhhxg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + switch (ctrl3_c.sim) + { + case ASM330LHHXG1_SPI_4_WIRE: + *val = ASM330LHHXG1_SPI_4_WIRE; + break; + case ASM330LHHXG1_SPI_3_WIRE: + *val = ASM330LHHXG1_SPI_3_WIRE; + break; + default: + *val = ASM330LHHXG1_SPI_4_WIRE; + break; + } + return ret; +} + +/** + * @brief Disable / Enable I2C interface.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of i2c_disable in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_i2c_interface_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_i2c_disable_t val) +{ + asm330lhhxg1_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret == 0) + { + ctrl4_c.i2c_disable = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + } + return ret; +} + +/** + * @brief Disable / Enable I2C interface.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of i2c reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_i2c_interface_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_i2c_disable_t *val) +{ + asm330lhhxg1_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + + switch (ctrl4_c.i2c_disable) + { + case ASM330LHHXG1_I2C_ENABLE: + *val = ASM330LHHXG1_I2C_ENABLE; + break; + case ASM330LHHXG1_I2C_DISABLE: + *val = ASM330LHHXG1_I2C_DISABLE; + break; + default: + *val = ASM330LHHXG1_I2C_ENABLE; + break; + } + return ret; +} + +/** + * @brief I3C Enable/Disable communication protocol.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of i3c_disable in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_i3c_disable_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_i3c_disable_t val) +{ + asm330lhhxg1_ctrl9_xl_t ctrl9_xl; + asm330lhhxg1_i3c_bus_avb_t i3c_bus_avb; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret == 0) + { + ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL9_XL, + (uint8_t *)&ctrl9_xl, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_I3C_BUS_AVB, + (uint8_t *)&i3c_bus_avb, 1); + } + if (ret == 0) + { + i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_I3C_BUS_AVB, + (uint8_t *)&i3c_bus_avb, 1); + } + return ret; +} + +/** + * @brief I3C Enable/Disable communication protocol.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of i3c_disable in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_i3c_disable_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_i3c_disable_t *val) +{ + asm330lhhxg1_ctrl9_xl_t ctrl9_xl; + asm330lhhxg1_i3c_bus_avb_t i3c_bus_avb; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_I3C_BUS_AVB, + (uint8_t *)&i3c_bus_avb, 1); + } + switch ((ctrl9_xl.i3c_disable << 7) + i3c_bus_avb.i3c_bus_avb_sel) + { + case ASM330LHHXG1_I3C_DISABLE: + *val = ASM330LHHXG1_I3C_DISABLE; + break; + case ASM330LHHXG1_I3C_ENABLE_T_50us: + *val = ASM330LHHXG1_I3C_ENABLE_T_50us; + break; + case ASM330LHHXG1_I3C_ENABLE_T_2us: + *val = ASM330LHHXG1_I3C_ENABLE_T_2us; + break; + case ASM330LHHXG1_I3C_ENABLE_T_1ms: + *val = ASM330LHHXG1_I3C_ENABLE_T_1ms; + break; + case ASM330LHHXG1_I3C_ENABLE_T_25ms: + *val = ASM330LHHXG1_I3C_ENABLE_T_25ms; + break; + default: + *val = ASM330LHHXG1_I3C_DISABLE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHHXG1_interrupt_pins + * @brief This section groups all the functions that manage + * interrupt pins + * @{ + * + */ + +/** + * @brief Select the signal that need to route on int1 pad.[set] + * + * @param ctx read / write interface definitions + * @param val struct of registers: INT1_CTRL, + * MD1_CFG, EMB_FUNC_INT1, FSM_INT1_A, + * FSM_INT1_B + * + */ +int32_t asm330lhhxg1_pin_int1_route_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_pin_int1_route_t *val) +{ + asm330lhhxg1_pin_int2_route_t pin_int2_route; + asm330lhhxg1_int_cfg1_t int_cfg1; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MLC_INT1, + (uint8_t *)&val->mlc_int1, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_INT1, + (uint8_t *)&val->emb_func_int1, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FSM_INT1_A, + (uint8_t *)&val->fsm_int1_a, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FSM_INT1_B, + (uint8_t *)&val->fsm_int1_b, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + + if (ret == 0) + { + if ((val->emb_func_int1.int1_fsm_lc + | val->fsm_int1_a.int1_fsm1 + | val->fsm_int1_a.int1_fsm2 + | val->fsm_int1_a.int1_fsm3 + | val->fsm_int1_a.int1_fsm4 + | val->fsm_int1_a.int1_fsm5 + | val->fsm_int1_a.int1_fsm6 + | val->fsm_int1_a.int1_fsm7 + | val->fsm_int1_a.int1_fsm8 + | val->fsm_int1_b.int1_fsm9 + | val->fsm_int1_b.int1_fsm10 + | val->fsm_int1_b.int1_fsm11 + | val->fsm_int1_b.int1_fsm12 + | val->fsm_int1_b.int1_fsm13 + | val->fsm_int1_b.int1_fsm14 + | val->fsm_int1_b.int1_fsm15 + | val->fsm_int1_b.int1_fsm16 + | val->mlc_int1.int1_mlc1 + | val->mlc_int1.int1_mlc2 + | val->mlc_int1.int1_mlc3 + | val->mlc_int1.int1_mlc4 + | val->mlc_int1.int1_mlc5 + | val->mlc_int1.int1_mlc6 + | val->mlc_int1.int1_mlc7 + | val->mlc_int1.int1_mlc8) != PROPERTY_DISABLE) + { + val->md1_cfg.int1_emb_func = PROPERTY_ENABLE; + } + else + { + val->md1_cfg.int1_emb_func = PROPERTY_DISABLE; + } + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_INT1_CTRL, + (uint8_t *)&val->int1_ctrl, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MD1_CFG, (uint8_t *)&val->md1_cfg, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INT_CFG1, (uint8_t *) &int_cfg1, 1); + } + + if (ret == 0) + { + ret = asm330lhhxg1_pin_int2_route_get(ctx, &pin_int2_route); + } + if (ret == 0) + { + if ((pin_int2_route.int2_ctrl.int2_cnt_bdr + | pin_int2_route.int2_ctrl.int2_drdy_g + | pin_int2_route.int2_ctrl.int2_drdy_temp + | pin_int2_route.int2_ctrl.int2_drdy_xl + | pin_int2_route.int2_ctrl.int2_fifo_full + | pin_int2_route.int2_ctrl.int2_fifo_ovr + | pin_int2_route.int2_ctrl.int2_fifo_th + | pin_int2_route.md2_cfg.int2_6d + | pin_int2_route.md2_cfg.int2_ff + | pin_int2_route.md2_cfg.int2_wu + | pin_int2_route.md2_cfg.int2_sleep_change + | val->int1_ctrl.den_drdy_flag + | val->int1_ctrl.int1_boot + | val->int1_ctrl.int1_cnt_bdr + | val->int1_ctrl.int1_drdy_g + | val->int1_ctrl.int1_drdy_xl + | val->int1_ctrl.int1_fifo_full + | val->int1_ctrl.int1_fifo_ovr + | val->int1_ctrl.int1_fifo_th + | val->md1_cfg.int1_shub + | val->md1_cfg.int1_6d + | val->md1_cfg.int1_ff + | val->md1_cfg.int1_wu + | val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE) + { + int_cfg1.interrupts_enable = PROPERTY_ENABLE; + } + else + { + int_cfg1.interrupts_enable = PROPERTY_DISABLE; + } + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_INT_CFG1, (uint8_t *) &int_cfg1, 1); + } + return ret; +} + +/** + * @brief Select the signal that need to route on int1 pad.[get] + * + * @param ctx read / write interface definitions + * @param val struct of registers: INT1_CTRL, MD1_CFG, + * EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B + * + */ +int32_t asm330lhhxg1_pin_int1_route_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_pin_int1_route_t *val) +{ + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MLC_INT1, + (uint8_t *)&val->mlc_int1, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_INT1, + (uint8_t *)&val->emb_func_int1, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_INT1_A, + (uint8_t *)&val->fsm_int1_a, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_INT1_B, + (uint8_t *)&val->fsm_int1_b, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + if (ret == 0) + { + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INT1_CTRL, + (uint8_t *)&val->int1_ctrl, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MD1_CFG, (uint8_t *)&val->md1_cfg, 1); + } + + return ret; +} + +/** + * @brief Select the signal that need to route on int2 pad.[set] + * + * @param ctx read / write interface definitions + * @param val union of registers INT2_CTRL, MD2_CFG, + * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B + * + */ +int32_t asm330lhhxg1_pin_int2_route_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_pin_int2_route_t *val) +{ + asm330lhhxg1_pin_int1_route_t pin_int1_route; + asm330lhhxg1_int_cfg1_t int_cfg1; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MLC_INT2, + (uint8_t *)&val->mlc_int2, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_INT2, + (uint8_t *)&val->emb_func_int2, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FSM_INT2_A, + (uint8_t *)&val->fsm_int2_a, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FSM_INT2_B, + (uint8_t *)&val->fsm_int2_b, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + + if (ret == 0) + { + if ((val->emb_func_int2.int2_fsm_lc + | val->fsm_int2_a.int2_fsm1 + | val->fsm_int2_a.int2_fsm2 + | val->fsm_int2_a.int2_fsm3 + | val->fsm_int2_a.int2_fsm4 + | val->fsm_int2_a.int2_fsm5 + | val->fsm_int2_a.int2_fsm6 + | val->fsm_int2_a.int2_fsm7 + | val->fsm_int2_a.int2_fsm8 + | val->fsm_int2_b.int2_fsm9 + | val->fsm_int2_b.int2_fsm10 + | val->fsm_int2_b.int2_fsm11 + | val->fsm_int2_b.int2_fsm12 + | val->fsm_int2_b.int2_fsm13 + | val->fsm_int2_b.int2_fsm14 + | val->fsm_int2_b.int2_fsm15 + | val->fsm_int2_b.int2_fsm16 + | val->mlc_int2.int2_mlc1 + | val->mlc_int2.int2_mlc2 + | val->mlc_int2.int2_mlc3 + | val->mlc_int2.int2_mlc4 + | val->mlc_int2.int2_mlc5 + | val->mlc_int2.int2_mlc6 + | val->mlc_int2.int2_mlc7 + | val->mlc_int2.int2_mlc8) != PROPERTY_DISABLE) + { + val->md2_cfg.int2_emb_func = PROPERTY_ENABLE; + } + else + { + val->md2_cfg.int2_emb_func = PROPERTY_DISABLE; + } + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_INT2_CTRL, + (uint8_t *)&val->int2_ctrl, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MD2_CFG, (uint8_t *)&val->md2_cfg, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INT_CFG1, (uint8_t *) &int_cfg1, 1); + } + + if (ret == 0) + { + ret = asm330lhhxg1_pin_int1_route_get(ctx, &pin_int1_route); + } + + if (ret == 0) + { + if ((val->int2_ctrl.int2_cnt_bdr + | val->int2_ctrl.int2_drdy_g + | val->int2_ctrl.int2_drdy_temp + | val->int2_ctrl.int2_drdy_xl + | val->int2_ctrl.int2_fifo_full + | val->int2_ctrl.int2_fifo_ovr + | val->int2_ctrl.int2_fifo_th + | val->md2_cfg.int2_6d + | val->md2_cfg.int2_ff + | val->md2_cfg.int2_wu + | val->md2_cfg.int2_sleep_change + | pin_int1_route.int1_ctrl.den_drdy_flag + | pin_int1_route.int1_ctrl.int1_boot + | pin_int1_route.int1_ctrl.int1_cnt_bdr + | pin_int1_route.int1_ctrl.int1_drdy_g + | pin_int1_route.int1_ctrl.int1_drdy_xl + | pin_int1_route.int1_ctrl.int1_fifo_full + | pin_int1_route.int1_ctrl.int1_fifo_ovr + | pin_int1_route.int1_ctrl.int1_fifo_th + | pin_int1_route.md1_cfg.int1_6d + | pin_int1_route.md1_cfg.int1_ff + | pin_int1_route.md1_cfg.int1_wu + | pin_int1_route.md1_cfg.int1_sleep_change) != PROPERTY_DISABLE) + { + int_cfg1.interrupts_enable = PROPERTY_ENABLE; + } + else + { + int_cfg1.interrupts_enable = PROPERTY_DISABLE; + } + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_INT_CFG1, (uint8_t *) &int_cfg1, 1); + } + return ret; +} + +/** + * @brief Select the signal that need to route on int2 pad.[get] + * + * @param ctx read / write interface definitions + * @param val union of registers INT2_CTRL, MD2_CFG, + * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B + * + */ +int32_t asm330lhhxg1_pin_int2_route_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_pin_int2_route_t *val) +{ + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MLC_INT2, + (uint8_t *)&val->mlc_int2, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_INT2, + (uint8_t *)&val->emb_func_int2, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_INT2_A, + (uint8_t *)&val->fsm_int2_a, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_INT2_B, + (uint8_t *)&val->fsm_int2_b, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + if (ret == 0) + { + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INT2_CTRL, + (uint8_t *)&val->int2_ctrl, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MD2_CFG, (uint8_t *)&val->md2_cfg, 1); + } + return ret; +} + +/** + * @brief Push-pull/open drain selection on interrupt pads.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of pp_od in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_pin_mode_set(const stmdev_ctx_t *ctx, asm330lhhxg1_pp_od_t val) +{ + asm330lhhxg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret == 0) + { + ctrl3_c.pp_od = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Push-pull/open drain selection on interrupt pads.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of pp_od in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_pin_mode_get(const stmdev_ctx_t *ctx, asm330lhhxg1_pp_od_t *val) +{ + asm330lhhxg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + switch (ctrl3_c.pp_od) + { + case ASM330LHHXG1_PUSH_PULL: + *val = ASM330LHHXG1_PUSH_PULL; + break; + case ASM330LHHXG1_OPEN_DRAIN: + *val = ASM330LHHXG1_OPEN_DRAIN; + break; + default: + *val = ASM330LHHXG1_PUSH_PULL; + break; + } + return ret; +} + +/** + * @brief Interrupt active-high/low.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of h_lactive in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_pin_polarity_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_h_lactive_t val) +{ + asm330lhhxg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + if (ret == 0) + { + ctrl3_c.h_lactive = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Interrupt active-high/low.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of h_lactive in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_pin_polarity_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_h_lactive_t *val) +{ + asm330lhhxg1_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1); + + switch (ctrl3_c.h_lactive) + { + case ASM330LHHXG1_ACTIVE_HIGH: + *val = ASM330LHHXG1_ACTIVE_HIGH; + break; + case ASM330LHHXG1_ACTIVE_LOW: + *val = ASM330LHHXG1_ACTIVE_LOW; + break; + default: + *val = ASM330LHHXG1_ACTIVE_HIGH; + break; + } + return ret; +} + +/** + * @brief All interrupt signals become available on INT1 pin.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of int2_on_int1 in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret == 0) + { + ctrl4_c.int2_on_int1 = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + } + return ret; +} + +/** + * @brief All interrupt signals become available on INT1 pin.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of int2_on_int1 in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + *val = ctrl4_c.int2_on_int1; + + return ret; +} + +/** + * @brief All interrupt signals notification mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of lir in reg INT_CFG0 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_int_notification_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_lir_t val) +{ + asm330lhhxg1_int_cfg0_t int_cfg0; + asm330lhhxg1_page_rw_t page_rw; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INT_CFG0, (uint8_t *)&int_cfg0, 1); + if (ret == 0) + { + int_cfg0.lir = (uint8_t)val & 0x01U; + int_cfg0.int_clr_on_read = (uint8_t)val & 0x01U; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_INT_CFG0, + (uint8_t *)&int_cfg0, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief All interrupt signals notification mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of lir in reg INT_CFG0 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_int_notification_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_lir_t *val) +{ + asm330lhhxg1_int_cfg0_t int_cfg0; + asm330lhhxg1_page_rw_t page_rw; + int32_t ret; + + *val = ASM330LHHXG1_ALL_INT_PULSED; + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INT_CFG0, (uint8_t *)&int_cfg0, 1); + + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + switch ((page_rw.emb_func_lir << 1) + int_cfg0.lir) + { + case ASM330LHHXG1_ALL_INT_PULSED: + *val = ASM330LHHXG1_ALL_INT_PULSED; + break; + case ASM330LHHXG1_BASE_LATCHED_EMB_PULSED: + *val = ASM330LHHXG1_BASE_LATCHED_EMB_PULSED; + break; + case ASM330LHHXG1_BASE_PULSED_EMB_LATCHED: + *val = ASM330LHHXG1_BASE_PULSED_EMB_LATCHED; + break; + case ASM330LHHXG1_ALL_INT_LATCHED: + *val = ASM330LHHXG1_ALL_INT_LATCHED; + break; + default: + *val = ASM330LHHXG1_ALL_INT_PULSED; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHHXG1_Wake_Up_event + * @brief This section groups all the functions that manage the + * Wake Up event generation. + * @{ + * + */ + +/** + * @brief Weight of 1 LSB of wakeup threshold.[set] + * 0: 1 LSB =FS_XL / 64 + * 1: 1 LSB = FS_XL / 256 + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of wake_ths_w in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_wkup_ths_weight_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_wake_ths_w_t val) +{ + asm330lhhxg1_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + wake_up_dur.wake_ths_w = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + } + return ret; +} + +/** + * @brief Weight of 1 LSB of wakeup threshold.[get] + * 0: 1 LSB =FS_XL / 64 + * 1: 1 LSB = FS_XL / 256 + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of wake_ths_w in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_wkup_ths_weight_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_wake_ths_w_t *val) +{ + asm330lhhxg1_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + + switch (wake_up_dur.wake_ths_w) + { + case ASM330LHHXG1_LSb_FS_DIV_64: + *val = ASM330LHHXG1_LSb_FS_DIV_64; + break; + case ASM330LHHXG1_LSb_FS_DIV_256: + *val = ASM330LHHXG1_LSb_FS_DIV_256; + break; + default: + *val = ASM330LHHXG1_LSb_FS_DIV_64; + break; + } + return ret; +} + +/** + * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in + * WAKE_UP_DUR.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of wk_ths in reg WAKE_UP_THS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_THS, + (uint8_t *)&wake_up_ths, 1); + if (ret == 0) + { + wake_up_ths.wk_ths = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_WAKE_UP_THS, + (uint8_t *)&wake_up_ths, 1); + } + return ret; +} + +/** + * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in + * WAKE_UP_DUR.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of wk_ths in reg WAKE_UP_THS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_THS, + (uint8_t *)&wake_up_ths, 1); + *val = wake_up_ths.wk_ths; + + return ret; +} + +/** + * @brief Wake up duration event( 1LSb = 1 / ODR ).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of usr_off_on_wu in reg WAKE_UP_THS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_THS, + (uint8_t *)&wake_up_ths, 1); + if (ret == 0) + { + wake_up_ths.usr_off_on_wu = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_WAKE_UP_THS, + (uint8_t *)&wake_up_ths, 1); + } + return ret; +} + +/** + * @brief Wake up duration event( 1LSb = 1 / ODR ).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of usr_off_on_wu in reg WAKE_UP_THS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, + uint8_t *val) +{ + asm330lhhxg1_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_THS, + (uint8_t *)&wake_up_ths, 1); + *val = wake_up_ths.usr_off_on_wu; + + return ret; +} + +/** + * @brief Wake up duration event(1LSb = 1 / ODR).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of wake_dur in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + wake_up_dur.wake_dur = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + } + return ret; +} + +/** + * @brief Wake up duration event(1LSb = 1 / ODR).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of wake_dur in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + *val = wake_up_dur.wake_dur; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHHXG1_ Activity/Inactivity_detection + * @brief This section groups all the functions concerning + * activity/inactivity detection. + * @{ + * + */ + +/** + * @brief Enables gyroscope Sleep mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sleep_g in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + if (ret == 0) + { + ctrl4_c.sleep_g = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + } + return ret; +} + +/** + * @brief Enables gyroscope Sleep mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sleep_g in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1); + *val = ctrl4_c.sleep_g; + + return ret; +} + +/** + * @brief Drives the sleep status instead of sleep change on INT pins + * (only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits + * are enabled).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sleep_status_on_int in reg INT_CFG0 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_act_pin_notification_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_sleep_status_on_int_t val) +{ + asm330lhhxg1_int_cfg0_t int_cfg0; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INT_CFG0, (uint8_t *)&int_cfg0, 1); + if (ret == 0) + { + int_cfg0. sleep_status_on_int = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_INT_CFG0, + (uint8_t *)&int_cfg0, 1); + } + return ret; +} + +/** + * @brief Drives the sleep status instead of sleep change on INT pins + * (only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits + * are enabled).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of sleep_status_on_int in reg INT_CFG0 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_act_pin_notification_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_sleep_status_on_int_t *val) +{ + asm330lhhxg1_int_cfg0_t int_cfg0; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INT_CFG0, (uint8_t *)&int_cfg0, 1); + switch (int_cfg0. sleep_status_on_int) + { + case ASM330LHHXG1_DRIVE_SLEEP_CHG_EVENT: + *val = ASM330LHHXG1_DRIVE_SLEEP_CHG_EVENT; + break; + case ASM330LHHXG1_DRIVE_SLEEP_STATUS: + *val = ASM330LHHXG1_DRIVE_SLEEP_STATUS; + break; + default: + *val = ASM330LHHXG1_DRIVE_SLEEP_CHG_EVENT; + break; + } + return ret; +} + +/** + * @brief Enable inactivity function.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of inact_en in reg INT_CFG1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_act_mode_set(const stmdev_ctx_t *ctx, asm330lhhxg1_inact_en_t val) +{ + asm330lhhxg1_int_cfg1_t int_cfg1; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INT_CFG1, (uint8_t *)&int_cfg1, 1); + if (ret == 0) + { + int_cfg1.inact_en = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_INT_CFG1, (uint8_t *)&int_cfg1, 1); + } + return ret; +} + +/** + * @brief Enable inactivity function.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of inact_en in reg INT_CFG1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_act_mode_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_inact_en_t *val) +{ + asm330lhhxg1_int_cfg1_t int_cfg1; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INT_CFG1, (uint8_t *)&int_cfg1, 1); + + switch (int_cfg1.inact_en) + { + case ASM330LHHXG1_XL_AND_GY_NOT_AFFECTED: + *val = ASM330LHHXG1_XL_AND_GY_NOT_AFFECTED; + break; + case ASM330LHHXG1_XL_12Hz5_GY_NOT_AFFECTED: + *val = ASM330LHHXG1_XL_12Hz5_GY_NOT_AFFECTED; + break; + case ASM330LHHXG1_XL_12Hz5_GY_SLEEP: + *val = ASM330LHHXG1_XL_12Hz5_GY_SLEEP; + break; + case ASM330LHHXG1_XL_12Hz5_GY_PD: + *val = ASM330LHHXG1_XL_12Hz5_GY_PD; + break; + default: + *val = ASM330LHHXG1_XL_AND_GY_NOT_AFFECTED; + break; + } + return ret; +} + +/** + * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sleep_dur in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + wake_up_dur.sleep_dur = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + } + return ret; +} + +/** + * @brief Duration to go in sleep mode.(1 LSb = 512 / ODR).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sleep_dur in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + *val = wake_up_dur.sleep_dur; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHHXG1_ Six_position_detection(6D/4D) + * @brief This section groups all the functions concerning six + * position detection (6D). + * @{ + * + */ + +/** + * @brief Threshold for 4D/6D function.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of sixd_ths in reg TAP_THS_6D + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_6d_threshold_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_sixd_ths_t val) +{ + asm330lhhxg1_ths_6d_t ths_6d; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_THS_6D, + (uint8_t *)&ths_6d, 1); + if (ret == 0) + { + ths_6d.sixd_ths = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_THS_6D, + (uint8_t *)&ths_6d, 1); + } + return ret; +} + +/** + * @brief Threshold for 4D/6D function.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of sixd_ths in reg TAP_THS_6D + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_6d_threshold_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_sixd_ths_t *val) +{ + asm330lhhxg1_ths_6d_t ths_6d; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_THS_6D, + (uint8_t *)&ths_6d, 1); + + switch (ths_6d.sixd_ths) + { + case ASM330LHHXG1_DEG_80: + *val = ASM330LHHXG1_DEG_80; + break; + case ASM330LHHXG1_DEG_70: + *val = ASM330LHHXG1_DEG_70; + break; + case ASM330LHHXG1_DEG_60: + *val = ASM330LHHXG1_DEG_60; + break; + case ASM330LHHXG1_DEG_50: + *val = ASM330LHHXG1_DEG_50; + break; + default: + *val = ASM330LHHXG1_DEG_80; + break; + } + return ret; +} + +/** + * @brief 4D orientation detection enable.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of d4d_en in reg TAP_THS_6D + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_ths_6d_t ths_6d; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_THS_6D, + (uint8_t *)&ths_6d, 1); + if (ret == 0) + { + ths_6d.d4d_en = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_THS_6D, + (uint8_t *)&ths_6d, 1); + } + return ret; +} + +/** + * @brief 4D orientation detection enable.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of d4d_en in reg TAP_THS_6D + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_ths_6d_t ths_6d; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_THS_6D, + (uint8_t *)&ths_6d, 1); + *val = ths_6d.d4d_en; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHHXG1_free_fall + * @brief This section group all the functions concerning the free + * fall detection. + * @{ + * + */ + +/** + * @brief Free fall threshold setting.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of ff_ths in reg FREE_FALL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_ff_threshold_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_ff_ths_t val) +{ + asm330lhhxg1_free_fall_t free_fall; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret == 0) + { + free_fall.ff_ths = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FREE_FALL, + (uint8_t *)&free_fall, 1); + } + return ret; +} + +/** + * @brief Free fall threshold setting.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of ff_ths in reg FREE_FALL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_ff_threshold_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_ff_ths_t *val) +{ + asm330lhhxg1_free_fall_t free_fall; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FREE_FALL, (uint8_t *)&free_fall, 1); + + switch (free_fall.ff_ths) + { + case ASM330LHHXG1_FF_TSH_156mg: + *val = ASM330LHHXG1_FF_TSH_156mg; + break; + case ASM330LHHXG1_FF_TSH_219mg: + *val = ASM330LHHXG1_FF_TSH_219mg; + break; + case ASM330LHHXG1_FF_TSH_250mg: + *val = ASM330LHHXG1_FF_TSH_250mg; + break; + case ASM330LHHXG1_FF_TSH_312mg: + *val = ASM330LHHXG1_FF_TSH_312mg; + break; + case ASM330LHHXG1_FF_TSH_344mg: + *val = ASM330LHHXG1_FF_TSH_344mg; + break; + case ASM330LHHXG1_FF_TSH_406mg: + *val = ASM330LHHXG1_FF_TSH_406mg; + break; + case ASM330LHHXG1_FF_TSH_469mg: + *val = ASM330LHHXG1_FF_TSH_469mg; + break; + case ASM330LHHXG1_FF_TSH_500mg: + *val = ASM330LHHXG1_FF_TSH_500mg; + break; + default: + *val = ASM330LHHXG1_FF_TSH_156mg; + break; + } + return ret; +} + +/** + * @brief Free-fall duration event(1LSb = 1 / ODR).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of ff_dur in reg FREE_FALL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_wake_up_dur_t wake_up_dur; + asm330lhhxg1_free_fall_t free_fall; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + wake_up_dur.ff_dur = (val & 0x20U) >> 5; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FREE_FALL, + (uint8_t *)&free_fall, 1); + } + if (ret == 0) + { + free_fall.ff_dur = val & 0x1FU; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FREE_FALL, + (uint8_t *)&free_fall, 1); + } + return ret; +} + +/** + * @brief Free-fall duration event(1LSb = 1 / ODR).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of ff_dur in reg FREE_FALL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_wake_up_dur_t wake_up_dur; + asm330lhhxg1_free_fall_t free_fall; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR, + (uint8_t *)&wake_up_dur, 1); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FREE_FALL, + (uint8_t *)&free_fall, 1); + } + *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHHXG1_fifo + * @brief This section group all the functions concerning + * the fifo usage + * @{ + * + */ + +/** + * @brief FIFO watermark level selection.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of wtm in reg FIFO_CTRL1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + asm330lhhxg1_fifo_ctrl1_t fifo_ctrl1; + asm330lhhxg1_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.wtm = (uint8_t)((val / 256U) & 0x01U); + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + } + if (ret == 0) + { + fifo_ctrl1.wtm = (uint8_t)(val - (fifo_ctrl2.wtm * 256U)); + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FIFO_CTRL1, + (uint8_t *)&fifo_ctrl1, 1); + } + + return ret; +} + +/** + * @brief FIFO watermark level selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of wtm in reg FIFO_CTRL1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + asm330lhhxg1_fifo_ctrl1_t fifo_ctrl1; + asm330lhhxg1_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL1, + (uint8_t *)&fifo_ctrl1, 1); + } + *val = fifo_ctrl2.wtm; + *val = (*val * 256U) + fifo_ctrl1.wtm; + return ret; +} + +/** + * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of odrchg_en in reg FIFO_CTRL2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, + uint8_t val) +{ + asm330lhhxg1_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.odrchg_en = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of odrchg_en in reg FIFO_CTRL2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, + uint8_t *val) +{ + asm330lhhxg1_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.odrchg_en; + + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at threshold + * level.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of stop_on_wtm in reg FIFO_CTRL2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.stop_on_wtm = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + } + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at threshold + * level.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of stop_on_wtm in reg FIFO_CTRL2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL2, + (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.stop_on_wtm; + + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for accelerometer data.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of bdr_xl in reg FIFO_CTRL3 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fifo_xl_batch_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_bdr_xl_t val) +{ + asm330lhhxg1_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL3, + (uint8_t *)&fifo_ctrl3, 1); + if (ret == 0) + { + fifo_ctrl3.bdr_xl = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FIFO_CTRL3, + (uint8_t *)&fifo_ctrl3, 1); + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for accelerometer data.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of bdr_xl in reg FIFO_CTRL3 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fifo_xl_batch_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_bdr_xl_t *val) +{ + asm330lhhxg1_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL3, + (uint8_t *)&fifo_ctrl3, 1); + + switch (fifo_ctrl3.bdr_xl) + { + case ASM330LHHXG1_XL_NOT_BATCHED: + *val = ASM330LHHXG1_XL_NOT_BATCHED; + break; + case ASM330LHHXG1_XL_BATCHED_AT_12Hz5: + *val = ASM330LHHXG1_XL_BATCHED_AT_12Hz5; + break; + case ASM330LHHXG1_XL_BATCHED_AT_26Hz: + *val = ASM330LHHXG1_XL_BATCHED_AT_26Hz; + break; + case ASM330LHHXG1_XL_BATCHED_AT_52Hz: + *val = ASM330LHHXG1_XL_BATCHED_AT_52Hz; + break; + case ASM330LHHXG1_XL_BATCHED_AT_104Hz: + *val = ASM330LHHXG1_XL_BATCHED_AT_104Hz; + break; + case ASM330LHHXG1_XL_BATCHED_AT_208Hz: + *val = ASM330LHHXG1_XL_BATCHED_AT_208Hz; + break; + case ASM330LHHXG1_XL_BATCHED_AT_417Hz: + *val = ASM330LHHXG1_XL_BATCHED_AT_417Hz; + break; + case ASM330LHHXG1_XL_BATCHED_AT_833Hz: + *val = ASM330LHHXG1_XL_BATCHED_AT_833Hz; + break; + case ASM330LHHXG1_XL_BATCHED_AT_1667Hz: + *val = ASM330LHHXG1_XL_BATCHED_AT_1667Hz; + break; + case ASM330LHHXG1_XL_BATCHED_AT_3333Hz: + *val = ASM330LHHXG1_XL_BATCHED_AT_3333Hz; + break; + case ASM330LHHXG1_XL_BATCHED_AT_6667Hz: + *val = ASM330LHHXG1_XL_BATCHED_AT_6667Hz; + break; + case ASM330LHHXG1_XL_BATCHED_AT_1Hz6: + *val = ASM330LHHXG1_XL_BATCHED_AT_1Hz6; + break; + default: + *val = ASM330LHHXG1_XL_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for gyroscope data.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of bdr_gy in reg FIFO_CTRL3 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fifo_gy_batch_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_bdr_gy_t val) +{ + asm330lhhxg1_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL3, + (uint8_t *)&fifo_ctrl3, 1); + if (ret == 0) + { + fifo_ctrl3.bdr_gy = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FIFO_CTRL3, + (uint8_t *)&fifo_ctrl3, 1); + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for gyroscope data.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of bdr_gy in reg FIFO_CTRL3 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fifo_gy_batch_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_bdr_gy_t *val) +{ + asm330lhhxg1_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL3, + (uint8_t *)&fifo_ctrl3, 1); + + switch (fifo_ctrl3.bdr_gy) + { + case ASM330LHHXG1_GY_NOT_BATCHED: + *val = ASM330LHHXG1_GY_NOT_BATCHED; + break; + case ASM330LHHXG1_GY_BATCHED_AT_12Hz5: + *val = ASM330LHHXG1_GY_BATCHED_AT_12Hz5; + break; + case ASM330LHHXG1_GY_BATCHED_AT_26Hz: + *val = ASM330LHHXG1_GY_BATCHED_AT_26Hz; + break; + case ASM330LHHXG1_GY_BATCHED_AT_52Hz: + *val = ASM330LHHXG1_GY_BATCHED_AT_52Hz; + break; + case ASM330LHHXG1_GY_BATCHED_AT_104Hz: + *val = ASM330LHHXG1_GY_BATCHED_AT_104Hz; + break; + case ASM330LHHXG1_GY_BATCHED_AT_208Hz: + *val = ASM330LHHXG1_GY_BATCHED_AT_208Hz; + break; + case ASM330LHHXG1_GY_BATCHED_AT_417Hz: + *val = ASM330LHHXG1_GY_BATCHED_AT_417Hz; + break; + case ASM330LHHXG1_GY_BATCHED_AT_833Hz: + *val = ASM330LHHXG1_GY_BATCHED_AT_833Hz; + break; + case ASM330LHHXG1_GY_BATCHED_AT_1667Hz: + *val = ASM330LHHXG1_GY_BATCHED_AT_1667Hz; + break; + case ASM330LHHXG1_GY_BATCHED_AT_3333Hz: + *val = ASM330LHHXG1_GY_BATCHED_AT_3333Hz; + break; + case ASM330LHHXG1_GY_BATCHED_AT_6667Hz: + *val = ASM330LHHXG1_GY_BATCHED_AT_6667Hz; + break; + case ASM330LHHXG1_GY_BATCHED_AT_6Hz5: + *val = ASM330LHHXG1_GY_BATCHED_AT_6Hz5; + break; + default: + *val = ASM330LHHXG1_GY_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief FIFO mode selection.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fifo_mode in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fifo_mode_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_fifo_mode_t val) +{ + asm330lhhxg1_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.fifo_mode = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + } + return ret; +} + +/** + * @brief FIFO mode selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of fifo_mode in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fifo_mode_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_fifo_mode_t *val) +{ + asm330lhhxg1_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + + switch (fifo_ctrl4.fifo_mode) + { + case ASM330LHHXG1_BYPASS_MODE: + *val = ASM330LHHXG1_BYPASS_MODE; + break; + case ASM330LHHXG1_FIFO_MODE: + *val = ASM330LHHXG1_FIFO_MODE; + break; + case ASM330LHHXG1_STREAM_TO_FIFO_MODE: + *val = ASM330LHHXG1_STREAM_TO_FIFO_MODE; + break; + case ASM330LHHXG1_BYPASS_TO_STREAM_MODE: + *val = ASM330LHHXG1_BYPASS_TO_STREAM_MODE; + break; + case ASM330LHHXG1_STREAM_MODE: + *val = ASM330LHHXG1_STREAM_MODE; + break; + case ASM330LHHXG1_BYPASS_TO_FIFO_MODE: + *val = ASM330LHHXG1_BYPASS_TO_FIFO_MODE; + break; + default: + *val = ASM330LHHXG1_BYPASS_MODE; + break; + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for temperature data.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of odr_t_batch in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fifo_temp_batch_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_odr_t_batch_t val) +{ + asm330lhhxg1_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.odr_t_batch = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for temperature data.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of odr_t_batch in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fifo_temp_batch_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_odr_t_batch_t *val) +{ + asm330lhhxg1_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + + switch (fifo_ctrl4.odr_t_batch) + { + case ASM330LHHXG1_TEMP_NOT_BATCHED: + *val = ASM330LHHXG1_TEMP_NOT_BATCHED; + break; + case ASM330LHHXG1_TEMP_BATCHED_AT_52Hz: + *val = ASM330LHHXG1_TEMP_BATCHED_AT_52Hz; + break; + case ASM330LHHXG1_TEMP_BATCHED_AT_12Hz5: + *val = ASM330LHHXG1_TEMP_BATCHED_AT_12Hz5; + break; + case ASM330LHHXG1_TEMP_BATCHED_AT_1Hz6: + *val = ASM330LHHXG1_TEMP_BATCHED_AT_1Hz6; + break; + default: + *val = ASM330LHHXG1_TEMP_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief Selects decimation for timestamp batching in FIFO. + * Writing rate will be the maximum rate between XL and + * GYRO BDR divided by decimation decoder.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of dec_ts_batch in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_dec_ts_batch_t val) +{ + asm330lhhxg1_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.dec_ts_batch = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + } + return ret; +} + +/** + * @brief Selects decimation for timestamp batching in FIFO. + * Writing rate will be the maximum rate between XL and + * GYRO BDR divided by decimation decoder.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of dec_ts_batch in reg + * FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_dec_ts_batch_t *val) +{ + asm330lhhxg1_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL4, + (uint8_t *)&fifo_ctrl4, 1); + + switch (fifo_ctrl4.dec_ts_batch) + { + case ASM330LHHXG1_NO_DECIMATION: + *val = ASM330LHHXG1_NO_DECIMATION; + break; + case ASM330LHHXG1_DEC_1: + *val = ASM330LHHXG1_DEC_1; + break; + case ASM330LHHXG1_DEC_8: + *val = ASM330LHHXG1_DEC_8; + break; + case ASM330LHHXG1_DEC_32: + *val = ASM330LHHXG1_DEC_32; + break; + default: + *val = ASM330LHHXG1_NO_DECIMATION; + break; + } + return ret; +} + +/** + * @brief Selects the trigger for the internal counter of batching events + * between XL and gyro.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of trig_counter_bdr in + * reg COUNTER_BDR_REG1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_trig_counter_bdr_t val) +{ + asm330lhhxg1_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + if (ret == 0) + { + counter_bdr_reg1.trig_counter_bdr = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + } + return ret; +} + +/** + * @brief Selects the trigger for the internal counter of batching events + * between XL and gyro.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of trig_counter_bdr + * in reg COUNTER_BDR_REG1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_trig_counter_bdr_t *val) +{ + asm330lhhxg1_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + + switch (counter_bdr_reg1.trig_counter_bdr) + { + case ASM330LHHXG1_XL_BATCH_EVENT: + *val = ASM330LHHXG1_XL_BATCH_EVENT; + break; + case ASM330LHHXG1_GYRO_BATCH_EVENT: + *val = ASM330LHHXG1_GYRO_BATCH_EVENT; + break; + default: + *val = ASM330LHHXG1_XL_BATCH_EVENT; + break; + } + return ret; +} + +/** + * @brief Resets the internal counter of batching events for a single sensor. + * This bit is automatically reset to zero if it was set to ‘1’.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of rst_counter_bdr in reg COUNTER_BDR_REG1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + if (ret == 0) + { + counter_bdr_reg1.rst_counter_bdr = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + } + return ret; +} + +/** + * @brief Resets the internal counter of batching events for a single sensor. + * This bit is automatically reset to zero if it was set to ‘1’.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of rst_counter_bdr in reg COUNTER_BDR_REG1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + *val = counter_bdr_reg1.rst_counter_bdr; + + return ret; +} + +/** + * @brief Batch data rate counter.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of cnt_bdr_th in reg COUNTER_BDR_REG2 + * and COUNTER_BDR_REG1. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + asm330lhhxg1_counter_bdr_reg2_t counter_bdr_reg1; + asm330lhhxg1_counter_bdr_reg2_t counter_bdr_reg2; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + if (ret == 0) + { + counter_bdr_reg1.cnt_bdr_th = (uint8_t)((val / 256U) & 0x07U); + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + } + if (ret == 0) + { + counter_bdr_reg2.cnt_bdr_th = (uint8_t)(val - (counter_bdr_reg1.cnt_bdr_th * 256U)); + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG2, + (uint8_t *)&counter_bdr_reg2, 1); + } + return ret; +} + +/** + * @brief Batch data rate counter.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of cnt_bdr_th in reg COUNTER_BDR_REG2 + * and COUNTER_BDR_REG1. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_batch_counter_threshold_get(const stmdev_ctx_t *ctx, + uint16_t *val) +{ + asm330lhhxg1_counter_bdr_reg1_t counter_bdr_reg1; + asm330lhhxg1_counter_bdr_reg2_t counter_bdr_reg2; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1, + (uint8_t *)&counter_bdr_reg1, 1); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG2, + (uint8_t *)&counter_bdr_reg2, 1); + } + + *val = counter_bdr_reg1.cnt_bdr_th; + *val = (*val * 256U) + counter_bdr_reg2.cnt_bdr_th; + return ret; +} + +/** + * @brief Number of unread sensor data (TAG + 6 bytes) stored in FIFO.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of diff_fifo in reg FIFO_STATUS1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + asm330lhhxg1_fifo_status1_t fifo_status1; + asm330lhhxg1_fifo_status2_t fifo_status2; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_STATUS1, + (uint8_t *)&fifo_status1, 1); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_STATUS2, + (uint8_t *)&fifo_status2, 1); + + *val = fifo_status2.diff_fifo; + *val = (*val * 256U) + fifo_status1.diff_fifo; + } + return ret; +} + +/** + * @brief Smart FIFO status.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Registers FIFO_STATUS2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fifo_status_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_fifo_status2_t *val) +{ + int32_t ret; + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_STATUS2, (uint8_t *)val, 1); + return ret; +} + +/** + * @brief Smart FIFO full status.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fifo_full_ia in reg FIFO_STATUS2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_fifo_status2_t fifo_status2; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_STATUS2, + (uint8_t *)&fifo_status2, 1); + *val = fifo_status2.fifo_full_ia; + + return ret; +} + +/** + * @brief FIFO overrun status.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fifo_over_run_latched in + * reg FIFO_STATUS2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_fifo_status2_t fifo_status2; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_STATUS2, + (uint8_t *)&fifo_status2, 1); + *val = fifo_status2. fifo_ovr_ia; + + return ret; +} + +/** + * @brief FIFO watermark status.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fifo_wtm_ia in reg FIFO_STATUS2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_fifo_status2_t fifo_status2; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_STATUS2, + (uint8_t *)&fifo_status2, 1); + *val = fifo_status2.fifo_wtm_ia; + + return ret; +} + +/** + * @brief Identifies the sensor in FIFO_DATA_OUT.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of tag_sensor in reg FIFO_DATA_OUT_TAG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_fifo_tag_t *val) +{ + asm330lhhxg1_fifo_data_out_tag_t fifo_data_out_tag; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_DATA_OUT_TAG, + (uint8_t *)&fifo_data_out_tag, 1); + + switch (fifo_data_out_tag.tag_sensor) + { + case ASM330LHHXG1_GYRO_NC_TAG: + *val = ASM330LHHXG1_GYRO_NC_TAG; + break; + case ASM330LHHXG1_XL_NC_TAG: + *val = ASM330LHHXG1_XL_NC_TAG; + break; + case ASM330LHHXG1_TEMPERATURE_TAG: + *val = ASM330LHHXG1_TEMPERATURE_TAG; + break; + case ASM330LHHXG1_TIMESTAMP_TAG: + *val = ASM330LHHXG1_TIMESTAMP_TAG; + break; + case ASM330LHHXG1_CFG_CHANGE_TAG: + *val = ASM330LHHXG1_CFG_CHANGE_TAG; + break; + case ASM330LHHXG1_SENSORHUB_SLAVE0_TAG: + *val = ASM330LHHXG1_SENSORHUB_SLAVE0_TAG; + break; + case ASM330LHHXG1_SENSORHUB_SLAVE1_TAG: + *val = ASM330LHHXG1_SENSORHUB_SLAVE1_TAG; + break; + case ASM330LHHXG1_SENSORHUB_SLAVE2_TAG: + *val = ASM330LHHXG1_SENSORHUB_SLAVE2_TAG; + break; + case ASM330LHHXG1_SENSORHUB_SLAVE3_TAG: + *val = ASM330LHHXG1_SENSORHUB_SLAVE3_TAG; + break; + case ASM330LHHXG1_SENSORHUB_NACK_TAG: + *val = ASM330LHHXG1_SENSORHUB_NACK_TAG; + break; + default: + *val = ASM330LHHXG1_SENSORHUB_NACK_TAG; + break; + } + return ret; +} + +/** + * @brief Enable FIFO batching data of first slave.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of batch_ext_sens_0_en in reg SLV0_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_slv0_config_t slv0_config; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV0_CONFIG, + (uint8_t *)&slv0_config, 1); + } + if (ret == 0) + { + slv0_config. batch_ext_sens_0_en = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV0_CONFIG, + (uint8_t *)&slv0_config, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Enable FIFO batching data of first slave.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of batch_ext_sens_0_en in + * reg SLV0_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_slv0_config_t slv0_config; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV0_CONFIG, + (uint8_t *)&slv0_config, 1); + } + if (ret == 0) + { + *val = slv0_config. batch_ext_sens_0_en; + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Enable FIFO batching data of second slave.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of batch_ext_sens_1_en in + * reg SLV1_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_slv1_config_t slv1_config; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV1_CONFIG, + (uint8_t *)&slv1_config, 1); + } + if (ret == 0) + { + slv1_config. batch_ext_sens_1_en = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV1_CONFIG, + (uint8_t *)&slv1_config, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Enable FIFO batching data of second slave.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of batch_ext_sens_1_en in + * reg SLV1_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_slv1_config_t slv1_config; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV1_CONFIG, + (uint8_t *)&slv1_config, 1); + *val = slv1_config. batch_ext_sens_1_en; + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Enable FIFO batching data of third slave.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of batch_ext_sens_2_en in + * reg SLV2_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_slv2_config_t slv2_config; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV2_CONFIG, + (uint8_t *)&slv2_config, 1); + } + if (ret == 0) + { + slv2_config. batch_ext_sens_2_en = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV2_CONFIG, + (uint8_t *)&slv2_config, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Enable FIFO batching data of third slave.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of batch_ext_sens_2_en in + * reg SLV2_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_slv2_config_t slv2_config; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV2_CONFIG, + (uint8_t *)&slv2_config, 1); + } + if (ret == 0) + { + *val = slv2_config. batch_ext_sens_2_en; + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Enable FIFO batching data of fourth slave.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of batch_ext_sens_3_en in + * reg SLV3_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_slv3_config_t slv3_config; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV3_CONFIG, + (uint8_t *)&slv3_config, 1); + } + if (ret == 0) + { + slv3_config. batch_ext_sens_3_en = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV3_CONFIG, + (uint8_t *)&slv3_config, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Enable FIFO batching data of fourth slave.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of batch_ext_sens_3_en in + * reg SLV3_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_slv3_config_t slv3_config; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV3_CONFIG, + (uint8_t *)&slv3_config, 1); + *val = slv3_config. batch_ext_sens_3_en; + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHHXG1_DEN_functionality + * @brief This section groups all the functions concerning + * DEN functionality. + * @{ + * + */ + +/** + * @brief DEN functionality marking mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of den_mode in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_den_mode_set(const stmdev_ctx_t *ctx, asm330lhhxg1_den_mode_t val) +{ + asm330lhhxg1_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + if (ret == 0) + { + ctrl6_c.den_mode = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + } + return ret; +} + +/** + * @brief DEN functionality marking mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of den_mode in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_den_mode_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_den_mode_t *val) +{ + asm330lhhxg1_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1); + + switch (ctrl6_c.den_mode) + { + case ASM330LHHXG1_DEN_DISABLE: + *val = ASM330LHHXG1_DEN_DISABLE; + break; + case ASM330LHHXG1_LEVEL_FIFO: + *val = ASM330LHHXG1_LEVEL_FIFO; + break; + case ASM330LHHXG1_LEVEL_LETCHED: + *val = ASM330LHHXG1_LEVEL_LETCHED; + break; + case ASM330LHHXG1_LEVEL_TRIGGER: + *val = ASM330LHHXG1_LEVEL_TRIGGER; + break; + case ASM330LHHXG1_EDGE_TRIGGER: + *val = ASM330LHHXG1_EDGE_TRIGGER; + break; + default: + *val = ASM330LHHXG1_DEN_DISABLE; + break; + } + return ret; +} + +/** + * @brief DEN active level configuration.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of den_lh in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_den_polarity_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_den_lh_t val) +{ + asm330lhhxg1_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret == 0) + { + ctrl9_xl.den_lh = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL9_XL, + (uint8_t *)&ctrl9_xl, 1); + } + return ret; +} + +/** + * @brief DEN active level configuration.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of den_lh in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_den_polarity_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_den_lh_t *val) +{ + asm330lhhxg1_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + + switch (ctrl9_xl.den_lh) + { + case ASM330LHHXG1_DEN_ACT_LOW: + *val = ASM330LHHXG1_DEN_ACT_LOW; + break; + case ASM330LHHXG1_DEN_ACT_HIGH: + *val = ASM330LHHXG1_DEN_ACT_HIGH; + break; + default: + *val = ASM330LHHXG1_DEN_ACT_LOW; + break; + } + return ret; +} + +/** + * @brief DEN configuration.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of den_xl_g in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_den_enable_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_den_xl_g_t val) +{ + asm330lhhxg1_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret == 0) + { + ctrl9_xl.den_xl_g = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL9_XL, + (uint8_t *)&ctrl9_xl, 1); + } + return ret; +} + +/** + * @brief DEN configuration.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of den_xl_g in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_den_enable_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_den_xl_g_t *val) +{ + asm330lhhxg1_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + + switch (ctrl9_xl.den_xl_g) + { + case ASM330LHHXG1_STAMP_IN_GY_DATA: + *val = ASM330LHHXG1_STAMP_IN_GY_DATA; + break; + case ASM330LHHXG1_STAMP_IN_XL_DATA: + *val = ASM330LHHXG1_STAMP_IN_XL_DATA; + break; + case ASM330LHHXG1_STAMP_IN_GY_XL_DATA: + *val = ASM330LHHXG1_STAMP_IN_GY_XL_DATA; + break; + default: + *val = ASM330LHHXG1_STAMP_IN_GY_DATA; + break; + } + return ret; +} + +/** + * @brief DEN value stored in LSB of X-axis.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of den_z in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret == 0) + { + ctrl9_xl.den_z = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL9_XL, + (uint8_t *)&ctrl9_xl, 1); + } + return ret; +} + +/** + * @brief DEN value stored in LSB of X-axis.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of den_z in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + *val = ctrl9_xl.den_z; + + return ret; +} + +/** + * @brief DEN value stored in LSB of Y-axis.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of den_y in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret == 0) + { + ctrl9_xl.den_y = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL9_XL, + (uint8_t *)&ctrl9_xl, 1); + } + return ret; +} + +/** + * @brief DEN value stored in LSB of Y-axis.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of den_y in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + *val = ctrl9_xl.den_y; + + return ret; +} + +/** + * @brief DEN value stored in LSB of Z-axis.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of den_x in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + if (ret == 0) + { + ctrl9_xl.den_x = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + } + return ret; +} + +/** + * @brief DEN value stored in LSB of Z-axis.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of den_x in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); + *val = ctrl9_xl.den_x; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHHXG1_ magnetometer_sensor + * @brief This section groups all the functions that manage additional + * magnetometer sensor. + * @{ + * + */ + +/** + * @brief External magnetometer sensitivity value register.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SENSITIVITY_L, &buff[0]); + if (ret == 0) + { + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SENSITIVITY_H, &buff[1]); + } + return ret; +} + +/** + * @brief External magnetometer sensitivity value register.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SENSITIVITY_L, &buff[0]); + if (ret == 0) + { + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SENSITIVITY_H, &buff[1]); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } + return ret; +} + +/** + * @brief Offset for hard-iron compensation register (r/w).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + uint8_t i; + + buff[1] = (uint8_t)((uint16_t)val[0] / 256U); + buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U)); + buff[3] = (uint8_t)((uint16_t)val[1] / 256U); + buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U)); + buff[5] = (uint8_t)((uint16_t)val[2] / 256U); + buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U)); + + i = 0x00U; + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_OFFX_L, &buff[i]); + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_OFFX_H, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_OFFY_L, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_OFFY_H, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_OFFZ_L, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_OFFZ_H, &buff[i]); + } + return ret; +} + +/** + * @brief Offset for hard-iron compensation register (r/w).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + uint8_t i; + + i = 0x00U; + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_OFFX_L, &buff[i]); + + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_OFFX_H, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_OFFY_L, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_OFFY_H, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_OFFZ_L, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_OFFZ_H, &buff[i]); + } + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Soft-iron (3x3 symmetric) matrix correction register (r/w). + * The value is expressed as half-precision floating-point format: + * SEEEEEFFFFFFFFFF + * S: 1 sign bit; + * E: 5 exponent bits; + * F: 10 fraction bits).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[12]; + int32_t ret; + uint8_t i; + + buff[1] = (uint8_t)(val[0] / 256U); + buff[0] = (uint8_t)(val[0] - (buff[1] * 256U)); + buff[3] = (uint8_t)(val[1] / 256U); + buff[2] = (uint8_t)(val[1] - (buff[3] * 256U)); + buff[5] = (uint8_t)(val[2] / 256U); + buff[4] = (uint8_t)(val[2] - (buff[5] * 256U)); + buff[7] = (uint8_t)(val[3] / 256U); + buff[6] = (uint8_t)(val[3] - (buff[1] * 256U)); + buff[9] = (uint8_t)(val[4] / 256U); + buff[8] = (uint8_t)(val[4] - (buff[3] * 256U)); + buff[11] = (uint8_t)(val[5] / 256U); + buff[10] = (uint8_t)(val[5] - (buff[5] * 256U)); + + i = 0x00U; + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SI_XX_L, &buff[i]); + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SI_XX_H, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SI_XY_L, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SI_XY_H, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SI_XZ_L, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SI_XZ_H, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SI_YY_L, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SI_YY_H, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SI_YZ_L, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SI_YZ_H, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SI_ZZ_L, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SI_ZZ_H, &buff[i]); + } + return ret; +} + +/** + * @brief Soft-iron (3x3 symmetric) matrix correction register (r/w). + * The value is expressed as half-precision floating-point format: + * SEEEEEFFFFFFFFFF + * S: 1 sign bit; + * E: 5 exponent bits; + * F: 10 fraction bits).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[12]; + int32_t ret; + uint8_t i; + + i = 0x00U; + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SI_XX_L, &buff[i]); + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SI_XX_H, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SI_XY_L, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SI_XY_H, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SI_XZ_L, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SI_XZ_H, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SI_YY_L, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SI_YY_H, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SI_YZ_L, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SI_YZ_H, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SI_ZZ_L, &buff[i]); + } + if (ret == 0) + { + i++; + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SI_ZZ_H, &buff[i]); + } + + val[0] = buff[1]; + val[0] = (val[0] * 256U) + buff[0]; + val[1] = buff[3]; + val[1] = (val[1] * 256U) + buff[2]; + val[2] = buff[5]; + val[2] = (val[2] * 256U) + buff[4]; + val[3] = buff[7]; + val[3] = (val[3] * 256U) + buff[6]; + val[4] = buff[9]; + val[4] = (val[4] * 256U) + buff[8]; + val[5] = buff[11]; + val[6] = (val[5] * 256U) + buff[10]; + + return ret; +} + +/** + * @brief Magnetometer Z-axis coordinates rotation (to be aligned to + * accelerometer/gyroscope axes orientation).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of mag_z_axis in reg MAG_CFG_A + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_mag_z_orient_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_mag_z_axis_t val) +{ + asm330lhhxg1_mag_cfg_a_t mag_cfg_a; + int32_t ret; + + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_CFG_A, + (uint8_t *)&mag_cfg_a); + + if (ret == 0) + { + mag_cfg_a.mag_z_axis = (uint8_t)val; + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_CFG_A, + (uint8_t *)&mag_cfg_a); + } + return ret; +} + +/** + * @brief Magnetometer Z-axis coordinates rotation (to be aligned to + * accelerometer/gyroscope axes orientation).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of mag_z_axis in reg MAG_CFG_A + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_mag_z_orient_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_mag_z_axis_t *val) +{ + asm330lhhxg1_mag_cfg_a_t mag_cfg_a; + int32_t ret; + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_CFG_A, + (uint8_t *)&mag_cfg_a); + + switch (mag_cfg_a.mag_z_axis) + { + case ASM330LHHXG1_Z_EQ_Y: + *val = ASM330LHHXG1_Z_EQ_Y; + break; + case ASM330LHHXG1_Z_EQ_MIN_Y: + *val = ASM330LHHXG1_Z_EQ_MIN_Y; + break; + case ASM330LHHXG1_Z_EQ_X: + *val = ASM330LHHXG1_Z_EQ_X; + break; + case ASM330LHHXG1_Z_EQ_MIN_X: + *val = ASM330LHHXG1_Z_EQ_MIN_X; + break; + case ASM330LHHXG1_Z_EQ_MIN_Z: + *val = ASM330LHHXG1_Z_EQ_MIN_Z; + break; + case ASM330LHHXG1_Z_EQ_Z: + *val = ASM330LHHXG1_Z_EQ_Z; + break; + default: + *val = ASM330LHHXG1_Z_EQ_Y; + break; + } + return ret; +} + +/** + * @brief Magnetometer Y-axis coordinates rotation (to be aligned to + * accelerometer/gyroscope axes orientation).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of mag_y_axis in + * reg MAG_CFG_A + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_mag_y_orient_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_mag_y_axis_t val) +{ + asm330lhhxg1_mag_cfg_a_t mag_cfg_a; + int32_t ret; + + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_CFG_A, + (uint8_t *)&mag_cfg_a); + if (ret == 0) + { + mag_cfg_a.mag_y_axis = (uint8_t)val; + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_CFG_A, + (uint8_t *)&mag_cfg_a); + } + return ret; +} + +/** + * @brief Magnetometer Y-axis coordinates rotation (to be aligned to + * accelerometer/gyroscope axes orientation).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of mag_y_axis in reg MAG_CFG_A + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_mag_y_orient_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_mag_y_axis_t *val) +{ + asm330lhhxg1_mag_cfg_a_t mag_cfg_a; + int32_t ret; + + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_CFG_A, + (uint8_t *)&mag_cfg_a); + + switch (mag_cfg_a.mag_y_axis) + { + case ASM330LHHXG1_Y_EQ_Y: + *val = ASM330LHHXG1_Y_EQ_Y; + break; + case ASM330LHHXG1_Y_EQ_MIN_Y: + *val = ASM330LHHXG1_Y_EQ_MIN_Y; + break; + case ASM330LHHXG1_Y_EQ_X: + *val = ASM330LHHXG1_Y_EQ_X; + break; + case ASM330LHHXG1_Y_EQ_MIN_X: + *val = ASM330LHHXG1_Y_EQ_MIN_X; + break; + case ASM330LHHXG1_Y_EQ_MIN_Z: + *val = ASM330LHHXG1_Y_EQ_MIN_Z; + break; + case ASM330LHHXG1_Y_EQ_Z: + *val = ASM330LHHXG1_Y_EQ_Z; + break; + default: + *val = ASM330LHHXG1_Y_EQ_Y; + break; + } + return ret; +} + +/** + * @brief Magnetometer X-axis coordinates rotation (to be aligned to + * accelerometer/gyroscope axes orientation).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of mag_x_axis in reg MAG_CFG_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_mag_x_orient_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_mag_x_axis_t val) +{ + asm330lhhxg1_mag_cfg_b_t mag_cfg_b; + int32_t ret; + + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_CFG_B, + (uint8_t *)&mag_cfg_b); + if (ret == 0) + { + mag_cfg_b.mag_x_axis = (uint8_t)val; + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_CFG_B, + (uint8_t *)&mag_cfg_b); + } + return ret; +} + +/** + * @brief Magnetometer X-axis coordinates rotation (to be aligned to + * accelerometer/gyroscope axes orientation).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of mag_x_axis in reg MAG_CFG_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_mag_x_orient_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_mag_x_axis_t *val) +{ + asm330lhhxg1_mag_cfg_b_t mag_cfg_b; + int32_t ret; + + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_CFG_B, + (uint8_t *)&mag_cfg_b); + + switch (mag_cfg_b.mag_x_axis) + { + case ASM330LHHXG1_X_EQ_Y: + *val = ASM330LHHXG1_X_EQ_Y; + break; + case ASM330LHHXG1_X_EQ_MIN_Y: + *val = ASM330LHHXG1_X_EQ_MIN_Y; + break; + case ASM330LHHXG1_X_EQ_X: + *val = ASM330LHHXG1_X_EQ_X; + break; + case ASM330LHHXG1_X_EQ_MIN_X: + *val = ASM330LHHXG1_X_EQ_MIN_X; + break; + case ASM330LHHXG1_X_EQ_MIN_Z: + *val = ASM330LHHXG1_X_EQ_MIN_Z; + break; + case ASM330LHHXG1_X_EQ_Z: + *val = ASM330LHHXG1_X_EQ_Z; + break; + default: + *val = ASM330LHHXG1_X_EQ_Y; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHHXG1_finite_state_machine + * @brief This section groups all the functions that manage the + * state_machine. + * @{ + * + */ + +/** + * @brief FSM status register[get] + * + * @param ctx read / write interface definitions + * @param val register ASM330LHHXG1_FSM_STATUS_A_MAINPAGE, + * ASM330LHHXG1_FSM_STATUS_B_MAINPAGE + * + */ +int32_t asm330lhhxg1_fsm_status_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_fsm_status_t *val) +{ + asm330lhhxg1_fsm_status_a_mainpage_t status_a; + asm330lhhxg1_fsm_status_b_mainpage_t status_b; + int32_t ret; + + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_STATUS_A_MAINPAGE, + (uint8_t *)&status_a, 1); + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_STATUS_B_MAINPAGE, + (uint8_t *)&status_b, 1); + + val->fsm1 = status_a.is_fsm1; + val->fsm2 = status_a.is_fsm2; + val->fsm3 = status_a.is_fsm3; + val->fsm4 = status_a.is_fsm4; + val->fsm5 = status_a.is_fsm5; + val->fsm6 = status_a.is_fsm6; + val->fsm7 = status_a.is_fsm7; + val->fsm8 = status_a.is_fsm8; + val->fsm9 = status_b.is_fsm9; + val->fsm10 = status_b.is_fsm10; + val->fsm11 = status_b.is_fsm11; + val->fsm12 = status_b.is_fsm12; + val->fsm13 = status_b.is_fsm13; + val->fsm14 = status_b.is_fsm14; + val->fsm15 = status_b.is_fsm15; + val->fsm16 = status_b.is_fsm16; + return ret; +} + +/** + * @brief prgsens_out: [get] Output value of all FSMs. + * + * @param ctx_t *ctx: read / write interface definitions + * @param uint8_t * : buffer that stores data read + * + */ +int32_t asm330lhhxg1_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_OUTS1, buff, 16); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Interrupt status bit for FSM long counter timeout interrupt + * event.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of is_fsm_lc in reg EMB_FUNC_STATUS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, + uint8_t *val) +{ + asm330lhhxg1_emb_func_status_t emb_func_status; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_STATUS, + (uint8_t *)&emb_func_status, 1); + } + if (ret == 0) + { + *val = emb_func_status.is_fsm_lc; + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +int32_t asm330lhhxg1_emb_func_clk_dis_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_page_sel_t page_sel; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + + page_sel.emb_func_clk_dis = val; + } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + + return ret; +} + +int32_t asm330lhhxg1_emb_func_clk_dis_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_page_sel_t page_sel; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_SEL, + (uint8_t *)&page_sel, 1); + + *val = page_sel.emb_func_clk_dis; + } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + + return ret; +} + +/** + * @brief Embedded final state machine functions mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fsm_en in reg EMB_FUNC_EN_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + int32_t ret; + asm330lhhxg1_emb_func_en_b_t emb_func_en_b; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + emb_func_en_b.fsm_en = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Embedded final state machine functions mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of fsm_en in reg EMB_FUNC_EN_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + int32_t ret; + asm330lhhxg1_emb_func_en_b_t emb_func_en_b; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + *val = emb_func_en_b.fsm_en; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Embedded final state machine functions mode.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fsm_enable_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_emb_fsm_enable_t *val) +{ + asm330lhhxg1_emb_func_en_b_t emb_func_en_b; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FSM_ENABLE_A, + (uint8_t *)&val->fsm_enable_a, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FSM_ENABLE_B, + (uint8_t *)&val->fsm_enable_b, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + if ((val->fsm_enable_a.fsm1_en | + val->fsm_enable_a.fsm2_en | + val->fsm_enable_a.fsm3_en | + val->fsm_enable_a.fsm4_en | + val->fsm_enable_a.fsm5_en | + val->fsm_enable_a.fsm6_en | + val->fsm_enable_a.fsm7_en | + val->fsm_enable_a.fsm8_en | + val->fsm_enable_b.fsm9_en | + val->fsm_enable_b.fsm10_en | + val->fsm_enable_b.fsm11_en | + val->fsm_enable_b.fsm12_en | + val->fsm_enable_b.fsm13_en | + val->fsm_enable_b.fsm14_en | + val->fsm_enable_b.fsm15_en | + val->fsm_enable_b.fsm16_en) != PROPERTY_DISABLE) + { + emb_func_en_b.fsm_en = PROPERTY_ENABLE; + } + else + { + emb_func_en_b.fsm_en = PROPERTY_DISABLE; + } + } + if (ret == 0) + { + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_EN_B, + (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Embedded final state machine functions mode.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fsm_enable_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_emb_fsm_enable_t *val) +{ + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_ENABLE_A, + (uint8_t *)&val->fsm_enable_a, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_ENABLE_B, + (uint8_t *)&val->fsm_enable_b, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an + * unsigned integer value (16-bit format).[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FSM_LONG_COUNTER_L, buff, 2); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an + * unsigned integer value (16-bit format).[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_LONG_COUNTER_L, buff, 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Clear FSM long counter value.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fsm_lc_clr in reg + * FSM_LONG_COUNTER_CLEAR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_long_clr_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_fsm_lc_clr_t val) +{ + asm330lhhxg1_fsm_long_counter_clear_t fsm_long_counter_clear; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_LONG_COUNTER_CLEAR, + (uint8_t *)&fsm_long_counter_clear, 1); + } + if (ret == 0) + { + fsm_long_counter_clear.fsm_lc_clr = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FSM_LONG_COUNTER_CLEAR, + (uint8_t *)&fsm_long_counter_clear, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Clear FSM long counter value.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of fsm_lc_clr in reg FSM_LONG_COUNTER_CLEAR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_long_clr_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_fsm_lc_clr_t *val) +{ + asm330lhhxg1_fsm_long_counter_clear_t fsm_long_counter_clear; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_LONG_COUNTER_CLEAR, + (uint8_t *)&fsm_long_counter_clear, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + switch (fsm_long_counter_clear.fsm_lc_clr) + { + case ASM330LHHXG1_LC_NORMAL: + *val = ASM330LHHXG1_LC_NORMAL; + break; + case ASM330LHHXG1_LC_CLEAR: + *val = ASM330LHHXG1_LC_CLEAR; + break; + case ASM330LHHXG1_LC_CLEAR_DONE: + *val = ASM330LHHXG1_LC_CLEAR_DONE; + break; + default: + *val = ASM330LHHXG1_LC_NORMAL; + break; + } + return ret; +} + +/** + * @brief Finite State Machine ODR configuration.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fsm_data_rate_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_fsm_odr_t val) +{ + asm330lhhxg1_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_ODR_CFG_B, + (uint8_t *)&emb_func_odr_cfg_b, 1); + } + if (ret == 0) + { + emb_func_odr_cfg_b.not_used_01 = 3; /* set default values */ + emb_func_odr_cfg_b.not_used_02 = 1; /* set default values */ + emb_func_odr_cfg_b.fsm_odr = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_ODR_CFG_B, + (uint8_t *)&emb_func_odr_cfg_b, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Finite State Machine ODR configuration.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fsm_data_rate_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_fsm_odr_t *val) +{ + asm330lhhxg1_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_ODR_CFG_B, + (uint8_t *)&emb_func_odr_cfg_b, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + switch (emb_func_odr_cfg_b.fsm_odr) + { + case ASM330LHHXG1_ODR_FSM_12Hz5: + *val = ASM330LHHXG1_ODR_FSM_12Hz5; + break; + case ASM330LHHXG1_ODR_FSM_26Hz: + *val = ASM330LHHXG1_ODR_FSM_26Hz; + break; + case ASM330LHHXG1_ODR_FSM_52Hz: + *val = ASM330LHHXG1_ODR_FSM_52Hz; + break; + case ASM330LHHXG1_ODR_FSM_104Hz: + *val = ASM330LHHXG1_ODR_FSM_104Hz; + break; + default: + *val = ASM330LHHXG1_ODR_FSM_12Hz5; + break; + } + return ret; +} + +/** + * @brief FSM initialization request.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fsm_init in reg FSM_INIT + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_emb_func_init_b_t emb_func_init_b; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); + } + if (ret == 0) + { + emb_func_init_b.fsm_init = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief FSM initialization request.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of fsm_init in reg FSM_INIT + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_emb_func_init_b_t emb_func_init_b; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); + } + if (ret == 0) + { + *val = emb_func_init_b.fsm_init; + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief FSM long counter timeout register (r/w). The long counter + * timeout value is an unsigned integer value (16-bit format). + * When the long counter value reached this value, the FSM + * generates an interrupt.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_FSM_LC_TIMEOUT_L, &buff[0]); + + if (ret == 0) + { + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_FSM_LC_TIMEOUT_H, + &buff[1]); + } + return ret; +} + +/** + * @brief FSM long counter timeout register (r/w). The long counter + * timeout value is an unsigned integer value (16-bit format). + * When the long counter value reached this value, the FSM generates + * an interrupt.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_FSM_LC_TIMEOUT_L, &buff[0]); + + if (ret == 0) + { + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_FSM_LC_TIMEOUT_H, + &buff[1]); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } + return ret; +} + +/** + * @brief FSM number of programs register.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_FSM_PROGRAMS, buff); + + if (ret == 0) + { + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_FSM_PROGRAMS + 0x01U, + buff); + } + return ret; +} + +/** + * @brief FSM number of programs register.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_FSM_PROGRAMS, buff); + + return ret; +} + +/** + * @brief FSM start address register (r/w). First available address is + * 0x033C.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_FSM_START_ADD_L, &buff[0]); + if (ret == 0) + { + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_FSM_START_ADD_H, &buff[1]); + } + return ret; +} + +/** + * @brief FSM start address register (r/w). First available address + * is 0x033C.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_FSM_START_ADD_L, &buff[0]); + if (ret == 0) + { + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_FSM_START_ADD_H, &buff[1]); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @addtogroup Machine Learning Core + * @brief This section group all the functions concerning the + * usage of Machine Learning Core + * @{ + * + */ + +/** + * @brief Enable Machine Learning Core.[set] + * + * @param ctx read / write interface definitions + * @param val change the values of mlc_en in + * reg EMB_FUNC_EN_B and mlc_init + * in EMB_FUNC_INIT_B + * + */ +int32_t asm330lhhxg1_mlc_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_emb_func_en_b_t reg; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_EN_B, (uint8_t *)®, 1); + } + if (ret == 0) + { + reg.mlc_en = val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_EN_B, (uint8_t *)®, 1); + } + if ((val != PROPERTY_DISABLE) && (ret == 0)) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_INIT_B, + (uint8_t *)®, 1); + if (ret == 0) + { + reg.mlc_en = val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_INIT_B, + (uint8_t *)®, 1); + } + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Enable Machine Learning Core.[get] + * + * @param ctx read / write interface definitions + * @param val Get the values of mlc_en in + * reg EMB_FUNC_EN_B + * + */ +int32_t asm330lhhxg1_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_emb_func_en_b_t reg; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_EN_B, (uint8_t *)®, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + *val = reg.mlc_en; + } + return ret; +} + +/** + * @brief Machine Learning Core status register[get] + * + * @param ctx read / write interface definitions + * @param val register MLC_STATUS_MAINPAGE + * + */ +int32_t asm330lhhxg1_mlc_status_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_mlc_status_mainpage_t *val) +{ + return asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MLC_STATUS_MAINPAGE, + (uint8_t *) val, 1); +} + +/** + * @brief Machine Learning Core data rate selection.[set] + * + * @param ctx read / write interface definitions + * @param val get the values of mlc_odr in + * reg EMB_FUNC_ODR_CFG_C + * + */ +int32_t asm330lhhxg1_mlc_data_rate_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_mlc_odr_t val) +{ + asm330lhhxg1_emb_func_odr_cfg_c_t reg; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_ODR_CFG_C, + (uint8_t *)®, 1); + } + if (ret == 0) + { + reg.mlc_odr = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_ODR_CFG_C, + (uint8_t *)®, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + + return ret; +} + +/** + * @brief Machine Learning Core data rate selection.[get] + * + * @param ctx read / write interface definitions + * @param val change the values of mlc_odr in + * reg EMB_FUNC_ODR_CFG_C + * + */ +int32_t asm330lhhxg1_mlc_data_rate_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_mlc_odr_t *val) +{ + asm330lhhxg1_emb_func_odr_cfg_c_t reg; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_ODR_CFG_C, + (uint8_t *)®, 1); + } + if (ret == 0) + { + switch (reg.mlc_odr) + { + case ASM330LHHXG1_ODR_PRGS_12Hz5: + *val = ASM330LHHXG1_ODR_PRGS_12Hz5; + break; + case ASM330LHHXG1_ODR_PRGS_26Hz: + *val = ASM330LHHXG1_ODR_PRGS_26Hz; + break; + case ASM330LHHXG1_ODR_PRGS_52Hz: + *val = ASM330LHHXG1_ODR_PRGS_52Hz; + break; + case ASM330LHHXG1_ODR_PRGS_104Hz: + *val = ASM330LHHXG1_ODR_PRGS_104Hz; + break; + default: + *val = ASM330LHHXG1_ODR_PRGS_12Hz5; + break; + } + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief MLC initialization request.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of mlc_init + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_mlc_init_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_emb_func_init_b_t emb_func_init_b; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); + } + if (ret == 0) + { + emb_func_init_b.mlc_init = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); + } + + ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + + return ret; +} + +/** + * @brief MLC initialization request.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of mlc_init + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_mlc_init_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_emb_func_init_b_t emb_func_init_b; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_INIT_B, + (uint8_t *)&emb_func_init_b, 1); + } + if (ret == 0) + { + *val = emb_func_init_b.mlc_init; + } + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + + return ret; +} + +/** + * @brief prgsens_out: [get] Output value of all MLCx decision trees. + * + * @param ctx_t *ctx: read / write interface definitions + * @param uint8_t * : buffer that stores data read + * + */ +int32_t asm330lhhxg1_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MLC0_SRC, buff, 8); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief External magnetometer sensitivity value register for + * Machine Learning Core.[set] + * + * @param ctx read / write interface definitions + * @param buff buffer that contains data to write + * + */ +int32_t asm330lhhxg1_mlc_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MLC_MAG_SENSITIVITY_L, + &buff[0]); + if (ret == 0) + { + ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MLC_MAG_SENSITIVITY_H, + &buff[1]); + } + return ret; +} + +/** + * @brief External magnetometer sensitivity value register for + * Machine Learning Core.[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * + */ +int32_t asm330lhhxg1_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MLC_MAG_SENSITIVITY_L, + &buff[0]); + if (ret == 0) + { + ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MLC_MAG_SENSITIVITY_H, + &buff[1]); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup ASM330LHHXG1_Sensor_hub + * @brief This section groups all the functions that manage the + * sensor hub. + * @{ + * + */ + +/** + * @brief Sensor hub output registers.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Structure of registers from SENSOR_HUB_1 to SENSOR_HUB_18 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_read_data_raw_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_emb_sh_read_t *val) +{ + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SENSOR_HUB_1, (uint8_t *)val, 18); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Number of external sensors to be read by the sensor hub.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of aux_sens_on in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_slave_connected_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_aux_sens_on_t val) +{ + asm330lhhxg1_master_config_t master_config; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + master_config.aux_sens_on = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Number of external sensors to be read by the sensor hub.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of aux_sens_on in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_slave_connected_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_aux_sens_on_t *val) +{ + asm330lhhxg1_master_config_t master_config; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + switch (master_config.aux_sens_on) + { + case ASM330LHHXG1_SLV_0: + *val = ASM330LHHXG1_SLV_0; + break; + case ASM330LHHXG1_SLV_0_1: + *val = ASM330LHHXG1_SLV_0_1; + break; + case ASM330LHHXG1_SLV_0_1_2: + *val = ASM330LHHXG1_SLV_0_1_2; + break; + case ASM330LHHXG1_SLV_0_1_2_3: + *val = ASM330LHHXG1_SLV_0_1_2_3; + break; + default: + *val = ASM330LHHXG1_SLV_0; + break; + } + return ret; +} + +/** + * @brief Sensor hub I2C master enable.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of master_on in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_master_config_t master_config; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + master_config.master_on = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Sensor hub I2C master enable.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of master_on in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_master_config_t master_config; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + *val = master_config.master_on; + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Master I2C pull-up enable.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of shub_pu_en in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_pin_mode_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_shub_pu_en_t val) +{ + asm330lhhxg1_master_config_t master_config; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + master_config.shub_pu_en = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Master I2C pull-up enable.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of shub_pu_en in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_pin_mode_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_shub_pu_en_t *val) +{ + asm330lhhxg1_master_config_t master_config; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + switch (master_config.shub_pu_en) + { + case ASM330LHHXG1_EXT_PULL_UP: + *val = ASM330LHHXG1_EXT_PULL_UP; + break; + case ASM330LHHXG1_INTERNAL_PULL_UP: + *val = ASM330LHHXG1_INTERNAL_PULL_UP; + break; + default: + *val = ASM330LHHXG1_EXT_PULL_UP; + break; + } + return ret; +} + +/** + * @brief I2C interface pass-through.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of pass_through_mode in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + asm330lhhxg1_master_config_t master_config; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + master_config.pass_through_mode = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief I2C interface pass-through.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of pass_through_mode in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_master_config_t master_config; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + *val = master_config.pass_through_mode; + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Sensor hub trigger signal selection.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of start_config in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_syncro_mode_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_start_config_t val) +{ + asm330lhhxg1_master_config_t master_config; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + master_config.start_config = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Sensor hub trigger signal selection.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of start_config in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_syncro_mode_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_start_config_t *val) +{ + asm330lhhxg1_master_config_t master_config; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + switch (master_config.start_config) + { + case ASM330LHHXG1_EXT_ON_INT2_PIN: + *val = ASM330LHHXG1_EXT_ON_INT2_PIN; + break; + case ASM330LHHXG1_XL_GY_DRDY: + *val = ASM330LHHXG1_XL_GY_DRDY; + break; + default: + *val = ASM330LHHXG1_EXT_ON_INT2_PIN; + break; + } + return ret; +} + +/** + * @brief Slave 0 write operation is performed only at the first sensor + * hub cycle.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of write_once in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_write_mode_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_write_once_t val) +{ + asm330lhhxg1_master_config_t master_config; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + master_config.write_once = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Slave 0 write operation is performed only at the first sensor + * hub cycle.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of write_once in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_write_mode_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_write_once_t *val) +{ + asm330lhhxg1_master_config_t master_config; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + switch (master_config.write_once) + { + case ASM330LHHXG1_EACH_SH_CYCLE: + *val = ASM330LHHXG1_EACH_SH_CYCLE; + break; + case ASM330LHHXG1_ONLY_FIRST_CYCLE: + *val = ASM330LHHXG1_ONLY_FIRST_CYCLE; + break; + default: + *val = ASM330LHHXG1_EACH_SH_CYCLE; + break; + } + return ret; +} + +/** + * @brief Reset Master logic and output registers.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_reset_set(const stmdev_ctx_t *ctx) +{ + asm330lhhxg1_master_config_t master_config; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + master_config.rst_master_regs = PROPERTY_ENABLE; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + master_config.rst_master_regs = PROPERTY_DISABLE; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Reset Master logic and output registers.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of rst_master_regs in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + asm330lhhxg1_master_config_t master_config; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG, + (uint8_t *)&master_config, 1); + *val = master_config.rst_master_regs; + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Rate at which the master communicates.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Change the values of shub_odr in reg SLV0_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_data_rate_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_shub_odr_t val) +{ + asm330lhhxg1_slv0_config_t slv0_config; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV0_CONFIG, + (uint8_t *)&slv0_config, 1); + } + if (ret == 0) + { + slv0_config.shub_odr = (uint8_t)val; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV0_CONFIG, + (uint8_t *)&slv0_config, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Rate at which the master communicates.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Get the values of shub_odr in reg slv1_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_data_rate_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_shub_odr_t *val) +{ + asm330lhhxg1_slv0_config_t slv0_config; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV0_CONFIG, + (uint8_t *)&slv0_config, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + switch (slv0_config.shub_odr) + { + case ASM330LHHXG1_SH_ODR_104Hz: + *val = ASM330LHHXG1_SH_ODR_104Hz; + break; + case ASM330LHHXG1_SH_ODR_52Hz: + *val = ASM330LHHXG1_SH_ODR_52Hz; + break; + case ASM330LHHXG1_SH_ODR_26Hz: + *val = ASM330LHHXG1_SH_ODR_26Hz; + break; + case ASM330LHHXG1_SH_ODR_13Hz: + *val = ASM330LHHXG1_SH_ODR_13Hz; + break; + default: + *val = ASM330LHHXG1_SH_ODR_104Hz; + break; + } + return ret; +} + +/** + * @brief Configure slave 0 for perform a write.[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Structure that contain + * - uint8_t slv0_add; 8 bit i2c device address + * - uint8_t slv0_subadd; 8 bit register device address + * - uint8_t slv0_data; 8 bit data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_cfg_write(const stmdev_ctx_t *ctx, + asm330lhhxg1_sh_cfg_write_t *val) +{ + asm330lhhxg1_slv0_add_t slv0_add; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + + if (ret == 0) + { + slv0_add.slave0 = (uint8_t)(val->slv0_add >> 1); + slv0_add.rw_0 = 0; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV0_ADD, + (uint8_t *) & (slv0_add), 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV0_SUBADD, + (uint8_t *) & (val->slv0_subadd), 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_DATAWRITE_SLV0, + (uint8_t *) & (val->slv0_data), 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Configure slave 0 for perform a write/read.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Structure that contain + * - uint8_t slv_add; 8 bit i2c device address + * - uint8_t slv_subadd; 8 bit register device address + * - uint8_t slv_len; num of bit to read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, + asm330lhhxg1_sh_cfg_read_t *val) +{ + asm330lhhxg1_slv0_config_t slv0_config; + asm330lhhxg1_slv0_add_t slv0_add; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + + if (ret == 0) + { + slv0_add.slave0 = (uint8_t) val->slv_add >> 1; + slv0_add.rw_0 = 1; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV0_ADD, + (uint8_t *) & (slv0_add), 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV0_SUBADD, + &(val->slv_subadd), 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV0_CONFIG, + (uint8_t *)&slv0_config, 1); + } + if (ret == 0) + { + slv0_config.slave0_numop = val->slv_len; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV0_CONFIG, + (uint8_t *)&slv0_config, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Configure slave 0 for perform a write/read.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Structure that contain + * - uint8_t slv_add; 8 bit i2c device address + * - uint8_t slv_subadd; 8 bit register device address + * - uint8_t slv_len; num of bit to read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, + asm330lhhxg1_sh_cfg_read_t *val) +{ + asm330lhhxg1_slv1_config_t slv1_config; + asm330lhhxg1_slv1_add_t slv1_add; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + if (ret == 0) + { + slv1_add.slave1_add = (uint8_t)(val->slv_add >> 1); + slv1_add.r_1 = 1; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV1_ADD, (uint8_t *)&slv1_add, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV1_SUBADD, + &(val->slv_subadd), 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV1_CONFIG, + (uint8_t *)&slv1_config, 1); + } + if (ret == 0) + { + slv1_config.slave1_numop = val->slv_len; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV1_CONFIG, + (uint8_t *)&slv1_config, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Configure slave 2 for perform a write/read.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Structure that contain + * - uint8_t slv_add; 8 bit i2c device address + * - uint8_t slv_subadd; 8 bit register device address + * - uint8_t slv_len; num of bit to read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, + asm330lhhxg1_sh_cfg_read_t *val) +{ + asm330lhhxg1_slv2_config_t slv2_config; + asm330lhhxg1_slv2_add_t slv2_add; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + + if (ret == 0) + { + slv2_add.slave2_add = (uint8_t)(val->slv_add >> 1); + slv2_add.r_2 = 1; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV2_ADD, + (uint8_t *)&slv2_add, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV2_SUBADD, + (uint8_t *) & (val->slv_subadd), 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV2_CONFIG, + (uint8_t *)&slv2_config, 1); + } + if (ret == 0) + { + slv2_config.slave2_numop = val->slv_len; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV2_CONFIG, + (uint8_t *)&slv2_config, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Configure slave 3 for perform a write/read.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Structure that contain + * - uint8_t slv_add; 8 bit i2c device address + * - uint8_t slv_subadd; 8 bit register device address + * - uint8_t slv_len; num of bit to read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, + asm330lhhxg1_sh_cfg_read_t *val) +{ + asm330lhhxg1_slv3_config_t slv3_config; + asm330lhhxg1_slv3_add_t slv3_add; + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + + if (ret == 0) + { + slv3_add.slave3_add = (uint8_t)(val->slv_add >> 1); + slv3_add.r_3 = 1; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV3_ADD, + (uint8_t *)&slv3_add, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV3_SUBADD, + &(val->slv_subadd), 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV3_CONFIG, + (uint8_t *)&slv3_config, 1); + } + if (ret == 0) + { + slv3_config.slave3_numop = val->slv_len; + ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV3_CONFIG, + (uint8_t *)&slv3_config, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @brief Sensor hub source register.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val Registers from STATUS_MASTER + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t asm330lhhxg1_sh_status_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_status_master_t *val) +{ + int32_t ret; + + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK); + + if (ret == 0) + { + ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_STATUS_MASTER, (uint8_t *)val, 1); + } + if (ret == 0) + { + ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK); + } + return ret; +} + +/** + * @} + * + */ + +/** + * @} + * + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/asm330lhhxg1_STdC/driver/asm330lhhxg1_reg.h b/sensor/stmemsc/asm330lhhxg1_STdC/driver/asm330lhhxg1_reg.h new file mode 100644 index 00000000..e2c1bb1f --- /dev/null +++ b/sensor/stmemsc/asm330lhhxg1_STdC/driver/asm330lhhxg1_reg.h @@ -0,0 +1,3555 @@ +/* + ****************************************************************************** + * @file asm330lhhxg1_reg.h + * @author Sensor Solutions Software Team + * @brief This file contains all the functions prototypes for the + * asm330lhhxg1_reg.c driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef ASM330LHHXG1_REGS_H +#define ASM330LHHXG1_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include + +/** @addtogroup ASM330LHHXG1 + * @{ + * + */ + +/** @defgroup Endianness definitions + * @{ + * + */ + +#ifndef DRV_BYTE_ORDER +#ifndef __BYTE_ORDER__ + +#define DRV_LITTLE_ENDIAN 1234 +#define DRV_BIG_ENDIAN 4321 + +/** if _BYTE_ORDER is not defined, choose the endianness of your architecture + * by uncommenting the define which fits your platform endianness + */ +//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN +#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN + +#else /* defined __BYTE_ORDER__ */ + +#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ +#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ +#define DRV_BYTE_ORDER __BYTE_ORDER__ + +#endif /* __BYTE_ORDER__*/ +#endif /* DRV_BYTE_ORDER */ + +/** + * @} + * + */ + +/** @defgroup STMicroelectronics sensors common types + * @{ + * + */ + +#ifndef MEMS_SHARED_TYPES +#define MEMS_SHARED_TYPES + +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} bitwise_t; + +#define PROPERTY_DISABLE (0U) +#define PROPERTY_ENABLE (1U) + +/** @addtogroup Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); +typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); + +typedef struct +{ + /** Component mandatory fields **/ + stmdev_write_ptr write_reg; + stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; + /** Customizable optional pointer **/ + void *handle; +} stmdev_ctx_t; + +/** + * @} + * + */ + +#endif /* MEMS_SHARED_TYPES */ + +#ifndef MEMS_UCF_SHARED_TYPES +#define MEMS_UCF_SHARED_TYPES + +/** @defgroup Generic address-data structure definition + * @brief This structure is useful to load a predefined configuration + * of a sensor. + * You can create a sensor configuration by your own or using + * Unico / Unicleo tools available on STMicroelectronics + * web site. + * + * @{ + * + */ + +typedef struct +{ + uint8_t address; + uint8_t data; +} ucf_line_t; + +/** + * @} + * + */ + +#endif /* MEMS_UCF_SHARED_TYPES */ + +/** + * @} + * + */ + +/** @defgroup ASM330LHHXG1 Infos + * @{ + * + */ + +/** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ +#define ASM330LHHXG1_I2C_ADD_L 0xD5U +#define ASM330LHHXG1_I2C_ADD_H 0xD7U + +/** Device Identification (Who am I) **/ +#define ASM330LHHXG1_ID 0x6BU + +/** + * @} + * + */ + +#define ASM330LHHXG1_FUNC_CFG_ACCESS 0x01U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 6; + uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */ +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */ + uint8_t not_used_01 : 6; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_func_cfg_access_t; + +#define ASM330LHHXG1_PIN_CTRL 0x02U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 6; + uint8_t sdo_pu_en : 1; + uint8_t not_used_02 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 1; + uint8_t sdo_pu_en : 1; + uint8_t not_used_01 : 6; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_pin_ctrl_t; + +#define ASM330LHHXG1_FIFO_CTRL1 0x07U +typedef struct +{ + uint8_t wtm : 8; +} asm330lhhxg1_fifo_ctrl1_t; + +#define ASM330LHHXG1_FIFO_CTRL2 0x08U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wtm : 1; + uint8_t not_used_01 : 3; + uint8_t odrchg_en : 1; + uint8_t not_used_02 : 2; + uint8_t stop_on_wtm : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t stop_on_wtm : 1; + uint8_t not_used_02 : 2; + uint8_t odrchg_en : 1; + uint8_t not_used_01 : 3; + uint8_t wtm : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fifo_ctrl2_t; + +#define ASM330LHHXG1_FIFO_CTRL3 0x09U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bdr_xl : 4; + uint8_t bdr_gy : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bdr_gy : 4; + uint8_t bdr_xl : 4; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fifo_ctrl3_t; + +#define ASM330LHHXG1_FIFO_CTRL4 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_mode : 3; + uint8_t not_used_01 : 1; + uint8_t odr_t_batch : 2; + uint8_t dec_ts_batch : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dec_ts_batch : 2; + uint8_t odr_t_batch : 2; + uint8_t not_used_01 : 1; + uint8_t fifo_mode : 3; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fifo_ctrl4_t; + +#define ASM330LHHXG1_COUNTER_BDR_REG1 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t cnt_bdr_th : 3; + uint8_t not_used_01 : 2; + uint8_t trig_counter_bdr : 1; + uint8_t rst_counter_bdr : 1; + uint8_t dataready_pulsed : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dataready_pulsed : 1; + uint8_t rst_counter_bdr : 1; + uint8_t trig_counter_bdr : 1; + uint8_t not_used_01 : 2; + uint8_t cnt_bdr_th : 3; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_counter_bdr_reg1_t; + +#define ASM330LHHXG1_COUNTER_BDR_REG2 0x0CU +typedef struct +{ + uint8_t cnt_bdr_th : 8; +} asm330lhhxg1_counter_bdr_reg2_t; + +#define ASM330LHHXG1_INT1_CTRL 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_drdy_xl : 1; + uint8_t int1_drdy_g : 1; + uint8_t int1_boot : 1; + uint8_t int1_fifo_th : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_fifo_full : 1; + uint8_t int1_cnt_bdr : 1; + uint8_t den_drdy_flag : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t den_drdy_flag : 1; + uint8_t int1_cnt_bdr : 1; + uint8_t int1_fifo_full : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_fifo_th : 1; + uint8_t int1_boot : 1; + uint8_t int1_drdy_g : 1; + uint8_t int1_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_int1_ctrl_t; + +#define ASM330LHHXG1_INT2_CTRL 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_drdy_xl : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_temp : 1; + uint8_t int2_fifo_th : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_fifo_full : 1; + uint8_t int2_cnt_bdr : 1; + uint8_t not_used_01 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 1; + uint8_t int2_cnt_bdr : 1; + uint8_t int2_fifo_full : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_fifo_th : 1; + uint8_t int2_drdy_temp : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_int2_ctrl_t; + +#define ASM330LHHXG1_WHO_AM_I 0x0FU + +#define ASM330LHHXG1_CTRL1_XL 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 1; + uint8_t lpf2_xl_en : 1; + uint8_t fs_xl : 2; + uint8_t odr_xl : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t odr_xl : 4; + uint8_t fs_xl : 2; + uint8_t lpf2_xl_en : 1; + uint8_t not_used_01 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_ctrl1_xl_t; + +#define ASM330LHHXG1_CTRL2_G 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */ + uint8_t odr_g : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t odr_g : 4; + uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */ +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_ctrl2_g_t; + +#define ASM330LHHXG1_CTRL3_C 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sw_reset : 1; + uint8_t not_used_01 : 1; + uint8_t if_inc : 1; + uint8_t sim : 1; + uint8_t pp_od : 1; + uint8_t h_lactive : 1; + uint8_t bdu : 1; + uint8_t boot : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t boot : 1; + uint8_t bdu : 1; + uint8_t h_lactive : 1; + uint8_t pp_od : 1; + uint8_t sim : 1; + uint8_t if_inc : 1; + uint8_t not_used_01 : 1; + uint8_t sw_reset : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_ctrl3_c_t; + +#define ASM330LHHXG1_CTRL4_C 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 1; + uint8_t lpf1_sel_g : 1; + uint8_t i2c_disable : 1; + uint8_t drdy_mask : 1; + uint8_t not_used_02 : 1; + uint8_t int2_on_int1 : 1; + uint8_t sleep_g : 1; + uint8_t not_used_03 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_03 : 1; + uint8_t sleep_g : 1; + uint8_t int2_on_int1 : 1; + uint8_t not_used_02 : 1; + uint8_t drdy_mask : 1; + uint8_t i2c_disable : 1; + uint8_t lpf1_sel_g : 1; + uint8_t not_used_01 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_ctrl4_c_t; + +#define ASM330LHHXG1_CTRL5_C 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t st_xl : 2; + uint8_t st_g : 2; + uint8_t not_used_01 : 1; + uint8_t rounding : 2; + uint8_t not_used_02 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 1; + uint8_t rounding : 2; + uint8_t not_used_01 : 1; + uint8_t st_g : 2; + uint8_t st_xl : 2; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_ctrl5_c_t; + +#define ASM330LHHXG1_CTRL6_C 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ftype : 3; + uint8_t usr_off_w : 1; + uint8_t xl_hm_mode : 1; + uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ + uint8_t xl_hm_mode : 1; + uint8_t usr_off_w : 1; + uint8_t ftype : 3; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_ctrl6_c_t; + +#define ASM330LHHXG1_CTRL7_G 0x16U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_00 : 1; + uint8_t usr_off_on_out : 1; + uint8_t not_used_01 : 2; + uint8_t hpm_g : 2; + uint8_t hp_en_g : 1; + uint8_t g_hm_mode : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t g_hm_mode : 1; + uint8_t hp_en_g : 1; + uint8_t hpm_g : 2; + uint8_t not_used_01 : 2; + uint8_t usr_off_on_out : 1; + uint8_t not_used_00 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_ctrl7_g_t; + +#define ASM330LHHXG1_CTRL8_XL 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t low_pass_on_6d : 1; + uint8_t not_used_01 : 1; + uint8_t hp_slope_xl_en : 1; + uint8_t fastsettl_mode_xl : 1; + uint8_t hp_ref_mode_xl : 1; + uint8_t hpcf_xl : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t hpcf_xl : 3; + uint8_t hp_ref_mode_xl : 1; + uint8_t fastsettl_mode_xl : 1; + uint8_t hp_slope_xl_en : 1; + uint8_t not_used_01 : 1; + uint8_t low_pass_on_6d : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_ctrl8_xl_t; + +#define ASM330LHHXG1_CTRL9_XL 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 1; + uint8_t i3c_disable : 1; + uint8_t den_lh : 1; + uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ + uint8_t den_z : 1; + uint8_t den_y : 1; + uint8_t den_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t den_x : 1; + uint8_t den_y : 1; + uint8_t den_z : 1; + uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ + uint8_t den_lh : 1; + uint8_t i3c_disable : 1; + uint8_t not_used_01 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_ctrl9_xl_t; + +#define ASM330LHHXG1_CTRL10_C 0x19U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 5; + uint8_t timestamp_en : 1; + uint8_t not_used_02 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 2; + uint8_t timestamp_en : 1; + uint8_t not_used_01 : 5; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_ctrl10_c_t; + +#define ASM330LHHXG1_ALL_INT_SRC 0x1AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ia : 1; + uint8_t wu_ia : 1; + uint8_t not_used_00 : 2; + uint8_t d6d_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t not_used_01 : 1; + uint8_t timestamp_endcount : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp_endcount : 1; + uint8_t not_used_01 : 1; + uint8_t sleep_change_ia : 1; + uint8_t d6d_ia : 1; + uint8_t not_used_00 : 2; + uint8_t wu_ia : 1; + uint8_t ff_ia : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_all_int_src_t; + +#define ASM330LHHXG1_WAKE_UP_SRC 0x1BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t z_wu : 1; + uint8_t y_wu : 1; + uint8_t x_wu : 1; + uint8_t wu_ia : 1; + uint8_t sleep_state : 1; + uint8_t ff_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t not_used_01 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 1; + uint8_t sleep_change_ia : 1; + uint8_t ff_ia : 1; + uint8_t sleep_state : 1; + uint8_t wu_ia : 1; + uint8_t x_wu : 1; + uint8_t y_wu : 1; + uint8_t z_wu : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_wake_up_src_t; + +#define ASM330LHHXG1_D6D_SRC 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xl : 1; + uint8_t xh : 1; + uint8_t yl : 1; + uint8_t yh : 1; + uint8_t zl : 1; + uint8_t zh : 1; + uint8_t d6d_ia : 1; + uint8_t den_drdy : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t den_drdy : 1; + uint8_t d6d_ia : 1; + uint8_t zh : 1; + uint8_t zl : 1; + uint8_t yh : 1; + uint8_t yl : 1; + uint8_t xh : 1; + uint8_t xl : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_d6d_src_t; + +#define ASM330LHHXG1_STATUS_REG 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xlda : 1; + uint8_t gda : 1; + uint8_t tda : 1; + uint8_t not_used_01 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 5; + uint8_t tda : 1; + uint8_t gda : 1; + uint8_t xlda : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_status_reg_t; + +#define ASM330LHHXG1_OUT_TEMP_L 0x20U +#define ASM330LHHXG1_OUT_TEMP_H 0x21U +#define ASM330LHHXG1_OUTX_L_G 0x22U +#define ASM330LHHXG1_OUTX_H_G 0x23U +#define ASM330LHHXG1_OUTY_L_G 0x24U +#define ASM330LHHXG1_OUTY_H_G 0x25U +#define ASM330LHHXG1_OUTZ_L_G 0x26U +#define ASM330LHHXG1_OUTZ_H_G 0x27U +#define ASM330LHHXG1_OUTX_L_A 0x28U +#define ASM330LHHXG1_OUTX_H_A 0x29U +#define ASM330LHHXG1_OUTY_L_A 0x2AU +#define ASM330LHHXG1_OUTY_H_A 0x2BU +#define ASM330LHHXG1_OUTZ_L_A 0x2CU +#define ASM330LHHXG1_OUTZ_H_A 0x2DU +#define ASM330LHHXG1_EMB_FUNC_STATUS_MAINPAGE 0x35U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 7; + uint8_t is_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm_lc : 1; + uint8_t not_used_01 : 7; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_emb_func_status_mainpage_t; + +#define ASM330LHHXG1_FSM_STATUS_A_MAINPAGE 0x36U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm8 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fsm_status_a_mainpage_t; + +#define ASM330LHHXG1_FSM_STATUS_B_MAINPAGE 0x37U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm9 : 1; + uint8_t is_fsm10 : 1; + uint8_t is_fsm11 : 1; + uint8_t is_fsm12 : 1; + uint8_t is_fsm13 : 1; + uint8_t is_fsm14 : 1; + uint8_t is_fsm15 : 1; + uint8_t is_fsm16 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm16 : 1; + uint8_t is_fsm15 : 1; + uint8_t is_fsm14 : 1; + uint8_t is_fsm13 : 1; + uint8_t is_fsm12 : 1; + uint8_t is_fsm11 : 1; + uint8_t is_fsm10 : 1; + uint8_t is_fsm9 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fsm_status_b_mainpage_t; + +#define ASM330LHHXG1_MLC_STATUS_MAINPAGE 0x38U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_mlc1 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc4 : 1; + uint8_t is_mlc5 : 1; + uint8_t is_mlc6 : 1; + uint8_t is_mlc7 : 1; + uint8_t is_mlc8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_mlc8 : 1; + uint8_t is_mlc7 : 1; + uint8_t is_mlc6 : 1; + uint8_t is_mlc5 : 1; + uint8_t is_mlc4 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_mlc_status_mainpage_t; + +#define ASM330LHHXG1_STATUS_MASTER_MAINPAGE 0x39U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sens_hub_endop : 1; + uint8_t not_used_01 : 2; + uint8_t slave0_nack : 1; + uint8_t slave1_nack : 1; + uint8_t slave2_nack : 1; + uint8_t slave3_nack : 1; + uint8_t wr_once_done : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t wr_once_done : 1; + uint8_t slave3_nack : 1; + uint8_t slave2_nack : 1; + uint8_t slave1_nack : 1; + uint8_t slave0_nack : 1; + uint8_t not_used_01 : 2; + uint8_t sens_hub_endop : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_status_master_mainpage_t; + +#define ASM330LHHXG1_FIFO_STATUS1 0x3AU +typedef struct +{ + uint8_t diff_fifo : 8; +} asm330lhhxg1_fifo_status1_t; + +#define ASM330LHHXG1_FIFO_STATUS2 0x3BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t diff_fifo : 2; + uint8_t not_used_01 : 1; + uint8_t over_run_latched : 1; + uint8_t counter_bdr_ia : 1; + uint8_t fifo_full_ia : 1; + uint8_t fifo_ovr_ia : 1; + uint8_t fifo_wtm_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_wtm_ia : 1; + uint8_t fifo_ovr_ia : 1; + uint8_t fifo_full_ia : 1; + uint8_t counter_bdr_ia : 1; + uint8_t over_run_latched : 1; + uint8_t not_used_01 : 1; + uint8_t diff_fifo : 2; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fifo_status2_t; + +#define ASM330LHHXG1_TIMESTAMP0 0x40U +#define ASM330LHHXG1_TIMESTAMP1 0x41U +#define ASM330LHHXG1_TIMESTAMP2 0x42U +#define ASM330LHHXG1_TIMESTAMP3 0x43U +#define ASM330LHHXG1_INT_CFG0 0x56U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t lir : 1; + uint8_t not_used_01 : 3; + uint8_t slope_fds : 1; + uint8_t sleep_status_on_int : 1; + uint8_t int_clr_on_read : 1; + uint8_t not_used_02 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 1; + uint8_t int_clr_on_read : 1; + uint8_t sleep_status_on_int : 1; + uint8_t slope_fds : 1; + uint8_t not_used_01 : 3; + uint8_t lir : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_int_cfg0_t; + +#define ASM330LHHXG1_INT_CFG1 0x58U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 5; + uint8_t inact_en : 2; + uint8_t interrupts_enable : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t interrupts_enable : 1; + uint8_t inact_en : 2; + uint8_t not_used_01 : 5; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_int_cfg1_t; + +#define ASM330LHHXG1_THS_6D 0x59U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 5; + uint8_t sixd_ths : 2; + uint8_t d4d_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t d4d_en : 1; + uint8_t sixd_ths : 2; + uint8_t not_used_01 : 5; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_ths_6d_t; + +#define ASM330LHHXG1_WAKE_UP_THS 0x5BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wk_ths : 6; + uint8_t usr_off_on_wu : 1; + uint8_t not_used_01 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 1; + uint8_t usr_off_on_wu : 1; + uint8_t wk_ths : 6; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_wake_up_ths_t; + +#define ASM330LHHXG1_WAKE_UP_DUR 0x5CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sleep_dur : 4; + uint8_t wake_ths_w : 1; + uint8_t wake_dur : 2; + uint8_t ff_dur : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 1; + uint8_t wake_dur : 2; + uint8_t wake_ths_w : 1; + uint8_t sleep_dur : 4; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_wake_up_dur_t; + +#define ASM330LHHXG1_FREE_FALL 0x5DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ths : 3; + uint8_t ff_dur : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 5; + uint8_t ff_ths : 3; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_free_fall_t; + +#define ASM330LHHXG1_MD1_CFG 0x5EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_shub : 1; + uint8_t int1_emb_func : 1; + uint8_t int1_6d : 1; + uint8_t not_used_01 : 1; + uint8_t int1_ff : 1; + uint8_t int1_wu : 1; + uint8_t not_used_02 : 1; + uint8_t int1_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_sleep_change : 1; + uint8_t not_used_02 : 1; + uint8_t int1_wu : 1; + uint8_t int1_ff : 1; + uint8_t not_used_01 : 1; + uint8_t int1_6d : 1; + uint8_t int1_emb_func : 1; + uint8_t int1_shub : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_md1_cfg_t; + +#define ASM330LHHXG1_MD2_CFG 0x5FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_timestamp : 1; + uint8_t int2_emb_func : 1; + uint8_t int2_6d : 1; + uint8_t not_used_01 : 1; + uint8_t int2_ff : 1; + uint8_t int2_wu : 1; + uint8_t not_used_02 : 1; + uint8_t int2_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_sleep_change : 1; + uint8_t not_used_02 : 1; + uint8_t int2_wu : 1; + uint8_t int2_ff : 1; + uint8_t not_used_01 : 1; + uint8_t int2_6d : 1; + uint8_t int2_emb_func : 1; + uint8_t int2_timestamp : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_md2_cfg_t; + +#define ASM330LHHXG1_I3C_BUS_AVB 0x62U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t pd_dis_int1 : 1; + uint8_t not_used_01 : 2; + uint8_t i3c_bus_avb_sel : 2; + uint8_t not_used_02 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 3; + uint8_t i3c_bus_avb_sel : 2; + uint8_t not_used_01 : 2; + uint8_t pd_dis_int1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_i3c_bus_avb_t; + +#define ASM330LHHXG1_INTERNAL_FREQ_FINE 0x63U +typedef struct +{ + uint8_t freq_fine : 8; +} asm330lhhxg1_internal_freq_fine_t; + +#define ASM330LHHXG1_X_OFS_USR 0x73U +#define ASM330LHHXG1_Y_OFS_USR 0x74U +#define ASM330LHHXG1_Z_OFS_USR 0x75U +#define ASM330LHHXG1_FIFO_DATA_OUT_TAG 0x78U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tag_parity : 1; + uint8_t tag_cnt : 2; + uint8_t tag_sensor : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tag_sensor : 5; + uint8_t tag_cnt : 2; + uint8_t tag_parity : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fifo_data_out_tag_t; + +#define ASM330LHHXG1_FIFO_DATA_OUT_X_L 0x79U +#define ASM330LHHXG1_FIFO_DATA_OUT_X_H 0x7AU +#define ASM330LHHXG1_FIFO_DATA_OUT_Y_L 0x7BU +#define ASM330LHHXG1_FIFO_DATA_OUT_Y_H 0x7CU +#define ASM330LHHXG1_FIFO_DATA_OUT_Z_L 0x7DU +#define ASM330LHHXG1_FIFO_DATA_OUT_Z_H 0x7EU + +#define ASM330LHHXG1_PAGE_SEL 0x02U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 1; + uint8_t emb_func_clk_dis : 1; + uint8_t not_used_02 : 2; + uint8_t page_sel : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_sel : 4; + uint8_t not_used_02 : 2; + uint8_t emb_func_clk_dis : 1; + uint8_t not_used_01 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_page_sel_t; + +#define ASM330LHHXG1_EMB_FUNC_EN_B 0x05U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_en : 1; + uint8_t not_used_01 : 3; + uint8_t mlc_en : 1; + uint8_t not_used_02 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 3; + uint8_t mlc_en : 1; + uint8_t not_used_01 : 3; + uint8_t fsm_en : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_emb_func_en_b_t; + +#define ASM330LHHXG1_PAGE_ADDRESS 0x08U +typedef struct +{ + uint8_t page_addr : 8; +} asm330lhhxg1_page_address_t; + +#define ASM330LHHXG1_PAGE_VALUE 0x09U +typedef struct +{ + uint8_t page_value : 8; +} asm330lhhxg1_page_value_t; + +#define ASM330LHHXG1_EMB_FUNC_INT1 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 7; + uint8_t int1_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm_lc : 1; + uint8_t not_used_01 : 7; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_emb_func_int1_t; + +#define ASM330LHHXG1_FSM_INT1_A 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_fsm1 : 1; + uint8_t int1_fsm2 : 1; + uint8_t int1_fsm3 : 1; + uint8_t int1_fsm4 : 1; + uint8_t int1_fsm5 : 1; + uint8_t int1_fsm6 : 1; + uint8_t int1_fsm7 : 1; + uint8_t int1_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm8 : 1; + uint8_t int1_fsm7 : 1; + uint8_t int1_fsm6 : 1; + uint8_t int1_fsm5 : 1; + uint8_t int1_fsm4 : 1; + uint8_t int1_fsm3 : 1; + uint8_t int1_fsm2 : 1; + uint8_t int1_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fsm_int1_a_t; + +#define ASM330LHHXG1_FSM_INT1_B 0x0CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_fsm9 : 1; + uint8_t int1_fsm10 : 1; + uint8_t int1_fsm11 : 1; + uint8_t int1_fsm12 : 1; + uint8_t int1_fsm13 : 1; + uint8_t int1_fsm14 : 1; + uint8_t int1_fsm15 : 1; + uint8_t int1_fsm16 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm16 : 1; + uint8_t int1_fsm15 : 1; + uint8_t int1_fsm14 : 1; + uint8_t int1_fsm13 : 1; + uint8_t int1_fsm12 : 1; + uint8_t int1_fsm11 : 1; + uint8_t int1_fsm10 : 1; + uint8_t int1_fsm9 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fsm_int1_b_t; + +#define ASM330LHHXG1_MLC_INT1 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_mlc1 : 1; + uint8_t int1_mlc2 : 1; + uint8_t int1_mlc3 : 1; + uint8_t int1_mlc4 : 1; + uint8_t int1_mlc5 : 1; + uint8_t int1_mlc6 : 1; + uint8_t int1_mlc7 : 1; + uint8_t int1_mlc8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_mlc8 : 1; + uint8_t int1_mlc7 : 1; + uint8_t int1_mlc6 : 1; + uint8_t int1_mlc5 : 1; + uint8_t int1_mlc4 : 1; + uint8_t int1_mlc3 : 1; + uint8_t int1_mlc2 : 1; + uint8_t int1_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_mlc_int1_t; + +#define ASM330LHHXG1_EMB_FUNC_INT2 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 7; + uint8_t int2_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm_lc : 1; + uint8_t not_used_01 : 7; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_emb_func_int2_t; + +#define ASM330LHHXG1_FSM_INT2_A 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_fsm1 : 1; + uint8_t int2_fsm2 : 1; + uint8_t int2_fsm3 : 1; + uint8_t int2_fsm4 : 1; + uint8_t int2_fsm5 : 1; + uint8_t int2_fsm6 : 1; + uint8_t int2_fsm7 : 1; + uint8_t int2_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm8 : 1; + uint8_t int2_fsm7 : 1; + uint8_t int2_fsm6 : 1; + uint8_t int2_fsm5 : 1; + uint8_t int2_fsm4 : 1; + uint8_t int2_fsm3 : 1; + uint8_t int2_fsm2 : 1; + uint8_t int2_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fsm_int2_a_t; + +#define ASM330LHHXG1_FSM_INT2_B 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_fsm9 : 1; + uint8_t int2_fsm10 : 1; + uint8_t int2_fsm11 : 1; + uint8_t int2_fsm12 : 1; + uint8_t int2_fsm13 : 1; + uint8_t int2_fsm14 : 1; + uint8_t int2_fsm15 : 1; + uint8_t int2_fsm16 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm16 : 1; + uint8_t int2_fsm15 : 1; + uint8_t int2_fsm14 : 1; + uint8_t int2_fsm13 : 1; + uint8_t int2_fsm12 : 1; + uint8_t int2_fsm11 : 1; + uint8_t int2_fsm10 : 1; + uint8_t int2_fsm9 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fsm_int2_b_t; + +#define ASM330LHHXG1_MLC_INT2 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_mlc1 : 1; + uint8_t int2_mlc2 : 1; + uint8_t int2_mlc3 : 1; + uint8_t int2_mlc4 : 1; + uint8_t int2_mlc5 : 1; + uint8_t int2_mlc6 : 1; + uint8_t int2_mlc7 : 1; + uint8_t int2_mlc8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_mlc8 : 1; + uint8_t int2_mlc7 : 1; + uint8_t int2_mlc6 : 1; + uint8_t int2_mlc5 : 1; + uint8_t int2_mlc4 : 1; + uint8_t int2_mlc3 : 1; + uint8_t int2_mlc2 : 1; + uint8_t int2_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_mlc_int2_t; + +#define ASM330LHHXG1_EMB_FUNC_STATUS 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 7; + uint8_t is_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm_lc : 1; + uint8_t not_used_01 : 7; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_emb_func_status_t; + +#define ASM330LHHXG1_FSM_STATUS_A 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm8 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fsm_status_a_t; + +#define ASM330LHHXG1_FSM_STATUS_B 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm9 : 1; + uint8_t is_fsm10 : 1; + uint8_t is_fsm11 : 1; + uint8_t is_fsm12 : 1; + uint8_t is_fsm13 : 1; + uint8_t is_fsm14 : 1; + uint8_t is_fsm15 : 1; + uint8_t is_fsm16 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm16 : 1; + uint8_t is_fsm15 : 1; + uint8_t is_fsm14 : 1; + uint8_t is_fsm13 : 1; + uint8_t is_fsm12 : 1; + uint8_t is_fsm11 : 1; + uint8_t is_fsm10 : 1; + uint8_t is_fsm9 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fsm_status_b_t; + +#define ASM330LHHXG1_MLC_STATUS 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_mlc1 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc4 : 1; + uint8_t is_mlc5 : 1; + uint8_t is_mlc6 : 1; + uint8_t is_mlc7 : 1; + uint8_t is_mlc8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_mlc8 : 1; + uint8_t is_mlc7 : 1; + uint8_t is_mlc6 : 1; + uint8_t is_mlc5 : 1; + uint8_t is_mlc4 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_mlc_status_t; + +#define ASM330LHHXG1_PAGE_RW 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 5; + uint8_t page_rw : 2; /* page_write + page_read */ + uint8_t emb_func_lir : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_lir : 1; + uint8_t page_rw : 2; /* page_write + page_read */ + uint8_t not_used_01 : 5; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_page_rw_t; + +#define ASM330LHHXG1_FSM_ENABLE_A 0x46U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm1_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm8_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm8_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm1_en : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fsm_enable_a_t; + +#define ASM330LHHXG1_FSM_ENABLE_B 0x47U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm9_en : 1; + uint8_t fsm10_en : 1; + uint8_t fsm11_en : 1; + uint8_t fsm12_en : 1; + uint8_t fsm13_en : 1; + uint8_t fsm14_en : 1; + uint8_t fsm15_en : 1; + uint8_t fsm16_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm16_en : 1; + uint8_t fsm15_en : 1; + uint8_t fsm14_en : 1; + uint8_t fsm13_en : 1; + uint8_t fsm12_en : 1; + uint8_t fsm11_en : 1; + uint8_t fsm10_en : 1; + uint8_t fsm9_en : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fsm_enable_b_t; + +#define ASM330LHHXG1_FSM_LONG_COUNTER_L 0x48U +#define ASM330LHHXG1_FSM_LONG_COUNTER_H 0x49U +#define ASM330LHHXG1_FSM_LONG_COUNTER_CLEAR 0x4AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ + uint8_t not_used_01 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 6; + uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fsm_long_counter_clear_t; + +#define ASM330LHHXG1_FSM_OUTS1 0x4CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fsm_outs1_t; + +#define ASM330LHHXG1_FSM_OUTS2 0x4DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fsm_outs2_t; + +#define ASM330LHHXG1_FSM_OUTS3 0x4EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fsm_outs3_t; + +#define ASM330LHHXG1_FSM_OUTS4 0x4FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fsm_outs4_t; + +#define ASM330LHHXG1_FSM_OUTS5 0x50U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fsm_outs5_t; + +#define ASM330LHHXG1_FSM_OUTS6 0x51U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fsm_outs6_t; + +#define ASM330LHHXG1_FSM_OUTS7 0x52U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fsm_outs7_t; + +#define ASM330LHHXG1_FSM_OUTS8 0x53U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fsm_outs8_t; + +#define ASM330LHHXG1_FSM_OUTS9 0x54U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fsm_outs9_t; + +#define ASM330LHHXG1_FSM_OUTS10 0x55U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fsm_outs10_t; + +#define ASM330LHHXG1_FSM_OUTS11 0x56U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fsm_outs11_t; + +#define ASM330LHHXG1_FSM_OUTS12 0x57U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fsm_outs12_t; + +#define ASM330LHHXG1_FSM_OUTS13 0x58U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fsm_outs13_t; + +#define ASM330LHHXG1_FSM_OUTS14 0x59U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fsm_outs14_t; + +#define ASM330LHHXG1_FSM_OUTS15 0x5AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fsm_outs15_t; + +#define ASM330LHHXG1_FSM_OUTS16 0x5BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t n_v : 1; + uint8_t p_v : 1; + uint8_t n_z : 1; + uint8_t p_z : 1; + uint8_t n_y : 1; + uint8_t p_y : 1; + uint8_t n_x : 1; + uint8_t p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t p_x : 1; + uint8_t n_x : 1; + uint8_t p_y : 1; + uint8_t n_y : 1; + uint8_t p_z : 1; + uint8_t n_z : 1; + uint8_t p_v : 1; + uint8_t n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_fsm_outs16_t; + +#define ASM330LHHXG1_EMB_FUNC_ODR_CFG_B 0x5FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 3; + uint8_t fsm_odr : 2; + uint8_t not_used_02 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 3; + uint8_t fsm_odr : 2; + uint8_t not_used_01 : 3; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_emb_func_odr_cfg_b_t; + +#define ASM330LHHXG1_EMB_FUNC_ODR_CFG_C 0x60U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used_01 : 4; + uint8_t mlc_odr : 2; + uint8_t not_used_02 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 2; + uint8_t mlc_odr : 2; + uint8_t not_used_01 : 4; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_emb_func_odr_cfg_c_t; + +#define ASM330LHHXG1_EMB_FUNC_INIT_B 0x67U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_init : 1; + uint8_t not_used_01 : 3; + uint8_t mlc_init : 1; + uint8_t not_used_02 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 3; + uint8_t mlc_init : 1; + uint8_t not_used_01 : 3; + uint8_t fsm_init : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_emb_func_init_b_t; + +#define ASM330LHHXG1_MLC0_SRC 0x70U +#define ASM330LHHXG1_MLC1_SRC 0x71U +#define ASM330LHHXG1_MLC2_SRC 0x72U +#define ASM330LHHXG1_MLC3_SRC 0x73U +#define ASM330LHHXG1_MLC4_SRC 0x74U +#define ASM330LHHXG1_MLC5_SRC 0x75U +#define ASM330LHHXG1_MLC6_SRC 0x76U +#define ASM330LHHXG1_MLC7_SRC 0x77U + +#define ASM330LHHXG1_MAG_SENSITIVITY_L 0xBAU +#define ASM330LHHXG1_MAG_SENSITIVITY_H 0xBBU +#define ASM330LHHXG1_MAG_OFFX_L 0xC0U +#define ASM330LHHXG1_MAG_OFFX_H 0xC1U +#define ASM330LHHXG1_MAG_OFFY_L 0xC2U +#define ASM330LHHXG1_MAG_OFFY_H 0xC3U +#define ASM330LHHXG1_MAG_OFFZ_L 0xC4U +#define ASM330LHHXG1_MAG_OFFZ_H 0xC5U +#define ASM330LHHXG1_MAG_SI_XX_L 0xC6U +#define ASM330LHHXG1_MAG_SI_XX_H 0xC7U +#define ASM330LHHXG1_MAG_SI_XY_L 0xC8U +#define ASM330LHHXG1_MAG_SI_XY_H 0xC9U +#define ASM330LHHXG1_MAG_SI_XZ_L 0xCAU +#define ASM330LHHXG1_MAG_SI_XZ_H 0xCBU +#define ASM330LHHXG1_MAG_SI_YY_L 0xCCU +#define ASM330LHHXG1_MAG_SI_YY_H 0xCDU +#define ASM330LHHXG1_MAG_SI_YZ_L 0xCEU +#define ASM330LHHXG1_MAG_SI_YZ_H 0xCFU +#define ASM330LHHXG1_MAG_SI_ZZ_L 0xD0U +#define ASM330LHHXG1_MAG_SI_ZZ_H 0xD1U +#define ASM330LHHXG1_MAG_CFG_A 0xD4U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mag_z_axis : 3; + uint8_t not_used_01 : 1; + uint8_t mag_y_axis : 3; + uint8_t not_used_02 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_02 : 1; + uint8_t mag_y_axis : 3; + uint8_t not_used_01 : 1; + uint8_t mag_z_axis : 3; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_mag_cfg_a_t; + +#define ASM330LHHXG1_MAG_CFG_B 0xD5U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mag_x_axis : 3; + uint8_t not_used_01 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 5; + uint8_t mag_x_axis : 3; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_mag_cfg_b_t; + +#define ASM330LHHXG1_FSM_LC_TIMEOUT_L 0x17AU +#define ASM330LHHXG1_FSM_LC_TIMEOUT_H 0x17BU +#define ASM330LHHXG1_FSM_PROGRAMS 0x17CU +#define ASM330LHHXG1_FSM_START_ADD_L 0x17EU +#define ASM330LHHXG1_FSM_START_ADD_H 0x17FU + +#define ASM330LHHXG1_MLC_MAG_SENSITIVITY_L 0x1E8U +#define ASM330LHHXG1_MLC_MAG_SENSITIVITY_H 0x1E9U + +#define ASM330LHHXG1_SENSOR_HUB_1 0x02U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_sensor_hub_1_t; + +#define ASM330LHHXG1_SENSOR_HUB_2 0x03U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_sensor_hub_2_t; + +#define ASM330LHHXG1_SENSOR_HUB_3 0x04U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_sensor_hub_3_t; + +#define ASM330LHHXG1_SENSOR_HUB_4 0x05U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_sensor_hub_4_t; + +#define ASM330LHHXG1_SENSOR_HUB_5 0x06U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_sensor_hub_5_t; + +#define ASM330LHHXG1_SENSOR_HUB_6 0x07U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_sensor_hub_6_t; + +#define ASM330LHHXG1_SENSOR_HUB_7 0x08U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_sensor_hub_7_t; + +#define ASM330LHHXG1_SENSOR_HUB_8 0x09U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_sensor_hub_8_t; + +#define ASM330LHHXG1_SENSOR_HUB_9 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_sensor_hub_9_t; + +#define ASM330LHHXG1_SENSOR_HUB_10 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_sensor_hub_10_t; + +#define ASM330LHHXG1_SENSOR_HUB_11 0x0CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_sensor_hub_11_t; + +#define ASM330LHHXG1_SENSOR_HUB_12 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_sensor_hub_12_t; + +#define ASM330LHHXG1_SENSOR_HUB_13 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_sensor_hub_13_t; + +#define ASM330LHHXG1_SENSOR_HUB_14 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_sensor_hub_14_t; + +#define ASM330LHHXG1_SENSOR_HUB_15 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_sensor_hub_15_t; + +#define ASM330LHHXG1_SENSOR_HUB_16 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_sensor_hub_16_t; + +#define ASM330LHHXG1_SENSOR_HUB_17 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_sensor_hub_17_t; + +#define ASM330LHHXG1_SENSOR_HUB_18 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_sensor_hub_18_t; + +#define ASM330LHHXG1_MASTER_CONFIG 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t aux_sens_on : 2; + uint8_t master_on : 1; + uint8_t shub_pu_en : 1; + uint8_t pass_through_mode : 1; + uint8_t start_config : 1; + uint8_t write_once : 1; + uint8_t rst_master_regs : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t rst_master_regs : 1; + uint8_t write_once : 1; + uint8_t start_config : 1; + uint8_t pass_through_mode : 1; + uint8_t shub_pu_en : 1; + uint8_t master_on : 1; + uint8_t aux_sens_on : 2; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_master_config_t; + +#define ASM330LHHXG1_SLV0_ADD 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t rw_0 : 1; + uint8_t slave0 : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave0 : 7; + uint8_t rw_0 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_slv0_add_t; + +#define ASM330LHHXG1_SLV0_SUBADD 0x16U +typedef struct +{ + uint8_t slave0_reg : 8; +} asm330lhhxg1_slv0_subadd_t; + +#define ASM330LHHXG1_SLV0_CONFIG 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave0_numop : 3; + uint8_t batch_ext_sens_0_en : 1; + uint8_t not_used_01 : 2; + uint8_t shub_odr : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t shub_odr : 2; + uint8_t not_used_01 : 2; + uint8_t batch_ext_sens_0_en : 1; + uint8_t slave0_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_slv0_config_t; + +#define ASM330LHHXG1_SLV1_ADD 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t r_1 : 1; + uint8_t slave1_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave1_add : 7; + uint8_t r_1 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_slv1_add_t; + +#define ASM330LHHXG1_SLV1_SUBADD 0x19U +typedef struct +{ + uint8_t slave1_reg : 8; +} asm330lhhxg1_slv1_subadd_t; + +#define ASM330LHHXG1_SLV1_CONFIG 0x1AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave1_numop : 3; + uint8_t batch_ext_sens_1_en : 1; + uint8_t not_used_01 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 4; + uint8_t batch_ext_sens_1_en : 1; + uint8_t slave1_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_slv1_config_t; + +#define ASM330LHHXG1_SLV2_ADD 0x1BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t r_2 : 1; + uint8_t slave2_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave2_add : 7; + uint8_t r_2 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_slv2_add_t; + +#define ASM330LHHXG1_SLV2_SUBADD 0x1CU +typedef struct +{ + uint8_t slave2_reg : 8; +} asm330lhhxg1_slv2_subadd_t; + +#define ASM330LHHXG1_SLV2_CONFIG 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave2_numop : 3; + uint8_t batch_ext_sens_2_en : 1; + uint8_t not_used_01 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 4; + uint8_t batch_ext_sens_2_en : 1; + uint8_t slave2_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_slv2_config_t; + +#define ASM330LHHXG1_SLV3_ADD 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t r_3 : 1; + uint8_t slave3_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave3_add : 7; + uint8_t r_3 : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_slv3_add_t; + +#define ASM330LHHXG1_SLV3_SUBADD 0x1FU +typedef struct +{ + uint8_t slave3_reg : 8; +} asm330lhhxg1_slv3_subadd_t; + +#define ASM330LHHXG1_SLV3_CONFIG 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave3_numop : 3; + uint8_t batch_ext_sens_3_en : 1; + uint8_t not_used_01 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used_01 : 4; + uint8_t batch_ext_sens_3_en : 1; + uint8_t slave3_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_slv3_config_t; + +#define ASM330LHHXG1_DATAWRITE_SLV0 0x21U +typedef struct +{ + uint8_t slave0_dataw : 8; +} asm330lhhxg1_datawrite_slv0_t; + +#define ASM330LHHXG1_STATUS_MASTER 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sens_hub_endop : 1; + uint8_t not_used_01 : 2; + uint8_t slave0_nack : 1; + uint8_t slave1_nack : 1; + uint8_t slave2_nack : 1; + uint8_t slave3_nack : 1; + uint8_t wr_once_done : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t wr_once_done : 1; + uint8_t slave3_nack : 1; + uint8_t slave2_nack : 1; + uint8_t slave1_nack : 1; + uint8_t slave0_nack : 1; + uint8_t not_used_01 : 2; + uint8_t sens_hub_endop : 1; +#endif /* DRV_BYTE_ORDER */ +} asm330lhhxg1_status_master_t; + +/** + * @defgroup ASM330LHHXG1_Register_Union + * @brief This union group all the registers that has a bit-field + * description. + * This union is useful but not need by the driver. + * + * REMOVING this union you are compliant with: + * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " + * + * @{ + * + */ +typedef union +{ + asm330lhhxg1_func_cfg_access_t func_cfg_access; + asm330lhhxg1_pin_ctrl_t pin_ctrl; + asm330lhhxg1_fifo_ctrl1_t fifo_ctrl1; + asm330lhhxg1_fifo_ctrl2_t fifo_ctrl2; + asm330lhhxg1_fifo_ctrl3_t fifo_ctrl3; + asm330lhhxg1_fifo_ctrl4_t fifo_ctrl4; + asm330lhhxg1_counter_bdr_reg1_t counter_bdr_reg1; + asm330lhhxg1_counter_bdr_reg2_t counter_bdr_reg2; + asm330lhhxg1_int1_ctrl_t int1_ctrl; + asm330lhhxg1_int2_ctrl_t int2_ctrl; + asm330lhhxg1_ctrl1_xl_t ctrl1_xl; + asm330lhhxg1_ctrl2_g_t ctrl2_g; + asm330lhhxg1_ctrl3_c_t ctrl3_c; + asm330lhhxg1_ctrl4_c_t ctrl4_c; + asm330lhhxg1_ctrl5_c_t ctrl5_c; + asm330lhhxg1_ctrl6_c_t ctrl6_c; + asm330lhhxg1_ctrl7_g_t ctrl7_g; + asm330lhhxg1_ctrl8_xl_t ctrl8_xl; + asm330lhhxg1_ctrl9_xl_t ctrl9_xl; + asm330lhhxg1_ctrl10_c_t ctrl10_c; + asm330lhhxg1_all_int_src_t all_int_src; + asm330lhhxg1_wake_up_src_t wake_up_src; + asm330lhhxg1_d6d_src_t d6d_src; + asm330lhhxg1_status_reg_t status_reg; + asm330lhhxg1_fifo_status1_t fifo_status1; + asm330lhhxg1_fifo_status2_t fifo_status2; + asm330lhhxg1_int_cfg0_t int_cfg0; + asm330lhhxg1_int_cfg1_t int_cfg1; + asm330lhhxg1_ths_6d_t ths_6d; + asm330lhhxg1_wake_up_ths_t wake_up_ths; + asm330lhhxg1_wake_up_dur_t wake_up_dur; + asm330lhhxg1_free_fall_t free_fall; + asm330lhhxg1_md1_cfg_t md1_cfg; + asm330lhhxg1_md2_cfg_t md2_cfg; + asm330lhhxg1_i3c_bus_avb_t i3c_bus_avb; + asm330lhhxg1_internal_freq_fine_t internal_freq_fine; + asm330lhhxg1_fifo_data_out_tag_t fifo_data_out_tag; + asm330lhhxg1_page_sel_t page_sel; + asm330lhhxg1_emb_func_en_b_t emb_func_en_b; + asm330lhhxg1_page_address_t page_address; + asm330lhhxg1_page_value_t page_value; + asm330lhhxg1_emb_func_int1_t emb_func_int1; + asm330lhhxg1_fsm_int1_a_t fsm_int1_a; + asm330lhhxg1_fsm_int1_b_t fsm_int1_b; + asm330lhhxg1_mlc_int1_t mlc_int1; + asm330lhhxg1_emb_func_int2_t emb_func_int2; + asm330lhhxg1_fsm_int2_a_t fsm_int2_a; + asm330lhhxg1_fsm_int2_b_t fsm_int2_b; + asm330lhhxg1_mlc_int2_t mlc_int2; + asm330lhhxg1_emb_func_status_t emb_func_status; + asm330lhhxg1_fsm_status_a_t fsm_status_a; + asm330lhhxg1_fsm_status_b_t fsm_status_b; + asm330lhhxg1_mlc_status_mainpage_t mlc_status_mainpage; + asm330lhhxg1_emb_func_odr_cfg_c_t emb_func_odr_cfg_c; + asm330lhhxg1_page_rw_t page_rw; + asm330lhhxg1_fsm_enable_a_t fsm_enable_a; + asm330lhhxg1_fsm_enable_b_t fsm_enable_b; + asm330lhhxg1_fsm_long_counter_clear_t fsm_long_counter_clear; + asm330lhhxg1_fsm_outs1_t fsm_outs1; + asm330lhhxg1_fsm_outs2_t fsm_outs2; + asm330lhhxg1_fsm_outs3_t fsm_outs3; + asm330lhhxg1_fsm_outs4_t fsm_outs4; + asm330lhhxg1_fsm_outs5_t fsm_outs5; + asm330lhhxg1_fsm_outs6_t fsm_outs6; + asm330lhhxg1_fsm_outs7_t fsm_outs7; + asm330lhhxg1_fsm_outs8_t fsm_outs8; + asm330lhhxg1_fsm_outs9_t fsm_outs9; + asm330lhhxg1_fsm_outs10_t fsm_outs10; + asm330lhhxg1_fsm_outs11_t fsm_outs11; + asm330lhhxg1_fsm_outs12_t fsm_outs12; + asm330lhhxg1_fsm_outs13_t fsm_outs13; + asm330lhhxg1_fsm_outs14_t fsm_outs14; + asm330lhhxg1_fsm_outs15_t fsm_outs15; + asm330lhhxg1_fsm_outs16_t fsm_outs16; + asm330lhhxg1_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; + asm330lhhxg1_emb_func_init_b_t emb_func_init_b; + asm330lhhxg1_mag_cfg_a_t mag_cfg_a; + asm330lhhxg1_mag_cfg_b_t mag_cfg_b; + asm330lhhxg1_sensor_hub_1_t sensor_hub_1; + asm330lhhxg1_sensor_hub_2_t sensor_hub_2; + asm330lhhxg1_sensor_hub_3_t sensor_hub_3; + asm330lhhxg1_sensor_hub_4_t sensor_hub_4; + asm330lhhxg1_sensor_hub_5_t sensor_hub_5; + asm330lhhxg1_sensor_hub_6_t sensor_hub_6; + asm330lhhxg1_sensor_hub_7_t sensor_hub_7; + asm330lhhxg1_sensor_hub_8_t sensor_hub_8; + asm330lhhxg1_sensor_hub_9_t sensor_hub_9; + asm330lhhxg1_sensor_hub_10_t sensor_hub_10; + asm330lhhxg1_sensor_hub_11_t sensor_hub_11; + asm330lhhxg1_sensor_hub_12_t sensor_hub_12; + asm330lhhxg1_sensor_hub_13_t sensor_hub_13; + asm330lhhxg1_sensor_hub_14_t sensor_hub_14; + asm330lhhxg1_sensor_hub_15_t sensor_hub_15; + asm330lhhxg1_sensor_hub_16_t sensor_hub_16; + asm330lhhxg1_sensor_hub_17_t sensor_hub_17; + asm330lhhxg1_sensor_hub_18_t sensor_hub_18; + asm330lhhxg1_master_config_t master_config; + asm330lhhxg1_slv0_add_t slv0_add; + asm330lhhxg1_slv0_subadd_t slv0_subadd; + asm330lhhxg1_slv0_config_t slv0_config; + asm330lhhxg1_slv1_add_t slv1_add; + asm330lhhxg1_slv1_subadd_t slv1_subadd; + asm330lhhxg1_slv1_config_t slv1_config; + asm330lhhxg1_slv2_add_t slv2_add; + asm330lhhxg1_slv2_subadd_t slv2_subadd; + asm330lhhxg1_slv2_config_t slv2_config; + asm330lhhxg1_slv3_add_t slv3_add; + asm330lhhxg1_slv3_subadd_t slv3_subadd; + asm330lhhxg1_slv3_config_t slv3_config; + asm330lhhxg1_datawrite_slv0_t datawrite_slv0; + asm330lhhxg1_status_master_t status_master; + bitwise_t bitwise; + uint8_t byte; +} asm330lhhxg1_reg_t; + +/** + * @} + * + */ + +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + +int32_t asm330lhhxg1_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len); +int32_t asm330lhhxg1_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, + uint16_t len); + +float_t asm330lhhxg1_from_fs2g_to_mg(int16_t lsb); +float_t asm330lhhxg1_from_fs4g_to_mg(int16_t lsb); +float_t asm330lhhxg1_from_fs8g_to_mg(int16_t lsb); +float_t asm330lhhxg1_from_fs16g_to_mg(int16_t lsb); +float_t asm330lhhxg1_from_fs125dps_to_mdps(int16_t lsb); +float_t asm330lhhxg1_from_fs250dps_to_mdps(int16_t lsb); +float_t asm330lhhxg1_from_fs500dps_to_mdps(int16_t lsb); +float_t asm330lhhxg1_from_fs1000dps_to_mdps(int16_t lsb); +float_t asm330lhhxg1_from_fs2000dps_to_mdps(int16_t lsb); +float_t asm330lhhxg1_from_fs4000dps_to_mdps(int16_t lsb); +float_t asm330lhhxg1_from_lsb_to_celsius(int16_t lsb); +float_t asm330lhhxg1_from_lsb_to_nsec(int32_t lsb); + +typedef enum +{ + ASM330LHHXG1_2g = 0, + ASM330LHHXG1_16g = 1, /* if XL_FS_MODE = '1' -> ASM330LHHXG1_2g */ + ASM330LHHXG1_4g = 2, + ASM330LHHXG1_8g = 3, +} asm330lhhxg1_fs_xl_t; +int32_t asm330lhhxg1_xl_full_scale_set(const stmdev_ctx_t *ctx, asm330lhhxg1_fs_xl_t val); +int32_t asm330lhhxg1_xl_full_scale_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_fs_xl_t *val); + +typedef enum +{ + ASM330LHHXG1_XL_ODR_OFF = 0, + ASM330LHHXG1_XL_ODR_12Hz5 = 1, + ASM330LHHXG1_XL_ODR_26Hz = 2, + ASM330LHHXG1_XL_ODR_52Hz = 3, + ASM330LHHXG1_XL_ODR_104Hz = 4, + ASM330LHHXG1_XL_ODR_208Hz = 5, + ASM330LHHXG1_XL_ODR_417Hz = 6, + ASM330LHHXG1_XL_ODR_833Hz = 7, + ASM330LHHXG1_XL_ODR_1667Hz = 8, + ASM330LHHXG1_XL_ODR_3333Hz = 9, + ASM330LHHXG1_XL_ODR_6667Hz = 10, + ASM330LHHXG1_XL_ODR_1Hz6 = 11, /* (low power only) */ +} asm330lhhxg1_odr_xl_t; +int32_t asm330lhhxg1_xl_data_rate_set(const stmdev_ctx_t *ctx, asm330lhhxg1_odr_xl_t val); +int32_t asm330lhhxg1_xl_data_rate_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_odr_xl_t *val); + +typedef enum +{ + ASM330LHHXG1_125dps = 2, + ASM330LHHXG1_250dps = 0, + ASM330LHHXG1_500dps = 4, + ASM330LHHXG1_1000dps = 8, + ASM330LHHXG1_2000dps = 12, + ASM330LHHXG1_4000dps = 1, +} asm330lhhxg1_fs_g_t; +int32_t asm330lhhxg1_gy_full_scale_set(const stmdev_ctx_t *ctx, asm330lhhxg1_fs_g_t val); +int32_t asm330lhhxg1_gy_full_scale_get(const stmdev_ctx_t *ctx, asm330lhhxg1_fs_g_t *val); + +typedef enum +{ + ASM330LHHXG1_GY_ODR_OFF = 0, + ASM330LHHXG1_GY_ODR_12Hz5 = 1, + ASM330LHHXG1_GY_ODR_26Hz = 2, + ASM330LHHXG1_GY_ODR_52Hz = 3, + ASM330LHHXG1_GY_ODR_104Hz = 4, + ASM330LHHXG1_GY_ODR_208Hz = 5, + ASM330LHHXG1_GY_ODR_417Hz = 6, + ASM330LHHXG1_GY_ODR_833Hz = 7, + ASM330LHHXG1_GY_ODR_1667Hz = 8, + ASM330LHHXG1_GY_ODR_3333Hz = 9, + ASM330LHHXG1_GY_ODR_6667Hz = 10, +} asm330lhhxg1_odr_g_t; +int32_t asm330lhhxg1_gy_data_rate_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_odr_g_t val); +int32_t asm330lhhxg1_gy_data_rate_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_odr_g_t *val); + +int32_t asm330lhhxg1_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHHXG1_LSb_1mg = 0, + ASM330LHHXG1_LSb_16mg = 1, +} asm330lhhxg1_usr_off_w_t; +int32_t asm330lhhxg1_xl_offset_weight_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_usr_off_w_t val); +int32_t asm330lhhxg1_xl_offset_weight_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_usr_off_w_t *val); + +typedef enum +{ + ASM330LHHXG1_HIGH_PERFORMANCE_MD = 0, + ASM330LHHXG1_LOW_NORMAL_POWER_MD = 1, +} asm330lhhxg1_xl_hm_mode_t; +int32_t asm330lhhxg1_xl_power_mode_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_xl_hm_mode_t val); +int32_t asm330lhhxg1_xl_power_mode_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_xl_hm_mode_t *val); + +typedef enum +{ + ASM330LHHXG1_GY_HIGH_PERFORMANCE = 0, + ASM330LHHXG1_GY_NORMAL = 1, +} asm330lhhxg1_g_hm_mode_t; +int32_t asm330lhhxg1_gy_power_mode_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_g_hm_mode_t val); +int32_t asm330lhhxg1_gy_power_mode_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_g_hm_mode_t *val); + +typedef struct +{ + asm330lhhxg1_all_int_src_t all_int_src; + asm330lhhxg1_wake_up_src_t wake_up_src; + asm330lhhxg1_d6d_src_t d6d_src; + asm330lhhxg1_status_reg_t status_reg; + asm330lhhxg1_emb_func_status_t emb_func_status; + asm330lhhxg1_fsm_status_a_t fsm_status_a; + asm330lhhxg1_fsm_status_b_t fsm_status_b; + asm330lhhxg1_mlc_status_mainpage_t mlc_status; +} asm330lhhxg1_all_sources_t; +int32_t asm330lhhxg1_all_sources_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_all_sources_t *val); + +int32_t asm330lhhxg1_status_reg_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_status_reg_t *val); + +int32_t asm330lhhxg1_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhhxg1_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhhxg1_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhhxg1_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhhxg1_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t asm330lhhxg1_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhhxg1_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t asm330lhhxg1_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t asm330lhhxg1_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t asm330lhhxg1_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhhxg1_timestamp_rst(const stmdev_ctx_t *ctx); + +int32_t asm330lhhxg1_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhhxg1_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); + +typedef enum +{ + ASM330LHHXG1_NO_ROUND = 0, + ASM330LHHXG1_ROUND_XL = 1, + ASM330LHHXG1_ROUND_GY = 2, + ASM330LHHXG1_ROUND_GY_XL = 3, +} asm330lhhxg1_rounding_t; +int32_t asm330lhhxg1_rounding_mode_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_rounding_t val); +int32_t asm330lhhxg1_rounding_mode_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_rounding_t *val); + +int32_t asm330lhhxg1_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t asm330lhhxg1_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t asm330lhhxg1_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t asm330lhhxg1_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhhxg1_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHHXG1_USER_BANK = 0, + ASM330LHHXG1_SENSOR_HUB_BANK = 1, + ASM330LHHXG1_EMBEDDED_FUNC_BANK = 2, +} asm330lhhxg1_reg_access_t; +int32_t asm330lhhxg1_mem_bank_set(const stmdev_ctx_t *ctx, asm330lhhxg1_reg_access_t val); +int32_t asm330lhhxg1_mem_bank_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_reg_access_t *val); + +int32_t asm330lhhxg1_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t address, + uint8_t *val); +int32_t asm330lhhxg1_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len); +int32_t asm330lhhxg1_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, + uint8_t *val); +int32_t asm330lhhxg1_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, + uint8_t *val); + +typedef enum +{ + ASM330LHHXG1_DRDY_LATCHED = 0, + ASM330LHHXG1_DRDY_PULSED = 1, +} asm330lhhxg1_dataready_pulsed_t; +int32_t asm330lhhxg1_data_ready_mode_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_dataready_pulsed_t val); +int32_t asm330lhhxg1_data_ready_mode_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_dataready_pulsed_t *val); + +int32_t asm330lhhxg1_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t asm330lhhxg1_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhhxg1_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhhxg1_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHHXG1_XL_ST_DISABLE = 0, + ASM330LHHXG1_XL_ST_POSITIVE = 1, + ASM330LHHXG1_XL_ST_NEGATIVE = 2, +} asm330lhhxg1_st_xl_t; +int32_t asm330lhhxg1_xl_self_test_set(const stmdev_ctx_t *ctx, asm330lhhxg1_st_xl_t val); +int32_t asm330lhhxg1_xl_self_test_get(const stmdev_ctx_t *ctx, asm330lhhxg1_st_xl_t *val); + +typedef enum +{ + ASM330LHHXG1_GY_ST_DISABLE = 0, + ASM330LHHXG1_GY_ST_POSITIVE = 1, + ASM330LHHXG1_GY_ST_NEGATIVE = 3, +} asm330lhhxg1_st_g_t; +int32_t asm330lhhxg1_gy_self_test_set(const stmdev_ctx_t *ctx, asm330lhhxg1_st_g_t val); +int32_t asm330lhhxg1_gy_self_test_get(const stmdev_ctx_t *ctx, asm330lhhxg1_st_g_t *val); + +int32_t asm330lhhxg1_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhhxg1_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhhxg1_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHHXG1_ULTRA_LIGHT = 0, + ASM330LHHXG1_VERY_LIGHT = 1, + ASM330LHHXG1_LIGHT = 2, + ASM330LHHXG1_MEDIUM = 3, + ASM330LHHXG1_STRONG = 4, + ASM330LHHXG1_VERY_STRONG = 5, + ASM330LHHXG1_AGGRESSIVE = 6, + ASM330LHHXG1_XTREME = 7, +} asm330lhhxg1_ftype_t; +int32_t asm330lhhxg1_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_ftype_t val); +int32_t asm330lhhxg1_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_ftype_t *val); + +int32_t asm330lhhxg1_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHHXG1_HP_PATH_DISABLE_ON_OUT = 0x00, + ASM330LHHXG1_SLOPE_ODR_DIV_4 = 0x10, + ASM330LHHXG1_HP_ODR_DIV_10 = 0x11, + ASM330LHHXG1_HP_ODR_DIV_20 = 0x12, + ASM330LHHXG1_HP_ODR_DIV_45 = 0x13, + ASM330LHHXG1_HP_ODR_DIV_100 = 0x14, + ASM330LHHXG1_HP_ODR_DIV_200 = 0x15, + ASM330LHHXG1_HP_ODR_DIV_400 = 0x16, + ASM330LHHXG1_HP_ODR_DIV_800 = 0x17, + ASM330LHHXG1_HP_REF_MD_ODR_DIV_10 = 0x31, + ASM330LHHXG1_HP_REF_MD_ODR_DIV_20 = 0x32, + ASM330LHHXG1_HP_REF_MD_ODR_DIV_45 = 0x33, + ASM330LHHXG1_HP_REF_MD_ODR_DIV_100 = 0x34, + ASM330LHHXG1_HP_REF_MD_ODR_DIV_200 = 0x35, + ASM330LHHXG1_HP_REF_MD_ODR_DIV_400 = 0x36, + ASM330LHHXG1_HP_REF_MD_ODR_DIV_800 = 0x37, + ASM330LHHXG1_LP_ODR_DIV_10 = 0x01, + ASM330LHHXG1_LP_ODR_DIV_20 = 0x02, + ASM330LHHXG1_LP_ODR_DIV_45 = 0x03, + ASM330LHHXG1_LP_ODR_DIV_100 = 0x04, + ASM330LHHXG1_LP_ODR_DIV_200 = 0x05, + ASM330LHHXG1_LP_ODR_DIV_400 = 0x06, + ASM330LHHXG1_LP_ODR_DIV_800 = 0x07, +} asm330lhhxg1_hp_slope_xl_en_t; +int32_t asm330lhhxg1_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_hp_slope_xl_en_t val); +int32_t asm330lhhxg1_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_hp_slope_xl_en_t *val); + +int32_t asm330lhhxg1_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHHXG1_USE_SLOPE = 0, + ASM330LHHXG1_USE_HPF = 1, +} asm330lhhxg1_slope_fds_t; +int32_t asm330lhhxg1_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_slope_fds_t val); +int32_t asm330lhhxg1_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_slope_fds_t *val); + +typedef enum +{ + ASM330LHHXG1_HP_FILTER_NONE = 0x00, + ASM330LHHXG1_HP_FILTER_16mHz = 0x80, + ASM330LHHXG1_HP_FILTER_65mHz = 0x81, + ASM330LHHXG1_HP_FILTER_260mHz = 0x82, + ASM330LHHXG1_HP_FILTER_1Hz04 = 0x83, +} asm330lhhxg1_hpm_g_t; +int32_t asm330lhhxg1_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_hpm_g_t val); +int32_t asm330lhhxg1_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_hpm_g_t *val); + +typedef enum +{ + ASM330LHHXG1_PULL_UP_DISC = 0, + ASM330LHHXG1_PULL_UP_CONNECT = 1, +} asm330lhhxg1_sdo_pu_en_t; +int32_t asm330lhhxg1_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_sdo_pu_en_t val); +int32_t asm330lhhxg1_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_sdo_pu_en_t *val); + +typedef enum +{ + ASM330LHHXG1_PULL_DOWN_CONNECT = 0, + ASM330LHHXG1_PULL_DOWN_DISC = 1, +} asm330lhhxg1_pd_dis_int1_t; +int32_t asm330lhhxg1_int1_mode_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_pd_dis_int1_t val); +int32_t asm330lhhxg1_int1_mode_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_pd_dis_int1_t *val); + +typedef enum +{ + ASM330LHHXG1_SPI_4_WIRE = 0, + ASM330LHHXG1_SPI_3_WIRE = 1, +} asm330lhhxg1_sim_t; +int32_t asm330lhhxg1_spi_mode_set(const stmdev_ctx_t *ctx, asm330lhhxg1_sim_t val); +int32_t asm330lhhxg1_spi_mode_get(const stmdev_ctx_t *ctx, asm330lhhxg1_sim_t *val); + +typedef enum +{ + ASM330LHHXG1_I2C_ENABLE = 0, + ASM330LHHXG1_I2C_DISABLE = 1, +} asm330lhhxg1_i2c_disable_t; +int32_t asm330lhhxg1_i2c_interface_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_i2c_disable_t val); +int32_t asm330lhhxg1_i2c_interface_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_i2c_disable_t *val); + +typedef enum +{ + ASM330LHHXG1_I3C_DISABLE = 0x80, + ASM330LHHXG1_I3C_ENABLE_T_50us = 0x00, + ASM330LHHXG1_I3C_ENABLE_T_2us = 0x01, + ASM330LHHXG1_I3C_ENABLE_T_1ms = 0x02, + ASM330LHHXG1_I3C_ENABLE_T_25ms = 0x03, +} asm330lhhxg1_i3c_disable_t; +int32_t asm330lhhxg1_i3c_disable_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_i3c_disable_t val); +int32_t asm330lhhxg1_i3c_disable_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_i3c_disable_t *val); + +typedef struct +{ + asm330lhhxg1_int1_ctrl_t int1_ctrl; + asm330lhhxg1_md1_cfg_t md1_cfg; + asm330lhhxg1_emb_func_int1_t emb_func_int1; + asm330lhhxg1_fsm_int1_a_t fsm_int1_a; + asm330lhhxg1_fsm_int1_b_t fsm_int1_b; + asm330lhhxg1_mlc_int1_t mlc_int1; +} asm330lhhxg1_pin_int1_route_t; +int32_t asm330lhhxg1_pin_int1_route_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_pin_int1_route_t *val); +int32_t asm330lhhxg1_pin_int1_route_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_pin_int1_route_t *val); + +typedef struct +{ + asm330lhhxg1_int2_ctrl_t int2_ctrl; + asm330lhhxg1_md2_cfg_t md2_cfg; + asm330lhhxg1_emb_func_int2_t emb_func_int2; + asm330lhhxg1_fsm_int2_a_t fsm_int2_a; + asm330lhhxg1_fsm_int2_b_t fsm_int2_b; + asm330lhhxg1_mlc_int2_t mlc_int2; +} asm330lhhxg1_pin_int2_route_t; +int32_t asm330lhhxg1_pin_int2_route_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_pin_int2_route_t *val); +int32_t asm330lhhxg1_pin_int2_route_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_pin_int2_route_t *val); + +typedef enum +{ + ASM330LHHXG1_PUSH_PULL = 0, + ASM330LHHXG1_OPEN_DRAIN = 1, +} asm330lhhxg1_pp_od_t; +int32_t asm330lhhxg1_pin_mode_set(const stmdev_ctx_t *ctx, asm330lhhxg1_pp_od_t val); +int32_t asm330lhhxg1_pin_mode_get(const stmdev_ctx_t *ctx, asm330lhhxg1_pp_od_t *val); + +typedef enum +{ + ASM330LHHXG1_ACTIVE_HIGH = 0, + ASM330LHHXG1_ACTIVE_LOW = 1, +} asm330lhhxg1_h_lactive_t; +int32_t asm330lhhxg1_pin_polarity_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_h_lactive_t val); +int32_t asm330lhhxg1_pin_polarity_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_h_lactive_t *val); + +int32_t asm330lhhxg1_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHHXG1_ALL_INT_PULSED = 0, + ASM330LHHXG1_BASE_LATCHED_EMB_PULSED = 1, + ASM330LHHXG1_BASE_PULSED_EMB_LATCHED = 2, + ASM330LHHXG1_ALL_INT_LATCHED = 3, +} asm330lhhxg1_lir_t; +int32_t asm330lhhxg1_int_notification_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_lir_t val); +int32_t asm330lhhxg1_int_notification_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_lir_t *val); + +typedef enum +{ + ASM330LHHXG1_LSb_FS_DIV_64 = 0, + ASM330LHHXG1_LSb_FS_DIV_256 = 1, +} asm330lhhxg1_wake_ths_w_t; +int32_t asm330lhhxg1_wkup_ths_weight_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_wake_ths_w_t val); +int32_t asm330lhhxg1_wkup_ths_weight_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_wake_ths_w_t *val); + +int32_t asm330lhhxg1_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhhxg1_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, + uint8_t val); +int32_t asm330lhhxg1_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t asm330lhhxg1_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhhxg1_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHHXG1_DRIVE_SLEEP_CHG_EVENT = 0, + ASM330LHHXG1_DRIVE_SLEEP_STATUS = 1, +} asm330lhhxg1_sleep_status_on_int_t; +int32_t asm330lhhxg1_act_pin_notification_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_sleep_status_on_int_t val); +int32_t asm330lhhxg1_act_pin_notification_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_sleep_status_on_int_t *val); + +typedef enum +{ + ASM330LHHXG1_XL_AND_GY_NOT_AFFECTED = 0, + ASM330LHHXG1_XL_12Hz5_GY_NOT_AFFECTED = 1, + ASM330LHHXG1_XL_12Hz5_GY_SLEEP = 2, + ASM330LHHXG1_XL_12Hz5_GY_PD = 3, +} asm330lhhxg1_inact_en_t; +int32_t asm330lhhxg1_act_mode_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_inact_en_t val); +int32_t asm330lhhxg1_act_mode_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_inact_en_t *val); + +int32_t asm330lhhxg1_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHHXG1_DEG_80 = 0, + ASM330LHHXG1_DEG_70 = 1, + ASM330LHHXG1_DEG_60 = 2, + ASM330LHHXG1_DEG_50 = 3, +} asm330lhhxg1_sixd_ths_t; +int32_t asm330lhhxg1_6d_threshold_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_sixd_ths_t val); +int32_t asm330lhhxg1_6d_threshold_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_sixd_ths_t *val); + +int32_t asm330lhhxg1_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHHXG1_FF_TSH_156mg = 0, + ASM330LHHXG1_FF_TSH_219mg = 1, + ASM330LHHXG1_FF_TSH_250mg = 2, + ASM330LHHXG1_FF_TSH_312mg = 3, + ASM330LHHXG1_FF_TSH_344mg = 4, + ASM330LHHXG1_FF_TSH_406mg = 5, + ASM330LHHXG1_FF_TSH_469mg = 6, + ASM330LHHXG1_FF_TSH_500mg = 7, +} asm330lhhxg1_ff_ths_t; +int32_t asm330lhhxg1_ff_threshold_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_ff_ths_t val); +int32_t asm330lhhxg1_ff_threshold_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_ff_ths_t *val); + +int32_t asm330lhhxg1_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhhxg1_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhhxg1_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t asm330lhhxg1_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, + uint8_t val); +int32_t asm330lhhxg1_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t asm330lhhxg1_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHHXG1_XL_NOT_BATCHED = 0, + ASM330LHHXG1_XL_BATCHED_AT_12Hz5 = 1, + ASM330LHHXG1_XL_BATCHED_AT_26Hz = 2, + ASM330LHHXG1_XL_BATCHED_AT_52Hz = 3, + ASM330LHHXG1_XL_BATCHED_AT_104Hz = 4, + ASM330LHHXG1_XL_BATCHED_AT_208Hz = 5, + ASM330LHHXG1_XL_BATCHED_AT_417Hz = 6, + ASM330LHHXG1_XL_BATCHED_AT_833Hz = 7, + ASM330LHHXG1_XL_BATCHED_AT_1667Hz = 8, + ASM330LHHXG1_XL_BATCHED_AT_3333Hz = 9, + ASM330LHHXG1_XL_BATCHED_AT_6667Hz = 10, + ASM330LHHXG1_XL_BATCHED_AT_1Hz6 = 11, +} asm330lhhxg1_bdr_xl_t; +int32_t asm330lhhxg1_fifo_xl_batch_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_bdr_xl_t val); +int32_t asm330lhhxg1_fifo_xl_batch_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_bdr_xl_t *val); + +typedef enum +{ + ASM330LHHXG1_GY_NOT_BATCHED = 0, + ASM330LHHXG1_GY_BATCHED_AT_12Hz5 = 1, + ASM330LHHXG1_GY_BATCHED_AT_26Hz = 2, + ASM330LHHXG1_GY_BATCHED_AT_52Hz = 3, + ASM330LHHXG1_GY_BATCHED_AT_104Hz = 4, + ASM330LHHXG1_GY_BATCHED_AT_208Hz = 5, + ASM330LHHXG1_GY_BATCHED_AT_417Hz = 6, + ASM330LHHXG1_GY_BATCHED_AT_833Hz = 7, + ASM330LHHXG1_GY_BATCHED_AT_1667Hz = 8, + ASM330LHHXG1_GY_BATCHED_AT_3333Hz = 9, + ASM330LHHXG1_GY_BATCHED_AT_6667Hz = 10, + ASM330LHHXG1_GY_BATCHED_AT_6Hz5 = 11, +} asm330lhhxg1_bdr_gy_t; +int32_t asm330lhhxg1_fifo_gy_batch_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_bdr_gy_t val); +int32_t asm330lhhxg1_fifo_gy_batch_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_bdr_gy_t *val); + +typedef enum +{ + ASM330LHHXG1_BYPASS_MODE = 0, + ASM330LHHXG1_FIFO_MODE = 1, + ASM330LHHXG1_STREAM_TO_FIFO_MODE = 3, + ASM330LHHXG1_BYPASS_TO_STREAM_MODE = 4, + ASM330LHHXG1_STREAM_MODE = 6, + ASM330LHHXG1_BYPASS_TO_FIFO_MODE = 7, +} asm330lhhxg1_fifo_mode_t; +int32_t asm330lhhxg1_fifo_mode_set(const stmdev_ctx_t *ctx, asm330lhhxg1_fifo_mode_t val); +int32_t asm330lhhxg1_fifo_mode_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_fifo_mode_t *val); + +typedef enum +{ + ASM330LHHXG1_TEMP_NOT_BATCHED = 0, + ASM330LHHXG1_TEMP_BATCHED_AT_52Hz = 1, + ASM330LHHXG1_TEMP_BATCHED_AT_12Hz5 = 2, + ASM330LHHXG1_TEMP_BATCHED_AT_1Hz6 = 3, +} asm330lhhxg1_odr_t_batch_t; +int32_t asm330lhhxg1_fifo_temp_batch_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_odr_t_batch_t val); +int32_t asm330lhhxg1_fifo_temp_batch_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_odr_t_batch_t *val); + +typedef enum +{ + ASM330LHHXG1_NO_DECIMATION = 0, + ASM330LHHXG1_DEC_1 = 1, + ASM330LHHXG1_DEC_8 = 2, + ASM330LHHXG1_DEC_32 = 3, +} asm330lhhxg1_dec_ts_batch_t; +int32_t asm330lhhxg1_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_dec_ts_batch_t val); +int32_t asm330lhhxg1_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_dec_ts_batch_t *val); + +typedef enum +{ + ASM330LHHXG1_XL_BATCH_EVENT = 0, + ASM330LHHXG1_GYRO_BATCH_EVENT = 1, +} asm330lhhxg1_trig_counter_bdr_t; +int32_t asm330lhhxg1_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_trig_counter_bdr_t val); +int32_t asm330lhhxg1_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_trig_counter_bdr_t *val); + +int32_t asm330lhhxg1_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhhxg1_batch_counter_threshold_set(const stmdev_ctx_t *ctx, + uint16_t val); +int32_t asm330lhhxg1_batch_counter_threshold_get(const stmdev_ctx_t *ctx, + uint16_t *val); + +int32_t asm330lhhxg1_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t asm330lhhxg1_fifo_status_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_fifo_status2_t *val); + +int32_t asm330lhhxg1_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhhxg1_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhhxg1_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHHXG1_GYRO_NC_TAG = 0x01, + ASM330LHHXG1_XL_NC_TAG = 0x02, + ASM330LHHXG1_TEMPERATURE_TAG = 0x03, + ASM330LHHXG1_TIMESTAMP_TAG = 0x04, + ASM330LHHXG1_CFG_CHANGE_TAG = 0x05, + ASM330LHHXG1_SENSORHUB_SLAVE0_TAG = 0x0E, + ASM330LHHXG1_SENSORHUB_SLAVE1_TAG = 0x0F, + ASM330LHHXG1_SENSORHUB_SLAVE2_TAG = 0x10, + ASM330LHHXG1_SENSORHUB_SLAVE3_TAG = 0x11, + ASM330LHHXG1_SENSORHUB_NACK_TAG = 0x19, +} asm330lhhxg1_fifo_tag_t; +int32_t asm330lhhxg1_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_fifo_tag_t *val); + +int32_t asm330lhhxg1_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhhxg1_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhhxg1_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhhxg1_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHHXG1_DEN_DISABLE = 0, + ASM330LHHXG1_LEVEL_FIFO = 6, + ASM330LHHXG1_LEVEL_LETCHED = 3, + ASM330LHHXG1_LEVEL_TRIGGER = 2, + ASM330LHHXG1_EDGE_TRIGGER = 4, +} asm330lhhxg1_den_mode_t; +int32_t asm330lhhxg1_den_mode_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_den_mode_t val); +int32_t asm330lhhxg1_den_mode_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_den_mode_t *val); + +typedef enum +{ + ASM330LHHXG1_DEN_ACT_LOW = 0, + ASM330LHHXG1_DEN_ACT_HIGH = 1, +} asm330lhhxg1_den_lh_t; +int32_t asm330lhhxg1_den_polarity_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_den_lh_t val); +int32_t asm330lhhxg1_den_polarity_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_den_lh_t *val); + +typedef enum +{ + ASM330LHHXG1_STAMP_IN_GY_DATA = 0, + ASM330LHHXG1_STAMP_IN_XL_DATA = 1, + ASM330LHHXG1_STAMP_IN_GY_XL_DATA = 2, +} asm330lhhxg1_den_xl_g_t; +int32_t asm330lhhxg1_den_enable_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_den_xl_g_t val); +int32_t asm330lhhxg1_den_enable_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_den_xl_g_t *val); + +int32_t asm330lhhxg1_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhhxg1_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhhxg1_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhhxg1_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhhxg1_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t asm330lhhxg1_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val); +int32_t asm330lhhxg1_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t asm330lhhxg1_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint16_t *val); +int32_t asm330lhhxg1_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val); + +typedef enum +{ + ASM330LHHXG1_Z_EQ_Y = 0, + ASM330LHHXG1_Z_EQ_MIN_Y = 1, + ASM330LHHXG1_Z_EQ_X = 2, + ASM330LHHXG1_Z_EQ_MIN_X = 3, + ASM330LHHXG1_Z_EQ_MIN_Z = 4, + ASM330LHHXG1_Z_EQ_Z = 5, +} asm330lhhxg1_mag_z_axis_t; +int32_t asm330lhhxg1_mag_z_orient_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_mag_z_axis_t val); +int32_t asm330lhhxg1_mag_z_orient_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_mag_z_axis_t *val); + +typedef enum +{ + ASM330LHHXG1_Y_EQ_Y = 0, + ASM330LHHXG1_Y_EQ_MIN_Y = 1, + ASM330LHHXG1_Y_EQ_X = 2, + ASM330LHHXG1_Y_EQ_MIN_X = 3, + ASM330LHHXG1_Y_EQ_MIN_Z = 4, + ASM330LHHXG1_Y_EQ_Z = 5, +} asm330lhhxg1_mag_y_axis_t; +int32_t asm330lhhxg1_mag_y_orient_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_mag_y_axis_t val); +int32_t asm330lhhxg1_mag_y_orient_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_mag_y_axis_t *val); + +typedef enum +{ + ASM330LHHXG1_X_EQ_Y = 0, + ASM330LHHXG1_X_EQ_MIN_Y = 1, + ASM330LHHXG1_X_EQ_X = 2, + ASM330LHHXG1_X_EQ_MIN_X = 3, + ASM330LHHXG1_X_EQ_MIN_Z = 4, + ASM330LHHXG1_X_EQ_Z = 5, +} asm330lhhxg1_mag_x_axis_t; +int32_t asm330lhhxg1_mag_x_orient_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_mag_x_axis_t val); +int32_t asm330lhhxg1_mag_x_orient_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_mag_x_axis_t *val); + +typedef struct +{ + uint16_t fsm1 : 1; + uint16_t fsm2 : 1; + uint16_t fsm3 : 1; + uint16_t fsm4 : 1; + uint16_t fsm5 : 1; + uint16_t fsm6 : 1; + uint16_t fsm7 : 1; + uint16_t fsm8 : 1; + uint16_t fsm9 : 1; + uint16_t fsm10 : 1; + uint16_t fsm11 : 1; + uint16_t fsm12 : 1; + uint16_t fsm13 : 1; + uint16_t fsm14 : 1; + uint16_t fsm15 : 1; + uint16_t fsm16 : 1; +} asm330lhhxg1_fsm_status_t; +int32_t asm330lhhxg1_fsm_status_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_fsm_status_t *val); +int32_t asm330lhhxg1_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t asm330lhhxg1_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t asm330lhhxg1_emb_func_clk_dis_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_emb_func_clk_dis_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhhxg1_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + asm330lhhxg1_fsm_enable_a_t fsm_enable_a; + asm330lhhxg1_fsm_enable_b_t fsm_enable_b; +} asm330lhhxg1_emb_fsm_enable_t; +int32_t asm330lhhxg1_fsm_enable_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_emb_fsm_enable_t *val); +int32_t asm330lhhxg1_fsm_enable_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_emb_fsm_enable_t *val); + +int32_t asm330lhhxg1_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhhxg1_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); + +typedef enum +{ + ASM330LHHXG1_LC_NORMAL = 0, + ASM330LHHXG1_LC_CLEAR = 1, + ASM330LHHXG1_LC_CLEAR_DONE = 2, +} asm330lhhxg1_fsm_lc_clr_t; +int32_t asm330lhhxg1_long_clr_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_fsm_lc_clr_t val); +int32_t asm330lhhxg1_long_clr_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_fsm_lc_clr_t *val); + +typedef enum +{ + ASM330LHHXG1_ODR_FSM_12Hz5 = 0, + ASM330LHHXG1_ODR_FSM_26Hz = 1, + ASM330LHHXG1_ODR_FSM_52Hz = 2, + ASM330LHHXG1_ODR_FSM_104Hz = 3, +} asm330lhhxg1_fsm_odr_t; +int32_t asm330lhhxg1_fsm_data_rate_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_fsm_odr_t val); +int32_t asm330lhhxg1_fsm_data_rate_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_fsm_odr_t *val); + +int32_t asm330lhhxg1_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhhxg1_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhhxg1_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t asm330lhhxg1_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, + uint8_t *buff); +int32_t asm330lhhxg1_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, + uint8_t *buff); + +int32_t asm330lhhxg1_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhhxg1_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t asm330lhhxg1_mlc_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhhxg1_mlc_status_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_mlc_status_mainpage_t *val); + +typedef enum +{ + ASM330LHHXG1_ODR_PRGS_12Hz5 = 0, + ASM330LHHXG1_ODR_PRGS_26Hz = 1, + ASM330LHHXG1_ODR_PRGS_52Hz = 2, + ASM330LHHXG1_ODR_PRGS_104Hz = 3, +} asm330lhhxg1_mlc_odr_t; +int32_t asm330lhhxg1_mlc_data_rate_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_mlc_odr_t val); +int32_t asm330lhhxg1_mlc_data_rate_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_mlc_odr_t *val); + +int32_t asm330lhhxg1_mlc_init_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_mlc_init_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t asm330lhhxg1_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t asm330lhhxg1_mlc_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t asm330lhhxg1_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); + +typedef struct +{ + asm330lhhxg1_sensor_hub_1_t sh_byte_1; + asm330lhhxg1_sensor_hub_2_t sh_byte_2; + asm330lhhxg1_sensor_hub_3_t sh_byte_3; + asm330lhhxg1_sensor_hub_4_t sh_byte_4; + asm330lhhxg1_sensor_hub_5_t sh_byte_5; + asm330lhhxg1_sensor_hub_6_t sh_byte_6; + asm330lhhxg1_sensor_hub_7_t sh_byte_7; + asm330lhhxg1_sensor_hub_8_t sh_byte_8; + asm330lhhxg1_sensor_hub_9_t sh_byte_9; + asm330lhhxg1_sensor_hub_10_t sh_byte_10; + asm330lhhxg1_sensor_hub_11_t sh_byte_11; + asm330lhhxg1_sensor_hub_12_t sh_byte_12; + asm330lhhxg1_sensor_hub_13_t sh_byte_13; + asm330lhhxg1_sensor_hub_14_t sh_byte_14; + asm330lhhxg1_sensor_hub_15_t sh_byte_15; + asm330lhhxg1_sensor_hub_16_t sh_byte_16; + asm330lhhxg1_sensor_hub_17_t sh_byte_17; + asm330lhhxg1_sensor_hub_18_t sh_byte_18; +} asm330lhhxg1_emb_sh_read_t; +int32_t asm330lhhxg1_sh_read_data_raw_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_emb_sh_read_t *val); + +typedef enum +{ + ASM330LHHXG1_SLV_0 = 0, + ASM330LHHXG1_SLV_0_1 = 1, + ASM330LHHXG1_SLV_0_1_2 = 2, + ASM330LHHXG1_SLV_0_1_2_3 = 3, +} asm330lhhxg1_aux_sens_on_t; +int32_t asm330lhhxg1_sh_slave_connected_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_aux_sens_on_t val); +int32_t asm330lhhxg1_sh_slave_connected_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_aux_sens_on_t *val); + +int32_t asm330lhhxg1_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHHXG1_EXT_PULL_UP = 0, + ASM330LHHXG1_INTERNAL_PULL_UP = 1, +} asm330lhhxg1_shub_pu_en_t; +int32_t asm330lhhxg1_sh_pin_mode_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_shub_pu_en_t val); +int32_t asm330lhhxg1_sh_pin_mode_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_shub_pu_en_t *val); + +int32_t asm330lhhxg1_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t asm330lhhxg1_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHHXG1_EXT_ON_INT2_PIN = 0, + ASM330LHHXG1_XL_GY_DRDY = 1, +} asm330lhhxg1_start_config_t; +int32_t asm330lhhxg1_sh_syncro_mode_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_start_config_t val); +int32_t asm330lhhxg1_sh_syncro_mode_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_start_config_t *val); + +typedef enum +{ + ASM330LHHXG1_EACH_SH_CYCLE = 0, + ASM330LHHXG1_ONLY_FIRST_CYCLE = 1, +} asm330lhhxg1_write_once_t; +int32_t asm330lhhxg1_sh_write_mode_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_write_once_t val); +int32_t asm330lhhxg1_sh_write_mode_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_write_once_t *val); + +int32_t asm330lhhxg1_sh_reset_set(const stmdev_ctx_t *ctx); +int32_t asm330lhhxg1_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ASM330LHHXG1_SH_ODR_104Hz = 0, + ASM330LHHXG1_SH_ODR_52Hz = 1, + ASM330LHHXG1_SH_ODR_26Hz = 2, + ASM330LHHXG1_SH_ODR_13Hz = 3, +} asm330lhhxg1_shub_odr_t; +int32_t asm330lhhxg1_sh_data_rate_set(const stmdev_ctx_t *ctx, + asm330lhhxg1_shub_odr_t val); +int32_t asm330lhhxg1_sh_data_rate_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_shub_odr_t *val); + +typedef struct +{ + uint8_t slv0_add; + uint8_t slv0_subadd; + uint8_t slv0_data; +} asm330lhhxg1_sh_cfg_write_t; +int32_t asm330lhhxg1_sh_cfg_write(const stmdev_ctx_t *ctx, + asm330lhhxg1_sh_cfg_write_t *val); + +typedef struct +{ + uint8_t slv_add; + uint8_t slv_subadd; + uint8_t slv_len; +} asm330lhhxg1_sh_cfg_read_t; +int32_t asm330lhhxg1_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, + asm330lhhxg1_sh_cfg_read_t *val); +int32_t asm330lhhxg1_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, + asm330lhhxg1_sh_cfg_read_t *val); +int32_t asm330lhhxg1_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, + asm330lhhxg1_sh_cfg_read_t *val); +int32_t asm330lhhxg1_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, + asm330lhhxg1_sh_cfg_read_t *val); + +int32_t asm330lhhxg1_sh_status_get(const stmdev_ctx_t *ctx, + asm330lhhxg1_status_master_t *val); + +/** + *@} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ASM330LHHXG1_REGS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.c b/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.c index 1f9f4129..12080cd8 100644 --- a/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.c +++ b/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.c @@ -46,12 +46,14 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak h3lis100dl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak h3lis100dl_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +69,14 @@ int32_t __weak h3lis100dl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak h3lis100dl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak h3lis100dl_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -116,7 +120,7 @@ float_t h3lis100dl_from_fs100g_to_mg(int8_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t h3lis100dl_axis_x_data_set(const stmdev_ctx_t *ctx, uint8_t val) { h3lis100dl_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -142,7 +146,7 @@ int32_t h3lis100dl_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t h3lis100dl_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val) { h3lis100dl_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -162,7 +166,7 @@ int32_t h3lis100dl_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t h3lis100dl_axis_y_data_set(const stmdev_ctx_t *ctx, uint8_t val) { h3lis100dl_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -188,7 +192,7 @@ int32_t h3lis100dl_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t h3lis100dl_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val) { h3lis100dl_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -208,7 +212,7 @@ int32_t h3lis100dl_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t h3lis100dl_axis_z_data_set(const stmdev_ctx_t *ctx, uint8_t val) { h3lis100dl_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -234,7 +238,7 @@ int32_t h3lis100dl_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t h3lis100dl_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val) { h3lis100dl_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -254,7 +258,7 @@ int32_t h3lis100dl_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_data_rate_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_data_rate_set(const stmdev_ctx_t *ctx, h3lis100dl_dr_t val) { h3lis100dl_ctrl_reg1_t ctrl_reg1; @@ -282,7 +286,7 @@ int32_t h3lis100dl_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_data_rate_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_data_rate_get(const stmdev_ctx_t *ctx, h3lis100dl_dr_t *val) { h3lis100dl_ctrl_reg1_t ctrl_reg1; @@ -345,7 +349,7 @@ int32_t h3lis100dl_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_reference_mode_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_reference_mode_set(const stmdev_ctx_t *ctx, h3lis100dl_hpm_t val) { h3lis100dl_ctrl_reg2_t ctrl_reg2; @@ -372,7 +376,7 @@ int32_t h3lis100dl_reference_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_reference_mode_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_reference_mode_get(const stmdev_ctx_t *ctx, h3lis100dl_hpm_t *val) { h3lis100dl_ctrl_reg2_t ctrl_reg2; @@ -407,7 +411,7 @@ int32_t h3lis100dl_reference_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_status_reg_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_status_reg_get(const stmdev_ctx_t *ctx, h3lis100dl_status_reg_t *val) { int32_t ret; @@ -425,7 +429,7 @@ int32_t h3lis100dl_status_reg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { h3lis100dl_status_reg_t status_reg; @@ -459,7 +463,7 @@ int32_t h3lis100dl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_acceleration_raw_get(const stmdev_ctx_t *ctx, int8_t *val) { int32_t ret; @@ -491,7 +495,7 @@ int32_t h3lis100dl_acceleration_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t h3lis100dl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -508,7 +512,7 @@ int32_t h3lis100dl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t h3lis100dl_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { h3lis100dl_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -534,7 +538,7 @@ int32_t h3lis100dl_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t h3lis100dl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { h3lis100dl_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -567,7 +571,7 @@ int32_t h3lis100dl_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_hp_bandwidth_set(const stmdev_ctx_t *ctx, h3lis100dl_hpcf_t val) { h3lis100dl_ctrl_reg2_t ctrl_reg2; @@ -594,7 +598,7 @@ int32_t h3lis100dl_hp_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_hp_bandwidth_get(const stmdev_ctx_t *ctx, h3lis100dl_hpcf_t *val) { h3lis100dl_ctrl_reg2_t ctrl_reg2; @@ -637,7 +641,7 @@ int32_t h3lis100dl_hp_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_hp_path_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_hp_path_set(const stmdev_ctx_t *ctx, h3lis100dl_hpen_t val) { h3lis100dl_ctrl_reg2_t ctrl_reg2; @@ -665,7 +669,7 @@ int32_t h3lis100dl_hp_path_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_hp_path_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_hp_path_get(const stmdev_ctx_t *ctx, h3lis100dl_hpen_t *val) { h3lis100dl_ctrl_reg2_t ctrl_reg2; @@ -728,7 +732,7 @@ int32_t h3lis100dl_hp_path_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_hp_reset_get(stmdev_ctx_t *ctx) +int32_t h3lis100dl_hp_reset_get(const stmdev_ctx_t *ctx) { uint8_t dummy; int32_t ret; @@ -747,7 +751,7 @@ int32_t h3lis100dl_hp_reset_get(stmdev_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_hp_reference_value_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_hp_reference_value_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; @@ -765,7 +769,7 @@ int32_t h3lis100dl_hp_reference_value_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_hp_reference_value_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_hp_reference_value_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -796,7 +800,7 @@ int32_t h3lis100dl_hp_reference_value_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_spi_mode_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_spi_mode_set(const stmdev_ctx_t *ctx, h3lis100dl_sim_t val) { h3lis100dl_ctrl_reg4_t ctrl_reg4; @@ -823,7 +827,7 @@ int32_t h3lis100dl_spi_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_spi_mode_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_spi_mode_get(const stmdev_ctx_t *ctx, h3lis100dl_sim_t *val) { h3lis100dl_ctrl_reg4_t ctrl_reg4; @@ -871,7 +875,7 @@ int32_t h3lis100dl_spi_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_pin_int1_route_set(const stmdev_ctx_t *ctx, h3lis100dl_i1_cfg_t val) { h3lis100dl_ctrl_reg3_t ctrl_reg3; @@ -898,7 +902,7 @@ int32_t h3lis100dl_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_pin_int1_route_get(const stmdev_ctx_t *ctx, h3lis100dl_i1_cfg_t *val) { h3lis100dl_ctrl_reg3_t ctrl_reg3; @@ -942,7 +946,7 @@ int32_t h3lis100dl_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_int1_notification_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int1_notification_set(const stmdev_ctx_t *ctx, h3lis100dl_lir1_t val) { h3lis100dl_ctrl_reg3_t ctrl_reg3; @@ -970,7 +974,7 @@ int32_t h3lis100dl_int1_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_int1_notification_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int1_notification_get(const stmdev_ctx_t *ctx, h3lis100dl_lir1_t *val) { h3lis100dl_ctrl_reg3_t ctrl_reg3; @@ -1005,7 +1009,7 @@ int32_t h3lis100dl_int1_notification_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_pin_int2_route_set(const stmdev_ctx_t *ctx, h3lis100dl_i2_cfg_t val) { h3lis100dl_ctrl_reg3_t ctrl_reg3; @@ -1032,7 +1036,7 @@ int32_t h3lis100dl_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_pin_int2_route_get(const stmdev_ctx_t *ctx, h3lis100dl_i2_cfg_t *val) { h3lis100dl_ctrl_reg3_t ctrl_reg3; @@ -1076,7 +1080,7 @@ int32_t h3lis100dl_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_int2_notification_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int2_notification_set(const stmdev_ctx_t *ctx, h3lis100dl_lir2_t val) { h3lis100dl_ctrl_reg3_t ctrl_reg3; @@ -1104,7 +1108,7 @@ int32_t h3lis100dl_int2_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_int2_notification_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int2_notification_get(const stmdev_ctx_t *ctx, h3lis100dl_lir2_t *val) { h3lis100dl_ctrl_reg3_t ctrl_reg3; @@ -1139,7 +1143,7 @@ int32_t h3lis100dl_int2_notification_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_pin_mode_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_pin_mode_set(const stmdev_ctx_t *ctx, h3lis100dl_pp_od_t val) { h3lis100dl_ctrl_reg3_t ctrl_reg3; @@ -1166,7 +1170,7 @@ int32_t h3lis100dl_pin_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_pin_mode_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_pin_mode_get(const stmdev_ctx_t *ctx, h3lis100dl_pp_od_t *val) { h3lis100dl_ctrl_reg3_t ctrl_reg3; @@ -1201,7 +1205,7 @@ int32_t h3lis100dl_pin_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_pin_polarity_set(const stmdev_ctx_t *ctx, h3lis100dl_ihl_t val) { h3lis100dl_ctrl_reg3_t ctrl_reg3; @@ -1228,7 +1232,7 @@ int32_t h3lis100dl_pin_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_pin_polarity_get(const stmdev_ctx_t *ctx, h3lis100dl_ihl_t *val) { h3lis100dl_ctrl_reg3_t ctrl_reg3; @@ -1276,7 +1280,7 @@ int32_t h3lis100dl_pin_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_int1_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int1_on_threshold_conf_set(const stmdev_ctx_t *ctx, int1_on_th_conf_t val) { h3lis100dl_int1_cfg_t int1_cfg; @@ -1308,7 +1312,7 @@ int32_t h3lis100dl_int1_on_threshold_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_int1_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int1_on_threshold_conf_get(const stmdev_ctx_t *ctx, int1_on_th_conf_t *val) { h3lis100dl_int1_cfg_t int1_cfg; @@ -1334,7 +1338,7 @@ int32_t h3lis100dl_int1_on_threshold_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_int1_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int1_on_threshold_mode_set(const stmdev_ctx_t *ctx, h3lis100dl_int1_aoi_t val) { h3lis100dl_int1_cfg_t int1_cfg; @@ -1361,7 +1365,7 @@ int32_t h3lis100dl_int1_on_threshold_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_int1_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int1_on_threshold_mode_get(const stmdev_ctx_t *ctx, h3lis100dl_int1_aoi_t *val) { h3lis100dl_int1_cfg_t int1_cfg; @@ -1396,7 +1400,7 @@ int32_t h3lis100dl_int1_on_threshold_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_int1_src_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int1_src_get(const stmdev_ctx_t *ctx, h3lis100dl_int1_src_t *val) { int32_t ret; @@ -1414,7 +1418,7 @@ int32_t h3lis100dl_int1_src_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t h3lis100dl_int1_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { h3lis100dl_int1_ths_t int1_ths; int32_t ret; @@ -1440,7 +1444,7 @@ int32_t h3lis100dl_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t h3lis100dl_int1_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { h3lis100dl_int1_ths_t int1_ths; int32_t ret; @@ -1460,7 +1464,7 @@ int32_t h3lis100dl_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t h3lis100dl_int1_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { h3lis100dl_int1_duration_t int1_duration; int32_t ret; @@ -1486,7 +1490,7 @@ int32_t h3lis100dl_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t h3lis100dl_int1_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { h3lis100dl_int1_duration_t int1_duration; int32_t ret; @@ -1506,7 +1510,7 @@ int32_t h3lis100dl_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_int2_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int2_on_threshold_conf_set(const stmdev_ctx_t *ctx, int2_on_th_conf_t val) { h3lis100dl_int2_cfg_t int2_cfg; @@ -1538,7 +1542,7 @@ int32_t h3lis100dl_int2_on_threshold_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_int2_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int2_on_threshold_conf_get(const stmdev_ctx_t *ctx, int2_on_th_conf_t *val) { h3lis100dl_int2_cfg_t int2_cfg; @@ -1564,7 +1568,7 @@ int32_t h3lis100dl_int2_on_threshold_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_int2_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int2_on_threshold_mode_set(const stmdev_ctx_t *ctx, h3lis100dl_int2_aoi_t val) { h3lis100dl_int2_cfg_t int2_cfg; @@ -1591,7 +1595,7 @@ int32_t h3lis100dl_int2_on_threshold_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_int2_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int2_on_threshold_mode_get(const stmdev_ctx_t *ctx, h3lis100dl_int2_aoi_t *val) { h3lis100dl_int2_cfg_t int2_cfg; @@ -1626,7 +1630,7 @@ int32_t h3lis100dl_int2_on_threshold_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_int2_src_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int2_src_get(const stmdev_ctx_t *ctx, h3lis100dl_int2_src_t *val) { int32_t ret; @@ -1644,7 +1648,7 @@ int32_t h3lis100dl_int2_src_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t h3lis100dl_int2_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { h3lis100dl_int2_ths_t int2_ths; int32_t ret; @@ -1670,7 +1674,7 @@ int32_t h3lis100dl_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t h3lis100dl_int2_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { h3lis100dl_int2_ths_t int2_ths; int32_t ret; @@ -1690,7 +1694,7 @@ int32_t h3lis100dl_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t h3lis100dl_int2_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { h3lis100dl_int2_duration_t int2_duration; int32_t ret; @@ -1716,7 +1720,7 @@ int32_t h3lis100dl_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t h3lis100dl_int2_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { h3lis100dl_int2_duration_t int2_duration; int32_t ret; @@ -1749,7 +1753,7 @@ int32_t h3lis100dl_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t h3lis100dl_wkup_to_sleep_set(const stmdev_ctx_t *ctx, uint8_t val) { h3lis100dl_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1775,7 +1779,7 @@ int32_t h3lis100dl_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis100dl_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t h3lis100dl_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val) { h3lis100dl_ctrl_reg5_t ctrl_reg5; int32_t ret; diff --git a/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.h b/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.h index 211cdd8c..1ea5e20f 100644 --- a/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.h +++ b/sensor/stmemsc/h3lis100dl_STdC/driver/h3lis100dl_reg.h @@ -485,23 +485,23 @@ typedef union * them with a custom implementation. */ -int32_t h3lis100dl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t h3lis100dl_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t h3lis100dl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t h3lis100dl_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); float_t h3lis100dl_from_fs100g_to_mg(int8_t lsb); -int32_t h3lis100dl_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t h3lis100dl_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t h3lis100dl_axis_x_data_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t h3lis100dl_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t h3lis100dl_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t h3lis100dl_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t h3lis100dl_axis_y_data_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t h3lis100dl_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t h3lis100dl_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t h3lis100dl_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t h3lis100dl_axis_z_data_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t h3lis100dl_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -515,9 +515,9 @@ typedef enum H3LIS100DL_ODR_100Hz = 0x11, H3LIS100DL_ODR_400Hz = 0x21, } h3lis100dl_dr_t; -int32_t h3lis100dl_data_rate_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_data_rate_set(const stmdev_ctx_t *ctx, h3lis100dl_dr_t val); -int32_t h3lis100dl_data_rate_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_data_rate_get(const stmdev_ctx_t *ctx, h3lis100dl_dr_t *val); typedef enum @@ -525,24 +525,24 @@ typedef enum H3LIS100DL_NORMAL_MODE = 0, H3LIS100DL_REF_MODE_ENABLE = 1, } h3lis100dl_hpm_t; -int32_t h3lis100dl_reference_mode_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_reference_mode_set(const stmdev_ctx_t *ctx, h3lis100dl_hpm_t val); -int32_t h3lis100dl_reference_mode_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_reference_mode_get(const stmdev_ctx_t *ctx, h3lis100dl_hpm_t *val); -int32_t h3lis100dl_status_reg_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_status_reg_get(const stmdev_ctx_t *ctx, h3lis100dl_status_reg_t *val); -int32_t h3lis100dl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t h3lis100dl_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_acceleration_raw_get(const stmdev_ctx_t *ctx, int8_t *val); -int32_t h3lis100dl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t h3lis100dl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t h3lis100dl_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t h3lis100dl_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t h3lis100dl_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t h3lis100dl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -551,9 +551,9 @@ typedef enum H3LIS100DL_CUT_OFF_32Hz = 2, H3LIS100DL_CUT_OFF_64Hz = 3, } h3lis100dl_hpcf_t; -int32_t h3lis100dl_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_hp_bandwidth_set(const stmdev_ctx_t *ctx, h3lis100dl_hpcf_t val); -int32_t h3lis100dl_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_hp_bandwidth_get(const stmdev_ctx_t *ctx, h3lis100dl_hpcf_t *val); typedef enum @@ -567,16 +567,16 @@ typedef enum H3LIS100DL_HP_ON_INT2_OUT = 6, H3LIS100DL_HP_ON_INT1_OUT = 5, } h3lis100dl_hpen_t; -int32_t h3lis100dl_hp_path_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_hp_path_set(const stmdev_ctx_t *ctx, h3lis100dl_hpen_t val); -int32_t h3lis100dl_hp_path_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_hp_path_get(const stmdev_ctx_t *ctx, h3lis100dl_hpen_t *val); -int32_t h3lis100dl_hp_reset_get(stmdev_ctx_t *ctx); +int32_t h3lis100dl_hp_reset_get(const stmdev_ctx_t *ctx); -int32_t h3lis100dl_hp_reference_value_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_hp_reference_value_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t h3lis100dl_hp_reference_value_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_hp_reference_value_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -584,9 +584,9 @@ typedef enum H3LIS100DL_SPI_4_WIRE = 0, H3LIS100DL_SPI_3_WIRE = 1, } h3lis100dl_sim_t; -int32_t h3lis100dl_spi_mode_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_spi_mode_set(const stmdev_ctx_t *ctx, h3lis100dl_sim_t val); -int32_t h3lis100dl_spi_mode_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_spi_mode_get(const stmdev_ctx_t *ctx, h3lis100dl_sim_t *val); typedef enum @@ -596,9 +596,9 @@ typedef enum H3LIS100DL_PAD1_DRDY = 2, H3LIS100DL_PAD1_BOOT = 3, } h3lis100dl_i1_cfg_t; -int32_t h3lis100dl_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_pin_int1_route_set(const stmdev_ctx_t *ctx, h3lis100dl_i1_cfg_t val); -int32_t h3lis100dl_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_pin_int1_route_get(const stmdev_ctx_t *ctx, h3lis100dl_i1_cfg_t *val); typedef enum @@ -606,9 +606,9 @@ typedef enum H3LIS100DL_INT1_PULSED = 0, H3LIS100DL_INT1_LATCHED = 1, } h3lis100dl_lir1_t; -int32_t h3lis100dl_int1_notification_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int1_notification_set(const stmdev_ctx_t *ctx, h3lis100dl_lir1_t val); -int32_t h3lis100dl_int1_notification_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int1_notification_get(const stmdev_ctx_t *ctx, h3lis100dl_lir1_t *val); typedef enum @@ -618,9 +618,9 @@ typedef enum H3LIS100DL_PAD2_DRDY = 2, H3LIS100DL_PAD2_BOOT = 3, } h3lis100dl_i2_cfg_t; -int32_t h3lis100dl_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_pin_int2_route_set(const stmdev_ctx_t *ctx, h3lis100dl_i2_cfg_t val); -int32_t h3lis100dl_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_pin_int2_route_get(const stmdev_ctx_t *ctx, h3lis100dl_i2_cfg_t *val); typedef enum @@ -628,9 +628,9 @@ typedef enum H3LIS100DL_INT2_PULSED = 0, H3LIS100DL_INT2_LATCHED = 1, } h3lis100dl_lir2_t; -int32_t h3lis100dl_int2_notification_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int2_notification_set(const stmdev_ctx_t *ctx, h3lis100dl_lir2_t val); -int32_t h3lis100dl_int2_notification_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int2_notification_get(const stmdev_ctx_t *ctx, h3lis100dl_lir2_t *val); typedef enum @@ -638,9 +638,9 @@ typedef enum H3LIS100DL_PUSH_PULL = 0, H3LIS100DL_OPEN_DRAIN = 1, } h3lis100dl_pp_od_t; -int32_t h3lis100dl_pin_mode_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_pin_mode_set(const stmdev_ctx_t *ctx, h3lis100dl_pp_od_t val); -int32_t h3lis100dl_pin_mode_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_pin_mode_get(const stmdev_ctx_t *ctx, h3lis100dl_pp_od_t *val); typedef enum @@ -648,9 +648,9 @@ typedef enum H3LIS100DL_ACTIVE_HIGH = 0, H3LIS100DL_ACTIVE_LOW = 1, } h3lis100dl_ihl_t; -int32_t h3lis100dl_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_pin_polarity_set(const stmdev_ctx_t *ctx, h3lis100dl_ihl_t val); -int32_t h3lis100dl_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_pin_polarity_get(const stmdev_ctx_t *ctx, h3lis100dl_ihl_t *val); typedef struct @@ -662,9 +662,9 @@ typedef struct uint8_t int1_zlie : 1; uint8_t int1_zhie : 1; } int1_on_th_conf_t; -int32_t h3lis100dl_int1_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int1_on_threshold_conf_set(const stmdev_ctx_t *ctx, int1_on_th_conf_t val); -int32_t h3lis100dl_int1_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int1_on_threshold_conf_get(const stmdev_ctx_t *ctx, int1_on_th_conf_t *val); typedef enum @@ -672,19 +672,19 @@ typedef enum H3LIS100DL_INT1_ON_THRESHOLD_OR = 0, H3LIS100DL_INT1_ON_THRESHOLD_AND = 1, } h3lis100dl_int1_aoi_t; -int32_t h3lis100dl_int1_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int1_on_threshold_mode_set(const stmdev_ctx_t *ctx, h3lis100dl_int1_aoi_t val); -int32_t h3lis100dl_int1_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int1_on_threshold_mode_get(const stmdev_ctx_t *ctx, h3lis100dl_int1_aoi_t *val); -int32_t h3lis100dl_int1_src_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int1_src_get(const stmdev_ctx_t *ctx, h3lis100dl_int1_src_t *val); -int32_t h3lis100dl_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t h3lis100dl_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t h3lis100dl_int1_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t h3lis100dl_int1_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t h3lis100dl_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t h3lis100dl_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t h3lis100dl_int1_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t h3lis100dl_int1_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -695,9 +695,9 @@ typedef struct uint8_t int2_zlie : 1; uint8_t int2_zhie : 1; } int2_on_th_conf_t; -int32_t h3lis100dl_int2_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int2_on_threshold_conf_set(const stmdev_ctx_t *ctx, int2_on_th_conf_t val); -int32_t h3lis100dl_int2_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int2_on_threshold_conf_get(const stmdev_ctx_t *ctx, int2_on_th_conf_t *val); typedef enum @@ -705,22 +705,22 @@ typedef enum H3LIS100DL_INT2_ON_THRESHOLD_OR = 0, H3LIS100DL_INT2_ON_THRESHOLD_AND = 1, } h3lis100dl_int2_aoi_t; -int32_t h3lis100dl_int2_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int2_on_threshold_mode_set(const stmdev_ctx_t *ctx, h3lis100dl_int2_aoi_t val); -int32_t h3lis100dl_int2_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int2_on_threshold_mode_get(const stmdev_ctx_t *ctx, h3lis100dl_int2_aoi_t *val); -int32_t h3lis100dl_int2_src_get(stmdev_ctx_t *ctx, +int32_t h3lis100dl_int2_src_get(const stmdev_ctx_t *ctx, h3lis100dl_int2_src_t *val); -int32_t h3lis100dl_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t h3lis100dl_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t h3lis100dl_int2_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t h3lis100dl_int2_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t h3lis100dl_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t h3lis100dl_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t h3lis100dl_int2_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t h3lis100dl_int2_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t h3lis100dl_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t h3lis100dl_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t h3lis100dl_wkup_to_sleep_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t h3lis100dl_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val); /** *@} diff --git a/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.c b/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.c index 46bfcbed..4217c96d 100644 --- a/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.c +++ b/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.c @@ -46,12 +46,14 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak h3lis331dl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak h3lis331dl_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +69,14 @@ int32_t __weak h3lis331dl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak h3lis331dl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak h3lis331dl_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -126,7 +130,7 @@ float_t h3lis331dl_from_fs400_to_mg(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t h3lis331dl_axis_x_data_set(const stmdev_ctx_t *ctx, uint8_t val) { h3lis331dl_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -152,7 +156,7 @@ int32_t h3lis331dl_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t h3lis331dl_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val) { h3lis331dl_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -172,7 +176,7 @@ int32_t h3lis331dl_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t h3lis331dl_axis_y_data_set(const stmdev_ctx_t *ctx, uint8_t val) { h3lis331dl_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -198,7 +202,7 @@ int32_t h3lis331dl_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t h3lis331dl_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val) { h3lis331dl_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -218,7 +222,7 @@ int32_t h3lis331dl_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t h3lis331dl_axis_z_data_set(const stmdev_ctx_t *ctx, uint8_t val) { h3lis331dl_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -244,7 +248,7 @@ int32_t h3lis331dl_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t h3lis331dl_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val) { h3lis331dl_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -264,7 +268,7 @@ int32_t h3lis331dl_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_data_rate_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_data_rate_set(const stmdev_ctx_t *ctx, h3lis331dl_dr_t val) { h3lis331dl_ctrl_reg1_t ctrl_reg1; @@ -292,7 +296,7 @@ int32_t h3lis331dl_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_data_rate_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_data_rate_get(const stmdev_ctx_t *ctx, h3lis331dl_dr_t *val) { h3lis331dl_ctrl_reg1_t ctrl_reg1; @@ -359,7 +363,7 @@ int32_t h3lis331dl_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_reference_mode_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_reference_mode_set(const stmdev_ctx_t *ctx, h3lis331dl_hpm_t val) { h3lis331dl_ctrl_reg2_t ctrl_reg2; @@ -386,7 +390,7 @@ int32_t h3lis331dl_reference_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_reference_mode_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_reference_mode_get(const stmdev_ctx_t *ctx, h3lis331dl_hpm_t *val) { h3lis331dl_ctrl_reg2_t ctrl_reg2; @@ -421,7 +425,7 @@ int32_t h3lis331dl_reference_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_full_scale_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_full_scale_set(const stmdev_ctx_t *ctx, h3lis331dl_fs_t val) { h3lis331dl_ctrl_reg4_t ctrl_reg4; @@ -448,7 +452,7 @@ int32_t h3lis331dl_full_scale_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_full_scale_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_full_scale_get(const stmdev_ctx_t *ctx, h3lis331dl_fs_t *val) { h3lis331dl_ctrl_reg4_t ctrl_reg4; @@ -487,7 +491,7 @@ int32_t h3lis331dl_full_scale_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_block_data_update_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { h3lis331dl_ctrl_reg4_t ctrl_reg4; @@ -514,7 +518,7 @@ int32_t h3lis331dl_block_data_update_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_block_data_update_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { h3lis331dl_ctrl_reg4_t ctrl_reg4; @@ -535,7 +539,7 @@ int32_t h3lis331dl_block_data_update_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_status_reg_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_status_reg_get(const stmdev_ctx_t *ctx, h3lis331dl_status_reg_t *val) { int32_t ret; @@ -554,7 +558,7 @@ int32_t h3lis331dl_status_reg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { h3lis331dl_status_reg_t status_reg; @@ -588,7 +592,7 @@ int32_t h3lis331dl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -625,7 +629,7 @@ int32_t h3lis331dl_acceleration_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t h3lis331dl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -642,7 +646,7 @@ int32_t h3lis331dl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t h3lis331dl_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { h3lis331dl_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -668,7 +672,7 @@ int32_t h3lis331dl_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t h3lis331dl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { h3lis331dl_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -688,7 +692,7 @@ int32_t h3lis331dl_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_data_format_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_data_format_set(const stmdev_ctx_t *ctx, h3lis331dl_ble_t val) { h3lis331dl_ctrl_reg4_t ctrl_reg4; @@ -715,7 +719,7 @@ int32_t h3lis331dl_data_format_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_data_format_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_data_format_get(const stmdev_ctx_t *ctx, h3lis331dl_ble_t *val) { h3lis331dl_ctrl_reg4_t ctrl_reg4; @@ -763,7 +767,7 @@ int32_t h3lis331dl_data_format_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_hp_bandwidth_set(const stmdev_ctx_t *ctx, h3lis331dl_hpcf_t val) { h3lis331dl_ctrl_reg2_t ctrl_reg2; @@ -790,7 +794,7 @@ int32_t h3lis331dl_hp_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_hp_bandwidth_get(const stmdev_ctx_t *ctx, h3lis331dl_hpcf_t *val) { h3lis331dl_ctrl_reg2_t ctrl_reg2; @@ -833,7 +837,7 @@ int32_t h3lis331dl_hp_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_hp_path_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_hp_path_set(const stmdev_ctx_t *ctx, h3lis331dl_hpen_t val) { h3lis331dl_ctrl_reg2_t ctrl_reg2; @@ -861,7 +865,7 @@ int32_t h3lis331dl_hp_path_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_hp_path_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_hp_path_get(const stmdev_ctx_t *ctx, h3lis331dl_hpen_t *val) { h3lis331dl_ctrl_reg2_t ctrl_reg2; @@ -924,7 +928,7 @@ int32_t h3lis331dl_hp_path_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_hp_reset_get(stmdev_ctx_t *ctx) +int32_t h3lis331dl_hp_reset_get(const stmdev_ctx_t *ctx) { uint8_t dummy; int32_t ret; @@ -943,7 +947,7 @@ int32_t h3lis331dl_hp_reset_get(stmdev_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_hp_reference_value_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_hp_reference_value_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; @@ -961,7 +965,7 @@ int32_t h3lis331dl_hp_reference_value_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_hp_reference_value_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_hp_reference_value_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -992,7 +996,7 @@ int32_t h3lis331dl_hp_reference_value_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_spi_mode_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_spi_mode_set(const stmdev_ctx_t *ctx, h3lis331dl_sim_t val) { h3lis331dl_ctrl_reg4_t ctrl_reg4; @@ -1019,7 +1023,7 @@ int32_t h3lis331dl_spi_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_spi_mode_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_spi_mode_get(const stmdev_ctx_t *ctx, h3lis331dl_sim_t *val) { h3lis331dl_ctrl_reg4_t ctrl_reg4; @@ -1067,7 +1071,7 @@ int32_t h3lis331dl_spi_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_pin_int1_route_set(const stmdev_ctx_t *ctx, h3lis331dl_i1_cfg_t val) { h3lis331dl_ctrl_reg3_t ctrl_reg3; @@ -1094,7 +1098,7 @@ int32_t h3lis331dl_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_pin_int1_route_get(const stmdev_ctx_t *ctx, h3lis331dl_i1_cfg_t *val) { h3lis331dl_ctrl_reg3_t ctrl_reg3; @@ -1138,7 +1142,7 @@ int32_t h3lis331dl_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_int1_notification_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int1_notification_set(const stmdev_ctx_t *ctx, h3lis331dl_lir1_t val) { h3lis331dl_ctrl_reg3_t ctrl_reg3; @@ -1166,7 +1170,7 @@ int32_t h3lis331dl_int1_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_int1_notification_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int1_notification_get(const stmdev_ctx_t *ctx, h3lis331dl_lir1_t *val) { h3lis331dl_ctrl_reg3_t ctrl_reg3; @@ -1201,7 +1205,7 @@ int32_t h3lis331dl_int1_notification_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_pin_int2_route_set(const stmdev_ctx_t *ctx, h3lis331dl_i2_cfg_t val) { h3lis331dl_ctrl_reg3_t ctrl_reg3; @@ -1228,7 +1232,7 @@ int32_t h3lis331dl_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_pin_int2_route_get(const stmdev_ctx_t *ctx, h3lis331dl_i2_cfg_t *val) { h3lis331dl_ctrl_reg3_t ctrl_reg3; @@ -1272,7 +1276,7 @@ int32_t h3lis331dl_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_int2_notification_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int2_notification_set(const stmdev_ctx_t *ctx, h3lis331dl_lir2_t val) { h3lis331dl_ctrl_reg3_t ctrl_reg3; @@ -1300,7 +1304,7 @@ int32_t h3lis331dl_int2_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_int2_notification_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int2_notification_get(const stmdev_ctx_t *ctx, h3lis331dl_lir2_t *val) { h3lis331dl_ctrl_reg3_t ctrl_reg3; @@ -1335,7 +1339,7 @@ int32_t h3lis331dl_int2_notification_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_pin_mode_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_pin_mode_set(const stmdev_ctx_t *ctx, h3lis331dl_pp_od_t val) { h3lis331dl_ctrl_reg3_t ctrl_reg3; @@ -1362,7 +1366,7 @@ int32_t h3lis331dl_pin_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_pin_mode_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_pin_mode_get(const stmdev_ctx_t *ctx, h3lis331dl_pp_od_t *val) { h3lis331dl_ctrl_reg3_t ctrl_reg3; @@ -1397,7 +1401,7 @@ int32_t h3lis331dl_pin_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_pin_polarity_set(const stmdev_ctx_t *ctx, h3lis331dl_ihl_t val) { h3lis331dl_ctrl_reg3_t ctrl_reg3; @@ -1424,7 +1428,7 @@ int32_t h3lis331dl_pin_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_pin_polarity_get(const stmdev_ctx_t *ctx, h3lis331dl_ihl_t *val) { h3lis331dl_ctrl_reg3_t ctrl_reg3; @@ -1472,7 +1476,7 @@ int32_t h3lis331dl_pin_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_int1_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int1_on_threshold_conf_set(const stmdev_ctx_t *ctx, h3lis331dl_int1_on_th_conf_t val) { h3lis331dl_int1_cfg_t int1_cfg; @@ -1504,7 +1508,7 @@ int32_t h3lis331dl_int1_on_threshold_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_int1_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int1_on_threshold_conf_get(const stmdev_ctx_t *ctx, h3lis331dl_int1_on_th_conf_t *val) { h3lis331dl_int1_cfg_t int1_cfg; @@ -1530,7 +1534,7 @@ int32_t h3lis331dl_int1_on_threshold_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_int1_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int1_on_threshold_mode_set(const stmdev_ctx_t *ctx, h3lis331dl_int1_aoi_t val) { h3lis331dl_int1_cfg_t int1_cfg; @@ -1557,7 +1561,7 @@ int32_t h3lis331dl_int1_on_threshold_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_int1_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int1_on_threshold_mode_get(const stmdev_ctx_t *ctx, h3lis331dl_int1_aoi_t *val) { h3lis331dl_int1_cfg_t int1_cfg; @@ -1592,7 +1596,7 @@ int32_t h3lis331dl_int1_on_threshold_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_int1_src_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int1_src_get(const stmdev_ctx_t *ctx, h3lis331dl_int1_src_t *val) { int32_t ret; @@ -1610,7 +1614,7 @@ int32_t h3lis331dl_int1_src_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t h3lis331dl_int1_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { h3lis331dl_int1_ths_t int1_ths; int32_t ret; @@ -1636,7 +1640,7 @@ int32_t h3lis331dl_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t h3lis331dl_int1_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { h3lis331dl_int1_ths_t int1_ths; int32_t ret; @@ -1656,7 +1660,7 @@ int32_t h3lis331dl_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t h3lis331dl_int1_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { h3lis331dl_int1_duration_t int1_duration; int32_t ret; @@ -1682,7 +1686,7 @@ int32_t h3lis331dl_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t h3lis331dl_int1_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { h3lis331dl_int1_duration_t int1_duration; int32_t ret; @@ -1702,7 +1706,7 @@ int32_t h3lis331dl_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_int2_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int2_on_threshold_conf_set(const stmdev_ctx_t *ctx, h3lis331dl_int2_on_th_conf_t val) { h3lis331dl_int2_cfg_t int2_cfg; @@ -1734,7 +1738,7 @@ int32_t h3lis331dl_int2_on_threshold_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_int2_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int2_on_threshold_conf_get(const stmdev_ctx_t *ctx, h3lis331dl_int2_on_th_conf_t *val) { h3lis331dl_int2_cfg_t int2_cfg; @@ -1760,7 +1764,7 @@ int32_t h3lis331dl_int2_on_threshold_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_int2_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int2_on_threshold_mode_set(const stmdev_ctx_t *ctx, h3lis331dl_int2_aoi_t val) { h3lis331dl_int2_cfg_t int2_cfg; @@ -1787,7 +1791,7 @@ int32_t h3lis331dl_int2_on_threshold_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_int2_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int2_on_threshold_mode_get(const stmdev_ctx_t *ctx, h3lis331dl_int2_aoi_t *val) { h3lis331dl_int2_cfg_t int2_cfg; @@ -1822,7 +1826,7 @@ int32_t h3lis331dl_int2_on_threshold_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_int2_src_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int2_src_get(const stmdev_ctx_t *ctx, h3lis331dl_int2_src_t *val) { int32_t ret; @@ -1840,7 +1844,7 @@ int32_t h3lis331dl_int2_src_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t h3lis331dl_int2_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { h3lis331dl_int2_ths_t int2_ths; int32_t ret; @@ -1866,7 +1870,7 @@ int32_t h3lis331dl_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t h3lis331dl_int2_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { h3lis331dl_int2_ths_t int2_ths; int32_t ret; @@ -1886,7 +1890,7 @@ int32_t h3lis331dl_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t h3lis331dl_int2_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { h3lis331dl_int2_duration_t int2_duration; int32_t ret; @@ -1912,7 +1916,7 @@ int32_t h3lis331dl_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t h3lis331dl_int2_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { h3lis331dl_int2_duration_t int2_duration; int32_t ret; @@ -1945,7 +1949,7 @@ int32_t h3lis331dl_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t h3lis331dl_wkup_to_sleep_set(const stmdev_ctx_t *ctx, uint8_t val) { h3lis331dl_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1971,7 +1975,7 @@ int32_t h3lis331dl_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t h3lis331dl_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t h3lis331dl_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val) { h3lis331dl_ctrl_reg5_t ctrl_reg5; int32_t ret; diff --git a/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.h b/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.h index 7de8a3b7..5b73ee60 100644 --- a/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.h +++ b/sensor/stmemsc/h3lis331dl_STdC/driver/h3lis331dl_reg.h @@ -493,10 +493,10 @@ typedef union * them with a custom implementation. */ -int32_t h3lis331dl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t h3lis331dl_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t h3lis331dl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t h3lis331dl_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -504,14 +504,14 @@ float_t h3lis331dl_from_fs100_to_mg(int16_t lsb); float_t h3lis331dl_from_fs200_to_mg(int16_t lsb); float_t h3lis331dl_from_fs400_to_mg(int16_t lsb); -int32_t h3lis331dl_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t h3lis331dl_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t h3lis331dl_axis_x_data_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t h3lis331dl_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t h3lis331dl_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t h3lis331dl_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t h3lis331dl_axis_y_data_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t h3lis331dl_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t h3lis331dl_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t h3lis331dl_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t h3lis331dl_axis_z_data_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t h3lis331dl_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -526,9 +526,9 @@ typedef enum H3LIS331DL_ODR_400Hz = 0x21, H3LIS331DL_ODR_1kHz = 0x31, } h3lis331dl_dr_t; -int32_t h3lis331dl_data_rate_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_data_rate_set(const stmdev_ctx_t *ctx, h3lis331dl_dr_t val); -int32_t h3lis331dl_data_rate_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_data_rate_get(const stmdev_ctx_t *ctx, h3lis331dl_dr_t *val); typedef enum @@ -536,9 +536,9 @@ typedef enum H3LIS331DL_NORMAL_MODE = 0, H3LIS331DL_REF_MODE_ENABLE = 1, } h3lis331dl_hpm_t; -int32_t h3lis331dl_reference_mode_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_reference_mode_set(const stmdev_ctx_t *ctx, h3lis331dl_hpm_t val); -int32_t h3lis331dl_reference_mode_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_reference_mode_get(const stmdev_ctx_t *ctx, h3lis331dl_hpm_t *val); typedef enum @@ -547,38 +547,38 @@ typedef enum H3LIS331DL_200g = 1, H3LIS331DL_400g = 3, } h3lis331dl_fs_t; -int32_t h3lis331dl_full_scale_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_full_scale_set(const stmdev_ctx_t *ctx, h3lis331dl_fs_t val); -int32_t h3lis331dl_full_scale_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_full_scale_get(const stmdev_ctx_t *ctx, h3lis331dl_fs_t *val); -int32_t h3lis331dl_block_data_update_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t h3lis331dl_block_data_update_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t h3lis331dl_status_reg_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_status_reg_get(const stmdev_ctx_t *ctx, h3lis331dl_status_reg_t *val); -int32_t h3lis331dl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t h3lis331dl_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t h3lis331dl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t h3lis331dl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t h3lis331dl_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t h3lis331dl_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t h3lis331dl_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t h3lis331dl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { H3LIS331DL_LSB_AT_LOW_ADD = 0, H3LIS331DL_MSB_AT_LOW_ADD = 1, } h3lis331dl_ble_t; -int32_t h3lis331dl_data_format_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_data_format_set(const stmdev_ctx_t *ctx, h3lis331dl_ble_t val); -int32_t h3lis331dl_data_format_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_data_format_get(const stmdev_ctx_t *ctx, h3lis331dl_ble_t *val); typedef enum @@ -588,9 +588,9 @@ typedef enum H3LIS331DL_CUT_OFF_32Hz = 2, H3LIS331DL_CUT_OFF_64Hz = 3, } h3lis331dl_hpcf_t; -int32_t h3lis331dl_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_hp_bandwidth_set(const stmdev_ctx_t *ctx, h3lis331dl_hpcf_t val); -int32_t h3lis331dl_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_hp_bandwidth_get(const stmdev_ctx_t *ctx, h3lis331dl_hpcf_t *val); typedef enum @@ -604,16 +604,16 @@ typedef enum H3LIS331DL_HP_ON_INT2_OUT = 6, H3LIS331DL_HP_ON_INT1_OUT = 5, } h3lis331dl_hpen_t; -int32_t h3lis331dl_hp_path_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_hp_path_set(const stmdev_ctx_t *ctx, h3lis331dl_hpen_t val); -int32_t h3lis331dl_hp_path_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_hp_path_get(const stmdev_ctx_t *ctx, h3lis331dl_hpen_t *val); -int32_t h3lis331dl_hp_reset_get(stmdev_ctx_t *ctx); +int32_t h3lis331dl_hp_reset_get(const stmdev_ctx_t *ctx); -int32_t h3lis331dl_hp_reference_value_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_hp_reference_value_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t h3lis331dl_hp_reference_value_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_hp_reference_value_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -621,9 +621,9 @@ typedef enum H3LIS331DL_SPI_4_WIRE = 0, H3LIS331DL_SPI_3_WIRE = 1, } h3lis331dl_sim_t; -int32_t h3lis331dl_spi_mode_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_spi_mode_set(const stmdev_ctx_t *ctx, h3lis331dl_sim_t val); -int32_t h3lis331dl_spi_mode_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_spi_mode_get(const stmdev_ctx_t *ctx, h3lis331dl_sim_t *val); typedef enum @@ -633,9 +633,9 @@ typedef enum H3LIS331DL_PAD1_DRDY = 2, H3LIS331DL_PAD1_BOOT = 3, } h3lis331dl_i1_cfg_t; -int32_t h3lis331dl_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_pin_int1_route_set(const stmdev_ctx_t *ctx, h3lis331dl_i1_cfg_t val); -int32_t h3lis331dl_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_pin_int1_route_get(const stmdev_ctx_t *ctx, h3lis331dl_i1_cfg_t *val); typedef enum @@ -643,9 +643,9 @@ typedef enum H3LIS331DL_INT1_PULSED = 0, H3LIS331DL_INT1_LATCHED = 1, } h3lis331dl_lir1_t; -int32_t h3lis331dl_int1_notification_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int1_notification_set(const stmdev_ctx_t *ctx, h3lis331dl_lir1_t val); -int32_t h3lis331dl_int1_notification_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int1_notification_get(const stmdev_ctx_t *ctx, h3lis331dl_lir1_t *val); typedef enum @@ -655,9 +655,9 @@ typedef enum H3LIS331DL_PAD2_DRDY = 2, H3LIS331DL_PAD2_BOOT = 3, } h3lis331dl_i2_cfg_t; -int32_t h3lis331dl_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_pin_int2_route_set(const stmdev_ctx_t *ctx, h3lis331dl_i2_cfg_t val); -int32_t h3lis331dl_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_pin_int2_route_get(const stmdev_ctx_t *ctx, h3lis331dl_i2_cfg_t *val); typedef enum @@ -665,9 +665,9 @@ typedef enum H3LIS331DL_INT2_PULSED = 0, H3LIS331DL_INT2_LATCHED = 1, } h3lis331dl_lir2_t; -int32_t h3lis331dl_int2_notification_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int2_notification_set(const stmdev_ctx_t *ctx, h3lis331dl_lir2_t val); -int32_t h3lis331dl_int2_notification_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int2_notification_get(const stmdev_ctx_t *ctx, h3lis331dl_lir2_t *val); typedef enum @@ -675,9 +675,9 @@ typedef enum H3LIS331DL_PUSH_PULL = 0, H3LIS331DL_OPEN_DRAIN = 1, } h3lis331dl_pp_od_t; -int32_t h3lis331dl_pin_mode_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_pin_mode_set(const stmdev_ctx_t *ctx, h3lis331dl_pp_od_t val); -int32_t h3lis331dl_pin_mode_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_pin_mode_get(const stmdev_ctx_t *ctx, h3lis331dl_pp_od_t *val); typedef enum @@ -685,9 +685,9 @@ typedef enum H3LIS331DL_ACTIVE_HIGH = 0, H3LIS331DL_ACTIVE_LOW = 1, } h3lis331dl_ihl_t; -int32_t h3lis331dl_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_pin_polarity_set(const stmdev_ctx_t *ctx, h3lis331dl_ihl_t val); -int32_t h3lis331dl_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_pin_polarity_get(const stmdev_ctx_t *ctx, h3lis331dl_ihl_t *val); typedef struct @@ -699,9 +699,9 @@ typedef struct uint8_t int1_zlie : 1; uint8_t int1_zhie : 1; } h3lis331dl_int1_on_th_conf_t; -int32_t h3lis331dl_int1_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int1_on_threshold_conf_set(const stmdev_ctx_t *ctx, h3lis331dl_int1_on_th_conf_t val); -int32_t h3lis331dl_int1_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int1_on_threshold_conf_get(const stmdev_ctx_t *ctx, h3lis331dl_int1_on_th_conf_t *val); typedef enum @@ -709,19 +709,19 @@ typedef enum H3LIS331DL_INT1_ON_THRESHOLD_OR = 0, H3LIS331DL_INT1_ON_THRESHOLD_AND = 1, } h3lis331dl_int1_aoi_t; -int32_t h3lis331dl_int1_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int1_on_threshold_mode_set(const stmdev_ctx_t *ctx, h3lis331dl_int1_aoi_t val); -int32_t h3lis331dl_int1_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int1_on_threshold_mode_get(const stmdev_ctx_t *ctx, h3lis331dl_int1_aoi_t *val); -int32_t h3lis331dl_int1_src_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int1_src_get(const stmdev_ctx_t *ctx, h3lis331dl_int1_src_t *val); -int32_t h3lis331dl_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t h3lis331dl_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t h3lis331dl_int1_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t h3lis331dl_int1_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t h3lis331dl_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t h3lis331dl_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t h3lis331dl_int1_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t h3lis331dl_int1_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -732,9 +732,9 @@ typedef struct uint8_t int2_zlie : 1; uint8_t int2_zhie : 1; } h3lis331dl_int2_on_th_conf_t; -int32_t h3lis331dl_int2_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int2_on_threshold_conf_set(const stmdev_ctx_t *ctx, h3lis331dl_int2_on_th_conf_t val); -int32_t h3lis331dl_int2_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int2_on_threshold_conf_get(const stmdev_ctx_t *ctx, h3lis331dl_int2_on_th_conf_t *val); typedef enum @@ -742,22 +742,22 @@ typedef enum H3LIS331DL_INT2_ON_THRESHOLD_OR = 0, H3LIS331DL_INT2_ON_THRESHOLD_AND = 1, } h3lis331dl_int2_aoi_t; -int32_t h3lis331dl_int2_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int2_on_threshold_mode_set(const stmdev_ctx_t *ctx, h3lis331dl_int2_aoi_t val); -int32_t h3lis331dl_int2_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int2_on_threshold_mode_get(const stmdev_ctx_t *ctx, h3lis331dl_int2_aoi_t *val); -int32_t h3lis331dl_int2_src_get(stmdev_ctx_t *ctx, +int32_t h3lis331dl_int2_src_get(const stmdev_ctx_t *ctx, h3lis331dl_int2_src_t *val); -int32_t h3lis331dl_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t h3lis331dl_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t h3lis331dl_int2_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t h3lis331dl_int2_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t h3lis331dl_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t h3lis331dl_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t h3lis331dl_int2_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t h3lis331dl_int2_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t h3lis331dl_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t h3lis331dl_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t h3lis331dl_wkup_to_sleep_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t h3lis331dl_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val); /** *@} diff --git a/sensor/stmemsc/hts221_STdC/driver/hts221_reg.c b/sensor/stmemsc/hts221_STdC/driver/hts221_reg.c index 1455299d..8f8cfead 100644 --- a/sensor/stmemsc/hts221_STdC/driver/hts221_reg.c +++ b/sensor/stmemsc/hts221_STdC/driver/hts221_reg.c @@ -45,11 +45,13 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak hts221_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, +int32_t __weak hts221_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -65,12 +67,14 @@ int32_t __weak hts221_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak hts221_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak hts221_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -96,7 +100,7 @@ int32_t __weak hts221_write_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_humidity_avg_set(stmdev_ctx_t *ctx, hts221_avgh_t val) +int32_t hts221_humidity_avg_set(const stmdev_ctx_t *ctx, hts221_avgh_t val) { hts221_av_conf_t reg; int32_t ret; @@ -120,7 +124,7 @@ int32_t hts221_humidity_avg_set(stmdev_ctx_t *ctx, hts221_avgh_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_humidity_avg_get(stmdev_ctx_t *ctx, hts221_avgh_t *val) +int32_t hts221_humidity_avg_get(const stmdev_ctx_t *ctx, hts221_avgh_t *val) { hts221_av_conf_t reg; int32_t ret; @@ -177,7 +181,7 @@ int32_t hts221_humidity_avg_get(stmdev_ctx_t *ctx, hts221_avgh_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_temperature_avg_set(stmdev_ctx_t *ctx, +int32_t hts221_temperature_avg_set(const stmdev_ctx_t *ctx, hts221_avgt_t val) { hts221_av_conf_t reg; @@ -202,7 +206,7 @@ int32_t hts221_temperature_avg_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_temperature_avg_get(stmdev_ctx_t *ctx, +int32_t hts221_temperature_avg_get(const stmdev_ctx_t *ctx, hts221_avgt_t *val) { hts221_av_conf_t reg; @@ -260,7 +264,7 @@ int32_t hts221_temperature_avg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_data_rate_set(stmdev_ctx_t *ctx, hts221_odr_t val) +int32_t hts221_data_rate_set(const stmdev_ctx_t *ctx, hts221_odr_t val) { hts221_ctrl_reg1_t reg; int32_t ret; @@ -284,7 +288,7 @@ int32_t hts221_data_rate_set(stmdev_ctx_t *ctx, hts221_odr_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_data_rate_get(stmdev_ctx_t *ctx, hts221_odr_t *val) +int32_t hts221_data_rate_get(const stmdev_ctx_t *ctx, hts221_odr_t *val) { hts221_ctrl_reg1_t reg; int32_t ret; @@ -325,7 +329,7 @@ int32_t hts221_data_rate_get(stmdev_ctx_t *ctx, hts221_odr_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t hts221_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { hts221_ctrl_reg1_t reg; int32_t ret; @@ -349,7 +353,7 @@ int32_t hts221_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t hts221_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { hts221_ctrl_reg1_t reg; int32_t ret; @@ -368,7 +372,7 @@ int32_t hts221_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t hts221_one_shoot_trigger_set(const stmdev_ctx_t *ctx, uint8_t val) { hts221_ctrl_reg2_t reg; int32_t ret; @@ -392,7 +396,7 @@ int32_t hts221_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t hts221_one_shoot_trigger_get(const stmdev_ctx_t *ctx, uint8_t *val) { hts221_ctrl_reg2_t reg; int32_t ret; @@ -411,7 +415,7 @@ int32_t hts221_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t hts221_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { hts221_status_reg_t reg; int32_t ret; @@ -430,7 +434,7 @@ int32_t hts221_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_hum_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t hts221_hum_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { hts221_status_reg_t reg; int32_t ret; @@ -449,7 +453,7 @@ int32_t hts221_hum_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_humidity_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t hts221_humidity_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -469,7 +473,7 @@ int32_t hts221_humidity_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t hts221_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -501,7 +505,7 @@ int32_t hts221_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t hts221_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -518,7 +522,7 @@ int32_t hts221_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_power_on_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t hts221_power_on_set(const stmdev_ctx_t *ctx, uint8_t val) { hts221_ctrl_reg1_t reg; int32_t ret; @@ -542,7 +546,7 @@ int32_t hts221_power_on_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_power_on_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t hts221_power_on_get(const stmdev_ctx_t *ctx, uint8_t *val) { hts221_ctrl_reg1_t reg; int32_t ret; @@ -561,7 +565,7 @@ int32_t hts221_power_on_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_heater_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t hts221_heater_set(const stmdev_ctx_t *ctx, uint8_t val) { hts221_ctrl_reg2_t reg; int32_t ret; @@ -585,7 +589,7 @@ int32_t hts221_heater_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_heater_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t hts221_heater_get(const stmdev_ctx_t *ctx, uint8_t *val) { hts221_ctrl_reg2_t reg; int32_t ret; @@ -604,7 +608,7 @@ int32_t hts221_heater_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t hts221_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { hts221_ctrl_reg2_t reg; int32_t ret; @@ -628,7 +632,7 @@ int32_t hts221_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t hts221_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { hts221_ctrl_reg2_t reg; int32_t ret; @@ -647,7 +651,7 @@ int32_t hts221_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_status_get(stmdev_ctx_t *ctx, hts221_status_reg_t *val) +int32_t hts221_status_get(const stmdev_ctx_t *ctx, hts221_status_reg_t *val) { int32_t ret; @@ -676,7 +680,7 @@ int32_t hts221_status_get(stmdev_ctx_t *ctx, hts221_status_reg_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_drdy_on_int_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t hts221_drdy_on_int_set(const stmdev_ctx_t *ctx, uint8_t val) { hts221_ctrl_reg3_t reg; int32_t ret; @@ -700,7 +704,7 @@ int32_t hts221_drdy_on_int_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t hts221_drdy_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) { hts221_ctrl_reg3_t reg; int32_t ret; @@ -718,7 +722,7 @@ int32_t hts221_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) * @param val change the values of pp_od in reg CTRL_REG3 * */ -int32_t hts221_pin_mode_set(stmdev_ctx_t *ctx, hts221_pp_od_t val) +int32_t hts221_pin_mode_set(const stmdev_ctx_t *ctx, hts221_pp_od_t val) { hts221_ctrl_reg3_t reg; int32_t ret; @@ -742,7 +746,7 @@ int32_t hts221_pin_mode_set(stmdev_ctx_t *ctx, hts221_pp_od_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_pin_mode_get(stmdev_ctx_t *ctx, hts221_pp_od_t *val) +int32_t hts221_pin_mode_get(const stmdev_ctx_t *ctx, hts221_pp_od_t *val) { hts221_ctrl_reg3_t reg; int32_t ret; @@ -775,7 +779,7 @@ int32_t hts221_pin_mode_get(stmdev_ctx_t *ctx, hts221_pp_od_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_int_polarity_set(stmdev_ctx_t *ctx, +int32_t hts221_int_polarity_set(const stmdev_ctx_t *ctx, hts221_drdy_h_l_t val) { hts221_ctrl_reg3_t reg; @@ -800,7 +804,7 @@ int32_t hts221_int_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_int_polarity_get(stmdev_ctx_t *ctx, +int32_t hts221_int_polarity_get(const stmdev_ctx_t *ctx, hts221_drdy_h_l_t *val) { hts221_ctrl_reg3_t reg; @@ -847,7 +851,7 @@ int32_t hts221_int_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_hum_rh_point_0_get(stmdev_ctx_t *ctx, float_t *val) +int32_t hts221_hum_rh_point_0_get(const stmdev_ctx_t *ctx, float_t *val) { uint8_t coeff; int32_t ret; @@ -866,7 +870,7 @@ int32_t hts221_hum_rh_point_0_get(stmdev_ctx_t *ctx, float_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_hum_rh_point_1_get(stmdev_ctx_t *ctx, float_t *val) +int32_t hts221_hum_rh_point_1_get(const stmdev_ctx_t *ctx, float_t *val) { uint8_t coeff; int32_t ret; @@ -885,7 +889,7 @@ int32_t hts221_hum_rh_point_1_get(stmdev_ctx_t *ctx, float_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_temp_deg_point_0_get(stmdev_ctx_t *ctx, float_t *val) +int32_t hts221_temp_deg_point_0_get(const stmdev_ctx_t *ctx, float_t *val) { hts221_t1_t0_msb_t reg; uint8_t coeff_h; @@ -912,7 +916,7 @@ int32_t hts221_temp_deg_point_0_get(stmdev_ctx_t *ctx, float_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_temp_deg_point_1_get(stmdev_ctx_t *ctx, float_t *val) +int32_t hts221_temp_deg_point_1_get(const stmdev_ctx_t *ctx, float_t *val) { hts221_t1_t0_msb_t reg; uint8_t coeff_h; @@ -939,7 +943,7 @@ int32_t hts221_temp_deg_point_1_get(stmdev_ctx_t *ctx, float_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_hum_adc_point_0_get(stmdev_ctx_t *ctx, float_t *val) +int32_t hts221_hum_adc_point_0_get(const stmdev_ctx_t *ctx, float_t *val) { uint8_t coeff_p[2]; int16_t coeff; @@ -960,7 +964,7 @@ int32_t hts221_hum_adc_point_0_get(stmdev_ctx_t *ctx, float_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_hum_adc_point_1_get(stmdev_ctx_t *ctx, float_t *val) +int32_t hts221_hum_adc_point_1_get(const stmdev_ctx_t *ctx, float_t *val) { uint8_t coeff_p[2]; int16_t coeff; @@ -981,7 +985,7 @@ int32_t hts221_hum_adc_point_1_get(stmdev_ctx_t *ctx, float_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_temp_adc_point_0_get(stmdev_ctx_t *ctx, float_t *val) +int32_t hts221_temp_adc_point_0_get(const stmdev_ctx_t *ctx, float_t *val) { uint8_t coeff_p[2]; int16_t coeff; @@ -1002,7 +1006,7 @@ int32_t hts221_temp_adc_point_0_get(stmdev_ctx_t *ctx, float_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t hts221_temp_adc_point_1_get(stmdev_ctx_t *ctx, float_t *val) +int32_t hts221_temp_adc_point_1_get(const stmdev_ctx_t *ctx, float_t *val) { uint8_t coeff_p[2]; int16_t coeff; diff --git a/sensor/stmemsc/hts221_STdC/driver/hts221_reg.h b/sensor/stmemsc/hts221_STdC/driver/hts221_reg.h index f25b69de..184872ab 100644 --- a/sensor/stmemsc/hts221_STdC/driver/hts221_reg.h +++ b/sensor/stmemsc/hts221_STdC/driver/hts221_reg.h @@ -330,10 +330,10 @@ typedef union * The __weak directive allows the final application to overwrite * them with a custom implementation. */ -int32_t hts221_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t hts221_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t hts221_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t hts221_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -349,8 +349,8 @@ typedef enum HTS221_H_AVG_512 = 7, HTS221_H_AVG_ND = 8, } hts221_avgh_t; -int32_t hts221_humidity_avg_set(stmdev_ctx_t *ctx, hts221_avgh_t val); -int32_t hts221_humidity_avg_get(stmdev_ctx_t *ctx, +int32_t hts221_humidity_avg_set(const stmdev_ctx_t *ctx, hts221_avgh_t val); +int32_t hts221_humidity_avg_get(const stmdev_ctx_t *ctx, hts221_avgh_t *val); typedef enum @@ -365,9 +365,9 @@ typedef enum HTS221_T_AVG_256 = 7, HTS221_T_AVG_ND = 8, } hts221_avgt_t; -int32_t hts221_temperature_avg_set(stmdev_ctx_t *ctx, +int32_t hts221_temperature_avg_set(const stmdev_ctx_t *ctx, hts221_avgt_t val); -int32_t hts221_temperature_avg_get(stmdev_ctx_t *ctx, +int32_t hts221_temperature_avg_get(const stmdev_ctx_t *ctx, hts221_avgt_t *val); typedef enum @@ -378,40 +378,40 @@ typedef enum HTS221_ODR_12Hz5 = 3, HTS221_ODR_ND = 4, } hts221_odr_t; -int32_t hts221_data_rate_set(stmdev_ctx_t *ctx, hts221_odr_t val); -int32_t hts221_data_rate_get(stmdev_ctx_t *ctx, hts221_odr_t *val); +int32_t hts221_data_rate_set(const stmdev_ctx_t *ctx, hts221_odr_t val); +int32_t hts221_data_rate_get(const stmdev_ctx_t *ctx, hts221_odr_t *val); -int32_t hts221_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t hts221_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t hts221_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t hts221_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t hts221_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t hts221_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t hts221_one_shoot_trigger_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t hts221_one_shoot_trigger_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t hts221_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t hts221_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t hts221_hum_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t hts221_hum_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t hts221_humidity_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t hts221_humidity_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t hts221_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t hts221_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t hts221_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t hts221_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t hts221_power_on_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t hts221_power_on_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t hts221_power_on_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t hts221_power_on_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t hts221_heater_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t hts221_heater_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t hts221_heater_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t hts221_heater_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t hts221_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t hts221_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t hts221_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t hts221_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t hts221_status_get(stmdev_ctx_t *ctx, +int32_t hts221_status_get(const stmdev_ctx_t *ctx, hts221_status_reg_t *val); -int32_t hts221_drdy_on_int_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t hts221_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t hts221_drdy_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t hts221_drdy_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -419,8 +419,8 @@ typedef enum HTS221_OPEN_DRAIN = 1, HTS221_PIN_MODE_ND = 2, } hts221_pp_od_t; -int32_t hts221_pin_mode_set(stmdev_ctx_t *ctx, hts221_pp_od_t val); -int32_t hts221_pin_mode_get(stmdev_ctx_t *ctx, hts221_pp_od_t *val); +int32_t hts221_pin_mode_set(const stmdev_ctx_t *ctx, hts221_pp_od_t val); +int32_t hts221_pin_mode_get(const stmdev_ctx_t *ctx, hts221_pp_od_t *val); typedef enum { @@ -428,22 +428,22 @@ typedef enum HTS221_ACTIVE_LOW = 1, HTS221_ACTIVE_ND = 2, } hts221_drdy_h_l_t; -int32_t hts221_int_polarity_set(stmdev_ctx_t *ctx, +int32_t hts221_int_polarity_set(const stmdev_ctx_t *ctx, hts221_drdy_h_l_t val); -int32_t hts221_int_polarity_get(stmdev_ctx_t *ctx, +int32_t hts221_int_polarity_get(const stmdev_ctx_t *ctx, hts221_drdy_h_l_t *val); -int32_t hts221_hum_rh_point_0_get(stmdev_ctx_t *ctx, float_t *val); -int32_t hts221_hum_rh_point_1_get(stmdev_ctx_t *ctx, float_t *val); +int32_t hts221_hum_rh_point_0_get(const stmdev_ctx_t *ctx, float_t *val); +int32_t hts221_hum_rh_point_1_get(const stmdev_ctx_t *ctx, float_t *val); -int32_t hts221_temp_deg_point_0_get(stmdev_ctx_t *ctx, float_t *val); -int32_t hts221_temp_deg_point_1_get(stmdev_ctx_t *ctx, float_t *val); +int32_t hts221_temp_deg_point_0_get(const stmdev_ctx_t *ctx, float_t *val); +int32_t hts221_temp_deg_point_1_get(const stmdev_ctx_t *ctx, float_t *val); -int32_t hts221_hum_adc_point_0_get(stmdev_ctx_t *ctx, float_t *val); -int32_t hts221_hum_adc_point_1_get(stmdev_ctx_t *ctx, float_t *val); +int32_t hts221_hum_adc_point_0_get(const stmdev_ctx_t *ctx, float_t *val); +int32_t hts221_hum_adc_point_1_get(const stmdev_ctx_t *ctx, float_t *val); -int32_t hts221_temp_adc_point_0_get(stmdev_ctx_t *ctx, float_t *val); -int32_t hts221_temp_adc_point_1_get(stmdev_ctx_t *ctx, float_t *val); +int32_t hts221_temp_adc_point_0_get(const stmdev_ctx_t *ctx, float_t *val); +int32_t hts221_temp_adc_point_1_get(const stmdev_ctx_t *ctx, float_t *val); /** * @} diff --git a/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.c b/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.c index c33a2285..1d8903a9 100644 --- a/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.c +++ b/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.c @@ -46,12 +46,14 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak i3g4250d_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak i3g4250d_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +69,14 @@ int32_t __weak i3g4250d_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak i3g4250d_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak i3g4250d_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -121,7 +125,7 @@ float_t i3g4250d_from_lsb_to_celsius(int16_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_data_rate_set(stmdev_ctx_t *ctx, i3g4250d_dr_t val) +int32_t i3g4250d_data_rate_set(const stmdev_ctx_t *ctx, i3g4250d_dr_t val) { i3g4250d_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -148,7 +152,7 @@ int32_t i3g4250d_data_rate_set(stmdev_ctx_t *ctx, i3g4250d_dr_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_data_rate_get(stmdev_ctx_t *ctx, i3g4250d_dr_t *val) +int32_t i3g4250d_data_rate_get(const stmdev_ctx_t *ctx, i3g4250d_dr_t *val) { i3g4250d_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -198,7 +202,7 @@ int32_t i3g4250d_data_rate_get(stmdev_ctx_t *ctx, i3g4250d_dr_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_full_scale_set(stmdev_ctx_t *ctx, i3g4250d_fs_t val) +int32_t i3g4250d_full_scale_set(const stmdev_ctx_t *ctx, i3g4250d_fs_t val) { i3g4250d_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -224,7 +228,7 @@ int32_t i3g4250d_full_scale_set(stmdev_ctx_t *ctx, i3g4250d_fs_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_full_scale_get(stmdev_ctx_t *ctx, i3g4250d_fs_t *val) +int32_t i3g4250d_full_scale_get(const stmdev_ctx_t *ctx, i3g4250d_fs_t *val) { i3g4250d_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -262,7 +266,7 @@ int32_t i3g4250d_full_scale_get(stmdev_ctx_t *ctx, i3g4250d_fs_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_status_reg_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_status_reg_get(const stmdev_ctx_t *ctx, i3g4250d_status_reg_t *val) { int32_t ret; @@ -280,7 +284,7 @@ int32_t i3g4250d_status_reg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t i3g4250d_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { i3g4250d_status_reg_t status_reg; int32_t ret; @@ -311,7 +315,7 @@ int32_t i3g4250d_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t i3g4250d_temperature_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -329,7 +333,7 @@ int32_t i3g4250d_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t i3g4250d_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -365,7 +369,7 @@ int32_t i3g4250d_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t i3g4250d_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -382,7 +386,7 @@ int32_t i3g4250d_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_self_test_set(stmdev_ctx_t *ctx, i3g4250d_st_t val) +int32_t i3g4250d_self_test_set(const stmdev_ctx_t *ctx, i3g4250d_st_t val) { i3g4250d_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -408,7 +412,7 @@ int32_t i3g4250d_self_test_set(stmdev_ctx_t *ctx, i3g4250d_st_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_self_test_get(stmdev_ctx_t *ctx, i3g4250d_st_t *val) +int32_t i3g4250d_self_test_get(const stmdev_ctx_t *ctx, i3g4250d_st_t *val) { i3g4250d_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -446,7 +450,7 @@ int32_t i3g4250d_self_test_get(stmdev_ctx_t *ctx, i3g4250d_st_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_data_format_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_data_format_set(const stmdev_ctx_t *ctx, i3g4250d_ble_t val) { i3g4250d_ctrl_reg4_t ctrl_reg4; @@ -473,7 +477,7 @@ int32_t i3g4250d_data_format_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_data_format_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_data_format_get(const stmdev_ctx_t *ctx, i3g4250d_ble_t *val) { i3g4250d_ctrl_reg4_t ctrl_reg4; @@ -508,7 +512,7 @@ int32_t i3g4250d_data_format_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t i3g4250d_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { i3g4250d_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -534,7 +538,7 @@ int32_t i3g4250d_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t i3g4250d_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { i3g4250d_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -567,7 +571,7 @@ int32_t i3g4250d_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_lp_bandwidth_set(const stmdev_ctx_t *ctx, i3g4250d_bw_t val) { i3g4250d_ctrl_reg1_t ctrl_reg1; @@ -594,7 +598,7 @@ int32_t i3g4250d_lp_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_lp_bandwidth_get(const stmdev_ctx_t *ctx, i3g4250d_bw_t *val) { i3g4250d_ctrl_reg1_t ctrl_reg1; @@ -637,7 +641,7 @@ int32_t i3g4250d_lp_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_hp_bandwidth_set(const stmdev_ctx_t *ctx, i3g4250d_hpcf_t val) { i3g4250d_ctrl_reg2_t ctrl_reg2; @@ -664,7 +668,7 @@ int32_t i3g4250d_hp_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_hp_bandwidth_get(const stmdev_ctx_t *ctx, i3g4250d_hpcf_t *val) { i3g4250d_ctrl_reg2_t ctrl_reg2; @@ -731,7 +735,7 @@ int32_t i3g4250d_hp_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_hp_mode_set(stmdev_ctx_t *ctx, i3g4250d_hpm_t val) +int32_t i3g4250d_hp_mode_set(const stmdev_ctx_t *ctx, i3g4250d_hpm_t val) { i3g4250d_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -757,7 +761,7 @@ int32_t i3g4250d_hp_mode_set(stmdev_ctx_t *ctx, i3g4250d_hpm_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_hp_mode_get(stmdev_ctx_t *ctx, i3g4250d_hpm_t *val) +int32_t i3g4250d_hp_mode_get(const stmdev_ctx_t *ctx, i3g4250d_hpm_t *val) { i3g4250d_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -799,7 +803,7 @@ int32_t i3g4250d_hp_mode_get(stmdev_ctx_t *ctx, i3g4250d_hpm_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_filter_path_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_filter_path_set(const stmdev_ctx_t *ctx, i3g4250d_out_sel_t val) { i3g4250d_ctrl_reg5_t ctrl_reg5; @@ -827,7 +831,7 @@ int32_t i3g4250d_filter_path_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_filter_path_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_filter_path_get(const stmdev_ctx_t *ctx, i3g4250d_out_sel_t *val) { i3g4250d_ctrl_reg5_t ctrl_reg5; @@ -870,7 +874,7 @@ int32_t i3g4250d_filter_path_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_filter_path_internal_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_filter_path_internal_set(const stmdev_ctx_t *ctx, i3g4250d_int1_sel_t val) { i3g4250d_ctrl_reg5_t ctrl_reg5; @@ -898,7 +902,7 @@ int32_t i3g4250d_filter_path_internal_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_filter_path_internal_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_filter_path_internal_get(const stmdev_ctx_t *ctx, i3g4250d_int1_sel_t *val) { i3g4250d_ctrl_reg5_t ctrl_reg5; @@ -941,7 +945,7 @@ int32_t i3g4250d_filter_path_internal_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_hp_reference_value_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_hp_reference_value_set(const stmdev_ctx_t *ctx, uint8_t val) { i3g4250d_reference_t reference; @@ -968,7 +972,7 @@ int32_t i3g4250d_hp_reference_value_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_hp_reference_value_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_hp_reference_value_get(const stmdev_ctx_t *ctx, uint8_t *val) { i3g4250d_reference_t reference; @@ -1002,7 +1006,7 @@ int32_t i3g4250d_hp_reference_value_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_spi_mode_set(stmdev_ctx_t *ctx, i3g4250d_sim_t val) +int32_t i3g4250d_spi_mode_set(const stmdev_ctx_t *ctx, i3g4250d_sim_t val) { i3g4250d_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -1028,7 +1032,7 @@ int32_t i3g4250d_spi_mode_set(stmdev_ctx_t *ctx, i3g4250d_sim_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_spi_mode_get(stmdev_ctx_t *ctx, i3g4250d_sim_t *val) +int32_t i3g4250d_spi_mode_get(const stmdev_ctx_t *ctx, i3g4250d_sim_t *val) { i3g4250d_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -1075,7 +1079,7 @@ int32_t i3g4250d_spi_mode_get(stmdev_ctx_t *ctx, i3g4250d_sim_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_pin_int1_route_set(const stmdev_ctx_t *ctx, i3g4250d_int1_route_t val) { i3g4250d_ctrl_reg3_t ctrl_reg3; @@ -1104,7 +1108,7 @@ int32_t i3g4250d_pin_int1_route_set(stmdev_ctx_t *ctx, * */ -int32_t i3g4250d_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_pin_int1_route_get(const stmdev_ctx_t *ctx, i3g4250d_int1_route_t *val) { i3g4250d_ctrl_reg3_t ctrl_reg3; @@ -1125,7 +1129,7 @@ int32_t i3g4250d_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_pin_int2_route_set(const stmdev_ctx_t *ctx, i3g4250d_int2_route_t val) { i3g4250d_ctrl_reg3_t ctrl_reg3; @@ -1155,7 +1159,7 @@ int32_t i3g4250d_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_pin_int2_route_get(const stmdev_ctx_t *ctx, i3g4250d_int2_route_t *val) { i3g4250d_ctrl_reg3_t ctrl_reg3; @@ -1179,7 +1183,7 @@ int32_t i3g4250d_pin_int2_route_get(stmdev_ctx_t *ctx, * */ -int32_t i3g4250d_pin_mode_set(stmdev_ctx_t *ctx, i3g4250d_pp_od_t val) +int32_t i3g4250d_pin_mode_set(const stmdev_ctx_t *ctx, i3g4250d_pp_od_t val) { i3g4250d_ctrl_reg3_t ctrl_reg3; int32_t ret; @@ -1205,7 +1209,7 @@ int32_t i3g4250d_pin_mode_set(stmdev_ctx_t *ctx, i3g4250d_pp_od_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_pin_mode_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_pin_mode_get(const stmdev_ctx_t *ctx, i3g4250d_pp_od_t *val) { i3g4250d_ctrl_reg3_t ctrl_reg3; @@ -1240,7 +1244,7 @@ int32_t i3g4250d_pin_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_pin_polarity_set(const stmdev_ctx_t *ctx, i3g4250d_h_lactive_t val) { i3g4250d_ctrl_reg3_t ctrl_reg3; @@ -1267,7 +1271,7 @@ int32_t i3g4250d_pin_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_pin_polarity_get(const stmdev_ctx_t *ctx, i3g4250d_h_lactive_t *val) { i3g4250d_ctrl_reg3_t ctrl_reg3; @@ -1302,7 +1306,7 @@ int32_t i3g4250d_pin_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_int_notification_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_int_notification_set(const stmdev_ctx_t *ctx, i3g4250d_lir_t val) { i3g4250d_int1_cfg_t int1_cfg; @@ -1327,7 +1331,7 @@ int32_t i3g4250d_int_notification_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_int_notification_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_int_notification_get(const stmdev_ctx_t *ctx, i3g4250d_lir_t *val) { i3g4250d_int1_cfg_t int1_cfg; @@ -1374,7 +1378,7 @@ int32_t i3g4250d_int_notification_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_int_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_int_on_threshold_conf_set(const stmdev_ctx_t *ctx, i3g4250d_int1_cfg_t *val) { int32_t ret; @@ -1392,7 +1396,7 @@ int32_t i3g4250d_int_on_threshold_conf_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_int_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_int_on_threshold_conf_get(const stmdev_ctx_t *ctx, i3g4250d_int1_cfg_t *val) { int32_t ret; @@ -1409,7 +1413,7 @@ int32_t i3g4250d_int_on_threshold_conf_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_int_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_int_on_threshold_mode_set(const stmdev_ctx_t *ctx, i3g4250d_and_or_t val) { i3g4250d_int1_cfg_t int1_cfg; @@ -1434,7 +1438,7 @@ int32_t i3g4250d_int_on_threshold_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_int_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_int_on_threshold_mode_get(const stmdev_ctx_t *ctx, i3g4250d_and_or_t *val) { i3g4250d_int1_cfg_t int1_cfg; @@ -1468,7 +1472,7 @@ int32_t i3g4250d_int_on_threshold_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_int_on_threshold_src_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_int_on_threshold_src_get(const stmdev_ctx_t *ctx, i3g4250d_int1_src_t *val) { int32_t ret; @@ -1486,7 +1490,7 @@ int32_t i3g4250d_int_on_threshold_src_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_int_x_treshold_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t i3g4250d_int_x_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { i3g4250d_int1_tsh_xh_t int1_tsh_xh; i3g4250d_int1_tsh_xl_t int1_tsh_xl; @@ -1526,7 +1530,7 @@ int32_t i3g4250d_int_x_treshold_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_int_x_treshold_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t i3g4250d_int_x_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { i3g4250d_int1_tsh_xh_t int1_tsh_xh; i3g4250d_int1_tsh_xl_t int1_tsh_xl; @@ -1555,7 +1559,7 @@ int32_t i3g4250d_int_x_treshold_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_int_y_treshold_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t i3g4250d_int_y_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { i3g4250d_int1_tsh_yh_t int1_tsh_yh; i3g4250d_int1_tsh_yl_t int1_tsh_yl; @@ -1595,7 +1599,7 @@ int32_t i3g4250d_int_y_treshold_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_int_y_treshold_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t i3g4250d_int_y_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { i3g4250d_int1_tsh_yh_t int1_tsh_yh; i3g4250d_int1_tsh_yl_t int1_tsh_yl; @@ -1624,7 +1628,7 @@ int32_t i3g4250d_int_y_treshold_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_int_z_treshold_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t i3g4250d_int_z_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { i3g4250d_int1_tsh_zh_t int1_tsh_zh; i3g4250d_int1_tsh_zl_t int1_tsh_zl; @@ -1664,7 +1668,7 @@ int32_t i3g4250d_int_z_treshold_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_int_z_treshold_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t i3g4250d_int_z_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { i3g4250d_int1_tsh_zh_t int1_tsh_zh; i3g4250d_int1_tsh_zl_t int1_tsh_zl; @@ -1693,7 +1697,7 @@ int32_t i3g4250d_int_z_treshold_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_int_on_threshold_dur_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_int_on_threshold_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { i3g4250d_int1_duration_t int1_duration; @@ -1731,7 +1735,7 @@ int32_t i3g4250d_int_on_threshold_dur_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_int_on_threshold_dur_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_int_on_threshold_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { i3g4250d_int1_duration_t int1_duration; @@ -1764,7 +1768,7 @@ int32_t i3g4250d_int_on_threshold_dur_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_fifo_enable_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t i3g4250d_fifo_enable_set(const stmdev_ctx_t *ctx, uint8_t val) { i3g4250d_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1790,7 +1794,7 @@ int32_t i3g4250d_fifo_enable_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_fifo_enable_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t i3g4250d_fifo_enable_get(const stmdev_ctx_t *ctx, uint8_t *val) { i3g4250d_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1810,7 +1814,7 @@ int32_t i3g4250d_fifo_enable_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t i3g4250d_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { i3g4250d_fifo_ctrl_reg_t fifo_ctrl_reg; int32_t ret; @@ -1836,7 +1840,7 @@ int32_t i3g4250d_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t i3g4250d_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { i3g4250d_fifo_ctrl_reg_t fifo_ctrl_reg; int32_t ret; @@ -1856,7 +1860,7 @@ int32_t i3g4250d_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_fifo_mode_set(const stmdev_ctx_t *ctx, i3g4250d_fifo_mode_t val) { i3g4250d_fifo_ctrl_reg_t fifo_ctrl_reg; @@ -1883,7 +1887,7 @@ int32_t i3g4250d_fifo_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_fifo_mode_get(const stmdev_ctx_t *ctx, i3g4250d_fifo_mode_t *val) { i3g4250d_fifo_ctrl_reg_t fifo_ctrl_reg; @@ -1922,7 +1926,7 @@ int32_t i3g4250d_fifo_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t i3g4250d_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) { i3g4250d_fifo_src_reg_t fifo_src_reg; int32_t ret; @@ -1942,7 +1946,7 @@ int32_t i3g4250d_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t i3g4250d_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { i3g4250d_fifo_src_reg_t fifo_src_reg; int32_t ret; @@ -1962,7 +1966,7 @@ int32_t i3g4250d_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t i3g4250d_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t i3g4250d_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { i3g4250d_fifo_src_reg_t fifo_src_reg; int32_t ret; @@ -1985,7 +1989,7 @@ int32_t i3g4250d_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * */ -int32_t i3g4250d_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t i3g4250d_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { i3g4250d_fifo_src_reg_t fifo_src_reg; int32_t ret; diff --git a/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.h b/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.h index 2779c236..de131379 100644 --- a/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.h +++ b/sensor/stmemsc/i3g4250d_STdC/driver/i3g4250d_reg.h @@ -506,24 +506,24 @@ typedef union * them with a custom implementation. */ -int32_t i3g4250d_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t i3g4250d_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t i3g4250d_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t i3g4250d_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); float_t i3g4250d_from_fs245dps_to_mdps(int16_t lsb); float_t i3g4250d_from_lsb_to_celsius(int16_t lsb); -int32_t i3g4250d_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t i3g4250d_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t i3g4250d_axis_x_data_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t i3g4250d_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t i3g4250d_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t i3g4250d_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t i3g4250d_axis_y_data_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t i3g4250d_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t i3g4250d_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t i3g4250d_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t i3g4250d_axis_z_data_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t i3g4250d_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -534,8 +534,8 @@ typedef enum I3G4250D_ODR_400Hz = 0x2F, I3G4250D_ODR_800Hz = 0x3F, } i3g4250d_dr_t; -int32_t i3g4250d_data_rate_set(stmdev_ctx_t *ctx, i3g4250d_dr_t val); -int32_t i3g4250d_data_rate_get(stmdev_ctx_t *ctx, i3g4250d_dr_t *val); +int32_t i3g4250d_data_rate_set(const stmdev_ctx_t *ctx, i3g4250d_dr_t val); +int32_t i3g4250d_data_rate_get(const stmdev_ctx_t *ctx, i3g4250d_dr_t *val); typedef enum { @@ -543,22 +543,22 @@ typedef enum I3G4250D_500dps = 0x01, I3G4250D_2000dps = 0x02, } i3g4250d_fs_t; -int32_t i3g4250d_full_scale_set(stmdev_ctx_t *ctx, i3g4250d_fs_t val); -int32_t i3g4250d_full_scale_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_full_scale_set(const stmdev_ctx_t *ctx, i3g4250d_fs_t val); +int32_t i3g4250d_full_scale_get(const stmdev_ctx_t *ctx, i3g4250d_fs_t *val); -int32_t i3g4250d_status_reg_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_status_reg_get(const stmdev_ctx_t *ctx, i3g4250d_status_reg_t *val); -int32_t i3g4250d_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t i3g4250d_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t i3g4250d_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_temperature_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t i3g4250d_angular_rate_raw_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t i3g4250d_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t i3g4250d_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); typedef enum { @@ -566,21 +566,21 @@ typedef enum I3G4250D_GY_ST_POSITIVE = 1, I3G4250D_GY_ST_NEGATIVE = 3, } i3g4250d_st_t; -int32_t i3g4250d_self_test_set(stmdev_ctx_t *ctx, i3g4250d_st_t val); -int32_t i3g4250d_self_test_get(stmdev_ctx_t *ctx, i3g4250d_st_t *val); +int32_t i3g4250d_self_test_set(const stmdev_ctx_t *ctx, i3g4250d_st_t val); +int32_t i3g4250d_self_test_get(const stmdev_ctx_t *ctx, i3g4250d_st_t *val); typedef enum { I3G4250D_AUX_LSB_AT_LOW_ADD = 0, I3G4250D_AUX_MSB_AT_LOW_ADD = 1, } i3g4250d_ble_t; -int32_t i3g4250d_data_format_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_data_format_set(const stmdev_ctx_t *ctx, i3g4250d_ble_t val); -int32_t i3g4250d_data_format_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_data_format_get(const stmdev_ctx_t *ctx, i3g4250d_ble_t *val); -int32_t i3g4250d_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t i3g4250d_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t i3g4250d_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t i3g4250d_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -589,9 +589,9 @@ typedef enum I3G4250D_CUT_OFF_HIGH = 2, I3G4250D_CUT_OFF_VERY_HIGH = 3, } i3g4250d_bw_t; -int32_t i3g4250d_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_lp_bandwidth_set(const stmdev_ctx_t *ctx, i3g4250d_bw_t val); -int32_t i3g4250d_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_lp_bandwidth_get(const stmdev_ctx_t *ctx, i3g4250d_bw_t *val); typedef enum @@ -607,9 +607,9 @@ typedef enum I3G4250D_HP_LEVEL_8 = 8, I3G4250D_HP_LEVEL_9 = 9, } i3g4250d_hpcf_t; -int32_t i3g4250d_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_hp_bandwidth_set(const stmdev_ctx_t *ctx, i3g4250d_hpcf_t val); -int32_t i3g4250d_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_hp_bandwidth_get(const stmdev_ctx_t *ctx, i3g4250d_hpcf_t *val); typedef enum @@ -619,8 +619,8 @@ typedef enum I3G4250D_HP_NORMAL_MODE = 2, I3G4250D_HP_AUTO_RESET_ON_INT = 3, } i3g4250d_hpm_t; -int32_t i3g4250d_hp_mode_set(stmdev_ctx_t *ctx, i3g4250d_hpm_t val); -int32_t i3g4250d_hp_mode_get(stmdev_ctx_t *ctx, i3g4250d_hpm_t *val); +int32_t i3g4250d_hp_mode_set(const stmdev_ctx_t *ctx, i3g4250d_hpm_t val); +int32_t i3g4250d_hp_mode_get(const stmdev_ctx_t *ctx, i3g4250d_hpm_t *val); typedef enum { @@ -629,9 +629,9 @@ typedef enum I3G4250D_LPF1_LPF2_ON_OUT = 2, I3G4250D_LPF1_HP_LPF2_ON_OUT = 6, } i3g4250d_out_sel_t; -int32_t i3g4250d_filter_path_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_filter_path_set(const stmdev_ctx_t *ctx, i3g4250d_out_sel_t val); -int32_t i3g4250d_filter_path_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_filter_path_get(const stmdev_ctx_t *ctx, i3g4250d_out_sel_t *val); typedef enum @@ -641,14 +641,14 @@ typedef enum I3G4250D_LPF1_LPF2_ON_INT = 2, I3G4250D_LPF1_HP_LPF2_ON_INT = 6, } i3g4250d_int1_sel_t; -int32_t i3g4250d_filter_path_internal_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_filter_path_internal_set(const stmdev_ctx_t *ctx, i3g4250d_int1_sel_t val); -int32_t i3g4250d_filter_path_internal_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_filter_path_internal_get(const stmdev_ctx_t *ctx, i3g4250d_int1_sel_t *val); -int32_t i3g4250d_hp_reference_value_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_hp_reference_value_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t i3g4250d_hp_reference_value_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_hp_reference_value_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -656,17 +656,17 @@ typedef enum I3G4250D_SPI_4_WIRE = 0, I3G4250D_SPI_3_WIRE = 1, } i3g4250d_sim_t; -int32_t i3g4250d_spi_mode_set(stmdev_ctx_t *ctx, i3g4250d_sim_t val); -int32_t i3g4250d_spi_mode_get(stmdev_ctx_t *ctx, i3g4250d_sim_t *val); +int32_t i3g4250d_spi_mode_set(const stmdev_ctx_t *ctx, i3g4250d_sim_t val); +int32_t i3g4250d_spi_mode_get(const stmdev_ctx_t *ctx, i3g4250d_sim_t *val); typedef struct { uint8_t i1_int1 : 1; uint8_t i1_boot : 1; } i3g4250d_int1_route_t; -int32_t i3g4250d_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_pin_int1_route_set(const stmdev_ctx_t *ctx, i3g4250d_int1_route_t val); -int32_t i3g4250d_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_pin_int1_route_get(const stmdev_ctx_t *ctx, i3g4250d_int1_route_t *val); typedef struct @@ -676,9 +676,9 @@ typedef struct uint8_t i2_wtm : 1; uint8_t i2_drdy : 1; } i3g4250d_int2_route_t; -int32_t i3g4250d_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_pin_int2_route_set(const stmdev_ctx_t *ctx, i3g4250d_int2_route_t val); -int32_t i3g4250d_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_pin_int2_route_get(const stmdev_ctx_t *ctx, i3g4250d_int2_route_t *val); typedef enum @@ -686,9 +686,9 @@ typedef enum I3G4250D_PUSH_PULL = 0, I3G4250D_OPEN_DRAIN = 1, } i3g4250d_pp_od_t; -int32_t i3g4250d_pin_mode_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_pin_mode_set(const stmdev_ctx_t *ctx, i3g4250d_pp_od_t val); -int32_t i3g4250d_pin_mode_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_pin_mode_get(const stmdev_ctx_t *ctx, i3g4250d_pp_od_t *val); typedef enum @@ -696,9 +696,9 @@ typedef enum I3G4250D_ACTIVE_HIGH = 0, I3G4250D_ACTIVE_LOW = 1, } i3g4250d_h_lactive_t; -int32_t i3g4250d_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_pin_polarity_set(const stmdev_ctx_t *ctx, i3g4250d_h_lactive_t val); -int32_t i3g4250d_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_pin_polarity_get(const stmdev_ctx_t *ctx, i3g4250d_h_lactive_t *val); typedef enum @@ -706,14 +706,14 @@ typedef enum I3G4250D_INT_PULSED = 0, I3G4250D_INT_LATCHED = 1, } i3g4250d_lir_t; -int32_t i3g4250d_int_notification_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_int_notification_set(const stmdev_ctx_t *ctx, i3g4250d_lir_t val); -int32_t i3g4250d_int_notification_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_int_notification_get(const stmdev_ctx_t *ctx, i3g4250d_lir_t *val); -int32_t i3g4250d_int_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_int_on_threshold_conf_set(const stmdev_ctx_t *ctx, i3g4250d_int1_cfg_t *val); -int32_t i3g4250d_int_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_int_on_threshold_conf_get(const stmdev_ctx_t *ctx, i3g4250d_int1_cfg_t *val); typedef enum @@ -721,33 +721,33 @@ typedef enum I3G4250D_INT1_ON_TH_AND = 1, I3G4250D_INT1_ON_TH_OR = 0, } i3g4250d_and_or_t; -int32_t i3g4250d_int_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_int_on_threshold_mode_set(const stmdev_ctx_t *ctx, i3g4250d_and_or_t val); -int32_t i3g4250d_int_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_int_on_threshold_mode_get(const stmdev_ctx_t *ctx, i3g4250d_and_or_t *val); -int32_t i3g4250d_int_on_threshold_src_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_int_on_threshold_src_get(const stmdev_ctx_t *ctx, i3g4250d_int1_src_t *val); -int32_t i3g4250d_int_x_treshold_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t i3g4250d_int_x_treshold_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t i3g4250d_int_x_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t i3g4250d_int_x_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t i3g4250d_int_y_treshold_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t i3g4250d_int_y_treshold_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t i3g4250d_int_y_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t i3g4250d_int_y_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t i3g4250d_int_z_treshold_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t i3g4250d_int_z_treshold_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t i3g4250d_int_z_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t i3g4250d_int_z_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t i3g4250d_int_on_threshold_dur_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_int_on_threshold_dur_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t i3g4250d_int_on_threshold_dur_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_int_on_threshold_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t i3g4250d_fifo_enable_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t i3g4250d_fifo_enable_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t i3g4250d_fifo_enable_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t i3g4250d_fifo_enable_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t i3g4250d_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t i3g4250d_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t i3g4250d_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t i3g4250d_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -755,18 +755,18 @@ typedef enum I3G4250D_FIFO_MODE = 0x01, I3G4250D_FIFO_STREAM_MODE = 0x02, } i3g4250d_fifo_mode_t; -int32_t i3g4250d_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t i3g4250d_fifo_mode_set(const stmdev_ctx_t *ctx, i3g4250d_fifo_mode_t val); -int32_t i3g4250d_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t i3g4250d_fifo_mode_get(const stmdev_ctx_t *ctx, i3g4250d_fifo_mode_t *val); -int32_t i3g4250d_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t i3g4250d_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t i3g4250d_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t i3g4250d_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t i3g4250d_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t i3g4250d_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t i3g4250d_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t i3g4250d_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); /** * @} diff --git a/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.c b/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.c index 3c6baa9f..a7519d7d 100644 --- a/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.c +++ b/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.c @@ -46,11 +46,13 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak iis2dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, +int32_t __weak iis2dh_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -66,12 +68,14 @@ int32_t __weak iis2dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak iis2dh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak iis2dh_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -184,7 +188,7 @@ float_t iis2dh_from_lsb_lp_to_celsius(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis2dh_temp_status_reg_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -200,7 +204,7 @@ int32_t iis2dh_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dh_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dh_status_reg_aux_t status_reg_aux; int32_t ret; @@ -219,7 +223,7 @@ int32_t iis2dh_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dh_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dh_status_reg_aux_t status_reg_aux; int32_t ret; @@ -238,7 +242,7 @@ int32_t iis2dh_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t iis2dh_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -257,7 +261,7 @@ int32_t iis2dh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_temperature_meas_set(stmdev_ctx_t *ctx, +int32_t iis2dh_temperature_meas_set(const stmdev_ctx_t *ctx, iis2dh_temp_en_t val) { iis2dh_temp_cfg_reg_t temp_cfg_reg; @@ -284,7 +288,7 @@ int32_t iis2dh_temperature_meas_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_temperature_meas_get(stmdev_ctx_t *ctx, +int32_t iis2dh_temperature_meas_get(const stmdev_ctx_t *ctx, iis2dh_temp_en_t *val) { iis2dh_temp_cfg_reg_t temp_cfg_reg; @@ -320,7 +324,7 @@ int32_t iis2dh_temperature_meas_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_operating_mode_set(stmdev_ctx_t *ctx, +int32_t iis2dh_operating_mode_set(const stmdev_ctx_t *ctx, iis2dh_op_md_t val) { iis2dh_ctrl_reg1_t ctrl_reg1; @@ -373,7 +377,7 @@ int32_t iis2dh_operating_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_operating_mode_get(stmdev_ctx_t *ctx, +int32_t iis2dh_operating_mode_get(const stmdev_ctx_t *ctx, iis2dh_op_md_t *val) { iis2dh_ctrl_reg1_t ctrl_reg1; @@ -413,7 +417,7 @@ int32_t iis2dh_operating_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_data_rate_set(stmdev_ctx_t *ctx, iis2dh_odr_t val) +int32_t iis2dh_data_rate_set(const stmdev_ctx_t *ctx, iis2dh_odr_t val) { iis2dh_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -437,7 +441,7 @@ int32_t iis2dh_data_rate_set(stmdev_ctx_t *ctx, iis2dh_odr_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_data_rate_get(stmdev_ctx_t *ctx, iis2dh_odr_t *val) +int32_t iis2dh_data_rate_get(const stmdev_ctx_t *ctx, iis2dh_odr_t *val) { iis2dh_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -503,7 +507,7 @@ int32_t iis2dh_data_rate_get(stmdev_ctx_t *ctx, iis2dh_odr_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_high_pass_on_outputs_set(stmdev_ctx_t *ctx, +int32_t iis2dh_high_pass_on_outputs_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dh_ctrl_reg2_t ctrl_reg2; @@ -529,7 +533,7 @@ int32_t iis2dh_high_pass_on_outputs_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_high_pass_on_outputs_get(stmdev_ctx_t *ctx, +int32_t iis2dh_high_pass_on_outputs_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dh_ctrl_reg2_t ctrl_reg2; @@ -555,7 +559,7 @@ int32_t iis2dh_high_pass_on_outputs_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_high_pass_bandwidth_set(stmdev_ctx_t *ctx, +int32_t iis2dh_high_pass_bandwidth_set(const stmdev_ctx_t *ctx, iis2dh_hpcf_t val) { iis2dh_ctrl_reg2_t ctrl_reg2; @@ -586,7 +590,7 @@ int32_t iis2dh_high_pass_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_high_pass_bandwidth_get(stmdev_ctx_t *ctx, +int32_t iis2dh_high_pass_bandwidth_get(const stmdev_ctx_t *ctx, iis2dh_hpcf_t *val) { iis2dh_ctrl_reg2_t ctrl_reg2; @@ -628,7 +632,7 @@ int32_t iis2dh_high_pass_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_high_pass_mode_set(stmdev_ctx_t *ctx, iis2dh_hpm_t val) +int32_t iis2dh_high_pass_mode_set(const stmdev_ctx_t *ctx, iis2dh_hpm_t val) { iis2dh_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -652,7 +656,7 @@ int32_t iis2dh_high_pass_mode_set(stmdev_ctx_t *ctx, iis2dh_hpm_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_high_pass_mode_get(stmdev_ctx_t *ctx, +int32_t iis2dh_high_pass_mode_get(const stmdev_ctx_t *ctx, iis2dh_hpm_t *val) { iis2dh_ctrl_reg2_t ctrl_reg2; @@ -694,7 +698,7 @@ int32_t iis2dh_high_pass_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_full_scale_set(stmdev_ctx_t *ctx, iis2dh_fs_t val) +int32_t iis2dh_full_scale_set(const stmdev_ctx_t *ctx, iis2dh_fs_t val) { iis2dh_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -718,7 +722,7 @@ int32_t iis2dh_full_scale_set(stmdev_ctx_t *ctx, iis2dh_fs_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_full_scale_get(stmdev_ctx_t *ctx, iis2dh_fs_t *val) +int32_t iis2dh_full_scale_get(const stmdev_ctx_t *ctx, iis2dh_fs_t *val) { iis2dh_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -759,7 +763,7 @@ int32_t iis2dh_full_scale_get(stmdev_ctx_t *ctx, iis2dh_fs_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dh_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dh_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -783,7 +787,7 @@ int32_t iis2dh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dh_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dh_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -803,7 +807,7 @@ int32_t iis2dh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis2dh_filter_reference_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -821,7 +825,7 @@ int32_t iis2dh_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_filter_reference_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis2dh_filter_reference_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -837,7 +841,7 @@ int32_t iis2dh_filter_reference_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dh_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dh_status_reg_t status_reg; int32_t ret; @@ -855,7 +859,7 @@ int32_t iis2dh_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dh_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dh_status_reg_t status_reg; int32_t ret; @@ -873,7 +877,7 @@ int32_t iis2dh_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t iis2dh_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -908,7 +912,7 @@ int32_t iis2dh_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis2dh_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -924,7 +928,7 @@ int32_t iis2dh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_self_test_set(stmdev_ctx_t *ctx, iis2dh_st_t val) +int32_t iis2dh_self_test_set(const stmdev_ctx_t *ctx, iis2dh_st_t val) { iis2dh_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -948,7 +952,7 @@ int32_t iis2dh_self_test_set(stmdev_ctx_t *ctx, iis2dh_st_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_self_test_get(stmdev_ctx_t *ctx, iis2dh_st_t *val) +int32_t iis2dh_self_test_get(const stmdev_ctx_t *ctx, iis2dh_st_t *val) { iis2dh_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -985,7 +989,7 @@ int32_t iis2dh_self_test_get(stmdev_ctx_t *ctx, iis2dh_st_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_data_format_set(stmdev_ctx_t *ctx, iis2dh_ble_t val) +int32_t iis2dh_data_format_set(const stmdev_ctx_t *ctx, iis2dh_ble_t val) { iis2dh_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -1009,7 +1013,7 @@ int32_t iis2dh_data_format_set(stmdev_ctx_t *ctx, iis2dh_ble_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_data_format_get(stmdev_ctx_t *ctx, iis2dh_ble_t *val) +int32_t iis2dh_data_format_get(const stmdev_ctx_t *ctx, iis2dh_ble_t *val) { iis2dh_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -1042,7 +1046,7 @@ int32_t iis2dh_data_format_get(stmdev_ctx_t *ctx, iis2dh_ble_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dh_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dh_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1066,7 +1070,7 @@ int32_t iis2dh_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dh_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dh_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1085,7 +1089,7 @@ int32_t iis2dh_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_int_occurrencies_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dh_int_occurrencies_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -1102,7 +1106,7 @@ int32_t iis2dh_int_occurrencies_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_status_get(stmdev_ctx_t *ctx, iis2dh_status_reg_t *val) +int32_t iis2dh_status_get(const stmdev_ctx_t *ctx, iis2dh_status_reg_t *val) { int32_t ret; @@ -1131,7 +1135,7 @@ int32_t iis2dh_status_get(stmdev_ctx_t *ctx, iis2dh_status_reg_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_int1_gen_conf_set(stmdev_ctx_t *ctx, +int32_t iis2dh_int1_gen_conf_set(const stmdev_ctx_t *ctx, iis2dh_int1_cfg_t *val) { int32_t ret; @@ -1149,7 +1153,7 @@ int32_t iis2dh_int1_gen_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_int1_gen_conf_get(stmdev_ctx_t *ctx, +int32_t iis2dh_int1_gen_conf_get(const stmdev_ctx_t *ctx, iis2dh_int1_cfg_t *val) { int32_t ret; @@ -1167,7 +1171,7 @@ int32_t iis2dh_int1_gen_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_int1_gen_source_get(stmdev_ctx_t *ctx, +int32_t iis2dh_int1_gen_source_get(const stmdev_ctx_t *ctx, iis2dh_int1_src_t *val) { int32_t ret; @@ -1186,7 +1190,7 @@ int32_t iis2dh_int1_gen_source_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_int1_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dh_int1_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dh_int1_ths_t int1_ths; int32_t ret; @@ -1212,7 +1216,7 @@ int32_t iis2dh_int1_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_int1_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dh_int1_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dh_int1_ths_t int1_ths; int32_t ret; @@ -1232,7 +1236,7 @@ int32_t iis2dh_int1_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dh_int1_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dh_int1_duration_t int1_duration; int32_t ret; @@ -1259,7 +1263,7 @@ int32_t iis2dh_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dh_int1_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dh_int1_duration_t int1_duration; int32_t ret; @@ -1292,7 +1296,7 @@ int32_t iis2dh_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_int2_gen_conf_set(stmdev_ctx_t *ctx, +int32_t iis2dh_int2_gen_conf_set(const stmdev_ctx_t *ctx, iis2dh_int2_cfg_t *val) { int32_t ret; @@ -1310,7 +1314,7 @@ int32_t iis2dh_int2_gen_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_int2_gen_conf_get(stmdev_ctx_t *ctx, +int32_t iis2dh_int2_gen_conf_get(const stmdev_ctx_t *ctx, iis2dh_int2_cfg_t *val) { int32_t ret; @@ -1327,7 +1331,7 @@ int32_t iis2dh_int2_gen_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_int2_gen_source_get(stmdev_ctx_t *ctx, +int32_t iis2dh_int2_gen_source_get(const stmdev_ctx_t *ctx, iis2dh_int2_src_t *val) { int32_t ret; @@ -1346,7 +1350,7 @@ int32_t iis2dh_int2_gen_source_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_int2_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dh_int2_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dh_int2_ths_t int2_ths; int32_t ret; @@ -1372,7 +1376,7 @@ int32_t iis2dh_int2_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_int2_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dh_int2_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dh_int2_ths_t int2_ths; int32_t ret; @@ -1392,7 +1396,7 @@ int32_t iis2dh_int2_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dh_int2_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dh_int2_duration_t int2_duration; int32_t ret; @@ -1419,7 +1423,7 @@ int32_t iis2dh_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dh_int2_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dh_int2_duration_t int2_duration; int32_t ret; @@ -1451,7 +1455,7 @@ int32_t iis2dh_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_high_pass_int_conf_set(stmdev_ctx_t *ctx, +int32_t iis2dh_high_pass_int_conf_set(const stmdev_ctx_t *ctx, iis2dh_hp_t val) { iis2dh_ctrl_reg2_t ctrl_reg2; @@ -1476,7 +1480,7 @@ int32_t iis2dh_high_pass_int_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_high_pass_int_conf_get(stmdev_ctx_t *ctx, +int32_t iis2dh_high_pass_int_conf_get(const stmdev_ctx_t *ctx, iis2dh_hp_t *val) { iis2dh_ctrl_reg2_t ctrl_reg2; @@ -1534,7 +1538,7 @@ int32_t iis2dh_high_pass_int_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_pin_int1_config_set(stmdev_ctx_t *ctx, +int32_t iis2dh_pin_int1_config_set(const stmdev_ctx_t *ctx, iis2dh_ctrl_reg3_t *val) { int32_t ret; @@ -1552,7 +1556,7 @@ int32_t iis2dh_pin_int1_config_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_pin_int1_config_get(stmdev_ctx_t *ctx, +int32_t iis2dh_pin_int1_config_get(const stmdev_ctx_t *ctx, iis2dh_ctrl_reg3_t *val) { int32_t ret; @@ -1571,7 +1575,7 @@ int32_t iis2dh_pin_int1_config_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dh_int2_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dh_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1596,7 +1600,7 @@ int32_t iis2dh_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dh_int2_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dh_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1617,7 +1621,7 @@ int32_t iis2dh_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_int2_pin_notification_mode_set(stmdev_ctx_t *ctx, +int32_t iis2dh_int2_pin_notification_mode_set(const stmdev_ctx_t *ctx, iis2dh_lir_int2_t val) { iis2dh_ctrl_reg5_t ctrl_reg5; @@ -1644,7 +1648,7 @@ int32_t iis2dh_int2_pin_notification_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_int2_pin_notification_mode_get(stmdev_ctx_t *ctx, +int32_t iis2dh_int2_pin_notification_mode_get(const stmdev_ctx_t *ctx, iis2dh_lir_int2_t *val) { iis2dh_ctrl_reg5_t ctrl_reg5; @@ -1679,7 +1683,7 @@ int32_t iis2dh_int2_pin_notification_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dh_int1_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dh_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1704,7 +1708,7 @@ int32_t iis2dh_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dh_int1_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dh_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1724,7 +1728,7 @@ int32_t iis2dh_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_int1_pin_notification_mode_set(stmdev_ctx_t *ctx, +int32_t iis2dh_int1_pin_notification_mode_set(const stmdev_ctx_t *ctx, iis2dh_lir_int1_t val) { iis2dh_ctrl_reg5_t ctrl_reg5; @@ -1750,7 +1754,7 @@ int32_t iis2dh_int1_pin_notification_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_int1_pin_notification_mode_get(stmdev_ctx_t *ctx, +int32_t iis2dh_int1_pin_notification_mode_get(const stmdev_ctx_t *ctx, iis2dh_lir_int1_t *val) { iis2dh_ctrl_reg5_t ctrl_reg5; @@ -1784,7 +1788,7 @@ int32_t iis2dh_int1_pin_notification_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_pin_int2_config_set(stmdev_ctx_t *ctx, +int32_t iis2dh_pin_int2_config_set(const stmdev_ctx_t *ctx, iis2dh_ctrl_reg6_t *val) { int32_t ret; @@ -1802,7 +1806,7 @@ int32_t iis2dh_pin_int2_config_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_pin_int2_config_get(stmdev_ctx_t *ctx, +int32_t iis2dh_pin_int2_config_get(const stmdev_ctx_t *ctx, iis2dh_ctrl_reg6_t *val) { int32_t ret; @@ -1832,7 +1836,7 @@ int32_t iis2dh_pin_int2_config_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_fifo_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dh_fifo_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dh_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1856,7 +1860,7 @@ int32_t iis2dh_fifo_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_fifo_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dh_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dh_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1875,7 +1879,7 @@ int32_t iis2dh_fifo_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dh_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dh_fifo_ctrl_reg_t fifo_ctrl_reg; int32_t ret; @@ -1901,7 +1905,7 @@ int32_t iis2dh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dh_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dh_fifo_ctrl_reg_t fifo_ctrl_reg; int32_t ret; @@ -1921,7 +1925,7 @@ int32_t iis2dh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_fifo_trigger_event_set(stmdev_ctx_t *ctx, +int32_t iis2dh_fifo_trigger_event_set(const stmdev_ctx_t *ctx, iis2dh_tr_t val) { iis2dh_fifo_ctrl_reg_t fifo_ctrl_reg; @@ -1948,7 +1952,7 @@ int32_t iis2dh_fifo_trigger_event_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_fifo_trigger_event_get(stmdev_ctx_t *ctx, +int32_t iis2dh_fifo_trigger_event_get(const stmdev_ctx_t *ctx, iis2dh_tr_t *val) { iis2dh_fifo_ctrl_reg_t fifo_ctrl_reg; @@ -1983,7 +1987,7 @@ int32_t iis2dh_fifo_trigger_event_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_fifo_mode_set(stmdev_ctx_t *ctx, iis2dh_fm_t val) +int32_t iis2dh_fifo_mode_set(const stmdev_ctx_t *ctx, iis2dh_fm_t val) { iis2dh_fifo_ctrl_reg_t fifo_ctrl_reg; int32_t ret; @@ -2009,7 +2013,7 @@ int32_t iis2dh_fifo_mode_set(stmdev_ctx_t *ctx, iis2dh_fm_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_fifo_mode_get(stmdev_ctx_t *ctx, iis2dh_fm_t *val) +int32_t iis2dh_fifo_mode_get(const stmdev_ctx_t *ctx, iis2dh_fm_t *val) { iis2dh_fifo_ctrl_reg_t fifo_ctrl_reg; int32_t ret; @@ -2051,7 +2055,7 @@ int32_t iis2dh_fifo_mode_get(stmdev_ctx_t *ctx, iis2dh_fm_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_fifo_status_get(stmdev_ctx_t *ctx, +int32_t iis2dh_fifo_status_get(const stmdev_ctx_t *ctx, iis2dh_fifo_src_reg_t *val) { int32_t ret; @@ -2068,7 +2072,7 @@ int32_t iis2dh_fifo_status_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dh_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dh_fifo_src_reg_t fifo_src_reg; int32_t ret; @@ -2087,7 +2091,7 @@ int32_t iis2dh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dh_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dh_fifo_src_reg_t fifo_src_reg; int32_t ret; @@ -2106,7 +2110,7 @@ int32_t iis2dh_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dh_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dh_fifo_src_reg_t fifo_src_reg; int32_t ret; @@ -2125,7 +2129,7 @@ int32_t iis2dh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dh_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dh_fifo_src_reg_t fifo_src_reg; int32_t ret; @@ -2157,7 +2161,7 @@ int32_t iis2dh_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_tap_conf_set(stmdev_ctx_t *ctx, +int32_t iis2dh_tap_conf_set(const stmdev_ctx_t *ctx, iis2dh_click_cfg_t *val) { int32_t ret; @@ -2175,7 +2179,7 @@ int32_t iis2dh_tap_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_tap_conf_get(stmdev_ctx_t *ctx, +int32_t iis2dh_tap_conf_get(const stmdev_ctx_t *ctx, iis2dh_click_cfg_t *val) { int32_t ret; @@ -2192,7 +2196,7 @@ int32_t iis2dh_tap_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_tap_source_get(stmdev_ctx_t *ctx, +int32_t iis2dh_tap_source_get(const stmdev_ctx_t *ctx, iis2dh_click_src_t *val) { int32_t ret; @@ -2210,7 +2214,7 @@ int32_t iis2dh_tap_source_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dh_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dh_click_ths_t click_ths; int32_t ret; @@ -2235,7 +2239,7 @@ int32_t iis2dh_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dh_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dh_click_ths_t click_ths; int32_t ret; @@ -2256,7 +2260,7 @@ int32_t iis2dh_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dh_shock_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dh_time_limit_t time_limit; int32_t ret; @@ -2282,7 +2286,7 @@ int32_t iis2dh_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dh_shock_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dh_time_limit_t time_limit; int32_t ret; @@ -2304,7 +2308,7 @@ int32_t iis2dh_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dh_quiet_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dh_time_latency_t time_latency; int32_t ret; @@ -2333,7 +2337,7 @@ int32_t iis2dh_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dh_quiet_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dh_time_latency_t time_latency; int32_t ret; @@ -2356,7 +2360,7 @@ int32_t iis2dh_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dh_double_tap_timeout_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dh_time_window_t time_window; int32_t ret; @@ -2385,7 +2389,7 @@ int32_t iis2dh_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_double_tap_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dh_double_tap_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dh_time_window_t time_window; int32_t ret; @@ -2420,7 +2424,7 @@ int32_t iis2dh_double_tap_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dh_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dh_act_ths_t act_ths; int32_t ret; @@ -2446,7 +2450,7 @@ int32_t iis2dh_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dh_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dh_act_ths_t act_ths; int32_t ret; @@ -2466,7 +2470,7 @@ int32_t iis2dh_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dh_act_timeout_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dh_act_dur_t act_dur; int32_t ret; @@ -2491,7 +2495,7 @@ int32_t iis2dh_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dh_act_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dh_act_dur_t act_dur; int32_t ret; @@ -2523,7 +2527,7 @@ int32_t iis2dh_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_spi_mode_set(stmdev_ctx_t *ctx, iis2dh_sim_t val) +int32_t iis2dh_spi_mode_set(const stmdev_ctx_t *ctx, iis2dh_sim_t val) { iis2dh_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -2547,7 +2551,7 @@ int32_t iis2dh_spi_mode_set(stmdev_ctx_t *ctx, iis2dh_sim_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dh_spi_mode_get(stmdev_ctx_t *ctx, iis2dh_sim_t *val) +int32_t iis2dh_spi_mode_get(const stmdev_ctx_t *ctx, iis2dh_sim_t *val) { iis2dh_ctrl_reg4_t ctrl_reg4; int32_t ret; diff --git a/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.h b/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.h index 48ef2045..87d51e88 100644 --- a/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.h +++ b/sensor/stmemsc/iis2dh_STdC/driver/iis2dh_reg.h @@ -705,9 +705,9 @@ typedef union * them with a custom implementation. */ -int32_t iis2dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, +int32_t iis2dh_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t iis2dh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t iis2dh_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -729,21 +729,21 @@ float_t iis2dh_from_fs8_lp_to_mg(int16_t lsb); float_t iis2dh_from_fs16_lp_to_mg(int16_t lsb); float_t iis2dh_from_lsb_lp_to_celsius(int16_t lsb); -int32_t iis2dh_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t iis2dh_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dh_temp_status_reg_get(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t iis2dh_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dh_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dh_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t iis2dh_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); typedef enum { IIS2DH_TEMP_DISABLE = 0, IIS2DH_TEMP_ENABLE = 3, } iis2dh_temp_en_t; -int32_t iis2dh_temperature_meas_set(stmdev_ctx_t *ctx, +int32_t iis2dh_temperature_meas_set(const stmdev_ctx_t *ctx, iis2dh_temp_en_t val); -int32_t iis2dh_temperature_meas_get(stmdev_ctx_t *ctx, +int32_t iis2dh_temperature_meas_get(const stmdev_ctx_t *ctx, iis2dh_temp_en_t *val); typedef enum @@ -752,9 +752,9 @@ typedef enum IIS2DH_NM_10bit = 1, IIS2DH_LP_8bit = 2, } iis2dh_op_md_t; -int32_t iis2dh_operating_mode_set(stmdev_ctx_t *ctx, +int32_t iis2dh_operating_mode_set(const stmdev_ctx_t *ctx, iis2dh_op_md_t val); -int32_t iis2dh_operating_mode_get(stmdev_ctx_t *ctx, +int32_t iis2dh_operating_mode_get(const stmdev_ctx_t *ctx, iis2dh_op_md_t *val); typedef enum @@ -770,12 +770,12 @@ typedef enum IIS2DH_ODR_1kHz620_LP = 0x08, IIS2DH_ODR_5kHz376_LP_1kHz344_NM_HP = 0x09, } iis2dh_odr_t; -int32_t iis2dh_data_rate_set(stmdev_ctx_t *ctx, iis2dh_odr_t val); -int32_t iis2dh_data_rate_get(stmdev_ctx_t *ctx, iis2dh_odr_t *val); +int32_t iis2dh_data_rate_set(const stmdev_ctx_t *ctx, iis2dh_odr_t val); +int32_t iis2dh_data_rate_get(const stmdev_ctx_t *ctx, iis2dh_odr_t *val); -int32_t iis2dh_high_pass_on_outputs_set(stmdev_ctx_t *ctx, +int32_t iis2dh_high_pass_on_outputs_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dh_high_pass_on_outputs_get(stmdev_ctx_t *ctx, +int32_t iis2dh_high_pass_on_outputs_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -785,9 +785,9 @@ typedef enum IIS2DH_MEDIUM = 2, IIS2DH_LIGHT = 3, } iis2dh_hpcf_t; -int32_t iis2dh_high_pass_bandwidth_set(stmdev_ctx_t *ctx, +int32_t iis2dh_high_pass_bandwidth_set(const stmdev_ctx_t *ctx, iis2dh_hpcf_t val); -int32_t iis2dh_high_pass_bandwidth_get(stmdev_ctx_t *ctx, +int32_t iis2dh_high_pass_bandwidth_get(const stmdev_ctx_t *ctx, iis2dh_hpcf_t *val); typedef enum @@ -797,9 +797,9 @@ typedef enum IIS2DH_NORMAL = 2, IIS2DH_AUTORST_ON_INT = 3, } iis2dh_hpm_t; -int32_t iis2dh_high_pass_mode_set(stmdev_ctx_t *ctx, +int32_t iis2dh_high_pass_mode_set(const stmdev_ctx_t *ctx, iis2dh_hpm_t val); -int32_t iis2dh_high_pass_mode_get(stmdev_ctx_t *ctx, +int32_t iis2dh_high_pass_mode_get(const stmdev_ctx_t *ctx, iis2dh_hpm_t *val); typedef enum @@ -809,22 +809,22 @@ typedef enum IIS2DH_8g = 2, IIS2DH_16g = 3, } iis2dh_fs_t; -int32_t iis2dh_full_scale_set(stmdev_ctx_t *ctx, iis2dh_fs_t val); -int32_t iis2dh_full_scale_get(stmdev_ctx_t *ctx, iis2dh_fs_t *val); +int32_t iis2dh_full_scale_set(const stmdev_ctx_t *ctx, iis2dh_fs_t val); +int32_t iis2dh_full_scale_get(const stmdev_ctx_t *ctx, iis2dh_fs_t *val); -int32_t iis2dh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dh_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dh_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dh_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t iis2dh_filter_reference_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t iis2dh_filter_reference_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t iis2dh_filter_reference_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t iis2dh_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dh_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dh_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dh_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dh_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t iis2dh_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t iis2dh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t iis2dh_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); typedef enum { @@ -832,53 +832,53 @@ typedef enum IIS2DH_ST_POSITIVE = 1, IIS2DH_ST_NEGATIVE = 2, } iis2dh_st_t; -int32_t iis2dh_self_test_set(stmdev_ctx_t *ctx, iis2dh_st_t val); -int32_t iis2dh_self_test_get(stmdev_ctx_t *ctx, iis2dh_st_t *val); +int32_t iis2dh_self_test_set(const stmdev_ctx_t *ctx, iis2dh_st_t val); +int32_t iis2dh_self_test_get(const stmdev_ctx_t *ctx, iis2dh_st_t *val); typedef enum { IIS2DH_LSB_AT_LOW_ADD = 0, IIS2DH_MSB_AT_LOW_ADD = 1, } iis2dh_ble_t; -int32_t iis2dh_data_format_set(stmdev_ctx_t *ctx, iis2dh_ble_t val); -int32_t iis2dh_data_format_get(stmdev_ctx_t *ctx, iis2dh_ble_t *val); +int32_t iis2dh_data_format_set(const stmdev_ctx_t *ctx, iis2dh_ble_t val); +int32_t iis2dh_data_format_get(const stmdev_ctx_t *ctx, iis2dh_ble_t *val); -int32_t iis2dh_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dh_boot_get(stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dh_int_occurrencies_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dh_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dh_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dh_int_occurrencies_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dh_status_get(stmdev_ctx_t *ctx, +int32_t iis2dh_status_get(const stmdev_ctx_t *ctx, iis2dh_status_reg_t *val); -int32_t iis2dh_int1_gen_conf_set(stmdev_ctx_t *ctx, +int32_t iis2dh_int1_gen_conf_set(const stmdev_ctx_t *ctx, iis2dh_int1_cfg_t *val); -int32_t iis2dh_int1_gen_conf_get(stmdev_ctx_t *ctx, +int32_t iis2dh_int1_gen_conf_get(const stmdev_ctx_t *ctx, iis2dh_int1_cfg_t *val); -int32_t iis2dh_int1_gen_source_get(stmdev_ctx_t *ctx, +int32_t iis2dh_int1_gen_source_get(const stmdev_ctx_t *ctx, iis2dh_int1_src_t *val); -int32_t iis2dh_int1_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dh_int1_gen_threshold_get(stmdev_ctx_t *ctx, +int32_t iis2dh_int1_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dh_int1_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dh_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dh_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dh_int1_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dh_int1_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dh_int2_gen_conf_set(stmdev_ctx_t *ctx, +int32_t iis2dh_int2_gen_conf_set(const stmdev_ctx_t *ctx, iis2dh_int2_cfg_t *val); -int32_t iis2dh_int2_gen_conf_get(stmdev_ctx_t *ctx, +int32_t iis2dh_int2_gen_conf_get(const stmdev_ctx_t *ctx, iis2dh_int2_cfg_t *val); -int32_t iis2dh_int2_gen_source_get(stmdev_ctx_t *ctx, +int32_t iis2dh_int2_gen_source_get(const stmdev_ctx_t *ctx, iis2dh_int2_src_t *val); -int32_t iis2dh_int2_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dh_int2_gen_threshold_get(stmdev_ctx_t *ctx, +int32_t iis2dh_int2_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dh_int2_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dh_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dh_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dh_int2_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dh_int2_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -891,18 +891,18 @@ typedef enum IIS2DH_ON_INT2_TAP_GEN = 6, IIS2DH_ON_INT1_INT2_TAP_GEN = 7, } iis2dh_hp_t; -int32_t iis2dh_high_pass_int_conf_set(stmdev_ctx_t *ctx, +int32_t iis2dh_high_pass_int_conf_set(const stmdev_ctx_t *ctx, iis2dh_hp_t val); -int32_t iis2dh_high_pass_int_conf_get(stmdev_ctx_t *ctx, +int32_t iis2dh_high_pass_int_conf_get(const stmdev_ctx_t *ctx, iis2dh_hp_t *val); -int32_t iis2dh_pin_int1_config_set(stmdev_ctx_t *ctx, +int32_t iis2dh_pin_int1_config_set(const stmdev_ctx_t *ctx, iis2dh_ctrl_reg3_t *val); -int32_t iis2dh_pin_int1_config_get(stmdev_ctx_t *ctx, +int32_t iis2dh_pin_int1_config_get(const stmdev_ctx_t *ctx, iis2dh_ctrl_reg3_t *val); -int32_t iis2dh_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dh_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, +int32_t iis2dh_int2_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dh_int2_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -910,13 +910,13 @@ typedef enum IIS2DH_INT2_PULSED = 0, IIS2DH_INT2_LATCHED = 1, } iis2dh_lir_int2_t; -int32_t iis2dh_int2_pin_notification_mode_set(stmdev_ctx_t *ctx, +int32_t iis2dh_int2_pin_notification_mode_set(const stmdev_ctx_t *ctx, iis2dh_lir_int2_t val); -int32_t iis2dh_int2_pin_notification_mode_get(stmdev_ctx_t *ctx, +int32_t iis2dh_int2_pin_notification_mode_get(const stmdev_ctx_t *ctx, iis2dh_lir_int2_t *val); -int32_t iis2dh_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dh_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, +int32_t iis2dh_int1_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dh_int1_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -924,30 +924,30 @@ typedef enum IIS2DH_INT1_PULSED = 0, IIS2DH_INT1_LATCHED = 1, } iis2dh_lir_int1_t; -int32_t iis2dh_int1_pin_notification_mode_set(stmdev_ctx_t *ctx, +int32_t iis2dh_int1_pin_notification_mode_set(const stmdev_ctx_t *ctx, iis2dh_lir_int1_t val); -int32_t iis2dh_int1_pin_notification_mode_get(stmdev_ctx_t *ctx, +int32_t iis2dh_int1_pin_notification_mode_get(const stmdev_ctx_t *ctx, iis2dh_lir_int1_t *val); -int32_t iis2dh_pin_int2_config_set(stmdev_ctx_t *ctx, +int32_t iis2dh_pin_int2_config_set(const stmdev_ctx_t *ctx, iis2dh_ctrl_reg6_t *val); -int32_t iis2dh_pin_int2_config_get(stmdev_ctx_t *ctx, +int32_t iis2dh_pin_int2_config_get(const stmdev_ctx_t *ctx, iis2dh_ctrl_reg6_t *val); -int32_t iis2dh_fifo_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dh_fifo_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dh_fifo_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dh_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dh_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dh_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { IIS2DH_INT1_GEN = 0, IIS2DH_INT2_GEN = 1, } iis2dh_tr_t; -int32_t iis2dh_fifo_trigger_event_set(stmdev_ctx_t *ctx, +int32_t iis2dh_fifo_trigger_event_set(const stmdev_ctx_t *ctx, iis2dh_tr_t val); -int32_t iis2dh_fifo_trigger_event_get(stmdev_ctx_t *ctx, +int32_t iis2dh_fifo_trigger_event_get(const stmdev_ctx_t *ctx, iis2dh_tr_t *val); typedef enum @@ -957,74 +957,64 @@ typedef enum IIS2DH_DYNAMIC_STREAM_MODE = 2, IIS2DH_STREAM_TO_FIFO_MODE = 3, } iis2dh_fm_t; -int32_t iis2dh_fifo_mode_set(stmdev_ctx_t *ctx, iis2dh_fm_t val); -int32_t iis2dh_fifo_mode_get(stmdev_ctx_t *ctx, iis2dh_fm_t *val); +int32_t iis2dh_fifo_mode_set(const stmdev_ctx_t *ctx, iis2dh_fm_t val); +int32_t iis2dh_fifo_mode_get(const stmdev_ctx_t *ctx, iis2dh_fm_t *val); -int32_t iis2dh_fifo_status_get(stmdev_ctx_t *ctx, +int32_t iis2dh_fifo_status_get(const stmdev_ctx_t *ctx, iis2dh_fifo_src_reg_t *val); -int32_t iis2dh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dh_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dh_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dh_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dh_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dh_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dh_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dh_tap_conf_set(stmdev_ctx_t *ctx, +int32_t iis2dh_tap_conf_set(const stmdev_ctx_t *ctx, iis2dh_click_cfg_t *val); -int32_t iis2dh_tap_conf_get(stmdev_ctx_t *ctx, +int32_t iis2dh_tap_conf_get(const stmdev_ctx_t *ctx, iis2dh_click_cfg_t *val); -int32_t iis2dh_tap_source_get(stmdev_ctx_t *ctx, +int32_t iis2dh_tap_source_get(const stmdev_ctx_t *ctx, iis2dh_click_src_t *val); -int32_t iis2dh_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dh_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dh_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dh_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { IIS2DH_TAP_PULSED = 0, IIS2DH_TAP_LATCHED = 1, } iis2dh_lir_click_t; -int32_t iis2dh_tap_notification_mode_set(stmdev_ctx_t *ctx, +int32_t iis2dh_tap_notification_mode_set(const stmdev_ctx_t *ctx, iis2dh_lir_click_t val); -int32_t iis2dh_tap_notification_mode_get(stmdev_ctx_t *ctx, +int32_t iis2dh_tap_notification_mode_get(const stmdev_ctx_t *ctx, iis2dh_lir_click_t *val); -int32_t iis2dh_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dh_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dh_shock_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dh_shock_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dh_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dh_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dh_quiet_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dh_quiet_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dh_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dh_double_tap_timeout_get(stmdev_ctx_t *ctx, +int32_t iis2dh_double_tap_timeout_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dh_double_tap_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dh_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dh_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dh_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dh_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dh_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dh_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val); - -typedef enum -{ - IIS2DH_PULL_UP_DISCONNECT = 0, - IIS2DH_PULL_UP_CONNECT = 1, -} iis2dh_sdo_pu_disc_t; -int32_t iis2dh_pin_sdo_sa0_mode_set(stmdev_ctx_t *ctx, - iis2dh_sdo_pu_disc_t val); -int32_t iis2dh_pin_sdo_sa0_mode_get(stmdev_ctx_t *ctx, - iis2dh_sdo_pu_disc_t *val); +int32_t iis2dh_act_timeout_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dh_act_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { IIS2DH_SPI_4_WIRE = 0, IIS2DH_SPI_3_WIRE = 1, } iis2dh_sim_t; -int32_t iis2dh_spi_mode_set(stmdev_ctx_t *ctx, iis2dh_sim_t val); -int32_t iis2dh_spi_mode_get(stmdev_ctx_t *ctx, iis2dh_sim_t *val); +int32_t iis2dh_spi_mode_set(const stmdev_ctx_t *ctx, iis2dh_sim_t val); +int32_t iis2dh_spi_mode_get(const stmdev_ctx_t *ctx, iis2dh_sim_t *val); /** * @} diff --git a/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.c b/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.c index b5f65db9..c2360bdb 100644 --- a/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.c +++ b/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.c @@ -46,12 +46,14 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak iis2dlpc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak iis2dlpc_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +69,14 @@ int32_t __weak iis2dlpc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak iis2dlpc_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak iis2dlpc_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -157,7 +161,7 @@ float_t iis2dlpc_from_lsb_to_celsius(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_power_mode_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_power_mode_set(const stmdev_ctx_t *ctx, iis2dlpc_mode_t val) { iis2dlpc_ctrl1_t ctrl1; @@ -201,7 +205,7 @@ int32_t iis2dlpc_power_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_power_mode_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_power_mode_get(const stmdev_ctx_t *ctx, iis2dlpc_mode_t *val) { iis2dlpc_ctrl1_t ctrl1; @@ -306,7 +310,7 @@ int32_t iis2dlpc_power_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_data_rate_set(stmdev_ctx_t *ctx, iis2dlpc_odr_t val) +int32_t iis2dlpc_data_rate_set(const stmdev_ctx_t *ctx, iis2dlpc_odr_t val) { iis2dlpc_ctrl1_t ctrl1; iis2dlpc_ctrl3_t ctrl3; @@ -347,7 +351,7 @@ int32_t iis2dlpc_data_rate_set(stmdev_ctx_t *ctx, iis2dlpc_odr_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_data_rate_get(stmdev_ctx_t *ctx, iis2dlpc_odr_t *val) +int32_t iis2dlpc_data_rate_get(const stmdev_ctx_t *ctx, iis2dlpc_odr_t *val) { iis2dlpc_ctrl1_t ctrl1; iis2dlpc_ctrl3_t ctrl3; @@ -426,7 +430,7 @@ int32_t iis2dlpc_data_rate_get(stmdev_ctx_t *ctx, iis2dlpc_odr_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dlpc_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dlpc_ctrl2_t reg; int32_t ret; @@ -450,7 +454,7 @@ int32_t iis2dlpc_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_block_data_update_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dlpc_ctrl2_t reg; @@ -470,7 +474,7 @@ int32_t iis2dlpc_block_data_update_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_full_scale_set(stmdev_ctx_t *ctx, iis2dlpc_fs_t val) +int32_t iis2dlpc_full_scale_set(const stmdev_ctx_t *ctx, iis2dlpc_fs_t val) { iis2dlpc_ctrl6_t reg; int32_t ret; @@ -494,7 +498,7 @@ int32_t iis2dlpc_full_scale_set(stmdev_ctx_t *ctx, iis2dlpc_fs_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_full_scale_get(stmdev_ctx_t *ctx, iis2dlpc_fs_t *val) +int32_t iis2dlpc_full_scale_get(const stmdev_ctx_t *ctx, iis2dlpc_fs_t *val) { iis2dlpc_ctrl6_t reg; int32_t ret; @@ -535,7 +539,7 @@ int32_t iis2dlpc_full_scale_get(stmdev_ctx_t *ctx, iis2dlpc_fs_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_status_reg_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_status_reg_get(const stmdev_ctx_t *ctx, iis2dlpc_status_t *val) { int32_t ret; @@ -553,7 +557,7 @@ int32_t iis2dlpc_status_reg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dlpc_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dlpc_status_t reg; int32_t ret; @@ -572,7 +576,7 @@ int32_t iis2dlpc_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_all_sources_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_all_sources_get(const stmdev_ctx_t *ctx, iis2dlpc_all_sources_t *val) { int32_t ret; @@ -592,7 +596,7 @@ int32_t iis2dlpc_all_sources_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis2dlpc_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -611,7 +615,7 @@ int32_t iis2dlpc_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis2dlpc_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -630,7 +634,7 @@ int32_t iis2dlpc_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis2dlpc_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -649,7 +653,7 @@ int32_t iis2dlpc_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis2dlpc_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -668,7 +672,7 @@ int32_t iis2dlpc_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis2dlpc_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -687,7 +691,7 @@ int32_t iis2dlpc_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis2dlpc_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -706,7 +710,7 @@ int32_t iis2dlpc_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_offset_weight_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_offset_weight_set(const stmdev_ctx_t *ctx, iis2dlpc_usr_off_w_t val) { iis2dlpc_ctrl7_t reg; @@ -732,7 +736,7 @@ int32_t iis2dlpc_offset_weight_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_offset_weight_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_offset_weight_get(const stmdev_ctx_t *ctx, iis2dlpc_usr_off_w_t *val) { iis2dlpc_ctrl7_t reg; @@ -779,7 +783,7 @@ int32_t iis2dlpc_offset_weight_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t iis2dlpc_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -800,7 +804,7 @@ int32_t iis2dlpc_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t iis2dlpc_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -836,7 +840,7 @@ int32_t iis2dlpc_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis2dlpc_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -854,7 +858,7 @@ int32_t iis2dlpc_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dlpc_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dlpc_ctrl2_t reg; int32_t ret; @@ -879,7 +883,7 @@ int32_t iis2dlpc_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dlpc_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dlpc_ctrl2_t reg; int32_t ret; @@ -898,7 +902,7 @@ int32_t iis2dlpc_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dlpc_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dlpc_ctrl2_t reg; int32_t ret; @@ -922,7 +926,7 @@ int32_t iis2dlpc_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dlpc_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dlpc_ctrl2_t reg; int32_t ret; @@ -941,7 +945,7 @@ int32_t iis2dlpc_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dlpc_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dlpc_ctrl2_t reg; int32_t ret; @@ -965,7 +969,7 @@ int32_t iis2dlpc_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dlpc_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dlpc_ctrl2_t reg; int32_t ret; @@ -984,7 +988,7 @@ int32_t iis2dlpc_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_self_test_set(stmdev_ctx_t *ctx, iis2dlpc_st_t val) +int32_t iis2dlpc_self_test_set(const stmdev_ctx_t *ctx, iis2dlpc_st_t val) { iis2dlpc_ctrl3_t reg; int32_t ret; @@ -1008,7 +1012,7 @@ int32_t iis2dlpc_self_test_set(stmdev_ctx_t *ctx, iis2dlpc_st_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_self_test_get(stmdev_ctx_t *ctx, iis2dlpc_st_t *val) +int32_t iis2dlpc_self_test_get(const stmdev_ctx_t *ctx, iis2dlpc_st_t *val) { iis2dlpc_ctrl3_t reg; int32_t ret; @@ -1045,7 +1049,7 @@ int32_t iis2dlpc_self_test_get(stmdev_ctx_t *ctx, iis2dlpc_st_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_data_ready_mode_set(const stmdev_ctx_t *ctx, iis2dlpc_drdy_pulsed_t val) { iis2dlpc_ctrl7_t reg; @@ -1070,7 +1074,7 @@ int32_t iis2dlpc_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_data_ready_mode_get(const stmdev_ctx_t *ctx, iis2dlpc_drdy_pulsed_t *val) { iis2dlpc_ctrl7_t reg; @@ -1117,7 +1121,7 @@ int32_t iis2dlpc_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_filter_path_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_filter_path_set(const stmdev_ctx_t *ctx, iis2dlpc_fds_t val) { iis2dlpc_ctrl6_t ctrl6; @@ -1159,7 +1163,7 @@ int32_t iis2dlpc_filter_path_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_filter_path_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_filter_path_get(const stmdev_ctx_t *ctx, iis2dlpc_fds_t *val) { iis2dlpc_ctrl6_t ctrl6; @@ -1204,7 +1208,7 @@ int32_t iis2dlpc_filter_path_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_filter_bandwidth_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_filter_bandwidth_set(const stmdev_ctx_t *ctx, iis2dlpc_bw_filt_t val) { iis2dlpc_ctrl6_t reg; @@ -1230,7 +1234,7 @@ int32_t iis2dlpc_filter_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_filter_bandwidth_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_filter_bandwidth_get(const stmdev_ctx_t *ctx, iis2dlpc_bw_filt_t *val) { iis2dlpc_ctrl6_t reg; @@ -1272,7 +1276,7 @@ int32_t iis2dlpc_filter_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dlpc_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dlpc_ctrl7_t reg; int32_t ret; @@ -1296,7 +1300,7 @@ int32_t iis2dlpc_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dlpc_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dlpc_ctrl7_t reg; int32_t ret; @@ -1328,7 +1332,7 @@ int32_t iis2dlpc_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_spi_mode_set(stmdev_ctx_t *ctx, iis2dlpc_sim_t val) +int32_t iis2dlpc_spi_mode_set(const stmdev_ctx_t *ctx, iis2dlpc_sim_t val) { iis2dlpc_ctrl2_t reg; int32_t ret; @@ -1352,7 +1356,7 @@ int32_t iis2dlpc_spi_mode_set(stmdev_ctx_t *ctx, iis2dlpc_sim_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_spi_mode_get(stmdev_ctx_t *ctx, iis2dlpc_sim_t *val) +int32_t iis2dlpc_spi_mode_get(const stmdev_ctx_t *ctx, iis2dlpc_sim_t *val) { iis2dlpc_ctrl2_t reg; int32_t ret; @@ -1386,7 +1390,7 @@ int32_t iis2dlpc_spi_mode_get(stmdev_ctx_t *ctx, iis2dlpc_sim_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_i2c_interface_set(const stmdev_ctx_t *ctx, iis2dlpc_i2c_disable_t val) { iis2dlpc_ctrl2_t reg; @@ -1411,7 +1415,7 @@ int32_t iis2dlpc_i2c_interface_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_i2c_interface_get(const stmdev_ctx_t *ctx, iis2dlpc_i2c_disable_t *val) { iis2dlpc_ctrl2_t reg; @@ -1445,7 +1449,7 @@ int32_t iis2dlpc_i2c_interface_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_cs_mode_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_cs_mode_set(const stmdev_ctx_t *ctx, iis2dlpc_cs_pu_disc_t val) { iis2dlpc_ctrl2_t reg; @@ -1470,7 +1474,7 @@ int32_t iis2dlpc_cs_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_cs_mode_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_cs_mode_get(const stmdev_ctx_t *ctx, iis2dlpc_cs_pu_disc_t *val) { iis2dlpc_ctrl2_t reg; @@ -1516,7 +1520,7 @@ int32_t iis2dlpc_cs_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_pin_polarity_set(const stmdev_ctx_t *ctx, iis2dlpc_h_lactive_t val) { iis2dlpc_ctrl3_t reg; @@ -1541,7 +1545,7 @@ int32_t iis2dlpc_pin_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_pin_polarity_get(const stmdev_ctx_t *ctx, iis2dlpc_h_lactive_t *val) { iis2dlpc_ctrl3_t reg; @@ -1575,7 +1579,7 @@ int32_t iis2dlpc_pin_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_int_notification_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_int_notification_set(const stmdev_ctx_t *ctx, iis2dlpc_lir_t val) { iis2dlpc_ctrl3_t reg; @@ -1600,7 +1604,7 @@ int32_t iis2dlpc_int_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_int_notification_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_int_notification_get(const stmdev_ctx_t *ctx, iis2dlpc_lir_t *val) { iis2dlpc_ctrl3_t reg; @@ -1634,7 +1638,7 @@ int32_t iis2dlpc_int_notification_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_pin_mode_set(stmdev_ctx_t *ctx, iis2dlpc_pp_od_t val) +int32_t iis2dlpc_pin_mode_set(const stmdev_ctx_t *ctx, iis2dlpc_pp_od_t val) { iis2dlpc_ctrl3_t reg; int32_t ret; @@ -1658,7 +1662,7 @@ int32_t iis2dlpc_pin_mode_set(stmdev_ctx_t *ctx, iis2dlpc_pp_od_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_pin_mode_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_pin_mode_get(const stmdev_ctx_t *ctx, iis2dlpc_pp_od_t *val) { iis2dlpc_ctrl3_t reg; @@ -1692,7 +1696,7 @@ int32_t iis2dlpc_pin_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_pin_int1_route_set(const stmdev_ctx_t *ctx, iis2dlpc_ctrl4_int1_pad_ctrl_t *val) { iis2dlpc_ctrl5_int2_pad_ctrl_t ctrl5_int2_pad_ctrl; @@ -1750,7 +1754,7 @@ int32_t iis2dlpc_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_pin_int1_route_get(const stmdev_ctx_t *ctx, iis2dlpc_ctrl4_int1_pad_ctrl_t *val) { int32_t ret; @@ -1769,7 +1773,7 @@ int32_t iis2dlpc_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_pin_int2_route_set(const stmdev_ctx_t *ctx, iis2dlpc_ctrl5_int2_pad_ctrl_t *val) { iis2dlpc_ctrl7_t ctrl_reg7; @@ -1827,7 +1831,7 @@ int32_t iis2dlpc_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_pin_int2_route_get(const stmdev_ctx_t *ctx, iis2dlpc_ctrl5_int2_pad_ctrl_t *val) { int32_t ret; @@ -1845,7 +1849,7 @@ int32_t iis2dlpc_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dlpc_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dlpc_ctrl7_t reg; int32_t ret; @@ -1869,7 +1873,7 @@ int32_t iis2dlpc_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dlpc_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dlpc_ctrl7_t reg; int32_t ret; @@ -1901,7 +1905,7 @@ int32_t iis2dlpc_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dlpc_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dlpc_wake_up_ths_t reg; int32_t ret; @@ -1925,7 +1929,7 @@ int32_t iis2dlpc_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dlpc_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dlpc_wake_up_ths_t reg; int32_t ret; @@ -1944,7 +1948,7 @@ int32_t iis2dlpc_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dlpc_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dlpc_wake_up_dur_t reg; int32_t ret; @@ -1968,7 +1972,7 @@ int32_t iis2dlpc_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dlpc_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dlpc_wake_up_dur_t reg; int32_t ret; @@ -1987,7 +1991,7 @@ int32_t iis2dlpc_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_wkup_feed_data_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_wkup_feed_data_set(const stmdev_ctx_t *ctx, iis2dlpc_usr_off_on_wu_t val) { iis2dlpc_ctrl7_t reg; @@ -2012,7 +2016,7 @@ int32_t iis2dlpc_wkup_feed_data_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_wkup_feed_data_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_wkup_feed_data_get(const stmdev_ctx_t *ctx, iis2dlpc_usr_off_on_wu_t *val) { iis2dlpc_ctrl7_t reg; @@ -2061,7 +2065,7 @@ int32_t iis2dlpc_wkup_feed_data_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_act_mode_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_act_mode_set(const stmdev_ctx_t *ctx, iis2dlpc_sleep_on_t val) { iis2dlpc_wake_up_ths_t wake_up_ths; @@ -2102,7 +2106,7 @@ int32_t iis2dlpc_act_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_act_mode_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_act_mode_get(const stmdev_ctx_t *ctx, iis2dlpc_sleep_on_t *val) { iis2dlpc_wake_up_ths_t wake_up_ths; @@ -2148,7 +2152,7 @@ int32_t iis2dlpc_act_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dlpc_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dlpc_wake_up_dur_t reg; int32_t ret; @@ -2172,7 +2176,7 @@ int32_t iis2dlpc_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dlpc_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dlpc_wake_up_dur_t reg; int32_t ret; @@ -2204,7 +2208,7 @@ int32_t iis2dlpc_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dlpc_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dlpc_tap_ths_x_t reg; int32_t ret; @@ -2228,7 +2232,7 @@ int32_t iis2dlpc_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dlpc_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dlpc_tap_ths_x_t reg; int32_t ret; @@ -2247,7 +2251,7 @@ int32_t iis2dlpc_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dlpc_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dlpc_tap_ths_y_t reg; int32_t ret; @@ -2271,7 +2275,7 @@ int32_t iis2dlpc_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dlpc_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dlpc_tap_ths_y_t reg; int32_t ret; @@ -2290,7 +2294,7 @@ int32_t iis2dlpc_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_tap_axis_priority_set(const stmdev_ctx_t *ctx, iis2dlpc_tap_prior_t val) { iis2dlpc_tap_ths_y_t reg; @@ -2315,7 +2319,7 @@ int32_t iis2dlpc_tap_axis_priority_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_tap_axis_priority_get(const stmdev_ctx_t *ctx, iis2dlpc_tap_prior_t *val) { iis2dlpc_tap_ths_y_t reg; @@ -2365,7 +2369,7 @@ int32_t iis2dlpc_tap_axis_priority_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dlpc_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dlpc_tap_ths_z_t reg; int32_t ret; @@ -2389,7 +2393,7 @@ int32_t iis2dlpc_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dlpc_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dlpc_tap_ths_z_t reg; int32_t ret; @@ -2408,7 +2412,7 @@ int32_t iis2dlpc_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dlpc_tap_ths_z_t reg; @@ -2433,7 +2437,7 @@ int32_t iis2dlpc_tap_detection_on_z_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dlpc_tap_ths_z_t reg; @@ -2453,7 +2457,7 @@ int32_t iis2dlpc_tap_detection_on_z_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dlpc_tap_ths_z_t reg; @@ -2478,7 +2482,7 @@ int32_t iis2dlpc_tap_detection_on_y_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dlpc_tap_ths_z_t reg; @@ -2498,7 +2502,7 @@ int32_t iis2dlpc_tap_detection_on_y_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dlpc_tap_ths_z_t reg; @@ -2523,7 +2527,7 @@ int32_t iis2dlpc_tap_detection_on_x_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dlpc_tap_ths_z_t reg; @@ -2547,7 +2551,7 @@ int32_t iis2dlpc_tap_detection_on_x_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dlpc_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dlpc_int_dur_t reg; int32_t ret; @@ -2575,7 +2579,7 @@ int32_t iis2dlpc_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dlpc_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dlpc_int_dur_t reg; int32_t ret; @@ -2598,7 +2602,7 @@ int32_t iis2dlpc_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dlpc_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dlpc_int_dur_t reg; int32_t ret; @@ -2626,7 +2630,7 @@ int32_t iis2dlpc_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dlpc_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dlpc_int_dur_t reg; int32_t ret; @@ -2650,7 +2654,7 @@ int32_t iis2dlpc_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dlpc_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dlpc_int_dur_t reg; int32_t ret; @@ -2679,7 +2683,7 @@ int32_t iis2dlpc_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dlpc_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dlpc_int_dur_t reg; int32_t ret; @@ -2698,7 +2702,7 @@ int32_t iis2dlpc_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_tap_mode_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_tap_mode_set(const stmdev_ctx_t *ctx, iis2dlpc_single_double_tap_t val) { iis2dlpc_wake_up_ths_t reg; @@ -2723,7 +2727,7 @@ int32_t iis2dlpc_tap_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_tap_mode_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_tap_mode_get(const stmdev_ctx_t *ctx, iis2dlpc_single_double_tap_t *val) { iis2dlpc_wake_up_ths_t reg; @@ -2757,7 +2761,7 @@ int32_t iis2dlpc_tap_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_tap_src_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_tap_src_get(const stmdev_ctx_t *ctx, iis2dlpc_tap_src_t *val) { int32_t ret; @@ -2788,7 +2792,7 @@ int32_t iis2dlpc_tap_src_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dlpc_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dlpc_tap_ths_x_t reg; int32_t ret; @@ -2812,7 +2816,7 @@ int32_t iis2dlpc_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dlpc_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dlpc_tap_ths_x_t reg; int32_t ret; @@ -2831,7 +2835,7 @@ int32_t iis2dlpc_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dlpc_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dlpc_tap_ths_x_t reg; int32_t ret; @@ -2855,7 +2859,7 @@ int32_t iis2dlpc_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dlpc_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dlpc_tap_ths_x_t reg; int32_t ret; @@ -2874,7 +2878,7 @@ int32_t iis2dlpc_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_6d_src_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_6d_src_get(const stmdev_ctx_t *ctx, iis2dlpc_sixd_src_t *val) { int32_t ret; @@ -2891,7 +2895,7 @@ int32_t iis2dlpc_6d_src_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_6d_feed_data_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_6d_feed_data_set(const stmdev_ctx_t *ctx, iis2dlpc_lpass_on6d_t val) { iis2dlpc_ctrl7_t reg; @@ -2916,7 +2920,7 @@ int32_t iis2dlpc_6d_feed_data_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_6d_feed_data_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_6d_feed_data_get(const stmdev_ctx_t *ctx, iis2dlpc_lpass_on6d_t *val) { iis2dlpc_ctrl7_t reg; @@ -2964,7 +2968,7 @@ int32_t iis2dlpc_6d_feed_data_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dlpc_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dlpc_wake_up_dur_t wake_up_dur; iis2dlpc_free_fall_t free_fall; @@ -3005,7 +3009,7 @@ int32_t iis2dlpc_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dlpc_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dlpc_wake_up_dur_t wake_up_dur; iis2dlpc_free_fall_t free_fall; @@ -3032,7 +3036,7 @@ int32_t iis2dlpc_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_ff_threshold_set(const stmdev_ctx_t *ctx, iis2dlpc_ff_ths_t val) { iis2dlpc_free_fall_t reg; @@ -3057,7 +3061,7 @@ int32_t iis2dlpc_ff_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_ff_threshold_get(const stmdev_ctx_t *ctx, iis2dlpc_ff_ths_t *val) { iis2dlpc_free_fall_t reg; @@ -3127,7 +3131,7 @@ int32_t iis2dlpc_ff_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2dlpc_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2dlpc_fifo_ctrl_t reg; int32_t ret; @@ -3151,7 +3155,7 @@ int32_t iis2dlpc_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dlpc_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dlpc_fifo_ctrl_t reg; int32_t ret; @@ -3170,7 +3174,7 @@ int32_t iis2dlpc_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_fifo_mode_set(const stmdev_ctx_t *ctx, iis2dlpc_fmode_t val) { iis2dlpc_fifo_ctrl_t reg; @@ -3195,7 +3199,7 @@ int32_t iis2dlpc_fifo_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_fifo_mode_get(const stmdev_ctx_t *ctx, iis2dlpc_fmode_t *val) { iis2dlpc_fifo_ctrl_t reg; @@ -3241,7 +3245,7 @@ int32_t iis2dlpc_fifo_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dlpc_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dlpc_fifo_samples_t reg; int32_t ret; @@ -3259,7 +3263,7 @@ int32_t iis2dlpc_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dlpc_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dlpc_fifo_samples_t reg; int32_t ret; @@ -3277,7 +3281,7 @@ int32_t iis2dlpc_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2dlpc_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2dlpc_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2dlpc_fifo_samples_t reg; int32_t ret; diff --git a/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.h b/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.h index 19cfadfd..f67c6691 100644 --- a/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.h +++ b/sensor/stmemsc/iis2dlpc_STdC/driver/iis2dlpc_reg.h @@ -665,10 +665,10 @@ typedef union * them with a custom implementation. */ -int32_t iis2dlpc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t iis2dlpc_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t iis2dlpc_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t iis2dlpc_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -705,9 +705,9 @@ typedef enum IIS2DLPC_SINGLE_LOW_PWR_LOW_NOISE_2 = 0x19, IIS2DLPC_SINGLE_LOW_LOW_NOISE_PWR_12bit = 0x18, } iis2dlpc_mode_t; -int32_t iis2dlpc_power_mode_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_power_mode_set(const stmdev_ctx_t *ctx, iis2dlpc_mode_t val); -int32_t iis2dlpc_power_mode_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_power_mode_get(const stmdev_ctx_t *ctx, iis2dlpc_mode_t *val); typedef enum @@ -725,13 +725,13 @@ typedef enum IIS2DLPC_XL_SET_SW_TRIG = 0x12, /* Use this only in SINGLE mode */ IIS2DLPC_XL_SET_PIN_TRIG = 0x22, /* Use this only in SINGLE mode */ } iis2dlpc_odr_t; -int32_t iis2dlpc_data_rate_set(stmdev_ctx_t *ctx, iis2dlpc_odr_t val); -int32_t iis2dlpc_data_rate_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_data_rate_set(const stmdev_ctx_t *ctx, iis2dlpc_odr_t val); +int32_t iis2dlpc_data_rate_get(const stmdev_ctx_t *ctx, iis2dlpc_odr_t *val); -int32_t iis2dlpc_block_data_update_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dlpc_block_data_update_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -741,14 +741,14 @@ typedef enum IIS2DLPC_8g = 2, IIS2DLPC_16g = 3, } iis2dlpc_fs_t; -int32_t iis2dlpc_full_scale_set(stmdev_ctx_t *ctx, iis2dlpc_fs_t val); -int32_t iis2dlpc_full_scale_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_full_scale_set(const stmdev_ctx_t *ctx, iis2dlpc_fs_t val); +int32_t iis2dlpc_full_scale_get(const stmdev_ctx_t *ctx, iis2dlpc_fs_t *val); -int32_t iis2dlpc_status_reg_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_status_reg_get(const stmdev_ctx_t *ctx, iis2dlpc_status_t *val); -int32_t iis2dlpc_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dlpc_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -758,43 +758,43 @@ typedef struct iis2dlpc_sixd_src_t sixd_src; iis2dlpc_all_int_src_t all_int_src; } iis2dlpc_all_sources_t; -int32_t iis2dlpc_all_sources_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_all_sources_get(const stmdev_ctx_t *ctx, iis2dlpc_all_sources_t *val); -int32_t iis2dlpc_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t iis2dlpc_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t iis2dlpc_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t iis2dlpc_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t iis2dlpc_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t iis2dlpc_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t iis2dlpc_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t iis2dlpc_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t iis2dlpc_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t iis2dlpc_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t iis2dlpc_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t iis2dlpc_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff); typedef enum { IIS2DLPC_LSb_977ug = 0, IIS2DLPC_LSb_15mg6 = 1, } iis2dlpc_usr_off_w_t; -int32_t iis2dlpc_offset_weight_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_offset_weight_set(const stmdev_ctx_t *ctx, iis2dlpc_usr_off_w_t val); -int32_t iis2dlpc_offset_weight_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_offset_weight_get(const stmdev_ctx_t *ctx, iis2dlpc_usr_off_w_t *val); -int32_t iis2dlpc_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t iis2dlpc_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t iis2dlpc_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t iis2dlpc_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t iis2dlpc_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t iis2dlpc_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dlpc_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dlpc_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dlpc_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dlpc_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dlpc_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dlpc_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dlpc_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dlpc_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dlpc_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dlpc_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dlpc_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -802,17 +802,17 @@ typedef enum IIS2DLPC_XL_ST_POSITIVE = 1, IIS2DLPC_XL_ST_NEGATIVE = 2, } iis2dlpc_st_t; -int32_t iis2dlpc_self_test_set(stmdev_ctx_t *ctx, iis2dlpc_st_t val); -int32_t iis2dlpc_self_test_get(stmdev_ctx_t *ctx, iis2dlpc_st_t *val); +int32_t iis2dlpc_self_test_set(const stmdev_ctx_t *ctx, iis2dlpc_st_t val); +int32_t iis2dlpc_self_test_get(const stmdev_ctx_t *ctx, iis2dlpc_st_t *val); typedef enum { IIS2DLPC_DRDY_LATCHED = 0, IIS2DLPC_DRDY_PULSED = 1, } iis2dlpc_drdy_pulsed_t; -int32_t iis2dlpc_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_data_ready_mode_set(const stmdev_ctx_t *ctx, iis2dlpc_drdy_pulsed_t val); -int32_t iis2dlpc_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_data_ready_mode_get(const stmdev_ctx_t *ctx, iis2dlpc_drdy_pulsed_t *val); typedef enum @@ -821,9 +821,9 @@ typedef enum IIS2DLPC_USER_OFFSET_ON_OUT = 0x01, IIS2DLPC_HIGH_PASS_ON_OUT = 0x10, } iis2dlpc_fds_t; -int32_t iis2dlpc_filter_path_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_filter_path_set(const stmdev_ctx_t *ctx, iis2dlpc_fds_t val); -int32_t iis2dlpc_filter_path_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_filter_path_get(const stmdev_ctx_t *ctx, iis2dlpc_fds_t *val); typedef enum @@ -833,30 +833,30 @@ typedef enum IIS2DLPC_ODR_DIV_10 = 2, IIS2DLPC_ODR_DIV_20 = 3, } iis2dlpc_bw_filt_t; -int32_t iis2dlpc_filter_bandwidth_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_filter_bandwidth_set(const stmdev_ctx_t *ctx, iis2dlpc_bw_filt_t val); -int32_t iis2dlpc_filter_bandwidth_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_filter_bandwidth_get(const stmdev_ctx_t *ctx, iis2dlpc_bw_filt_t *val); -int32_t iis2dlpc_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dlpc_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dlpc_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dlpc_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { IIS2DLPC_SPI_4_WIRE = 0, IIS2DLPC_SPI_3_WIRE = 1, } iis2dlpc_sim_t; -int32_t iis2dlpc_spi_mode_set(stmdev_ctx_t *ctx, iis2dlpc_sim_t val); -int32_t iis2dlpc_spi_mode_get(stmdev_ctx_t *ctx, iis2dlpc_sim_t *val); +int32_t iis2dlpc_spi_mode_set(const stmdev_ctx_t *ctx, iis2dlpc_sim_t val); +int32_t iis2dlpc_spi_mode_get(const stmdev_ctx_t *ctx, iis2dlpc_sim_t *val); typedef enum { IIS2DLPC_I2C_ENABLE = 0, IIS2DLPC_I2C_DISABLE = 1, } iis2dlpc_i2c_disable_t; -int32_t iis2dlpc_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_i2c_interface_set(const stmdev_ctx_t *ctx, iis2dlpc_i2c_disable_t val); -int32_t iis2dlpc_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_i2c_interface_get(const stmdev_ctx_t *ctx, iis2dlpc_i2c_disable_t *val); typedef enum @@ -864,9 +864,9 @@ typedef enum IIS2DLPC_PULL_UP_CONNECT = 0, IIS2DLPC_PULL_UP_DISCONNECT = 1, } iis2dlpc_cs_pu_disc_t; -int32_t iis2dlpc_cs_mode_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_cs_mode_set(const stmdev_ctx_t *ctx, iis2dlpc_cs_pu_disc_t val); -int32_t iis2dlpc_cs_mode_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_cs_mode_get(const stmdev_ctx_t *ctx, iis2dlpc_cs_pu_disc_t *val); typedef enum @@ -874,9 +874,9 @@ typedef enum IIS2DLPC_ACTIVE_HIGH = 0, IIS2DLPC_ACTIVE_LOW = 1, } iis2dlpc_h_lactive_t; -int32_t iis2dlpc_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_pin_polarity_set(const stmdev_ctx_t *ctx, iis2dlpc_h_lactive_t val); -int32_t iis2dlpc_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_pin_polarity_get(const stmdev_ctx_t *ctx, iis2dlpc_h_lactive_t *val); typedef enum @@ -884,9 +884,9 @@ typedef enum IIS2DLPC_INT_PULSED = 0, IIS2DLPC_INT_LATCHED = 1, } iis2dlpc_lir_t; -int32_t iis2dlpc_int_notification_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_int_notification_set(const stmdev_ctx_t *ctx, iis2dlpc_lir_t val); -int32_t iis2dlpc_int_notification_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_int_notification_get(const stmdev_ctx_t *ctx, iis2dlpc_lir_t *val); typedef enum @@ -894,38 +894,38 @@ typedef enum IIS2DLPC_PUSH_PULL = 0, IIS2DLPC_OPEN_DRAIN = 1, } iis2dlpc_pp_od_t; -int32_t iis2dlpc_pin_mode_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_pin_mode_set(const stmdev_ctx_t *ctx, iis2dlpc_pp_od_t val); -int32_t iis2dlpc_pin_mode_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_pin_mode_get(const stmdev_ctx_t *ctx, iis2dlpc_pp_od_t *val); -int32_t iis2dlpc_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_pin_int1_route_set(const stmdev_ctx_t *ctx, iis2dlpc_ctrl4_int1_pad_ctrl_t *val); -int32_t iis2dlpc_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_pin_int1_route_get(const stmdev_ctx_t *ctx, iis2dlpc_ctrl4_int1_pad_ctrl_t *val); -int32_t iis2dlpc_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_pin_int2_route_set(const stmdev_ctx_t *ctx, iis2dlpc_ctrl5_int2_pad_ctrl_t *val); -int32_t iis2dlpc_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_pin_int2_route_get(const stmdev_ctx_t *ctx, iis2dlpc_ctrl5_int2_pad_ctrl_t *val); -int32_t iis2dlpc_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dlpc_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dlpc_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dlpc_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dlpc_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dlpc_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dlpc_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dlpc_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dlpc_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dlpc_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dlpc_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dlpc_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { IIS2DLPC_HP_FEED = 0, IIS2DLPC_USER_OFFSET_FEED = 1, } iis2dlpc_usr_off_on_wu_t; -int32_t iis2dlpc_wkup_feed_data_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_wkup_feed_data_set(const stmdev_ctx_t *ctx, iis2dlpc_usr_off_on_wu_t val); -int32_t iis2dlpc_wkup_feed_data_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_wkup_feed_data_get(const stmdev_ctx_t *ctx, iis2dlpc_usr_off_on_wu_t *val); typedef enum @@ -934,19 +934,19 @@ typedef enum IIS2DLPC_DETECT_ACT_INACT = 1, IIS2DLPC_DETECT_STAT_MOTION = 3, } iis2dlpc_sleep_on_t; -int32_t iis2dlpc_act_mode_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_act_mode_set(const stmdev_ctx_t *ctx, iis2dlpc_sleep_on_t val); -int32_t iis2dlpc_act_mode_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_act_mode_get(const stmdev_ctx_t *ctx, iis2dlpc_sleep_on_t *val); -int32_t iis2dlpc_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dlpc_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dlpc_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dlpc_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dlpc_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dlpc_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dlpc_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dlpc_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dlpc_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dlpc_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dlpc_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dlpc_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -957,58 +957,58 @@ typedef enum IIS2DLPC_YZX = 5, IIS2DLPC_ZXY = 6, } iis2dlpc_tap_prior_t; -int32_t iis2dlpc_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_tap_axis_priority_set(const stmdev_ctx_t *ctx, iis2dlpc_tap_prior_t val); -int32_t iis2dlpc_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_tap_axis_priority_get(const stmdev_ctx_t *ctx, iis2dlpc_tap_prior_t *val); -int32_t iis2dlpc_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dlpc_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dlpc_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dlpc_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dlpc_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dlpc_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dlpc_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dlpc_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dlpc_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dlpc_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dlpc_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dlpc_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dlpc_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dlpc_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dlpc_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dlpc_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dlpc_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dlpc_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dlpc_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dlpc_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dlpc_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dlpc_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { IIS2DLPC_ONLY_SINGLE = 0, IIS2DLPC_BOTH_SINGLE_DOUBLE = 1, } iis2dlpc_single_double_tap_t; -int32_t iis2dlpc_tap_mode_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_tap_mode_set(const stmdev_ctx_t *ctx, iis2dlpc_single_double_tap_t val); -int32_t iis2dlpc_tap_mode_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_tap_mode_get(const stmdev_ctx_t *ctx, iis2dlpc_single_double_tap_t *val); -int32_t iis2dlpc_tap_src_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_tap_src_get(const stmdev_ctx_t *ctx, iis2dlpc_tap_src_t *val); -int32_t iis2dlpc_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dlpc_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dlpc_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dlpc_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dlpc_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dlpc_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dlpc_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dlpc_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dlpc_6d_src_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_6d_src_get(const stmdev_ctx_t *ctx, iis2dlpc_sixd_src_t *val); typedef enum @@ -1016,13 +1016,13 @@ typedef enum IIS2DLPC_ODR_DIV_2_FEED = 0, IIS2DLPC_LPF2_FEED = 1, } iis2dlpc_lpass_on6d_t; -int32_t iis2dlpc_6d_feed_data_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_6d_feed_data_set(const stmdev_ctx_t *ctx, iis2dlpc_lpass_on6d_t val); -int32_t iis2dlpc_6d_feed_data_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_6d_feed_data_get(const stmdev_ctx_t *ctx, iis2dlpc_lpass_on6d_t *val); -int32_t iis2dlpc_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dlpc_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dlpc_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dlpc_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -1035,13 +1035,13 @@ typedef enum IIS2DLPC_FF_TSH_15LSb_FS2g = 6, IIS2DLPC_FF_TSH_16LSb_FS2g = 7, } iis2dlpc_ff_ths_t; -int32_t iis2dlpc_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_ff_threshold_set(const stmdev_ctx_t *ctx, iis2dlpc_ff_ths_t val); -int32_t iis2dlpc_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_ff_threshold_get(const stmdev_ctx_t *ctx, iis2dlpc_ff_ths_t *val); -int32_t iis2dlpc_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2dlpc_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dlpc_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2dlpc_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -1051,16 +1051,16 @@ typedef enum IIS2DLPC_BYPASS_TO_STREAM_MODE = 4, IIS2DLPC_STREAM_MODE = 6, } iis2dlpc_fmode_t; -int32_t iis2dlpc_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t iis2dlpc_fifo_mode_set(const stmdev_ctx_t *ctx, iis2dlpc_fmode_t val); -int32_t iis2dlpc_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t iis2dlpc_fifo_mode_get(const stmdev_ctx_t *ctx, iis2dlpc_fmode_t *val); -int32_t iis2dlpc_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dlpc_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dlpc_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dlpc_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2dlpc_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2dlpc_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); /** * @} diff --git a/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.c b/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.c index 2e393174..8f664bc7 100644 --- a/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.c +++ b/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.c @@ -46,12 +46,14 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak iis2iclx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak iis2iclx_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +69,14 @@ int32_t __weak iis2iclx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak iis2iclx_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak iis2iclx_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -141,7 +145,7 @@ float_t iis2iclx_from_lsb_to_nsec(int32_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_full_scale_set(const stmdev_ctx_t *ctx, iis2iclx_fs_xl_t val) { iis2iclx_ctrl1_xl_t ctrl1_xl; @@ -167,7 +171,7 @@ int32_t iis2iclx_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_full_scale_get(const stmdev_ctx_t *ctx, iis2iclx_fs_xl_t *val) { iis2iclx_ctrl1_xl_t ctrl1_xl; @@ -209,7 +213,7 @@ int32_t iis2iclx_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_data_rate_set(const stmdev_ctx_t *ctx, iis2iclx_odr_xl_t val) { iis2iclx_odr_xl_t odr_xl = val; @@ -518,7 +522,7 @@ int32_t iis2iclx_xl_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_data_rate_get(const stmdev_ctx_t *ctx, iis2iclx_odr_xl_t *val) { iis2iclx_ctrl1_xl_t ctrl1_xl; @@ -576,7 +580,7 @@ int32_t iis2iclx_xl_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -600,7 +604,7 @@ int32_t iis2iclx_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_block_data_update_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_ctrl3_c_t ctrl3_c; @@ -621,7 +625,7 @@ int32_t iis2iclx_block_data_update_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_offset_weight_set(const stmdev_ctx_t *ctx, iis2iclx_usr_off_w_t val) { iis2iclx_ctrl6_c_t ctrl6_c; @@ -647,7 +651,7 @@ int32_t iis2iclx_xl_offset_weight_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_offset_weight_get(const stmdev_ctx_t *ctx, iis2iclx_usr_off_w_t *val) { iis2iclx_ctrl6_c_t ctrl6_c; @@ -683,7 +687,7 @@ int32_t iis2iclx_xl_offset_weight_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_all_sources_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_all_sources_get(const stmdev_ctx_t *ctx, iis2iclx_all_sources_t *val) { int32_t ret; @@ -754,7 +758,7 @@ int32_t iis2iclx_all_sources_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_status_reg_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_status_reg_get(const stmdev_ctx_t *ctx, iis2iclx_status_reg_t *val) { int32_t ret; @@ -772,7 +776,7 @@ int32_t iis2iclx_status_reg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_status_reg_t status_reg; @@ -793,7 +797,7 @@ int32_t iis2iclx_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_status_reg_t status_reg; @@ -816,7 +820,7 @@ int32_t iis2iclx_temp_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis2iclx_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -835,7 +839,7 @@ int32_t iis2iclx_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis2iclx_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -854,7 +858,7 @@ int32_t iis2iclx_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis2iclx_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -873,7 +877,7 @@ int32_t iis2iclx_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis2iclx_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -890,7 +894,7 @@ int32_t iis2iclx_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_ctrl7_xl_t ctrl7_xl; int32_t ret; @@ -914,7 +918,7 @@ int32_t iis2iclx_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_ctrl7_xl_t ctrl7_xl; int32_t ret; @@ -946,7 +950,7 @@ int32_t iis2iclx_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_ctrl10_c_t ctrl10_c; int32_t ret; @@ -971,7 +975,7 @@ int32_t iis2iclx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_ctrl10_c_t ctrl10_c; int32_t ret; @@ -992,7 +996,7 @@ int32_t iis2iclx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_timestamp_raw_get(stmdev_ctx_t *ctx, int32_t *val) +int32_t iis2iclx_timestamp_raw_get(const stmdev_ctx_t *ctx, int32_t *val) { uint8_t buff[4]; int32_t ret; @@ -1028,7 +1032,7 @@ int32_t iis2iclx_timestamp_raw_get(stmdev_ctx_t *ctx, int32_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t iis2iclx_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1049,7 +1053,7 @@ int32_t iis2iclx_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t iis2iclx_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[4]; int32_t ret; @@ -1071,7 +1075,7 @@ int32_t iis2iclx_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis2iclx_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1100,7 +1104,7 @@ int32_t iis2iclx_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_device_conf_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_device_conf_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -1124,7 +1128,7 @@ int32_t iis2iclx_device_conf_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_device_conf_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_device_conf_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -1145,7 +1149,7 @@ int32_t iis2iclx_device_conf_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_internal_freq_fine_t internal_freq_fine; int32_t ret; @@ -1173,7 +1177,7 @@ int32_t iis2iclx_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_internal_freq_fine_t internal_freq_fine; int32_t ret; @@ -1194,7 +1198,7 @@ int32_t iis2iclx_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_mem_bank_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_mem_bank_set(const stmdev_ctx_t *ctx, iis2iclx_reg_access_t val) { iis2iclx_func_cfg_access_t func_cfg_access; @@ -1222,7 +1226,7 @@ int32_t iis2iclx_mem_bank_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_mem_bank_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_mem_bank_get(const stmdev_ctx_t *ctx, iis2iclx_reg_access_t *val) { iis2iclx_func_cfg_access_t func_cfg_access; @@ -1262,7 +1266,7 @@ int32_t iis2iclx_mem_bank_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add, +int32_t iis2iclx_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t add, uint8_t *val) { iis2iclx_page_rw_t page_rw; @@ -1337,7 +1341,7 @@ int32_t iis2iclx_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add, +int32_t iis2iclx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t add, uint8_t *buf, uint8_t len) { iis2iclx_page_rw_t page_rw; @@ -1447,7 +1451,7 @@ int32_t iis2iclx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add, +int32_t iis2iclx_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, uint8_t *val) { iis2iclx_page_rw_t page_rw; @@ -1521,7 +1525,7 @@ int32_t iis2iclx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_data_ready_mode_set(const stmdev_ctx_t *ctx, iis2iclx_dataready_pulsed_t val) { iis2iclx_counter_bdr_reg1_t counter_bdr_reg1; @@ -1549,7 +1553,7 @@ int32_t iis2iclx_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_data_ready_mode_get(const stmdev_ctx_t *ctx, iis2iclx_dataready_pulsed_t *val) { iis2iclx_counter_bdr_reg1_t counter_bdr_reg1; @@ -1584,7 +1588,7 @@ int32_t iis2iclx_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis2iclx_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1601,7 +1605,7 @@ int32_t iis2iclx_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1625,7 +1629,7 @@ int32_t iis2iclx_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1645,7 +1649,7 @@ int32_t iis2iclx_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1670,7 +1674,7 @@ int32_t iis2iclx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1689,7 +1693,7 @@ int32_t iis2iclx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1713,7 +1717,7 @@ int32_t iis2iclx_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1734,7 +1738,7 @@ int32_t iis2iclx_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_self_test_set(const stmdev_ctx_t *ctx, iis2iclx_st_xl_t val) { iis2iclx_ctrl5_c_t ctrl5_c; @@ -1759,7 +1763,7 @@ int32_t iis2iclx_xl_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_self_test_get(const stmdev_ctx_t *ctx, iis2iclx_st_xl_t *val) { iis2iclx_ctrl5_c_t ctrl5_c; @@ -1810,7 +1814,7 @@ int32_t iis2iclx_xl_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_ctrl1_xl_t ctrl1_xl; int32_t ret; @@ -1835,7 +1839,7 @@ int32_t iis2iclx_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_ctrl1_xl_t ctrl1_xl; int32_t ret; @@ -1855,7 +1859,7 @@ int32_t iis2iclx_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_ctrl4_c_t ctrl4_c; @@ -1881,7 +1885,7 @@ int32_t iis2iclx_filter_settling_mask_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_ctrl4_c_t ctrl4_c; @@ -1902,7 +1906,7 @@ int32_t iis2iclx_filter_settling_mask_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, iis2iclx_hp_slope_xl_en_t val) { iis2iclx_ctrl8_xl_t ctrl8_xl; @@ -1931,7 +1935,7 @@ int32_t iis2iclx_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, iis2iclx_hp_slope_xl_en_t *val) { iis2iclx_ctrl8_xl_t ctrl8_xl; @@ -2053,7 +2057,7 @@ int32_t iis2iclx_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -2080,7 +2084,7 @@ int32_t iis2iclx_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -2100,7 +2104,7 @@ int32_t iis2iclx_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, iis2iclx_slope_fds_t val) { iis2iclx_tap_cfg0_t tap_cfg0; @@ -2127,7 +2131,7 @@ int32_t iis2iclx_xl_hp_path_internal_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, iis2iclx_slope_fds_t *val) { iis2iclx_tap_cfg0_t tap_cfg0; @@ -2174,7 +2178,7 @@ int32_t iis2iclx_xl_hp_path_internal_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, iis2iclx_sdo_pu_en_t val) { iis2iclx_pin_ctrl_t pin_ctrl; @@ -2199,7 +2203,7 @@ int32_t iis2iclx_sdo_sa0_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, iis2iclx_sdo_pu_en_t *val) { iis2iclx_pin_ctrl_t pin_ctrl; @@ -2233,7 +2237,7 @@ int32_t iis2iclx_sdo_sa0_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_spi_mode_set(stmdev_ctx_t *ctx, iis2iclx_sim_t val) +int32_t iis2iclx_spi_mode_set(const stmdev_ctx_t *ctx, iis2iclx_sim_t val) { iis2iclx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2257,7 +2261,7 @@ int32_t iis2iclx_spi_mode_set(stmdev_ctx_t *ctx, iis2iclx_sim_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_spi_mode_get(stmdev_ctx_t *ctx, iis2iclx_sim_t *val) +int32_t iis2iclx_spi_mode_get(const stmdev_ctx_t *ctx, iis2iclx_sim_t *val) { iis2iclx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2290,7 +2294,7 @@ int32_t iis2iclx_spi_mode_get(stmdev_ctx_t *ctx, iis2iclx_sim_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_i2c_interface_set(const stmdev_ctx_t *ctx, iis2iclx_i2c_disable_t val) { iis2iclx_ctrl4_c_t ctrl4_c; @@ -2315,7 +2319,7 @@ int32_t iis2iclx_i2c_interface_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_i2c_interface_get(const stmdev_ctx_t *ctx, iis2iclx_i2c_disable_t *val) { iis2iclx_ctrl4_c_t ctrl4_c; @@ -2363,7 +2367,7 @@ int32_t iis2iclx_i2c_interface_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_pin_int1_route_set(const stmdev_ctx_t *ctx, iis2iclx_pin_int1_route_t *val) { iis2iclx_pin_int2_route_t pin_int2_route; @@ -2506,7 +2510,7 @@ int32_t iis2iclx_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_pin_int1_route_get(const stmdev_ctx_t *ctx, iis2iclx_pin_int1_route_t *val) { int32_t ret; @@ -2566,7 +2570,7 @@ int32_t iis2iclx_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_pin_int2_route_set(const stmdev_ctx_t *ctx, iis2iclx_pin_int2_route_t *val) { iis2iclx_pin_int1_route_t pin_int1_route; @@ -2708,7 +2712,7 @@ int32_t iis2iclx_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_pin_int2_route_get(const stmdev_ctx_t *ctx, iis2iclx_pin_int2_route_t *val) { int32_t ret; @@ -2767,7 +2771,7 @@ int32_t iis2iclx_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_pin_mode_set(stmdev_ctx_t *ctx, iis2iclx_pp_od_t val) +int32_t iis2iclx_pin_mode_set(const stmdev_ctx_t *ctx, iis2iclx_pp_od_t val) { iis2iclx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2791,7 +2795,7 @@ int32_t iis2iclx_pin_mode_set(stmdev_ctx_t *ctx, iis2iclx_pp_od_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_pin_mode_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_pin_mode_get(const stmdev_ctx_t *ctx, iis2iclx_pp_od_t *val) { iis2iclx_ctrl3_c_t ctrl3_c; @@ -2825,7 +2829,7 @@ int32_t iis2iclx_pin_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_pin_polarity_set(const stmdev_ctx_t *ctx, iis2iclx_h_lactive_t val) { iis2iclx_ctrl3_c_t ctrl3_c; @@ -2850,7 +2854,7 @@ int32_t iis2iclx_pin_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_pin_polarity_get(const stmdev_ctx_t *ctx, iis2iclx_h_lactive_t *val) { iis2iclx_ctrl3_c_t ctrl3_c; @@ -2884,7 +2888,7 @@ int32_t iis2iclx_pin_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_ctrl4_c_t ctrl4_c; int32_t ret; @@ -2908,7 +2912,7 @@ int32_t iis2iclx_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_ctrl4_c_t ctrl4_c; int32_t ret; @@ -2927,7 +2931,7 @@ int32_t iis2iclx_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_int_notification_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_int_notification_set(const stmdev_ctx_t *ctx, iis2iclx_lir_t val) { iis2iclx_tap_cfg0_t tap_cfg0; @@ -2976,7 +2980,7 @@ int32_t iis2iclx_int_notification_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_int_notification_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_int_notification_get(const stmdev_ctx_t *ctx, iis2iclx_lir_t *val) { iis2iclx_tap_cfg0_t tap_cfg0; @@ -3050,7 +3054,7 @@ int32_t iis2iclx_int_notification_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_wkup_ths_weight_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_wkup_ths_weight_set(const stmdev_ctx_t *ctx, iis2iclx_wake_ths_w_t val) { iis2iclx_wake_up_dur_t wake_up_dur; @@ -3079,7 +3083,7 @@ int32_t iis2iclx_wkup_ths_weight_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_wkup_ths_weight_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_wkup_ths_weight_get(const stmdev_ctx_t *ctx, iis2iclx_wake_ths_w_t *val) { iis2iclx_wake_up_dur_t wake_up_dur; @@ -3115,7 +3119,7 @@ int32_t iis2iclx_wkup_ths_weight_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_wake_up_ths_t wake_up_ths; int32_t ret; @@ -3142,7 +3146,7 @@ int32_t iis2iclx_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_wake_up_ths_t wake_up_ths; int32_t ret; @@ -3162,7 +3166,7 @@ int32_t iis2iclx_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_wake_up_ths_t wake_up_ths; @@ -3189,7 +3193,7 @@ int32_t iis2iclx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_wake_up_ths_t wake_up_ths; @@ -3210,7 +3214,7 @@ int32_t iis2iclx_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_wake_up_dur_t wake_up_dur; int32_t ret; @@ -3236,7 +3240,7 @@ int32_t iis2iclx_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_wake_up_dur_t wake_up_dur; int32_t ret; @@ -3271,7 +3275,7 @@ int32_t iis2iclx_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_act_pin_notification_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_act_pin_notification_set(const stmdev_ctx_t *ctx, iis2iclx_sleep_status_on_int_t val) { iis2iclx_tap_cfg0_t tap_cfg0; @@ -3299,7 +3303,7 @@ int32_t iis2iclx_act_pin_notification_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_act_pin_notification_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_act_pin_notification_get(const stmdev_ctx_t *ctx, iis2iclx_sleep_status_on_int_t *val) { iis2iclx_tap_cfg0_t tap_cfg0; @@ -3333,7 +3337,7 @@ int32_t iis2iclx_act_pin_notification_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_wake_up_dur_t wake_up_dur; int32_t ret; @@ -3359,7 +3363,7 @@ int32_t iis2iclx_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_wake_up_dur_t wake_up_dur; int32_t ret; @@ -3392,7 +3396,7 @@ int32_t iis2iclx_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_tap_cfg0_t tap_cfg0; @@ -3418,7 +3422,7 @@ int32_t iis2iclx_tap_detection_on_y_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_tap_cfg0_t tap_cfg0; @@ -3438,7 +3442,7 @@ int32_t iis2iclx_tap_detection_on_y_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_tap_cfg0_t tap_cfg0; @@ -3464,7 +3468,7 @@ int32_t iis2iclx_tap_detection_on_x_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_tap_cfg0_t tap_cfg0; @@ -3484,7 +3488,7 @@ int32_t iis2iclx_tap_detection_on_x_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_tap_cfg1_t tap_cfg1; int32_t ret; @@ -3509,7 +3513,7 @@ int32_t iis2iclx_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_tap_cfg1_t tap_cfg1; int32_t ret; @@ -3528,7 +3532,7 @@ int32_t iis2iclx_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_tap_axis_priority_set(const stmdev_ctx_t *ctx, iis2iclx_tap_priority_t val) { iis2iclx_tap_cfg1_t tap_cfg1; @@ -3553,7 +3557,7 @@ int32_t iis2iclx_tap_axis_priority_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_tap_axis_priority_get(const stmdev_ctx_t *ctx, iis2iclx_tap_priority_t *val) { iis2iclx_tap_cfg1_t tap_cfg1; @@ -3587,7 +3591,7 @@ int32_t iis2iclx_tap_axis_priority_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_tap_cfg2_t tap_cfg2; int32_t ret; @@ -3612,7 +3616,7 @@ int32_t iis2iclx_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_tap_cfg2_t tap_cfg2; int32_t ret; @@ -3635,7 +3639,7 @@ int32_t iis2iclx_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_int_dur2_t int_dur2; int32_t ret; @@ -3664,7 +3668,7 @@ int32_t iis2iclx_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_int_dur2_t int_dur2; int32_t ret; @@ -3687,7 +3691,7 @@ int32_t iis2iclx_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_int_dur2_t int_dur2; int32_t ret; @@ -3716,7 +3720,7 @@ int32_t iis2iclx_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_int_dur2_t int_dur2; int32_t ret; @@ -3741,7 +3745,7 @@ int32_t iis2iclx_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_int_dur2_t int_dur2; int32_t ret; @@ -3770,7 +3774,7 @@ int32_t iis2iclx_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_int_dur2_t int_dur2; int32_t ret; @@ -3789,7 +3793,7 @@ int32_t iis2iclx_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_tap_mode_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_tap_mode_set(const stmdev_ctx_t *ctx, iis2iclx_single_double_tap_t val) { iis2iclx_wake_up_ths_t wake_up_ths; @@ -3816,7 +3820,7 @@ int32_t iis2iclx_tap_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_tap_mode_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_tap_mode_get(const stmdev_ctx_t *ctx, iis2iclx_single_double_tap_t *val) { iis2iclx_wake_up_ths_t wake_up_ths; @@ -3864,7 +3868,7 @@ int32_t iis2iclx_tap_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t iis2iclx_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val) { iis2iclx_fifo_ctrl1_t fifo_ctrl1; iis2iclx_fifo_ctrl2_t fifo_ctrl2; @@ -3898,7 +3902,7 @@ int32_t iis2iclx_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t iis2iclx_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) { iis2iclx_fifo_ctrl1_t fifo_ctrl1; iis2iclx_fifo_ctrl2_t fifo_ctrl2; @@ -3928,7 +3932,7 @@ int32_t iis2iclx_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_fifo_ctrl2_t fifo_ctrl2; @@ -3955,7 +3959,7 @@ int32_t iis2iclx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_fifo_ctrl2_t fifo_ctrl2; @@ -3977,7 +3981,7 @@ int32_t iis2iclx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -4004,7 +4008,7 @@ int32_t iis2iclx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -4025,7 +4029,7 @@ int32_t iis2iclx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_fifo_xl_batch_set(const stmdev_ctx_t *ctx, iis2iclx_bdr_xl_t val) { iis2iclx_fifo_ctrl3_t fifo_ctrl3; @@ -4053,7 +4057,7 @@ int32_t iis2iclx_fifo_xl_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_fifo_xl_batch_get(const stmdev_ctx_t *ctx, iis2iclx_bdr_xl_t *val) { iis2iclx_fifo_ctrl3_t fifo_ctrl3; @@ -4116,7 +4120,7 @@ int32_t iis2iclx_fifo_xl_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_fifo_mode_set(const stmdev_ctx_t *ctx, iis2iclx_fifo_mode_t val) { iis2iclx_fifo_ctrl4_t fifo_ctrl4; @@ -4143,7 +4147,7 @@ int32_t iis2iclx_fifo_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_fifo_mode_get(const stmdev_ctx_t *ctx, iis2iclx_fifo_mode_t *val) { iis2iclx_fifo_ctrl4_t fifo_ctrl4; @@ -4195,7 +4199,7 @@ int32_t iis2iclx_fifo_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_fifo_temp_batch_set(const stmdev_ctx_t *ctx, iis2iclx_odr_t_batch_t val) { iis2iclx_fifo_ctrl4_t fifo_ctrl4; @@ -4223,7 +4227,7 @@ int32_t iis2iclx_fifo_temp_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_fifo_temp_batch_get(const stmdev_ctx_t *ctx, iis2iclx_odr_t_batch_t *val) { iis2iclx_fifo_ctrl4_t fifo_ctrl4; @@ -4268,7 +4272,7 @@ int32_t iis2iclx_fifo_temp_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, iis2iclx_odr_ts_batch_t val) { iis2iclx_fifo_ctrl4_t fifo_ctrl4; @@ -4298,7 +4302,7 @@ int32_t iis2iclx_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, iis2iclx_odr_ts_batch_t *val) { iis2iclx_fifo_ctrl4_t fifo_ctrl4; @@ -4342,7 +4346,7 @@ int32_t iis2iclx_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_counter_bdr_reg1_t counter_bdr_reg1; int32_t ret; @@ -4369,7 +4373,7 @@ int32_t iis2iclx_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_rst_batch_counter_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_counter_bdr_reg1_t counter_bdr_reg1; @@ -4391,7 +4395,7 @@ int32_t iis2iclx_rst_batch_counter_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_batch_counter_threshold_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { iis2iclx_counter_bdr_reg2_t counter_bdr_reg1; @@ -4427,7 +4431,7 @@ int32_t iis2iclx_batch_counter_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { iis2iclx_counter_bdr_reg1_t counter_bdr_reg1; @@ -4458,7 +4462,7 @@ int32_t iis2iclx_batch_counter_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t iis2iclx_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) { iis2iclx_fifo_status1_t fifo_status1; iis2iclx_fifo_status2_t fifo_status2; @@ -4487,7 +4491,7 @@ int32_t iis2iclx_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fifo_status_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_fifo_status_get(const stmdev_ctx_t *ctx, iis2iclx_fifo_status2_t *val) { int32_t ret; @@ -4505,7 +4509,7 @@ int32_t iis2iclx_fifo_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_fifo_status2_t fifo_status2; int32_t ret; @@ -4526,7 +4530,7 @@ int32_t iis2iclx_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_fifo_status2_t fifo_status2; int32_t ret; @@ -4546,7 +4550,7 @@ int32_t iis2iclx_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_fifo_status2_t fifo_status2; int32_t ret; @@ -4566,7 +4570,7 @@ int32_t iis2iclx_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fifo_sensor_tag_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, iis2iclx_fifo_tag_t *val) { iis2iclx_fifo_data_out_tag_t fifo_data_out_tag; @@ -4629,7 +4633,7 @@ int32_t iis2iclx_fifo_sensor_tag_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_slv0_config_t slv0_config; int32_t ret; @@ -4666,7 +4670,7 @@ int32_t iis2iclx_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_slv0_config_t slv0_config; int32_t ret; @@ -4697,7 +4701,7 @@ int32_t iis2iclx_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_slv1_config_t slv1_config; int32_t ret; @@ -4734,7 +4738,7 @@ int32_t iis2iclx_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_slv1_config_t slv1_config; int32_t ret; @@ -4765,7 +4769,7 @@ int32_t iis2iclx_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_slv2_config_t slv2_config; int32_t ret; @@ -4802,7 +4806,7 @@ int32_t iis2iclx_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_slv2_config_t slv2_config; int32_t ret; @@ -4833,7 +4837,7 @@ int32_t iis2iclx_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_slv3_config_t slv3_config; int32_t ret; @@ -4870,7 +4874,7 @@ int32_t iis2iclx_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_slv3_config_t slv3_config; int32_t ret; @@ -4913,7 +4917,7 @@ int32_t iis2iclx_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_den_mode_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_den_mode_set(const stmdev_ctx_t *ctx, iis2iclx_den_mode_t val) { iis2iclx_ctrl6_c_t ctrl6_c; @@ -4951,7 +4955,7 @@ int32_t iis2iclx_den_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_den_mode_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_den_mode_get(const stmdev_ctx_t *ctx, iis2iclx_den_mode_t *val) { iis2iclx_ctrl6_c_t ctrl6_c; @@ -5003,7 +5007,7 @@ int32_t iis2iclx_den_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_den_polarity_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_den_polarity_set(const stmdev_ctx_t *ctx, iis2iclx_den_lh_t val) { iis2iclx_ctrl9_xl_t ctrl9_xl; @@ -5029,7 +5033,7 @@ int32_t iis2iclx_den_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_den_polarity_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_den_polarity_get(const stmdev_ctx_t *ctx, iis2iclx_den_lh_t *val) { iis2iclx_ctrl9_xl_t ctrl9_xl; @@ -5063,7 +5067,7 @@ int32_t iis2iclx_den_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -5088,7 +5092,7 @@ int32_t iis2iclx_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -5107,7 +5111,7 @@ int32_t iis2iclx_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -5131,7 +5135,7 @@ int32_t iis2iclx_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -5164,7 +5168,7 @@ int32_t iis2iclx_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_emb_func_status_t emb_func_status; @@ -5195,7 +5199,7 @@ int32_t iis2iclx_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; @@ -5231,7 +5235,7 @@ int32_t iis2iclx_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -5267,7 +5271,7 @@ int32_t iis2iclx_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fsm_enable_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_fsm_enable_set(const stmdev_ctx_t *ctx, iis2iclx_emb_fsm_enable_t *val) { iis2iclx_emb_func_en_b_t emb_func_en_b; @@ -5343,7 +5347,7 @@ int32_t iis2iclx_fsm_enable_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fsm_enable_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_fsm_enable_get(const stmdev_ctx_t *ctx, iis2iclx_emb_fsm_enable_t *val) { int32_t ret; @@ -5379,7 +5383,7 @@ int32_t iis2iclx_fsm_enable_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t iis2iclx_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -5410,7 +5414,7 @@ int32_t iis2iclx_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t iis2iclx_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -5441,7 +5445,7 @@ int32_t iis2iclx_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_long_clr_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_long_clr_set(const stmdev_ctx_t *ctx, iis2iclx_fsm_lc_clr_t val) { iis2iclx_fsm_long_counter_clear_t fsm_long_counter_clear; @@ -5478,7 +5482,7 @@ int32_t iis2iclx_long_clr_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_long_clr_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_long_clr_get(const stmdev_ctx_t *ctx, iis2iclx_fsm_lc_clr_t *val) { iis2iclx_fsm_long_counter_clear_t fsm_long_counter_clear; @@ -5527,7 +5531,7 @@ int32_t iis2iclx_long_clr_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fsm_out_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_fsm_out_get(const stmdev_ctx_t *ctx, iis2iclx_fsm_out_t *val) { int32_t ret; @@ -5556,7 +5560,7 @@ int32_t iis2iclx_fsm_out_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fsm_data_rate_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_fsm_data_rate_set(const stmdev_ctx_t *ctx, iis2iclx_fsm_odr_t val) { iis2iclx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; @@ -5595,7 +5599,7 @@ int32_t iis2iclx_fsm_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fsm_data_rate_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_fsm_data_rate_get(const stmdev_ctx_t *ctx, iis2iclx_fsm_odr_t *val) { iis2iclx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; @@ -5648,7 +5652,7 @@ int32_t iis2iclx_fsm_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_emb_func_init_b_t emb_func_init_b; int32_t ret; @@ -5684,7 +5688,7 @@ int32_t iis2iclx_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_emb_func_init_b_t emb_func_init_b; int32_t ret; @@ -5717,7 +5721,7 @@ int32_t iis2iclx_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_long_cnt_int_value_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; @@ -5748,7 +5752,7 @@ int32_t iis2iclx_long_cnt_int_value_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_long_cnt_int_value_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -5776,7 +5780,7 @@ int32_t iis2iclx_long_cnt_int_value_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fsm_number_of_programs_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -5800,7 +5804,7 @@ int32_t iis2iclx_fsm_number_of_programs_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fsm_number_of_programs_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -5819,7 +5823,7 @@ int32_t iis2iclx_fsm_number_of_programs_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fsm_start_address_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; @@ -5848,7 +5852,7 @@ int32_t iis2iclx_fsm_start_address_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_fsm_start_address_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -5890,7 +5894,7 @@ int32_t iis2iclx_fsm_start_address_get(stmdev_ctx_t *ctx, * in EMB_FUNC_INIT_B * */ -int32_t iis2iclx_mlc_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_mlc_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_emb_func_en_b_t reg; int32_t ret; @@ -5937,7 +5941,7 @@ int32_t iis2iclx_mlc_set(stmdev_ctx_t *ctx, uint8_t val) * reg EMB_FUNC_EN_B * */ -int32_t iis2iclx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_emb_func_en_b_t reg; int32_t ret; @@ -5965,7 +5969,7 @@ int32_t iis2iclx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val) * @param val register MLC_STATUS_MAINPAGE * */ -int32_t iis2iclx_mlc_status_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_mlc_status_get(const stmdev_ctx_t *ctx, iis2iclx_mlc_status_mainpage_t *val) { return iis2iclx_read_reg(ctx, IIS2ICLX_MLC_STATUS_MAINPAGE, @@ -5980,7 +5984,7 @@ int32_t iis2iclx_mlc_status_get(stmdev_ctx_t *ctx, * reg EMB_FUNC_ODR_CFG_C * */ -int32_t iis2iclx_mlc_data_rate_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_mlc_data_rate_set(const stmdev_ctx_t *ctx, iis2iclx_mlc_odr_t val) { iis2iclx_emb_func_odr_cfg_c_t reg; @@ -6017,7 +6021,7 @@ int32_t iis2iclx_mlc_data_rate_set(stmdev_ctx_t *ctx, * reg EMB_FUNC_ODR_CFG_C * */ -int32_t iis2iclx_mlc_data_rate_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_mlc_data_rate_get(const stmdev_ctx_t *ctx, iis2iclx_mlc_odr_t *val) { iis2iclx_emb_func_odr_cfg_c_t reg; @@ -6069,7 +6073,7 @@ int32_t iis2iclx_mlc_data_rate_get(stmdev_ctx_t *ctx, * @param uint8_t * : buffer that stores data read * */ -int32_t iis2iclx_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis2iclx_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -6109,17 +6113,23 @@ int32_t iis2iclx_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_read_data_raw_get(stmdev_ctx_t *ctx, - iis2iclx_emb_sh_read_t *val) +int32_t iis2iclx_sh_read_data_raw_get(const stmdev_ctx_t *ctx, + iis2iclx_emb_sh_read_t *val, uint16_t len) { int32_t ret; + /* Check on registers SENSOR_HUB_X range */ + if (len > 18) + { + ret = -22; /* -EINVAL */ + goto exit; + } + ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK); if (ret == 0) { - ret = iis2iclx_read_reg(ctx, IIS2ICLX_SENSOR_HUB_1, (uint8_t *)val, - 18); + ret = iis2iclx_read_reg(ctx, IIS2ICLX_SENSOR_HUB_1, (uint8_t *)val, len); } if (ret == 0) @@ -6127,6 +6137,7 @@ int32_t iis2iclx_sh_read_data_raw_get(stmdev_ctx_t *ctx, ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK); } +exit: return ret; } @@ -6138,7 +6149,7 @@ int32_t iis2iclx_sh_read_data_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_slave_connected_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_slave_connected_set(const stmdev_ctx_t *ctx, iis2iclx_aux_sens_on_t val) { iis2iclx_master_config_t master_config; @@ -6175,7 +6186,7 @@ int32_t iis2iclx_sh_slave_connected_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_slave_connected_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_slave_connected_get(const stmdev_ctx_t *ctx, iis2iclx_aux_sens_on_t *val) { iis2iclx_master_config_t master_config; @@ -6228,7 +6239,7 @@ int32_t iis2iclx_sh_slave_connected_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_master_config_t master_config; int32_t ret; @@ -6264,7 +6275,7 @@ int32_t iis2iclx_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_master_config_t master_config; int32_t ret; @@ -6294,7 +6305,7 @@ int32_t iis2iclx_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_pin_mode_set(const stmdev_ctx_t *ctx, iis2iclx_shub_pu_en_t val) { iis2iclx_master_config_t master_config; @@ -6331,7 +6342,7 @@ int32_t iis2iclx_sh_pin_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_pin_mode_get(const stmdev_ctx_t *ctx, iis2iclx_shub_pu_en_t *val) { iis2iclx_master_config_t master_config; @@ -6376,7 +6387,7 @@ int32_t iis2iclx_sh_pin_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2iclx_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2iclx_master_config_t master_config; int32_t ret; @@ -6412,7 +6423,7 @@ int32_t iis2iclx_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_master_config_t master_config; int32_t ret; @@ -6442,7 +6453,7 @@ int32_t iis2iclx_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_syncro_mode_set(const stmdev_ctx_t *ctx, iis2iclx_start_config_t val) { iis2iclx_master_config_t master_config; @@ -6479,7 +6490,7 @@ int32_t iis2iclx_sh_syncro_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_syncro_mode_get(const stmdev_ctx_t *ctx, iis2iclx_start_config_t *val) { iis2iclx_master_config_t master_config; @@ -6525,7 +6536,7 @@ int32_t iis2iclx_sh_syncro_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_write_mode_set(const stmdev_ctx_t *ctx, iis2iclx_write_once_t val) { iis2iclx_master_config_t master_config; @@ -6563,7 +6574,7 @@ int32_t iis2iclx_sh_write_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_write_mode_get(const stmdev_ctx_t *ctx, iis2iclx_write_once_t *val) { iis2iclx_master_config_t master_config; @@ -6607,7 +6618,7 @@ int32_t iis2iclx_sh_write_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_reset_set(stmdev_ctx_t *ctx) +int32_t iis2iclx_sh_reset_set(const stmdev_ctx_t *ctx) { iis2iclx_master_config_t master_config; int32_t ret; @@ -6650,7 +6661,7 @@ int32_t iis2iclx_sh_reset_set(stmdev_ctx_t *ctx) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2iclx_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2iclx_master_config_t master_config; int32_t ret; @@ -6680,7 +6691,7 @@ int32_t iis2iclx_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_data_rate_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_data_rate_set(const stmdev_ctx_t *ctx, iis2iclx_shub_odr_t val) { iis2iclx_slv0_config_t slv0_config; @@ -6717,7 +6728,7 @@ int32_t iis2iclx_sh_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_data_rate_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_data_rate_get(const stmdev_ctx_t *ctx, iis2iclx_shub_odr_t *val) { iis2iclx_slv0_config_t slv0_config; @@ -6773,7 +6784,7 @@ int32_t iis2iclx_sh_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_cfg_write(const stmdev_ctx_t *ctx, iis2iclx_sh_cfg_write_t *val) { iis2iclx_slv0_add_t slv0_add; @@ -6783,7 +6794,7 @@ int32_t iis2iclx_sh_cfg_write(stmdev_ctx_t *ctx, if (ret == 0) { - slv0_add.slave0 = (uint8_t)(val->slv0_add >> 1); + slv0_add.slave0 = (uint8_t)val->slv0_add; slv0_add.rw_0 = 0; ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV0_ADD, (uint8_t *) & (slv0_add), 1); @@ -6820,7 +6831,7 @@ int32_t iis2iclx_sh_cfg_write(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_slv0_cfg_read(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, iis2iclx_sh_cfg_read_t *val) { iis2iclx_slv0_config_t slv0_config; @@ -6833,8 +6844,9 @@ int32_t iis2iclx_sh_slv0_cfg_read(stmdev_ctx_t *ctx, { slv0_add.slave0 = (uint8_t) val->slv_add >> 1; slv0_add.rw_0 = 1; + ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV0_ADD, - (uint8_t *) & (slv0_add), 1); + (uint8_t*)&slv0_add, 1); } if (ret == 0) @@ -6875,7 +6887,7 @@ int32_t iis2iclx_sh_slv0_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_slv1_cfg_read(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, iis2iclx_sh_cfg_read_t *val) { iis2iclx_slv1_config_t slv1_config; @@ -6929,7 +6941,7 @@ int32_t iis2iclx_sh_slv1_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_slv2_cfg_read(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, iis2iclx_sh_cfg_read_t *val) { iis2iclx_slv2_config_t slv2_config; @@ -6984,7 +6996,7 @@ int32_t iis2iclx_sh_slv2_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_slv3_cfg_read(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, iis2iclx_sh_cfg_read_t *val) { iis2iclx_slv3_config_t slv3_config; @@ -7036,7 +7048,7 @@ int32_t iis2iclx_sh_slv3_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis2iclx_sh_status_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_status_get(const stmdev_ctx_t *ctx, iis2iclx_status_master_t *val) { int32_t ret; @@ -7056,7 +7068,7 @@ int32_t iis2iclx_sh_status_get(stmdev_ctx_t *ctx, return ret; } -int32_t iis2iclx_bus_mode_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_bus_mode_set(const stmdev_ctx_t *ctx, iis2iclx_bus_mode_t val) { iis2iclx_ctrl9_xl_t ctrl9_xl; @@ -7097,7 +7109,7 @@ int32_t iis2iclx_bus_mode_set(stmdev_ctx_t *ctx, return ret; } -int32_t iis2iclx_bus_mode_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_bus_mode_get(const stmdev_ctx_t *ctx, iis2iclx_bus_mode_t *val) { iis2iclx_ctrl3_c_t ctrl3_c; diff --git a/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.h b/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.h index 9bbcbb6c..81f167ff 100644 --- a/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.h +++ b/sensor/stmemsc/iis2iclx_STdC/driver/iis2iclx_reg.h @@ -2471,10 +2471,10 @@ typedef union * them with a custom implementation. */ -int32_t iis2iclx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t iis2iclx_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t iis2iclx_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t iis2iclx_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -2494,9 +2494,9 @@ typedef enum IIS2ICLX_1g = 2, IIS2ICLX_2g = 3, } iis2iclx_fs_xl_t; -int32_t iis2iclx_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_full_scale_set(const stmdev_ctx_t *ctx, iis2iclx_fs_xl_t val); -int32_t iis2iclx_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_full_scale_get(const stmdev_ctx_t *ctx, iis2iclx_fs_xl_t *val); typedef enum @@ -2510,14 +2510,14 @@ typedef enum IIS2ICLX_XL_ODR_416Hz = 6, IIS2ICLX_XL_ODR_833Hz = 7, } iis2iclx_odr_xl_t; -int32_t iis2iclx_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_data_rate_set(const stmdev_ctx_t *ctx, iis2iclx_odr_xl_t val); -int32_t iis2iclx_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_data_rate_get(const stmdev_ctx_t *ctx, iis2iclx_odr_xl_t *val); -int32_t iis2iclx_block_data_update_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_block_data_update_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2525,9 +2525,9 @@ typedef enum IIS2ICLX_LSb_1mg = 0, IIS2ICLX_LSb_16mg = 1, } iis2iclx_usr_off_w_t; -int32_t iis2iclx_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_offset_weight_set(const stmdev_ctx_t *ctx, iis2iclx_usr_off_w_t val); -int32_t iis2iclx_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_offset_weight_get(const stmdev_ctx_t *ctx, iis2iclx_usr_off_w_t *val); typedef enum @@ -2535,9 +2535,9 @@ typedef enum IIS2ICLX_HIGH_PERFORMANCE_MD = 0, IIS2ICLX_LOW_NORMAL_POWER_MD = 1, } iis2iclx_xl_hm_mode_t; -int32_t iis2iclx_xl_power_mode_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_power_mode_set(const stmdev_ctx_t *ctx, iis2iclx_xl_hm_mode_t val); -int32_t iis2iclx_xl_power_mode_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_power_mode_get(const stmdev_ctx_t *ctx, iis2iclx_xl_hm_mode_t *val); typedef enum @@ -2545,9 +2545,9 @@ typedef enum IIS2ICLX_GY_HIGH_PERFORMANCE = 0, IIS2ICLX_GY_NORMAL = 1, } iis2iclx_g_hm_mode_t; -int32_t iis2iclx_gy_power_mode_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_gy_power_mode_set(const stmdev_ctx_t *ctx, iis2iclx_g_hm_mode_t val); -int32_t iis2iclx_gy_power_mode_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_gy_power_mode_get(const stmdev_ctx_t *ctx, iis2iclx_g_hm_mode_t *val); typedef struct @@ -2561,48 +2561,48 @@ typedef struct iis2iclx_fsm_status_a_t fsm_status_a; iis2iclx_fsm_status_b_t fsm_status_b; } iis2iclx_all_sources_t; -int32_t iis2iclx_all_sources_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_all_sources_get(const stmdev_ctx_t *ctx, iis2iclx_all_sources_t *val); -int32_t iis2iclx_status_reg_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_status_reg_get(const stmdev_ctx_t *ctx, iis2iclx_status_reg_t *val); -int32_t iis2iclx_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_xl_usr_offset_x_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t iis2iclx_xl_usr_offset_x_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t iis2iclx_xl_usr_offset_y_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t iis2iclx_xl_usr_offset_y_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t iis2iclx_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_timestamp_raw_get(stmdev_ctx_t *ctx, int32_t *val); +int32_t iis2iclx_timestamp_raw_get(const stmdev_ctx_t *ctx, int32_t *val); -int32_t iis2iclx_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t iis2iclx_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t iis2iclx_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t iis2iclx_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t iis2iclx_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t iis2iclx_device_conf_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_device_conf_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_device_conf_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_device_conf_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2610,18 +2610,18 @@ typedef enum IIS2ICLX_SENSOR_HUB_BANK = 1, IIS2ICLX_EMBEDDED_FUNC_BANK = 2, } iis2iclx_reg_access_t; -int32_t iis2iclx_mem_bank_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_mem_bank_set(const stmdev_ctx_t *ctx, iis2iclx_reg_access_t val); -int32_t iis2iclx_mem_bank_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_mem_bank_get(const stmdev_ctx_t *ctx, iis2iclx_reg_access_t *val); -int32_t iis2iclx_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address, +int32_t iis2iclx_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val); -int32_t iis2iclx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, +int32_t iis2iclx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); -int32_t iis2iclx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add, +int32_t iis2iclx_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, uint8_t *val); -int32_t iis2iclx_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, +int32_t iis2iclx_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val); typedef enum @@ -2629,21 +2629,21 @@ typedef enum IIS2ICLX_DRDY_LATCHED = 0, IIS2ICLX_DRDY_PULSED = 1, } iis2iclx_dataready_pulsed_t; -int32_t iis2iclx_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_data_ready_mode_set(const stmdev_ctx_t *ctx, iis2iclx_dataready_pulsed_t val); -int32_t iis2iclx_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_data_ready_mode_get(const stmdev_ctx_t *ctx, iis2iclx_dataready_pulsed_t *val); -int32_t iis2iclx_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t iis2iclx_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t iis2iclx_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2651,17 +2651,17 @@ typedef enum IIS2ICLX_XL_ST_POSITIVE = 1, IIS2ICLX_XL_ST_NEGATIVE = 2, } iis2iclx_st_xl_t; -int32_t iis2iclx_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_self_test_set(const stmdev_ctx_t *ctx, iis2iclx_st_xl_t val); -int32_t iis2iclx_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_self_test_get(const stmdev_ctx_t *ctx, iis2iclx_st_xl_t *val); -int32_t iis2iclx_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2690,13 +2690,13 @@ typedef enum IIS2ICLX_LP_ODR_DIV_400 = 0x06, IIS2ICLX_LP_ODR_DIV_800 = 0x07, } iis2iclx_hp_slope_xl_en_t; -int32_t iis2iclx_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, iis2iclx_hp_slope_xl_en_t val); -int32_t iis2iclx_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, iis2iclx_hp_slope_xl_en_t *val); -int32_t iis2iclx_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_xl_fast_settling_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2704,9 +2704,9 @@ typedef enum IIS2ICLX_USE_SLOPE = 0, IIS2ICLX_USE_HPF = 1, } iis2iclx_slope_fds_t; -int32_t iis2iclx_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, iis2iclx_slope_fds_t val); -int32_t iis2iclx_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, iis2iclx_slope_fds_t *val); typedef enum @@ -2714,9 +2714,9 @@ typedef enum IIS2ICLX_PULL_UP_DISC = 0, IIS2ICLX_PULL_UP_CONNECT = 1, } iis2iclx_sdo_pu_en_t; -int32_t iis2iclx_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, iis2iclx_sdo_pu_en_t val); -int32_t iis2iclx_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, iis2iclx_sdo_pu_en_t *val); typedef enum @@ -2724,17 +2724,17 @@ typedef enum IIS2ICLX_SPI_4_WIRE = 0, IIS2ICLX_SPI_3_WIRE = 1, } iis2iclx_sim_t; -int32_t iis2iclx_spi_mode_set(stmdev_ctx_t *ctx, iis2iclx_sim_t val); -int32_t iis2iclx_spi_mode_get(stmdev_ctx_t *ctx, iis2iclx_sim_t *val); +int32_t iis2iclx_spi_mode_set(const stmdev_ctx_t *ctx, iis2iclx_sim_t val); +int32_t iis2iclx_spi_mode_get(const stmdev_ctx_t *ctx, iis2iclx_sim_t *val); typedef enum { IIS2ICLX_I2C_ENABLE = 0, IIS2ICLX_I2C_DISABLE = 1, } iis2iclx_i2c_disable_t; -int32_t iis2iclx_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_i2c_interface_set(const stmdev_ctx_t *ctx, iis2iclx_i2c_disable_t val); -int32_t iis2iclx_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_i2c_interface_get(const stmdev_ctx_t *ctx, iis2iclx_i2c_disable_t *val); typedef struct @@ -2746,9 +2746,9 @@ typedef struct iis2iclx_fsm_int1_b_t fsm_int1_b; iis2iclx_mlc_int1_t mlc_int1; } iis2iclx_pin_int1_route_t; -int32_t iis2iclx_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_pin_int1_route_set(const stmdev_ctx_t *ctx, iis2iclx_pin_int1_route_t *val); -int32_t iis2iclx_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_pin_int1_route_get(const stmdev_ctx_t *ctx, iis2iclx_pin_int1_route_t *val); typedef struct @@ -2760,9 +2760,9 @@ typedef struct iis2iclx_fsm_int2_b_t fsm_int2_b; iis2iclx_mlc_int2_t mlc_int2; } iis2iclx_pin_int2_route_t; -int32_t iis2iclx_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_pin_int2_route_set(const stmdev_ctx_t *ctx, iis2iclx_pin_int2_route_t *val); -int32_t iis2iclx_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_pin_int2_route_get(const stmdev_ctx_t *ctx, iis2iclx_pin_int2_route_t *val); typedef enum @@ -2770,9 +2770,9 @@ typedef enum IIS2ICLX_PUSH_PULL = 0, IIS2ICLX_OPEN_DRAIN = 1, } iis2iclx_pp_od_t; -int32_t iis2iclx_pin_mode_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_pin_mode_set(const stmdev_ctx_t *ctx, iis2iclx_pp_od_t val); -int32_t iis2iclx_pin_mode_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_pin_mode_get(const stmdev_ctx_t *ctx, iis2iclx_pp_od_t *val); typedef enum @@ -2780,13 +2780,13 @@ typedef enum IIS2ICLX_ACTIVE_HIGH = 0, IIS2ICLX_ACTIVE_LOW = 1, } iis2iclx_h_lactive_t; -int32_t iis2iclx_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_pin_polarity_set(const stmdev_ctx_t *ctx, iis2iclx_h_lactive_t val); -int32_t iis2iclx_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_pin_polarity_get(const stmdev_ctx_t *ctx, iis2iclx_h_lactive_t *val); -int32_t iis2iclx_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2795,9 +2795,9 @@ typedef enum IIS2ICLX_BASE_PULSED_EMB_LATCHED = 2, IIS2ICLX_ALL_INT_LATCHED = 3, } iis2iclx_lir_t; -int32_t iis2iclx_int_notification_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_int_notification_set(const stmdev_ctx_t *ctx, iis2iclx_lir_t val); -int32_t iis2iclx_int_notification_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_int_notification_get(const stmdev_ctx_t *ctx, iis2iclx_lir_t *val); typedef enum @@ -2805,90 +2805,90 @@ typedef enum IIS2ICLX_LSb_FS_DIV_64 = 0, IIS2ICLX_LSb_FS_DIV_256 = 1, } iis2iclx_wake_ths_w_t; -int32_t iis2iclx_wkup_ths_weight_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_wkup_ths_weight_set(const stmdev_ctx_t *ctx, iis2iclx_wake_ths_w_t val); -int32_t iis2iclx_wkup_ths_weight_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_wkup_ths_weight_get(const stmdev_ctx_t *ctx, iis2iclx_wake_ths_w_t *val); -int32_t iis2iclx_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { IIS2ICLX_DRIVE_SLEEP_CHG_EVENT = 0, IIS2ICLX_DRIVE_SLEEP_STATUS = 1, } iis2iclx_sleep_status_on_int_t; -int32_t iis2iclx_act_pin_notification_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_act_pin_notification_set(const stmdev_ctx_t *ctx, iis2iclx_sleep_status_on_int_t val); -int32_t iis2iclx_act_pin_notification_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_act_pin_notification_get(const stmdev_ctx_t *ctx, iis2iclx_sleep_status_on_int_t *val); -int32_t iis2iclx_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { IIS2ICLX_XY = 0, IIS2ICLX_YX = 1, } iis2iclx_tap_priority_t; -int32_t iis2iclx_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_tap_axis_priority_set(const stmdev_ctx_t *ctx, iis2iclx_tap_priority_t val); -int32_t iis2iclx_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_tap_axis_priority_get(const stmdev_ctx_t *ctx, iis2iclx_tap_priority_t *val); -int32_t iis2iclx_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { IIS2ICLX_ONLY_SINGLE = 0, IIS2ICLX_BOTH_SINGLE_DOUBLE = 1, } iis2iclx_single_double_tap_t; -int32_t iis2iclx_tap_mode_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_tap_mode_set(const stmdev_ctx_t *ctx, iis2iclx_single_double_tap_t val); -int32_t iis2iclx_tap_mode_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_tap_mode_get(const stmdev_ctx_t *ctx, iis2iclx_single_double_tap_t *val); -int32_t iis2iclx_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t iis2iclx_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t iis2iclx_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t iis2iclx_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t iis2iclx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2903,9 +2903,9 @@ typedef enum IIS2ICLX_XL_BATCHED_AT_417Hz = 6, IIS2ICLX_XL_BATCHED_AT_833Hz = 7, } iis2iclx_bdr_xl_t; -int32_t iis2iclx_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_fifo_xl_batch_set(const stmdev_ctx_t *ctx, iis2iclx_bdr_xl_t val); -int32_t iis2iclx_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_fifo_xl_batch_get(const stmdev_ctx_t *ctx, iis2iclx_bdr_xl_t *val); typedef enum @@ -2917,9 +2917,9 @@ typedef enum IIS2ICLX_STREAM_MODE = 6, IIS2ICLX_BYPASS_TO_FIFO_MODE = 7, } iis2iclx_fifo_mode_t; -int32_t iis2iclx_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_fifo_mode_set(const stmdev_ctx_t *ctx, iis2iclx_fifo_mode_t val); -int32_t iis2iclx_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_fifo_mode_get(const stmdev_ctx_t *ctx, iis2iclx_fifo_mode_t *val); typedef enum @@ -2929,9 +2929,9 @@ typedef enum IIS2ICLX_TEMP_BATCHED_AT_12Hz5 = 2, IIS2ICLX_TEMP_BATCHED_AT_52Hz = 3, } iis2iclx_odr_t_batch_t; -int32_t iis2iclx_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_fifo_temp_batch_set(const stmdev_ctx_t *ctx, iis2iclx_odr_t_batch_t val); -int32_t iis2iclx_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_fifo_temp_batch_get(const stmdev_ctx_t *ctx, iis2iclx_odr_t_batch_t *val); typedef enum @@ -2941,32 +2941,32 @@ typedef enum IIS2ICLX_DEC_8 = 2, IIS2ICLX_DEC_32 = 3, } iis2iclx_odr_ts_batch_t; -int32_t iis2iclx_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, iis2iclx_odr_ts_batch_t val); -int32_t iis2iclx_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, iis2iclx_odr_ts_batch_t *val); -int32_t iis2iclx_rst_batch_counter_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_rst_batch_counter_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_batch_counter_threshold_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t iis2iclx_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t iis2iclx_fifo_data_level_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t iis2iclx_fifo_status_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_fifo_status_get(const stmdev_ctx_t *ctx, iis2iclx_fifo_status2_t *val); -int32_t iis2iclx_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2980,23 +2980,23 @@ typedef enum IIS2ICLX_SENSORHUB_SLAVE3_TAG, IIS2ICLX_SENSORHUB_NACK_TAG = 0x19, } iis2iclx_fifo_tag_t; -int32_t iis2iclx_fifo_sensor_tag_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, iis2iclx_fifo_tag_t *val); -int32_t iis2iclx_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_sh_batch_slave_0_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_sh_batch_slave_1_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_sh_batch_slave_2_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_sh_batch_slave_3_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3007,9 +3007,9 @@ typedef enum IIS2ICLX_LEVEL_TRIGGER = 0x72, IIS2ICLX_EDGE_TRIGGER = 0x74, } iis2iclx_den_mode_t; -int32_t iis2iclx_den_mode_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_den_mode_set(const stmdev_ctx_t *ctx, iis2iclx_den_mode_t val); -int32_t iis2iclx_den_mode_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_den_mode_get(const stmdev_ctx_t *ctx, iis2iclx_den_mode_t *val); typedef enum @@ -3017,35 +3017,35 @@ typedef enum IIS2ICLX_DEN_ACT_LOW = 0, IIS2ICLX_DEN_ACT_HIGH = 1, } iis2iclx_den_lh_t; -int32_t iis2iclx_den_polarity_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_den_polarity_set(const stmdev_ctx_t *ctx, iis2iclx_den_lh_t val); -int32_t iis2iclx_den_polarity_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_den_polarity_get(const stmdev_ctx_t *ctx, iis2iclx_den_lh_t *val); -int32_t iis2iclx_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { iis2iclx_fsm_enable_a_t fsm_enable_a; iis2iclx_fsm_enable_b_t fsm_enable_b; } iis2iclx_emb_fsm_enable_t; -int32_t iis2iclx_fsm_enable_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_fsm_enable_set(const stmdev_ctx_t *ctx, iis2iclx_emb_fsm_enable_t *val); -int32_t iis2iclx_fsm_enable_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_fsm_enable_get(const stmdev_ctx_t *ctx, iis2iclx_emb_fsm_enable_t *val); -int32_t iis2iclx_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t iis2iclx_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t iis2iclx_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t iis2iclx_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum { @@ -3053,9 +3053,9 @@ typedef enum IIS2ICLX_LC_CLEAR = 1, IIS2ICLX_LC_CLEAR_DONE = 2, } iis2iclx_fsm_lc_clr_t; -int32_t iis2iclx_long_clr_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_long_clr_set(const stmdev_ctx_t *ctx, iis2iclx_fsm_lc_clr_t val); -int32_t iis2iclx_long_clr_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_long_clr_get(const stmdev_ctx_t *ctx, iis2iclx_fsm_lc_clr_t *val); typedef struct @@ -3077,7 +3077,7 @@ typedef struct iis2iclx_fsm_outs15_t fsm_outs15; iis2iclx_fsm_outs16_t fsm_outs16; } iis2iclx_fsm_out_t; -int32_t iis2iclx_fsm_out_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_fsm_out_get(const stmdev_ctx_t *ctx, iis2iclx_fsm_out_t *val); typedef enum @@ -3087,33 +3087,33 @@ typedef enum IIS2ICLX_ODR_FSM_52Hz = 2, IIS2ICLX_ODR_FSM_104Hz = 3, } iis2iclx_fsm_odr_t; -int32_t iis2iclx_fsm_data_rate_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_fsm_data_rate_set(const stmdev_ctx_t *ctx, iis2iclx_fsm_odr_t val); -int32_t iis2iclx_fsm_data_rate_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_fsm_data_rate_get(const stmdev_ctx_t *ctx, iis2iclx_fsm_odr_t *val); -int32_t iis2iclx_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_long_cnt_int_value_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t iis2iclx_long_cnt_int_value_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t iis2iclx_fsm_number_of_programs_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t iis2iclx_fsm_number_of_programs_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t iis2iclx_fsm_start_address_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t iis2iclx_fsm_start_address_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t iis2iclx_mlc_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_mlc_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2iclx_mlc_status_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_mlc_status_get(const stmdev_ctx_t *ctx, iis2iclx_mlc_status_mainpage_t *val); typedef enum @@ -3123,12 +3123,12 @@ typedef enum IIS2ICLX_ODR_PRGS_52Hz = 2, IIS2ICLX_ODR_PRGS_104Hz = 3, } iis2iclx_mlc_odr_t; -int32_t iis2iclx_mlc_data_rate_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_mlc_data_rate_set(const stmdev_ctx_t *ctx, iis2iclx_mlc_odr_t val); -int32_t iis2iclx_mlc_data_rate_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_mlc_data_rate_get(const stmdev_ctx_t *ctx, iis2iclx_mlc_odr_t *val); -int32_t iis2iclx_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t iis2iclx_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); typedef struct { @@ -3151,8 +3151,8 @@ typedef struct iis2iclx_sensor_hub_17_t sh_byte_17; iis2iclx_sensor_hub_18_t sh_byte_18; } iis2iclx_emb_sh_read_t; -int32_t iis2iclx_sh_read_data_raw_get(stmdev_ctx_t *ctx, - iis2iclx_emb_sh_read_t *val); +int32_t iis2iclx_sh_read_data_raw_get(const stmdev_ctx_t *ctx, + iis2iclx_emb_sh_read_t *val, uint16_t len); typedef enum { @@ -3161,35 +3161,35 @@ typedef enum IIS2ICLX_SLV_0_1_2 = 2, IIS2ICLX_SLV_0_1_2_3 = 3, } iis2iclx_aux_sens_on_t; -int32_t iis2iclx_sh_slave_connected_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_slave_connected_set(const stmdev_ctx_t *ctx, iis2iclx_aux_sens_on_t val); -int32_t iis2iclx_sh_slave_connected_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_slave_connected_get(const stmdev_ctx_t *ctx, iis2iclx_aux_sens_on_t *val); -int32_t iis2iclx_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { IIS2ICLX_EXT_PULL_UP = 0, IIS2ICLX_INTERNAL_PULL_UP = 1, } iis2iclx_shub_pu_en_t; -int32_t iis2iclx_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_pin_mode_set(const stmdev_ctx_t *ctx, iis2iclx_shub_pu_en_t val); -int32_t iis2iclx_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_pin_mode_get(const stmdev_ctx_t *ctx, iis2iclx_shub_pu_en_t *val); -int32_t iis2iclx_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2iclx_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2iclx_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { IIS2ICLX_EXT_ON_INT2_PIN = 1, IIS2ICLX_XL_GY_DRDY = 0, } iis2iclx_start_config_t; -int32_t iis2iclx_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_syncro_mode_set(const stmdev_ctx_t *ctx, iis2iclx_start_config_t val); -int32_t iis2iclx_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_syncro_mode_get(const stmdev_ctx_t *ctx, iis2iclx_start_config_t *val); typedef enum @@ -3197,13 +3197,13 @@ typedef enum IIS2ICLX_EACH_SH_CYCLE = 0, IIS2ICLX_ONLY_FIRST_CYCLE = 1, } iis2iclx_write_once_t; -int32_t iis2iclx_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_write_mode_set(const stmdev_ctx_t *ctx, iis2iclx_write_once_t val); -int32_t iis2iclx_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_write_mode_get(const stmdev_ctx_t *ctx, iis2iclx_write_once_t *val); -int32_t iis2iclx_sh_reset_set(stmdev_ctx_t *ctx); -int32_t iis2iclx_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2iclx_sh_reset_set(const stmdev_ctx_t *ctx); +int32_t iis2iclx_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3212,9 +3212,9 @@ typedef enum IIS2ICLX_SH_ODR_26Hz = 2, IIS2ICLX_SH_ODR_13Hz = 3, } iis2iclx_shub_odr_t; -int32_t iis2iclx_sh_data_rate_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_data_rate_set(const stmdev_ctx_t *ctx, iis2iclx_shub_odr_t val); -int32_t iis2iclx_sh_data_rate_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_data_rate_get(const stmdev_ctx_t *ctx, iis2iclx_shub_odr_t *val); typedef struct @@ -3223,7 +3223,7 @@ typedef struct uint8_t slv0_subadd; uint8_t slv0_data; } iis2iclx_sh_cfg_write_t; -int32_t iis2iclx_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_cfg_write(const stmdev_ctx_t *ctx, iis2iclx_sh_cfg_write_t *val); typedef struct @@ -3232,16 +3232,16 @@ typedef struct uint8_t slv_subadd; uint8_t slv_len; } iis2iclx_sh_cfg_read_t; -int32_t iis2iclx_sh_slv0_cfg_read(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, iis2iclx_sh_cfg_read_t *val); -int32_t iis2iclx_sh_slv1_cfg_read(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, iis2iclx_sh_cfg_read_t *val); -int32_t iis2iclx_sh_slv2_cfg_read(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, iis2iclx_sh_cfg_read_t *val); -int32_t iis2iclx_sh_slv3_cfg_read(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, iis2iclx_sh_cfg_read_t *val); -int32_t iis2iclx_sh_status_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_sh_status_get(const stmdev_ctx_t *ctx, iis2iclx_status_master_t *val); typedef enum @@ -3250,9 +3250,9 @@ typedef enum IIS2ICLX_SPI_4W = 0x01, /* Only SPI: SDO / SDI separated pins */ IIS2ICLX_SPI_3W = 0x03, /* Only SPI: SDO / SDI share the same pin */ } iis2iclx_bus_mode_t; -int32_t iis2iclx_bus_mode_set(stmdev_ctx_t *ctx, +int32_t iis2iclx_bus_mode_set(const stmdev_ctx_t *ctx, iis2iclx_bus_mode_t val); -int32_t iis2iclx_bus_mode_get(stmdev_ctx_t *ctx, +int32_t iis2iclx_bus_mode_get(const stmdev_ctx_t *ctx, iis2iclx_bus_mode_t *val); /** diff --git a/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.c b/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.c index 7110a688..a785c438 100644 --- a/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.c +++ b/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.c @@ -45,12 +45,14 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak iis2mdc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak iis2mdc_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -66,12 +68,14 @@ int32_t __weak iis2mdc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak iis2mdc_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak iis2mdc_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -125,7 +129,7 @@ float_t iis2mdc_from_lsb_to_celsius(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_mag_user_offset_set(stmdev_ctx_t *ctx, int16_t *val) +int32_t iis2mdc_mag_user_offset_set(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -154,7 +158,7 @@ int32_t iis2mdc_mag_user_offset_set(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_mag_user_offset_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t iis2mdc_mag_user_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -178,7 +182,7 @@ int32_t iis2mdc_mag_user_offset_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_operating_mode_set(stmdev_ctx_t *ctx, +int32_t iis2mdc_operating_mode_set(const stmdev_ctx_t *ctx, iis2mdc_md_t val) { iis2mdc_cfg_reg_a_t reg; @@ -203,7 +207,7 @@ int32_t iis2mdc_operating_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_operating_mode_get(stmdev_ctx_t *ctx, +int32_t iis2mdc_operating_mode_get(const stmdev_ctx_t *ctx, iis2mdc_md_t *val) { iis2mdc_cfg_reg_a_t reg; @@ -241,7 +245,7 @@ int32_t iis2mdc_operating_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_data_rate_set(stmdev_ctx_t *ctx, iis2mdc_odr_t val) +int32_t iis2mdc_data_rate_set(const stmdev_ctx_t *ctx, iis2mdc_odr_t val) { iis2mdc_cfg_reg_a_t reg; int32_t ret; @@ -265,7 +269,7 @@ int32_t iis2mdc_data_rate_set(stmdev_ctx_t *ctx, iis2mdc_odr_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_data_rate_get(stmdev_ctx_t *ctx, iis2mdc_odr_t *val) +int32_t iis2mdc_data_rate_get(const stmdev_ctx_t *ctx, iis2mdc_odr_t *val) { iis2mdc_cfg_reg_a_t reg; int32_t ret; @@ -306,7 +310,7 @@ int32_t iis2mdc_data_rate_get(stmdev_ctx_t *ctx, iis2mdc_odr_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_power_mode_set(stmdev_ctx_t *ctx, iis2mdc_lp_t val) +int32_t iis2mdc_power_mode_set(const stmdev_ctx_t *ctx, iis2mdc_lp_t val) { iis2mdc_cfg_reg_a_t reg; int32_t ret; @@ -330,7 +334,7 @@ int32_t iis2mdc_power_mode_set(stmdev_ctx_t *ctx, iis2mdc_lp_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_power_mode_get(stmdev_ctx_t *ctx, iis2mdc_lp_t *val) +int32_t iis2mdc_power_mode_get(const stmdev_ctx_t *ctx, iis2mdc_lp_t *val) { iis2mdc_cfg_reg_a_t reg; int32_t ret; @@ -363,7 +367,7 @@ int32_t iis2mdc_power_mode_get(stmdev_ctx_t *ctx, iis2mdc_lp_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_offset_temp_comp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2mdc_offset_temp_comp_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2mdc_cfg_reg_a_t reg; int32_t ret; @@ -387,7 +391,7 @@ int32_t iis2mdc_offset_temp_comp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_offset_temp_comp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2mdc_offset_temp_comp_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2mdc_cfg_reg_a_t reg; int32_t ret; @@ -406,7 +410,7 @@ int32_t iis2mdc_offset_temp_comp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_low_pass_bandwidth_set(stmdev_ctx_t *ctx, +int32_t iis2mdc_low_pass_bandwidth_set(const stmdev_ctx_t *ctx, iis2mdc_lpf_t val) { iis2mdc_cfg_reg_b_t reg; @@ -431,7 +435,7 @@ int32_t iis2mdc_low_pass_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_low_pass_bandwidth_get(stmdev_ctx_t *ctx, +int32_t iis2mdc_low_pass_bandwidth_get(const stmdev_ctx_t *ctx, iis2mdc_lpf_t *val) { iis2mdc_cfg_reg_b_t reg; @@ -466,7 +470,7 @@ int32_t iis2mdc_low_pass_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_set_rst_mode_set(stmdev_ctx_t *ctx, +int32_t iis2mdc_set_rst_mode_set(const stmdev_ctx_t *ctx, iis2mdc_set_rst_t val) { iis2mdc_cfg_reg_b_t reg; @@ -491,7 +495,7 @@ int32_t iis2mdc_set_rst_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_set_rst_mode_get(stmdev_ctx_t *ctx, +int32_t iis2mdc_set_rst_mode_get(const stmdev_ctx_t *ctx, iis2mdc_set_rst_t *val) { iis2mdc_cfg_reg_b_t reg; @@ -534,7 +538,7 @@ int32_t iis2mdc_set_rst_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_set_rst_sensor_single_set(stmdev_ctx_t *ctx, +int32_t iis2mdc_set_rst_sensor_single_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2mdc_cfg_reg_b_t reg; @@ -563,7 +567,7 @@ int32_t iis2mdc_set_rst_sensor_single_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_set_rst_sensor_single_get(stmdev_ctx_t *ctx, +int32_t iis2mdc_set_rst_sensor_single_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2mdc_cfg_reg_b_t reg; @@ -583,7 +587,7 @@ int32_t iis2mdc_set_rst_sensor_single_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2mdc_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2mdc_cfg_reg_c_t reg; int32_t ret; @@ -607,7 +611,7 @@ int32_t iis2mdc_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2mdc_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2mdc_cfg_reg_c_t reg; int32_t ret; @@ -626,7 +630,7 @@ int32_t iis2mdc_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_mag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2mdc_mag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2mdc_status_reg_t reg; int32_t ret; @@ -645,7 +649,7 @@ int32_t iis2mdc_mag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_mag_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2mdc_mag_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2mdc_status_reg_t reg; int32_t ret; @@ -664,7 +668,7 @@ int32_t iis2mdc_mag_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t iis2mdc_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -688,7 +692,7 @@ int32_t iis2mdc_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t iis2mdc_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -720,7 +724,7 @@ int32_t iis2mdc_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis2mdc_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -738,7 +742,7 @@ int32_t iis2mdc_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2mdc_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2mdc_cfg_reg_a_t reg; int32_t ret; @@ -762,7 +766,7 @@ int32_t iis2mdc_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2mdc_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2mdc_cfg_reg_a_t reg; int32_t ret; @@ -781,7 +785,7 @@ int32_t iis2mdc_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2mdc_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2mdc_cfg_reg_a_t reg; int32_t ret; @@ -805,7 +809,7 @@ int32_t iis2mdc_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2mdc_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2mdc_cfg_reg_a_t reg; int32_t ret; @@ -824,7 +828,7 @@ int32_t iis2mdc_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_self_test_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2mdc_self_test_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2mdc_cfg_reg_c_t reg; int32_t ret; @@ -848,7 +852,7 @@ int32_t iis2mdc_self_test_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_self_test_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2mdc_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2mdc_cfg_reg_c_t reg; int32_t ret; @@ -867,7 +871,7 @@ int32_t iis2mdc_self_test_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_data_format_set(stmdev_ctx_t *ctx, iis2mdc_ble_t val) +int32_t iis2mdc_data_format_set(const stmdev_ctx_t *ctx, iis2mdc_ble_t val) { iis2mdc_cfg_reg_c_t reg; int32_t ret; @@ -891,7 +895,7 @@ int32_t iis2mdc_data_format_set(stmdev_ctx_t *ctx, iis2mdc_ble_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_data_format_get(stmdev_ctx_t *ctx, iis2mdc_ble_t *val) +int32_t iis2mdc_data_format_get(const stmdev_ctx_t *ctx, iis2mdc_ble_t *val) { iis2mdc_cfg_reg_c_t reg; int32_t ret; @@ -924,7 +928,7 @@ int32_t iis2mdc_data_format_get(stmdev_ctx_t *ctx, iis2mdc_ble_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_status_get(stmdev_ctx_t *ctx, +int32_t iis2mdc_status_get(const stmdev_ctx_t *ctx, iis2mdc_status_reg_t *val) { int32_t ret; @@ -957,7 +961,7 @@ int32_t iis2mdc_status_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_offset_int_conf_set(stmdev_ctx_t *ctx, +int32_t iis2mdc_offset_int_conf_set(const stmdev_ctx_t *ctx, iis2mdc_int_on_dataoff_t val) { iis2mdc_cfg_reg_b_t reg; @@ -984,7 +988,7 @@ int32_t iis2mdc_offset_int_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_offset_int_conf_get(stmdev_ctx_t *ctx, +int32_t iis2mdc_offset_int_conf_get(const stmdev_ctx_t *ctx, iis2mdc_int_on_dataoff_t *val) { iis2mdc_cfg_reg_b_t reg; @@ -1018,7 +1022,7 @@ int32_t iis2mdc_offset_int_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_drdy_on_pin_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2mdc_drdy_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2mdc_cfg_reg_c_t reg; int32_t ret; @@ -1042,7 +1046,7 @@ int32_t iis2mdc_drdy_on_pin_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_drdy_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2mdc_drdy_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2mdc_cfg_reg_c_t reg; int32_t ret; @@ -1061,7 +1065,7 @@ int32_t iis2mdc_drdy_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_int_on_pin_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis2mdc_int_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val) { iis2mdc_cfg_reg_c_t reg; int32_t ret; @@ -1085,7 +1089,7 @@ int32_t iis2mdc_int_on_pin_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_int_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis2mdc_int_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis2mdc_cfg_reg_c_t reg; int32_t ret; @@ -1104,7 +1108,7 @@ int32_t iis2mdc_int_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_int_gen_conf_set(stmdev_ctx_t *ctx, +int32_t iis2mdc_int_gen_conf_set(const stmdev_ctx_t *ctx, iis2mdc_int_crtl_reg_t *val) { int32_t ret; @@ -1122,7 +1126,7 @@ int32_t iis2mdc_int_gen_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_int_gen_conf_get(stmdev_ctx_t *ctx, +int32_t iis2mdc_int_gen_conf_get(const stmdev_ctx_t *ctx, iis2mdc_int_crtl_reg_t *val) { int32_t ret; @@ -1140,7 +1144,7 @@ int32_t iis2mdc_int_gen_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_int_gen_source_get(stmdev_ctx_t *ctx, +int32_t iis2mdc_int_gen_source_get(const stmdev_ctx_t *ctx, iis2mdc_int_source_reg_t *val) { int32_t ret; @@ -1160,7 +1164,7 @@ int32_t iis2mdc_int_gen_source_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_int_gen_treshold_set(stmdev_ctx_t *ctx, int16_t val) +int32_t iis2mdc_int_gen_threshold_set(const stmdev_ctx_t *ctx, int16_t val) { uint8_t buff[2]; int32_t ret; @@ -1182,7 +1186,7 @@ int32_t iis2mdc_int_gen_treshold_set(stmdev_ctx_t *ctx, int16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_int_gen_treshold_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t iis2mdc_int_gen_threshold_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1215,7 +1219,7 @@ int32_t iis2mdc_int_gen_treshold_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t iis2mdc_i2c_interface_set(const stmdev_ctx_t *ctx, iis2mdc_i2c_dis_t val) { iis2mdc_cfg_reg_c_t reg; @@ -1240,7 +1244,7 @@ int32_t iis2mdc_i2c_interface_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis2mdc_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t iis2mdc_i2c_interface_get(const stmdev_ctx_t *ctx, iis2mdc_i2c_dis_t *val) { iis2mdc_cfg_reg_c_t reg; diff --git a/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.h b/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.h index 095b5364..30f4b19a 100644 --- a/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.h +++ b/sensor/stmemsc/iis2mdc_STdC/driver/iis2mdc_reg.h @@ -354,27 +354,27 @@ typedef union * The __weak directive allows the final application to overwrite * them with a custom implementation. */ -int32_t iis2mdc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t iis2mdc_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t iis2mdc_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t iis2mdc_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); float_t iis2mdc_from_lsb_to_mgauss(int16_t lsb); float_t iis2mdc_from_lsb_to_celsius(int16_t lsb); -int32_t iis2mdc_mag_user_offset_set(stmdev_ctx_t *ctx, int16_t *val); -int32_t iis2mdc_mag_user_offset_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t iis2mdc_mag_user_offset_set(const stmdev_ctx_t *ctx, int16_t *val); +int32_t iis2mdc_mag_user_offset_get(const stmdev_ctx_t *ctx, int16_t *val); typedef enum { IIS2MDC_CONTINUOUS_MODE = 0, IIS2MDC_SINGLE_TRIGGER = 1, IIS2MDC_POWER_DOWN = 2, } iis2mdc_md_t; -int32_t iis2mdc_operating_mode_set(stmdev_ctx_t *ctx, +int32_t iis2mdc_operating_mode_set(const stmdev_ctx_t *ctx, iis2mdc_md_t val); -int32_t iis2mdc_operating_mode_get(stmdev_ctx_t *ctx, +int32_t iis2mdc_operating_mode_get(const stmdev_ctx_t *ctx, iis2mdc_md_t *val); typedef enum @@ -384,28 +384,28 @@ typedef enum IIS2MDC_ODR_50Hz = 2, IIS2MDC_ODR_100Hz = 3, } iis2mdc_odr_t; -int32_t iis2mdc_data_rate_set(stmdev_ctx_t *ctx, iis2mdc_odr_t val); -int32_t iis2mdc_data_rate_get(stmdev_ctx_t *ctx, iis2mdc_odr_t *val); +int32_t iis2mdc_data_rate_set(const stmdev_ctx_t *ctx, iis2mdc_odr_t val); +int32_t iis2mdc_data_rate_get(const stmdev_ctx_t *ctx, iis2mdc_odr_t *val); typedef enum { IIS2MDC_HIGH_RESOLUTION = 0, IIS2MDC_LOW_POWER = 1, } iis2mdc_lp_t; -int32_t iis2mdc_power_mode_set(stmdev_ctx_t *ctx, iis2mdc_lp_t val); -int32_t iis2mdc_power_mode_get(stmdev_ctx_t *ctx, iis2mdc_lp_t *val); +int32_t iis2mdc_power_mode_set(const stmdev_ctx_t *ctx, iis2mdc_lp_t val); +int32_t iis2mdc_power_mode_get(const stmdev_ctx_t *ctx, iis2mdc_lp_t *val); -int32_t iis2mdc_offset_temp_comp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2mdc_offset_temp_comp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2mdc_offset_temp_comp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2mdc_offset_temp_comp_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { IIS2MDC_ODR_DIV_2 = 0, IIS2MDC_ODR_DIV_4 = 1, } iis2mdc_lpf_t; -int32_t iis2mdc_low_pass_bandwidth_set(stmdev_ctx_t *ctx, +int32_t iis2mdc_low_pass_bandwidth_set(const stmdev_ctx_t *ctx, iis2mdc_lpf_t val); -int32_t iis2mdc_low_pass_bandwidth_get(stmdev_ctx_t *ctx, +int32_t iis2mdc_low_pass_bandwidth_get(const stmdev_ctx_t *ctx, iis2mdc_lpf_t *val); typedef enum @@ -414,49 +414,49 @@ typedef enum IIS2MDC_SENS_OFF_CANC_EVERY_ODR = 1, IIS2MDC_SET_SENS_ONLY_AT_POWER_ON = 2, } iis2mdc_set_rst_t; -int32_t iis2mdc_set_rst_mode_set(stmdev_ctx_t *ctx, +int32_t iis2mdc_set_rst_mode_set(const stmdev_ctx_t *ctx, iis2mdc_set_rst_t val); -int32_t iis2mdc_set_rst_mode_get(stmdev_ctx_t *ctx, +int32_t iis2mdc_set_rst_mode_get(const stmdev_ctx_t *ctx, iis2mdc_set_rst_t *val); -int32_t iis2mdc_set_rst_sensor_single_set(stmdev_ctx_t *ctx, +int32_t iis2mdc_set_rst_sensor_single_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2mdc_set_rst_sensor_single_get(stmdev_ctx_t *ctx, +int32_t iis2mdc_set_rst_sensor_single_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2mdc_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2mdc_block_data_update_get(stmdev_ctx_t *ctx, +int32_t iis2mdc_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2mdc_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2mdc_mag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2mdc_mag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2mdc_mag_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2mdc_mag_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2mdc_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t iis2mdc_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t iis2mdc_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t iis2mdc_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t iis2mdc_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t iis2mdc_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t iis2mdc_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2mdc_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2mdc_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2mdc_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2mdc_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2mdc_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2mdc_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2mdc_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2mdc_self_test_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2mdc_self_test_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2mdc_self_test_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2mdc_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { IIS2MDC_LSB_AT_LOW_ADD = 0, IIS2MDC_MSB_AT_LOW_ADD = 1, } iis2mdc_ble_t; -int32_t iis2mdc_data_format_set(stmdev_ctx_t *ctx, iis2mdc_ble_t val); -int32_t iis2mdc_data_format_get(stmdev_ctx_t *ctx, +int32_t iis2mdc_data_format_set(const stmdev_ctx_t *ctx, iis2mdc_ble_t val); +int32_t iis2mdc_data_format_get(const stmdev_ctx_t *ctx, iis2mdc_ble_t *val); -int32_t iis2mdc_status_get(stmdev_ctx_t *ctx, +int32_t iis2mdc_status_get(const stmdev_ctx_t *ctx, iis2mdc_status_reg_t *val); typedef enum @@ -464,36 +464,36 @@ typedef enum IIS2MDC_CHECK_BEFORE = 0, IIS2MDC_CHECK_AFTER = 1, } iis2mdc_int_on_dataoff_t; -int32_t iis2mdc_offset_int_conf_set(stmdev_ctx_t *ctx, +int32_t iis2mdc_offset_int_conf_set(const stmdev_ctx_t *ctx, iis2mdc_int_on_dataoff_t val); -int32_t iis2mdc_offset_int_conf_get(stmdev_ctx_t *ctx, +int32_t iis2mdc_offset_int_conf_get(const stmdev_ctx_t *ctx, iis2mdc_int_on_dataoff_t *val); -int32_t iis2mdc_drdy_on_pin_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2mdc_drdy_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2mdc_drdy_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2mdc_drdy_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2mdc_int_on_pin_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis2mdc_int_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis2mdc_int_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis2mdc_int_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis2mdc_int_gen_conf_set(stmdev_ctx_t *ctx, +int32_t iis2mdc_int_gen_conf_set(const stmdev_ctx_t *ctx, iis2mdc_int_crtl_reg_t *val); -int32_t iis2mdc_int_gen_conf_get(stmdev_ctx_t *ctx, +int32_t iis2mdc_int_gen_conf_get(const stmdev_ctx_t *ctx, iis2mdc_int_crtl_reg_t *val); -int32_t iis2mdc_int_gen_source_get(stmdev_ctx_t *ctx, +int32_t iis2mdc_int_gen_source_get(const stmdev_ctx_t *ctx, iis2mdc_int_source_reg_t *val); -int32_t iis2mdc_int_gen_treshold_set(stmdev_ctx_t *ctx, int16_t val); -int32_t iis2mdc_int_gen_treshold_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t iis2mdc_int_gen_threshold_set(const stmdev_ctx_t *ctx, int16_t val); +int32_t iis2mdc_int_gen_threshold_get(const stmdev_ctx_t *ctx, int16_t *val); typedef enum { IIS2MDC_I2C_ENABLE = 0, IIS2MDC_I2C_DISABLE = 1, } iis2mdc_i2c_dis_t; -int32_t iis2mdc_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t iis2mdc_i2c_interface_set(const stmdev_ctx_t *ctx, iis2mdc_i2c_dis_t val); -int32_t iis2mdc_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t iis2mdc_i2c_interface_get(const stmdev_ctx_t *ctx, iis2mdc_i2c_dis_t *val); /** diff --git a/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.c b/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.c index d4865558..006d2686 100644 --- a/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.c +++ b/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.c @@ -46,12 +46,14 @@ * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak iis328dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak iis328dq_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +69,14 @@ int32_t __weak iis328dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak iis328dq_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak iis328dq_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -126,7 +130,7 @@ float_t iis328dq_from_fs8_to_mg(int16_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis328dq_axis_x_data_set(const stmdev_ctx_t *ctx, uint8_t val) { iis328dq_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -152,7 +156,7 @@ int32_t iis328dq_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis328dq_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis328dq_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -172,7 +176,7 @@ int32_t iis328dq_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis328dq_axis_y_data_set(const stmdev_ctx_t *ctx, uint8_t val) { iis328dq_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -198,7 +202,7 @@ int32_t iis328dq_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis328dq_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis328dq_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -218,7 +222,7 @@ int32_t iis328dq_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis328dq_axis_z_data_set(const stmdev_ctx_t *ctx, uint8_t val) { iis328dq_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -244,7 +248,7 @@ int32_t iis328dq_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis328dq_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis328dq_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -264,7 +268,7 @@ int32_t iis328dq_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_data_rate_set(stmdev_ctx_t *ctx, iis328dq_dr_t val) +int32_t iis328dq_data_rate_set(const stmdev_ctx_t *ctx, iis328dq_dr_t val) { iis328dq_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -291,7 +295,7 @@ int32_t iis328dq_data_rate_set(stmdev_ctx_t *ctx, iis328dq_dr_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_data_rate_get(stmdev_ctx_t *ctx, iis328dq_dr_t *val) +int32_t iis328dq_data_rate_get(const stmdev_ctx_t *ctx, iis328dq_dr_t *val) { iis328dq_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -313,8 +317,8 @@ int32_t iis328dq_data_rate_get(stmdev_ctx_t *ctx, iis328dq_dr_t *val) *val = IIS328DQ_ODR_1Hz; break; - case IIS328DQ_ODR_5Hz2: - *val = IIS328DQ_ODR_5Hz2; + case IIS328DQ_ODR_2Hz: + *val = IIS328DQ_ODR_2Hz; break; case IIS328DQ_ODR_5Hz: @@ -357,7 +361,7 @@ int32_t iis328dq_data_rate_get(stmdev_ctx_t *ctx, iis328dq_dr_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_reference_mode_set(stmdev_ctx_t *ctx, +int32_t iis328dq_reference_mode_set(const stmdev_ctx_t *ctx, iis328dq_hpm_t val) { iis328dq_ctrl_reg2_t ctrl_reg2; @@ -384,7 +388,7 @@ int32_t iis328dq_reference_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_reference_mode_get(stmdev_ctx_t *ctx, +int32_t iis328dq_reference_mode_get(const stmdev_ctx_t *ctx, iis328dq_hpm_t *val) { iis328dq_ctrl_reg2_t ctrl_reg2; @@ -419,7 +423,7 @@ int32_t iis328dq_reference_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_full_scale_set(stmdev_ctx_t *ctx, iis328dq_fs_t val) +int32_t iis328dq_full_scale_set(const stmdev_ctx_t *ctx, iis328dq_fs_t val) { iis328dq_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -445,7 +449,7 @@ int32_t iis328dq_full_scale_set(stmdev_ctx_t *ctx, iis328dq_fs_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_full_scale_get(stmdev_ctx_t *ctx, iis328dq_fs_t *val) +int32_t iis328dq_full_scale_get(const stmdev_ctx_t *ctx, iis328dq_fs_t *val) { iis328dq_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -483,7 +487,7 @@ int32_t iis328dq_full_scale_get(stmdev_ctx_t *ctx, iis328dq_fs_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis328dq_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { iis328dq_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -509,7 +513,7 @@ int32_t iis328dq_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_block_data_update_get(stmdev_ctx_t *ctx, +int32_t iis328dq_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis328dq_ctrl_reg4_t ctrl_reg4; @@ -530,7 +534,7 @@ int32_t iis328dq_block_data_update_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_status_reg_get(stmdev_ctx_t *ctx, +int32_t iis328dq_status_reg_get(const stmdev_ctx_t *ctx, iis328dq_status_reg_t *val) { int32_t ret; @@ -548,7 +552,7 @@ int32_t iis328dq_status_reg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis328dq_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis328dq_status_reg_t status_reg; int32_t ret; @@ -581,7 +585,7 @@ int32_t iis328dq_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t iis328dq_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -617,7 +621,7 @@ int32_t iis328dq_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis328dq_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -634,7 +638,7 @@ int32_t iis328dq_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis328dq_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { iis328dq_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -660,7 +664,7 @@ int32_t iis328dq_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis328dq_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis328dq_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -680,7 +684,7 @@ int32_t iis328dq_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_self_test_set(stmdev_ctx_t *ctx, iis328dq_st_t val) +int32_t iis328dq_self_test_set(const stmdev_ctx_t *ctx, iis328dq_st_t val) { iis328dq_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -706,7 +710,7 @@ int32_t iis328dq_self_test_set(stmdev_ctx_t *ctx, iis328dq_st_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_self_test_get(stmdev_ctx_t *ctx, iis328dq_st_t *val) +int32_t iis328dq_self_test_get(const stmdev_ctx_t *ctx, iis328dq_st_t *val) { iis328dq_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -744,7 +748,7 @@ int32_t iis328dq_self_test_get(stmdev_ctx_t *ctx, iis328dq_st_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_data_format_set(stmdev_ctx_t *ctx, +int32_t iis328dq_data_format_set(const stmdev_ctx_t *ctx, iis328dq_ble_t val) { iis328dq_ctrl_reg4_t ctrl_reg4; @@ -771,7 +775,7 @@ int32_t iis328dq_data_format_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_data_format_get(stmdev_ctx_t *ctx, +int32_t iis328dq_data_format_get(const stmdev_ctx_t *ctx, iis328dq_ble_t *val) { iis328dq_ctrl_reg4_t ctrl_reg4; @@ -819,7 +823,7 @@ int32_t iis328dq_data_format_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t iis328dq_hp_bandwidth_set(const stmdev_ctx_t *ctx, iis328dq_hpcf_t val) { iis328dq_ctrl_reg2_t ctrl_reg2; @@ -846,7 +850,7 @@ int32_t iis328dq_hp_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t iis328dq_hp_bandwidth_get(const stmdev_ctx_t *ctx, iis328dq_hpcf_t *val) { iis328dq_ctrl_reg2_t ctrl_reg2; @@ -889,7 +893,7 @@ int32_t iis328dq_hp_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_hp_path_set(stmdev_ctx_t *ctx, iis328dq_hpen_t val) +int32_t iis328dq_hp_path_set(const stmdev_ctx_t *ctx, iis328dq_hpen_t val) { iis328dq_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -916,7 +920,7 @@ int32_t iis328dq_hp_path_set(stmdev_ctx_t *ctx, iis328dq_hpen_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_hp_path_get(stmdev_ctx_t *ctx, iis328dq_hpen_t *val) +int32_t iis328dq_hp_path_get(const stmdev_ctx_t *ctx, iis328dq_hpen_t *val) { iis328dq_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -978,7 +982,7 @@ int32_t iis328dq_hp_path_get(stmdev_ctx_t *ctx, iis328dq_hpen_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_hp_reset_get(stmdev_ctx_t *ctx) +int32_t iis328dq_hp_reset_get(const stmdev_ctx_t *ctx) { uint8_t dummy; int32_t ret; @@ -997,7 +1001,7 @@ int32_t iis328dq_hp_reset_get(stmdev_ctx_t *ctx) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_hp_reference_value_set(stmdev_ctx_t *ctx, +int32_t iis328dq_hp_reference_value_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; @@ -1015,7 +1019,7 @@ int32_t iis328dq_hp_reference_value_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_hp_reference_value_get(stmdev_ctx_t *ctx, +int32_t iis328dq_hp_reference_value_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -1046,7 +1050,7 @@ int32_t iis328dq_hp_reference_value_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_spi_mode_set(stmdev_ctx_t *ctx, iis328dq_sim_t val) +int32_t iis328dq_spi_mode_set(const stmdev_ctx_t *ctx, iis328dq_sim_t val) { iis328dq_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -1072,7 +1076,7 @@ int32_t iis328dq_spi_mode_set(stmdev_ctx_t *ctx, iis328dq_sim_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_spi_mode_get(stmdev_ctx_t *ctx, iis328dq_sim_t *val) +int32_t iis328dq_spi_mode_get(const stmdev_ctx_t *ctx, iis328dq_sim_t *val) { iis328dq_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -1119,7 +1123,7 @@ int32_t iis328dq_spi_mode_get(stmdev_ctx_t *ctx, iis328dq_sim_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t iis328dq_pin_int1_route_set(const stmdev_ctx_t *ctx, iis328dq_i1_cfg_t val) { iis328dq_ctrl_reg3_t ctrl_reg3; @@ -1146,7 +1150,7 @@ int32_t iis328dq_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t iis328dq_pin_int1_route_get(const stmdev_ctx_t *ctx, iis328dq_i1_cfg_t *val) { iis328dq_ctrl_reg3_t ctrl_reg3; @@ -1190,7 +1194,7 @@ int32_t iis328dq_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int1_notification_set(stmdev_ctx_t *ctx, +int32_t iis328dq_int1_notification_set(const stmdev_ctx_t *ctx, iis328dq_lir1_t val) { iis328dq_ctrl_reg3_t ctrl_reg3; @@ -1218,7 +1222,7 @@ int32_t iis328dq_int1_notification_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int1_notification_get(stmdev_ctx_t *ctx, +int32_t iis328dq_int1_notification_get(const stmdev_ctx_t *ctx, iis328dq_lir1_t *val) { iis328dq_ctrl_reg3_t ctrl_reg3; @@ -1253,7 +1257,7 @@ int32_t iis328dq_int1_notification_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t iis328dq_pin_int2_route_set(const stmdev_ctx_t *ctx, iis328dq_i2_cfg_t val) { iis328dq_ctrl_reg3_t ctrl_reg3; @@ -1280,7 +1284,7 @@ int32_t iis328dq_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t iis328dq_pin_int2_route_get(const stmdev_ctx_t *ctx, iis328dq_i2_cfg_t *val) { iis328dq_ctrl_reg3_t ctrl_reg3; @@ -1324,7 +1328,7 @@ int32_t iis328dq_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int2_notification_set(stmdev_ctx_t *ctx, +int32_t iis328dq_int2_notification_set(const stmdev_ctx_t *ctx, iis328dq_lir2_t val) { iis328dq_ctrl_reg3_t ctrl_reg3; @@ -1352,7 +1356,7 @@ int32_t iis328dq_int2_notification_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int2_notification_get(stmdev_ctx_t *ctx, +int32_t iis328dq_int2_notification_get(const stmdev_ctx_t *ctx, iis328dq_lir2_t *val) { iis328dq_ctrl_reg3_t ctrl_reg3; @@ -1387,7 +1391,7 @@ int32_t iis328dq_int2_notification_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_pin_mode_set(stmdev_ctx_t *ctx, iis328dq_pp_od_t val) +int32_t iis328dq_pin_mode_set(const stmdev_ctx_t *ctx, iis328dq_pp_od_t val) { iis328dq_ctrl_reg3_t ctrl_reg3; int32_t ret; @@ -1413,7 +1417,7 @@ int32_t iis328dq_pin_mode_set(stmdev_ctx_t *ctx, iis328dq_pp_od_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_pin_mode_get(stmdev_ctx_t *ctx, +int32_t iis328dq_pin_mode_get(const stmdev_ctx_t *ctx, iis328dq_pp_od_t *val) { iis328dq_ctrl_reg3_t ctrl_reg3; @@ -1448,7 +1452,7 @@ int32_t iis328dq_pin_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t iis328dq_pin_polarity_set(const stmdev_ctx_t *ctx, iis328dq_ihl_t val) { iis328dq_ctrl_reg3_t ctrl_reg3; @@ -1475,7 +1479,7 @@ int32_t iis328dq_pin_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t iis328dq_pin_polarity_get(const stmdev_ctx_t *ctx, iis328dq_ihl_t *val) { iis328dq_ctrl_reg3_t ctrl_reg3; @@ -1523,7 +1527,7 @@ int32_t iis328dq_pin_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int1_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t iis328dq_int1_on_threshold_conf_set(const stmdev_ctx_t *ctx, int1_on_th_conf_t val) { iis328dq_int1_cfg_t int1_cfg; @@ -1554,7 +1558,7 @@ int32_t iis328dq_int1_on_threshold_conf_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int1_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t iis328dq_int1_on_threshold_conf_get(const stmdev_ctx_t *ctx, int1_on_th_conf_t *val) { iis328dq_int1_cfg_t int1_cfg; @@ -1579,7 +1583,7 @@ int32_t iis328dq_int1_on_threshold_conf_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int1_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t iis328dq_int1_on_threshold_mode_set(const stmdev_ctx_t *ctx, iis328dq_int1_aoi_t val) { iis328dq_int1_cfg_t int1_cfg; @@ -1605,7 +1609,7 @@ int32_t iis328dq_int1_on_threshold_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int1_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t iis328dq_int1_on_threshold_mode_get(const stmdev_ctx_t *ctx, iis328dq_int1_aoi_t *val) { iis328dq_int1_cfg_t int1_cfg; @@ -1639,7 +1643,7 @@ int32_t iis328dq_int1_on_threshold_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int1_src_get(stmdev_ctx_t *ctx, +int32_t iis328dq_int1_src_get(const stmdev_ctx_t *ctx, iis328dq_int1_src_t *val) { int32_t ret; @@ -1657,7 +1661,7 @@ int32_t iis328dq_int1_src_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis328dq_int1_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { iis328dq_int1_ths_t int1_ths; int32_t ret; @@ -1682,7 +1686,7 @@ int32_t iis328dq_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis328dq_int1_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis328dq_int1_ths_t int1_ths; int32_t ret; @@ -1701,7 +1705,7 @@ int32_t iis328dq_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis328dq_int1_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { iis328dq_int1_duration_t int1_duration; int32_t ret; @@ -1727,7 +1731,7 @@ int32_t iis328dq_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis328dq_int1_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis328dq_int1_duration_t int1_duration; int32_t ret; @@ -1747,7 +1751,7 @@ int32_t iis328dq_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int2_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t iis328dq_int2_on_threshold_conf_set(const stmdev_ctx_t *ctx, int2_on_th_conf_t val) { iis328dq_int2_cfg_t int2_cfg; @@ -1779,7 +1783,7 @@ int32_t iis328dq_int2_on_threshold_conf_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int2_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t iis328dq_int2_on_threshold_conf_get(const stmdev_ctx_t *ctx, int2_on_th_conf_t *val) { iis328dq_int2_cfg_t int2_cfg; @@ -1804,7 +1808,7 @@ int32_t iis328dq_int2_on_threshold_conf_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int2_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t iis328dq_int2_on_threshold_mode_set(const stmdev_ctx_t *ctx, iis328dq_int2_aoi_t val) { iis328dq_int2_cfg_t int2_cfg; @@ -1830,7 +1834,7 @@ int32_t iis328dq_int2_on_threshold_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int2_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t iis328dq_int2_on_threshold_mode_get(const stmdev_ctx_t *ctx, iis328dq_int2_aoi_t *val) { iis328dq_int2_cfg_t int2_cfg; @@ -1864,7 +1868,7 @@ int32_t iis328dq_int2_on_threshold_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int2_src_get(stmdev_ctx_t *ctx, +int32_t iis328dq_int2_src_get(const stmdev_ctx_t *ctx, iis328dq_int2_src_t *val) { int32_t ret; @@ -1882,7 +1886,7 @@ int32_t iis328dq_int2_src_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis328dq_int2_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { iis328dq_int2_ths_t int2_ths; int32_t ret; @@ -1907,7 +1911,7 @@ int32_t iis328dq_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis328dq_int2_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis328dq_int2_ths_t int2_ths; int32_t ret; @@ -1926,7 +1930,7 @@ int32_t iis328dq_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis328dq_int2_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { iis328dq_int2_duration_t int2_duration; int32_t ret; @@ -1952,7 +1956,7 @@ int32_t iis328dq_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis328dq_int2_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis328dq_int2_duration_t int2_duration; int32_t ret; @@ -1985,7 +1989,7 @@ int32_t iis328dq_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis328dq_wkup_to_sleep_set(const stmdev_ctx_t *ctx, uint8_t val) { iis328dq_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -2011,7 +2015,7 @@ int32_t iis328dq_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis328dq_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis328dq_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -2044,7 +2048,7 @@ int32_t iis328dq_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int1_6d_mode_set(stmdev_ctx_t *ctx, +int32_t iis328dq_int1_6d_mode_set(const stmdev_ctx_t *ctx, iis328dq_int1_6d_t val) { iis328dq_int1_cfg_t int1_cfg; @@ -2070,7 +2074,7 @@ int32_t iis328dq_int1_6d_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int1_6d_mode_get(stmdev_ctx_t *ctx, +int32_t iis328dq_int1_6d_mode_get(const stmdev_ctx_t *ctx, iis328dq_int1_6d_t *val) { iis328dq_int1_cfg_t int1_cfg; @@ -2108,7 +2112,7 @@ int32_t iis328dq_int1_6d_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int1_6d_src_get(stmdev_ctx_t *ctx, +int32_t iis328dq_int1_6d_src_get(const stmdev_ctx_t *ctx, iis328dq_int1_src_t *val) { int32_t ret; @@ -2126,7 +2130,7 @@ int32_t iis328dq_int1_6d_src_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int1_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis328dq_int1_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { iis328dq_int1_ths_t int1_ths; int32_t ret; @@ -2150,7 +2154,7 @@ int32_t iis328dq_int1_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int1_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis328dq_int1_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis328dq_int1_ths_t int1_ths; int32_t ret; @@ -2169,7 +2173,7 @@ int32_t iis328dq_int1_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int2_6d_mode_set(stmdev_ctx_t *ctx, +int32_t iis328dq_int2_6d_mode_set(const stmdev_ctx_t *ctx, iis328dq_int2_6d_t val) { iis328dq_int2_cfg_t int2_cfg; @@ -2196,7 +2200,7 @@ int32_t iis328dq_int2_6d_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int2_6d_mode_get(stmdev_ctx_t *ctx, +int32_t iis328dq_int2_6d_mode_get(const stmdev_ctx_t *ctx, iis328dq_int2_6d_t *val) { iis328dq_int2_cfg_t int2_cfg; @@ -2234,7 +2238,7 @@ int32_t iis328dq_int2_6d_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int2_6d_src_get(stmdev_ctx_t *ctx, +int32_t iis328dq_int2_6d_src_get(const stmdev_ctx_t *ctx, iis328dq_int2_src_t *val) { int32_t ret; @@ -2252,7 +2256,7 @@ int32_t iis328dq_int2_6d_src_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int2_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis328dq_int2_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { iis328dq_int2_ths_t int2_ths; int32_t ret; @@ -2277,7 +2281,7 @@ int32_t iis328dq_int2_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t iis328dq_int2_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis328dq_int2_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis328dq_int2_ths_t int2_ths; int32_t ret; diff --git a/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.h b/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.h index d11453d8..4a4645d5 100644 --- a/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.h +++ b/sensor/stmemsc/iis328dq_STdC/driver/iis328dq_reg.h @@ -494,10 +494,10 @@ typedef union * them with a custom implementation. */ -int32_t iis328dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t iis328dq_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t iis328dq_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t iis328dq_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -505,21 +505,21 @@ float_t iis328dq_from_fs2_to_mg(int16_t lsb); float_t iis328dq_from_fs4_to_mg(int16_t lsb); float_t iis328dq_from_fs8_to_mg(int16_t lsb); -int32_t iis328dq_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis328dq_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis328dq_axis_x_data_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis328dq_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis328dq_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis328dq_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis328dq_axis_y_data_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis328dq_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis328dq_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis328dq_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis328dq_axis_z_data_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis328dq_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { IIS328DQ_ODR_OFF = 0x00, IIS328DQ_ODR_Hz5 = 0x02, IIS328DQ_ODR_1Hz = 0x03, - IIS328DQ_ODR_5Hz2 = 0x04, + IIS328DQ_ODR_2Hz = 0x04, IIS328DQ_ODR_5Hz = 0x05, IIS328DQ_ODR_10Hz = 0x06, IIS328DQ_ODR_50Hz = 0x01, @@ -527,17 +527,17 @@ typedef enum IIS328DQ_ODR_400Hz = 0x21, IIS328DQ_ODR_1kHz = 0x31, } iis328dq_dr_t; -int32_t iis328dq_data_rate_set(stmdev_ctx_t *ctx, iis328dq_dr_t val); -int32_t iis328dq_data_rate_get(stmdev_ctx_t *ctx, iis328dq_dr_t *val); +int32_t iis328dq_data_rate_set(const stmdev_ctx_t *ctx, iis328dq_dr_t val); +int32_t iis328dq_data_rate_get(const stmdev_ctx_t *ctx, iis328dq_dr_t *val); typedef enum { IIS328DQ_NORMAL_MODE = 0, IIS328DQ_REF_MODE_ENABLE = 1, } iis328dq_hpm_t; -int32_t iis328dq_reference_mode_set(stmdev_ctx_t *ctx, +int32_t iis328dq_reference_mode_set(const stmdev_ctx_t *ctx, iis328dq_hpm_t val); -int32_t iis328dq_reference_mode_get(stmdev_ctx_t *ctx, +int32_t iis328dq_reference_mode_get(const stmdev_ctx_t *ctx, iis328dq_hpm_t *val); typedef enum @@ -546,28 +546,28 @@ typedef enum IIS328DQ_4g = 1, IIS328DQ_8g = 3, } iis328dq_fs_t; -int32_t iis328dq_full_scale_set(stmdev_ctx_t *ctx, iis328dq_fs_t val); -int32_t iis328dq_full_scale_get(stmdev_ctx_t *ctx, +int32_t iis328dq_full_scale_set(const stmdev_ctx_t *ctx, iis328dq_fs_t val); +int32_t iis328dq_full_scale_get(const stmdev_ctx_t *ctx, iis328dq_fs_t *val); -int32_t iis328dq_block_data_update_set(stmdev_ctx_t *ctx, +int32_t iis328dq_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t iis328dq_block_data_update_get(stmdev_ctx_t *ctx, +int32_t iis328dq_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis328dq_status_reg_get(stmdev_ctx_t *ctx, +int32_t iis328dq_status_reg_get(const stmdev_ctx_t *ctx, iis328dq_status_reg_t *val); -int32_t iis328dq_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t iis328dq_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis328dq_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t iis328dq_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t iis328dq_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t iis328dq_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t iis328dq_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis328dq_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis328dq_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis328dq_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -575,17 +575,17 @@ typedef enum IIS328DQ_ST_POSITIVE = 1, IIS328DQ_ST_NEGATIVE = 5, } iis328dq_st_t; -int32_t iis328dq_self_test_set(stmdev_ctx_t *ctx, iis328dq_st_t val); -int32_t iis328dq_self_test_get(stmdev_ctx_t *ctx, iis328dq_st_t *val); +int32_t iis328dq_self_test_set(const stmdev_ctx_t *ctx, iis328dq_st_t val); +int32_t iis328dq_self_test_get(const stmdev_ctx_t *ctx, iis328dq_st_t *val); typedef enum { IIS328DQ_LSB_AT_LOW_ADD = 0, IIS328DQ_MSB_AT_LOW_ADD = 1, } iis328dq_ble_t; -int32_t iis328dq_data_format_set(stmdev_ctx_t *ctx, +int32_t iis328dq_data_format_set(const stmdev_ctx_t *ctx, iis328dq_ble_t val); -int32_t iis328dq_data_format_get(stmdev_ctx_t *ctx, +int32_t iis328dq_data_format_get(const stmdev_ctx_t *ctx, iis328dq_ble_t *val); typedef enum @@ -595,9 +595,9 @@ typedef enum IIS328DQ_CUT_OFF_32Hz = 2, IIS328DQ_CUT_OFF_64Hz = 3, } iis328dq_hpcf_t; -int32_t iis328dq_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t iis328dq_hp_bandwidth_set(const stmdev_ctx_t *ctx, iis328dq_hpcf_t val); -int32_t iis328dq_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t iis328dq_hp_bandwidth_get(const stmdev_ctx_t *ctx, iis328dq_hpcf_t *val); typedef enum @@ -611,14 +611,14 @@ typedef enum IIS328DQ_HP_ON_INT2_OUT = 6, IIS328DQ_HP_ON_INT1_OUT = 5, } iis328dq_hpen_t; -int32_t iis328dq_hp_path_set(stmdev_ctx_t *ctx, iis328dq_hpen_t val); -int32_t iis328dq_hp_path_get(stmdev_ctx_t *ctx, iis328dq_hpen_t *val); +int32_t iis328dq_hp_path_set(const stmdev_ctx_t *ctx, iis328dq_hpen_t val); +int32_t iis328dq_hp_path_get(const stmdev_ctx_t *ctx, iis328dq_hpen_t *val); -int32_t iis328dq_hp_reset_get(stmdev_ctx_t *ctx); +int32_t iis328dq_hp_reset_get(const stmdev_ctx_t *ctx); -int32_t iis328dq_hp_reference_value_set(stmdev_ctx_t *ctx, +int32_t iis328dq_hp_reference_value_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t iis328dq_hp_reference_value_get(stmdev_ctx_t *ctx, +int32_t iis328dq_hp_reference_value_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -626,8 +626,8 @@ typedef enum IIS328DQ_SPI_4_WIRE = 0, IIS328DQ_SPI_3_WIRE = 1, } iis328dq_sim_t; -int32_t iis328dq_spi_mode_set(stmdev_ctx_t *ctx, iis328dq_sim_t val); -int32_t iis328dq_spi_mode_get(stmdev_ctx_t *ctx, iis328dq_sim_t *val); +int32_t iis328dq_spi_mode_set(const stmdev_ctx_t *ctx, iis328dq_sim_t val); +int32_t iis328dq_spi_mode_get(const stmdev_ctx_t *ctx, iis328dq_sim_t *val); typedef enum { @@ -636,9 +636,9 @@ typedef enum IIS328DQ_PAD1_DRDY = 2, IIS328DQ_PAD1_BOOT = 3, } iis328dq_i1_cfg_t; -int32_t iis328dq_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t iis328dq_pin_int1_route_set(const stmdev_ctx_t *ctx, iis328dq_i1_cfg_t val); -int32_t iis328dq_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t iis328dq_pin_int1_route_get(const stmdev_ctx_t *ctx, iis328dq_i1_cfg_t *val); typedef enum @@ -646,9 +646,9 @@ typedef enum IIS328DQ_INT1_PULSED = 0, IIS328DQ_INT1_LATCHED = 1, } iis328dq_lir1_t; -int32_t iis328dq_int1_notification_set(stmdev_ctx_t *ctx, +int32_t iis328dq_int1_notification_set(const stmdev_ctx_t *ctx, iis328dq_lir1_t val); -int32_t iis328dq_int1_notification_get(stmdev_ctx_t *ctx, +int32_t iis328dq_int1_notification_get(const stmdev_ctx_t *ctx, iis328dq_lir1_t *val); typedef enum @@ -658,9 +658,9 @@ typedef enum IIS328DQ_PAD2_DRDY = 2, IIS328DQ_PAD2_BOOT = 3, } iis328dq_i2_cfg_t; -int32_t iis328dq_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t iis328dq_pin_int2_route_set(const stmdev_ctx_t *ctx, iis328dq_i2_cfg_t val); -int32_t iis328dq_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t iis328dq_pin_int2_route_get(const stmdev_ctx_t *ctx, iis328dq_i2_cfg_t *val); typedef enum @@ -668,9 +668,9 @@ typedef enum IIS328DQ_INT2_PULSED = 0, IIS328DQ_INT2_LATCHED = 1, } iis328dq_lir2_t; -int32_t iis328dq_int2_notification_set(stmdev_ctx_t *ctx, +int32_t iis328dq_int2_notification_set(const stmdev_ctx_t *ctx, iis328dq_lir2_t val); -int32_t iis328dq_int2_notification_get(stmdev_ctx_t *ctx, +int32_t iis328dq_int2_notification_get(const stmdev_ctx_t *ctx, iis328dq_lir2_t *val); typedef enum @@ -678,9 +678,9 @@ typedef enum IIS328DQ_PUSH_PULL = 0, IIS328DQ_OPEN_DRAIN = 1, } iis328dq_pp_od_t; -int32_t iis328dq_pin_mode_set(stmdev_ctx_t *ctx, +int32_t iis328dq_pin_mode_set(const stmdev_ctx_t *ctx, iis328dq_pp_od_t val); -int32_t iis328dq_pin_mode_get(stmdev_ctx_t *ctx, +int32_t iis328dq_pin_mode_get(const stmdev_ctx_t *ctx, iis328dq_pp_od_t *val); typedef enum @@ -688,9 +688,9 @@ typedef enum IIS328DQ_ACTIVE_HIGH = 0, IIS328DQ_ACTIVE_LOW = 1, } iis328dq_ihl_t; -int32_t iis328dq_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t iis328dq_pin_polarity_set(const stmdev_ctx_t *ctx, iis328dq_ihl_t val); -int32_t iis328dq_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t iis328dq_pin_polarity_get(const stmdev_ctx_t *ctx, iis328dq_ihl_t *val); typedef struct @@ -702,9 +702,9 @@ typedef struct uint8_t int1_zlie : 1; uint8_t int1_zhie : 1; } int1_on_th_conf_t; -int32_t iis328dq_int1_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t iis328dq_int1_on_threshold_conf_set(const stmdev_ctx_t *ctx, int1_on_th_conf_t val); -int32_t iis328dq_int1_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t iis328dq_int1_on_threshold_conf_get(const stmdev_ctx_t *ctx, int1_on_th_conf_t *val); typedef enum @@ -712,19 +712,19 @@ typedef enum IIS328DQ_INT1_ON_THRESHOLD_OR = 0, IIS328DQ_INT1_ON_THRESHOLD_AND = 1, } iis328dq_int1_aoi_t; -int32_t iis328dq_int1_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t iis328dq_int1_on_threshold_mode_set(const stmdev_ctx_t *ctx, iis328dq_int1_aoi_t val); -int32_t iis328dq_int1_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t iis328dq_int1_on_threshold_mode_get(const stmdev_ctx_t *ctx, iis328dq_int1_aoi_t *val); -int32_t iis328dq_int1_src_get(stmdev_ctx_t *ctx, +int32_t iis328dq_int1_src_get(const stmdev_ctx_t *ctx, iis328dq_int1_src_t *val); -int32_t iis328dq_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis328dq_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis328dq_int1_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis328dq_int1_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis328dq_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis328dq_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis328dq_int1_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis328dq_int1_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -735,9 +735,9 @@ typedef struct uint8_t int2_zlie : 1; uint8_t int2_zhie : 1; } int2_on_th_conf_t; -int32_t iis328dq_int2_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t iis328dq_int2_on_threshold_conf_set(const stmdev_ctx_t *ctx, int2_on_th_conf_t val); -int32_t iis328dq_int2_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t iis328dq_int2_on_threshold_conf_get(const stmdev_ctx_t *ctx, int2_on_th_conf_t *val); typedef enum @@ -745,22 +745,22 @@ typedef enum IIS328DQ_INT2_ON_THRESHOLD_OR = 0, IIS328DQ_INT2_ON_THRESHOLD_AND = 1, } iis328dq_int2_aoi_t; -int32_t iis328dq_int2_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t iis328dq_int2_on_threshold_mode_set(const stmdev_ctx_t *ctx, iis328dq_int2_aoi_t val); -int32_t iis328dq_int2_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t iis328dq_int2_on_threshold_mode_get(const stmdev_ctx_t *ctx, iis328dq_int2_aoi_t *val); -int32_t iis328dq_int2_src_get(stmdev_ctx_t *ctx, +int32_t iis328dq_int2_src_get(const stmdev_ctx_t *ctx, iis328dq_int2_src_t *val); -int32_t iis328dq_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis328dq_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis328dq_int2_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis328dq_int2_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis328dq_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis328dq_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis328dq_int2_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis328dq_int2_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis328dq_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis328dq_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis328dq_wkup_to_sleep_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis328dq_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -768,16 +768,16 @@ typedef enum IIS328DQ_6D_INT1_MOVEMENT = 1, IIS328DQ_6D_INT1_POSITION = 3, } iis328dq_int1_6d_t; -int32_t iis328dq_int1_6d_mode_set(stmdev_ctx_t *ctx, +int32_t iis328dq_int1_6d_mode_set(const stmdev_ctx_t *ctx, iis328dq_int1_6d_t val); -int32_t iis328dq_int1_6d_mode_get(stmdev_ctx_t *ctx, +int32_t iis328dq_int1_6d_mode_get(const stmdev_ctx_t *ctx, iis328dq_int1_6d_t *val); -int32_t iis328dq_int1_6d_src_get(stmdev_ctx_t *ctx, +int32_t iis328dq_int1_6d_src_get(const stmdev_ctx_t *ctx, iis328dq_int1_src_t *val); -int32_t iis328dq_int1_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis328dq_int1_6d_treshold_get(stmdev_ctx_t *ctx, +int32_t iis328dq_int1_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis328dq_int1_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -786,16 +786,16 @@ typedef enum IIS328DQ_6D_INT2_MOVEMENT = 1, IIS328DQ_6D_INT2_POSITION = 3, } iis328dq_int2_6d_t; -int32_t iis328dq_int2_6d_mode_set(stmdev_ctx_t *ctx, +int32_t iis328dq_int2_6d_mode_set(const stmdev_ctx_t *ctx, iis328dq_int2_6d_t val); -int32_t iis328dq_int2_6d_mode_get(stmdev_ctx_t *ctx, +int32_t iis328dq_int2_6d_mode_get(const stmdev_ctx_t *ctx, iis328dq_int2_6d_t *val); -int32_t iis328dq_int2_6d_src_get(stmdev_ctx_t *ctx, +int32_t iis328dq_int2_6d_src_get(const stmdev_ctx_t *ctx, iis328dq_int2_src_t *val); -int32_t iis328dq_int2_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis328dq_int2_6d_treshold_get(stmdev_ctx_t *ctx, +int32_t iis328dq_int2_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis328dq_int2_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); /** diff --git a/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.c b/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.c index 1bfd69a8..c1937f67 100644 --- a/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.c +++ b/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.c @@ -46,12 +46,14 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak iis3dhhc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak iis3dhhc_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +69,14 @@ int32_t __weak iis3dhhc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak iis3dhhc_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak iis3dhhc_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -121,7 +125,7 @@ float_t iis3dhhc_from_lsb_to_celsius(int16_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dhhc_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dhhc_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -147,7 +151,7 @@ int32_t iis3dhhc_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_block_data_update_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dhhc_ctrl_reg1_t ctrl_reg1; @@ -168,7 +172,7 @@ int32_t iis3dhhc_block_data_update_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_data_rate_set(stmdev_ctx_t *ctx, +int32_t iis3dhhc_data_rate_set(const stmdev_ctx_t *ctx, iis3dhhc_norm_mod_en_t val) { iis3dhhc_ctrl_reg1_t ctrl_reg1; @@ -195,7 +199,7 @@ int32_t iis3dhhc_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_data_rate_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_data_rate_get(const stmdev_ctx_t *ctx, iis3dhhc_norm_mod_en_t *val) { iis3dhhc_ctrl_reg1_t ctrl_reg1; @@ -230,7 +234,7 @@ int32_t iis3dhhc_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_offset_temp_comp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dhhc_offset_temp_comp_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dhhc_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -256,7 +260,7 @@ int32_t iis3dhhc_offset_temp_comp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_offset_temp_comp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dhhc_offset_temp_comp_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dhhc_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -276,7 +280,7 @@ int32_t iis3dhhc_offset_temp_comp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t iis3dhhc_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -296,7 +300,7 @@ int32_t iis3dhhc_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t iis3dhhc_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -320,7 +324,7 @@ int32_t iis3dhhc_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dhhc_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dhhc_status_t status; int32_t ret; @@ -339,7 +343,7 @@ int32_t iis3dhhc_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dhhc_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dhhc_status_t status; int32_t ret; @@ -370,7 +374,7 @@ int32_t iis3dhhc_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis3dhhc_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -387,7 +391,7 @@ int32_t iis3dhhc_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dhhc_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dhhc_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -413,7 +417,7 @@ int32_t iis3dhhc_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dhhc_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dhhc_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -433,7 +437,7 @@ int32_t iis3dhhc_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dhhc_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dhhc_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -459,7 +463,7 @@ int32_t iis3dhhc_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dhhc_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dhhc_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -479,7 +483,7 @@ int32_t iis3dhhc_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_self_test_set(stmdev_ctx_t *ctx, iis3dhhc_st_t val) +int32_t iis3dhhc_self_test_set(const stmdev_ctx_t *ctx, iis3dhhc_st_t val) { iis3dhhc_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -505,7 +509,7 @@ int32_t iis3dhhc_self_test_set(stmdev_ctx_t *ctx, iis3dhhc_st_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_self_test_get(stmdev_ctx_t *ctx, iis3dhhc_st_t *val) +int32_t iis3dhhc_self_test_get(const stmdev_ctx_t *ctx, iis3dhhc_st_t *val) { iis3dhhc_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -543,7 +547,7 @@ int32_t iis3dhhc_self_test_get(stmdev_ctx_t *ctx, iis3dhhc_st_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_filter_config_set(stmdev_ctx_t *ctx, +int32_t iis3dhhc_filter_config_set(const stmdev_ctx_t *ctx, iis3dhhc_dsp_t val) { iis3dhhc_ctrl_reg4_t ctrl_reg4; @@ -570,7 +574,7 @@ int32_t iis3dhhc_filter_config_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_filter_config_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_filter_config_get(const stmdev_ctx_t *ctx, iis3dhhc_dsp_t *val) { iis3dhhc_ctrl_reg4_t ctrl_reg4; @@ -613,7 +617,7 @@ int32_t iis3dhhc_filter_config_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_status_get(stmdev_ctx_t *ctx, iis3dhhc_status_t *val) +int32_t iis3dhhc_status_get(const stmdev_ctx_t *ctx, iis3dhhc_status_t *val) { int32_t ret; @@ -642,7 +646,7 @@ int32_t iis3dhhc_status_get(stmdev_ctx_t *ctx, iis3dhhc_status_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_drdy_notification_mode_set(stmdev_ctx_t *ctx, +int32_t iis3dhhc_drdy_notification_mode_set(const stmdev_ctx_t *ctx, iis3dhhc_drdy_pulse_t val) { iis3dhhc_ctrl_reg1_t ctrl_reg1; @@ -669,7 +673,7 @@ int32_t iis3dhhc_drdy_notification_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_drdy_notification_mode_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_drdy_notification_mode_get(const stmdev_ctx_t *ctx, iis3dhhc_drdy_pulse_t *val) { iis3dhhc_ctrl_reg1_t ctrl_reg1; @@ -705,7 +709,7 @@ int32_t iis3dhhc_drdy_notification_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_int1_mode_set(stmdev_ctx_t *ctx, +int32_t iis3dhhc_int1_mode_set(const stmdev_ctx_t *ctx, iis3dhhc_int1_ext_t val) { iis3dhhc_int1_ctrl_t int1_ctrl; @@ -733,7 +737,7 @@ int32_t iis3dhhc_int1_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_int1_mode_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_int1_mode_get(const stmdev_ctx_t *ctx, iis3dhhc_int1_ext_t *val) { iis3dhhc_int1_ctrl_t int1_ctrl; @@ -768,7 +772,7 @@ int32_t iis3dhhc_int1_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_fifo_threshold_on_int1_set(stmdev_ctx_t *ctx, +int32_t iis3dhhc_fifo_threshold_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dhhc_int1_ctrl_t int1_ctrl; @@ -795,7 +799,7 @@ int32_t iis3dhhc_fifo_threshold_on_int1_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_fifo_threshold_on_int1_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_fifo_threshold_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dhhc_int1_ctrl_t int1_ctrl; @@ -816,7 +820,7 @@ int32_t iis3dhhc_fifo_threshold_on_int1_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_fifo_full_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dhhc_fifo_full_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dhhc_int1_ctrl_t int1_ctrl; int32_t ret; @@ -842,7 +846,7 @@ int32_t iis3dhhc_fifo_full_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_fifo_full_on_int1_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_fifo_full_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dhhc_int1_ctrl_t int1_ctrl; @@ -863,7 +867,7 @@ int32_t iis3dhhc_fifo_full_on_int1_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_fifo_ovr_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dhhc_fifo_ovr_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dhhc_int1_ctrl_t int1_ctrl; int32_t ret; @@ -889,7 +893,7 @@ int32_t iis3dhhc_fifo_ovr_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_fifo_ovr_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dhhc_fifo_ovr_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dhhc_int1_ctrl_t int1_ctrl; int32_t ret; @@ -909,7 +913,7 @@ int32_t iis3dhhc_fifo_ovr_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_boot_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dhhc_boot_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dhhc_int1_ctrl_t int1_ctrl; int32_t ret; @@ -935,7 +939,7 @@ int32_t iis3dhhc_boot_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_boot_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dhhc_boot_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dhhc_int1_ctrl_t int1_ctrl; int32_t ret; @@ -955,7 +959,7 @@ int32_t iis3dhhc_boot_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dhhc_drdy_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dhhc_int1_ctrl_t int1_ctrl; int32_t ret; @@ -981,7 +985,7 @@ int32_t iis3dhhc_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dhhc_drdy_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dhhc_int1_ctrl_t int1_ctrl; int32_t ret; @@ -1001,7 +1005,7 @@ int32_t iis3dhhc_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_fifo_threshold_on_int2_set(stmdev_ctx_t *ctx, +int32_t iis3dhhc_fifo_threshold_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dhhc_int2_ctrl_t int2_ctrl; @@ -1028,7 +1032,7 @@ int32_t iis3dhhc_fifo_threshold_on_int2_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_fifo_threshold_on_int2_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_fifo_threshold_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dhhc_int2_ctrl_t int2_ctrl; @@ -1049,7 +1053,7 @@ int32_t iis3dhhc_fifo_threshold_on_int2_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_fifo_full_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dhhc_fifo_full_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dhhc_int2_ctrl_t int2_ctrl; int32_t ret; @@ -1075,7 +1079,7 @@ int32_t iis3dhhc_fifo_full_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_fifo_full_on_int2_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_fifo_full_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dhhc_int2_ctrl_t int2_ctrl; @@ -1096,7 +1100,7 @@ int32_t iis3dhhc_fifo_full_on_int2_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_fifo_ovr_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dhhc_fifo_ovr_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dhhc_int2_ctrl_t int2_ctrl; int32_t ret; @@ -1122,7 +1126,7 @@ int32_t iis3dhhc_fifo_ovr_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_fifo_ovr_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dhhc_fifo_ovr_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dhhc_int2_ctrl_t int2_ctrl; int32_t ret; @@ -1142,7 +1146,7 @@ int32_t iis3dhhc_fifo_ovr_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_boot_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dhhc_boot_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dhhc_int2_ctrl_t int2_ctrl; int32_t ret; @@ -1168,7 +1172,7 @@ int32_t iis3dhhc_boot_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_boot_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dhhc_boot_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dhhc_int2_ctrl_t int2_ctrl; int32_t ret; @@ -1188,7 +1192,7 @@ int32_t iis3dhhc_boot_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dhhc_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dhhc_int2_ctrl_t int2_ctrl; int32_t ret; @@ -1214,7 +1218,7 @@ int32_t iis3dhhc_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dhhc_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dhhc_int2_ctrl_t int2_ctrl; int32_t ret; @@ -1234,7 +1238,7 @@ int32_t iis3dhhc_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_pin_mode_set(stmdev_ctx_t *ctx, iis3dhhc_pp_od_t val) +int32_t iis3dhhc_pin_mode_set(const stmdev_ctx_t *ctx, iis3dhhc_pp_od_t val) { iis3dhhc_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -1260,7 +1264,7 @@ int32_t iis3dhhc_pin_mode_set(stmdev_ctx_t *ctx, iis3dhhc_pp_od_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_pin_mode_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_pin_mode_get(const stmdev_ctx_t *ctx, iis3dhhc_pp_od_t *val) { iis3dhhc_ctrl_reg4_t ctrl_reg4; @@ -1316,7 +1320,7 @@ int32_t iis3dhhc_pin_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_fifo_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dhhc_fifo_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dhhc_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -1342,7 +1346,7 @@ int32_t iis3dhhc_fifo_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_fifo_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dhhc_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dhhc_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -1365,7 +1369,7 @@ int32_t iis3dhhc_fifo_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_fifo_block_spi_hs_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dhhc_fifo_block_spi_hs_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dhhc_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1394,7 +1398,7 @@ int32_t iis3dhhc_fifo_block_spi_hs_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_fifo_block_spi_hs_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_fifo_block_spi_hs_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dhhc_ctrl_reg5_t ctrl_reg5; @@ -1415,7 +1419,7 @@ int32_t iis3dhhc_fifo_block_spi_hs_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dhhc_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dhhc_fifo_ctrl_t fifo_ctrl; int32_t ret; @@ -1441,7 +1445,7 @@ int32_t iis3dhhc_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dhhc_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dhhc_fifo_ctrl_t fifo_ctrl; int32_t ret; @@ -1461,7 +1465,7 @@ int32_t iis3dhhc_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t iis3dhhc_fifo_mode_set(const stmdev_ctx_t *ctx, iis3dhhc_fmode_t val) { iis3dhhc_fifo_ctrl_t fifo_ctrl; @@ -1488,7 +1492,7 @@ int32_t iis3dhhc_fifo_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_fifo_mode_get(const stmdev_ctx_t *ctx, iis3dhhc_fmode_t *val) { iis3dhhc_fifo_ctrl_t fifo_ctrl; @@ -1535,7 +1539,7 @@ int32_t iis3dhhc_fifo_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_fifo_status_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_fifo_status_get(const stmdev_ctx_t *ctx, iis3dhhc_fifo_src_t *val) { int32_t ret; @@ -1553,7 +1557,7 @@ int32_t iis3dhhc_fifo_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dhhc_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dhhc_fifo_src_t fifo_src; int32_t ret; @@ -1572,7 +1576,7 @@ int32_t iis3dhhc_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dhhc_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dhhc_fifo_src_t fifo_src; int32_t ret; @@ -1591,7 +1595,7 @@ int32_t iis3dhhc_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dhhc_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dhhc_fifo_src_t fifo_src; int32_t ret; @@ -1624,7 +1628,7 @@ int32_t iis3dhhc_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_auto_add_inc_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dhhc_auto_add_inc_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dhhc_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -1651,7 +1655,7 @@ int32_t iis3dhhc_auto_add_inc_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dhhc_auto_add_inc_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dhhc_auto_add_inc_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dhhc_ctrl_reg1_t ctrl_reg1; int32_t ret; diff --git a/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.h b/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.h index 03f7939c..8219a5ed 100644 --- a/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.h +++ b/sensor/stmemsc/iis3dhhc_STdC/driver/iis3dhhc_reg.h @@ -385,19 +385,19 @@ typedef union * them with a custom implementation. */ -int32_t iis3dhhc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t iis3dhhc_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t iis3dhhc_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t iis3dhhc_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); float_t iis3dhhc_from_lsb_to_mg(int16_t lsb); float_t iis3dhhc_from_lsb_to_celsius(int16_t lsb); -int32_t iis3dhhc_block_data_update_set(stmdev_ctx_t *ctx, +int32_t iis3dhhc_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dhhc_block_data_update_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -405,31 +405,31 @@ typedef enum IIS3DHHC_POWER_DOWN = 0, IIS3DHHC_1kHz1 = 1, } iis3dhhc_norm_mod_en_t; -int32_t iis3dhhc_data_rate_set(stmdev_ctx_t *ctx, +int32_t iis3dhhc_data_rate_set(const stmdev_ctx_t *ctx, iis3dhhc_norm_mod_en_t val); -int32_t iis3dhhc_data_rate_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_data_rate_get(const stmdev_ctx_t *ctx, iis3dhhc_norm_mod_en_t *val); -int32_t iis3dhhc_offset_temp_comp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dhhc_offset_temp_comp_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_offset_temp_comp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis3dhhc_offset_temp_comp_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dhhc_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t iis3dhhc_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t iis3dhhc_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t iis3dhhc_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis3dhhc_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dhhc_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis3dhhc_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dhhc_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t iis3dhhc_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t iis3dhhc_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dhhc_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis3dhhc_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis3dhhc_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dhhc_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dhhc_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis3dhhc_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis3dhhc_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -437,8 +437,8 @@ typedef enum IIS3DHHC_ST_POSITIVE = 1, IIS3DHHC_ST_NEGATIVE = 2, } iis3dhhc_st_t; -int32_t iis3dhhc_self_test_set(stmdev_ctx_t *ctx, iis3dhhc_st_t val); -int32_t iis3dhhc_self_test_get(stmdev_ctx_t *ctx, iis3dhhc_st_t *val); +int32_t iis3dhhc_self_test_set(const stmdev_ctx_t *ctx, iis3dhhc_st_t val); +int32_t iis3dhhc_self_test_get(const stmdev_ctx_t *ctx, iis3dhhc_st_t *val); typedef enum { @@ -447,12 +447,12 @@ typedef enum IIS3DHHC_NO_LINEAR_PHASE_440Hz = 2, IIS3DHHC_NO_LINEAR_PHASE_235Hz = 3, } iis3dhhc_dsp_t; -int32_t iis3dhhc_filter_config_set(stmdev_ctx_t *ctx, +int32_t iis3dhhc_filter_config_set(const stmdev_ctx_t *ctx, iis3dhhc_dsp_t val); -int32_t iis3dhhc_filter_config_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_filter_config_get(const stmdev_ctx_t *ctx, iis3dhhc_dsp_t *val); -int32_t iis3dhhc_status_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_status_get(const stmdev_ctx_t *ctx, iis3dhhc_status_t *val); typedef enum @@ -460,9 +460,9 @@ typedef enum IIS3DHHC_LATCHED = 0, IIS3DHHC_PULSED = 1, } iis3dhhc_drdy_pulse_t; -int32_t iis3dhhc_drdy_notification_mode_set(stmdev_ctx_t *ctx, +int32_t iis3dhhc_drdy_notification_mode_set(const stmdev_ctx_t *ctx, iis3dhhc_drdy_pulse_t val); -int32_t iis3dhhc_drdy_notification_mode_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_drdy_notification_mode_get(const stmdev_ctx_t *ctx, iis3dhhc_drdy_pulse_t *val); typedef enum @@ -470,50 +470,50 @@ typedef enum IIS3DHHC_PIN_AS_INTERRUPT = 0, IIS3DHHC_PIN_AS_TRIGGER = 1, } iis3dhhc_int1_ext_t; -int32_t iis3dhhc_int1_mode_set(stmdev_ctx_t *ctx, +int32_t iis3dhhc_int1_mode_set(const stmdev_ctx_t *ctx, iis3dhhc_int1_ext_t val); -int32_t iis3dhhc_int1_mode_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_int1_mode_get(const stmdev_ctx_t *ctx, iis3dhhc_int1_ext_t *val); -int32_t iis3dhhc_fifo_threshold_on_int1_set(stmdev_ctx_t *ctx, +int32_t iis3dhhc_fifo_threshold_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dhhc_fifo_threshold_on_int1_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_fifo_threshold_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dhhc_fifo_full_on_int1_set(stmdev_ctx_t *ctx, +int32_t iis3dhhc_fifo_full_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dhhc_fifo_full_on_int1_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_fifo_full_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dhhc_fifo_ovr_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dhhc_fifo_ovr_on_int1_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_fifo_ovr_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis3dhhc_fifo_ovr_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dhhc_boot_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dhhc_boot_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis3dhhc_boot_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis3dhhc_boot_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dhhc_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dhhc_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis3dhhc_drdy_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis3dhhc_drdy_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dhhc_fifo_threshold_on_int2_set(stmdev_ctx_t *ctx, +int32_t iis3dhhc_fifo_threshold_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dhhc_fifo_threshold_on_int2_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_fifo_threshold_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dhhc_fifo_full_on_int2_set(stmdev_ctx_t *ctx, +int32_t iis3dhhc_fifo_full_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dhhc_fifo_full_on_int2_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_fifo_full_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dhhc_fifo_ovr_on_int2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dhhc_fifo_ovr_on_int2_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_fifo_ovr_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis3dhhc_fifo_ovr_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dhhc_boot_on_int2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dhhc_boot_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis3dhhc_boot_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis3dhhc_boot_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dhhc_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dhhc_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis3dhhc_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis3dhhc_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -522,21 +522,21 @@ typedef enum IIS3DHHC_INT1_PP_INT2_OD = 2, IIS3DHHC_ALL_OPEN_DRAIN = 3, } iis3dhhc_pp_od_t; -int32_t iis3dhhc_pin_mode_set(stmdev_ctx_t *ctx, +int32_t iis3dhhc_pin_mode_set(const stmdev_ctx_t *ctx, iis3dhhc_pp_od_t val); -int32_t iis3dhhc_pin_mode_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_pin_mode_get(const stmdev_ctx_t *ctx, iis3dhhc_pp_od_t *val); -int32_t iis3dhhc_fifo_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dhhc_fifo_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis3dhhc_fifo_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis3dhhc_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dhhc_fifo_block_spi_hs_set(stmdev_ctx_t *ctx, +int32_t iis3dhhc_fifo_block_spi_hs_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dhhc_fifo_block_spi_hs_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_fifo_block_spi_hs_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dhhc_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dhhc_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis3dhhc_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis3dhhc_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -546,22 +546,22 @@ typedef enum IIS3DHHC_BYPASS_TO_STREAM_MODE = 4, IIS3DHHC_DYNAMIC_STREAM_MODE = 6, } iis3dhhc_fmode_t; -int32_t iis3dhhc_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t iis3dhhc_fifo_mode_set(const stmdev_ctx_t *ctx, iis3dhhc_fmode_t val); -int32_t iis3dhhc_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_fifo_mode_get(const stmdev_ctx_t *ctx, iis3dhhc_fmode_t *val); -int32_t iis3dhhc_fifo_status_get(stmdev_ctx_t *ctx, +int32_t iis3dhhc_fifo_status_get(const stmdev_ctx_t *ctx, iis3dhhc_fifo_src_t *val); -int32_t iis3dhhc_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis3dhhc_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dhhc_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis3dhhc_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dhhc_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis3dhhc_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dhhc_auto_add_inc_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dhhc_auto_add_inc_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis3dhhc_auto_add_inc_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis3dhhc_auto_add_inc_get(const stmdev_ctx_t *ctx, uint8_t *val); /** *@} diff --git a/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.c b/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.c index 72333990..a56aa68c 100644 --- a/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.c +++ b/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.c @@ -47,10 +47,12 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak iis3dwb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak iis3dwb_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { + if (ctx == NULL) return -1; + return ctx->read_reg(ctx->handle, reg, data, len); } @@ -64,10 +66,12 @@ int32_t __weak iis3dwb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak iis3dwb_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak iis3dwb_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { + if (ctx == NULL) return -1; + return ctx->write_reg(ctx->handle, reg, data, len); } @@ -154,7 +158,7 @@ float_t iis3dwb_from_lsb_to_nsec(int32_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_full_scale_set(const stmdev_ctx_t *ctx, iis3dwb_fs_xl_t val) { iis3dwb_ctrl1_xl_t ctrl1_xl; @@ -179,7 +183,7 @@ int32_t iis3dwb_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_full_scale_get(const stmdev_ctx_t *ctx, iis3dwb_fs_xl_t *val) { iis3dwb_ctrl1_xl_t ctrl1_xl; @@ -220,7 +224,7 @@ int32_t iis3dwb_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_data_rate_set(const stmdev_ctx_t *ctx, iis3dwb_odr_xl_t val) { iis3dwb_ctrl1_xl_t ctrl1_xl; @@ -245,7 +249,7 @@ int32_t iis3dwb_xl_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_data_rate_get(const stmdev_ctx_t *ctx, iis3dwb_odr_xl_t *val) { iis3dwb_ctrl1_xl_t ctrl1_xl; @@ -278,7 +282,7 @@ int32_t iis3dwb_xl_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dwb_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_ctrl3_c_t ctrl3_c; @@ -301,7 +305,7 @@ int32_t iis3dwb_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dwb_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_ctrl3_c_t ctrl3_c; @@ -320,7 +324,7 @@ int32_t iis3dwb_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_offset_weight_set(const stmdev_ctx_t *ctx, iis3dwb_usr_off_w_t val) { iis3dwb_ctrl6_c_t ctrl6_c; @@ -345,7 +349,7 @@ int32_t iis3dwb_xl_offset_weight_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_offset_weight_get(const stmdev_ctx_t *ctx, iis3dwb_usr_off_w_t *val) { iis3dwb_ctrl6_c_t ctrl6_c; @@ -379,7 +383,7 @@ int32_t iis3dwb_xl_offset_weight_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_xl_axis_selection_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_axis_selection_set(const stmdev_ctx_t *ctx, iis3dwb_xl_axis_sel_t val) { iis3dwb_ctrl4_c_t ctrl4_c; @@ -416,17 +420,17 @@ int32_t iis3dwb_xl_axis_selection_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_xl_axis_selection_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_axis_selection_get(const stmdev_ctx_t *ctx, iis3dwb_xl_axis_sel_t *val) { iis3dwb_ctrl4_c_t ctrl4_c; iis3dwb_ctrl6_c_t ctrl6_c; - + *val = IIS3DWB_ENABLE_ALL; int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL4_C, (uint8_t *)&ctrl4_c, 1); if (ret != 0) { return ret; } - + ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL6_C, (uint8_t *)&ctrl6_c, 1); if (ret != 0) { return ret; } @@ -477,7 +481,7 @@ int32_t iis3dwb_xl_axis_selection_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_all_sources_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_all_sources_get(const stmdev_ctx_t *ctx, iis3dwb_all_sources_t *val) { int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_ALL_INT_SRC, @@ -506,7 +510,7 @@ int32_t iis3dwb_all_sources_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_status_reg_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_status_reg_get(const stmdev_ctx_t *ctx, iis3dwb_status_reg_t *val) { const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_STATUS_REG, (uint8_t *) val, 1); @@ -522,7 +526,7 @@ int32_t iis3dwb_status_reg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_status_reg_t status_reg; @@ -542,7 +546,7 @@ int32_t iis3dwb_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_status_reg_t status_reg; @@ -555,7 +559,7 @@ int32_t iis3dwb_temp_flag_data_ready_get(stmdev_ctx_t *ctx, } /** - * @brief Enables the accelerometer user offset correction block, can be enabled + * @brief Enables the accelerometer user offset correction block, can be enabled * by setting the USR_OFF_ON_OUT bit of the CTRL7_C register.[set] * * @param ctx Read / write interface definitions.(ptr) @@ -563,7 +567,7 @@ int32_t iis3dwb_temp_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_usr_offset_block_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dwb_usr_offset_block_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_ctrl7_c_t ctrl7_c; @@ -579,7 +583,7 @@ int32_t iis3dwb_usr_offset_block_set(stmdev_ctx_t *ctx, uint8_t val) } /** - * @brief Enables the accelerometer user offset correction block, can be enabled + * @brief Enables the accelerometer user offset correction block, can be enabled * by setting the USR_OFF_ON_OUT bit of the CTRL7_C register.[get] * * @param ctx Read / write interface definitions.(ptr) @@ -587,7 +591,7 @@ int32_t iis3dwb_usr_offset_block_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_usr_offset_block_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dwb_usr_offset_block_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_ctrl7_c_t ctrl7_c; @@ -607,7 +611,7 @@ int32_t iis3dwb_usr_offset_block_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis3dwb_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) { const int32_t ret = iis3dwb_write_reg(ctx, IIS3DWB_X_OFS_USR, buff, 1); @@ -624,7 +628,7 @@ int32_t iis3dwb_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis3dwb_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) { const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_X_OFS_USR, buff, 1); @@ -641,7 +645,7 @@ int32_t iis3dwb_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis3dwb_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) { const int32_t ret = iis3dwb_write_reg(ctx, IIS3DWB_Y_OFS_USR, buff, 1); @@ -658,7 +662,7 @@ int32_t iis3dwb_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis3dwb_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) { const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_Y_OFS_USR, buff, 1); @@ -675,7 +679,7 @@ int32_t iis3dwb_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis3dwb_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) { const int32_t ret = iis3dwb_write_reg(ctx, IIS3DWB_Z_OFS_USR, buff, 1); @@ -692,7 +696,7 @@ int32_t iis3dwb_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis3dwb_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff) { const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_Z_OFS_USR, buff, 1); @@ -719,7 +723,7 @@ int32_t iis3dwb_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_timestamp_rst(stmdev_ctx_t *ctx) +int32_t iis3dwb_timestamp_rst(const stmdev_ctx_t *ctx) { uint8_t rst_val = 0xAA; return iis3dwb_write_reg(ctx, IIS3DWB_TIMESTAMP2, &rst_val, 1); @@ -733,7 +737,7 @@ int32_t iis3dwb_timestamp_rst(stmdev_ctx_t *ctx) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dwb_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_ctrl10_c_t ctrl10_c; @@ -757,7 +761,7 @@ int32_t iis3dwb_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dwb_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_ctrl10_c_t ctrl10_c; @@ -777,7 +781,7 @@ int32_t iis3dwb_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t iis3dwb_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; @@ -810,7 +814,7 @@ int32_t iis3dwb_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_rounding_mode_set(const stmdev_ctx_t *ctx, iis3dwb_rounding_t val) { iis3dwb_ctrl5_c_t ctrl5_c; @@ -834,7 +838,7 @@ int32_t iis3dwb_rounding_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_rounding_mode_get(const stmdev_ctx_t *ctx, iis3dwb_rounding_t *val) { iis3dwb_ctrl5_c_t ctrl5_c; @@ -869,7 +873,7 @@ int32_t iis3dwb_rounding_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t iis3dwb_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; @@ -889,7 +893,7 @@ int32_t iis3dwb_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t iis3dwb_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -912,7 +916,7 @@ int32_t iis3dwb_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_fifo_out_raw_get(stmdev_ctx_t *ctx, iis3dwb_fifo_out_raw_t *val) +int32_t iis3dwb_fifo_out_raw_get(const stmdev_ctx_t *ctx, iis3dwb_fifo_out_raw_t *val) { const int32_t ret = iis3dwb_fifo_out_multi_raw_get(ctx, val, 1); @@ -928,7 +932,7 @@ int32_t iis3dwb_fifo_out_raw_get(stmdev_ctx_t *ctx, iis3dwb_fifo_out_raw_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_fifo_out_multi_raw_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_fifo_out_multi_raw_get(const stmdev_ctx_t *ctx, iis3dwb_fifo_out_raw_t *fdata, uint16_t num) { @@ -948,7 +952,7 @@ int32_t iis3dwb_fifo_out_multi_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_fifo_sensor_tag_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, iis3dwb_fifo_tag_t *val) { iis3dwb_fifo_data_out_tag_t fifo_data_out_tag; @@ -1000,7 +1004,7 @@ int32_t iis3dwb_fifo_sensor_tag_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dwb_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_internal_freq_fine_t internal_freq_fine; @@ -1027,7 +1031,7 @@ int32_t iis3dwb_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dwb_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_internal_freq_fine_t internal_freq_fine; @@ -1047,7 +1051,7 @@ int32_t iis3dwb_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_data_ready_mode_set(const stmdev_ctx_t *ctx, iis3dwb_dataready_pulsed_t val) { iis3dwb_counter_bdr_reg1_t counter_bdr_reg1; @@ -1074,7 +1078,7 @@ int32_t iis3dwb_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_data_ready_mode_get(const stmdev_ctx_t *ctx, iis3dwb_dataready_pulsed_t *val) { iis3dwb_counter_bdr_reg1_t counter_bdr_reg1; @@ -1108,7 +1112,7 @@ int32_t iis3dwb_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t iis3dwb_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_WHO_AM_I, buff, 1); @@ -1116,14 +1120,14 @@ int32_t iis3dwb_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) } /** - * @brief Software reset. Restore the default values in user registers.[set] + * @brief Software reset.[set] * * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of sw_reset in reg CTRL3_C + * @param val Value of sw_reset in reg CTRL3_C * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dwb_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_ctrl3_c_t ctrl3_c; @@ -1139,14 +1143,14 @@ int32_t iis3dwb_reset_set(stmdev_ctx_t *ctx, uint8_t val) } /** - * @brief Software reset. Restore the default values in user registers.[get] + * @brief Software reset.[get] * * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of sw_reset in reg CTRL3_C + * @param val Value of sw_reset in reg CTRL3_C * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dwb_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_ctrl3_c_t ctrl3_c; @@ -1165,7 +1169,7 @@ int32_t iis3dwb_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dwb_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_ctrl3_c_t ctrl3_c; @@ -1189,7 +1193,7 @@ int32_t iis3dwb_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dwb_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_ctrl3_c_t ctrl3_c; @@ -1200,14 +1204,14 @@ int32_t iis3dwb_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) } /** - * @brief Reboot memory content. Reload the calibration parameters.[set] + * @brief Reboot memory content.[set] * * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of boot in reg CTRL3_C + * @param val Value of boot in reg CTRL3_C * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dwb_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_ctrl3_c_t ctrl3_c; @@ -1223,14 +1227,14 @@ int32_t iis3dwb_boot_set(stmdev_ctx_t *ctx, uint8_t val) } /** - * @brief Reboot memory content. Reload the calibration parameters.[get] + * @brief Reboot memory content.[get] * * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of boot in reg CTRL3_C + * @param val Value of boot in reg CTRL3_C * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dwb_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_ctrl3_c_t ctrl3_c; @@ -1250,7 +1254,7 @@ int32_t iis3dwb_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_self_test_set(const stmdev_ctx_t *ctx, iis3dwb_st_xl_t val) { iis3dwb_ctrl5_c_t ctrl5_c; @@ -1274,7 +1278,7 @@ int32_t iis3dwb_xl_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_self_test_get(const stmdev_ctx_t *ctx, iis3dwb_st_xl_t *val) { iis3dwb_ctrl5_c_t ctrl5_c; @@ -1327,7 +1331,7 @@ int32_t iis3dwb_xl_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_ctrl4_c_t ctrl4_c; @@ -1352,7 +1356,7 @@ int32_t iis3dwb_filter_settling_mask_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_ctrl4_c_t ctrl4_c; @@ -1370,7 +1374,7 @@ int32_t iis3dwb_filter_settling_mask_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_xl_filt_path_on_out_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_filt_path_on_out_set(const stmdev_ctx_t *ctx, iis3dwb_filt_xl_en_t val) { iis3dwb_ctrl1_xl_t ctrl1_xl; @@ -1408,17 +1412,17 @@ int32_t iis3dwb_xl_filt_path_on_out_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_xl_filt_path_on_out_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_filt_path_on_out_get(const stmdev_ctx_t *ctx, iis3dwb_filt_xl_en_t *val) { iis3dwb_ctrl1_xl_t ctrl1_xl; iis3dwb_ctrl8_xl_t ctrl8_xl; *val = IIS3DWB_HP_REF_MODE; - + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); if (ret != 0) { return ret; } - + ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); if (ret != 0) { return ret; } @@ -1511,7 +1515,7 @@ int32_t iis3dwb_xl_filt_path_on_out_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dwb_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_ctrl8_xl_t ctrl8_xl; @@ -1537,10 +1541,10 @@ int32_t iis3dwb_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dwb_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_ctrl8_xl_t ctrl8_xl; - + const int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); *val = ctrl8_xl.fastsettl_mode_xl; @@ -1556,7 +1560,7 @@ int32_t iis3dwb_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, iis3dwb_slope_fds_t val) { iis3dwb_slope_en_t int_cfg0; @@ -1582,7 +1586,7 @@ int32_t iis3dwb_xl_hp_path_internal_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, iis3dwb_slope_fds_t *val) { iis3dwb_slope_en_t int_cfg0; @@ -1628,7 +1632,7 @@ int32_t iis3dwb_xl_hp_path_internal_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, iis3dwb_sdo_pu_en_t val) { iis3dwb_pin_ctrl_t pin_ctrl; @@ -1652,7 +1656,7 @@ int32_t iis3dwb_sdo_sa0_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, iis3dwb_sdo_pu_en_t *val) { iis3dwb_pin_ctrl_t pin_ctrl; @@ -1685,7 +1689,7 @@ int32_t iis3dwb_sdo_sa0_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_spi_mode_set(stmdev_ctx_t *ctx, iis3dwb_sim_t val) +int32_t iis3dwb_spi_mode_set(const stmdev_ctx_t *ctx, iis3dwb_sim_t val) { iis3dwb_ctrl3_c_t ctrl3_c; @@ -1708,7 +1712,7 @@ int32_t iis3dwb_spi_mode_set(stmdev_ctx_t *ctx, iis3dwb_sim_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_spi_mode_get(stmdev_ctx_t *ctx, iis3dwb_sim_t *val) +int32_t iis3dwb_spi_mode_get(const stmdev_ctx_t *ctx, iis3dwb_sim_t *val) { iis3dwb_ctrl3_c_t ctrl3_c; @@ -1740,7 +1744,7 @@ int32_t iis3dwb_spi_mode_get(stmdev_ctx_t *ctx, iis3dwb_sim_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_i2c_interface_set(const stmdev_ctx_t *ctx, iis3dwb_i2c_disable_t val) { iis3dwb_ctrl4_c_t ctrl4_c; @@ -1764,7 +1768,7 @@ int32_t iis3dwb_i2c_interface_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_i2c_interface_get(const stmdev_ctx_t *ctx, iis3dwb_i2c_disable_t *val) { iis3dwb_ctrl4_c_t ctrl4_c; @@ -1810,7 +1814,7 @@ int32_t iis3dwb_i2c_interface_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_pin_int1_route_set(const stmdev_ctx_t *ctx, iis3dwb_pin_int1_route_t *val) { iis3dwb_int1_ctrl_t int1_ctrl; @@ -1819,7 +1823,7 @@ int32_t iis3dwb_pin_int1_route_set(stmdev_ctx_t *ctx, int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); if (ret != 0) { return ret; } - + ret = iis3dwb_read_reg(ctx, IIS3DWB_MD1_CFG, (uint8_t *)&md1_cfg, 1); if (ret != 0) { return ret; } @@ -1855,7 +1859,7 @@ int32_t iis3dwb_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_pin_int1_route_get(const stmdev_ctx_t *ctx, iis3dwb_pin_int1_route_t *val) { iis3dwb_int1_ctrl_t int1_ctrl; @@ -1863,10 +1867,10 @@ int32_t iis3dwb_pin_int1_route_get(stmdev_ctx_t *ctx, iis3dwb_md1_cfg_t md1_cfg; memset(val, 0, sizeof(iis3dwb_pin_int1_route_t)); - + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); if (ret != 0) { return ret; } - + ret = iis3dwb_read_reg(ctx, IIS3DWB_MD1_CFG, (uint8_t *)&md1_cfg, 1); if (ret != 0) { return ret; } @@ -1903,7 +1907,7 @@ int32_t iis3dwb_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_pin_int2_route_set(const stmdev_ctx_t *ctx, iis3dwb_pin_int2_route_t *val) { iis3dwb_int2_ctrl_t int2_ctrl; @@ -1912,7 +1916,7 @@ int32_t iis3dwb_pin_int2_route_set(stmdev_ctx_t *ctx, int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); if (ret != 0) { return ret; } - + ret = iis3dwb_read_reg(ctx, IIS3DWB_MD2_CFG, (uint8_t *)&md2_cfg, 1); if (ret != 0) { return ret; } @@ -1949,18 +1953,18 @@ int32_t iis3dwb_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_pin_int2_route_get(const stmdev_ctx_t *ctx, iis3dwb_pin_int2_route_t *val) { iis3dwb_int2_ctrl_t int2_ctrl; iis3dwb_slope_en_t slope_en; iis3dwb_md2_cfg_t md2_cfg; - + memset(val, 0, sizeof(iis3dwb_pin_int2_route_t)); int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); if (ret != 0) { return ret; } - + ret = iis3dwb_read_reg(ctx, IIS3DWB_MD2_CFG, (uint8_t *)&md2_cfg, 1); if (ret != 0) { return ret; } @@ -1998,7 +2002,7 @@ int32_t iis3dwb_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_pin_mode_set(stmdev_ctx_t *ctx, iis3dwb_pp_od_t val) +int32_t iis3dwb_pin_mode_set(const stmdev_ctx_t *ctx, iis3dwb_pp_od_t val) { iis3dwb_ctrl3_c_t ctrl3_c; @@ -2021,7 +2025,7 @@ int32_t iis3dwb_pin_mode_set(stmdev_ctx_t *ctx, iis3dwb_pp_od_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_pin_mode_get(stmdev_ctx_t *ctx, iis3dwb_pp_od_t *val) +int32_t iis3dwb_pin_mode_get(const stmdev_ctx_t *ctx, iis3dwb_pp_od_t *val) { iis3dwb_ctrl3_c_t ctrl3_c; @@ -2053,7 +2057,7 @@ int32_t iis3dwb_pin_mode_get(stmdev_ctx_t *ctx, iis3dwb_pp_od_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_pin_polarity_set(const stmdev_ctx_t *ctx, iis3dwb_h_lactive_t val) { iis3dwb_ctrl3_c_t ctrl3_c; @@ -2077,7 +2081,7 @@ int32_t iis3dwb_pin_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_pin_polarity_get(const stmdev_ctx_t *ctx, iis3dwb_h_lactive_t *val) { iis3dwb_ctrl3_c_t ctrl3_c; @@ -2110,7 +2114,7 @@ int32_t iis3dwb_pin_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dwb_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_ctrl4_c_t ctrl4_c; @@ -2133,7 +2137,7 @@ int32_t iis3dwb_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dwb_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_ctrl4_c_t ctrl4_c; @@ -2151,7 +2155,7 @@ int32_t iis3dwb_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_int_notification_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_int_notification_set(const stmdev_ctx_t *ctx, iis3dwb_lir_t val) { iis3dwb_slope_en_t slope_en; @@ -2175,7 +2179,7 @@ int32_t iis3dwb_int_notification_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_int_notification_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_int_notification_get(const stmdev_ctx_t *ctx, iis3dwb_lir_t *val) { iis3dwb_slope_en_t slope_en; @@ -2223,7 +2227,7 @@ int32_t iis3dwb_int_notification_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_wkup_ths_weight_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_wkup_ths_weight_set(const stmdev_ctx_t *ctx, iis3dwb_wake_ths_w_t val) { iis3dwb_wake_up_dur_t wake_up_dur; @@ -2251,7 +2255,7 @@ int32_t iis3dwb_wkup_ths_weight_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_wkup_ths_weight_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_wkup_ths_weight_get(const stmdev_ctx_t *ctx, iis3dwb_wake_ths_w_t *val) { iis3dwb_wake_up_dur_t wake_up_dur; @@ -2287,7 +2291,7 @@ int32_t iis3dwb_wkup_ths_weight_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dwb_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_interrupts_en_t interrupts_en; iis3dwb_wake_up_ths_t wake_up_ths; @@ -2327,7 +2331,7 @@ int32_t iis3dwb_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dwb_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_wake_up_ths_t wake_up_ths; @@ -2346,7 +2350,7 @@ int32_t iis3dwb_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_wake_up_ths_t wake_up_ths; @@ -2372,7 +2376,7 @@ int32_t iis3dwb_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_wake_up_ths_t wake_up_ths; @@ -2392,7 +2396,7 @@ int32_t iis3dwb_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dwb_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_wake_up_dur_t wake_up_dur; @@ -2417,7 +2421,7 @@ int32_t iis3dwb_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dwb_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_wake_up_dur_t wake_up_dur; @@ -2449,7 +2453,7 @@ int32_t iis3dwb_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dwb_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_wake_up_dur_t wake_up_dur; @@ -2474,7 +2478,7 @@ int32_t iis3dwb_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dwb_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_wake_up_dur_t wake_up_dur; @@ -2506,7 +2510,7 @@ int32_t iis3dwb_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t iis3dwb_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val) { iis3dwb_fifo_ctrl1_t fifo_ctrl1; iis3dwb_fifo_ctrl2_t fifo_ctrl2; @@ -2539,17 +2543,17 @@ int32_t iis3dwb_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t iis3dwb_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) { iis3dwb_fifo_ctrl1_t fifo_ctrl1; iis3dwb_fifo_ctrl2_t fifo_ctrl2; *val = 0; - + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); if (ret != 0) { return ret; } - + ret = iis3dwb_read_reg(ctx, IIS3DWB_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); @@ -2569,7 +2573,7 @@ int32_t iis3dwb_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dwb_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_fifo_ctrl2_t fifo_ctrl2; @@ -2595,7 +2599,7 @@ int32_t iis3dwb_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dwb_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_fifo_ctrl2_t fifo_ctrl2; @@ -2615,7 +2619,7 @@ int32_t iis3dwb_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_fifo_xl_batch_set(const stmdev_ctx_t *ctx, iis3dwb_bdr_xl_t val) { iis3dwb_fifo_ctrl3_t fifo_ctrl3; @@ -2642,7 +2646,7 @@ int32_t iis3dwb_fifo_xl_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_fifo_xl_batch_get(const stmdev_ctx_t *ctx, iis3dwb_bdr_xl_t *val) { iis3dwb_fifo_ctrl3_t fifo_ctrl3; @@ -2676,7 +2680,7 @@ int32_t iis3dwb_fifo_xl_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_fifo_mode_set(const stmdev_ctx_t *ctx, iis3dwb_fifo_mode_t val) { iis3dwb_fifo_ctrl4_t fifo_ctrl4; @@ -2702,7 +2706,7 @@ int32_t iis3dwb_fifo_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_fifo_mode_get(const stmdev_ctx_t *ctx, iis3dwb_fifo_mode_t *val) { iis3dwb_fifo_ctrl4_t fifo_ctrl4; @@ -2753,7 +2757,7 @@ int32_t iis3dwb_fifo_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_fifo_temp_batch_set(const stmdev_ctx_t *ctx, iis3dwb_odr_t_batch_t val) { iis3dwb_fifo_ctrl4_t fifo_ctrl4; @@ -2780,7 +2784,7 @@ int32_t iis3dwb_fifo_temp_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_fifo_temp_batch_get(const stmdev_ctx_t *ctx, iis3dwb_odr_t_batch_t *val) { iis3dwb_fifo_ctrl4_t fifo_ctrl4; @@ -2816,7 +2820,7 @@ int32_t iis3dwb_fifo_temp_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_fifo_timestamp_batch_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx, iis3dwb_fifo_timestamp_batch_t val) { iis3dwb_fifo_ctrl4_t fifo_ctrl4; @@ -2845,7 +2849,7 @@ int32_t iis3dwb_fifo_timestamp_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_fifo_timestamp_batch_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, iis3dwb_fifo_timestamp_batch_t *val) { iis3dwb_fifo_ctrl4_t fifo_ctrl4; @@ -2888,7 +2892,7 @@ int32_t iis3dwb_fifo_timestamp_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t iis3dwb_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val) { iis3dwb_counter_bdr_reg1_t counter_bdr_reg1; @@ -2914,7 +2918,7 @@ int32_t iis3dwb_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t iis3dwb_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val) { iis3dwb_counter_bdr_reg1_t counter_bdr_reg1; @@ -2934,7 +2938,7 @@ int32_t iis3dwb_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_batch_counter_threshold_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { iis3dwb_counter_bdr_reg2_t counter_bdr_reg1; @@ -2969,18 +2973,18 @@ int32_t iis3dwb_batch_counter_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { iis3dwb_counter_bdr_reg1_t counter_bdr_reg1; iis3dwb_counter_bdr_reg2_t counter_bdr_reg2; *val = 0; - + int32_t ret = iis3dwb_read_reg(ctx, IIS3DWB_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); if (ret != 0) { return ret; } - + ret = iis3dwb_read_reg(ctx, IIS3DWB_COUNTER_BDR_REG2, (uint8_t *)&counter_bdr_reg2, 1); if (ret != 0) { return ret; } @@ -3000,7 +3004,7 @@ int32_t iis3dwb_batch_counter_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t iis3dwb_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) { iis3dwb_fifo_status1_t fifo_status1; iis3dwb_fifo_status2_t fifo_status2; @@ -3028,7 +3032,7 @@ int32_t iis3dwb_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t iis3dwb_fifo_status_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_fifo_status_get(const stmdev_ctx_t *ctx, iis3dwb_fifo_status_t *val) { uint8_t buff[2]; diff --git a/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.h b/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.h index 564cc41b..f46bf048 100644 --- a/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.h +++ b/sensor/stmemsc/iis3dwb_STdC/driver/iis3dwb_reg.h @@ -746,10 +746,10 @@ typedef union * them with a custom implementation. */ -int32_t iis3dwb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t iis3dwb_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t iis3dwb_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t iis3dwb_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -769,9 +769,9 @@ typedef enum IIS3DWB_4g = 2, IIS3DWB_8g = 3, } iis3dwb_fs_xl_t; -int32_t iis3dwb_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_full_scale_set(const stmdev_ctx_t *ctx, iis3dwb_fs_xl_t val); -int32_t iis3dwb_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_full_scale_get(const stmdev_ctx_t *ctx, iis3dwb_fs_xl_t *val); typedef enum @@ -779,13 +779,13 @@ typedef enum IIS3DWB_XL_ODR_OFF = 0, IIS3DWB_XL_ODR_26k7Hz = 5, } iis3dwb_odr_xl_t; -int32_t iis3dwb_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_data_rate_set(const stmdev_ctx_t *ctx, iis3dwb_odr_xl_t val); -int32_t iis3dwb_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_data_rate_get(const stmdev_ctx_t *ctx, iis3dwb_odr_xl_t *val); -int32_t iis3dwb_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dwb_block_data_update_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis3dwb_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -793,9 +793,9 @@ typedef enum IIS3DWB_LSb_1mg = 0, IIS3DWB_LSb_16mg = 1, } iis3dwb_usr_off_w_t; -int32_t iis3dwb_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_offset_weight_set(const stmdev_ctx_t *ctx, iis3dwb_usr_off_w_t val); -int32_t iis3dwb_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_offset_weight_get(const stmdev_ctx_t *ctx, iis3dwb_usr_off_w_t *val); typedef enum @@ -808,9 +808,9 @@ typedef enum IIS3DWB_ONLY_Y_ON_ALL_OUT_REG = 0x12, IIS3DWB_ONLY_Z_ON_ALL_OUT_REG = 0x13, } iis3dwb_xl_axis_sel_t; -int32_t iis3dwb_xl_axis_selection_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_axis_selection_set(const stmdev_ctx_t *ctx, iis3dwb_xl_axis_sel_t val); -int32_t iis3dwb_xl_axis_selection_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_axis_selection_get(const stmdev_ctx_t *ctx, iis3dwb_xl_axis_sel_t *val); typedef struct @@ -819,77 +819,77 @@ typedef struct iis3dwb_wake_up_src_t wake_up_src; iis3dwb_status_reg_t status_reg; } iis3dwb_all_sources_t; -int32_t iis3dwb_all_sources_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_all_sources_get(const stmdev_ctx_t *ctx, iis3dwb_all_sources_t *val); -int32_t iis3dwb_status_reg_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_status_reg_get(const stmdev_ctx_t *ctx, iis3dwb_status_reg_t *val); -int32_t iis3dwb_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dwb_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dwb_usr_offset_block_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dwb_usr_offset_block_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis3dwb_usr_offset_block_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis3dwb_usr_offset_block_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dwb_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t iis3dwb_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t iis3dwb_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t iis3dwb_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t iis3dwb_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t iis3dwb_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t iis3dwb_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t iis3dwb_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t iis3dwb_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t iis3dwb_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t iis3dwb_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t iis3dwb_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t iis3dwb_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dwb_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis3dwb_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis3dwb_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dwb_timestamp_rst(stmdev_ctx_t *ctx); +int32_t iis3dwb_timestamp_rst(const stmdev_ctx_t *ctx); -int32_t iis3dwb_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dwb_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis3dwb_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis3dwb_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dwb_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); +int32_t iis3dwb_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); typedef enum { IIS3DWB_NO_ROUND = 0, IIS3DWB_ROUND = 1, } iis3dwb_rounding_t; -int32_t iis3dwb_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_rounding_mode_set(const stmdev_ctx_t *ctx, iis3dwb_rounding_t val); -int32_t iis3dwb_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_rounding_mode_get(const stmdev_ctx_t *ctx, iis3dwb_rounding_t *val); -int32_t iis3dwb_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t iis3dwb_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t iis3dwb_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t iis3dwb_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t iis3dwb_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dwb_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis3dwb_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis3dwb_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { IIS3DWB_DRDY_LATCHED = 0, IIS3DWB_DRDY_PULSED = 1, } iis3dwb_dataready_pulsed_t; -int32_t iis3dwb_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_data_ready_mode_set(const stmdev_ctx_t *ctx, iis3dwb_dataready_pulsed_t val); -int32_t iis3dwb_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_data_ready_mode_get(const stmdev_ctx_t *ctx, iis3dwb_dataready_pulsed_t *val); -int32_t iis3dwb_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t iis3dwb_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t iis3dwb_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dwb_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis3dwb_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis3dwb_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dwb_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dwb_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis3dwb_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis3dwb_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dwb_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dwb_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis3dwb_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis3dwb_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -897,14 +897,14 @@ typedef enum IIS3DWB_XL_ST_POSITIVE = 1, IIS3DWB_XL_ST_NEGATIVE = 2, } iis3dwb_st_xl_t; -int32_t iis3dwb_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_self_test_set(const stmdev_ctx_t *ctx, iis3dwb_st_xl_t val); -int32_t iis3dwb_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_self_test_get(const stmdev_ctx_t *ctx, iis3dwb_st_xl_t *val); -int32_t iis3dwb_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dwb_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -928,22 +928,22 @@ typedef enum IIS3DWB_LP_ODR_DIV_400 = 0x86, IIS3DWB_LP_ODR_DIV_800 = 0x87, } iis3dwb_filt_xl_en_t; -int32_t iis3dwb_xl_filt_path_on_out_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_filt_path_on_out_set(const stmdev_ctx_t *ctx, iis3dwb_filt_xl_en_t val); -int32_t iis3dwb_xl_filt_path_on_out_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_filt_path_on_out_get(const stmdev_ctx_t *ctx, iis3dwb_filt_xl_en_t *val); -int32_t iis3dwb_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dwb_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis3dwb_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis3dwb_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { IIS3DWB_USE_SLOPE = 0, IIS3DWB_USE_HPF = 1, } iis3dwb_slope_fds_t; -int32_t iis3dwb_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, iis3dwb_slope_fds_t val); -int32_t iis3dwb_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, iis3dwb_slope_fds_t *val); typedef enum @@ -951,9 +951,9 @@ typedef enum IIS3DWB_PULL_UP_DISC = 0, IIS3DWB_PULL_UP_CONNECT = 1, } iis3dwb_sdo_pu_en_t; -int32_t iis3dwb_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, iis3dwb_sdo_pu_en_t val); -int32_t iis3dwb_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, iis3dwb_sdo_pu_en_t *val); typedef enum @@ -961,17 +961,17 @@ typedef enum IIS3DWB_SPI_4_WIRE = 0, IIS3DWB_SPI_3_WIRE = 1, } iis3dwb_sim_t; -int32_t iis3dwb_spi_mode_set(stmdev_ctx_t *ctx, iis3dwb_sim_t val); -int32_t iis3dwb_spi_mode_get(stmdev_ctx_t *ctx, iis3dwb_sim_t *val); +int32_t iis3dwb_spi_mode_set(const stmdev_ctx_t *ctx, iis3dwb_sim_t val); +int32_t iis3dwb_spi_mode_get(const stmdev_ctx_t *ctx, iis3dwb_sim_t *val); typedef enum { IIS3DWB_I2C_ENABLE = 0, IIS3DWB_I2C_DISABLE = 1, } iis3dwb_i2c_disable_t; -int32_t iis3dwb_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_i2c_interface_set(const stmdev_ctx_t *ctx, iis3dwb_i2c_disable_t val); -int32_t iis3dwb_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_i2c_interface_get(const stmdev_ctx_t *ctx, iis3dwb_i2c_disable_t *val); typedef struct @@ -987,9 +987,9 @@ uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ uint8_t sleep_status : 1; /* Act/Inact status */ } iis3dwb_pin_int1_route_t; -int32_t iis3dwb_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_pin_int1_route_set(const stmdev_ctx_t *ctx, iis3dwb_pin_int1_route_t *val); -int32_t iis3dwb_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_pin_int1_route_get(const stmdev_ctx_t *ctx, iis3dwb_pin_int1_route_t *val); typedef struct @@ -1005,9 +1005,9 @@ typedef struct uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ uint8_t sleep_status : 1; /* Act/Inact status */ } iis3dwb_pin_int2_route_t; -int32_t iis3dwb_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_pin_int2_route_set(const stmdev_ctx_t *ctx, iis3dwb_pin_int2_route_t *val); -int32_t iis3dwb_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_pin_int2_route_get(const stmdev_ctx_t *ctx, iis3dwb_pin_int2_route_t *val); typedef enum @@ -1015,30 +1015,30 @@ typedef enum IIS3DWB_PUSH_PULL = 0, IIS3DWB_OPEN_DRAIN = 1, } iis3dwb_pp_od_t; -int32_t iis3dwb_pin_mode_set(stmdev_ctx_t *ctx, iis3dwb_pp_od_t val); -int32_t iis3dwb_pin_mode_get(stmdev_ctx_t *ctx, iis3dwb_pp_od_t *val); +int32_t iis3dwb_pin_mode_set(const stmdev_ctx_t *ctx, iis3dwb_pp_od_t val); +int32_t iis3dwb_pin_mode_get(const stmdev_ctx_t *ctx, iis3dwb_pp_od_t *val); typedef enum { IIS3DWB_ACTIVE_HIGH = 0, IIS3DWB_ACTIVE_LOW = 1, } iis3dwb_h_lactive_t; -int32_t iis3dwb_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_pin_polarity_set(const stmdev_ctx_t *ctx, iis3dwb_h_lactive_t val); -int32_t iis3dwb_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_pin_polarity_get(const stmdev_ctx_t *ctx, iis3dwb_h_lactive_t *val); -int32_t iis3dwb_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dwb_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis3dwb_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis3dwb_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { IIS3DWB_INT_PULSED = 0, IIS3DWB_INT_LATCHED = 1, } iis3dwb_lir_t; -int32_t iis3dwb_int_notification_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_int_notification_set(const stmdev_ctx_t *ctx, iis3dwb_lir_t val); -int32_t iis3dwb_int_notification_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_int_notification_get(const stmdev_ctx_t *ctx, iis3dwb_lir_t *val); typedef enum @@ -1046,39 +1046,39 @@ typedef enum IIS3DWB_LSb_FS_DIV_64 = 0, IIS3DWB_LSb_FS_DIV_256 = 1, } iis3dwb_wake_ths_w_t; -int32_t iis3dwb_wkup_ths_weight_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_wkup_ths_weight_set(const stmdev_ctx_t *ctx, iis3dwb_wake_ths_w_t val); -int32_t iis3dwb_wkup_ths_weight_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_wkup_ths_weight_get(const stmdev_ctx_t *ctx, iis3dwb_wake_ths_w_t *val); -int32_t iis3dwb_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dwb_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis3dwb_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis3dwb_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dwb_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dwb_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dwb_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dwb_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis3dwb_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis3dwb_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dwb_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dwb_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis3dwb_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis3dwb_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dwb_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t iis3dwb_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t iis3dwb_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t iis3dwb_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t iis3dwb_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dwb_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t iis3dwb_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis3dwb_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { IIS3DWB_XL_NOT_BATCHED = 0, IIS3DWB_XL_BATCHED_AT_26k7Hz = 10, } iis3dwb_bdr_xl_t; -int32_t iis3dwb_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_fifo_xl_batch_set(const stmdev_ctx_t *ctx, iis3dwb_bdr_xl_t val); -int32_t iis3dwb_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_fifo_xl_batch_get(const stmdev_ctx_t *ctx, iis3dwb_bdr_xl_t *val); typedef enum @@ -1090,9 +1090,9 @@ typedef enum IIS3DWB_STREAM_MODE = 6, IIS3DWB_BYPASS_TO_FIFO_MODE = 7, } iis3dwb_fifo_mode_t; -int32_t iis3dwb_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_fifo_mode_set(const stmdev_ctx_t *ctx, iis3dwb_fifo_mode_t val); -int32_t iis3dwb_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_fifo_mode_get(const stmdev_ctx_t *ctx, iis3dwb_fifo_mode_t *val); typedef enum @@ -1100,9 +1100,9 @@ typedef enum IIS3DWB_TEMP_NOT_BATCHED = 0, IIS3DWB_TEMP_BATCHED_AT_104Hz = 3, } iis3dwb_odr_t_batch_t; -int32_t iis3dwb_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_fifo_temp_batch_set(const stmdev_ctx_t *ctx, iis3dwb_odr_t_batch_t val); -int32_t iis3dwb_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_fifo_temp_batch_get(const stmdev_ctx_t *ctx, iis3dwb_odr_t_batch_t *val); typedef enum @@ -1112,21 +1112,21 @@ typedef enum IIS3DWB_DEC_8 = 2, IIS3DWB_DEC_32 = 3, } iis3dwb_fifo_timestamp_batch_t; -int32_t iis3dwb_fifo_timestamp_batch_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx, iis3dwb_fifo_timestamp_batch_t val); -int32_t iis3dwb_fifo_timestamp_batch_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, iis3dwb_fifo_timestamp_batch_t *val); -int32_t iis3dwb_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t iis3dwb_rst_batch_counter_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t iis3dwb_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t iis3dwb_batch_counter_threshold_set(stmdev_ctx_t *ctx, +int32_t iis3dwb_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t iis3dwb_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t iis3dwb_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t iis3dwb_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef struct { @@ -1136,7 +1136,7 @@ typedef struct uint8_t fifo_ovr : 1; uint8_t fifo_th : 1; } iis3dwb_fifo_status_t; -int32_t iis3dwb_fifo_status_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_fifo_status_get(const stmdev_ctx_t *ctx, iis3dwb_fifo_status_t *val); typedef struct @@ -1144,8 +1144,8 @@ typedef struct uint8_t tag; uint8_t data[6]; } iis3dwb_fifo_out_raw_t; -int32_t iis3dwb_fifo_out_raw_get(stmdev_ctx_t *ctx, iis3dwb_fifo_out_raw_t *val); -int32_t iis3dwb_fifo_out_multi_raw_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_fifo_out_raw_get(const stmdev_ctx_t *ctx, iis3dwb_fifo_out_raw_t *val); +int32_t iis3dwb_fifo_out_multi_raw_get(const stmdev_ctx_t *ctx, iis3dwb_fifo_out_raw_t *fdata, uint16_t num); @@ -1155,7 +1155,7 @@ typedef enum IIS3DWB_TEMPERATURE_TAG, IIS3DWB_TIMESTAMP_TAG, } iis3dwb_fifo_tag_t; -int32_t iis3dwb_fifo_sensor_tag_get(stmdev_ctx_t *ctx, +int32_t iis3dwb_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, iis3dwb_fifo_tag_t *val); /** diff --git a/sensor/stmemsc/ilps22qs_STdC/driver/ilps22qs_reg.c b/sensor/stmemsc/ilps22qs_STdC/driver/ilps22qs_reg.c index 68f01a35..7f958d68 100644 --- a/sensor/stmemsc/ilps22qs_STdC/driver/ilps22qs_reg.c +++ b/sensor/stmemsc/ilps22qs_STdC/driver/ilps22qs_reg.c @@ -46,11 +46,18 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak ilps22qs_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, +int32_t __weak ilps22qs_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); + return ret; } @@ -64,11 +71,18 @@ int32_t __weak ilps22qs_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak ilps22qs_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, +int32_t __weak ilps22qs_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); + return ret; } @@ -145,7 +159,7 @@ float_t ilps22qs_from_lsb_to_mv(int32_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_id_get(stmdev_ctx_t *ctx, ilps22qs_id_t *val) +int32_t ilps22qs_id_get(const stmdev_ctx_t *ctx, ilps22qs_id_t *val) { uint8_t reg; int32_t ret; @@ -164,7 +178,7 @@ int32_t ilps22qs_id_get(stmdev_ctx_t *ctx, ilps22qs_id_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_bus_mode_set(stmdev_ctx_t *ctx, ilps22qs_bus_mode_t *val) +int32_t ilps22qs_bus_mode_set(const stmdev_ctx_t *ctx, ilps22qs_bus_mode_t *val) { ilps22qs_i3c_if_ctrl_t i3c_if_ctrl; ilps22qs_if_ctrl_t if_ctrl; @@ -199,7 +213,7 @@ int32_t ilps22qs_bus_mode_set(stmdev_ctx_t *ctx, ilps22qs_bus_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_bus_mode_get(stmdev_ctx_t *ctx, ilps22qs_bus_mode_t *val) +int32_t ilps22qs_bus_mode_get(const stmdev_ctx_t *ctx, ilps22qs_bus_mode_t *val) { ilps22qs_i3c_if_ctrl_t i3c_if_ctrl; ilps22qs_if_ctrl_t if_ctrl; @@ -219,9 +233,6 @@ int32_t ilps22qs_bus_mode_get(stmdev_ctx_t *ctx, ilps22qs_bus_mode_t *val) case ILPS22QS_SPI_3W: val->interface = ILPS22QS_SPI_3W; break; - case ILPS22QS_SPI_4W: - val->interface = ILPS22QS_SPI_4W; - break; default: val->interface = ILPS22QS_SEL_BY_HW; break; @@ -251,7 +262,7 @@ int32_t ilps22qs_bus_mode_get(stmdev_ctx_t *ctx, ilps22qs_bus_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_init_set(stmdev_ctx_t *ctx, ilps22qs_init_t val) +int32_t ilps22qs_init_set(const stmdev_ctx_t *ctx, ilps22qs_init_t val) { ilps22qs_ctrl_reg2_t ctrl_reg2; ilps22qs_ctrl_reg3_t ctrl_reg3; @@ -302,7 +313,7 @@ int32_t ilps22qs_init_set(stmdev_ctx_t *ctx, ilps22qs_init_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_status_get(stmdev_ctx_t *ctx, ilps22qs_stat_t *val) +int32_t ilps22qs_status_get(const stmdev_ctx_t *ctx, ilps22qs_stat_t *val) { ilps22qs_interrupt_cfg_t interrupt_cfg; ilps22qs_int_source_t int_source; @@ -345,7 +356,7 @@ int32_t ilps22qs_status_get(stmdev_ctx_t *ctx, ilps22qs_stat_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_pin_conf_set(stmdev_ctx_t *ctx, ilps22qs_pin_conf_t *val) +int32_t ilps22qs_pin_conf_set(const stmdev_ctx_t *ctx, ilps22qs_pin_conf_t *val) { ilps22qs_if_ctrl_t if_ctrl; int32_t ret; @@ -370,7 +381,7 @@ int32_t ilps22qs_pin_conf_set(stmdev_ctx_t *ctx, ilps22qs_pin_conf_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_pin_conf_get(stmdev_ctx_t *ctx, ilps22qs_pin_conf_t *val) +int32_t ilps22qs_pin_conf_get(const stmdev_ctx_t *ctx, ilps22qs_pin_conf_t *val) { ilps22qs_if_ctrl_t if_ctrl; int32_t ret; @@ -391,7 +402,7 @@ int32_t ilps22qs_pin_conf_get(stmdev_ctx_t *ctx, ilps22qs_pin_conf_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_all_sources_get(stmdev_ctx_t *ctx, +int32_t ilps22qs_all_sources_get(const stmdev_ctx_t *ctx, ilps22qs_all_sources_t *val) { ilps22qs_fifo_status2_t fifo_status2; @@ -432,7 +443,7 @@ int32_t ilps22qs_all_sources_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_mode_set(stmdev_ctx_t *ctx, ilps22qs_md_t *val) +int32_t ilps22qs_mode_set(const stmdev_ctx_t *ctx, ilps22qs_md_t *val) { ilps22qs_ctrl_reg1_t ctrl_reg1; ilps22qs_ctrl_reg2_t ctrl_reg2; @@ -511,7 +522,7 @@ int32_t ilps22qs_mode_set(stmdev_ctx_t *ctx, ilps22qs_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_mode_get(stmdev_ctx_t *ctx, ilps22qs_md_t *val) +int32_t ilps22qs_mode_get(const stmdev_ctx_t *ctx, ilps22qs_md_t *val) { ilps22qs_ctrl_reg1_t ctrl_reg1; ilps22qs_ctrl_reg2_t ctrl_reg2; @@ -634,7 +645,7 @@ int32_t ilps22qs_mode_get(stmdev_ctx_t *ctx, ilps22qs_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_trigger_sw(stmdev_ctx_t *ctx, ilps22qs_md_t *md) +int32_t ilps22qs_trigger_sw(const stmdev_ctx_t *ctx, ilps22qs_md_t *md) { ilps22qs_ctrl_reg2_t ctrl_reg2; int32_t ret = 0; @@ -659,7 +670,7 @@ int32_t ilps22qs_trigger_sw(stmdev_ctx_t *ctx, ilps22qs_md_t *md) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ilps22qs_ah_qvar_en_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ilps22qs_ah_qvar_en_set(const stmdev_ctx_t *ctx, uint8_t val) { ilps22qs_ctrl_reg3_t ctrl_reg3; int32_t ret; @@ -683,7 +694,7 @@ int32_t ilps22qs_ah_qvar_en_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ilps22qs_ah_qvar_en_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ilps22qs_ah_qvar_en_get(const stmdev_ctx_t *ctx, uint8_t *val) { ilps22qs_ctrl_reg3_t ctrl_reg3; int32_t ret; @@ -699,11 +710,11 @@ int32_t ilps22qs_ah_qvar_en_get(stmdev_ctx_t *ctx, uint8_t *val) * * @param ctx communication interface handler.(ptr) * @param md the sensor conversion parameters.(ptr) - * @param data data retrived from the sensor.(ptr) + * @param data data retrieved from the sensor.(ptr) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_data_get(stmdev_ctx_t *ctx, ilps22qs_md_t *md, +int32_t ilps22qs_data_get(const stmdev_ctx_t *ctx, ilps22qs_md_t *md, ilps22qs_data_t *data) { uint8_t buff[5]; @@ -724,6 +735,29 @@ int32_t ilps22qs_data_get(stmdev_ctx_t *ctx, ilps22qs_md_t *md, /* data is a pressure sample */ switch (md->fs) { + case ILPS22QS_1260hPa: + data->pressure.hpa = ilps22qs_from_fs1260_to_hPa(data->pressure.raw); + break; + case ILPS22QS_4060hPa: + data->pressure.hpa = ilps22qs_from_fs4000_to_hPa(data->pressure.raw); + break; + default: + data->pressure.hpa = 0.0f; + break; + } + data->ah_qvar.lsb = 0; + } + else + { + /* data is a AH_QVAR sample */ + data->ah_qvar.lsb = (data->pressure.raw / 256); /* shift 8bit left */ + data->pressure.hpa = 0.0f; + } + } + else + { + switch (md->fs) + { case ILPS22QS_1260hPa: data->pressure.hpa = ilps22qs_from_fs1260_to_hPa(data->pressure.raw); break; @@ -733,25 +767,6 @@ int32_t ilps22qs_data_get(stmdev_ctx_t *ctx, ilps22qs_md_t *md, default: data->pressure.hpa = 0.0f; break; - } - data->ah_qvar.lsb = 0; - } else { - /* data is a AH_QVAR sample */ - data->ah_qvar.lsb = (data->pressure.raw / 256); /* shift 8bit left */ - data->pressure.hpa = 0.0f; - } - } else { - switch (md->fs) - { - case ILPS22QS_1260hPa: - data->pressure.hpa = ilps22qs_from_fs1260_to_hPa(data->pressure.raw); - break; - case ILPS22QS_4060hPa: - data->pressure.hpa = ilps22qs_from_fs4000_to_hPa(data->pressure.raw); - break; - default: - data->pressure.hpa = 0.0f; - break; } data->ah_qvar.lsb = 0; } @@ -764,16 +779,58 @@ int32_t ilps22qs_data_get(stmdev_ctx_t *ctx, ilps22qs_md_t *md, return ret; } +/** + * @brief Pressure output value.[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps22qs_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff) +{ + int32_t ret; + uint8_t reg[3]; + + ret = ilps22qs_read_reg(ctx, ILPS22QS_PRESS_OUT_XL, reg, 3); + *buff = reg[2]; + *buff = (*buff * 256U) + reg[1]; + *buff = (*buff * 256U) + reg[0]; + *buff *= 256U; + + return ret; +} + +/** + * @brief Temperature output value.[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps22qs_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) +{ + int32_t ret; + uint8_t reg[2]; + + ret = ilps22qs_read_reg(ctx, ILPS22QS_TEMP_OUT_L, reg, 2); + *buff = (int16_t)reg[1]; + *buff = (*buff * 256) + (int16_t)reg[0]; + + return ret; +} + /** * @brief AH/QVAR data read.[get] * * @param ctx communication interface handler.(ptr) * @param md the sensor conversion parameters.(ptr) - * @param data data retrived from the sensor.(ptr) + * @param data data retrieved from the sensor.(ptr) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_ah_qvar_data_get(stmdev_ctx_t *ctx, +int32_t ilps22qs_ah_qvar_data_get(const stmdev_ctx_t *ctx, ilps22qs_ah_qvar_data_t *data) { uint8_t buff[5]; @@ -814,7 +871,7 @@ int32_t ilps22qs_ah_qvar_data_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_fifo_mode_set(stmdev_ctx_t *ctx, ilps22qs_fifo_md_t *val) +int32_t ilps22qs_fifo_mode_set(const stmdev_ctx_t *ctx, ilps22qs_fifo_md_t *val) { ilps22qs_fifo_ctrl_t fifo_ctrl; ilps22qs_fifo_wtm_t fifo_wtm; @@ -857,7 +914,7 @@ int32_t ilps22qs_fifo_mode_set(stmdev_ctx_t *ctx, ilps22qs_fifo_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_fifo_mode_get(stmdev_ctx_t *ctx, ilps22qs_fifo_md_t *val) +int32_t ilps22qs_fifo_mode_get(const stmdev_ctx_t *ctx, ilps22qs_fifo_md_t *val) { ilps22qs_fifo_ctrl_t fifo_ctrl; ilps22qs_fifo_wtm_t fifo_wtm; @@ -908,7 +965,7 @@ int32_t ilps22qs_fifo_mode_get(stmdev_ctx_t *ctx, ilps22qs_fifo_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_fifo_level_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ilps22qs_fifo_level_get(const stmdev_ctx_t *ctx, uint8_t *val) { ilps22qs_fifo_status1_t fifo_status1; int32_t ret; @@ -928,11 +985,11 @@ int32_t ilps22qs_fifo_level_get(stmdev_ctx_t *ctx, uint8_t *val) * @param md the sensor conversion parameters.(ptr) * @param fmd get the FIFO operation mode.(ptr) * @param samp number of samples stored in FIFO.(ptr) - * @param data data retrived from FIFO.(ptr) + * @param data data retrieved from FIFO.(ptr) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_fifo_data_get(stmdev_ctx_t *ctx, uint8_t samp, +int32_t ilps22qs_fifo_data_get(const stmdev_ctx_t *ctx, uint8_t samp, ilps22qs_md_t *md, ilps22qs_fifo_data_t *data) { uint8_t fifo_data[3]; @@ -965,25 +1022,29 @@ int32_t ilps22qs_fifo_data_get(stmdev_ctx_t *ctx, uint8_t samp, break; } data[i].lsb = 0; - } else { + } + else + { /* data is a AH_QVAR sample */ data[i].lsb = (data[i].raw / 256); /* shift 8bit left */ data[i].hpa = 0.0f; } - } else { - switch (md->fs) - { - case ILPS22QS_1260hPa: - data[i].hpa = ilps22qs_from_fs1260_to_hPa(data[i].raw); - break; - case ILPS22QS_4060hPa: - data[i].hpa = ilps22qs_from_fs4000_to_hPa(data[i].raw); - break; - default: - data[i].hpa = 0.0f; - break; - } - data[i].lsb = 0; + } + else + { + switch (md->fs) + { + case ILPS22QS_1260hPa: + data[i].hpa = ilps22qs_from_fs1260_to_hPa(data[i].raw); + break; + case ILPS22QS_4060hPa: + data[i].hpa = ilps22qs_from_fs4000_to_hPa(data[i].raw); + break; + default: + data[i].hpa = 0.0f; + break; + } + data[i].lsb = 0; } } @@ -1012,7 +1073,7 @@ int32_t ilps22qs_fifo_data_get(stmdev_ctx_t *ctx, uint8_t samp, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_interrupt_mode_set(stmdev_ctx_t *ctx, +int32_t ilps22qs_interrupt_mode_set(const stmdev_ctx_t *ctx, ilps22qs_int_mode_t *val) { ilps22qs_interrupt_cfg_t interrupt_cfg; @@ -1037,7 +1098,7 @@ int32_t ilps22qs_interrupt_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_interrupt_mode_get(stmdev_ctx_t *ctx, +int32_t ilps22qs_interrupt_mode_get(const stmdev_ctx_t *ctx, ilps22qs_int_mode_t *val) { ilps22qs_interrupt_cfg_t interrupt_cfg; @@ -1058,7 +1119,7 @@ int32_t ilps22qs_interrupt_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_ah_qvar_disable(stmdev_ctx_t *ctx) +int32_t ilps22qs_ah_qvar_disable(const stmdev_ctx_t *ctx) { uint32_t val = 0; int32_t ret; @@ -1089,7 +1150,7 @@ int32_t ilps22qs_ah_qvar_disable(stmdev_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_int_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t ilps22qs_int_on_threshold_mode_set(const stmdev_ctx_t *ctx, ilps22qs_int_th_md_t *val) { ilps22qs_interrupt_cfg_t interrupt_cfg; @@ -1127,7 +1188,7 @@ int32_t ilps22qs_int_on_threshold_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_int_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t ilps22qs_int_on_threshold_mode_get(const stmdev_ctx_t *ctx, ilps22qs_int_th_md_t *val) { ilps22qs_interrupt_cfg_t interrupt_cfg; @@ -1171,7 +1232,7 @@ int32_t ilps22qs_int_on_threshold_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_reference_mode_set(stmdev_ctx_t *ctx, ilps22qs_ref_md_t *val) +int32_t ilps22qs_reference_mode_set(const stmdev_ctx_t *ctx, ilps22qs_ref_md_t *val) { ilps22qs_interrupt_cfg_t interrupt_cfg; int32_t ret; @@ -1201,7 +1262,7 @@ int32_t ilps22qs_reference_mode_set(stmdev_ctx_t *ctx, ilps22qs_ref_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_reference_mode_get(stmdev_ctx_t *ctx, ilps22qs_ref_md_t *val) +int32_t ilps22qs_reference_mode_get(const stmdev_ctx_t *ctx, ilps22qs_ref_md_t *val) { ilps22qs_interrupt_cfg_t interrupt_cfg; int32_t ret; @@ -1236,7 +1297,7 @@ int32_t ilps22qs_reference_mode_get(stmdev_ctx_t *ctx, ilps22qs_ref_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_opc_set(stmdev_ctx_t *ctx, int16_t val) +int32_t ilps22qs_opc_set(const stmdev_ctx_t *ctx, int16_t val) { uint8_t reg[2]; int32_t ret; @@ -1257,7 +1318,7 @@ int32_t ilps22qs_opc_set(stmdev_ctx_t *ctx, int16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps22qs_opc_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t ilps22qs_opc_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t reg[2]; int32_t ret; diff --git a/sensor/stmemsc/ilps22qs_STdC/driver/ilps22qs_reg.h b/sensor/stmemsc/ilps22qs_STdC/driver/ilps22qs_reg.h index 626a485a..66b707a5 100644 --- a/sensor/stmemsc/ilps22qs_STdC/driver/ilps22qs_reg.h +++ b/sensor/stmemsc/ilps22qs_STdC/driver/ilps22qs_reg.h @@ -476,9 +476,9 @@ typedef union * them with a custom implementation. */ -int32_t ilps22qs_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t ilps22qs_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t ilps22qs_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t ilps22qs_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); extern float_t ilps22qs_from_fs1260_to_hPa(int32_t lsb); @@ -492,24 +492,27 @@ typedef struct { uint8_t whoami; } ilps22qs_id_t; -int32_t ilps22qs_id_get(stmdev_ctx_t *ctx, ilps22qs_id_t *val); +int32_t ilps22qs_id_get(const stmdev_ctx_t *ctx, ilps22qs_id_t *val); + +typedef enum +{ + ILPS22QS_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */ + ILPS22QS_SPI_3W = 0x03, /* bus mode select by HW (SPI 3W enable) */ +} ilps22qs_interface_t; + +typedef enum +{ + ILPS22QS_AUTO = 0x00, /* bus mode select by HW (SPI 3W disable) */ + ILPS22QS_ALWAYS_ON = 0x01, /* Only SPI: SDO / SDI separated pins */ +} ilps22qs_filter_t; typedef struct { - enum - { - ILPS22QS_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */ - ILPS22QS_SPI_3W = 0x03, /* bus mode select by HW (SPI 3W disable) */ - ILPS22QS_SPI_4W = 0x02, /* bus mode select by HW (SPI 3W disable) */ - } interface; - enum - { - ILPS22QS_AUTO = 0x00, /* bus mode select by HW (SPI 3W disable) */ - ILPS22QS_ALWAYS_ON = 0x01, /* Only SPI: SDO / SDI separated pins */ - } filter; + ilps22qs_interface_t interface; + ilps22qs_filter_t filter; } ilps22qs_bus_mode_t; -int32_t ilps22qs_bus_mode_set(stmdev_ctx_t *ctx, ilps22qs_bus_mode_t *val); -int32_t ilps22qs_bus_mode_get(stmdev_ctx_t *ctx, ilps22qs_bus_mode_t *val); +int32_t ilps22qs_bus_mode_set(const stmdev_ctx_t *ctx, ilps22qs_bus_mode_t *val); +int32_t ilps22qs_bus_mode_get(const stmdev_ctx_t *ctx, ilps22qs_bus_mode_t *val); typedef enum { @@ -517,7 +520,7 @@ typedef enum ILPS22QS_BOOT = 0x01, /* Restore calib. param. ( it takes 10ms ) */ ILPS22QS_RESET = 0x02, /* Reset configuration registers */ } ilps22qs_init_t; -int32_t ilps22qs_init_set(stmdev_ctx_t *ctx, ilps22qs_init_t val); +int32_t ilps22qs_init_set(const stmdev_ctx_t *ctx, ilps22qs_init_t val); typedef struct { @@ -530,15 +533,15 @@ typedef struct uint8_t end_meas : 1; /* Single measurement is finished. */ uint8_t ref_done : 1; /* Auto-Zero value is set. */ } ilps22qs_stat_t; -int32_t ilps22qs_status_get(stmdev_ctx_t *ctx, ilps22qs_stat_t *val); +int32_t ilps22qs_status_get(const stmdev_ctx_t *ctx, ilps22qs_stat_t *val); typedef struct { uint8_t sda_pull_up : 1; /* 1 = pull-up always disabled */ uint8_t cs_pull_up : 1; /* 1 = pull-up always disabled */ } ilps22qs_pin_conf_t; -int32_t ilps22qs_pin_conf_set(stmdev_ctx_t *ctx, ilps22qs_pin_conf_t *val); -int32_t ilps22qs_pin_conf_get(stmdev_ctx_t *ctx, ilps22qs_pin_conf_t *val); +int32_t ilps22qs_pin_conf_set(const stmdev_ctx_t *ctx, ilps22qs_pin_conf_t *val); +int32_t ilps22qs_pin_conf_get(const stmdev_ctx_t *ctx, ilps22qs_pin_conf_t *val); typedef struct { @@ -551,51 +554,59 @@ typedef struct uint8_t fifo_ovr : 1; /* FIFO overrun */ uint8_t fifo_th : 1; /* FIFO threshold reached */ } ilps22qs_all_sources_t; -int32_t ilps22qs_all_sources_get(stmdev_ctx_t *ctx, +int32_t ilps22qs_all_sources_get(const stmdev_ctx_t *ctx, ilps22qs_all_sources_t *val); +typedef enum +{ + ILPS22QS_1260hPa = 0x00, + ILPS22QS_4060hPa = 0x01, +} ilps22qs_fs_t; + +typedef enum +{ + ILPS22QS_ONE_SHOT = 0x00, /* Device in power down till software trigger */ + ILPS22QS_1Hz = 0x01, + ILPS22QS_4Hz = 0x02, + ILPS22QS_10Hz = 0x03, + ILPS22QS_25Hz = 0x04, + ILPS22QS_50Hz = 0x05, + ILPS22QS_75Hz = 0x06, + ILPS22QS_100Hz = 0x07, + ILPS22QS_200Hz = 0x08, +} ilps22qs_odr_t; + +typedef enum +{ + ILPS22QS_4_AVG = 0, + ILPS22QS_8_AVG = 1, + ILPS22QS_16_AVG = 2, + ILPS22QS_32_AVG = 3, + ILPS22QS_64_AVG = 4, + ILPS22QS_128_AVG = 5, + ILPS22QS_256_AVG = 6, + ILPS22QS_512_AVG = 7, +} ilps22qs_avg_t; + +typedef enum +{ + ILPS22QS_LPF_DISABLE = 0, + ILPS22QS_LPF_ODR_DIV_4 = 1, + ILPS22QS_LPF_ODR_DIV_9 = 3, +} ilps22qs_lpf_t; + typedef struct { - enum - { - ILPS22QS_1260hPa = 0x00, - ILPS22QS_4060hPa = 0x01, - } fs; - enum - { - ILPS22QS_ONE_SHOT = 0x00, /* Device in power down till software trigger */ - ILPS22QS_1Hz = 0x01, - ILPS22QS_4Hz = 0x02, - ILPS22QS_10Hz = 0x03, - ILPS22QS_25Hz = 0x04, - ILPS22QS_50Hz = 0x05, - ILPS22QS_75Hz = 0x06, - ILPS22QS_100Hz = 0x07, - ILPS22QS_200Hz = 0x08, - } odr; - enum - { - ILPS22QS_4_AVG = 0, - ILPS22QS_8_AVG = 1, - ILPS22QS_16_AVG = 2, - ILPS22QS_32_AVG = 3, - ILPS22QS_64_AVG = 4, - ILPS22QS_128_AVG = 5, - ILPS22QS_256_AVG = 6, - ILPS22QS_512_AVG = 7, - } avg; - enum - { - ILPS22QS_LPF_DISABLE = 0, - ILPS22QS_LPF_ODR_DIV_4 = 1, - ILPS22QS_LPF_ODR_DIV_9 = 3, - } lpf; + ilps22qs_fs_t fs; + ilps22qs_odr_t odr; + ilps22qs_avg_t avg; + ilps22qs_lpf_t lpf; uint8_t interleaved_mode; } ilps22qs_md_t; -int32_t ilps22qs_mode_set(stmdev_ctx_t *ctx, ilps22qs_md_t *val); -int32_t ilps22qs_mode_get(stmdev_ctx_t *ctx, ilps22qs_md_t *val); +int32_t ilps22qs_mode_set(const stmdev_ctx_t *ctx, ilps22qs_md_t *val); +int32_t ilps22qs_mode_get(const stmdev_ctx_t *ctx, ilps22qs_md_t *val); -int32_t ilps22qs_trigger_sw(stmdev_ctx_t *ctx, ilps22qs_md_t *md); +int32_t ilps22qs_trigger_sw(const stmdev_ctx_t *ctx, ilps22qs_md_t *md); typedef struct { @@ -614,34 +625,40 @@ typedef struct int32_t lsb; /* 24 bit properly right aligned */ } ah_qvar; } ilps22qs_data_t; -int32_t ilps22qs_data_get(stmdev_ctx_t *ctx, ilps22qs_md_t *md, +int32_t ilps22qs_data_get(const stmdev_ctx_t *ctx, ilps22qs_md_t *md, ilps22qs_data_t *data); + +int32_t ilps22qs_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff); +int32_t ilps22qs_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff); + typedef struct { float_t mv; /* value converted in mV */ int32_t lsb; /* 24 bit properly right aligned */ int32_t raw; /* 32 bit signed-left algned format left */ } ilps22qs_ah_qvar_data_t; -int32_t ilps22qs_ah_qvar_data_get(stmdev_ctx_t *ctx, +int32_t ilps22qs_ah_qvar_data_get(const stmdev_ctx_t *ctx, ilps22qs_ah_qvar_data_t *data); +typedef enum +{ + ILPS22QS_BYPASS = 0, + ILPS22QS_FIFO = 1, + ILPS22QS_STREAM = 2, + ILPS22QS_STREAM_TO_FIFO = 7, /* Dynamic-Stream, FIFO on Trigger */ + ILPS22QS_BYPASS_TO_STREAM = 6, /* Bypass, Dynamic-Stream on Trigger */ + ILPS22QS_BYPASS_TO_FIFO = 5, /* Bypass, FIFO on Trigger */ +} ilps22qs_operation_t; + typedef struct { - enum - { - ILPS22QS_BYPASS = 0, - ILPS22QS_FIFO = 1, - ILPS22QS_STREAM = 2, - ILPS22QS_STREAM_TO_FIFO = 7, /* Dynamic-Stream, FIFO on Trigger */ - ILPS22QS_BYPASS_TO_STREAM = 6, /* Bypass, Dynamic-Stream on Trigger */ - ILPS22QS_BYPASS_TO_FIFO = 5, /* Bypass, FIFO on Trigger */ - } operation; + ilps22qs_operation_t operation; uint8_t watermark : 7; /* (0 disable) max 128.*/ } ilps22qs_fifo_md_t; -int32_t ilps22qs_fifo_mode_set(stmdev_ctx_t *ctx, ilps22qs_fifo_md_t *val); -int32_t ilps22qs_fifo_mode_get(stmdev_ctx_t *ctx, ilps22qs_fifo_md_t *val); +int32_t ilps22qs_fifo_mode_set(const stmdev_ctx_t *ctx, ilps22qs_fifo_md_t *val); +int32_t ilps22qs_fifo_mode_get(const stmdev_ctx_t *ctx, ilps22qs_fifo_md_t *val); -int32_t ilps22qs_fifo_level_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ilps22qs_fifo_level_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -649,21 +666,21 @@ typedef struct int32_t lsb; /* 24 bit properly right aligned */ int32_t raw; } ilps22qs_fifo_data_t; -int32_t ilps22qs_fifo_data_get(stmdev_ctx_t *ctx, uint8_t samp, +int32_t ilps22qs_fifo_data_get(const stmdev_ctx_t *ctx, uint8_t samp, ilps22qs_md_t *md, ilps22qs_fifo_data_t *data); typedef struct { uint8_t int_latched : 1; /* int events are: int on threshold, FIFO */ } ilps22qs_int_mode_t; -int32_t ilps22qs_interrupt_mode_set(stmdev_ctx_t *ctx, +int32_t ilps22qs_interrupt_mode_set(const stmdev_ctx_t *ctx, ilps22qs_int_mode_t *val); -int32_t ilps22qs_interrupt_mode_get(stmdev_ctx_t *ctx, +int32_t ilps22qs_interrupt_mode_get(const stmdev_ctx_t *ctx, ilps22qs_int_mode_t *val); -int32_t ilps22qs_ah_qvar_disable(stmdev_ctx_t *ctx); -int32_t ilps22qs_ah_qvar_en_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ilps22qs_ah_qvar_en_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ilps22qs_ah_qvar_disable(const stmdev_ctx_t *ctx); +int32_t ilps22qs_ah_qvar_en_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ilps22qs_ah_qvar_en_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -673,28 +690,30 @@ typedef struct uint8_t over_th : 1; /* Pressure data over threshold event */ uint8_t under_th : 1; /* Pressure data under threshold event */ } ilps22qs_int_th_md_t; -int32_t ilps22qs_int_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t ilps22qs_int_on_threshold_mode_set(const stmdev_ctx_t *ctx, ilps22qs_int_th_md_t *val); -int32_t ilps22qs_int_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t ilps22qs_int_on_threshold_mode_get(const stmdev_ctx_t *ctx, ilps22qs_int_th_md_t *val); +typedef enum +{ + ILPS22QS_OUT_AND_INTERRUPT = 0, + ILPS22QS_ONLY_INTERRUPT = 1, + ILPS22QS_RST_REFS = 2, +} ilps22qs_apply_ref_t; + typedef struct { - enum - { - ILPS22QS_OUT_AND_INTERRUPT = 0, - ILPS22QS_ONLY_INTERRUPT = 1, - ILPS22QS_RST_REFS = 2, - } apply_ref; + ilps22qs_apply_ref_t apply_ref; uint8_t get_ref : 1; /* Use current pressure value as reference */ } ilps22qs_ref_md_t; -int32_t ilps22qs_reference_mode_set(stmdev_ctx_t *ctx, +int32_t ilps22qs_reference_mode_set(const stmdev_ctx_t *ctx, ilps22qs_ref_md_t *val); -int32_t ilps22qs_reference_mode_get(stmdev_ctx_t *ctx, +int32_t ilps22qs_reference_mode_get(const stmdev_ctx_t *ctx, ilps22qs_ref_md_t *val); -int32_t ilps22qs_opc_set(stmdev_ctx_t *ctx, int16_t val); -int32_t ilps22qs_opc_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t ilps22qs_opc_set(const stmdev_ctx_t *ctx, int16_t val); +int32_t ilps22qs_opc_get(const stmdev_ctx_t *ctx, int16_t *val); /** *@} diff --git a/sensor/stmemsc/ilps28qsw_STdC/driver/ilps28qsw_reg.c b/sensor/stmemsc/ilps28qsw_STdC/driver/ilps28qsw_reg.c index f687f36c..bb42ae9e 100644 --- a/sensor/stmemsc/ilps28qsw_STdC/driver/ilps28qsw_reg.c +++ b/sensor/stmemsc/ilps28qsw_STdC/driver/ilps28qsw_reg.c @@ -46,11 +46,18 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak ilps28qsw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, +int32_t __weak ilps28qsw_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); + return ret; } @@ -64,12 +71,19 @@ int32_t __weak ilps28qsw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak ilps28qsw_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak ilps28qsw_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); + return ret; } @@ -146,7 +160,7 @@ float_t ilps28qsw_from_lsb_to_mv(int32_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_id_get(stmdev_ctx_t *ctx, ilps28qsw_id_t *val) +int32_t ilps28qsw_id_get(const stmdev_ctx_t *ctx, ilps28qsw_id_t *val) { uint8_t reg; int32_t ret; @@ -165,7 +179,7 @@ int32_t ilps28qsw_id_get(stmdev_ctx_t *ctx, ilps28qsw_id_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_bus_mode_set(stmdev_ctx_t *ctx, ilps28qsw_bus_mode_t *val) +int32_t ilps28qsw_bus_mode_set(const stmdev_ctx_t *ctx, ilps28qsw_bus_mode_t *val) { ilps28qsw_i3c_if_ctrl_t i3c_if_ctrl; int32_t ret; @@ -189,7 +203,7 @@ int32_t ilps28qsw_bus_mode_set(stmdev_ctx_t *ctx, ilps28qsw_bus_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_bus_mode_get(stmdev_ctx_t *ctx, ilps28qsw_bus_mode_t *val) +int32_t ilps28qsw_bus_mode_get(const stmdev_ctx_t *ctx, ilps28qsw_bus_mode_t *val) { ilps28qsw_i3c_if_ctrl_t i3c_if_ctrl; int32_t ret; @@ -222,7 +236,7 @@ int32_t ilps28qsw_bus_mode_get(stmdev_ctx_t *ctx, ilps28qsw_bus_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_init_set(stmdev_ctx_t *ctx, ilps28qsw_init_t val) +int32_t ilps28qsw_init_set(const stmdev_ctx_t *ctx, ilps28qsw_init_t val) { ilps28qsw_ctrl_reg2_t ctrl_reg2; ilps28qsw_ctrl_reg3_t ctrl_reg3; @@ -273,7 +287,7 @@ int32_t ilps28qsw_init_set(stmdev_ctx_t *ctx, ilps28qsw_init_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_status_get(stmdev_ctx_t *ctx, ilps28qsw_stat_t *val) +int32_t ilps28qsw_status_get(const stmdev_ctx_t *ctx, ilps28qsw_stat_t *val) { ilps28qsw_interrupt_cfg_t interrupt_cfg; ilps28qsw_int_source_t int_source; @@ -316,7 +330,7 @@ int32_t ilps28qsw_status_get(stmdev_ctx_t *ctx, ilps28qsw_stat_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_pin_conf_set(stmdev_ctx_t *ctx, ilps28qsw_pin_conf_t *val) +int32_t ilps28qsw_pin_conf_set(const stmdev_ctx_t *ctx, ilps28qsw_pin_conf_t *val) { ilps28qsw_if_ctrl_t if_ctrl; int32_t ret; @@ -340,7 +354,7 @@ int32_t ilps28qsw_pin_conf_set(stmdev_ctx_t *ctx, ilps28qsw_pin_conf_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_pin_conf_get(stmdev_ctx_t *ctx, ilps28qsw_pin_conf_t *val) +int32_t ilps28qsw_pin_conf_get(const stmdev_ctx_t *ctx, ilps28qsw_pin_conf_t *val) { ilps28qsw_if_ctrl_t if_ctrl; int32_t ret; @@ -360,7 +374,7 @@ int32_t ilps28qsw_pin_conf_get(stmdev_ctx_t *ctx, ilps28qsw_pin_conf_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_all_sources_get(stmdev_ctx_t *ctx, +int32_t ilps28qsw_all_sources_get(const stmdev_ctx_t *ctx, ilps28qsw_all_sources_t *val) { ilps28qsw_fifo_status2_t fifo_status2; @@ -401,7 +415,7 @@ int32_t ilps28qsw_all_sources_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_mode_set(stmdev_ctx_t *ctx, ilps28qsw_md_t *val) +int32_t ilps28qsw_mode_set(const stmdev_ctx_t *ctx, ilps28qsw_md_t *val) { ilps28qsw_ctrl_reg1_t ctrl_reg1; ilps28qsw_ctrl_reg2_t ctrl_reg2; @@ -480,7 +494,7 @@ int32_t ilps28qsw_mode_set(stmdev_ctx_t *ctx, ilps28qsw_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_mode_get(stmdev_ctx_t *ctx, ilps28qsw_md_t *val) +int32_t ilps28qsw_mode_get(const stmdev_ctx_t *ctx, ilps28qsw_md_t *val) { ilps28qsw_ctrl_reg1_t ctrl_reg1; ilps28qsw_ctrl_reg2_t ctrl_reg2; @@ -603,7 +617,7 @@ int32_t ilps28qsw_mode_get(stmdev_ctx_t *ctx, ilps28qsw_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_trigger_sw(stmdev_ctx_t *ctx, ilps28qsw_md_t *md) +int32_t ilps28qsw_trigger_sw(const stmdev_ctx_t *ctx, ilps28qsw_md_t *md) { ilps28qsw_ctrl_reg2_t ctrl_reg2; int32_t ret = 0; @@ -628,7 +642,7 @@ int32_t ilps28qsw_trigger_sw(stmdev_ctx_t *ctx, ilps28qsw_md_t *md) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ilps28qsw_ah_qvar_en_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ilps28qsw_ah_qvar_en_set(const stmdev_ctx_t *ctx, uint8_t val) { ilps28qsw_ctrl_reg3_t ctrl_reg3; int32_t ret; @@ -652,7 +666,7 @@ int32_t ilps28qsw_ah_qvar_en_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ilps28qsw_ah_qvar_en_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ilps28qsw_ah_qvar_en_get(const stmdev_ctx_t *ctx, uint8_t *val) { ilps28qsw_ctrl_reg3_t ctrl_reg3; int32_t ret; @@ -672,7 +686,7 @@ int32_t ilps28qsw_ah_qvar_en_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_data_get(stmdev_ctx_t *ctx, ilps28qsw_md_t *md, +int32_t ilps28qsw_data_get(const stmdev_ctx_t *ctx, ilps28qsw_md_t *md, ilps28qsw_data_t *data) { uint8_t buff[5]; @@ -737,6 +751,48 @@ int32_t ilps28qsw_data_get(stmdev_ctx_t *ctx, ilps28qsw_md_t *md, return ret; } +/** + * @brief Pressure output value.[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff) +{ + int32_t ret; + uint8_t reg[3]; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_PRESS_OUT_XL, reg, 3); + *buff = reg[2]; + *buff = (*buff * 256U) + reg[1]; + *buff = (*buff * 256U) + reg[0]; + *buff *= 256U; + + return ret; +} + +/** + * @brief Temperature output value.[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ilps28qsw_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) +{ + int32_t ret; + uint8_t reg[2]; + + ret = ilps28qsw_read_reg(ctx, ILPS28QSW_TEMP_OUT_L, reg, 2); + *buff = (int16_t)reg[1]; + *buff = (*buff * 256) + (int16_t)reg[0]; + + return ret; +} + /** * @brief AH/QVAR data read.[get] * @@ -746,7 +802,7 @@ int32_t ilps28qsw_data_get(stmdev_ctx_t *ctx, ilps28qsw_md_t *md, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_ah_qvar_data_get(stmdev_ctx_t *ctx, +int32_t ilps28qsw_ah_qvar_data_get(const stmdev_ctx_t *ctx, ilps28qsw_ah_qvar_data_t *data) { uint8_t buff[5]; @@ -787,7 +843,7 @@ int32_t ilps28qsw_ah_qvar_data_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_fifo_mode_set(stmdev_ctx_t *ctx, ilps28qsw_fifo_md_t *val) +int32_t ilps28qsw_fifo_mode_set(const stmdev_ctx_t *ctx, ilps28qsw_fifo_md_t *val) { ilps28qsw_fifo_ctrl_t fifo_ctrl; ilps28qsw_fifo_wtm_t fifo_wtm; @@ -830,7 +886,7 @@ int32_t ilps28qsw_fifo_mode_set(stmdev_ctx_t *ctx, ilps28qsw_fifo_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_fifo_mode_get(stmdev_ctx_t *ctx, ilps28qsw_fifo_md_t *val) +int32_t ilps28qsw_fifo_mode_get(const stmdev_ctx_t *ctx, ilps28qsw_fifo_md_t *val) { ilps28qsw_fifo_ctrl_t fifo_ctrl; ilps28qsw_fifo_wtm_t fifo_wtm; @@ -881,7 +937,7 @@ int32_t ilps28qsw_fifo_mode_get(stmdev_ctx_t *ctx, ilps28qsw_fifo_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_fifo_level_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ilps28qsw_fifo_level_get(const stmdev_ctx_t *ctx, uint8_t *val) { ilps28qsw_fifo_status1_t fifo_status1; int32_t ret; @@ -905,7 +961,7 @@ int32_t ilps28qsw_fifo_level_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_fifo_data_get(stmdev_ctx_t *ctx, uint8_t samp, +int32_t ilps28qsw_fifo_data_get(const stmdev_ctx_t *ctx, uint8_t samp, ilps28qsw_md_t *md, ilps28qsw_fifo_data_t *data) { uint8_t fifo_data[3]; @@ -989,7 +1045,7 @@ int32_t ilps28qsw_fifo_data_get(stmdev_ctx_t *ctx, uint8_t samp, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_interrupt_mode_set(stmdev_ctx_t *ctx, +int32_t ilps28qsw_interrupt_mode_set(const stmdev_ctx_t *ctx, ilps28qsw_int_mode_t *val) { ilps28qsw_interrupt_cfg_t interrupt_cfg; @@ -1014,7 +1070,7 @@ int32_t ilps28qsw_interrupt_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_interrupt_mode_get(stmdev_ctx_t *ctx, +int32_t ilps28qsw_interrupt_mode_get(const stmdev_ctx_t *ctx, ilps28qsw_int_mode_t *val) { ilps28qsw_interrupt_cfg_t interrupt_cfg; @@ -1035,7 +1091,7 @@ int32_t ilps28qsw_interrupt_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_ah_qvar_disable(stmdev_ctx_t *ctx) +int32_t ilps28qsw_ah_qvar_disable(const stmdev_ctx_t *ctx) { uint32_t val = 0; int32_t ret; @@ -1066,7 +1122,7 @@ int32_t ilps28qsw_ah_qvar_disable(stmdev_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_int_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t ilps28qsw_int_on_threshold_mode_set(const stmdev_ctx_t *ctx, ilps28qsw_int_th_md_t *val) { ilps28qsw_interrupt_cfg_t interrupt_cfg; @@ -1104,7 +1160,7 @@ int32_t ilps28qsw_int_on_threshold_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_int_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t ilps28qsw_int_on_threshold_mode_get(const stmdev_ctx_t *ctx, ilps28qsw_int_th_md_t *val) { ilps28qsw_interrupt_cfg_t interrupt_cfg; @@ -1148,7 +1204,7 @@ int32_t ilps28qsw_int_on_threshold_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_reference_mode_set(stmdev_ctx_t *ctx, ilps28qsw_ref_md_t *val) +int32_t ilps28qsw_reference_mode_set(const stmdev_ctx_t *ctx, ilps28qsw_ref_md_t *val) { ilps28qsw_interrupt_cfg_t interrupt_cfg; int32_t ret; @@ -1178,7 +1234,7 @@ int32_t ilps28qsw_reference_mode_set(stmdev_ctx_t *ctx, ilps28qsw_ref_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_reference_mode_get(stmdev_ctx_t *ctx, ilps28qsw_ref_md_t *val) +int32_t ilps28qsw_reference_mode_get(const stmdev_ctx_t *ctx, ilps28qsw_ref_md_t *val) { ilps28qsw_interrupt_cfg_t interrupt_cfg; int32_t ret; @@ -1213,7 +1269,7 @@ int32_t ilps28qsw_reference_mode_get(stmdev_ctx_t *ctx, ilps28qsw_ref_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_opc_set(stmdev_ctx_t *ctx, int16_t val) +int32_t ilps28qsw_opc_set(const stmdev_ctx_t *ctx, int16_t val) { uint8_t reg[2]; int32_t ret; @@ -1234,7 +1290,7 @@ int32_t ilps28qsw_opc_set(stmdev_ctx_t *ctx, int16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ilps28qsw_opc_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t ilps28qsw_opc_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t reg[2]; int32_t ret; diff --git a/sensor/stmemsc/ilps28qsw_STdC/driver/ilps28qsw_reg.h b/sensor/stmemsc/ilps28qsw_STdC/driver/ilps28qsw_reg.h index 67f983b8..0f3ee444 100644 --- a/sensor/stmemsc/ilps28qsw_STdC/driver/ilps28qsw_reg.h +++ b/sensor/stmemsc/ilps28qsw_STdC/driver/ilps28qsw_reg.h @@ -468,9 +468,9 @@ typedef union * them with a custom implementation. */ -int32_t ilps28qsw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t ilps28qsw_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t ilps28qsw_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t ilps28qsw_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); extern float_t ilps28qsw_from_fs1260_to_hPa(int32_t lsb); @@ -484,18 +484,20 @@ typedef struct { uint8_t whoami; } ilps28qsw_id_t; -int32_t ilps28qsw_id_get(stmdev_ctx_t *ctx, ilps28qsw_id_t *val); +int32_t ilps28qsw_id_get(const stmdev_ctx_t *ctx, ilps28qsw_id_t *val); + +typedef enum +{ + ILPS28QSW_AUTO = 0x00, /* anti-spike filters managed by protocol */ + ILPS28QSW_ALWAYS_ON = 0x01, /* anti-spike filters always on */ +} ilps28qsw_filter_t; typedef struct { - enum - { - ILPS28QSW_AUTO = 0x00, /* anti-spike filters managed by protocol */ - ILPS28QSW_ALWAYS_ON = 0x01, /* anti-spike filters always on */ - } filter; + ilps28qsw_filter_t filter; } ilps28qsw_bus_mode_t; -int32_t ilps28qsw_bus_mode_set(stmdev_ctx_t *ctx, ilps28qsw_bus_mode_t *val); -int32_t ilps28qsw_bus_mode_get(stmdev_ctx_t *ctx, ilps28qsw_bus_mode_t *val); +int32_t ilps28qsw_bus_mode_set(const stmdev_ctx_t *ctx, ilps28qsw_bus_mode_t *val); +int32_t ilps28qsw_bus_mode_get(const stmdev_ctx_t *ctx, ilps28qsw_bus_mode_t *val); typedef enum { @@ -503,7 +505,7 @@ typedef enum ILPS28QSW_BOOT = 0x01, /* Restore calib. param. ( it takes 10ms ) */ ILPS28QSW_RESET = 0x02, /* Reset configuration registers */ } ilps28qsw_init_t; -int32_t ilps28qsw_init_set(stmdev_ctx_t *ctx, ilps28qsw_init_t val); +int32_t ilps28qsw_init_set(const stmdev_ctx_t *ctx, ilps28qsw_init_t val); typedef struct { @@ -516,15 +518,15 @@ typedef struct uint8_t end_meas : 1; /* Single measurement is finished. */ uint8_t ref_done : 1; /* Auto-Zero value is set. */ } ilps28qsw_stat_t; -int32_t ilps28qsw_status_get(stmdev_ctx_t *ctx, ilps28qsw_stat_t *val); +int32_t ilps28qsw_status_get(const stmdev_ctx_t *ctx, ilps28qsw_stat_t *val); typedef struct { uint8_t sda_pull_up : 1; /* 1 = pull-up always disabled */ uint8_t cs_pull_up : 1; /* 1 = pull-up always disabled */ } ilps28qsw_pin_conf_t; -int32_t ilps28qsw_pin_conf_set(stmdev_ctx_t *ctx, ilps28qsw_pin_conf_t *val); -int32_t ilps28qsw_pin_conf_get(stmdev_ctx_t *ctx, ilps28qsw_pin_conf_t *val); +int32_t ilps28qsw_pin_conf_set(const stmdev_ctx_t *ctx, ilps28qsw_pin_conf_t *val); +int32_t ilps28qsw_pin_conf_get(const stmdev_ctx_t *ctx, ilps28qsw_pin_conf_t *val); typedef struct { @@ -537,51 +539,59 @@ typedef struct uint8_t fifo_ovr : 1; /* FIFO overrun */ uint8_t fifo_th : 1; /* FIFO threshold reached */ } ilps28qsw_all_sources_t; -int32_t ilps28qsw_all_sources_get(stmdev_ctx_t *ctx, +int32_t ilps28qsw_all_sources_get(const stmdev_ctx_t *ctx, ilps28qsw_all_sources_t *val); +typedef enum +{ + ILPS28QSW_1260hPa = 0x00, + ILPS28QSW_4060hPa = 0x01, +} ilps28qsw_fs_t; + +typedef enum +{ + ILPS28QSW_ONE_SHOT = 0x00, /* Device in power down till software trigger */ + ILPS28QSW_1Hz = 0x01, + ILPS28QSW_4Hz = 0x02, + ILPS28QSW_10Hz = 0x03, + ILPS28QSW_25Hz = 0x04, + ILPS28QSW_50Hz = 0x05, + ILPS28QSW_75Hz = 0x06, + ILPS28QSW_100Hz = 0x07, + ILPS28QSW_200Hz = 0x08, +} ilps28qsw_odr_t; + +typedef enum +{ + ILPS28QSW_4_AVG = 0, + ILPS28QSW_8_AVG = 1, + ILPS28QSW_16_AVG = 2, + ILPS28QSW_32_AVG = 3, + ILPS28QSW_64_AVG = 4, + ILPS28QSW_128_AVG = 5, + ILPS28QSW_256_AVG = 6, + ILPS28QSW_512_AVG = 7, +} ilps28qsw_avg_t; + +typedef enum +{ + ILPS28QSW_LPF_DISABLE = 0, + ILPS28QSW_LPF_ODR_DIV_4 = 1, + ILPS28QSW_LPF_ODR_DIV_9 = 3, +} ilps28qsw_lpf_t; + typedef struct { - enum - { - ILPS28QSW_1260hPa = 0x00, - ILPS28QSW_4060hPa = 0x01, - } fs; - enum - { - ILPS28QSW_ONE_SHOT = 0x00, /* Device in power down till software trigger */ - ILPS28QSW_1Hz = 0x01, - ILPS28QSW_4Hz = 0x02, - ILPS28QSW_10Hz = 0x03, - ILPS28QSW_25Hz = 0x04, - ILPS28QSW_50Hz = 0x05, - ILPS28QSW_75Hz = 0x06, - ILPS28QSW_100Hz = 0x07, - ILPS28QSW_200Hz = 0x08, - } odr; - enum - { - ILPS28QSW_4_AVG = 0, - ILPS28QSW_8_AVG = 1, - ILPS28QSW_16_AVG = 2, - ILPS28QSW_32_AVG = 3, - ILPS28QSW_64_AVG = 4, - ILPS28QSW_128_AVG = 5, - ILPS28QSW_256_AVG = 6, - ILPS28QSW_512_AVG = 7, - } avg; - enum - { - ILPS28QSW_LPF_DISABLE = 0, - ILPS28QSW_LPF_ODR_DIV_4 = 1, - ILPS28QSW_LPF_ODR_DIV_9 = 3, - } lpf; + ilps28qsw_fs_t fs; + ilps28qsw_odr_t odr; + ilps28qsw_avg_t avg; + ilps28qsw_lpf_t lpf; uint8_t interleaved_mode; } ilps28qsw_md_t; -int32_t ilps28qsw_mode_set(stmdev_ctx_t *ctx, ilps28qsw_md_t *val); -int32_t ilps28qsw_mode_get(stmdev_ctx_t *ctx, ilps28qsw_md_t *val); +int32_t ilps28qsw_mode_set(const stmdev_ctx_t *ctx, ilps28qsw_md_t *val); +int32_t ilps28qsw_mode_get(const stmdev_ctx_t *ctx, ilps28qsw_md_t *val); -int32_t ilps28qsw_trigger_sw(stmdev_ctx_t *ctx, ilps28qsw_md_t *md); +int32_t ilps28qsw_trigger_sw(const stmdev_ctx_t *ctx, ilps28qsw_md_t *md); typedef struct { @@ -600,34 +610,40 @@ typedef struct int32_t lsb; /* 24 bit properly right aligned */ } ah_qvar; } ilps28qsw_data_t; -int32_t ilps28qsw_data_get(stmdev_ctx_t *ctx, ilps28qsw_md_t *md, +int32_t ilps28qsw_data_get(const stmdev_ctx_t *ctx, ilps28qsw_md_t *md, ilps28qsw_data_t *data); + +int32_t ilps28qsw_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff); +int32_t ilps28qsw_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff); + typedef struct { float_t mv; /* value converted in mV */ int32_t lsb; /* 24 bit properly right aligned */ int32_t raw; /* 32 bit signed-left algned format left */ } ilps28qsw_ah_qvar_data_t; -int32_t ilps28qsw_ah_qvar_data_get(stmdev_ctx_t *ctx, +int32_t ilps28qsw_ah_qvar_data_get(const stmdev_ctx_t *ctx, ilps28qsw_ah_qvar_data_t *data); +typedef enum +{ + ILPS28QSW_BYPASS = 0, + ILPS28QSW_FIFO = 1, + ILPS28QSW_STREAM = 2, + ILPS28QSW_STREAM_TO_FIFO = 7, /* Dynamic-Stream, FIFO on Trigger */ + ILPS28QSW_BYPASS_TO_STREAM = 6, /* Bypass, Dynamic-Stream on Trigger */ + ILPS28QSW_BYPASS_TO_FIFO = 5, /* Bypass, FIFO on Trigger */ +} ilps28qsw_operation_t; + typedef struct { - enum - { - ILPS28QSW_BYPASS = 0, - ILPS28QSW_FIFO = 1, - ILPS28QSW_STREAM = 2, - ILPS28QSW_STREAM_TO_FIFO = 7, /* Dynamic-Stream, FIFO on Trigger */ - ILPS28QSW_BYPASS_TO_STREAM = 6, /* Bypass, Dynamic-Stream on Trigger */ - ILPS28QSW_BYPASS_TO_FIFO = 5, /* Bypass, FIFO on Trigger */ - } operation; + ilps28qsw_operation_t operation; uint8_t watermark : 7; /* (0 disable) max 128.*/ } ilps28qsw_fifo_md_t; -int32_t ilps28qsw_fifo_mode_set(stmdev_ctx_t *ctx, ilps28qsw_fifo_md_t *val); -int32_t ilps28qsw_fifo_mode_get(stmdev_ctx_t *ctx, ilps28qsw_fifo_md_t *val); +int32_t ilps28qsw_fifo_mode_set(const stmdev_ctx_t *ctx, ilps28qsw_fifo_md_t *val); +int32_t ilps28qsw_fifo_mode_get(const stmdev_ctx_t *ctx, ilps28qsw_fifo_md_t *val); -int32_t ilps28qsw_fifo_level_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ilps28qsw_fifo_level_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -635,21 +651,21 @@ typedef struct int32_t lsb; /* 24 bit properly right aligned */ int32_t raw; } ilps28qsw_fifo_data_t; -int32_t ilps28qsw_fifo_data_get(stmdev_ctx_t *ctx, uint8_t samp, +int32_t ilps28qsw_fifo_data_get(const stmdev_ctx_t *ctx, uint8_t samp, ilps28qsw_md_t *md, ilps28qsw_fifo_data_t *data); typedef struct { uint8_t int_latched : 1; /* int events are: int on threshold, FIFO */ } ilps28qsw_int_mode_t; -int32_t ilps28qsw_interrupt_mode_set(stmdev_ctx_t *ctx, +int32_t ilps28qsw_interrupt_mode_set(const stmdev_ctx_t *ctx, ilps28qsw_int_mode_t *val); -int32_t ilps28qsw_interrupt_mode_get(stmdev_ctx_t *ctx, +int32_t ilps28qsw_interrupt_mode_get(const stmdev_ctx_t *ctx, ilps28qsw_int_mode_t *val); -int32_t ilps28qsw_ah_qvar_disable(stmdev_ctx_t *ctx); -int32_t ilps28qsw_ah_qvar_en_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ilps28qsw_ah_qvar_en_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ilps28qsw_ah_qvar_disable(const stmdev_ctx_t *ctx); +int32_t ilps28qsw_ah_qvar_en_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ilps28qsw_ah_qvar_en_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -659,28 +675,30 @@ typedef struct uint8_t over_th : 1; /* Pressure data over threshold event */ uint8_t under_th : 1; /* Pressure data under threshold event */ } ilps28qsw_int_th_md_t; -int32_t ilps28qsw_int_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t ilps28qsw_int_on_threshold_mode_set(const stmdev_ctx_t *ctx, ilps28qsw_int_th_md_t *val); -int32_t ilps28qsw_int_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t ilps28qsw_int_on_threshold_mode_get(const stmdev_ctx_t *ctx, ilps28qsw_int_th_md_t *val); +typedef enum +{ + ILPS28QSW_OUT_AND_INTERRUPT = 0, + ILPS28QSW_ONLY_INTERRUPT = 1, + ILPS28QSW_RST_REFS = 2, +} ilps28qsw_apply_ref_t; + typedef struct { - enum - { - ILPS28QSW_OUT_AND_INTERRUPT = 0, - ILPS28QSW_ONLY_INTERRUPT = 1, - ILPS28QSW_RST_REFS = 2, - } apply_ref; + ilps28qsw_apply_ref_t apply_ref; uint8_t get_ref : 1; /* Use current pressure value as reference */ } ilps28qsw_ref_md_t; -int32_t ilps28qsw_reference_mode_set(stmdev_ctx_t *ctx, +int32_t ilps28qsw_reference_mode_set(const stmdev_ctx_t *ctx, ilps28qsw_ref_md_t *val); -int32_t ilps28qsw_reference_mode_get(stmdev_ctx_t *ctx, +int32_t ilps28qsw_reference_mode_get(const stmdev_ctx_t *ctx, ilps28qsw_ref_md_t *val); -int32_t ilps28qsw_opc_set(stmdev_ctx_t *ctx, int16_t val); -int32_t ilps28qsw_opc_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t ilps28qsw_opc_set(const stmdev_ctx_t *ctx, int16_t val); +int32_t ilps28qsw_opc_get(const stmdev_ctx_t *ctx, int16_t *val); /** *@} diff --git a/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.c b/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.c index 922725f6..ccbd7a51 100644 --- a/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.c +++ b/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak ism303dac_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak ism303dac_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak ism303dac_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak ism303dac_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak ism303dac_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -141,7 +151,7 @@ float_t ism303dac_from_lsb_to_celsius(int16_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_all_sources_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_all_sources_get(const stmdev_ctx_t *ctx, ism303dac_xl_all_sources_t *val) { int32_t ret; @@ -190,7 +200,7 @@ int32_t ism303dac_xl_all_sources_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_block_data_update_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_ctrl1_a_t ctrl1_a; @@ -215,7 +225,7 @@ int32_t ism303dac_xl_block_data_update_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_block_data_update_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_ctrl1_a_t ctrl1_a; @@ -235,7 +245,7 @@ int32_t ism303dac_xl_block_data_update_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_block_data_update_set(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_cfg_reg_c_m_t cfg_reg_c_m; @@ -262,7 +272,7 @@ int32_t ism303dac_mg_block_data_update_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_block_data_update_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_cfg_reg_c_m_t cfg_reg_c_m; @@ -283,7 +293,7 @@ int32_t ism303dac_mg_block_data_update_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_data_format_set(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_data_format_set(const stmdev_ctx_t *ctx, ism303dac_mg_ble_t val) { ism303dac_cfg_reg_c_m_t cfg_reg_c_m; @@ -310,7 +320,7 @@ int32_t ism303dac_mg_data_format_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_data_format_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_data_format_get(const stmdev_ctx_t *ctx, ism303dac_mg_ble_t *val) { ism303dac_cfg_reg_c_m_t cfg_reg_c_m; @@ -345,7 +355,7 @@ int32_t ism303dac_mg_data_format_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_full_scale_set(const stmdev_ctx_t *ctx, ism303dac_xl_fs_t val) { ism303dac_ctrl1_a_t ctrl1_a; @@ -370,7 +380,7 @@ int32_t ism303dac_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_full_scale_get(const stmdev_ctx_t *ctx, ism303dac_xl_fs_t *val) { ism303dac_ctrl1_a_t ctrl1_a; @@ -412,7 +422,7 @@ int32_t ism303dac_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_data_rate_set(const stmdev_ctx_t *ctx, ism303dac_xl_odr_t val) { ism303dac_ctrl1_a_t ctrl1_a; @@ -438,7 +448,7 @@ int32_t ism303dac_xl_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_data_rate_get(const stmdev_ctx_t *ctx, ism303dac_xl_odr_t *val) { ism303dac_ctrl1_a_t ctrl1_a; @@ -540,7 +550,7 @@ int32_t ism303dac_xl_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_status_reg_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_status_reg_get(const stmdev_ctx_t *ctx, ism303dac_status_a_t *val) { int32_t ret; @@ -558,7 +568,7 @@ int32_t ism303dac_xl_status_reg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_status_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_status_get(const stmdev_ctx_t *ctx, ism303dac_status_reg_m_t *val) { int32_t ret; @@ -576,7 +586,7 @@ int32_t ism303dac_mg_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_status_a_t status_a; @@ -597,7 +607,7 @@ int32_t ism303dac_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism303dac_mg_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_status_reg_m_t status_reg_m; int32_t ret; @@ -617,7 +627,7 @@ int32_t ism303dac_mg_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism303dac_mg_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_status_reg_m_t status_reg_m; int32_t ret; @@ -641,7 +651,7 @@ int32_t ism303dac_mg_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_user_offset_set(stmdev_ctx_t *ctx, uint16_t *val) +int32_t ism303dac_mg_user_offset_set(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[6]; int32_t ret; @@ -669,7 +679,7 @@ int32_t ism303dac_mg_user_offset_set(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_user_offset_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t ism303dac_mg_user_offset_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[6]; int32_t ret; @@ -693,7 +703,7 @@ int32_t ism303dac_mg_user_offset_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_operating_mode_set(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_operating_mode_set(const stmdev_ctx_t *ctx, ism303dac_mg_md_t val) { ism303dac_cfg_reg_a_m_t cfg_reg_a_m; @@ -720,7 +730,7 @@ int32_t ism303dac_mg_operating_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_operating_mode_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_operating_mode_get(const stmdev_ctx_t *ctx, ism303dac_mg_md_t *val) { ism303dac_cfg_reg_a_m_t cfg_reg_a_m; @@ -759,7 +769,7 @@ int32_t ism303dac_mg_operating_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_data_rate_set(const stmdev_ctx_t *ctx, ism303dac_mg_odr_t val) { ism303dac_cfg_reg_a_m_t cfg_reg_a_m; @@ -786,7 +796,7 @@ int32_t ism303dac_mg_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_data_rate_get(const stmdev_ctx_t *ctx, ism303dac_mg_odr_t *val) { ism303dac_cfg_reg_a_m_t cfg_reg_a_m; @@ -829,7 +839,7 @@ int32_t ism303dac_mg_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_power_mode_set(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_power_mode_set(const stmdev_ctx_t *ctx, ism303dac_mg_lp_t val) { ism303dac_cfg_reg_a_m_t cfg_reg_a_m; @@ -856,7 +866,7 @@ int32_t ism303dac_mg_power_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_power_mode_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_power_mode_get(const stmdev_ctx_t *ctx, ism303dac_mg_lp_t *val) { ism303dac_cfg_reg_a_m_t cfg_reg_a_m; @@ -891,7 +901,7 @@ int32_t ism303dac_mg_power_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_offset_temp_comp_set(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_offset_temp_comp_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_cfg_reg_a_m_t cfg_reg_a_m; @@ -918,7 +928,7 @@ int32_t ism303dac_mg_offset_temp_comp_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_offset_temp_comp_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_offset_temp_comp_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_cfg_reg_a_m_t cfg_reg_a_m; @@ -939,7 +949,7 @@ int32_t ism303dac_mg_offset_temp_comp_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_set_rst_mode_set(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_set_rst_mode_set(const stmdev_ctx_t *ctx, ism303dac_mg_set_rst_t val) { ism303dac_cfg_reg_b_m_t cfg_reg_b_m; @@ -966,7 +976,7 @@ int32_t ism303dac_mg_set_rst_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_set_rst_mode_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_set_rst_mode_get(const stmdev_ctx_t *ctx, ism303dac_mg_set_rst_t *val) { ism303dac_cfg_reg_b_m_t cfg_reg_b_m; @@ -1008,7 +1018,7 @@ int32_t ism303dac_mg_set_rst_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_set_rst_sensor_single_set(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_set_rst_sensor_single_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_cfg_reg_b_m_t cfg_reg_b_m; @@ -1038,7 +1048,7 @@ int32_t ism303dac_mg_set_rst_sensor_single_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_set_rst_sensor_single_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_set_rst_sensor_single_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_cfg_reg_b_m_t cfg_reg_b_m; @@ -1071,7 +1081,7 @@ int32_t ism303dac_mg_set_rst_sensor_single_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_acceleration_module_raw_get(stmdev_ctx_t *ctx, +int32_t ism303dac_acceleration_module_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1090,7 +1100,7 @@ int32_t ism303dac_acceleration_module_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_temperature_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1109,7 +1119,7 @@ int32_t ism303dac_xl_temperature_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t ism303dac_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -1134,7 +1144,7 @@ int32_t ism303dac_acceleration_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t ism303dac_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1170,7 +1180,7 @@ int32_t ism303dac_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ism303dac_xl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1187,7 +1197,7 @@ int32_t ism303dac_xl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ism303dac_mg_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1205,7 +1215,7 @@ int32_t ism303dac_mg_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_auto_increment_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_ctrl2_a_t ctrl2_a; @@ -1231,7 +1241,7 @@ int32_t ism303dac_xl_auto_increment_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_auto_increment_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_ctrl2_a_t ctrl2_a; @@ -1252,7 +1262,7 @@ int32_t ism303dac_xl_auto_increment_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism303dac_xl_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_ctrl2_a_t ctrl2_a; int32_t ret; @@ -1276,7 +1286,7 @@ int32_t ism303dac_xl_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism303dac_xl_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_ctrl2_a_t ctrl2_a; int32_t ret; @@ -1295,7 +1305,7 @@ int32_t ism303dac_xl_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism303dac_mg_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_cfg_reg_a_m_t cfg_reg_a_m; int32_t ret; @@ -1321,7 +1331,7 @@ int32_t ism303dac_mg_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism303dac_mg_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_cfg_reg_a_m_t cfg_reg_a_m; int32_t ret; @@ -1341,7 +1351,7 @@ int32_t ism303dac_mg_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism303dac_xl_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_ctrl2_a_t ctrl2_a; int32_t ret; @@ -1365,7 +1375,7 @@ int32_t ism303dac_xl_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism303dac_xl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_ctrl2_a_t ctrl2_a; int32_t ret; @@ -1384,7 +1394,7 @@ int32_t ism303dac_xl_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism303dac_mg_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_cfg_reg_a_m_t cfg_reg_a_m; int32_t ret; @@ -1410,7 +1420,7 @@ int32_t ism303dac_mg_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism303dac_mg_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_cfg_reg_a_m_t cfg_reg_a_m; int32_t ret; @@ -1430,7 +1440,7 @@ int32_t ism303dac_mg_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_self_test_set(const stmdev_ctx_t *ctx, ism303dac_xl_st_t val) { ism303dac_ctrl3_a_t ctrl3_a; @@ -1455,7 +1465,7 @@ int32_t ism303dac_xl_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_self_test_get(const stmdev_ctx_t *ctx, ism303dac_xl_st_t *val) { ism303dac_ctrl3_a_t ctrl3_a; @@ -1493,7 +1503,7 @@ int32_t ism303dac_xl_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_self_test_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism303dac_mg_self_test_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_cfg_reg_c_m_t cfg_reg_c_m; int32_t ret; @@ -1519,7 +1529,7 @@ int32_t ism303dac_mg_self_test_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_self_test_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism303dac_mg_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_cfg_reg_c_m_t cfg_reg_c_m; int32_t ret; @@ -1539,7 +1549,7 @@ int32_t ism303dac_mg_self_test_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_data_ready_mode_set(const stmdev_ctx_t *ctx, ism303dac_xl_drdy_pulsed_t val) { ism303dac_ctrl5_a_t ctrl5_a; @@ -1564,7 +1574,7 @@ int32_t ism303dac_xl_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_data_ready_mode_get(const stmdev_ctx_t *ctx, ism303dac_xl_drdy_pulsed_t *val) { ism303dac_ctrl5_a_t ctrl5_a; @@ -1611,7 +1621,7 @@ int32_t ism303dac_xl_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_hp_path_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_hp_path_set(const stmdev_ctx_t *ctx, ism303dac_xl_fds_slope_t val) { ism303dac_ctrl2_a_t ctrl2_a; @@ -1636,7 +1646,7 @@ int32_t ism303dac_xl_hp_path_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_hp_path_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_hp_path_get(const stmdev_ctx_t *ctx, ism303dac_xl_fds_slope_t *val) { ism303dac_ctrl2_a_t ctrl2_a; @@ -1670,7 +1680,7 @@ int32_t ism303dac_xl_hp_path_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_low_pass_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_low_pass_bandwidth_set(const stmdev_ctx_t *ctx, ism303dac_mg_lpf_t val) { ism303dac_cfg_reg_b_m_t cfg_reg_b_m; @@ -1697,7 +1707,7 @@ int32_t ism303dac_mg_low_pass_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_low_pass_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_low_pass_bandwidth_get(const stmdev_ctx_t *ctx, ism303dac_mg_lpf_t *val) { ism303dac_cfg_reg_b_m_t cfg_reg_b_m; @@ -1745,7 +1755,7 @@ int32_t ism303dac_mg_low_pass_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_spi_mode_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_spi_mode_set(const stmdev_ctx_t *ctx, ism303dac_xl_sim_t val) { ism303dac_ctrl2_a_t ctrl2_a; @@ -1770,7 +1780,7 @@ int32_t ism303dac_xl_spi_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_spi_mode_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_spi_mode_get(const stmdev_ctx_t *ctx, ism303dac_xl_sim_t *val) { ism303dac_ctrl2_a_t ctrl2_a; @@ -1804,7 +1814,7 @@ int32_t ism303dac_xl_spi_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_i2c_interface_set(const stmdev_ctx_t *ctx, ism303dac_xl_i2c_disable_t val) { ism303dac_ctrl2_a_t ctrl2_a; @@ -1829,7 +1839,7 @@ int32_t ism303dac_xl_i2c_interface_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_i2c_interface_get(const stmdev_ctx_t *ctx, ism303dac_xl_i2c_disable_t *val) { ism303dac_ctrl2_a_t ctrl2_a; @@ -1863,7 +1873,7 @@ int32_t ism303dac_xl_i2c_interface_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_i2c_interface_set(const stmdev_ctx_t *ctx, ism303dac_mg_i2c_dis_t val) { ism303dac_cfg_reg_c_m_t cfg_reg_c_m; @@ -1890,7 +1900,7 @@ int32_t ism303dac_mg_i2c_interface_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_i2c_interface_get(const stmdev_ctx_t *ctx, ism303dac_mg_i2c_dis_t *val) { ism303dac_cfg_reg_c_m_t cfg_reg_c_m; @@ -1926,7 +1936,7 @@ int32_t ism303dac_mg_i2c_interface_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_cs_mode_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_cs_mode_set(const stmdev_ctx_t *ctx, ism303dac_xl_if_cs_pu_dis_t val) { ism303dac_fifo_ctrl_a_t fifo_ctrl_a; @@ -1953,7 +1963,7 @@ int32_t ism303dac_xl_cs_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_cs_mode_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_cs_mode_get(const stmdev_ctx_t *ctx, ism303dac_xl_if_cs_pu_dis_t *val) { ism303dac_fifo_ctrl_a_t fifo_ctrl_a; @@ -2001,7 +2011,7 @@ int32_t ism303dac_xl_cs_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_pin_mode_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_pin_mode_set(const stmdev_ctx_t *ctx, ism303dac_xl_pp_od_t val) { ism303dac_ctrl3_a_t ctrl3_a; @@ -2026,7 +2036,7 @@ int32_t ism303dac_xl_pin_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_pin_mode_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_pin_mode_get(const stmdev_ctx_t *ctx, ism303dac_xl_pp_od_t *val) { ism303dac_ctrl3_a_t ctrl3_a; @@ -2060,7 +2070,7 @@ int32_t ism303dac_xl_pin_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_pin_polarity_set(const stmdev_ctx_t *ctx, ism303dac_xl_h_lactive_t val) { ism303dac_ctrl3_a_t ctrl3_a; @@ -2085,7 +2095,7 @@ int32_t ism303dac_xl_pin_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_pin_polarity_get(const stmdev_ctx_t *ctx, ism303dac_xl_h_lactive_t *val) { ism303dac_ctrl3_a_t ctrl3_a; @@ -2119,7 +2129,7 @@ int32_t ism303dac_xl_pin_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_int_notification_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_int_notification_set(const stmdev_ctx_t *ctx, ism303dac_xl_lir_t val) { ism303dac_ctrl3_a_t ctrl3_a; @@ -2144,7 +2154,7 @@ int32_t ism303dac_xl_int_notification_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_int_notification_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_int_notification_get(const stmdev_ctx_t *ctx, ism303dac_xl_lir_t *val) { ism303dac_ctrl3_a_t ctrl3_a; @@ -2178,7 +2188,7 @@ int32_t ism303dac_xl_int_notification_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_pin_int1_route_set(const stmdev_ctx_t *ctx, ism303dac_xl_pin_int1_route_t val) { ism303dac_ctrl4_a_t ctrl4_a; @@ -2223,7 +2233,7 @@ int32_t ism303dac_xl_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_pin_int1_route_get(const stmdev_ctx_t *ctx, ism303dac_xl_pin_int1_route_t *val) { ism303dac_ctrl4_a_t ctrl4_a; @@ -2261,7 +2271,7 @@ int32_t ism303dac_xl_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_pin_int2_route_set(const stmdev_ctx_t *ctx, ism303dac_xl_pin_int2_route_t val) { ism303dac_ctrl5_a_t ctrl5_a; @@ -2288,7 +2298,7 @@ int32_t ism303dac_xl_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_pin_int2_route_get(const stmdev_ctx_t *ctx, ism303dac_xl_pin_int2_route_t *val) { ism303dac_ctrl5_a_t ctrl5_a; @@ -2314,7 +2324,7 @@ int32_t ism303dac_xl_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism303dac_xl_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_ctrl5_a_t ctrl5_a; int32_t ret; @@ -2338,7 +2348,7 @@ int32_t ism303dac_xl_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism303dac_xl_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_ctrl5_a_t ctrl5_a; int32_t ret; @@ -2357,7 +2367,7 @@ int32_t ism303dac_xl_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_drdy_on_pin_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism303dac_mg_drdy_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_cfg_reg_c_m_t cfg_reg_c_m; int32_t ret; @@ -2383,7 +2393,7 @@ int32_t ism303dac_mg_drdy_on_pin_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_drdy_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism303dac_mg_drdy_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_cfg_reg_c_m_t cfg_reg_c_m; int32_t ret; @@ -2403,7 +2413,7 @@ int32_t ism303dac_mg_drdy_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_int_on_pin_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism303dac_mg_int_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_cfg_reg_c_m_t cfg_reg_c_m; int32_t ret; @@ -2429,7 +2439,7 @@ int32_t ism303dac_mg_int_on_pin_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_int_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism303dac_mg_int_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_cfg_reg_c_m_t cfg_reg_c_m; int32_t ret; @@ -2449,7 +2459,7 @@ int32_t ism303dac_mg_int_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_int_gen_conf_set(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_int_gen_conf_set(const stmdev_ctx_t *ctx, ism303dac_int_crtl_reg_m_t *val) { int32_t ret; @@ -2468,7 +2478,7 @@ int32_t ism303dac_mg_int_gen_conf_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_int_gen_conf_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_int_gen_conf_get(const stmdev_ctx_t *ctx, ism303dac_int_crtl_reg_m_t *val) { int32_t ret; @@ -2487,7 +2497,7 @@ int32_t ism303dac_mg_int_gen_conf_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_int_gen_source_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_int_gen_source_get(const stmdev_ctx_t *ctx, ism303dac_int_source_reg_m_t *val) { int32_t ret; @@ -2508,8 +2518,8 @@ int32_t ism303dac_mg_int_gen_source_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_int_gen_treshold_set(stmdev_ctx_t *ctx, - uint16_t val) +int32_t ism303dac_mg_int_gen_threshold_set(const stmdev_ctx_t *ctx, + uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -2531,8 +2541,8 @@ int32_t ism303dac_mg_int_gen_treshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_int_gen_treshold_get(stmdev_ctx_t *ctx, - uint16_t *val) +int32_t ism303dac_mg_int_gen_threshold_get(const stmdev_ctx_t *ctx, + uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -2578,7 +2588,7 @@ int32_t ism303dac_mg_int_gen_treshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_offset_int_conf_set(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_offset_int_conf_set(const stmdev_ctx_t *ctx, ism303dac_mg_int_on_dataoff_t val) { ism303dac_cfg_reg_b_m_t cfg_reg_b_m; @@ -2606,7 +2616,7 @@ int32_t ism303dac_mg_offset_int_conf_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_mg_offset_int_conf_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_offset_int_conf_get(const stmdev_ctx_t *ctx, ism303dac_mg_int_on_dataoff_t *val) { ism303dac_cfg_reg_b_m_t cfg_reg_b_m; @@ -2641,7 +2651,7 @@ int32_t ism303dac_mg_offset_int_conf_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_wkup_threshold_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_wake_up_ths_a_t wake_up_ths_a; @@ -2668,7 +2678,7 @@ int32_t ism303dac_xl_wkup_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_wkup_threshold_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_wake_up_ths_a_t wake_up_ths_a; @@ -2689,7 +2699,7 @@ int32_t ism303dac_xl_wkup_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism303dac_xl_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_wake_up_dur_a_t wake_up_dur_a; int32_t ret; @@ -2715,7 +2725,7 @@ int32_t ism303dac_xl_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism303dac_xl_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_wake_up_dur_a_t wake_up_dur_a; int32_t ret; @@ -2748,7 +2758,7 @@ int32_t ism303dac_xl_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism303dac_xl_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_wake_up_ths_a_t wake_up_ths_a; int32_t ret; @@ -2774,7 +2784,7 @@ int32_t ism303dac_xl_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism303dac_xl_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_wake_up_ths_a_t wake_up_ths_a; int32_t ret; @@ -2794,7 +2804,7 @@ int32_t ism303dac_xl_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism303dac_xl_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_wake_up_dur_a_t wake_up_dur_a; int32_t ret; @@ -2820,7 +2830,7 @@ int32_t ism303dac_xl_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_act_sleep_dur_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_wake_up_dur_a_t wake_up_dur_a; @@ -2854,7 +2864,7 @@ int32_t ism303dac_xl_act_sleep_dur_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_ctrl3_a_t ctrl3_a; @@ -2879,7 +2889,7 @@ int32_t ism303dac_xl_tap_detection_on_z_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_ctrl3_a_t ctrl3_a; @@ -2899,7 +2909,7 @@ int32_t ism303dac_xl_tap_detection_on_z_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_ctrl3_a_t ctrl3_a; @@ -2924,7 +2934,7 @@ int32_t ism303dac_xl_tap_detection_on_y_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_ctrl3_a_t ctrl3_a; @@ -2944,7 +2954,7 @@ int32_t ism303dac_xl_tap_detection_on_y_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_ctrl3_a_t ctrl3_a; @@ -2969,7 +2979,7 @@ int32_t ism303dac_xl_tap_detection_on_x_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_ctrl3_a_t ctrl3_a; @@ -2989,7 +2999,7 @@ int32_t ism303dac_xl_tap_detection_on_x_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism303dac_xl_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_tap_6d_ths_a_t tap_6d_ths_a; int32_t ret; @@ -3015,7 +3025,7 @@ int32_t ism303dac_xl_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_tap_threshold_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_tap_6d_ths_a_t tap_6d_ths_a; @@ -3040,7 +3050,7 @@ int32_t ism303dac_xl_tap_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism303dac_xl_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_int_dur_a_t int_dur_a; int32_t ret; @@ -3070,7 +3080,7 @@ int32_t ism303dac_xl_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism303dac_xl_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_int_dur_a_t int_dur_a; int32_t ret; @@ -3094,7 +3104,7 @@ int32_t ism303dac_xl_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism303dac_xl_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_int_dur_a_t int_dur_a; int32_t ret; @@ -3124,7 +3134,7 @@ int32_t ism303dac_xl_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism303dac_xl_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_int_dur_a_t int_dur_a; int32_t ret; @@ -3149,7 +3159,7 @@ int32_t ism303dac_xl_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism303dac_xl_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_int_dur_a_t int_dur_a; int32_t ret; @@ -3180,7 +3190,7 @@ int32_t ism303dac_xl_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism303dac_xl_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_int_dur_a_t int_dur_a; int32_t ret; @@ -3200,7 +3210,7 @@ int32_t ism303dac_xl_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_tap_mode_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_tap_mode_set(const stmdev_ctx_t *ctx, ism303dac_xl_single_double_tap_t val) { ism303dac_wake_up_ths_a_t wake_up_ths_a; @@ -3227,7 +3237,7 @@ int32_t ism303dac_xl_tap_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_tap_mode_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_tap_mode_get(const stmdev_ctx_t *ctx, ism303dac_xl_single_double_tap_t *val) { ism303dac_wake_up_ths_a_t wake_up_ths_a; @@ -3262,7 +3272,7 @@ int32_t ism303dac_xl_tap_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_tap_src_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_tap_src_get(const stmdev_ctx_t *ctx, ism303dac_tap_src_a_t *val) { int32_t ret; @@ -3293,7 +3303,7 @@ int32_t ism303dac_xl_tap_src_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_6d_threshold_set(const stmdev_ctx_t *ctx, ism303dac_xl_6d_ths_t val) { ism303dac_tap_6d_ths_a_t tap_6d_ths_a; @@ -3320,7 +3330,7 @@ int32_t ism303dac_xl_6d_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_6d_threshold_get(const stmdev_ctx_t *ctx, ism303dac_xl_6d_ths_t *val) { ism303dac_tap_6d_ths_a_t tap_6d_ths_a; @@ -3363,7 +3373,7 @@ int32_t ism303dac_xl_6d_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism303dac_xl_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_tap_6d_ths_a_t tap_6d_ths_a; int32_t ret; @@ -3389,7 +3399,7 @@ int32_t ism303dac_xl_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism303dac_xl_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_tap_6d_ths_a_t tap_6d_ths_a; int32_t ret; @@ -3409,7 +3419,7 @@ int32_t ism303dac_xl_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_6d_src_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_6d_src_get(const stmdev_ctx_t *ctx, ism303dac_6d_src_a_t *val) { int32_t ret; @@ -3440,7 +3450,7 @@ int32_t ism303dac_xl_6d_src_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism303dac_xl_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_wake_up_dur_a_t wake_up_dur_a; ism303dac_free_fall_a_t free_fall_a; @@ -3480,7 +3490,7 @@ int32_t ism303dac_xl_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism303dac_xl_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_wake_up_dur_a_t wake_up_dur_a; ism303dac_free_fall_a_t free_fall_a; @@ -3508,7 +3518,7 @@ int32_t ism303dac_xl_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_ff_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism303dac_xl_ff_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_free_fall_a_t free_fall_a; int32_t ret; @@ -3534,7 +3544,7 @@ int32_t ism303dac_xl_ff_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_ff_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism303dac_xl_ff_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_free_fall_a_t free_fall_a; int32_t ret; @@ -3567,7 +3577,7 @@ int32_t ism303dac_xl_ff_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_fifo_xl_module_batch_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_fifo_xl_module_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_fifo_ctrl_a_t fifo_ctrl_a; @@ -3595,7 +3605,7 @@ int32_t ism303dac_xl_fifo_xl_module_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_fifo_xl_module_batch_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_fifo_xl_module_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_fifo_ctrl_a_t fifo_ctrl_a; @@ -3616,7 +3626,7 @@ int32_t ism303dac_xl_fifo_xl_module_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_fifo_mode_set(const stmdev_ctx_t *ctx, ism303dac_xl_fmode_t val) { ism303dac_fifo_ctrl_a_t fifo_ctrl_a; @@ -3643,7 +3653,7 @@ int32_t ism303dac_xl_fifo_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_fifo_mode_get(const stmdev_ctx_t *ctx, ism303dac_xl_fmode_t *val) { ism303dac_fifo_ctrl_a_t fifo_ctrl_a; @@ -3690,7 +3700,7 @@ int32_t ism303dac_xl_fifo_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_fifo_watermark_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; @@ -3708,7 +3718,7 @@ int32_t ism303dac_xl_fifo_watermark_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_fifo_watermark_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -3726,7 +3736,7 @@ int32_t ism303dac_xl_fifo_watermark_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_fifo_full_flag_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_fifo_src_a_t fifo_src_a; @@ -3747,7 +3757,7 @@ int32_t ism303dac_xl_fifo_full_flag_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_fifo_ovr_flag_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_fifo_src_a_t fifo_src_a; @@ -3768,7 +3778,7 @@ int32_t ism303dac_xl_fifo_ovr_flag_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_fifo_wtm_flag_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_fifo_src_a_t fifo_src_a; @@ -3789,7 +3799,7 @@ int32_t ism303dac_xl_fifo_wtm_flag_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_fifo_data_level_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) { ism303dac_fifo_src_a_t fifo_src_a; @@ -3819,7 +3829,7 @@ int32_t ism303dac_xl_fifo_data_level_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_fifo_src_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_fifo_src_get(const stmdev_ctx_t *ctx, ism303dac_fifo_src_a_t *val) { int32_t ret; @@ -3850,7 +3860,7 @@ int32_t ism303dac_xl_fifo_src_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_module_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism303dac_xl_module_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { ism303dac_func_ctrl_a_t func_ctrl_a; int32_t ret; @@ -3876,7 +3886,7 @@ int32_t ism303dac_xl_module_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism303dac_xl_module_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism303dac_xl_module_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism303dac_func_ctrl_a_t func_ctrl_a; int32_t ret; diff --git a/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.h b/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.h index 31a9c5a5..a73300c2 100644 --- a/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.h +++ b/sensor/stmemsc/ism303dac_STdC/driver/ism303dac_reg.h @@ -767,10 +767,10 @@ typedef union * them with a custom implementation. */ -int32_t ism303dac_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t ism303dac_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t ism303dac_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t ism303dac_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -792,17 +792,17 @@ typedef struct ism303dac_6d_src_a_t _6d_src_a; ism303dac_func_src_a_t func_src_a; } ism303dac_xl_all_sources_t; -int32_t ism303dac_xl_all_sources_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_all_sources_get(const stmdev_ctx_t *ctx, ism303dac_xl_all_sources_t *val); -int32_t ism303dac_xl_block_data_update_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_xl_block_data_update_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_mg_block_data_update_set(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_mg_block_data_update_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -810,9 +810,9 @@ typedef enum ISM303DAC_MG_LSB_AT_LOW_ADD = 0, ISM303DAC_MG_MSB_AT_LOW_ADD = 1, } ism303dac_mg_ble_t; -int32_t ism303dac_mg_data_format_set(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_data_format_set(const stmdev_ctx_t *ctx, ism303dac_mg_ble_t val); -int32_t ism303dac_mg_data_format_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_data_format_get(const stmdev_ctx_t *ctx, ism303dac_mg_ble_t *val); typedef enum @@ -822,9 +822,9 @@ typedef enum ISM303DAC_XL_4g = 2, ISM303DAC_XL_8g = 3, } ism303dac_xl_fs_t; -int32_t ism303dac_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_full_scale_set(const stmdev_ctx_t *ctx, ism303dac_xl_fs_t val); -int32_t ism303dac_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_full_scale_get(const stmdev_ctx_t *ctx, ism303dac_xl_fs_t *val); typedef enum @@ -849,26 +849,26 @@ typedef enum ISM303DAC_XL_ODR_3k2Hz_HF = 0x16, ISM303DAC_XL_ODR_6k4Hz_HF = 0x17, } ism303dac_xl_odr_t; -int32_t ism303dac_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_data_rate_set(const stmdev_ctx_t *ctx, ism303dac_xl_odr_t val); -int32_t ism303dac_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_data_rate_get(const stmdev_ctx_t *ctx, ism303dac_xl_odr_t *val); -int32_t ism303dac_xl_status_reg_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_status_reg_get(const stmdev_ctx_t *ctx, ism303dac_status_a_t *val); -int32_t ism303dac_mg_status_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_status_get(const stmdev_ctx_t *ctx, ism303dac_status_reg_m_t *val); -int32_t ism303dac_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_mg_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_mg_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism303dac_mg_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism303dac_mg_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_mg_user_offset_set(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_user_offset_set(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t ism303dac_mg_user_offset_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_user_offset_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum @@ -877,9 +877,9 @@ typedef enum ISM303DAC_MG_SINGLE_TRIGGER = 1, ISM303DAC_MG_POWER_DOWN = 2, } ism303dac_mg_md_t; -int32_t ism303dac_mg_operating_mode_set(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_operating_mode_set(const stmdev_ctx_t *ctx, ism303dac_mg_md_t val); -int32_t ism303dac_mg_operating_mode_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_operating_mode_get(const stmdev_ctx_t *ctx, ism303dac_mg_md_t *val); typedef enum @@ -889,9 +889,9 @@ typedef enum ISM303DAC_MG_ODR_50Hz = 2, ISM303DAC_MG_ODR_100Hz = 3, } ism303dac_mg_odr_t; -int32_t ism303dac_mg_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_data_rate_set(const stmdev_ctx_t *ctx, ism303dac_mg_odr_t val); -int32_t ism303dac_mg_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_data_rate_get(const stmdev_ctx_t *ctx, ism303dac_mg_odr_t *val); typedef enum @@ -899,14 +899,14 @@ typedef enum ISM303DAC_MG_HIGH_RESOLUTION = 0, ISM303DAC_MG_LOW_POWER = 1, } ism303dac_mg_lp_t; -int32_t ism303dac_mg_power_mode_set(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_power_mode_set(const stmdev_ctx_t *ctx, ism303dac_mg_lp_t val); -int32_t ism303dac_mg_power_mode_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_power_mode_get(const stmdev_ctx_t *ctx, ism303dac_mg_lp_t *val); -int32_t ism303dac_mg_offset_temp_comp_set(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_offset_temp_comp_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_mg_offset_temp_comp_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_offset_temp_comp_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -915,47 +915,47 @@ typedef enum ISM303DAC_MG_SENS_OFF_CANC_EVERY_ODR = 1, ISM303DAC_MG_SET_SENS_ONLY_AT_POWER_ON = 2, } ism303dac_mg_set_rst_t; -int32_t ism303dac_mg_set_rst_mode_set(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_set_rst_mode_set(const stmdev_ctx_t *ctx, ism303dac_mg_set_rst_t val); -int32_t ism303dac_mg_set_rst_mode_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_set_rst_mode_get(const stmdev_ctx_t *ctx, ism303dac_mg_set_rst_t *val); -int32_t ism303dac_mg_set_rst_sensor_single_set(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_set_rst_sensor_single_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_mg_set_rst_sensor_single_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_set_rst_sensor_single_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_acceleration_module_raw_get(stmdev_ctx_t *ctx, +int32_t ism303dac_acceleration_module_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ism303dac_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t ism303dac_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t ism303dac_xl_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_temperature_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ism303dac_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t ism303dac_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t ism303dac_xl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t ism303dac_xl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ism303dac_mg_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t ism303dac_mg_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ism303dac_xl_auto_increment_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_xl_auto_increment_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_xl_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_xl_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism303dac_xl_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism303dac_xl_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_mg_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_mg_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism303dac_mg_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism303dac_mg_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_xl_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_xl_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism303dac_xl_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism303dac_xl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_mg_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_mg_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism303dac_mg_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism303dac_mg_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -963,22 +963,22 @@ typedef enum ISM303DAC_XL_ST_POSITIVE = 1, ISM303DAC_XL_ST_NEGATIVE = 2, } ism303dac_xl_st_t; -int32_t ism303dac_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_self_test_set(const stmdev_ctx_t *ctx, ism303dac_xl_st_t val); -int32_t ism303dac_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_self_test_get(const stmdev_ctx_t *ctx, ism303dac_xl_st_t *val); -int32_t ism303dac_mg_self_test_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_mg_self_test_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism303dac_mg_self_test_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism303dac_mg_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { ISM303DAC_XL_DRDY_LATCHED = 0, ISM303DAC_XL_DRDY_PULSED = 1, } ism303dac_xl_drdy_pulsed_t; -int32_t ism303dac_xl_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_data_ready_mode_set(const stmdev_ctx_t *ctx, ism303dac_xl_drdy_pulsed_t val); -int32_t ism303dac_xl_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_data_ready_mode_get(const stmdev_ctx_t *ctx, ism303dac_xl_drdy_pulsed_t *val); typedef enum @@ -986,9 +986,9 @@ typedef enum ISM303DAC_XL_HP_INTERNAL_ONLY = 0, ISM303DAC_XL_HP_ON_OUTPUTS = 1, } ism303dac_xl_fds_slope_t; -int32_t ism303dac_xl_hp_path_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_hp_path_set(const stmdev_ctx_t *ctx, ism303dac_xl_fds_slope_t val); -int32_t ism303dac_xl_hp_path_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_hp_path_get(const stmdev_ctx_t *ctx, ism303dac_xl_fds_slope_t *val); typedef enum @@ -996,9 +996,9 @@ typedef enum ISM303DAC_MG_ODR_DIV_2 = 0, ISM303DAC_MG_ODR_DIV_4 = 1, } ism303dac_mg_lpf_t; -int32_t ism303dac_mg_low_pass_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_low_pass_bandwidth_set(const stmdev_ctx_t *ctx, ism303dac_mg_lpf_t val); -int32_t ism303dac_mg_low_pass_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_low_pass_bandwidth_get(const stmdev_ctx_t *ctx, ism303dac_mg_lpf_t *val); typedef enum @@ -1006,9 +1006,9 @@ typedef enum ISM303DAC_XL_SPI_4_WIRE = 0, ISM303DAC_XL_SPI_3_WIRE = 1, } ism303dac_xl_sim_t; -int32_t ism303dac_xl_spi_mode_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_spi_mode_set(const stmdev_ctx_t *ctx, ism303dac_xl_sim_t val); -int32_t ism303dac_xl_spi_mode_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_spi_mode_get(const stmdev_ctx_t *ctx, ism303dac_xl_sim_t *val); typedef enum @@ -1016,9 +1016,9 @@ typedef enum ISM303DAC_XL_I2C_ENABLE = 0, ISM303DAC_XL_I2C_DISABLE = 1, } ism303dac_xl_i2c_disable_t; -int32_t ism303dac_xl_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_i2c_interface_set(const stmdev_ctx_t *ctx, ism303dac_xl_i2c_disable_t val); -int32_t ism303dac_xl_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_i2c_interface_get(const stmdev_ctx_t *ctx, ism303dac_xl_i2c_disable_t *val); typedef enum @@ -1026,9 +1026,9 @@ typedef enum ISM303DAC_MG_I2C_ENABLE = 0, ISM303DAC_MG_I2C_DISABLE = 1, } ism303dac_mg_i2c_dis_t; -int32_t ism303dac_mg_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_i2c_interface_set(const stmdev_ctx_t *ctx, ism303dac_mg_i2c_dis_t val); -int32_t ism303dac_mg_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_i2c_interface_get(const stmdev_ctx_t *ctx, ism303dac_mg_i2c_dis_t *val); typedef enum @@ -1036,9 +1036,9 @@ typedef enum ISM303DAC_XL_PULL_UP_CONNECTED = 0, ISM303DAC_XL_PULL_UP_DISCONNECTED = 1, } ism303dac_xl_if_cs_pu_dis_t; -int32_t ism303dac_xl_cs_mode_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_cs_mode_set(const stmdev_ctx_t *ctx, ism303dac_xl_if_cs_pu_dis_t val); -int32_t ism303dac_xl_cs_mode_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_cs_mode_get(const stmdev_ctx_t *ctx, ism303dac_xl_if_cs_pu_dis_t *val); typedef enum @@ -1046,9 +1046,9 @@ typedef enum ISM303DAC_XL_PUSH_PULL = 0, ISM303DAC_XL_OPEN_DRAIN = 1, } ism303dac_xl_pp_od_t; -int32_t ism303dac_xl_pin_mode_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_pin_mode_set(const stmdev_ctx_t *ctx, ism303dac_xl_pp_od_t val); -int32_t ism303dac_xl_pin_mode_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_pin_mode_get(const stmdev_ctx_t *ctx, ism303dac_xl_pp_od_t *val); typedef enum @@ -1056,9 +1056,9 @@ typedef enum ISM303DAC_XL_ACTIVE_HIGH = 0, ISM303DAC_XL_ACTIVE_LOW = 1, } ism303dac_xl_h_lactive_t; -int32_t ism303dac_xl_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_pin_polarity_set(const stmdev_ctx_t *ctx, ism303dac_xl_h_lactive_t val); -int32_t ism303dac_xl_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_pin_polarity_get(const stmdev_ctx_t *ctx, ism303dac_xl_h_lactive_t *val); typedef enum @@ -1066,9 +1066,9 @@ typedef enum ISM303DAC_XL_INT_PULSED = 0, ISM303DAC_XL_INT_LATCHED = 1, } ism303dac_xl_lir_t; -int32_t ism303dac_xl_int_notification_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_int_notification_set(const stmdev_ctx_t *ctx, ism303dac_xl_lir_t val); -int32_t ism303dac_xl_int_notification_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_int_notification_get(const stmdev_ctx_t *ctx, ism303dac_xl_lir_t *val); typedef struct @@ -1082,9 +1082,9 @@ typedef struct uint8_t int1_s_tap : 1; uint8_t int1_fss7 : 1; } ism303dac_xl_pin_int1_route_t; -int32_t ism303dac_xl_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_pin_int1_route_set(const stmdev_ctx_t *ctx, ism303dac_xl_pin_int1_route_t val); -int32_t ism303dac_xl_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_pin_int1_route_get(const stmdev_ctx_t *ctx, ism303dac_xl_pin_int1_route_t *val); typedef struct @@ -1093,99 +1093,99 @@ typedef struct uint8_t int2_fth : 1; uint8_t int2_drdy : 1; } ism303dac_xl_pin_int2_route_t; -int32_t ism303dac_xl_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_pin_int2_route_set(const stmdev_ctx_t *ctx, ism303dac_xl_pin_int2_route_t val); -int32_t ism303dac_xl_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_pin_int2_route_get(const stmdev_ctx_t *ctx, ism303dac_xl_pin_int2_route_t *val); -int32_t ism303dac_xl_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_xl_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism303dac_xl_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism303dac_xl_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_mg_drdy_on_pin_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_mg_drdy_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism303dac_mg_drdy_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism303dac_mg_drdy_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_mg_int_on_pin_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_mg_int_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism303dac_mg_int_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism303dac_mg_int_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_mg_int_gen_conf_set(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_int_gen_conf_set(const stmdev_ctx_t *ctx, ism303dac_int_crtl_reg_m_t *val); -int32_t ism303dac_mg_int_gen_conf_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_int_gen_conf_get(const stmdev_ctx_t *ctx, ism303dac_int_crtl_reg_m_t *val); -int32_t ism303dac_mg_int_gen_source_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_int_gen_source_get(const stmdev_ctx_t *ctx, ism303dac_int_source_reg_m_t *val); -int32_t ism303dac_mg_int_gen_treshold_set(stmdev_ctx_t *ctx, - uint16_t val); -int32_t ism303dac_mg_int_gen_treshold_get(stmdev_ctx_t *ctx, - uint16_t *val); +int32_t ism303dac_mg_int_gen_threshold_set(const stmdev_ctx_t *ctx, + uint16_t val); +int32_t ism303dac_mg_int_gen_threshold_get(const stmdev_ctx_t *ctx, + uint16_t *val); typedef enum { ISM303DAC_MG_CHECK_BEFORE = 0, ISM303DAC_MG_CHECK_AFTER = 1, } ism303dac_mg_int_on_dataoff_t; -int32_t ism303dac_mg_offset_int_conf_set(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_offset_int_conf_set(const stmdev_ctx_t *ctx, ism303dac_mg_int_on_dataoff_t val); -int32_t ism303dac_mg_offset_int_conf_get(stmdev_ctx_t *ctx, +int32_t ism303dac_mg_offset_int_conf_get(const stmdev_ctx_t *ctx, ism303dac_mg_int_on_dataoff_t *val); -int32_t ism303dac_xl_wkup_threshold_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_xl_wkup_threshold_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_xl_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_xl_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism303dac_xl_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism303dac_xl_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_xl_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_xl_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism303dac_xl_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism303dac_xl_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_xl_act_sleep_dur_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_xl_act_sleep_dur_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_xl_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_xl_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_xl_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_xl_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_xl_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_xl_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_xl_tap_threshold_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_xl_tap_threshold_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_xl_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_xl_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism303dac_xl_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism303dac_xl_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_xl_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_xl_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism303dac_xl_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism303dac_xl_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_xl_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_xl_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism303dac_xl_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism303dac_xl_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { ISM303DAC_XL_ONLY_SINGLE = 0, ISM303DAC_XL_ONLY_DOUBLE = 1, } ism303dac_xl_single_double_tap_t; -int32_t ism303dac_xl_tap_mode_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_tap_mode_set(const stmdev_ctx_t *ctx, ism303dac_xl_single_double_tap_t val); -int32_t ism303dac_xl_tap_mode_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_tap_mode_get(const stmdev_ctx_t *ctx, ism303dac_xl_single_double_tap_t *val); -int32_t ism303dac_xl_tap_src_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_tap_src_get(const stmdev_ctx_t *ctx, ism303dac_tap_src_a_t *val); typedef enum @@ -1195,27 +1195,27 @@ typedef enum ISM303DAC_XL_DEG_60 = 2, ISM303DAC_XL_DEG_50 = 3, } ism303dac_xl_6d_ths_t; -int32_t ism303dac_xl_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_6d_threshold_set(const stmdev_ctx_t *ctx, ism303dac_xl_6d_ths_t val); -int32_t ism303dac_xl_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_6d_threshold_get(const stmdev_ctx_t *ctx, ism303dac_xl_6d_ths_t *val); -int32_t ism303dac_xl_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_xl_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism303dac_xl_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism303dac_xl_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_xl_6d_src_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_6d_src_get(const stmdev_ctx_t *ctx, ism303dac_6d_src_a_t *val); -int32_t ism303dac_xl_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_xl_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism303dac_xl_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism303dac_xl_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_xl_ff_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_xl_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_ff_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism303dac_xl_ff_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_xl_fifo_xl_module_batch_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_fifo_xl_module_batch_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_xl_fifo_xl_module_batch_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_fifo_xl_module_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -1226,33 +1226,33 @@ typedef enum ISM303DAC_XL_BYPASS_TO_STREAM_MODE = 4, ISM303DAC_XL_STREAM_MODE = 6, } ism303dac_xl_fmode_t; -int32_t ism303dac_xl_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_fifo_mode_set(const stmdev_ctx_t *ctx, ism303dac_xl_fmode_t val); -int32_t ism303dac_xl_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_fifo_mode_get(const stmdev_ctx_t *ctx, ism303dac_xl_fmode_t *val); -int32_t ism303dac_xl_fifo_watermark_set(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_xl_fifo_watermark_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_xl_fifo_full_flag_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_xl_fifo_ovr_flag_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_xl_fifo_wtm_flag_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism303dac_xl_fifo_data_level_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t ism303dac_xl_fifo_src_get(stmdev_ctx_t *ctx, +int32_t ism303dac_xl_fifo_src_get(const stmdev_ctx_t *ctx, ism303dac_fifo_src_a_t *val); -int32_t ism303dac_xl_module_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism303dac_xl_module_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism303dac_xl_module_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism303dac_xl_module_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); /** * @} diff --git a/sensor/stmemsc/ism330bx_STdC/driver/ism330bx_reg.c b/sensor/stmemsc/ism330bx_STdC/driver/ism330bx_reg.c new file mode 100644 index 00000000..96b4f943 --- /dev/null +++ b/sensor/stmemsc/ism330bx_STdC/driver/ism330bx_reg.c @@ -0,0 +1,8439 @@ +/** + ****************************************************************************** + * @file ism330bx_reg.c + * @author Sensors Software Solution Team + * @brief ISM330BX driver file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2024 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "ism330bx_reg.h" + +/** + * @defgroup ISM330BX + * @brief This file provides a set of functions needed to drive the + * ism330bx enhanced inertial module. + * @{ + * + */ + +/** + * @defgroup Interfaces functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +/** + * @brief Read generic device register + * + * @param ctx communication interface handler.(ptr) + * @param reg first register address to read. + * @param data buffer for data read.(ptr) + * @param len number of consecutive register to read. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak ism330bx_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) +{ + int32_t ret; + + if (ctx == NULL) + { + return -1; + } + + ret = ctx->read_reg(ctx->handle, reg, data, len); + + return ret; +} + +/** + * @brief Write generic device register + * + * @param ctx communication interface handler.(ptr) + * @param reg first register address to write. + * @param data the buffer contains data to be written.(ptr) + * @param len number of consecutive register to write. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak ism330bx_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) +{ + int32_t ret; + + if (ctx == NULL) + { + return -1; + } + + ret = ctx->write_reg(ctx->handle, reg, data, len); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Private functions + * @brief Section collect all the utility functions needed by APIs. + * @{ + * + */ + +static void bytecpy(uint8_t *target, uint8_t *source) +{ + if ((target != NULL) && (source != NULL)) + { + *target = *source; + } +} + +/** + * @} + * + */ + +/** + * @defgroup Sensitivity + * @brief These functions convert raw-data into engineering units. + * @{ + * + */ +float_t ism330bx_from_sflp_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.061f; +} + +float_t ism330bx_from_fs2_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.061f; +} + +float_t ism330bx_from_fs4_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.122f; +} + +float_t ism330bx_from_fs8_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.244f; +} + +float_t ism330bx_from_fs16_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.488f; +} + +float_t ism330bx_from_fs125_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 4.375f; +} + +float_t ism330bx_from_fs250_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 8.750f; +} + +float_t ism330bx_from_fs500_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 17.50f; +} + +float_t ism330bx_from_fs1000_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 35.0f; +} + +float_t ism330bx_from_fs2000_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 70.0f; +} + +float_t ism330bx_from_fs4000_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 140.0f; +} + +float_t ism330bx_from_lsb_to_celsius(int16_t lsb) +{ + return (((float_t)lsb / 256.0f) + 25.0f); +} + +uint64_t ism330bx_from_lsb_to_nsec(uint32_t lsb) +{ + return ((uint64_t)lsb * 21750); +} + +float_t ism330bx_from_lsb_to_mv(int16_t lsb) +{ + return ((float_t)lsb) / 78.0f; +} + +/** + * @} + * + */ + +/** + * @defgroup Common + * @brief This section groups common useful functions. + * + */ + +/** + * @brief Reset of the device.[set] + * + * @param ctx read / write interface definitions + * @param val Reset of the device. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_reset_set(const stmdev_ctx_t *ctx, ism330bx_reset_t val) +{ + ism330bx_func_cfg_access_t func_cfg_access; + ism330bx_ctrl3_t ctrl3; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + ctrl3.boot = ((uint8_t)val & 0x04U) >> 2; + ctrl3.sw_reset = ((uint8_t)val & 0x02U) >> 1; + func_cfg_access.sw_por = (uint8_t)val & 0x01U; + + if (ret == 0) + { + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL3, (uint8_t *)&ctrl3, 1); + } + if (ret == 0) + { + ret = ism330bx_write_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Global reset of the device.[get] + * + * @param ctx read / write interface definitions + * @param val Global reset of the device. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_reset_get(const stmdev_ctx_t *ctx, ism330bx_reset_t *val) +{ + ism330bx_func_cfg_access_t func_cfg_access; + ism330bx_ctrl3_t ctrl3; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + switch ((ctrl3.sw_reset << 2) + (ctrl3.boot << 1) + func_cfg_access.sw_por) + { + case ISM330BX_READY: + *val = ISM330BX_READY; + break; + + case ISM330BX_GLOBAL_RST: + *val = ISM330BX_GLOBAL_RST; + break; + + case ISM330BX_RESTORE_CAL_PARAM: + *val = ISM330BX_RESTORE_CAL_PARAM; + break; + + case ISM330BX_RESTORE_CTRL_REGS: + *val = ISM330BX_RESTORE_CTRL_REGS; + break; + + default: + *val = ISM330BX_GLOBAL_RST; + break; + } + return ret; +} + +/** + * @brief Change memory bank.[set] + * + * @param ctx read / write interface definitions + * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_mem_bank_set(const stmdev_ctx_t *ctx, ism330bx_mem_bank_t val) +{ + ism330bx_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret == 0) + { + func_cfg_access.emb_func_reg_access = (uint8_t)val & 0x01U; + ret = ism330bx_write_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Change memory bank.[get] + * + * @param ctx read / write interface definitions + * @param val MAIN_MEM_BANK, SENSOR_HUB_MEM_BANK, EMBED_FUNC_MEM_BANK, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_mem_bank_get(const stmdev_ctx_t *ctx, ism330bx_mem_bank_t *val) +{ + ism330bx_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + switch (func_cfg_access.emb_func_reg_access) + { + case ISM330BX_MAIN_MEM_BANK: + *val = ISM330BX_MAIN_MEM_BANK; + break; + + case ISM330BX_EMBED_FUNC_MEM_BANK: + *val = ISM330BX_EMBED_FUNC_MEM_BANK; + break; + + default: + *val = ISM330BX_MAIN_MEM_BANK; + break; + } + return ret; +} + +/** + * @brief Device ID.[get] + * + * @param ctx read / write interface definitions + * @param val Device ID. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_who_am_i_t who_am_i; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_WHO_AM_I, (uint8_t *)&who_am_i, 1); + *val = who_am_i.id; + + return ret; +} + +/** + * @brief Accelerometer output data rate (ODR) selection.[set] + * + * @param ctx read / write interface definitions + * @param val ism330bx_xl_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_xl_data_rate_set(const stmdev_ctx_t *ctx, + ism330bx_xl_data_rate_t val) +{ + ism330bx_ctrl1_t ctrl1; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret == 0) + { + ctrl1.odr_xl = (uint8_t)val & 0xFU; + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL1, (uint8_t *)&ctrl1, 1); + } + + return ret; +} + +/** + * @brief Accelerometer output data rate (ODR) selection.[get] + * + * @param ctx read / write interface definitions + * @param val ism330bx_xl_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_xl_data_rate_get(const stmdev_ctx_t *ctx, + ism330bx_xl_data_rate_t *val) +{ + ism330bx_ctrl1_t ctrl1; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL1, (uint8_t *)&ctrl1, 1); + + switch (ctrl1.odr_xl) + { + case ISM330BX_XL_ODR_OFF: + *val = ISM330BX_XL_ODR_OFF; + break; + + case ISM330BX_XL_ODR_AT_1Hz875: + *val = ISM330BX_XL_ODR_AT_1Hz875; + break; + + case ISM330BX_XL_ODR_AT_7Hz5: + *val = ISM330BX_XL_ODR_AT_7Hz5; + break; + + case ISM330BX_XL_ODR_AT_15Hz: + *val = ISM330BX_XL_ODR_AT_15Hz; + break; + + case ISM330BX_XL_ODR_AT_30Hz: + *val = ISM330BX_XL_ODR_AT_30Hz; + break; + + case ISM330BX_XL_ODR_AT_60Hz: + *val = ISM330BX_XL_ODR_AT_60Hz; + break; + + case ISM330BX_XL_ODR_AT_120Hz: + *val = ISM330BX_XL_ODR_AT_120Hz; + break; + + case ISM330BX_XL_ODR_AT_240Hz: + *val = ISM330BX_XL_ODR_AT_240Hz; + break; + + case ISM330BX_XL_ODR_AT_480Hz: + *val = ISM330BX_XL_ODR_AT_480Hz; + break; + + case ISM330BX_XL_ODR_AT_960Hz: + *val = ISM330BX_XL_ODR_AT_960Hz; + break; + + case ISM330BX_XL_ODR_AT_1920Hz: + *val = ISM330BX_XL_ODR_AT_1920Hz; + break; + + case ISM330BX_XL_ODR_AT_3840Hz: + *val = ISM330BX_XL_ODR_AT_3840Hz; + break; + + default: + *val = ISM330BX_XL_ODR_OFF; + break; + } + return ret; +} + +/** + * @brief Accelerometer operating mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val ism330bx_xl_mode_t struct + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_xl_mode_set(const stmdev_ctx_t *ctx, ism330bx_xl_mode_t val) +{ + ism330bx_ctrl1_t ctrl1; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL1, (uint8_t *)&ctrl1, 1); + + if (ret == 0) + { + ctrl1.op_mode_xl = (uint8_t)val & 0x07U; + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL1, (uint8_t *)&ctrl1, 1); + } + + return ret; +} + +/** + * @brief Accelerometer operating mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val ism330bx_xl_mode_t struct + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_xl_mode_get(const stmdev_ctx_t *ctx, ism330bx_xl_mode_t *val) +{ + ism330bx_ctrl1_t ctrl1; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL1, (uint8_t *)&ctrl1, 1); + + switch (ctrl1.op_mode_xl) + { + case ISM330BX_XL_HIGH_PERFORMANCE_MD: + *val = ISM330BX_XL_HIGH_PERFORMANCE_MD; + break; + + case ISM330BX_XL_HIGH_PERFORMANCE_TDM_MD: + *val = ISM330BX_XL_HIGH_PERFORMANCE_TDM_MD; + break; + + case ISM330BX_XL_LOW_POWER_2_AVG_MD: + *val = ISM330BX_XL_LOW_POWER_2_AVG_MD; + break; + + case ISM330BX_XL_LOW_POWER_4_AVG_MD: + *val = ISM330BX_XL_LOW_POWER_4_AVG_MD; + break; + + case ISM330BX_XL_LOW_POWER_8_AVG_MD: + *val = ISM330BX_XL_LOW_POWER_8_AVG_MD; + break; + + default: + *val = ISM330BX_XL_HIGH_PERFORMANCE_MD; + break; + } + return ret; +} + +/** + * @brief Gyroscope output data rate (ODR) selection.[set] + * + * @param ctx read / write interface definitions + * @param val ism330bx_gy_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_gy_data_rate_set(const stmdev_ctx_t *ctx, + ism330bx_gy_data_rate_t val) +{ + ism330bx_ctrl2_t ctrl2; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL2, (uint8_t *)&ctrl2, 1); + + if (ret == 0) + { + ctrl2.odr_g = (uint8_t)val & 0xFU; + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL2, (uint8_t *)&ctrl2, 1); + } + + return ret; +} + +/** + * @brief Gyroscope output data rate (ODR) selection.[get] + * + * @param ctx read / write interface definitions + * @param val ism330bx_gy_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_gy_data_rate_get(const stmdev_ctx_t *ctx, + ism330bx_gy_data_rate_t *val) +{ + ism330bx_ctrl2_t ctrl2; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL2, (uint8_t *)&ctrl2, 1); + + switch (ctrl2.odr_g) + { + case ISM330BX_GY_ODR_OFF: + *val = ISM330BX_GY_ODR_OFF; + break; + + case ISM330BX_GY_ODR_AT_7Hz5: + *val = ISM330BX_GY_ODR_AT_7Hz5; + break; + + case ISM330BX_GY_ODR_AT_15Hz: + *val = ISM330BX_GY_ODR_AT_15Hz; + break; + + case ISM330BX_GY_ODR_AT_30Hz: + *val = ISM330BX_GY_ODR_AT_30Hz; + break; + + case ISM330BX_GY_ODR_AT_60Hz: + *val = ISM330BX_GY_ODR_AT_60Hz; + break; + + case ISM330BX_GY_ODR_AT_120Hz: + *val = ISM330BX_GY_ODR_AT_120Hz; + break; + + case ISM330BX_GY_ODR_AT_240Hz: + *val = ISM330BX_GY_ODR_AT_240Hz; + break; + + case ISM330BX_GY_ODR_AT_480Hz: + *val = ISM330BX_GY_ODR_AT_480Hz; + break; + + case ISM330BX_GY_ODR_AT_960Hz: + *val = ISM330BX_GY_ODR_AT_960Hz; + break; + + case ISM330BX_GY_ODR_AT_1920Hz: + *val = ISM330BX_GY_ODR_AT_1920Hz; + break; + + case ISM330BX_GY_ODR_AT_3840Hz: + *val = ISM330BX_GY_ODR_AT_3840Hz; + break; + + default: + *val = ISM330BX_GY_ODR_OFF; + break; + } + return ret; +} + +/** + * @brief Gyroscope operating mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURANCY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_gy_mode_set(const stmdev_ctx_t *ctx, ism330bx_gy_mode_t val) +{ + ism330bx_ctrl2_t ctrl2; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret == 0) + { + ctrl2.op_mode_g = (uint8_t)val & 0x07U; + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL2, (uint8_t *)&ctrl2, 1); + } + + return ret; +} + +/** + * @brief Gyroscope operating mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURANCY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_gy_mode_get(const stmdev_ctx_t *ctx, ism330bx_gy_mode_t *val) +{ + ism330bx_ctrl2_t ctrl2; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL2, (uint8_t *)&ctrl2, 1); + switch (ctrl2.op_mode_g) + { + case ISM330BX_GY_HIGH_PERFORMANCE_MD: + *val = ISM330BX_GY_HIGH_PERFORMANCE_MD; + break; + + case ISM330BX_GY_SLEEP_MD: + *val = ISM330BX_GY_SLEEP_MD; + break; + + case ISM330BX_GY_LOW_POWER_MD: + *val = ISM330BX_GY_LOW_POWER_MD; + break; + + default: + *val = ISM330BX_GY_HIGH_PERFORMANCE_MD; + break; + } + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[set] + * + * @param ctx read / write interface definitions + * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_ctrl3_t ctrl3; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret == 0) + { + ctrl3.if_inc = val; + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL3, (uint8_t *)&ctrl3, 1); + } + + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[get] + * + * @param ctx read / write interface definitions + * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_ctrl3_t ctrl3; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL3, (uint8_t *)&ctrl3, 1); + *val = ctrl3.if_inc; + + + return ret; +} + +/** + * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [set] + * + * @param ctx read / write interface definitions + * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_ctrl3_t ctrl3; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL3, (uint8_t *)&ctrl3, 1); + + if (ret == 0) + { + ctrl3.bdu = val; + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL3, (uint8_t *)&ctrl3, 1); + } + + return ret; +} + +/** + * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [get] + * + * @param ctx read / write interface definitions + * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_ctrl3_t ctrl3; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL3, (uint8_t *)&ctrl3, 1); + *val = ctrl3.bdu; + + return ret; +} + +/** + * @brief Enables pulsed data-ready mode (~75 us).[set] + * + * @param ctx read / write interface definitions + * @param val DRDY_LATCHED, DRDY_PULSED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_data_ready_mode_set(const stmdev_ctx_t *ctx, + ism330bx_data_ready_mode_t val) +{ + ism330bx_ctrl4_t ctrl4; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL4, (uint8_t *)&ctrl4, 1); + + if (ret == 0) + { + ctrl4.drdy_pulsed = (uint8_t)val & 0x1U; + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL4, (uint8_t *)&ctrl4, 1); + } + + return ret; +} + +/** + * @brief Enables pulsed data-ready mode (~75 us).[get] + * + * @param ctx read / write interface definitions + * @param val DRDY_LATCHED, DRDY_PULSED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_data_ready_mode_get(const stmdev_ctx_t *ctx, + ism330bx_data_ready_mode_t *val) +{ + ism330bx_ctrl4_t ctrl4; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL4, (uint8_t *)&ctrl4, 1); + + switch (ctrl4.drdy_pulsed) + { + case ISM330BX_DRDY_LATCHED: + *val = ISM330BX_DRDY_LATCHED; + break; + + case ISM330BX_DRDY_PULSED: + *val = ISM330BX_DRDY_PULSED; + break; + + default: + *val = ISM330BX_DRDY_LATCHED; + break; + } + return ret; +} + +/** + * @brief Gyroscope full-scale selection[set] + * + * @param ctx read / write interface definitions + * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_gy_full_scale_set(const stmdev_ctx_t *ctx, + ism330bx_gy_full_scale_t val) +{ + ism330bx_ctrl6_t ctrl6; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL6, (uint8_t *)&ctrl6, 1); + + if (ret == 0) + { + ctrl6.fs_g = (uint8_t)val & 0xFU; + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL6, (uint8_t *)&ctrl6, 1); + } + + return ret; +} + +/** + * @brief Gyroscope full-scale selection[get] + * + * @param ctx read / write interface definitions + * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_gy_full_scale_get(const stmdev_ctx_t *ctx, + ism330bx_gy_full_scale_t *val) +{ + ism330bx_ctrl6_t ctrl6; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL6, (uint8_t *)&ctrl6, 1); + + switch (ctrl6.fs_g) + { + case ISM330BX_125dps: + *val = ISM330BX_125dps; + break; + + case ISM330BX_250dps: + *val = ISM330BX_250dps; + break; + + case ISM330BX_500dps: + *val = ISM330BX_500dps; + break; + + case ISM330BX_1000dps: + *val = ISM330BX_1000dps; + break; + + case ISM330BX_2000dps: + *val = ISM330BX_2000dps; + break; + + case ISM330BX_4000dps: + *val = ISM330BX_4000dps; + break; + + default: + *val = ISM330BX_125dps; + break; + } + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[set] + * + * @param ctx read / write interface definitions + * @param val 2g, 4g, 8g, 16g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_xl_full_scale_set(const stmdev_ctx_t *ctx, + ism330bx_xl_full_scale_t val) +{ + ism330bx_ctrl8_t ctrl8; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1); + + if (ret == 0) + { + ctrl8.fs_xl = (uint8_t)val & 0x3U; + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1); + } + + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[get] + * + * @param ctx read / write interface definitions + * @param val 2g, 4g, 8g, 16g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_xl_full_scale_get(const stmdev_ctx_t *ctx, + ism330bx_xl_full_scale_t *val) +{ + ism330bx_ctrl8_t ctrl8; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1); + + switch (ctrl8.fs_xl) + { + case ISM330BX_2g: + *val = ISM330BX_2g; + break; + + case ISM330BX_4g: + *val = ISM330BX_4g; + break; + + case ISM330BX_8g: + *val = ISM330BX_8g; + break; + + default: + *val = ISM330BX_2g; + break; + } + return ret; +} + +/** + * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[set] + * + * @param ctx read / write interface definitions + * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_xl_dual_channel_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_ctrl8_t ctrl8; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1); + + if (ret == 0) + { + ctrl8.xl_dualc_en = val; + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1); + } + + return ret; +} + +/** + * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[get] + * + * @param ctx read / write interface definitions + * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_ctrl8_t ctrl8; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1); + *val = ctrl8.xl_dualc_en; + + return ret; +} + +/** + * @brief Accelerometer self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_xl_self_test_set(const stmdev_ctx_t *ctx, + ism330bx_xl_self_test_t val) +{ + ism330bx_ctrl10_t ctrl10; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1); + + if (ret == 0) + { + ctrl10.st_xl = (uint8_t)val & 0x3U; + ctrl10.xl_st_offset = ((uint8_t)val & 0x04U) >> 2; + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1); + } + + return ret; +} + +/** + * @brief Accelerometer self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_xl_self_test_get(const stmdev_ctx_t *ctx, + ism330bx_xl_self_test_t *val) +{ + ism330bx_ctrl10_t ctrl10; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1); + + //switch (ctrl10.xl_st_offset) + switch (ctrl10.st_xl) + { + case ISM330BX_XL_ST_DISABLE: + *val = ISM330BX_XL_ST_DISABLE; + break; + + case ISM330BX_XL_ST_POSITIVE: + *val = ISM330BX_XL_ST_POSITIVE; + break; + + case ISM330BX_XL_ST_NEGATIVE: + *val = ISM330BX_XL_ST_NEGATIVE; + break; + + default: + *val = ISM330BX_XL_ST_DISABLE; + break; + } + return ret; +} + +/** + * @brief Gyroscope self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_gy_self_test_set(const stmdev_ctx_t *ctx, + ism330bx_gy_self_test_t val) +{ + ism330bx_ctrl10_t ctrl10; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1); + + if (ret == 0) + { + ctrl10.st_g = (uint8_t)val & 0x3U; + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1); + } + + return ret; +} + +/** + * @brief Gyroscope self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_gy_self_test_get(const stmdev_ctx_t *ctx, + ism330bx_gy_self_test_t *val) +{ + ism330bx_ctrl10_t ctrl10; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1); + + switch (ctrl10.st_g) + { + case ISM330BX_GY_ST_DISABLE: + *val = ISM330BX_GY_ST_DISABLE; + break; + + case ISM330BX_GY_ST_POSITIVE: + *val = ISM330BX_GY_ST_POSITIVE; + break; + + case ISM330BX_GY_ST_NEGATIVE: + *val = ISM330BX_GY_ST_NEGATIVE; + break; + + default: + *val = ISM330BX_GY_ST_DISABLE; + break; + } + return ret; +} + +/** + * @brief Get the status of all the interrupt sources.[get] + * + * @param ctx read / write interface definitions + * @param val Get the status of all the interrupt sources. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_all_sources_get(const stmdev_ctx_t *ctx, + ism330bx_all_sources_t *val) +{ + ism330bx_emb_func_status_mainpage_t emb_func_status_mainpage; + ism330bx_emb_func_exec_status_t emb_func_exec_status; + ism330bx_fsm_status_mainpage_t fsm_status_mainpage; + ism330bx_mlc_status_mainpage_t mlc_status_mainpage; + ism330bx_functions_enable_t functions_enable; + ism330bx_emb_func_src_t emb_func_src; + ism330bx_fifo_status2_t fifo_status2; + ism330bx_all_int_src_t all_int_src; + ism330bx_wake_up_src_t wake_up_src; + ism330bx_status_reg_t status_reg; + ism330bx_d6d_src_t d6d_src; + ism330bx_tap_src_t tap_src; + uint8_t buff[7]; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret == 0) + { + functions_enable.dis_rst_lir_all_int = PROPERTY_ENABLE; + ret = ism330bx_write_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_STATUS1, (uint8_t *)&buff, 4); + } + bytecpy((uint8_t *)&fifo_status2, &buff[1]); + bytecpy((uint8_t *)&all_int_src, &buff[2]); + bytecpy((uint8_t *)&status_reg, &buff[3]); + + val->fifo_ovr = fifo_status2.fifo_ovr_ia; + val->fifo_bdr = fifo_status2.counter_bdr_ia; + val->fifo_full = fifo_status2.fifo_full_ia; + val->fifo_th = fifo_status2.fifo_wtm_ia; + + val->free_fall = all_int_src.ff_ia; + val->wake_up = all_int_src.wu_ia; + val->six_d = all_int_src.d6d_ia; + + val->drdy_xl = status_reg.xlda; + val->drdy_gy = status_reg.gda; + val->drdy_temp = status_reg.tda; + val->drdy_ah_qvar = status_reg.ah_qvarda; + val->timestamp = status_reg.timestamp_endcount; + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + if (ret == 0) + { + functions_enable.dis_rst_lir_all_int = PROPERTY_DISABLE; + ret = ism330bx_write_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_SRC, (uint8_t *)&buff, 7); + } + + if (ret == 0) + { + bytecpy((uint8_t *)&wake_up_src, &buff[0]); + bytecpy((uint8_t *)&tap_src, &buff[1]); + bytecpy((uint8_t *)&d6d_src, &buff[2]); + bytecpy((uint8_t *)&emb_func_status_mainpage, &buff[4]); + bytecpy((uint8_t *)&fsm_status_mainpage, &buff[5]); + bytecpy((uint8_t *)&mlc_status_mainpage, &buff[6]); + + val->sleep_change = wake_up_src.sleep_change_ia; + val->wake_up_x = wake_up_src.x_wu; + val->wake_up_y = wake_up_src.y_wu; + val->wake_up_z = wake_up_src.z_wu; + val->sleep_state = wake_up_src.sleep_state; + + val->tap_x = tap_src.x_tap; + val->tap_y = tap_src.y_tap; + val->tap_z = tap_src.z_tap; + val->tap_sign = tap_src.tap_sign; + val->double_tap = tap_src.double_tap; + val->single_tap = tap_src.single_tap; + + val->six_d_zl = d6d_src.zl; + val->six_d_zh = d6d_src.zh; + val->six_d_yl = d6d_src.yl; + val->six_d_yh = d6d_src.yh; + val->six_d_xl = d6d_src.xl; + val->six_d_xh = d6d_src.xh; + + val->step_detector = emb_func_status_mainpage.is_step_det; + val->tilt = emb_func_status_mainpage.is_tilt; + val->sig_mot = emb_func_status_mainpage.is_sigmot; + val->fsm_lc = emb_func_status_mainpage.is_fsm_lc; + + val->fsm1 = fsm_status_mainpage.is_fsm1; + val->fsm2 = fsm_status_mainpage.is_fsm2; + val->fsm3 = fsm_status_mainpage.is_fsm3; + val->fsm4 = fsm_status_mainpage.is_fsm4; + val->fsm5 = fsm_status_mainpage.is_fsm5; + val->fsm6 = fsm_status_mainpage.is_fsm6; + val->fsm7 = fsm_status_mainpage.is_fsm7; + val->fsm8 = fsm_status_mainpage.is_fsm8; + + val->mlc1 = mlc_status_mainpage.is_mlc1; + val->mlc2 = mlc_status_mainpage.is_mlc2; + val->mlc3 = mlc_status_mainpage.is_mlc3; + val->mlc4 = mlc_status_mainpage.is_mlc4; + } + + + if (ret == 0) + { + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, + 1); + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + val->emb_func_stand_by = emb_func_exec_status.emb_func_endop; + val->emb_func_time_exceed = emb_func_exec_status.emb_func_exec_ovr; + val->step_count_inc = emb_func_src.stepcounter_bit_set; + val->step_count_overflow = emb_func_src.step_overflow; + val->step_on_delta_time = emb_func_src.step_count_delta_ia; + + val->step_detector = emb_func_src.step_detected; + + return ret; +} + +int32_t ism330bx_flag_data_ready_get(const stmdev_ctx_t *ctx, + ism330bx_data_ready_t *val) +{ + ism330bx_status_reg_t status; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_STATUS_REG, (uint8_t *)&status, 1); + val->drdy_xl = status.xlda; + val->drdy_gy = status.gda; + val->drdy_temp = status.tda; + val->drdy_ah_qvar = status.ah_qvarda; + + return ret; +} + +/** + * @brief Temperature data output register[get] + * + * @param ctx read / write interface definitions + * @param val Temperature data output register + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_OUT_TEMP_L, &buff[0], 2); + *val = (int16_t)buff[1]; + *val = (*val * 256) + (int16_t)buff[0]; + + return ret; +} + +/** + * @brief Angular rate sensor.[get] + * + * @param ctx read / write interface definitions + * @param val Angular rate sensor. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_OUTX_L_G, &buff[0], 6); + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Linear acceleration sensor.[get] + * + * @param ctx read / write interface definitions + * @param val Linear acceleration sensor. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_OUTZ_L_A, &buff[0], 6); + val[2] = (int16_t)buff[1]; + val[2] = (val[2] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[0] = (int16_t)buff[5]; + val[0] = (val[0] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Linear acceleration sensor for Dual channel mode.[get] + * + * @param ctx read / write interface definitions + * @param val Linear acceleration sensor or Dual channel mode. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_UI_OUTZ_L_A_DUALC, &buff[0], 6); + val[2] = (int16_t)buff[1]; + val[2] = (val[2] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[0] = (int16_t)buff[5]; + val[0] = (val[0] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Qvar data output register.[get] + * + * @param ctx read / write interface definitions + * @param val Qvar data output register. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_ah_qvar_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_AH_QVAR_OUT_L, &buff[0], 2); + *val = (int16_t)buff[1]; + *val = (*val * 256) + (int16_t)buff[0]; + + return ret; +} + +/** + * @brief Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement.[get] + * + * @param ctx read / write interface definitions + * @param val Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val) +{ + ism330bx_internal_freq_t internal_freq; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_INTERNAL_FREQ, (uint8_t *)&internal_freq, 1); + *val = (int8_t)internal_freq.freq_fine; + + return ret; +} + +/** + * @brief Enable accelerometer axis.[set] + * + * @param ctx read / write interface definitions + * @param val Enable accelerometer axis. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tdm_xl_axis_set(const stmdev_ctx_t *ctx, ism330bx_tdm_xl_axis_t val) +{ + ism330bx_tdm_cfg1_t tdm_cfg1; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1); + if (ret == 0) + { + tdm_cfg1.tdm_xl_z_en = val.z; + tdm_cfg1.tdm_xl_y_en = val.y; + tdm_cfg1.tdm_xl_x_en = val.x; + ret = ism330bx_write_reg(ctx, ISM330BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1); + } + + return ret; +} + +/** + * @brief Enable accelerometer axis.[get] + * + * @param ctx read / write interface definitions + * @param val Enable accelerometer axis. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tdm_xl_axis_get(const stmdev_ctx_t *ctx, ism330bx_tdm_xl_axis_t *val) +{ + ism330bx_tdm_cfg1_t tdm_cfg1; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1); + val->x = tdm_cfg1.tdm_xl_x_en; + val->y = tdm_cfg1.tdm_xl_y_en; + val->z = tdm_cfg1.tdm_xl_z_en; + + return ret; +} + +/** + * @brief Write buffer in a page.[set] + * + * @param ctx read / write interface definitions + * @param val Write buffer in a page. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len) +{ + ism330bx_page_address_t page_address; + ism330bx_page_sel_t page_sel; + ism330bx_page_rw_t page_rw; + uint8_t msb; + uint8_t lsb; + int32_t ret; + uint8_t i ; + + msb = ((uint8_t)(address >> 8) & 0x0FU); + lsb = (uint8_t)address & 0xFFU; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + + /* set page write */ + ret += ism330bx_read_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_ENABLE; + ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); + + /* select page */ + ret += ism330bx_read_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, 1); + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + + /* set page addr */ + page_address.page_addr = lsb; + ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + + for (i = 0; ((i < len) && (ret == 0)); i++) + { + ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_VALUE, &buf[i], 1); + lsb++; + + /* Check if page wrap */ + if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) + { + msb++; + ret += ism330bx_read_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, 1); + + if (ret == 0) + { + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + } + } + } + + page_sel.page_sel = 0; + page_sel.not_used0 = 1;// Default value + ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + + /* unset page write */ + ret += ism330bx_read_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Read buffer in a page.[set] + * + * @param ctx read / write interface definitions + * @param val Write buffer in a page. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len) +{ + ism330bx_page_address_t page_address; + ism330bx_page_sel_t page_sel; + ism330bx_page_rw_t page_rw; + uint8_t msb; + uint8_t lsb; + int32_t ret; + uint8_t i ; + + msb = ((uint8_t)(address >> 8) & 0x0FU); + lsb = (uint8_t)address & 0xFFU; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + + /* set page write */ + ret += ism330bx_read_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_ENABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); + + /* select page */ + ret += ism330bx_read_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, 1); + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + + /* set page addr */ + page_address.page_addr = lsb; + ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + + for (i = 0; ((i < len) && (ret == 0)); i++) + { + ret += ism330bx_read_reg(ctx, ISM330BX_PAGE_VALUE, &buf[i], 1); + lsb++; + + /* Check if page wrap */ + if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) + { + msb++; + ret += ism330bx_read_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, 1); + + if (ret == 0) + { + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + } + } + } + + page_sel.page_sel = 0; + page_sel.not_used0 = 1;// Default value + ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + + /* unset page write */ + ret += ism330bx_read_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += ism330bx_write_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Timestamp + * @brief This section groups all the functions that manage the + * timestamp generation. + * @{ + * + */ + +/** + * @brief Enables timestamp counter.[set] + * + * @param ctx read / write interface definitions + * @param val Enables timestamp counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_functions_enable_t functions_enable; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret == 0) + { + functions_enable.timestamp_en = val; + ret = ism330bx_write_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + return ret; +} + +/** + * @brief Enables timestamp counter.[get] + * + * @param ctx read / write interface definitions + * @param val Enables timestamp counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_functions_enable_t functions_enable; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + *val = functions_enable.timestamp_en; + + return ret; +} + +/** + * @brief Timestamp data output.[get] + * + * @param ctx read / write interface definitions + * @param val Timestamp data output. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) +{ + uint8_t buff[4]; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TIMESTAMP0, &buff[0], 4); + *val = buff[3]; + *val = (*val * 256U) + buff[2]; + *val = (*val * 256U) + buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Filters + * @brief This section group all the functions concerning the + * filters configuration + * @{ + * + */ + +/** + * @brief Protocol anti-spike filters.[set] + * + * @param ctx read / write interface definitions + * @param val AUTO, ALWAYS_ACTIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_filt_anti_spike_set(const stmdev_ctx_t *ctx, + ism330bx_filt_anti_spike_t val) +{ + ism330bx_if_cfg_t if_cfg; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + + if (ret == 0) + { + if_cfg.asf_ctrl = (uint8_t)val & 0x01U; + ret = ism330bx_write_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Protocol anti-spike filters.[get] + * + * @param ctx read / write interface definitions + * @param val AUTO, ALWAYS_ACTIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_filt_anti_spike_get(const stmdev_ctx_t *ctx, + ism330bx_filt_anti_spike_t *val) +{ + ism330bx_if_cfg_t if_cfg; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + switch (if_cfg.asf_ctrl) + { + case ISM330BX_AUTO: + *val = ISM330BX_AUTO; + break; + + case ISM330BX_ALWAYS_ACTIVE: + *val = ISM330BX_ALWAYS_ACTIVE; + break; + + default: + *val = ISM330BX_AUTO; + break; + } + return ret; +} + +/** + * @brief It masks DRDY and Interrupts RQ until filter settling ends.[set] + * + * @param ctx read / write interface definitions + * @param val It masks DRDY and Interrupts RQ until filter settling ends. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_filt_settling_mask_set(const stmdev_ctx_t *ctx, + ism330bx_filt_settling_mask_t val) +{ + ism330bx_emb_func_cfg_t emb_func_cfg; + ism330bx_tdm_cfg2_t tdm_cfg2; + ism330bx_ctrl4_t ctrl4; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL4, (uint8_t *)&ctrl4, 1); + + if (ret == 0) + { + ctrl4.drdy_mask = val.drdy; + + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL4, (uint8_t *)&ctrl4, 1); + } + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + } + + if (ret == 0) + { + emb_func_cfg.emb_func_irq_mask_xl_settl = val.irq_xl; + emb_func_cfg.emb_func_irq_mask_g_settl = val.irq_g; + ret = ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + } + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1); + } + + if (ret == 0) + { + tdm_cfg2.tdm_data_mask = val.tdm_excep_code; + ret = ism330bx_write_reg(ctx, ISM330BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1); + } + + return ret; +} + +/** + * @brief It masks DRDY and Interrupts RQ until filter settling ends.[get] + * + * @param ctx read / write interface definitions + * @param val It masks DRDY and Interrupts RQ until filter settling ends. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_filt_settling_mask_get(const stmdev_ctx_t *ctx, + ism330bx_filt_settling_mask_t *val) +{ + ism330bx_emb_func_cfg_t emb_func_cfg; + ism330bx_tdm_cfg2_t tdm_cfg2; + ism330bx_ctrl4_t ctrl4; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1); + } + + val->drdy = ctrl4.drdy_mask; + val->irq_xl = emb_func_cfg.emb_func_irq_mask_xl_settl; + val->irq_g = emb_func_cfg.emb_func_irq_mask_g_settl; + val->tdm_excep_code = tdm_cfg2.tdm_data_mask; + + return ret; +} + +/** + * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[set] + * + * @param ctx read / write interface definitions + * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, + ism330bx_filt_gy_lp1_bandwidth_t val) +{ + ism330bx_ctrl6_t ctrl6; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL6, (uint8_t *)&ctrl6, 1); + if (ret == 0) + { + ctrl6.lpf1_g_bw = (uint8_t)val & 0x7U; + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL6, (uint8_t *)&ctrl6, 1); + } + + return ret; +} + +/** + * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[get] + * + * @param ctx read / write interface definitions + * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, + ism330bx_filt_gy_lp1_bandwidth_t *val) +{ + ism330bx_ctrl6_t ctrl6; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL6, (uint8_t *)&ctrl6, 1); + + switch (ctrl6.lpf1_g_bw) + { + case ISM330BX_GY_ULTRA_LIGHT: + *val = ISM330BX_GY_ULTRA_LIGHT; + break; + + case ISM330BX_GY_VERY_LIGHT: + *val = ISM330BX_GY_VERY_LIGHT; + break; + + case ISM330BX_GY_LIGHT: + *val = ISM330BX_GY_LIGHT; + break; + + case ISM330BX_GY_MEDIUM: + *val = ISM330BX_GY_MEDIUM; + break; + + case ISM330BX_GY_STRONG: + *val = ISM330BX_GY_STRONG; + break; + + case ISM330BX_GY_VERY_STRONG: + *val = ISM330BX_GY_VERY_STRONG; + break; + + case ISM330BX_GY_AGGRESSIVE: + *val = ISM330BX_GY_AGGRESSIVE; + break; + + case ISM330BX_GY_XTREME: + *val = ISM330BX_GY_XTREME; + break; + + default: + *val = ISM330BX_GY_ULTRA_LIGHT; + break; + } + return ret; +} + +/** + * @brief It enables gyroscope digital LPF1 filter.[set] + * + * @param ctx read / write interface definitions + * @param val It enables gyroscope digital LPF1 filter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_filt_gy_lp1_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_ctrl7_t ctrl7; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1); + + if (ret == 0) + { + ctrl7.lpf1_g_en = val; + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1); + } + + return ret; +} + +/** + * @brief It enables gyroscope digital LPF1 filter.[get] + * + * @param ctx read / write interface definitions + * @param val It enables gyroscope digital LPF1 filter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_ctrl7_t ctrl7; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1); + *val = ctrl7.lpf1_g_en; + + return ret; +} + +/** + * @brief Qvar filter configuration.[set] + * + * @param ctx read / write interface definitions + * @param val Qvar filter configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_filt_ah_qvar_conf_set(const stmdev_ctx_t *ctx, + ism330bx_filt_ah_qvar_conf_t val) +{ + ism330bx_ctrl9_t ctrl9; + ism330bx_ctrl8_t ctrl8; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + } + + ctrl8.ah_qvar_hpf = val.hpf; + ctrl9.ah_qvar_lpf = val.lpf; + + if (ret == 0) + { + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1); + } + if (ret == 0) + { + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Qvar filter configuration.[get] + * + * @param ctx read / write interface definitions + * @param val Qvar filter configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_filt_ah_qvar_conf_get(const stmdev_ctx_t *ctx, + ism330bx_filt_ah_qvar_conf_t *val) +{ + ism330bx_ctrl8_t ctrl8; + ism330bx_ctrl9_t ctrl9; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + } + + val->lpf = ctrl9.ah_qvar_lpf; + val->hpf = ctrl8.ah_qvar_hpf; + + return ret; +} + +/** + * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[set] + * + * @param ctx read / write interface definitions + * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, + ism330bx_filt_xl_lp2_bandwidth_t val) +{ + ism330bx_ctrl8_t ctrl8; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret == 0) + { + ctrl8.hp_lpf2_xl_bw = (uint8_t)val & 0x7U; + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1); + } + + return ret; +} + +/** + * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[get] + * + * @param ctx read / write interface definitions + * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, + ism330bx_filt_xl_lp2_bandwidth_t *val) +{ + ism330bx_ctrl8_t ctrl8; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL8, (uint8_t *)&ctrl8, 1); + switch (ctrl8.hp_lpf2_xl_bw) + { + case ISM330BX_XL_ULTRA_LIGHT: + *val = ISM330BX_XL_ULTRA_LIGHT; + break; + + case ISM330BX_XL_VERY_LIGHT: + *val = ISM330BX_XL_VERY_LIGHT; + break; + + case ISM330BX_XL_LIGHT: + *val = ISM330BX_XL_LIGHT; + break; + + case ISM330BX_XL_MEDIUM: + *val = ISM330BX_XL_MEDIUM; + break; + + case ISM330BX_XL_STRONG: + *val = ISM330BX_XL_STRONG; + break; + + case ISM330BX_XL_VERY_STRONG: + *val = ISM330BX_XL_VERY_STRONG; + break; + + case ISM330BX_XL_AGGRESSIVE: + *val = ISM330BX_XL_AGGRESSIVE; + break; + + case ISM330BX_XL_XTREME: + *val = ISM330BX_XL_XTREME; + break; + + default: + *val = ISM330BX_XL_ULTRA_LIGHT; + break; + } + return ret; +} + +/** + * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[set] + * + * @param ctx read / write interface definitions + * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_filt_xl_lp2_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_ctrl9_t ctrl9; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.lpf2_xl_en = val; + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[get] + * + * @param ctx read / write interface definitions + * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_ctrl9_t ctrl9; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.lpf2_xl_en; + + return ret; +} + +/** + * @brief Accelerometer slope filter / high-pass filter selection.[set] + * + * @param ctx read / write interface definitions + * @param val Accelerometer slope filter / high-pass filter selection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_filt_xl_hp_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_ctrl9_t ctrl9; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.hp_slope_xl_en = val; + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Accelerometer slope filter / high-pass filter selection.[get] + * + * @param ctx read / write interface definitions + * @param val Accelerometer slope filter / high-pass filter selection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_ctrl9_t ctrl9; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.hp_slope_xl_en; + + return ret; +} + +/** + * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[set] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_filt_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_ctrl9_t ctrl9; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.xl_fastsettl_mode = val; + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[get] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_ctrl9_t ctrl9; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.xl_fastsettl_mode; + + return ret; +} + +/** + * @brief Accelerometer high-pass filter mode.[set] + * + * @param ctx read / write interface definitions + * @param val HP_MD_NORMAL, HP_MD_REFERENCE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_filt_xl_hp_mode_set(const stmdev_ctx_t *ctx, + ism330bx_filt_xl_hp_mode_t val) +{ + ism330bx_ctrl9_t ctrl9; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.hp_ref_mode_xl = (uint8_t)val & 0x01U; + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Accelerometer high-pass filter mode.[get] + * + * @param ctx read / write interface definitions + * @param val HP_MD_NORMAL, HP_MD_REFERENCE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx, + ism330bx_filt_xl_hp_mode_t *val) +{ + ism330bx_ctrl9_t ctrl9; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + switch (ctrl9.hp_ref_mode_xl) + { + case ISM330BX_HP_MD_NORMAL: + *val = ISM330BX_HP_MD_NORMAL; + break; + + case ISM330BX_HP_MD_REFERENCE: + *val = ISM330BX_HP_MD_REFERENCE; + break; + + default: + *val = ISM330BX_HP_MD_NORMAL; + break; + } + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[set] + * + * @param ctx read / write interface definitions + * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx, + ism330bx_filt_wkup_act_feed_t val) +{ + ism330bx_wake_up_ths_t wake_up_ths; + ism330bx_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + tap_cfg0.slope_fds = (uint8_t)val & 0x01U; + wake_up_ths.usr_off_on_wu = ((uint8_t)val & 0x02U) >> 1; + + if (ret == 0) + { + + ret = ism330bx_write_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + if (ret == 0) + { + + ret = ism330bx_write_reg(ctx, ISM330BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[get] + * + * @param ctx read / write interface definitions + * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx, + ism330bx_filt_wkup_act_feed_t *val) +{ + ism330bx_wake_up_ths_t wake_up_ths; + ism330bx_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + switch ((wake_up_ths.usr_off_on_wu << 1) + tap_cfg0.slope_fds) + { + case ISM330BX_WK_FEED_SLOPE: + *val = ISM330BX_WK_FEED_SLOPE; + break; + + case ISM330BX_WK_FEED_HIGH_PASS: + *val = ISM330BX_WK_FEED_HIGH_PASS; + break; + + case ISM330BX_WK_FEED_LP_WITH_OFFSET: + *val = ISM330BX_WK_FEED_LP_WITH_OFFSET; + break; + + default: + *val = ISM330BX_WK_FEED_SLOPE; + break; + } + return ret; +} + +/** + * @brief Mask hw function triggers when xl is settling.[set] + * + * @param ctx read / write interface definitions + * @param val 0 or 1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_mask_trigger_xl_settl_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + + if (ret == 0) + { + tap_cfg0.hw_func_mask_xl_settl = val & 0x01U; + ret = ism330bx_write_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + return ret; +} + +/** + * @brief Mask hw function triggers when xl is settling.[get] + * + * @param ctx read / write interface definitions + * @param val 0 or 1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + *val = tap_cfg0.hw_func_mask_xl_settl; + + return ret; +} + + +/** + * @brief LPF2 filter on 6D (sixd) function selection.[set] + * + * @param ctx read / write interface definitions + * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_filt_sixd_feed_set(const stmdev_ctx_t *ctx, + ism330bx_filt_sixd_feed_t val) +{ + ism330bx_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret == 0) + { + tap_cfg0.low_pass_on_6d = (uint8_t)val & 0x01U; + ret = ism330bx_write_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + return ret; +} + +/** + * @brief LPF2 filter on 6D (sixd) function selection.[get] + * + * @param ctx read / write interface definitions + * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_filt_sixd_feed_get(const stmdev_ctx_t *ctx, + ism330bx_filt_sixd_feed_t *val) +{ + ism330bx_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + switch (tap_cfg0.low_pass_on_6d) + { + case ISM330BX_SIXD_FEED_ODR_DIV_2: + *val = ISM330BX_SIXD_FEED_ODR_DIV_2; + break; + + case ISM330BX_SIXD_FEED_LOW_PASS: + *val = ISM330BX_SIXD_FEED_LOW_PASS; + break; + + default: + *val = ISM330BX_SIXD_FEED_ODR_DIV_2; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Serial interfaces + * @brief This section groups all the functions concerning + * serial interfaces management (not auxiliary) + * @{ + * + */ + +/** + * @brief Enables pull-up on SDO pin of UI (User Interface).[set] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDO pin of UI (User Interface). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret == 0) + { + pin_ctrl.sdo_pu_en = val; + ret = ism330bx_write_reg(ctx, ISM330BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Enables pull-up on SDO pin of UI (User Interface).[get] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDO pin of UI (User Interface). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + *val = pin_ctrl.sdo_pu_en; + + return ret; +} + +/** + * @brief Disables I2C and I3C on UI (User Interface).[set] + * + * @param ctx read / write interface definitions + * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_ui_i2c_i3c_mode_set(const stmdev_ctx_t *ctx, + ism330bx_ui_i2c_i3c_mode_t val) +{ + ism330bx_if_cfg_t if_cfg; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.i2c_i3c_disable = (uint8_t)val & 0x01U; + ret = ism330bx_write_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Disables I2C and I3C on UI (User Interface).[get] + * + * @param ctx read / write interface definitions + * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx, + ism330bx_ui_i2c_i3c_mode_t *val) +{ + ism330bx_if_cfg_t if_cfg; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + switch (if_cfg.i2c_i3c_disable) + { + case ISM330BX_I2C_I3C_ENABLE: + *val = ISM330BX_I2C_I3C_ENABLE; + break; + + case ISM330BX_I2C_I3C_DISABLE: + *val = ISM330BX_I2C_I3C_DISABLE; + break; + + default: + *val = ISM330BX_I2C_I3C_ENABLE; + break; + } + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val SPI_4_WIRE, SPI_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_spi_mode_set(const stmdev_ctx_t *ctx, ism330bx_spi_mode_t val) +{ + ism330bx_if_cfg_t if_cfg; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.sim = (uint8_t)val & 0x01U; + ret = ism330bx_write_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val SPI_4_WIRE, SPI_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_spi_mode_get(const stmdev_ctx_t *ctx, ism330bx_spi_mode_t *val) +{ + ism330bx_if_cfg_t if_cfg; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + switch (if_cfg.sim) + { + case ISM330BX_SPI_4_WIRE: + *val = ISM330BX_SPI_4_WIRE; + break; + + case ISM330BX_SPI_3_WIRE: + *val = ISM330BX_SPI_3_WIRE; + break; + + default: + *val = ISM330BX_SPI_4_WIRE; + break; + } + return ret; +} + +/** + * @brief Enables pull-up on SDA pin.[set] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDA pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_ui_sda_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_if_cfg_t if_cfg; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.sda_pu_en = (uint8_t)val & 0x01U; + ret = ism330bx_write_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Enables pull-up on SDA pin.[get] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDA pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_if_cfg_t if_cfg; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + *val = if_cfg.sda_pu_en; + + return ret; +} + +/** + * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[set] + * + * @param ctx read / write interface definitions + * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_i3c_ibi_time_set(const stmdev_ctx_t *ctx, + ism330bx_i3c_ibi_time_t val) +{ + ism330bx_ctrl5_t ctrl5; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret == 0) + { + ctrl5.bus_act_sel = (uint8_t)val & 0x03U; + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL5, (uint8_t *)&ctrl5, 1); + } + + return ret; +} + +/** + * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[get] + * + * @param ctx read / write interface definitions + * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_i3c_ibi_time_get(const stmdev_ctx_t *ctx, + ism330bx_i3c_ibi_time_t *val) +{ + ism330bx_ctrl5_t ctrl5; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL5, (uint8_t *)&ctrl5, 1); + switch (ctrl5.bus_act_sel) + { + case ISM330BX_IBI_2us: + *val = ISM330BX_IBI_2us; + break; + + case ISM330BX_IBI_50us: + *val = ISM330BX_IBI_50us; + break; + + case ISM330BX_IBI_1ms: + *val = ISM330BX_IBI_1ms; + break; + + case ISM330BX_IBI_25ms: + *val = ISM330BX_IBI_25ms; + break; + + default: + *val = ISM330BX_IBI_2us; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Interrupt pins + * @brief This section groups all the functions that manage interrupt pins + * @{ + * + */ + +/** + * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[set] + * + * @param ctx read / write interface definitions + * @param val PUSH_PULL, OPEN_DRAIN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_int_pin_mode_set(const stmdev_ctx_t *ctx, + ism330bx_int_pin_mode_t val) +{ + ism330bx_if_cfg_t if_cfg; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.pp_od = (uint8_t)val & 0x01U; + ret = ism330bx_write_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[get] + * + * @param ctx read / write interface definitions + * @param val PUSH_PULL, OPEN_DRAIN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_int_pin_mode_get(const stmdev_ctx_t *ctx, + ism330bx_int_pin_mode_t *val) +{ + ism330bx_if_cfg_t if_cfg; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + switch (if_cfg.pp_od) + { + case ISM330BX_PUSH_PULL: + *val = ISM330BX_PUSH_PULL; + break; + + case ISM330BX_OPEN_DRAIN: + *val = ISM330BX_OPEN_DRAIN; + break; + + default: + *val = ISM330BX_PUSH_PULL; + break; + } + return ret; +} + +/** + * @brief Interrupt activation level.[set] + * + * @param ctx read / write interface definitions + * @param val ACTIVE_HIGH, ACTIVE_LOW, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_pin_polarity_set(const stmdev_ctx_t *ctx, + ism330bx_pin_polarity_t val) +{ + ism330bx_if_cfg_t if_cfg; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.h_lactive = (uint8_t)val & 0x01U; + ret = ism330bx_write_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Interrupt activation level.[get] + * + * @param ctx read / write interface definitions + * @param val ACTIVE_HIGH, ACTIVE_LOW, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_pin_polarity_get(const stmdev_ctx_t *ctx, + ism330bx_pin_polarity_t *val) +{ + ism330bx_if_cfg_t if_cfg; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + switch (if_cfg.h_lactive) + { + case ISM330BX_ACTIVE_HIGH: + *val = ISM330BX_ACTIVE_HIGH; + break; + + case ISM330BX_ACTIVE_LOW: + *val = ISM330BX_ACTIVE_LOW; + break; + + default: + *val = ISM330BX_ACTIVE_HIGH; + break; + } + return ret; +} + +/** + * @brief It routes interrupt signals on INT 1 pin.[set] + * + * @param ctx read / write interface definitions + * @param val It routes interrupt signals on INT 1 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_pin_int1_route_set(const stmdev_ctx_t *ctx, + ism330bx_pin_int_route_t val) +{ + ism330bx_functions_enable_t functions_enable; + ism330bx_pin_int_route_t pin_int2_route; + ism330bx_inactivity_dur_t inactivity_dur; + ism330bx_emb_func_int1_t emb_func_int1; + ism330bx_pedo_cmd_reg_t pedo_cmd_reg; + ism330bx_int2_ctrl_t int2_ctrl; + ism330bx_int1_ctrl_t int1_ctrl; + ism330bx_fsm_int1_t fsm_int1; + ism330bx_mlc_int1_t mlc_int1; + ism330bx_md1_cfg_t md1_cfg; + ism330bx_md2_cfg_t md2_cfg; + ism330bx_ctrl4_t ctrl4; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_FSM_INT1, (uint8_t *)&fsm_int1, 1); + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_MLC_INT1, (uint8_t *)&mlc_int1, 1); + } + + if (ret == 0) + { + emb_func_int1.int1_step_detector = val.step_detector; + emb_func_int1.int1_tilt = val.tilt; + emb_func_int1.int1_sig_mot = val.sig_mot; + emb_func_int1.int1_fsm_lc = val.fsm_lc; + ret = ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + } + if (ret == 0) + { + fsm_int1.int1_fsm1 = val.fsm1; + fsm_int1.int1_fsm2 = val.fsm2; + fsm_int1.int1_fsm3 = val.fsm3; + fsm_int1.int1_fsm4 = val.fsm4; + fsm_int1.int1_fsm5 = val.fsm5; + fsm_int1.int1_fsm6 = val.fsm6; + fsm_int1.int1_fsm7 = val.fsm7; + fsm_int1.int1_fsm8 = val.fsm8; + ret = ism330bx_write_reg(ctx, ISM330BX_FSM_INT1, (uint8_t *)&fsm_int1, 1); + } + if (ret == 0) + { + mlc_int1.int1_mlc1 = val.mlc1; + mlc_int1.int1_mlc2 = val.mlc2; + mlc_int1.int1_mlc3 = val.mlc3; + mlc_int1.int1_mlc4 = val.mlc4; + ret = ism330bx_write_reg(ctx, ISM330BX_MLC_INT1, (uint8_t *)&mlc_int1, 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL4, (uint8_t *)&ctrl4, 1); + } + if (ret == 0) + { + if ((val.emb_func_stand_by | val.timestamp) != PROPERTY_DISABLE) + { + ctrl4.int2_on_int1 = PROPERTY_ENABLE; + } + else + { + ctrl4.int2_on_int1 = PROPERTY_DISABLE; + } + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL4, (uint8_t *)&ctrl4, 1); + } + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + } + + if (ret == 0) + { + int2_ctrl.int2_emb_func_endop = val.emb_func_stand_by; + ret = ism330bx_write_reg(ctx, ISM330BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + } + + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + if (ret == 0) + { + md2_cfg.int2_timestamp = val.timestamp; + ret = ism330bx_write_reg(ctx, ISM330BX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + if (ret == 0) + { + inactivity_dur.sleep_status_on_int = val.sleep_status; + ret = ism330bx_write_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + } + + if (ret == 0) + { + int1_ctrl.int1_drdy_xl = val.drdy_xl; + int1_ctrl.int1_drdy_g = val.drdy_gy; + int1_ctrl.int1_fifo_th = val.fifo_th; + int1_ctrl.int1_fifo_ovr = val.fifo_ovr; + int1_ctrl.int1_fifo_full = val.fifo_full; + int1_ctrl.int1_cnt_bdr = val.fifo_bdr; + ret = ism330bx_write_reg(ctx, ISM330BX_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + } + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_MD1_CFG, (uint8_t *)&md1_cfg, 1); + } + + if (ret == 0) + { + if ((emb_func_int1.int1_fsm_lc + | emb_func_int1.int1_sig_mot + | emb_func_int1.int1_step_detector + | emb_func_int1.int1_tilt + | fsm_int1.int1_fsm1 + | fsm_int1.int1_fsm2 + | fsm_int1.int1_fsm3 + | fsm_int1.int1_fsm4 + | fsm_int1.int1_fsm5 + | fsm_int1.int1_fsm6 + | fsm_int1.int1_fsm7 + | fsm_int1.int1_fsm8 + | mlc_int1.int1_mlc1 + | mlc_int1.int1_mlc2 + | mlc_int1.int1_mlc3 + | mlc_int1.int1_mlc4) != PROPERTY_DISABLE) + { + md1_cfg.int1_emb_func = PROPERTY_ENABLE; + } + else + { + md1_cfg.int1_emb_func = PROPERTY_DISABLE; + } + md1_cfg.int1_6d = val.six_d; + md1_cfg.int1_double_tap = val.double_tap; + md1_cfg.int1_ff = val.free_fall; + md1_cfg.int1_wu = val.wake_up; + md1_cfg.int1_single_tap = val.single_tap; + if ((val.sleep_status | val.sleep_change) != PROPERTY_DISABLE) + { + md1_cfg.int1_sleep_change = PROPERTY_ENABLE; + } + else + { + md1_cfg.int1_sleep_change = PROPERTY_DISABLE; + } + ret = ism330bx_write_reg(ctx, ISM330BX_MD1_CFG, (uint8_t *)&md1_cfg, 1); + } + + if (ret == 0) + { + ret = ism330bx_ln_pg_read(ctx, ISM330BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + if (ret == 0) + { + pedo_cmd_reg.carry_count_en = val.step_count_overflow; + ret = ism330bx_ln_pg_write(ctx, ISM330BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + + if (ret == 0) + { + ret = ism330bx_pin_int2_route_get(ctx, &pin_int2_route); + } + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + if (ret == 0) + { + if ((pin_int2_route.six_d + | pin_int2_route.double_tap + | pin_int2_route.free_fall + | pin_int2_route.wake_up + | pin_int2_route.single_tap + | pin_int2_route.sleep_status + | pin_int2_route.sleep_change + | val.six_d + | val.double_tap + | val.free_fall + | val.wake_up + | val.single_tap + | val.sleep_status + | val.sleep_change) != PROPERTY_DISABLE) + { + functions_enable.interrupts_enable = PROPERTY_ENABLE; + } + + else + { + functions_enable.interrupts_enable = PROPERTY_DISABLE; + } + + ret = ism330bx_write_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + return ret; +} + +/** + * @brief It routes interrupt signals on INT 1 pin.[get] + * + * @param ctx read / write interface definitions + * @param val It routes interrupt signals on INT 1 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_pin_int1_route_get(const stmdev_ctx_t *ctx, + ism330bx_pin_int_route_t *val) +{ + ism330bx_inactivity_dur_t inactivity_dur; + ism330bx_emb_func_int1_t emb_func_int1; + ism330bx_pedo_cmd_reg_t pedo_cmd_reg; + ism330bx_int1_ctrl_t int1_ctrl; + ism330bx_int2_ctrl_t int2_ctrl; + ism330bx_fsm_int1_t fsm_int1; + ism330bx_mlc_int1_t mlc_int1; + ism330bx_md1_cfg_t md1_cfg; + ism330bx_md2_cfg_t md2_cfg; + ism330bx_ctrl4_t ctrl4; + int32_t ret; + + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL4, (uint8_t *)&ctrl4, 1); + if (ctrl4.int2_on_int1 == PROPERTY_ENABLE) + { + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop; + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + val->timestamp = md2_cfg.int2_timestamp; + } + } + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + val->sleep_status = inactivity_dur.sleep_status_on_int; + } + + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + val->drdy_xl = int1_ctrl.int1_drdy_xl; + val->drdy_gy = int1_ctrl.int1_drdy_g; + val->fifo_th = int1_ctrl.int1_fifo_th; + val->fifo_ovr = int1_ctrl.int1_fifo_ovr; + val->fifo_full = int1_ctrl.int1_fifo_full; + val->fifo_bdr = int1_ctrl.int1_cnt_bdr; + } + + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_MD1_CFG, (uint8_t *)&md1_cfg, 1); + val->six_d = md1_cfg.int1_6d; + val->double_tap = md1_cfg.int1_double_tap; + val->free_fall = md1_cfg.int1_ff; + val->wake_up = md1_cfg.int1_wu; + val->single_tap = md1_cfg.int1_single_tap; + val->sleep_change = md1_cfg.int1_sleep_change; + } + + if (ret == 0) + { + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + val->step_detector = emb_func_int1.int1_step_detector; + val->tilt = emb_func_int1.int1_tilt; + val->sig_mot = emb_func_int1.int1_sig_mot; + val->fsm_lc = emb_func_int1.int1_fsm_lc; + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_FSM_INT1, (uint8_t *)&fsm_int1, 1); + val->fsm1 = fsm_int1.int1_fsm1; + val->fsm2 = fsm_int1.int1_fsm2; + val->fsm3 = fsm_int1.int1_fsm3; + val->fsm4 = fsm_int1.int1_fsm4; + val->fsm5 = fsm_int1.int1_fsm5; + val->fsm6 = fsm_int1.int1_fsm6; + val->fsm7 = fsm_int1.int1_fsm7; + val->fsm8 = fsm_int1.int1_fsm8; + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_MLC_INT1, (uint8_t *)&mlc_int1, 1); + val->mlc1 = mlc_int1.int1_mlc1; + val->mlc2 = mlc_int1.int1_mlc2; + val->mlc3 = mlc_int1.int1_mlc3; + val->mlc4 = mlc_int1.int1_mlc4; + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = ism330bx_ln_pg_read(ctx, ISM330BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + val->step_count_overflow = pedo_cmd_reg.carry_count_en; + } + + return ret; +} + + +/** + * @brief It routes interrupt signals on INT 2 pin.[set] + * + * @param ctx read / write interface definitions + * @param val It routes interrupt signals on INT 2 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_pin_int2_route_set(const stmdev_ctx_t *ctx, + ism330bx_pin_int_route_t val) +{ + ism330bx_functions_enable_t functions_enable; + ism330bx_pin_int_route_t pin_int1_route; + ism330bx_inactivity_dur_t inactivity_dur; + ism330bx_emb_func_int2_t emb_func_int2; + ism330bx_pedo_cmd_reg_t pedo_cmd_reg; + ism330bx_int2_ctrl_t int2_ctrl; + ism330bx_fsm_int2_t fsm_int2; + ism330bx_mlc_int2_t mlc_int2; + ism330bx_ctrl7_t ctrl7; + ism330bx_md2_cfg_t md2_cfg; + ism330bx_ctrl4_t ctrl4; + int32_t ret; + + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_FSM_INT2, (uint8_t *)&fsm_int2, 1); + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_MLC_INT2, (uint8_t *)&mlc_int2, 1); + } + + if (ret == 0) + { + emb_func_int2.int2_step_detector = val.step_detector; + emb_func_int2.int2_tilt = val.tilt; + emb_func_int2.int2_sig_mot = val.sig_mot; + emb_func_int2.int2_fsm_lc = val.fsm_lc; + ret = ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + } + if (ret == 0) + { + fsm_int2.int2_fsm1 = val.fsm1; + fsm_int2.int2_fsm2 = val.fsm2; + fsm_int2.int2_fsm3 = val.fsm3; + fsm_int2.int2_fsm4 = val.fsm4; + fsm_int2.int2_fsm5 = val.fsm5; + fsm_int2.int2_fsm6 = val.fsm6; + fsm_int2.int2_fsm7 = val.fsm7; + fsm_int2.int2_fsm8 = val.fsm8; + ret = ism330bx_write_reg(ctx, ISM330BX_FSM_INT2, (uint8_t *)&fsm_int2, 1); + } + if (ret == 0) + { + mlc_int2.int2_mlc1 = val.mlc1; + mlc_int2.int2_mlc2 = val.mlc2; + mlc_int2.int2_mlc3 = val.mlc3; + mlc_int2.int2_mlc4 = val.mlc4; + ret = ism330bx_write_reg(ctx, ISM330BX_MLC_INT2, (uint8_t *)&mlc_int2, 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL4, (uint8_t *)&ctrl4, 1); + } + if (ret == 0) + { + if ((val.emb_func_stand_by | val.timestamp) != PROPERTY_DISABLE) + { + ctrl4.int2_on_int1 = PROPERTY_DISABLE; + } + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL4, (uint8_t *)&ctrl4, 1); + } + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + if (ret == 0) + { + inactivity_dur.sleep_status_on_int = val.sleep_status; + ret = ism330bx_write_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + } + + if (ret == 0) + { + int2_ctrl.int2_drdy_xl = val.drdy_xl; + int2_ctrl.int2_drdy_g = val.drdy_gy; + int2_ctrl.int2_fifo_th = val.fifo_th; + int2_ctrl.int2_fifo_ovr = val.fifo_ovr; + int2_ctrl.int2_fifo_full = val.fifo_full; + int2_ctrl.int2_cnt_bdr = val.fifo_bdr; + int2_ctrl.int2_emb_func_endop = val.emb_func_stand_by; + ret = ism330bx_write_reg(ctx, ISM330BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + } + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1); + ctrl7.int2_drdy_ah_qvar = val.drdy_ah_qvar; + ret += ism330bx_write_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1); + } + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + if (ret == 0) + { + if ((emb_func_int2.int2_fsm_lc + | emb_func_int2.int2_sig_mot + | emb_func_int2.int2_step_detector + | emb_func_int2.int2_tilt + | fsm_int2.int2_fsm1 + | fsm_int2.int2_fsm2 + | fsm_int2.int2_fsm3 + | fsm_int2.int2_fsm4 + | fsm_int2.int2_fsm5 + | fsm_int2.int2_fsm6 + | fsm_int2.int2_fsm7 + | fsm_int2.int2_fsm8 + | mlc_int2.int2_mlc1 + | mlc_int2.int2_mlc2 + | mlc_int2.int2_mlc3 + | mlc_int2.int2_mlc4) != PROPERTY_DISABLE) + { + md2_cfg.int2_emb_func = PROPERTY_ENABLE; + } + else + { + md2_cfg.int2_emb_func = PROPERTY_DISABLE; + } + md2_cfg.int2_6d = val.six_d; + md2_cfg.int2_double_tap = val.double_tap; + md2_cfg.int2_ff = val.free_fall; + md2_cfg.int2_wu = val.wake_up; + md2_cfg.int2_single_tap = val.single_tap; + md2_cfg.int2_timestamp = val.timestamp; + if ((val.sleep_status | val.sleep_change) != PROPERTY_DISABLE) + { + md2_cfg.int2_sleep_change = PROPERTY_ENABLE; + } + else + { + md2_cfg.int2_sleep_change = PROPERTY_DISABLE; + } + ret = ism330bx_write_reg(ctx, ISM330BX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + if (ret == 0) + { + ret = ism330bx_ln_pg_read(ctx, ISM330BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + if (ret == 0) + { + pedo_cmd_reg.carry_count_en = val.step_count_overflow; + ret = ism330bx_ln_pg_write(ctx, ISM330BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + + if (ret == 0) + { + ret = ism330bx_pin_int1_route_get(ctx, &pin_int1_route); + } + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + if (ret == 0) + { + if ((pin_int1_route.six_d + | pin_int1_route.double_tap + | pin_int1_route.free_fall + | pin_int1_route.wake_up + | pin_int1_route.single_tap + | pin_int1_route.sleep_status + | pin_int1_route.sleep_change + | val.six_d + | val.double_tap + | val.free_fall + | val.wake_up + | val.single_tap + | val.sleep_status + | val.sleep_change) != PROPERTY_DISABLE) + { + functions_enable.interrupts_enable = PROPERTY_ENABLE; + } + + else + { + functions_enable.interrupts_enable = PROPERTY_DISABLE; + } + + ret = ism330bx_write_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + return ret; +} + +/** + * @brief It routes interrupt signals on INT 2 pin.[get] + * + * @param ctx read / write interface definitions + * @param val It routes interrupt signals on INT 2 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_pin_int2_route_get(const stmdev_ctx_t *ctx, + ism330bx_pin_int_route_t *val) +{ + ism330bx_inactivity_dur_t inactivity_dur; + ism330bx_emb_func_int2_t emb_func_int2; + ism330bx_pedo_cmd_reg_t pedo_cmd_reg; + ism330bx_int2_ctrl_t int2_ctrl; + ism330bx_fsm_int2_t fsm_int2; + ism330bx_mlc_int2_t mlc_int2; + ism330bx_ctrl7_t ctrl7; + ism330bx_md2_cfg_t md2_cfg; + ism330bx_ctrl4_t ctrl4; + int32_t ret; + + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL4, (uint8_t *)&ctrl4, 1); + if (ctrl4.int2_on_int1 == PROPERTY_DISABLE) + { + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop; + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + val->timestamp = md2_cfg.int2_timestamp; + } + } + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + val->sleep_status = inactivity_dur.sleep_status_on_int; + } + + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + val->drdy_xl = int2_ctrl.int2_drdy_xl; + val->drdy_gy = int2_ctrl.int2_drdy_g; + val->fifo_th = int2_ctrl.int2_fifo_th; + val->fifo_ovr = int2_ctrl.int2_fifo_ovr; + val->fifo_full = int2_ctrl.int2_fifo_full; + val->fifo_bdr = int2_ctrl.int2_cnt_bdr; + } + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1); + val->drdy_ah_qvar = ctrl7.int2_drdy_ah_qvar; + } + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + val->six_d = md2_cfg.int2_6d; + val->double_tap = md2_cfg.int2_double_tap; + val->free_fall = md2_cfg.int2_ff; + val->wake_up = md2_cfg.int2_wu; + val->single_tap = md2_cfg.int2_single_tap; + val->sleep_change = md2_cfg.int2_sleep_change; + } + + if (ret == 0) + { + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + val->step_detector = emb_func_int2.int2_step_detector; + val->tilt = emb_func_int2.int2_tilt; + val->sig_mot = emb_func_int2.int2_sig_mot; + val->fsm_lc = emb_func_int2.int2_fsm_lc; + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_FSM_INT2, (uint8_t *)&fsm_int2, 1); + val->fsm1 = fsm_int2.int2_fsm1; + val->fsm2 = fsm_int2.int2_fsm2; + val->fsm3 = fsm_int2.int2_fsm3; + val->fsm4 = fsm_int2.int2_fsm4; + val->fsm5 = fsm_int2.int2_fsm5; + val->fsm6 = fsm_int2.int2_fsm6; + val->fsm7 = fsm_int2.int2_fsm7; + val->fsm8 = fsm_int2.int2_fsm8; + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_MLC_INT2, (uint8_t *)&mlc_int2, 1); + val->mlc1 = mlc_int2.int2_mlc1; + val->mlc2 = mlc_int2.int2_mlc2; + val->mlc3 = mlc_int2.int2_mlc3; + val->mlc4 = mlc_int2.int2_mlc4; + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = ism330bx_ln_pg_read(ctx, ISM330BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + val->step_count_overflow = pedo_cmd_reg.carry_count_en; + } + + return ret; +} + +/** + * @brief Enables INT pin when I3C is enabled.[set] + * + * @param ctx read / write interface definitions + * @param val Enables INT pin when I3C is enabled. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_pin_int_en_when_i2c_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_ctrl5_t ctrl5; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret == 0) + { + ctrl5.int_en_i3c = val; + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL5, (uint8_t *)&ctrl5, 1); + } + + return ret; +} + +/** + * @brief Enables INT pin when I3C is enabled.[get] + * + * @param ctx read / write interface definitions + * @param val Enables INT pin when I3C is enabled. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_pin_int_en_when_i2c_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_ctrl5_t ctrl5; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL5, (uint8_t *)&ctrl5, 1); + *val = ctrl5.int_en_i3c; + + return ret; +} + +/** + * @brief Interrupt notification mode.[set] + * + * @param ctx read / write interface definitions + * @param val ALL_INT_PULSED, BASE_LATCHED_EMB_PULSED, BASE_PULSED_EMB_LATCHED, ALL_INT_LATCHED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_int_notification_set(const stmdev_ctx_t *ctx, + ism330bx_int_notification_t val) +{ + ism330bx_tap_cfg0_t tap_cfg0; + ism330bx_page_rw_t page_rw; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret == 0) + { + tap_cfg0.lir = (uint8_t)val & 0x01U; + ret = ism330bx_write_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + if (ret == 0) + { + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + if (ret == 0) + { + page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; + ret = ism330bx_write_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Interrupt notification mode.[get] + * + * @param ctx read / write interface definitions + * @param val ALL_INT_PULSED, BASE_LATCHED_EMB_PULSED, BASE_PULSED_EMB_LATCHED, ALL_INT_LATCHED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_int_notification_get(const stmdev_ctx_t *ctx, + ism330bx_int_notification_t *val) +{ + ism330bx_tap_cfg0_t tap_cfg0; + ism330bx_page_rw_t page_rw; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret == 0) + { + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir) + { + case ISM330BX_ALL_INT_PULSED: + *val = ISM330BX_ALL_INT_PULSED; + break; + + case ISM330BX_BASE_LATCHED_EMB_PULSED: + *val = ISM330BX_BASE_LATCHED_EMB_PULSED; + break; + + case ISM330BX_BASE_PULSED_EMB_LATCHED: + *val = ISM330BX_BASE_PULSED_EMB_LATCHED; + break; + + case ISM330BX_ALL_INT_LATCHED: + *val = ISM330BX_ALL_INT_LATCHED; + break; + + default: + *val = ISM330BX_ALL_INT_PULSED; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Wake Up event and Activity / Inactivity detection + * @brief This section groups all the functions that manage the Wake Up + * event generation. + * @{ + * + */ + +/** + * @brief Enable activity/inactivity (sleep) function.[set] + * + * @param ctx read / write interface definitions + * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_act_mode_set(const stmdev_ctx_t *ctx, ism330bx_act_mode_t val) +{ + ism330bx_functions_enable_t functions_enable; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret == 0) + { + functions_enable.inact_en = (uint8_t)val & 0x03U; + ret = ism330bx_write_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + return ret; +} + +/** + * @brief Enable activity/inactivity (sleep) function.[get] + * + * @param ctx read / write interface definitions + * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_act_mode_get(const stmdev_ctx_t *ctx, ism330bx_act_mode_t *val) +{ + ism330bx_functions_enable_t functions_enable; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + switch (functions_enable.inact_en) + { + case ISM330BX_XL_AND_GY_NOT_AFFECTED: + *val = ISM330BX_XL_AND_GY_NOT_AFFECTED; + break; + + case ISM330BX_XL_LOW_POWER_GY_NOT_AFFECTED: + *val = ISM330BX_XL_LOW_POWER_GY_NOT_AFFECTED; + break; + + case ISM330BX_XL_LOW_POWER_GY_SLEEP: + *val = ISM330BX_XL_LOW_POWER_GY_SLEEP; + break; + + case ISM330BX_XL_LOW_POWER_GY_POWER_DOWN: + *val = ISM330BX_XL_LOW_POWER_GY_POWER_DOWN; + break; + + default: + *val = ISM330BX_XL_AND_GY_NOT_AFFECTED; + break; + } + return ret; +} + +/** + * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[set] + * + * @param ctx read / write interface definitions + * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_act_from_sleep_to_act_dur_set(const stmdev_ctx_t *ctx, + ism330bx_act_from_sleep_to_act_dur_t val) +{ + ism330bx_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret == 0) + { + inactivity_dur.inact_dur = (uint8_t)val & 0x3U; + ret = ism330bx_write_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + return ret; +} + +/** + * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[get] + * + * @param ctx read / write interface definitions + * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx, + ism330bx_act_from_sleep_to_act_dur_t *val) +{ + ism330bx_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + switch (inactivity_dur.inact_dur) + { + case ISM330BX_SLEEP_TO_ACT_AT_1ST_SAMPLE: + *val = ISM330BX_SLEEP_TO_ACT_AT_1ST_SAMPLE; + break; + + case ISM330BX_SLEEP_TO_ACT_AT_2ND_SAMPLE: + *val = ISM330BX_SLEEP_TO_ACT_AT_2ND_SAMPLE; + break; + + case ISM330BX_SLEEP_TO_ACT_AT_3RD_SAMPLE: + *val = ISM330BX_SLEEP_TO_ACT_AT_3RD_SAMPLE; + break; + + case ISM330BX_SLEEP_TO_ACT_AT_4th_SAMPLE: + *val = ISM330BX_SLEEP_TO_ACT_AT_4th_SAMPLE; + break; + + default: + *val = ISM330BX_SLEEP_TO_ACT_AT_1ST_SAMPLE; + break; + } + return ret; +} + +/** + * @brief Selects the accelerometer data rate during Inactivity.[set] + * + * @param ctx read / write interface definitions + * @param val 1Hz875, 15Hz, 30Hz, 60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_act_sleep_xl_odr_set(const stmdev_ctx_t *ctx, + ism330bx_act_sleep_xl_odr_t val) +{ + ism330bx_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret == 0) + { + inactivity_dur.xl_inact_odr = (uint8_t)val & 0x03U; + ret = ism330bx_write_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + return ret; +} + +/** + * @brief Selects the accelerometer data rate during Inactivity.[get] + * + * @param ctx read / write interface definitions + * @param val 1Hz875, 15Hz, 30Hz, 60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx, + ism330bx_act_sleep_xl_odr_t *val) +{ + ism330bx_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + switch (inactivity_dur.xl_inact_odr) + { + case ISM330BX_1Hz875: + *val = ISM330BX_1Hz875; + break; + + case ISM330BX_15Hz: + *val = ISM330BX_15Hz; + break; + + case ISM330BX_30Hz: + *val = ISM330BX_30Hz; + break; + + case ISM330BX_60Hz: + *val = ISM330BX_60Hz; + break; + + default: + *val = ISM330BX_1Hz875; + break; + } + return ret; +} + +/** + * @brief Wakeup and activity/inactivity threshold.[set] + * + * @param ctx read / write interface definitions + * @param val Wakeup and activity/inactivity threshold. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_act_thresholds_set(const stmdev_ctx_t *ctx, + ism330bx_act_thresholds_t val) +{ + ism330bx_inactivity_ths_t inactivity_ths; + ism330bx_inactivity_dur_t inactivity_dur; + ism330bx_wake_up_ths_t wake_up_ths; + int32_t ret; + float_t tmp; + + ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + } + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + if ((val.wk_ths_mg < (uint32_t)(7.8125f * 63.0f)) + && (val.inact_ths_mg < (uint32_t)(7.8125f * 63.0f))) + { + inactivity_dur.wu_inact_ths_w = 0; + + tmp = (float_t)val.inact_ths_mg / 7.8125f; + inactivity_ths.inact_ths = (uint8_t)tmp; + + tmp = (float_t)val.wk_ths_mg / 7.8125f; + wake_up_ths.wk_ths = (uint8_t)tmp; + } + else if ((val.wk_ths_mg < (uint32_t)(15.625f * 63.0f)) + && (val.inact_ths_mg < (uint32_t)(15.625f * 63.0f))) + { + inactivity_dur.wu_inact_ths_w = 1; + + tmp = (float_t)val.inact_ths_mg / 15.625f; + inactivity_ths.inact_ths = (uint8_t)tmp; + + tmp = (float_t)val.wk_ths_mg / 15.625f; + wake_up_ths.wk_ths = (uint8_t)tmp; + } + else if ((val.wk_ths_mg < (uint32_t)(31.25f * 63.0f)) + && (val.inact_ths_mg < (uint32_t)(31.25f * 63.0f))) + { + inactivity_dur.wu_inact_ths_w = 2; + + tmp = (float_t)val.inact_ths_mg / 31.25f; + inactivity_ths.inact_ths = (uint8_t)tmp; + + tmp = (float_t)val.wk_ths_mg / 31.25f; + wake_up_ths.wk_ths = (uint8_t)tmp; + } + else if ((val.wk_ths_mg < (uint32_t)(62.5f * 63.0f)) + && (val.inact_ths_mg < (uint32_t)(62.5f * 63.0f))) + { + inactivity_dur.wu_inact_ths_w = 3; + + tmp = (float_t)val.inact_ths_mg / 62.5f; + inactivity_ths.inact_ths = (uint8_t)tmp; + + tmp = (float_t)val.wk_ths_mg / 62.5f; + wake_up_ths.wk_ths = (uint8_t)tmp; + } + else if ((val.wk_ths_mg < (uint32_t)(125.0f * 63.0f)) + && (val.inact_ths_mg < (uint32_t)(125.0f * 63.0f))) + { + inactivity_dur.wu_inact_ths_w = 4; + + tmp = (float_t)val.inact_ths_mg / 125.0f; + inactivity_ths.inact_ths = (uint8_t)tmp; + + tmp = (float_t)val.wk_ths_mg / 125.0f; + wake_up_ths.wk_ths = (uint8_t)tmp; + } + else if ((val.wk_ths_mg < (uint32_t)(250.0f * 63.0f)) + && (val.inact_ths_mg < (uint32_t)(250.0f * 63.0f))) + { + inactivity_dur.wu_inact_ths_w = 5; + + tmp = (float_t)val.inact_ths_mg / 250.0f; + inactivity_ths.inact_ths = (uint8_t)tmp; + + tmp = (float_t)val.wk_ths_mg / 250.0f; + wake_up_ths.wk_ths = (uint8_t)tmp; + } + else // out of limit + { + inactivity_dur.wu_inact_ths_w = 5; + inactivity_ths.inact_ths = 0x3FU; + wake_up_ths.wk_ths = 0x3FU; + } + + if (ret == 0) + { + ret = ism330bx_write_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + if (ret == 0) + { + + ret = ism330bx_write_reg(ctx, ISM330BX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + } + if (ret == 0) + { + + ret = ism330bx_write_reg(ctx, ISM330BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + return ret; +} + +/** + * @brief Wakeup and activity/inactivity threshold.[get] + * + * @param ctx read / write interface definitions + * @param val Wakeup and activity/inactivity threshold. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_act_thresholds_get(const stmdev_ctx_t *ctx, + ism330bx_act_thresholds_t *val) +{ + ism330bx_inactivity_dur_t inactivity_dur; + ism330bx_inactivity_ths_t inactivity_ths; + ism330bx_wake_up_ths_t wake_up_ths; + int32_t ret; + float_t tmp; + + ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + switch (inactivity_dur.wu_inact_ths_w) + { + case 0: + tmp = (float_t)wake_up_ths.wk_ths * 7.8125f; + val->wk_ths_mg = (uint32_t)tmp; + + tmp = (float_t)inactivity_ths.inact_ths * 7.8125f; + val->inact_ths_mg = (uint32_t)tmp; + break; + + case 1: + tmp = (float_t)wake_up_ths.wk_ths * 15.625f; + val->wk_ths_mg = (uint32_t)tmp; + + tmp = (float_t)inactivity_ths.inact_ths * 15.625f; + val->inact_ths_mg = (uint32_t)tmp; + break; + + case 2: + tmp = (float_t)wake_up_ths.wk_ths * 31.25f; + val->wk_ths_mg = (uint32_t)tmp; + + tmp = (float_t)inactivity_ths.inact_ths * 31.25f; + val->inact_ths_mg = (uint32_t)tmp; + break; + + case 3: + tmp = (float_t)wake_up_ths.wk_ths * 62.5f; + val->wk_ths_mg = (uint32_t)tmp; + + tmp = (float_t)inactivity_ths.inact_ths * 62.5f; + val->inact_ths_mg = (uint32_t)tmp; + break; + + case 4: + tmp = (float_t)wake_up_ths.wk_ths * 125.0f; + val->wk_ths_mg = (uint32_t)tmp; + + tmp = (float_t)inactivity_ths.inact_ths * 125.0f; + val->inact_ths_mg = (uint32_t)tmp; + break; + + default: + tmp = (float_t)wake_up_ths.wk_ths * 250.0f; + val->wk_ths_mg = (uint32_t)tmp; + + tmp = (float_t)inactivity_ths.inact_ths * 250.0f; + val->inact_ths_mg = (uint32_t)tmp; + break; + } + + return ret; +} + +/** + * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [set] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_act_wkup_time_windows_set(const stmdev_ctx_t *ctx, + ism330bx_act_wkup_time_windows_t val) +{ + ism330bx_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + wake_up_dur.wake_dur = val.shock; + wake_up_dur.sleep_dur = val.quiet; + ret = ism330bx_write_reg(ctx, ISM330BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + } + + return ret; +} + +/** + * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [get] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, + ism330bx_act_wkup_time_windows_t *val) +{ + ism330bx_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + val->shock = wake_up_dur.wake_dur; + val->quiet = wake_up_dur.sleep_dur; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Tap Generator + * @brief This section groups all the functions that manage the + * tap and double tap event generation. + * @{ + * + */ + +/** + * @brief Enable axis for Tap - Double Tap detection.[set] + * + * @param ctx read / write interface definitions + * @param val Enable axis for Tap - Double Tap detection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tap_detection_set(const stmdev_ctx_t *ctx, + ism330bx_tap_detection_t val) +{ + ism330bx_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret == 0) + { + tap_cfg0.tap_x_en = val.tap_x_en; + tap_cfg0.tap_y_en = val.tap_y_en; + tap_cfg0.tap_z_en = val.tap_z_en; + ret = ism330bx_write_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + return ret; +} + +/** + * @brief Enable axis for Tap - Double Tap detection.[get] + * + * @param ctx read / write interface definitions + * @param val Enable axis for Tap - Double Tap detection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tap_detection_get(const stmdev_ctx_t *ctx, + ism330bx_tap_detection_t *val) +{ + ism330bx_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + val->tap_x_en = tap_cfg0.tap_x_en; + val->tap_y_en = tap_cfg0.tap_y_en; + val->tap_z_en = tap_cfg0.tap_z_en; + + return ret; +} + +/** + * @brief axis Tap - Double Tap recognition thresholds.[set] + * + * @param ctx read / write interface definitions + * @param val axis Tap - Double Tap recognition thresholds. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tap_thresholds_set(const stmdev_ctx_t *ctx, + ism330bx_tap_thresholds_t val) +{ + ism330bx_tap_ths_6d_t tap_ths_6d; + ism330bx_tap_cfg2_t tap_cfg2; + ism330bx_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + + tap_cfg1.tap_ths_z = val.z; + tap_cfg2.tap_ths_y = val.y; + tap_ths_6d.tap_ths_x = val.x; + + if (ret == 0) + { + ret = ism330bx_write_reg(ctx, ISM330BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + if (ret == 0) + { + ret = ism330bx_write_reg(ctx, ISM330BX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + } + if (ret == 0) + { + ret = ism330bx_write_reg(ctx, ISM330BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + } + + return ret; +} + +/** + * @brief axis Tap - Double Tap recognition thresholds.[get] + * + * @param ctx read / write interface definitions + * @param val axis Tap - Double Tap recognition thresholds. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tap_thresholds_get(const stmdev_ctx_t *ctx, + ism330bx_tap_thresholds_t *val) +{ + ism330bx_tap_ths_6d_t tap_ths_6d; + ism330bx_tap_cfg2_t tap_cfg2; + ism330bx_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + + val->z = tap_cfg1.tap_ths_z; + val->y = tap_cfg2.tap_ths_y; + val->x = tap_ths_6d.tap_ths_x; + + return ret; +} + +/** + * @brief Selection of axis priority for TAP detection.[set] + * + * @param ctx read / write interface definitions + * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY , + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tap_axis_priority_set(const stmdev_ctx_t *ctx, + ism330bx_tap_axis_priority_t val) +{ + ism330bx_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret == 0) + { + tap_cfg1.tap_priority = (uint8_t)val & 0x07U; + ret = ism330bx_write_reg(ctx, ISM330BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + } + + return ret; +} + +/** + * @brief Selection of axis priority for TAP detection.[get] + * + * @param ctx read / write interface definitions + * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY , + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tap_axis_priority_get(const stmdev_ctx_t *ctx, + ism330bx_tap_axis_priority_t *val) +{ + ism330bx_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + switch (tap_cfg1.tap_priority) + { + case ISM330BX_XYZ : + *val = ISM330BX_XYZ ; + break; + + case ISM330BX_YXZ : + *val = ISM330BX_YXZ ; + break; + + case ISM330BX_XZY: + *val = ISM330BX_XZY; + break; + + case ISM330BX_ZYX : + *val = ISM330BX_ZYX ; + break; + + case ISM330BX_YZX : + *val = ISM330BX_YZX ; + break; + + case ISM330BX_ZXY : + *val = ISM330BX_ZXY ; + break; + + default: + *val = ISM330BX_XYZ ; + break; + } + return ret; +} + + +/** + * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[set] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tap_time_windows_set(const stmdev_ctx_t *ctx, + ism330bx_tap_time_windows_t val) +{ + ism330bx_tap_dur_t tap_dur; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TAP_DUR, (uint8_t *)&tap_dur, 1); + if (ret == 0) + { + tap_dur.shock = val.shock; + tap_dur.quiet = val.quiet; + tap_dur.dur = val.tap_gap; + ret = ism330bx_write_reg(ctx, ISM330BX_TAP_DUR, (uint8_t *)&tap_dur, 1); + } + + return ret; +} + +/** + * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[get] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tap_time_windows_get(const stmdev_ctx_t *ctx, + ism330bx_tap_time_windows_t *val) +{ + ism330bx_tap_dur_t tap_dur; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TAP_DUR, (uint8_t *)&tap_dur, 1); + val->shock = tap_dur.shock; + val->quiet = tap_dur.quiet; + val->tap_gap = tap_dur.dur; + + return ret; +} + +/** + * @brief Single/double-tap event enable.[set] + * + * @param ctx read / write interface definitions + * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tap_mode_set(const stmdev_ctx_t *ctx, ism330bx_tap_mode_t val) +{ + ism330bx_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret == 0) + { + wake_up_ths.single_double_tap = (uint8_t)val & 0x01U; + ret = ism330bx_write_reg(ctx, ISM330BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + return ret; +} + +/** + * @brief Single/double-tap event enable.[get] + * + * @param ctx read / write interface definitions + * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tap_mode_get(const stmdev_ctx_t *ctx, ism330bx_tap_mode_t *val) +{ + ism330bx_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + switch (wake_up_ths.single_double_tap) + { + case ISM330BX_ONLY_SINGLE: + *val = ISM330BX_ONLY_SINGLE; + break; + + case ISM330BX_BOTH_SINGLE_DOUBLE: + *val = ISM330BX_BOTH_SINGLE_DOUBLE; + break; + + default: + *val = ISM330BX_ONLY_SINGLE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Six position detection (6D) + * @brief This section groups all the functions concerning six position + * detection (6D). + * @{ + * + */ + +/** + * @brief Threshold for 4D/6D function.[set] + * + * @param ctx read / write interface definitions + * @param val DEG_80, DEG_70, DEG_60, DEG_50, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_6d_threshold_set(const stmdev_ctx_t *ctx, + ism330bx_6d_threshold_t val) +{ + ism330bx_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret == 0) + { + tap_ths_6d.sixd_ths = (uint8_t)val & 0x03U; + ret = ism330bx_write_reg(ctx, ISM330BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + + return ret; +} + +/** + * @brief Threshold for 4D/6D function.[get] + * + * @param ctx read / write interface definitions + * @param val DEG_80, DEG_70, DEG_60, DEG_50, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_6d_threshold_get(const stmdev_ctx_t *ctx, + ism330bx_6d_threshold_t *val) +{ + ism330bx_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + switch (tap_ths_6d.sixd_ths) + { + case ISM330BX_DEG_80: + *val = ISM330BX_DEG_80; + break; + + case ISM330BX_DEG_70: + *val = ISM330BX_DEG_70; + break; + + case ISM330BX_DEG_60: + *val = ISM330BX_DEG_60; + break; + + case ISM330BX_DEG_50: + *val = ISM330BX_DEG_50; + break; + + default: + *val = ISM330BX_DEG_80; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Free fall + * @brief This section group all the functions concerning the free + * fall detection. + * @{ + * + */ + +/** + * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[set] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_wake_up_dur_t wake_up_dur; + ism330bx_free_fall_t free_fall; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5; + ret = ism330bx_write_reg(ctx, ISM330BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + if (ret == 0) + { + free_fall.ff_dur = (uint8_t)val & 0x1FU; + ret = ism330bx_write_reg(ctx, ISM330BX_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + return ret; +} + +/** + * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[get] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_wake_up_dur_t wake_up_dur; + ism330bx_free_fall_t free_fall; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; + + return ret; +} + +/** + * @brief Free fall threshold setting.[set] + * + * @param ctx read / write interface definitions + * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_ff_thresholds_set(const stmdev_ctx_t *ctx, + ism330bx_ff_thresholds_t val) +{ + ism330bx_free_fall_t free_fall; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret == 0) + { + free_fall.ff_ths = (uint8_t)val & 0x7U; + ret = ism330bx_write_reg(ctx, ISM330BX_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + return ret; +} + +/** + * @brief Free fall threshold setting.[get] + * + * @param ctx read / write interface definitions + * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_ff_thresholds_get(const stmdev_ctx_t *ctx, + ism330bx_ff_thresholds_t *val) +{ + ism330bx_free_fall_t free_fall; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FREE_FALL, (uint8_t *)&free_fall, 1); + + switch (free_fall.ff_ths) + { + case ISM330BX_156_mg: + *val = ISM330BX_156_mg; + break; + + case ISM330BX_219_mg: + *val = ISM330BX_219_mg; + break; + + case ISM330BX_250_mg: + *val = ISM330BX_250_mg; + break; + + case ISM330BX_312_mg: + *val = ISM330BX_312_mg; + break; + + case ISM330BX_344_mg: + *val = ISM330BX_344_mg; + break; + + case ISM330BX_406_mg: + *val = ISM330BX_406_mg; + break; + + case ISM330BX_469_mg: + *val = ISM330BX_469_mg; + break; + + case ISM330BX_500_mg: + *val = ISM330BX_500_mg; + break; + + default: + *val = ISM330BX_156_mg; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup FIFO + * @brief This section group all the functions concerning the fifo usage + * @{ + * + */ + +/** + * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[set] + * + * @param ctx read / write interface definitions + * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_fifo_ctrl1_t fifo_ctrl1; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + + if (ret == 0) + { + fifo_ctrl1.wtm = val; + ret = ism330bx_write_reg(ctx, ISM330BX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + } + + return ret; +} + +/** + * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[get] + * + * @param ctx read / write interface definitions + * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_fifo_ctrl1_t fifo_ctrl1; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + *val = fifo_ctrl1.wtm; + + return ret; +} + +/** + * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[set] + * + * @param ctx read / write interface definitions + * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.xl_dualc_batch_from_fsm = val; + ret = ism330bx_write_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[get] + * + * @param ctx read / write interface definitions + * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.xl_dualc_batch_from_fsm; + + return ret; +} + +/** + * @brief It configures the compression algorithm to write non-compressed data at each rate.[set] + * + * @param ctx read / write interface definitions + * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_compress_algo_set(const stmdev_ctx_t *ctx, + ism330bx_fifo_compress_algo_t val) +{ + ism330bx_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.uncompr_rate = (uint8_t)val & 0x03U; + ret = ism330bx_write_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief It configures the compression algorithm to write non-compressed data at each rate.[get] + * + * @param ctx read / write interface definitions + * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_compress_algo_get(const stmdev_ctx_t *ctx, + ism330bx_fifo_compress_algo_t *val) +{ + ism330bx_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + + switch (fifo_ctrl2.uncompr_rate) + { + case ISM330BX_CMP_DISABLE: + *val = ISM330BX_CMP_DISABLE; + break; + + case ISM330BX_CMP_8_TO_1: + *val = ISM330BX_CMP_8_TO_1; + break; + + case ISM330BX_CMP_16_TO_1: + *val = ISM330BX_CMP_16_TO_1; + break; + + case ISM330BX_CMP_32_TO_1: + *val = ISM330BX_CMP_32_TO_1; + break; + + default: + *val = ISM330BX_CMP_DISABLE; + break; + } + return ret; +} + +/** + * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set] + * + * @param ctx read / write interface definitions + * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, + uint8_t val) +{ + ism330bx_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.odr_chg_en = val; + ret = ism330bx_write_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get] + * + * @param ctx read / write interface definitions + * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, + uint8_t *val) +{ + ism330bx_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.odr_chg_en; + + return ret; +} + +/** + * @brief Enables/Disables compression algorithm runtime.[set] + * + * @param ctx read / write interface definitions + * @param val Enables/Disables compression algorithm runtime. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, + uint8_t val) +{ + ism330bx_emb_func_en_b_t emb_func_en_b; + ism330bx_fifo_ctrl2_t fifo_ctrl2; + + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.fifo_compr_rt_en = val; + ret = ism330bx_write_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + if (ret == 0) + { + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + emb_func_en_b.fifo_compr_en = val; + ret = ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables/Disables compression algorithm runtime.[get] + * + * @param ctx read / write interface definitions + * @param val Enables/Disables compression algorithm runtime. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, + uint8_t *val) +{ + ism330bx_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + + *val = fifo_ctrl2.fifo_compr_rt_en; + + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at threshold level.[set] + * + * @param ctx read / write interface definitions + * @param val Sensing chain FIFO stop values memorization at threshold level. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.stop_on_wtm = val; + ret = ism330bx_write_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at threshold level.[get] + * + * @param ctx read / write interface definitions + * @param val Sensing chain FIFO stop values memorization at threshold level. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.stop_on_wtm; + + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[set] + * + * @param ctx read / write interface definitions + * @param val ism330bx_fifo_xl_batch_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_xl_batch_set(const stmdev_ctx_t *ctx, + ism330bx_fifo_xl_batch_t val) +{ + ism330bx_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret == 0) + { + fifo_ctrl3.bdr_xl = (uint8_t)val & 0xFU; + ret = ism330bx_write_reg(ctx, ISM330BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + } + + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[get] + * + * @param ctx read / write interface definitions + * @param val ism330bx_fifo_xl_batch_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_xl_batch_get(const stmdev_ctx_t *ctx, + ism330bx_fifo_xl_batch_t *val) +{ + ism330bx_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + switch (fifo_ctrl3.bdr_xl) + { + case ISM330BX_XL_NOT_BATCHED: + *val = ISM330BX_XL_NOT_BATCHED; + break; + + case ISM330BX_XL_BATCHED_AT_1Hz875: + *val = ISM330BX_XL_BATCHED_AT_1Hz875; + break; + + case ISM330BX_XL_BATCHED_AT_7Hz5: + *val = ISM330BX_XL_BATCHED_AT_7Hz5; + break; + + case ISM330BX_XL_BATCHED_AT_15Hz: + *val = ISM330BX_XL_BATCHED_AT_15Hz; + break; + + case ISM330BX_XL_BATCHED_AT_30Hz: + *val = ISM330BX_XL_BATCHED_AT_30Hz; + break; + + case ISM330BX_XL_BATCHED_AT_60Hz: + *val = ISM330BX_XL_BATCHED_AT_60Hz; + break; + + case ISM330BX_XL_BATCHED_AT_120Hz: + *val = ISM330BX_XL_BATCHED_AT_120Hz; + break; + + case ISM330BX_XL_BATCHED_AT_240Hz: + *val = ISM330BX_XL_BATCHED_AT_240Hz; + break; + + case ISM330BX_XL_BATCHED_AT_480Hz: + *val = ISM330BX_XL_BATCHED_AT_480Hz; + break; + + case ISM330BX_XL_BATCHED_AT_960Hz: + *val = ISM330BX_XL_BATCHED_AT_960Hz; + break; + + case ISM330BX_XL_BATCHED_AT_1920Hz: + *val = ISM330BX_XL_BATCHED_AT_1920Hz; + break; + + case ISM330BX_XL_BATCHED_AT_3840Hz: + *val = ISM330BX_XL_BATCHED_AT_3840Hz; + break; + + default: + *val = ISM330BX_XL_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[set] + * + * @param ctx read / write interface definitions + * @param val ism330bx_fifo_gy_batch_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_gy_batch_set(const stmdev_ctx_t *ctx, + ism330bx_fifo_gy_batch_t val) +{ + ism330bx_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret == 0) + { + fifo_ctrl3.bdr_gy = (uint8_t)val & 0xFU; + ret = ism330bx_write_reg(ctx, ISM330BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + } + + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[get] + * + * @param ctx read / write interface definitions + * @param val ism330bx_fifo_gy_batch_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_gy_batch_get(const stmdev_ctx_t *ctx, + ism330bx_fifo_gy_batch_t *val) +{ + ism330bx_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + switch (fifo_ctrl3.bdr_gy) + { + case ISM330BX_GY_NOT_BATCHED: + *val = ISM330BX_GY_NOT_BATCHED; + break; + + case ISM330BX_GY_BATCHED_AT_1Hz875: + *val = ISM330BX_GY_BATCHED_AT_1Hz875; + break; + + case ISM330BX_GY_BATCHED_AT_7Hz5: + *val = ISM330BX_GY_BATCHED_AT_7Hz5; + break; + + case ISM330BX_GY_BATCHED_AT_15Hz: + *val = ISM330BX_GY_BATCHED_AT_15Hz; + break; + + case ISM330BX_GY_BATCHED_AT_30Hz: + *val = ISM330BX_GY_BATCHED_AT_30Hz; + break; + + case ISM330BX_GY_BATCHED_AT_60Hz: + *val = ISM330BX_GY_BATCHED_AT_60Hz; + break; + + case ISM330BX_GY_BATCHED_AT_120Hz: + *val = ISM330BX_GY_BATCHED_AT_120Hz; + break; + + case ISM330BX_GY_BATCHED_AT_240Hz: + *val = ISM330BX_GY_BATCHED_AT_240Hz; + break; + + case ISM330BX_GY_BATCHED_AT_480Hz: + *val = ISM330BX_GY_BATCHED_AT_480Hz; + break; + + case ISM330BX_GY_BATCHED_AT_960Hz: + *val = ISM330BX_GY_BATCHED_AT_960Hz; + break; + + case ISM330BX_GY_BATCHED_AT_1920Hz: + *val = ISM330BX_GY_BATCHED_AT_1920Hz; + break; + + case ISM330BX_GY_BATCHED_AT_3840Hz: + *val = ISM330BX_GY_BATCHED_AT_3840Hz; + break; + + default: + *val = ISM330BX_GY_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief FIFO mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_mode_set(const stmdev_ctx_t *ctx, + ism330bx_fifo_mode_t val) +{ + ism330bx_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.fifo_mode = (uint8_t)val & 0x07U; + ret = ism330bx_write_reg(ctx, ISM330BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief FIFO mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_mode_get(const stmdev_ctx_t *ctx, + ism330bx_fifo_mode_t *val) +{ + ism330bx_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + switch (fifo_ctrl4.fifo_mode) + { + case ISM330BX_BYPASS_MODE: + *val = ISM330BX_BYPASS_MODE; + break; + + case ISM330BX_FIFO_MODE: + *val = ISM330BX_FIFO_MODE; + break; + + case ISM330BX_STREAM_WTM_TO_FULL_MODE: + *val = ISM330BX_STREAM_WTM_TO_FULL_MODE; + break; + + case ISM330BX_STREAM_TO_FIFO_MODE: + *val = ISM330BX_STREAM_TO_FIFO_MODE; + break; + + case ISM330BX_BYPASS_TO_STREAM_MODE: + *val = ISM330BX_BYPASS_TO_STREAM_MODE; + break; + + case ISM330BX_STREAM_MODE: + *val = ISM330BX_STREAM_MODE; + break; + + case ISM330BX_BYPASS_TO_FIFO_MODE: + *val = ISM330BX_BYPASS_TO_FIFO_MODE; + break; + + default: + *val = ISM330BX_BYPASS_MODE; + break; + } + return ret; +} + +/** + * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[set] + * + * @param ctx read / write interface definitions + * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_temp_batch_set(const stmdev_ctx_t *ctx, + ism330bx_fifo_temp_batch_t val) +{ + ism330bx_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.odr_t_batch = (uint8_t)val & 0x03U; + ret = ism330bx_write_reg(ctx, ISM330BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[get] + * + * @param ctx read / write interface definitions + * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_temp_batch_get(const stmdev_ctx_t *ctx, + ism330bx_fifo_temp_batch_t *val) +{ + ism330bx_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + switch (fifo_ctrl4.odr_t_batch) + { + case ISM330BX_TEMP_NOT_BATCHED: + *val = ISM330BX_TEMP_NOT_BATCHED; + break; + + case ISM330BX_TEMP_BATCHED_AT_1Hz875: + *val = ISM330BX_TEMP_BATCHED_AT_1Hz875; + break; + + case ISM330BX_TEMP_BATCHED_AT_15Hz: + *val = ISM330BX_TEMP_BATCHED_AT_15Hz; + break; + + case ISM330BX_TEMP_BATCHED_AT_60Hz: + *val = ISM330BX_TEMP_BATCHED_AT_60Hz; + break; + + default: + *val = ISM330BX_TEMP_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[set] + * + * @param ctx read / write interface definitions + * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx, + ism330bx_fifo_timestamp_batch_t val) +{ + ism330bx_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.dec_ts_batch = (uint8_t)val & 0x3U; + ret = ism330bx_write_reg(ctx, ISM330BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[get] + * + * @param ctx read / write interface definitions + * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, + ism330bx_fifo_timestamp_batch_t *val) +{ + ism330bx_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + switch (fifo_ctrl4.dec_ts_batch) + { + case ISM330BX_TMSTMP_NOT_BATCHED: + *val = ISM330BX_TMSTMP_NOT_BATCHED; + break; + + case ISM330BX_TMSTMP_DEC_1: + *val = ISM330BX_TMSTMP_DEC_1; + break; + + case ISM330BX_TMSTMP_DEC_8: + *val = ISM330BX_TMSTMP_DEC_8; + break; + + case ISM330BX_TMSTMP_DEC_32: + *val = ISM330BX_TMSTMP_DEC_32; + break; + + default: + *val = ISM330BX_TMSTMP_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[set] + * + * @param ctx read / write interface definitions + * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx, + uint16_t val) +{ + ism330bx_counter_bdr_reg1_t counter_bdr_reg1; + ism330bx_counter_bdr_reg2_t counter_bdr_reg2; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + + if (ret == 0) + { + counter_bdr_reg2.cnt_bdr_th = (uint8_t)val & 0xFFU; + counter_bdr_reg1.cnt_bdr_th = (uint8_t)(val >> 8) & 0x3U; + ret = ism330bx_write_reg(ctx, ISM330BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + ret += ism330bx_write_reg(ctx, ISM330BX_COUNTER_BDR_REG2, (uint8_t *)&counter_bdr_reg2, 1); + } + + return ret; +} + +/** + * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[get] + * + * @param ctx read / write interface definitions + * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx, + uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_COUNTER_BDR_REG1, &buff[0], 2); + *val = (uint16_t)buff[0] & 0x3U; + *val = (*val * 256U) + (uint16_t)buff[1]; + + return ret; +} + +/** + * @brief Enables AH_QVAR batching in FIFO.[set] + * + * @param ctx read / write interface definitions + * @param val Enables AH_QVAR batching in FIFO. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_batch_ah_qvar_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret == 0) + { + counter_bdr_reg1.ah_qvar_batch_en = val; + ret = ism330bx_write_reg(ctx, ISM330BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + } + + return ret; +} + +/** + * @brief Enables AH_QVAR batching in FIFO.[get] + * + * @param ctx read / write interface definitions + * @param val Enables AH_QVAR batching in FIFO. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_batch_ah_qvar_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + *val = counter_bdr_reg1.ah_qvar_batch_en; + + return ret; +} + +/** + * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope.[set] + * + * @param ctx read / write interface definitions + * @param val XL_BATCH_EVENT, GY_BATCH_EVENT + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_batch_cnt_event_set(const stmdev_ctx_t *ctx, + ism330bx_fifo_batch_cnt_event_t val) +{ + ism330bx_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + + if (ret == 0) + { + counter_bdr_reg1.trig_counter_bdr = (uint8_t)val & 0x03U; + ret = ism330bx_write_reg(ctx, ISM330BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + } + + return ret; +} + +/** + * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope.[get] + * + * @param ctx read / write interface definitions + * @param val XL_BATCH_EVENT, GY_BATCH_EVENT + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx, + ism330bx_fifo_batch_cnt_event_t *val) +{ + ism330bx_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + switch (counter_bdr_reg1.trig_counter_bdr) + { + case ISM330BX_XL_BATCH_EVENT: + *val = ISM330BX_XL_BATCH_EVENT; + break; + + case ISM330BX_GY_BATCH_EVENT: + *val = ISM330BX_GY_BATCH_EVENT; + break; + + default: + *val = ISM330BX_XL_BATCH_EVENT; + break; + } + return ret; +} + +/** + * @brief Batching in FIFO buffer of SFLP.[set] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of SFLP values. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_sflp_batch_set(const stmdev_ctx_t *ctx, + ism330bx_fifo_sflp_raw_t val) +{ + ism330bx_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + emb_func_fifo_en_a.sflp_game_fifo_en = val.game_rotation; + emb_func_fifo_en_a.sflp_gravity_fifo_en = val.gravity; + emb_func_fifo_en_a.sflp_gbias_fifo_en = val.gbias; + ret += ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_A, + (uint8_t *)&emb_func_fifo_en_a, 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of SFLP.[get] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of SFLP values. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_sflp_batch_get(const stmdev_ctx_t *ctx, + ism330bx_fifo_sflp_raw_t *val) +{ + ism330bx_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + + val->game_rotation = emb_func_fifo_en_a.sflp_game_fifo_en; + val->gravity = emb_func_fifo_en_a.sflp_gravity_fifo_en; + val->gbias = emb_func_fifo_en_a.sflp_gbias_fifo_en; + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Status of FIFO.[get] + * + * @param ctx read / write interface definitions + * @param val Status of FIFO (level and flags). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_status_get(const stmdev_ctx_t *ctx, + ism330bx_fifo_status_t *val) +{ + uint8_t buff[2]; + ism330bx_fifo_status2_t status; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_STATUS1, (uint8_t *)&buff[0], 2); + bytecpy((uint8_t *)&status, &buff[1]); + + val->fifo_bdr = status.counter_bdr_ia; + val->fifo_ovr = status.fifo_ovr_ia; + val->fifo_full = status.fifo_full_ia; + val->fifo_th = status.fifo_wtm_ia; + + val->fifo_level = (uint16_t)buff[1] & 0x01U; + val->fifo_level = (val->fifo_level * 256U) + buff[0]; + + return ret; +} + +/** + * @brief FIFO data output[get] + * + * @param ctx read / write interface definitions + * @param val ism330bx_fifo_out_raw_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_out_raw_get(const stmdev_ctx_t *ctx, + ism330bx_fifo_out_raw_t *val) +{ + ism330bx_fifo_data_out_tag_t fifo_data_out_tag; + uint8_t buff[7]; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FIFO_DATA_OUT_TAG, buff, 7); + bytecpy((uint8_t *)&fifo_data_out_tag, &buff[0]); + + switch (fifo_data_out_tag.tag_sensor) + { + case ISM330BX_FIFO_EMPTY: + val->tag = ISM330BX_FIFO_EMPTY; + break; + + case ISM330BX_GY_NC_TAG: + val->tag = ISM330BX_GY_NC_TAG; + break; + + case ISM330BX_XL_NC_TAG: + val->tag = ISM330BX_XL_NC_TAG; + break; + + case ISM330BX_TIMESTAMP_TAG: + val->tag = ISM330BX_TIMESTAMP_TAG; + break; + + case ISM330BX_TEMPERATURE_TAG: + val->tag = ISM330BX_TEMPERATURE_TAG; + break; + + case ISM330BX_CFG_CHANGE_TAG: + val->tag = ISM330BX_CFG_CHANGE_TAG; + break; + + case ISM330BX_XL_NC_T_2_TAG: + val->tag = ISM330BX_XL_NC_T_2_TAG; + break; + + case ISM330BX_XL_NC_T_1_TAG: + val->tag = ISM330BX_XL_NC_T_1_TAG; + break; + + case ISM330BX_XL_2XC_TAG: + val->tag = ISM330BX_XL_2XC_TAG; + break; + + case ISM330BX_XL_3XC_TAG: + val->tag = ISM330BX_XL_3XC_TAG; + break; + + case ISM330BX_GY_NC_T_2_TAG: + val->tag = ISM330BX_GY_NC_T_2_TAG; + break; + + case ISM330BX_GY_NC_T_1_TAG: + val->tag = ISM330BX_GY_NC_T_1_TAG; + break; + + case ISM330BX_GY_2XC_TAG: + val->tag = ISM330BX_GY_2XC_TAG; + break; + + case ISM330BX_GY_3XC_TAG: + val->tag = ISM330BX_GY_3XC_TAG; + break; + + case ISM330BX_STEP_COUNTER_TAG: + val->tag = ISM330BX_STEP_COUNTER_TAG; + break; + + case ISM330BX_MLC_RESULT_TAG: + val->tag = ISM330BX_MLC_RESULT_TAG; + break; + + case ISM330BX_SFLP_GAME_ROTATION_VECTOR_TAG: + val->tag = ISM330BX_SFLP_GAME_ROTATION_VECTOR_TAG; + break; + + case ISM330BX_SFLP_GYROSCOPE_BIAS_TAG: + val->tag = ISM330BX_SFLP_GYROSCOPE_BIAS_TAG; + break; + + case ISM330BX_SFLP_GRAVITY_VECTOR_TAG: + val->tag = ISM330BX_SFLP_GRAVITY_VECTOR_TAG; + break; + + case ISM330BX_MLC_FILTER: + val->tag = ISM330BX_MLC_FILTER; + break; + + case ISM330BX_MLC_FEATURE: + val->tag = ISM330BX_MLC_FEATURE; + break; + + case ISM330BX_XL_DUAL_CORE: + val->tag = ISM330BX_XL_DUAL_CORE; + break; + + case ISM330BX_AH_QVAR: + val->tag = ISM330BX_AH_QVAR; + break; + + default: + val->tag = ISM330BX_FIFO_EMPTY; + break; + } + + val->cnt = fifo_data_out_tag.tag_cnt; + + val->data[0] = buff[1]; + val->data[1] = buff[2]; + val->data[2] = buff[3]; + val->data[3] = buff[4]; + val->data[4] = buff[5]; + val->data[5] = buff[6]; + + return ret; +} + +/** + * @brief Batching in FIFO buffer of step counter value.[set] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of step counter value. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + if (ret == 0) + { + emb_func_fifo_en_a.step_counter_fifo_en = val; + ret = ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of step counter value.[get] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of step counter value. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + *val = emb_func_fifo_en_a.step_counter_fifo_en; + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + + return ret; +} + +/** + * @brief Batching in FIFO buffer of machine learning core results.[set] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of machine learning core results. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_mlc_batch_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + if (ret == 0) + { + emb_func_fifo_en_a.mlc_fifo_en = val; + ret = ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of machine learning core results.[get] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of machine learning core results. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_mlc_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + *val = emb_func_fifo_en_a.mlc_fifo_en; + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables batching in FIFO buffer of machine learning core filters and features.[set] + * + * @param ctx read / write interface definitions + * @param val Enables batching in FIFO buffer of machine learning core filters and features. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_mlc_filt_batch_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_emb_func_fifo_en_b_t emb_func_fifo_en_b; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + } + + if (ret == 0) + { + emb_func_fifo_en_b.mlc_filter_feature_fifo_en = val; + ret = ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables batching in FIFO buffer of machine learning core filters and features.[get] + * + * @param ctx read / write interface definitions + * @param val Enables batching in FIFO buffer of machine learning core filters and features. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fifo_mlc_filt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_emb_func_fifo_en_b_t emb_func_fifo_en_b; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + } + + *val = emb_func_fifo_en_b.mlc_filter_feature_fifo_en; + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Step Counter + * @brief This section groups all the functions that manage pedometer. + * @{ + * + */ + +/** + * @brief Step counter mode[set] + * + * @param ctx read / write interface definitions + * @param val false_step_rej, step_counter, step_detector, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_stpcnt_mode_set(const stmdev_ctx_t *ctx, + ism330bx_stpcnt_mode_t val) +{ + ism330bx_emb_func_en_a_t emb_func_en_a; + ism330bx_emb_func_en_b_t emb_func_en_b; + ism330bx_pedo_cmd_reg_t pedo_cmd_reg; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + if ((val.false_step_rej == PROPERTY_ENABLE) + && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) == + PROPERTY_DISABLE)) + { + emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE; + } + if (ret == 0) + { + emb_func_en_a.pedo_en = val.step_counter_enable; + ret = ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = ism330bx_ln_pg_read(ctx, ISM330BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + if (ret == 0) + { + pedo_cmd_reg.fp_rejection_en = val.false_step_rej; + ret = ism330bx_ln_pg_write(ctx, ISM330BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + return ret; +} + +/** + * @brief Step counter mode[get] + * + * @param ctx read / write interface definitions + * @param val false_step_rej, step_counter, step_detector, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_stpcnt_mode_get(const stmdev_ctx_t *ctx, + ism330bx_stpcnt_mode_t *val) +{ + ism330bx_emb_func_en_a_t emb_func_en_a; + ism330bx_pedo_cmd_reg_t pedo_cmd_reg; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = ism330bx_ln_pg_read(ctx, ISM330BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + val->false_step_rej = pedo_cmd_reg.fp_rejection_en; + val->step_counter_enable = emb_func_en_a.pedo_en; + + return ret; +} + +/** + * @brief Step counter output, number of detected steps.[get] + * + * @param ctx read / write interface definitions + * @param val Step counter output, number of detected steps. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_STEP_COUNTER_L, &buff[0], 2); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief Reset step counter.[set] + * + * @param ctx read / write interface definitions + * @param val Reset step counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_stpcnt_rst_step_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_emb_func_src_t emb_func_src; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + + if (ret == 0) + { + emb_func_src.pedo_rst_step = val; + ret = ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Reset step counter.[get] + * + * @param ctx read / write interface definitions + * @param val Reset step counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_emb_func_src_t emb_func_src; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + + *val = emb_func_src.pedo_rst_step; + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Pedometer debounce configuration.[set] + * + * @param ctx read / write interface definitions + * @param val Pedometer debounce configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_pedo_deb_steps_conf_t pedo_deb_steps_conf; + int32_t ret; + + ret = ism330bx_ln_pg_read(ctx, ISM330BX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, + 1); + if (ret == 0) + { + pedo_deb_steps_conf.deb_step = val; + ret = ism330bx_ln_pg_write(ctx, ISM330BX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, + 1); + } + + return ret; +} + +/** + * @brief Pedometer debounce configuration.[get] + * + * @param ctx read / write interface definitions + * @param val Pedometer debounce configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_pedo_deb_steps_conf_t pedo_deb_steps_conf; + int32_t ret; + + ret = ism330bx_ln_pg_read(ctx, ISM330BX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, + 1); + *val = pedo_deb_steps_conf.deb_step; + + return ret; +} + +/** + * @brief Time period register for step detection on delta time.[set] + * + * @param ctx read / write interface definitions + * @param val Time period register for step detection on delta time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + + ret = ism330bx_ln_pg_write(ctx, ISM330BX_PEDO_SC_DELTAT_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief Time period register for step detection on delta time.[get] + * + * @param ctx read / write interface definitions + * @param val Time period register for step detection on delta time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = ism330bx_ln_pg_read(ctx, ISM330BX_PEDO_SC_DELTAT_L, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Significant motion + * @brief This section groups all the functions that manage the + * significant motion detection. + * @{ + * + */ + +/** + * @brief Enables significant motion detection function.[set] + * + * @param ctx read / write interface definitions + * @param val Enables significant motion detection function. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { + emb_func_en_a.sign_motion_en = val; + ret = ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + + return ret; +} + +/** + * @brief Enables significant motion detection function.[get] + * + * @param ctx read / write interface definitions + * @param val Enables significant motion detection function. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + *val = emb_func_en_a.sign_motion_en; + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Tilt detection + * @brief This section groups all the functions that manage the tilt + * event detection. + * @{ + * + */ + +/** + * @brief Tilt calculation.[set] + * + * @param ctx read / write interface definitions + * @param val Tilt calculation. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { + emb_func_en_a.tilt_en = val; + ret = ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Tilt calculation.[get] + * + * @param ctx read / write interface definitions + * @param val Tilt calculation. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + *val = emb_func_en_a.tilt_en; + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Sensor Fusion Low Power (SFLP) + * @brief This section groups all the functions that manage pedometer. + * @{ + * + */ + +/** + * @brief Enable SFLP Game Rotation Vector (6x).[set] + * + * @param ctx read / write interface definitions + * @param val Enable/Disable game rotation value (0/1). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + ism330bx_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + emb_func_en_a.sflp_game_en = val; + ret += ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_A, + (uint8_t *)&emb_func_en_a, 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable SFLP Game Rotation Vector (6x).[get] + * + * @param ctx read / write interface definitions + * @param val Enable/Disable game rotation value (0/1). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + ism330bx_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + *val = emb_func_en_a.sflp_game_en; + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief SFLP Data Rate (ODR) configuration.[set] + * + * @param ctx read / write interface definitions + * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_sflp_data_rate_set(const stmdev_ctx_t *ctx, + ism330bx_sflp_data_rate_t val) +{ + ism330bx_sflp_odr_t sflp_odr; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + sflp_odr.sflp_game_odr = (uint8_t)val & 0x07U; + ret += ism330bx_write_reg(ctx, ISM330BX_SFLP_ODR, (uint8_t *)&sflp_odr, + 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief SFLP Data Rate (ODR) configuration.[get] + * + * @param ctx read / write interface definitions + * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_sflp_data_rate_get(const stmdev_ctx_t *ctx, + ism330bx_sflp_data_rate_t *val) +{ + ism330bx_sflp_odr_t sflp_odr; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + ret += ism330bx_read_reg(ctx, ISM330BX_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + switch (sflp_odr.sflp_game_odr) + { + case ISM330BX_SFLP_15Hz: + *val = ISM330BX_SFLP_15Hz; + break; + + case ISM330BX_SFLP_30Hz: + *val = ISM330BX_SFLP_30Hz; + break; + + case ISM330BX_SFLP_60Hz: + *val = ISM330BX_SFLP_60Hz; + break; + + case ISM330BX_SFLP_120Hz: + *val = ISM330BX_SFLP_120Hz; + break; + + case ISM330BX_SFLP_240Hz: + *val = ISM330BX_SFLP_240Hz; + break; + + case ISM330BX_SFLP_480Hz: + *val = ISM330BX_SFLP_480Hz; + break; + + default: + *val = ISM330BX_SFLP_15Hz; + break; + } + return ret; +} + +/* + * Original conversion routines taken from: https://github.com/numpy/numpy + * + * uint16_t npy_floatbits_to_halfbits(uint32_t f); + * uint16_t npy_float_to_half(float_t f); + * + * Released under BSD-3-Clause License + */ + +#define NPY_HALF_GENERATE_OVERFLOW 0 /* do not trigger FP overflow */ +#define NPY_HALF_GENERATE_UNDERFLOW 0 /* do not trigger FP underflow */ +#ifndef NPY_HALF_ROUND_TIES_TO_EVEN +#define NPY_HALF_ROUND_TIES_TO_EVEN 1 +#endif + +static uint16_t npy_floatbits_to_halfbits(uint32_t f) +{ + uint32_t f_exp, f_sig; + uint16_t h_sgn, h_exp, h_sig; + + h_sgn = (uint16_t)((f & 0x80000000u) >> 16); + f_exp = (f & 0x7f800000u); + + /* Exponent overflow/NaN converts to signed inf/NaN */ + if (f_exp >= 0x47800000u) + { + if (f_exp == 0x7f800000u) + { + /* Inf or NaN */ + f_sig = (f & 0x007fffffu); + if (f_sig != 0) + { + /* NaN - propagate the flag in the significand... */ + uint16_t ret = (uint16_t)(0x7c00u + (f_sig >> 13)); + /* ...but make sure it stays a NaN */ + if (ret == 0x7c00u) + { + ret++; + } + return h_sgn + ret; + } + else + { + /* signed inf */ + return (uint16_t)(h_sgn + 0x7c00u); + } + } + else + { + /* overflow to signed inf */ +#if NPY_HALF_GENERATE_OVERFLOW + npy_set_floatstatus_overflow(); +#endif + return (uint16_t)(h_sgn + 0x7c00u); + } + } + + /* Exponent underflow converts to a subnormal half or signed zero */ + if (f_exp <= 0x38000000u) + { + /* + * Signed zeros, subnormal floats, and floats with small + * exponents all convert to signed zero half-floats. + */ + if (f_exp < 0x33000000u) + { +#if NPY_HALF_GENERATE_UNDERFLOW + /* If f != 0, it underflowed to 0 */ + if ((f & 0x7fffffff) != 0) + { + npy_set_floatstatus_underflow(); + } +#endif + return h_sgn; + } + /* Make the subnormal significand */ + f_exp >>= 23; + f_sig = (0x00800000u + (f & 0x007fffffu)); +#if NPY_HALF_GENERATE_UNDERFLOW + /* If it's not exactly represented, it underflowed */ + if ((f_sig & (((uint32_t)1 << (126 - f_exp)) - 1)) != 0) + { + npy_set_floatstatus_underflow(); + } +#endif + /* + * Usually the significand is shifted by 13. For subnormals an + * additional shift needs to occur. This shift is one for the largest + * exponent giving a subnormal `f_exp = 0x38000000 >> 23 = 112`, which + * offsets the new first bit. At most the shift can be 1+10 bits. + */ + f_sig >>= (113 - f_exp); + /* Handle rounding by adding 1 to the bit beyond half precision */ +#if NPY_HALF_ROUND_TIES_TO_EVEN + /* + * If the last bit in the half significand is 0 (already even), and + * the remaining bit pattern is 1000...0, then we do not add one + * to the bit after the half significand. However, the (113 - f_exp) + * shift can lose up to 11 bits, so the || checks them in the original. + * In all other cases, we can just add one. + */ + if (((f_sig & 0x00003fffu) != 0x00001000u) || (f & 0x000007ffu)) + { + f_sig += 0x00001000u; + } +#else + f_sig += 0x00001000u; +#endif + h_sig = (uint16_t)(f_sig >> 13); + /* + * If the rounding causes a bit to spill into h_exp, it will + * increment h_exp from zero to one and h_sig will be zero. + * This is the correct result. + */ + return (uint16_t)(h_sgn + h_sig); + } + + /* Regular case with no overflow or underflow */ + h_exp = (uint16_t)((f_exp - 0x38000000u) >> 13); + /* Handle rounding by adding 1 to the bit beyond half precision */ + f_sig = (f & 0x007fffffu); +#if NPY_HALF_ROUND_TIES_TO_EVEN + /* + * If the last bit in the half significand is 0 (already even), and + * the remaining bit pattern is 1000...0, then we do not add one + * to the bit after the half significand. In all other cases, we do. + */ + if ((f_sig & 0x00003fffu) != 0x00001000u) + { + f_sig += 0x00001000u; + } +#else + f_sig += 0x00001000u; +#endif + h_sig = (uint16_t)(f_sig >> 13); + /* + * If the rounding causes a bit to spill into h_exp, it will + * increment h_exp by one and h_sig will be zero. This is the + * correct result. h_exp may increment to 15, at greatest, in + * which case the result overflows to a signed inf. + */ +#if NPY_HALF_GENERATE_OVERFLOW + h_sig += h_exp; + if (h_sig == 0x7c00u) + { + npy_set_floatstatus_overflow(); + } + return h_sgn + h_sig; +#else + return h_sgn + h_exp + h_sig; +#endif +} + +static uint16_t npy_float_to_half(float_t f) +{ + union + { + float_t f; + uint32_t fbits; + } conv; + conv.f = f; + return npy_floatbits_to_halfbits(conv.fbits); +} + +/** + * @brief SFLP GBIAS value. The register value is expressed as half-precision + * floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent + * bits; F: 10 fraction bits).[set] + * + * @param ctx read / write interface definitions + * @param val GBIAS x/y/z val. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_sflp_game_gbias_set(const stmdev_ctx_t *ctx, + ism330bx_sflp_gbias_t *val) +{ + ism330bx_sflp_data_rate_t sflp_odr; + ism330bx_emb_func_exec_status_t emb_func_sts; + ism330bx_data_ready_t drdy; + ism330bx_xl_full_scale_t xl_fs; + ism330bx_ctrl10_t ctrl10; + uint8_t master_config; + uint8_t emb_func_en_saved[2]; + uint8_t conf_saved[2]; + uint8_t reg_zero[2] = {0x0, 0x0}; + uint16_t gbias_hf[3]; + float_t k = 0.005f; + int16_t xl_data[3]; + int32_t data_tmp; + uint8_t *data_ptr = (uint8_t *)&data_tmp; + uint8_t i, j; + int32_t ret; + + ret = ism330bx_sflp_data_rate_get(ctx, &sflp_odr); + if (ret != 0) + { + return ret; + } + + /* Calculate k factor */ + switch (sflp_odr) + { + case ISM330BX_SFLP_15Hz: + k = 0.04f; + break; + case ISM330BX_SFLP_30Hz: + k = 0.02f; + break; + case ISM330BX_SFLP_60Hz: + k = 0.01f; + break; + case ISM330BX_SFLP_120Hz: + k = 0.005f; + break; + case ISM330BX_SFLP_240Hz: + k = 0.0025f; + break; + case ISM330BX_SFLP_480Hz: + k = 0.00125f; + break; + } + + /* compute gbias as half precision float in order to be put in embedded advanced feature register */ + gbias_hf[0] = npy_float_to_half(val->gbias_x * (3.14159265358979323846f / 180.0f) / k); + gbias_hf[1] = npy_float_to_half(val->gbias_y * (3.14159265358979323846f / 180.0f) / k); + gbias_hf[2] = npy_float_to_half(val->gbias_z * (3.14159265358979323846f / 180.0f) / k); + + /* Save sensor configuration and set high-performance mode (if the sensor is in power-down mode, turn it on) */ + ret += ism330bx_read_reg(ctx, ISM330BX_CTRL1, conf_saved, 2); + ret += ism330bx_xl_mode_set(ctx, ISM330BX_XL_HIGH_PERFORMANCE_MD); + ret += ism330bx_gy_mode_set(ctx, ISM330BX_GY_HIGH_PERFORMANCE_MD); + if ((conf_saved[0] & 0x0FU) == ISM330BX_XL_ODR_OFF) + { + ret += ism330bx_xl_data_rate_set(ctx, ISM330BX_XL_ODR_AT_120Hz); + } + + /* disable algos */ + ret += ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + ret += ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, emb_func_en_saved, + 2); + ret += ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_A, reg_zero, 2); + do + { + ret += ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EXEC_STATUS, + (uint8_t *)&emb_func_sts, 1); + } while (emb_func_sts.emb_func_endop != 1); + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + // enable gbias setting + ret += ism330bx_read_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1); + ctrl10.emb_func_debug = 1; + ret += ism330bx_write_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1); + + /* enable algos */ + ret += ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + emb_func_en_saved[0] |= 0x02; /* force SFLP GAME en */ + ret += ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_A, emb_func_en_saved, + 2); + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + ret += ism330bx_xl_full_scale_get(ctx, &xl_fs); + + /* Read XL data */ + do + { + ret += ism330bx_flag_data_ready_get(ctx, &drdy); + } while (drdy.drdy_xl != 1); + ret += ism330bx_acceleration_raw_get(ctx, xl_data); + + /* force sflp initialization */ + master_config = 0x40; + ret += ism330bx_write_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, &master_config, + 1); + for (i = 0; i < 3; i++) + { + j = 0; + data_tmp = (int32_t)xl_data[i]; + data_tmp <<= xl_fs; // shift based on current fs + ret += ism330bx_write_reg(ctx, 0x02 + 3 * i, &data_ptr[j++], 1); + ret += ism330bx_write_reg(ctx, 0x03 + 3 * i, &data_ptr[j++], 1); + ret += ism330bx_write_reg(ctx, 0x04 + 3 * i, &data_ptr[j], 1); + } + for (i = 0; i < 3; i++) + { + j = 0; + data_tmp = 0; + ret += ism330bx_write_reg(ctx, 0x0B + 3 * i, &data_ptr[j++], 1); + ret += ism330bx_write_reg(ctx, 0x0C + 3 * i, &data_ptr[j++], 1); + ret += ism330bx_write_reg(ctx, 0x0D + 3 * i, &data_ptr[j], 1); + } + master_config = 0x00; + ret += ism330bx_write_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, &master_config, + 1); + + // wait end_op (and at least 30 us) + ctx->mdelay(1); + ret += ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + do + { + ret += ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EXEC_STATUS, + (uint8_t *)&emb_func_sts, 1); + } while (emb_func_sts.emb_func_endop != 1); + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + /* write gbias in embedded advanced features registers */ + ret += ism330bx_ln_pg_write(ctx, ISM330BX_SFLP_GAME_GBIASX_L, + (uint8_t *)gbias_hf, 6); + + /* reload previous sensor configuration */ + ret += ism330bx_write_reg(ctx, ISM330BX_CTRL1, conf_saved, 2); + + // disable gbias setting + ctrl10.emb_func_debug = 0; + ret += ism330bx_write_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1); + + return ret; +} + +/** + * @brief SFLP initial configuration [set] + * + * @param ctx read / write interface definitions + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_sflp_configure(const stmdev_ctx_t *ctx) +{ + uint8_t val = 0x50; + int32_t ret; + + ret = ism330bx_ln_pg_write(ctx, 0xD2, &val, 1); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Finite State Machine (FSM) + * @brief This section groups all the functions that manage the + * state_machine. + * @{ + * + */ + +/** + * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[set] + * + * @param ctx read / write interface definitions + * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fsm_permission_set(const stmdev_ctx_t *ctx, + ism330bx_fsm_permission_t val) +{ + ism330bx_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret == 0) + { + func_cfg_access.fsm_wr_ctrl_en = (uint8_t)val & 0x01U; + ret = ism330bx_write_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[get] + * + * @param ctx read / write interface definitions + * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fsm_permission_get(const stmdev_ctx_t *ctx, + ism330bx_fsm_permission_t *val) +{ + ism330bx_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + switch (func_cfg_access.fsm_wr_ctrl_en) + { + case ISM330BX_PROTECT_CTRL_REGS: + *val = ISM330BX_PROTECT_CTRL_REGS; + break; + + case ISM330BX_WRITE_CTRL_REG: + *val = ISM330BX_WRITE_CTRL_REG; + break; + + default: + *val = ISM330BX_PROTECT_CTRL_REGS; + break; + } + return ret; +} + +/** + * @brief Return the status of the CTRL registers permission (standard interface vs FSM).[get] + * + * @param ctx read / write interface definitions + * @param val 0: all FSM regs are under std_if control, 1: some regs are under FSM control. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fsm_permission_status(const stmdev_ctx_t *ctx, + ism330bx_fsm_permission_status_t *val) +{ + ism330bx_ctrl_status_t status; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL_STATUS, (uint8_t *)&status, 1); + *val = (status.fsm_wr_ctrl_status == 0) ? ISM330BX_STD_IF_CONTROL : ISM330BX_FSM_CONTROL; + + return ret; +} + +/** + * @brief Enable Finite State Machine (FSM) feature.[set] + * + * @param ctx read / write interface definitions + * @param val Enable Finite State Machine (FSM) feature. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fsm_mode_set(const stmdev_ctx_t *ctx, ism330bx_fsm_mode_t val) +{ + ism330bx_emb_func_en_b_t emb_func_en_b; + ism330bx_fsm_enable_t fsm_enable; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + } + if ((val.fsm1_en | val.fsm2_en | val.fsm1_en | val.fsm1_en + | val.fsm1_en | val.fsm2_en | val.fsm1_en | val.fsm1_en) == PROPERTY_ENABLE) + { + emb_func_en_b.fsm_en = PROPERTY_ENABLE; + } + else + { + emb_func_en_b.fsm_en = PROPERTY_DISABLE; + } + if (ret == 0) + { + fsm_enable.fsm1_en = val.fsm1_en; + fsm_enable.fsm2_en = val.fsm2_en; + fsm_enable.fsm3_en = val.fsm3_en; + fsm_enable.fsm4_en = val.fsm4_en; + fsm_enable.fsm5_en = val.fsm5_en; + fsm_enable.fsm6_en = val.fsm6_en; + fsm_enable.fsm7_en = val.fsm7_en; + fsm_enable.fsm8_en = val.fsm8_en; + ret = ism330bx_write_reg(ctx, ISM330BX_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + } + if (ret == 0) + { + ret = ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable Finite State Machine (FSM) feature.[get] + * + * @param ctx read / write interface definitions + * @param val Enable Finite State Machine (FSM) feature. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fsm_mode_get(const stmdev_ctx_t *ctx, ism330bx_fsm_mode_t *val) +{ + ism330bx_fsm_enable_t fsm_enable; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + val->fsm1_en = fsm_enable.fsm1_en; + val->fsm2_en = fsm_enable.fsm2_en; + val->fsm3_en = fsm_enable.fsm3_en; + val->fsm4_en = fsm_enable.fsm4_en; + val->fsm5_en = fsm_enable.fsm5_en; + val->fsm6_en = fsm_enable.fsm6_en; + val->fsm7_en = fsm_enable.fsm7_en; + val->fsm8_en = fsm_enable.fsm8_en; + + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[set] + * + * @param ctx read / write interface definitions + * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_write_reg(ctx, ISM330BX_FSM_LONG_COUNTER_L, (uint8_t *)&buff[0], 2); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[get] + * + * @param ctx read / write interface definitions + * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_FSM_LONG_COUNTER_L, &buff[0], 2); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief FSM output registers[get] + * + * @param ctx read / write interface definitions + * @param val FSM output registers + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fsm_out_get(const stmdev_ctx_t *ctx, ism330bx_fsm_out_t *val) +{ + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_FSM_OUTS1, (uint8_t *)val, 8); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Finite State Machine Output Data Rate (ODR) configuration.[set] + * + * @param ctx read / write interface definitions + * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fsm_data_rate_set(const stmdev_ctx_t *ctx, + ism330bx_fsm_data_rate_t val) +{ + ism330bx_fsm_odr_t fsm_odr; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_FSM_ODR, (uint8_t *)&fsm_odr, 1); + } + + if (ret == 0) + { + fsm_odr.fsm_odr = (uint8_t)val & 0x07U; + ret = ism330bx_write_reg(ctx, ISM330BX_FSM_ODR, (uint8_t *)&fsm_odr, 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Finite State Machine Output Data Rate (ODR) configuration.[get] + * + * @param ctx read / write interface definitions + * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fsm_data_rate_get(const stmdev_ctx_t *ctx, + ism330bx_fsm_data_rate_t *val) +{ + ism330bx_fsm_odr_t fsm_odr; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_FSM_ODR, (uint8_t *)&fsm_odr, 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + switch (fsm_odr.fsm_odr) + { + case ISM330BX_FSM_15Hz: + *val = ISM330BX_FSM_15Hz; + break; + + case ISM330BX_FSM_30Hz: + *val = ISM330BX_FSM_30Hz; + break; + + case ISM330BX_FSM_60Hz: + *val = ISM330BX_FSM_60Hz; + break; + + case ISM330BX_FSM_120Hz: + *val = ISM330BX_FSM_120Hz; + break; + + case ISM330BX_FSM_240Hz: + *val = ISM330BX_FSM_240Hz; + break; + + case ISM330BX_FSM_480Hz: + *val = ISM330BX_FSM_480Hz; + break; + + case ISM330BX_FSM_960Hz: + *val = ISM330BX_FSM_960Hz; + break; + + default: + *val = ISM330BX_FSM_15Hz; + break; + } + return ret; +} + +/** + * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[set] + * + * @param ctx read / write interface definitions + * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fsm_long_cnt_timeout_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = ism330bx_ln_pg_write(ctx, ISM330BX_FSM_LC_TIMEOUT_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[get] + * + * @param ctx read / write interface definitions + * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = ism330bx_ln_pg_read(ctx, ISM330BX_FSM_LC_TIMEOUT_L, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief FSM number of programs.[set] + * + * @param ctx read / write interface definitions + * @param val FSM number of programs. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_fsm_programs_t fsm_programs; + int32_t ret; + + ret = ism330bx_ln_pg_read(ctx, ISM330BX_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + if (ret == 0) + { + fsm_programs.fsm_n_prog = val; + ret = ism330bx_ln_pg_write(ctx, ISM330BX_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + } + + return ret; +} + +/** + * @brief FSM number of programs.[get] + * + * @param ctx read / write interface definitions + * @param val FSM number of programs. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_fsm_programs_t fsm_programs; + int32_t ret; + + ret = ism330bx_ln_pg_read(ctx, ISM330BX_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + *val = fsm_programs.fsm_n_prog; + + + return ret; +} + +/** + * @brief FSM start address. First available address is 0x35C.[set] + * + * @param ctx read / write interface definitions + * @param val FSM start address. First available address is 0x35C. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = ism330bx_ln_pg_write(ctx, ISM330BX_FSM_START_ADD_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief FSM start address. First available address is 0x35C.[get] + * + * @param ctx read / write interface definitions + * @param val FSM start address. First available address is 0x35C. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = ism330bx_ln_pg_read(ctx, ISM330BX_FSM_START_ADD_L, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @addtogroup Machine Learning Core + * @brief This section group all the functions concerning the + * usage of Machine Learning Core + * @{ + * + */ + +/** + * @brief It enables Machine Learning Core feature (MLC). When the Machine Learning Core is enabled the Finite State Machine (FSM) programs are executed before executing the MLC algorithms.[set] + * + * @param ctx read / write interface definitions + * @param val MLC_OFF, MLC_ON, MLC_BEFORE_FSM, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_mlc_set(const stmdev_ctx_t *ctx, ism330bx_mlc_mode_t val) +{ + ism330bx_emb_func_en_b_t emb_en_b; + ism330bx_emb_func_en_a_t emb_en_a; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + + switch (val) + { + case ISM330BX_MLC_OFF: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 0; + break; + case ISM330BX_MLC_ON: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 1; + break; + case ISM330BX_MLC_ON_BEFORE_FSM: + emb_en_a.mlc_before_fsm_en = 1; + emb_en_b.mlc_en = 0; + break; + default: + break; + } + + ret += ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += ism330bx_write_reg(ctx, ISM330BX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief It enables Machine Learning Core feature (MLC). When the Machine Learning Core is enabled the Finite State Machine (FSM) programs are executed before executing the MLC algorithms.[get] + * + * @param ctx read / write interface definitions + * @param val MLC_OFF, MLC_ON, MLC_BEFORE_FSM, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_mlc_get(const stmdev_ctx_t *ctx, ism330bx_mlc_mode_t *val) +{ + ism330bx_emb_func_en_b_t emb_en_b; + ism330bx_emb_func_en_a_t emb_en_a; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += ism330bx_read_reg(ctx, ISM330BX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + + if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U) + { + *val = ISM330BX_MLC_OFF; + } + else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U) + { + *val = ISM330BX_MLC_ON; + } + else if (emb_en_a.mlc_before_fsm_en == 1U) + { + *val = ISM330BX_MLC_ON_BEFORE_FSM; + } + else + { + /* Do nothing */ + } + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Machine Learning Core Output Data Rate (ODR) configuration.[set] + * + * @param ctx read / write interface definitions + * @param val MLC_15Hz, MLC_30Hz, MLC_60Hz, MLC_120Hz, MLC_240Hz, MLC_480Hz, MLC_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_mlc_data_rate_set(const stmdev_ctx_t *ctx, + ism330bx_mlc_data_rate_t val) +{ + ism330bx_mlc_odr_t mlc_odr; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_MLC_ODR, (uint8_t *)&mlc_odr, 1); + } + + if (ret == 0) + { + mlc_odr.mlc_odr = (uint8_t)val & 0x07U; + ret = ism330bx_write_reg(ctx, ISM330BX_MLC_ODR, (uint8_t *)&mlc_odr, 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Machine Learning Core Output Data Rate (ODR) configuration.[get] + * + * @param ctx read / write interface definitions + * @param val MLC_15Hz, MLC_30Hz, MLC_60Hz, MLC_120Hz, MLC_240Hz, MLC_480Hz, MLC_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_mlc_data_rate_get(const stmdev_ctx_t *ctx, + ism330bx_mlc_data_rate_t *val) +{ + ism330bx_mlc_odr_t mlc_odr; + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_MLC_ODR, (uint8_t *)&mlc_odr, 1); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + + switch (mlc_odr.mlc_odr) + { + case ISM330BX_MLC_15Hz: + *val = ISM330BX_MLC_15Hz; + break; + + case ISM330BX_MLC_30Hz: + *val = ISM330BX_MLC_30Hz; + break; + + case ISM330BX_MLC_60Hz: + *val = ISM330BX_MLC_60Hz; + break; + + case ISM330BX_MLC_120Hz: + *val = ISM330BX_MLC_120Hz; + break; + + case ISM330BX_MLC_240Hz: + *val = ISM330BX_MLC_240Hz; + break; + + case ISM330BX_MLC_480Hz: + *val = ISM330BX_MLC_480Hz; + break; + + case ISM330BX_MLC_960Hz: + *val = ISM330BX_MLC_960Hz; + break; + + default: + *val = ISM330BX_MLC_15Hz; + break; + } + return ret; +} + +/** + * @brief Output value of all MLC decision trees.[get] + * + * @param ctx read / write interface definitions + * @param val Output value of all MLC decision trees. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_mlc_out_get(const stmdev_ctx_t *ctx, ism330bx_mlc_out_t *val) +{ + int32_t ret; + + ret = ism330bx_mem_bank_set(ctx, ISM330BX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_MLC1_SRC, (uint8_t *)&val, 4); + } + + ret += ism330bx_mem_bank_set(ctx, ISM330BX_MAIN_MEM_BANK); + return ret; +} + +/** + * @brief Qvar sensor sensitivity value register for the Machine Learning Core. + * This register corresponds to the conversion value of the Qvar sensor. + * The register value is expressed as half-precision floating-point format: + * SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set] + * + * @param ctx read / write interface definitions + * @param val Qvar sensor sensitivity value register for the Machine Learning Core. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_mlc_qvar_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = ism330bx_ln_pg_write(ctx, ISM330BX_MLC_QVAR_SENSITIVITY_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief Qvar sensor sensitivity value register for the Machine Learning Core. + * This register corresponds to the conversion value of the Qvar sensor. + * The register value is expressed as half-precision floating-point format: + * SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get] + * + * @param ctx read / write interface definitions + * @param val Qvar sensor sensitivity value register for the Machine Learning Core. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_mlc_qvar_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = ism330bx_ln_pg_read(ctx, ISM330BX_MLC_QVAR_SENSITIVITY_L, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @addtogroup Accelerometer user offset correction + * @brief This section group all the functions concerning the + * usage of Accelerometer user offset correction + * @{ + * + */ + +/** + * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[set] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_xl_offset_on_out_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_ctrl9_t ctrl9; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.usr_off_on_out = val; + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[get] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_ctrl9_t ctrl9; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.usr_off_on_out; + + return ret; +} + +/** + * @brief Accelerometer user offset correction values in mg.[set] + * + * @param ctx read / write interface definitions + * @param val Accelerometer user offset correction values in mg. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_xl_offset_mg_set(const stmdev_ctx_t *ctx, + ism330bx_xl_offset_mg_t val) +{ + ism330bx_z_ofs_usr_t z_ofs_usr; + ism330bx_y_ofs_usr_t y_ofs_usr; + ism330bx_x_ofs_usr_t x_ofs_usr; + ism330bx_ctrl9_t ctrl9; + int32_t ret; + float_t tmp; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + } + + + if ((val.x_mg < (0.0078125f * 127.0f)) && (val.x_mg > (0.0078125f * -127.0f)) && + (val.y_mg < (0.0078125f * 127.0f)) && (val.y_mg > (0.0078125f * -127.0f)) && + (val.z_mg < (0.0078125f * 127.0f)) && (val.z_mg > (0.0078125f * -127.0f))) + { + ctrl9.usr_off_w = 0; + + tmp = val.z_mg / 0.0078125f; + z_ofs_usr.z_ofs_usr = (uint8_t)tmp; + + tmp = val.y_mg / 0.0078125f; + y_ofs_usr.y_ofs_usr = (uint8_t)tmp; + + tmp = val.x_mg / 0.0078125f; + x_ofs_usr.x_ofs_usr = (uint8_t)tmp; + } + else if ((val.x_mg < (0.125f * 127.0f)) && (val.x_mg > (0.125f * -127.0f)) && + (val.y_mg < (0.125f * 127.0f)) && (val.y_mg > (0.125f * -127.0f)) && + (val.z_mg < (0.125f * 127.0f)) && (val.z_mg > (0.125f * -127.0f))) + { + ctrl9.usr_off_w = 1; + + tmp = val.z_mg / 0.125f; + z_ofs_usr.z_ofs_usr = (uint8_t)tmp; + + tmp = val.y_mg / 0.125f; + y_ofs_usr.y_ofs_usr = (uint8_t)tmp; + + tmp = val.x_mg / 0.125f; + x_ofs_usr.x_ofs_usr = (uint8_t)tmp; + } + else // out of limit + { + ctrl9.usr_off_w = 1; + z_ofs_usr.z_ofs_usr = 0xFFU; + y_ofs_usr.y_ofs_usr = 0xFFU; + x_ofs_usr.x_ofs_usr = 0xFFU; + } + + if (ret == 0) + { + ret = ism330bx_write_reg(ctx, ISM330BX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + } + if (ret == 0) + { + ret = ism330bx_write_reg(ctx, ISM330BX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + } + if (ret == 0) + { + ret = ism330bx_write_reg(ctx, ISM330BX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + } + if (ret == 0) + { + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + } + return ret; +} + +/** + * @brief Accelerometer user offset correction values in mg.[get] + * + * @param ctx read / write interface definitions + * @param val Accelerometer user offset correction values in mg. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_xl_offset_mg_get(const stmdev_ctx_t *ctx, + ism330bx_xl_offset_mg_t *val) +{ + ism330bx_z_ofs_usr_t z_ofs_usr; + ism330bx_y_ofs_usr_t y_ofs_usr; + ism330bx_x_ofs_usr_t x_ofs_usr; + ism330bx_ctrl9_t ctrl9; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + } + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + } + + if (ctrl9.usr_off_w == PROPERTY_DISABLE) + { + val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.0078125f); + val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.0078125f); + val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.0078125f); + } + else + { + val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.125f); + val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.125f); + val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.125f); + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @addtogroup AH_QVAR + * @brief This section group all the functions concerning the + * usage of AH_QVAR + * @{ + * + */ + +/** + * @brief Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are + * connected to the AH1/Qvar1 and AH1/Qvar2 pins. Before setting this bit to 1, + * the accelerometer and gyroscope sensor have to be configured in power-down mode.[set] + * + * @param ctx read / write interface definitions + * @param val 1: Enables AH_QVAR chain, 0: Disable the AH_QVAR chain + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_ah_qvar_mode_set(const stmdev_ctx_t *ctx, + ism330bx_ah_qvar_mode_t val) +{ + ism330bx_ctrl10_t ctrl10; + ism330bx_ctrl7_t ctrl7; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1); + } + + if (ret == 0) + { + if ((val.ah_qvar1_en | val.ah_qvar2_en) == PROPERTY_ENABLE) + { + ctrl7.ah_qvar_en = PROPERTY_ENABLE; + } + else + { + ctrl7.ah_qvar_en = PROPERTY_DISABLE; + } + ctrl7.ah_qvar1_en = val.ah_qvar1_en; + ctrl7.ah_qvar2_en = val.ah_qvar2_en; + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1); + } + if (ret == 0) + { + ctrl10.ah_qvar_sw = val.swaps; + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1); + } + return ret; +} + +/** + * @brief Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are + * connected to the AH1/Qvar1 and AH1/Qvar2 pins. Before setting this bit to 1, + * the accelerometer and gyroscope sensor have to be configured in power-down mode.[get] + * + * @param ctx read / write interface definitions + * @param val 1: Enables AH_QVAR chain, 0: Disable the AH_QVAR chain + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_ah_qvar_mode_get(const stmdev_ctx_t *ctx, + ism330bx_ah_qvar_mode_t *val) +{ + ism330bx_ctrl10_t ctrl10; + ism330bx_ctrl7_t ctrl7; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret == 0) + { + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL10, (uint8_t *)&ctrl10, 1); + } + + val->ah_qvar1_en = ctrl7.ah_qvar1_en; + val->ah_qvar2_en = ctrl7.ah_qvar2_en; + val->swaps = ctrl10.ah_qvar_sw; + + return ret; +} + +/** + * @brief Configures the equivalent input impedance of the AH_QVAR buffers.[set] + * + * @param ctx read / write interface definitions + * @param val 2400MOhm, 730MOhm, 300MOhm, 255MOhm, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_ah_qvar_zin_set(const stmdev_ctx_t *ctx, + ism330bx_ah_qvar_zin_t val) +{ + ism330bx_ctrl7_t ctrl7; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret == 0) + { + ctrl7.ah_qvar_c_zin = (uint8_t)val & 0x03U; + ret = ism330bx_write_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1); + } + + return ret; +} + +/** + * @brief Configures the equivalent input impedance of the AH_QVAR buffers.[get] + * + * @param ctx read / write interface definitions + * @param val 2400MOhm, 730MOhm, 300MOhm, 255MOhm, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_ah_qvar_zin_get(const stmdev_ctx_t *ctx, + ism330bx_ah_qvar_zin_t *val) +{ + ism330bx_ctrl7_t ctrl7; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_CTRL7, (uint8_t *)&ctrl7, 1); + switch (ctrl7.ah_qvar_c_zin) + { + case ISM330BX_2400MOhm: + *val = ISM330BX_2400MOhm; + break; + + case ISM330BX_730MOhm: + *val = ISM330BX_730MOhm; + break; + + case ISM330BX_300MOhm: + *val = ISM330BX_300MOhm; + break; + + case ISM330BX_255MOhm: + *val = ISM330BX_255MOhm; + break; + + default: + *val = ISM330BX_2400MOhm; + break; + } + return ret; +} + +/** + * @brief Qvar sensor sensitivity value register for the Finite State Machine. + * This register corresponds to the conversion value of the Qvar sensor. + * The register value is expressed as half-precision floating-point format: + * SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set] + * + * @param ctx read / write interface definitions + * @param val Qvar sensor sensitivity value register for the Finite State Machine. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fsm_qvar_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = ism330bx_ln_pg_write(ctx, ISM330BX_FSM_QVAR_SENSITIVITY_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief Qvar sensor sensitivity value register for the Finite State Machine. + * This register corresponds to the conversion value of the Qvar sensor. + * The register value is expressed as half-precision floating-point format: + * SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get] + * + * @param ctx read / write interface definitions + * @param val Qvar sensor sensitivity value register for the Finite State Machine. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_fsm_qvar_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = ism330bx_ln_pg_read(ctx, ISM330BX_FSM_QVAR_SENSITIVITY_L, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @addtogroup SenseWire (I3C) + * @brief This section group all the functions concerning the + * usage of SenseWire (I3C) + * @{ + * + */ + +/** + * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[set] + * + * @param ctx read / write interface definitions + * @param val SW_RST_DYN_ADDRESS_RST, GLOBAL_RST_, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_i3c_reset_mode_set(const stmdev_ctx_t *ctx, + ism330bx_i3c_reset_mode_t val) +{ + ism330bx_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret == 0) + { + pin_ctrl.ibhr_por_en = (uint8_t)val & 0x01U; + ret = ism330bx_write_reg(ctx, ISM330BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[get] + * + * @param ctx read / write interface definitions + * @param val SW_RST_DYN_ADDRESS_RST, GLOBAL_RST_, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_i3c_reset_mode_get(const stmdev_ctx_t *ctx, + ism330bx_i3c_reset_mode_t *val) +{ + ism330bx_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + switch (pin_ctrl.ibhr_por_en) + { + case ISM330BX_SW_RST_DYN_ADDRESS_RST: + *val = ISM330BX_SW_RST_DYN_ADDRESS_RST; + break; + + case ISM330BX_I3C_GLOBAL_RST: + *val = ISM330BX_I3C_GLOBAL_RST; + break; + + default: + *val = ISM330BX_SW_RST_DYN_ADDRESS_RST; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @addtogroup Time-Division Multiplexing (TDM) + * @brief This section group all the functions concerning the + * usage of Time-Division Multiplexing (TDM) + * @{ + * + */ + +/** + * @brief Disables pull-up on WCLK pin.[set] + * + * @param ctx read / write interface definitions + * @param val Disables pull-up on WCLK pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tdm_dis_wclk_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret == 0) + { + pin_ctrl.tdm_wclk_pu_dis = val; + ret = ism330bx_write_reg(ctx, ISM330BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Disables pull-up on WCLK pin.[get] + * + * @param ctx read / write interface definitions + * @param val Disables pull-up on WCLK pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tdm_dis_wclk_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + *val = pin_ctrl.tdm_wclk_pu_dis; + + return ret; +} + +/** + * @brief Enables pull-up on TDMout pin.[set] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on TDMout pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tdm_tdmout_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_if_cfg_t if_cfg; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.tdm_out_pu_en = val; + ret = ism330bx_write_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Enables pull-up on TDMout pin.[get] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on TDMout pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tdm_tdmout_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_if_cfg_t if_cfg; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_IF_CFG, (uint8_t *)&if_cfg, 1); + *val = if_cfg.tdm_out_pu_en; + + return ret; +} + +/** + * @brief WCLK and BCLK frequencies.[set] + * + * @param ctx read / write interface definitions + * @param val WCLK_8kHZ_1024kHz, WCLK_16kHZ_2048kHz, WCLK_8kHZ_2048kHz, WCLK_16kHZ_1024kHz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tdm_wclk_bclk_set(const stmdev_ctx_t *ctx, + ism330bx_tdm_wclk_bclk_t val) +{ + ism330bx_tdm_cfg0_t tdm_cfg0; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + if (ret == 0) + { + tdm_cfg0.tdm_wclk_bclk_sel = ((uint8_t)val & 0x4U) >> 2; + tdm_cfg0.tdm_wclk = (uint8_t)val & 0x3U; + ret = ism330bx_write_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + } + + return ret; +} + +/** + * @brief WCLK and BCLK frequencies.[get] + * + * @param ctx read / write interface definitions + * @param val WCLK_8kHZ_1024kHz, WCLK_16kHZ_2048kHz, WCLK_8kHZ_2048kHz, WCLK_16kHZ_1024kHz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tdm_wclk_bclk_get(const stmdev_ctx_t *ctx, + ism330bx_tdm_wclk_bclk_t *val) +{ + ism330bx_tdm_cfg0_t tdm_cfg0; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + switch ((tdm_cfg0.tdm_wclk_bclk_sel << 2) + tdm_cfg0.tdm_wclk) + { + case ISM330BX_WCLK_16kHZ_BCLK_2048kHz: + *val = ISM330BX_WCLK_16kHZ_BCLK_2048kHz; + break; + + case ISM330BX_WCLK_8kHZ_BCLK_2048kHz: + *val = ISM330BX_WCLK_8kHZ_BCLK_2048kHz; + break; + + default: + *val = ISM330BX_WCLK_8kHZ_BCLK_2048kHz; + break; + } + return ret; +} + +/** + * @brief Selection of TDM slot for transmission.[set] + * + * @param ctx read / write interface definitions + * @param val SLOT_012, SLOT_456, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tdm_slot_set(const stmdev_ctx_t *ctx, ism330bx_tdm_slot_t val) +{ + ism330bx_tdm_cfg0_t tdm_cfg0; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + if (ret == 0) + { + tdm_cfg0.tdm_slot_sel = (uint8_t)val & 0x01U; + ret = ism330bx_write_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + } + + return ret; +} + +/** + * @brief Selection of TDM slot for transmission.[get] + * + * @param ctx read / write interface definitions + * @param val SLOT_012, SLOT_456, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tdm_slot_get(const stmdev_ctx_t *ctx, ism330bx_tdm_slot_t *val) +{ + ism330bx_tdm_cfg0_t tdm_cfg0; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + switch (tdm_cfg0.tdm_slot_sel) + { + case ISM330BX_SLOT_012: + *val = ISM330BX_SLOT_012; + break; + + case ISM330BX_SLOT_456: + *val = ISM330BX_SLOT_456; + break; + + default: + *val = ISM330BX_SLOT_012; + break; + } + return ret; +} + +/** + * @brief BCLK edge selection for TDM interface.[set] + * + * @param ctx read / write interface definitions + * @param val BCLK_RISING, BCLK_FALLING, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tdm_bclk_edge_set(const stmdev_ctx_t *ctx, + ism330bx_tdm_bclk_edge_t val) +{ + ism330bx_tdm_cfg0_t tdm_cfg0; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + if (ret == 0) + { + tdm_cfg0.tdm_bclk_edge_sel = (uint8_t)val & 0x01U; + ret = ism330bx_write_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + } + + return ret; +} + +/** + * @brief BCLK edge selection for TDM interface.[get] + * + * @param ctx read / write interface definitions + * @param val BCLK_RISING, BCLK_FALLING, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tdm_bclk_edge_get(const stmdev_ctx_t *ctx, + ism330bx_tdm_bclk_edge_t *val) +{ + ism330bx_tdm_cfg0_t tdm_cfg0; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + switch (tdm_cfg0.tdm_bclk_edge_sel) + { + case ISM330BX_BCLK_RISING: + *val = ISM330BX_BCLK_RISING; + break; + + case ISM330BX_BCLK_FALLING: + *val = ISM330BX_BCLK_FALLING; + break; + + default: + *val = ISM330BX_BCLK_RISING; + break; + } + return ret; +} + +/** + * @brief Enables TDM delayed configuration.[set] + * + * @param ctx read / write interface definitions + * @param val Enables TDM delayed configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tdm_delayed_conf_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + ism330bx_tdm_cfg0_t tdm_cfg0; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + if (ret == 0) + { + tdm_cfg0.tdm_delayed_cfg = val; + ret = ism330bx_write_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + } + + return ret; +} + +/** + * @brief Enables TDM delayed configuration.[get] + * + * @param ctx read / write interface definitions + * @param val Enables TDM delayed configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tdm_delayed_conf_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + ism330bx_tdm_cfg0_t tdm_cfg0; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + *val = tdm_cfg0.tdm_delayed_cfg; + + return ret; +} + + +/** + * @brief Selects order of transmission of TDM axes.[set] + * + * @param ctx read / write interface definitions + * @param val TDM_ORDER_ZYX, TDM_ORDER_XZY, TDM_ORDER_XYZ, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tdm_axis_order_set(const stmdev_ctx_t *ctx, + ism330bx_tdm_axis_order_t val) +{ + ism330bx_tdm_cfg1_t tdm_cfg1; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1); + if (ret == 0) + { + tdm_cfg1.tdm_axes_ord_sel = (uint8_t)val & 0x03U; + ret = ism330bx_write_reg(ctx, ISM330BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1); + } + + return ret; +} + +/** + * @brief Selects order of transmission of TDM axes.[get] + * + * @param ctx read / write interface definitions + * @param val TDM_ORDER_ZYX, TDM_ORDER_XZY, TDM_ORDER_XYZ, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tdm_axis_order_get(const stmdev_ctx_t *ctx, + ism330bx_tdm_axis_order_t *val) +{ + ism330bx_tdm_cfg1_t tdm_cfg1; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1); + switch (tdm_cfg1.tdm_axes_ord_sel) + { + case ISM330BX_TDM_ORDER_ZYX: + *val = ISM330BX_TDM_ORDER_ZYX; + break; + + case ISM330BX_TDM_ORDER_XZY: + *val = ISM330BX_TDM_ORDER_XZY; + break; + + case ISM330BX_TDM_ORDER_XYZ: + *val = ISM330BX_TDM_ORDER_XYZ; + break; + + default: + *val = ISM330BX_TDM_ORDER_ZYX; + break; + } + return ret; +} + +/** + * @brief TDM channel accelerometer full-scale selection.[set] + * + * @param ctx read / write interface definitions + * @param val TDM_2g, TDM_4g, TDM_8g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tdm_xl_full_scale_set(const stmdev_ctx_t *ctx, + ism330bx_tdm_xl_full_scale_t val) +{ + ism330bx_tdm_cfg2_t tdm_cfg2; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1); + if (ret == 0) + { + tdm_cfg2.tdm_fs_xl = (uint8_t)val & 0x3U; + ret = ism330bx_write_reg(ctx, ISM330BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1); + } + + return ret; +} + +/** + * @brief TDM channel accelerometer full-scale selection.[get] + * + * @param ctx read / write interface definitions + * @param val TDM_2g, TDM_4g, TDM_8g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t ism330bx_tdm_xl_full_scale_get(const stmdev_ctx_t *ctx, + ism330bx_tdm_xl_full_scale_t *val) +{ + ism330bx_tdm_cfg2_t tdm_cfg2; + int32_t ret; + + ret = ism330bx_read_reg(ctx, ISM330BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1); + switch (tdm_cfg2.tdm_fs_xl) + { + case ISM330BX_TDM_2g: + *val = ISM330BX_TDM_2g; + break; + + case ISM330BX_TDM_4g: + *val = ISM330BX_TDM_4g; + break; + + case ISM330BX_TDM_8g: + *val = ISM330BX_TDM_8g; + break; + + default: + *val = ISM330BX_TDM_2g; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @} + * + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ism330bx_STdC/driver/ism330bx_reg.h b/sensor/stmemsc/ism330bx_STdC/driver/ism330bx_reg.h new file mode 100644 index 00000000..4382dee4 --- /dev/null +++ b/sensor/stmemsc/ism330bx_STdC/driver/ism330bx_reg.h @@ -0,0 +1,3738 @@ +/** + ****************************************************************************** + * @file ism330bx_reg.h + * @author Sensors Software Solution Team + * @brief This file contains all the functions prototypes for the + * ism330bx_reg.c driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2024 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef ISM330BX_REGS_H +#define ISM330BX_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include + +/** @addtogroup ISM330BX + * @{ + * + */ + +/** @defgroup Endianness definitions + * @{ + * + */ + +#ifndef DRV_BYTE_ORDER +#ifndef __BYTE_ORDER__ + +#define DRV_LITTLE_ENDIAN 1234 +#define DRV_BIG_ENDIAN 4321 + +/** if _BYTE_ORDER is not defined, choose the endianness of your architecture + * by uncommenting the define which fits your platform endianness + */ +//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN +#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN + +#else /* defined __BYTE_ORDER__ */ + +#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ +#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ +#define DRV_BYTE_ORDER __BYTE_ORDER__ + +#endif /* __BYTE_ORDER__*/ +#endif /* DRV_BYTE_ORDER */ + +/** + * @} + * + */ + +/** @defgroup STMicroelectronics sensors common types + * @{ + * + */ + +#ifndef MEMS_SHARED_TYPES +#define MEMS_SHARED_TYPES + +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} bitwise_t; + +#define PROPERTY_DISABLE (0U) +#define PROPERTY_ENABLE (1U) + +/** @addtogroup Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); +typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); + +typedef struct +{ + /** Component mandatory fields **/ + stmdev_write_ptr write_reg; + stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; + /** Customizable optional pointer **/ + void *handle; +} stmdev_ctx_t; + +/** + * @} + * + */ + +#endif /* MEMS_SHARED_TYPES */ + +#ifndef MEMS_UCF_SHARED_TYPES +#define MEMS_UCF_SHARED_TYPES + +/** @defgroup Generic address-data structure definition + * @brief This structure is useful to load a predefined configuration + * of a sensor. + * You can create a sensor configuration by your own or using + * Unico / Unicleo tools available on STMicroelectronics + * web site. + * + * @{ + * + */ + +typedef struct +{ + uint8_t address; + uint8_t data; +} ucf_line_t; + +/** + * @} + * + */ + +#endif /* MEMS_UCF_SHARED_TYPES */ + +/** + * @} + * + */ + +/** @defgroup ISM330BX_Infos + * @{ + * + */ + +/** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ +#define ISM330BX_I2C_ADD_L 0xD5U +#define ISM330BX_I2C_ADD_H 0xD7U + +/** Device Identification (Who am I) **/ +#define ISM330BX_ID 0x71U + +/** + * @} + * + */ + +/** @defgroup bitfields page main + * @{ + * + */ + +#define ISM330BX_FUNC_CFG_ACCESS 0x1U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t sw_por : 1; + uint8_t fsm_wr_ctrl_en : 1; + uint8_t not_used1 : 3; + uint8_t emb_func_reg_access : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_reg_access : 1; + uint8_t not_used1 : 3; + uint8_t fsm_wr_ctrl_en : 1; + uint8_t sw_por : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_func_cfg_access_t; + +#define ISM330BX_PIN_CTRL 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 5; + uint8_t ibhr_por_en : 1; + uint8_t sdo_pu_en : 1; + uint8_t tdm_wclk_pu_dis : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tdm_wclk_pu_dis : 1; + uint8_t sdo_pu_en : 1; + uint8_t ibhr_por_en : 1; + uint8_t not_used0 : 5; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_pin_ctrl_t; + +#define ISM330BX_IF_CFG 0x3U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t i2c_i3c_disable : 1; + uint8_t not_used0 : 1; + uint8_t sim : 1; + uint8_t pp_od : 1; + uint8_t h_lactive : 1; + uint8_t asf_ctrl : 1; + uint8_t tdm_out_pu_en : 1; + uint8_t sda_pu_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sda_pu_en : 1; + uint8_t tdm_out_pu_en : 1; + uint8_t asf_ctrl : 1; + uint8_t h_lactive : 1; + uint8_t pp_od : 1; + uint8_t sim : 1; + uint8_t not_used0 : 1; + uint8_t i2c_i3c_disable : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_if_cfg_t; + +#define ISM330BX_FIFO_CTRL1 0x7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wtm : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t wtm : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fifo_ctrl1_t; + +#define ISM330BX_FIFO_CTRL2 0x8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xl_dualc_batch_from_fsm : 1; + uint8_t uncompr_rate : 2; + uint8_t not_used0 : 1; + uint8_t odr_chg_en : 1; + uint8_t not_used1 : 1; + uint8_t fifo_compr_rt_en : 1; + uint8_t stop_on_wtm : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t stop_on_wtm : 1; + uint8_t fifo_compr_rt_en : 1; + uint8_t not_used1 : 1; + uint8_t odr_chg_en : 1; + uint8_t not_used0 : 1; + uint8_t uncompr_rate : 2; + uint8_t xl_dualc_batch_from_fsm : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fifo_ctrl2_t; + +#define ISM330BX_FIFO_CTRL3 0x9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bdr_xl : 4; + uint8_t bdr_gy : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bdr_gy : 4; + uint8_t bdr_xl : 4; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fifo_ctrl3_t; + +#define ISM330BX_FIFO_CTRL4 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_mode : 3; + uint8_t not_used0 : 1; + uint8_t odr_t_batch : 2; + uint8_t dec_ts_batch : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dec_ts_batch : 2; + uint8_t odr_t_batch : 2; + uint8_t not_used0 : 1; + uint8_t fifo_mode : 3; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fifo_ctrl4_t; + +#define ISM330BX_COUNTER_BDR_REG1 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t cnt_bdr_th : 2; + uint8_t ah_qvar_batch_en : 1; + uint8_t not_used0 : 2; + uint8_t trig_counter_bdr : 2; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t trig_counter_bdr : 2; + uint8_t not_used0 : 2; + uint8_t ah_qvar_batch_en : 1; + uint8_t cnt_bdr_th : 2; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_counter_bdr_reg1_t; + +#define ISM330BX_COUNTER_BDR_REG2 0x0CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t cnt_bdr_th : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t cnt_bdr_th : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_counter_bdr_reg2_t; + +#define ISM330BX_INT1_CTRL 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_drdy_xl : 1; + uint8_t int1_drdy_g : 1; + uint8_t not_used0 : 1; + uint8_t int1_fifo_th : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_fifo_full : 1; + uint8_t int1_cnt_bdr : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t int1_cnt_bdr : 1; + uint8_t int1_fifo_full : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_fifo_th : 1; + uint8_t not_used0 : 1; + uint8_t int1_drdy_g : 1; + uint8_t int1_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_int1_ctrl_t; + +#define ISM330BX_INT2_CTRL 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_drdy_xl : 1; + uint8_t int2_drdy_g : 1; + uint8_t not_used0 : 1; + uint8_t int2_fifo_th : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_fifo_full : 1; + uint8_t int2_cnt_bdr : 1; + uint8_t int2_emb_func_endop : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_emb_func_endop : 1; + uint8_t int2_cnt_bdr : 1; + uint8_t int2_fifo_full : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_fifo_th : 1; + uint8_t not_used0 : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_int2_ctrl_t; + +#define ISM330BX_WHO_AM_I 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t id : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t id : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_who_am_i_t; + +#define ISM330BX_CTRL1 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t odr_xl : 4; + uint8_t op_mode_xl : 3; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t op_mode_xl : 3; + uint8_t odr_xl : 4; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_ctrl1_t; + +#define ISM330BX_CTRL2 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t odr_g : 4; + uint8_t op_mode_g : 3; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t op_mode_g : 3; + uint8_t odr_g : 4; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_ctrl2_t; + +#define ISM330BX_CTRL3 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sw_reset : 1; + uint8_t not_used0 : 1; + uint8_t if_inc : 1; + uint8_t not_used1 : 3; + uint8_t bdu : 1; + uint8_t boot : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t boot : 1; + uint8_t bdu : 1; + uint8_t not_used1 : 3; + uint8_t if_inc : 1; + uint8_t not_used0 : 1; + uint8_t sw_reset : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_ctrl3_t; + +#define ISM330BX_CTRL4 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used1 : 1; + uint8_t drdy_pulsed : 1; + uint8_t int2_drdy_temp : 1; + uint8_t drdy_mask : 1; + uint8_t int2_on_int1 : 1; + uint8_t not_used0 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 3; + uint8_t int2_on_int1 : 1; + uint8_t drdy_mask : 1; + uint8_t int2_drdy_temp : 1; + uint8_t drdy_pulsed : 1; + uint8_t not_used1 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_ctrl4_t; + +#define ISM330BX_CTRL5 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int_en_i3c : 1; + uint8_t bus_act_sel : 2; + uint8_t not_used0 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 5; + uint8_t bus_act_sel : 2; + uint8_t int_en_i3c : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_ctrl5_t; + +#define ISM330BX_CTRL6 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_g : 4; + uint8_t lpf1_g_bw : 3; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t lpf1_g_bw : 3; + uint8_t fs_g : 4; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_ctrl6_t; + +#define ISM330BX_CTRL7 0x16U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t lpf1_g_en : 1; + uint8_t not_used0 : 1; + uint8_t ah_qvar2_en : 1; + uint8_t ah_qvar1_en : 1; + uint8_t ah_qvar_c_zin : 2; + uint8_t int2_drdy_ah_qvar : 1; + uint8_t ah_qvar_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ah_qvar_en : 1; + uint8_t int2_drdy_ah_qvar : 1; + uint8_t ah_qvar_c_zin : 2; + uint8_t ah_qvar1_en : 1; + uint8_t ah_qvar2_en : 1; + uint8_t not_used0 : 1; + uint8_t lpf1_g_en : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_ctrl7_t; + +#define ISM330BX_CTRL8 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_xl : 2; + uint8_t not_used0 : 1; + uint8_t xl_dualc_en : 1; + uint8_t ah_qvar_hpf : 1; + uint8_t hp_lpf2_xl_bw : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t hp_lpf2_xl_bw : 3; + uint8_t ah_qvar_hpf : 1; + uint8_t xl_dualc_en : 1; + uint8_t not_used0 : 1; + uint8_t fs_xl : 2; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_ctrl8_t; + +#define ISM330BX_CTRL9 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t usr_off_on_out : 1; + uint8_t usr_off_w : 1; + uint8_t not_used0 : 1; + uint8_t lpf2_xl_en : 1; + uint8_t hp_slope_xl_en : 1; + uint8_t xl_fastsettl_mode : 1; + uint8_t hp_ref_mode_xl : 1; + uint8_t ah_qvar_lpf : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ah_qvar_lpf : 1; + uint8_t hp_ref_mode_xl : 1; + uint8_t xl_fastsettl_mode : 1; + uint8_t hp_slope_xl_en : 1; + uint8_t lpf2_xl_en : 1; + uint8_t not_used0 : 1; + uint8_t usr_off_w : 1; + uint8_t usr_off_on_out : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_ctrl9_t; + +#define ISM330BX_CTRL10 0x19U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t st_xl : 2; + uint8_t st_g : 2; + uint8_t xl_st_offset : 1; + uint8_t ah_qvar_sw : 1; + uint8_t emb_func_debug : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t emb_func_debug : 1; + uint8_t ah_qvar_sw : 1; + uint8_t xl_st_offset : 1; + uint8_t st_g : 2; + uint8_t st_xl : 2; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_ctrl10_t; + +#define ISM330BX_CTRL_STATUS 0x1AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t fsm_wr_ctrl_status : 1; + uint8_t not_used1 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 5; + uint8_t fsm_wr_ctrl_status : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_ctrl_status_t; + +#define ISM330BX_FIFO_STATUS1 0x1BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t diff_fifo : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t diff_fifo : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fifo_status1_t; + +#define ISM330BX_FIFO_STATUS2 0x1CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t diff_fifo : 1; + uint8_t not_used0 : 2; + uint8_t fifo_ovr_latched : 1; + uint8_t counter_bdr_ia : 1; + uint8_t fifo_full_ia : 1; + uint8_t fifo_ovr_ia : 1; + uint8_t fifo_wtm_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_wtm_ia : 1; + uint8_t fifo_ovr_ia : 1; + uint8_t fifo_full_ia : 1; + uint8_t counter_bdr_ia : 1; + uint8_t fifo_ovr_latched : 1; + uint8_t not_used0 : 2; + uint8_t diff_fifo : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fifo_status2_t; + +#define ISM330BX_ALL_INT_SRC 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ia : 1; + uint8_t wu_ia : 1; + uint8_t tap_ia : 1; + uint8_t not_used0 : 1; + uint8_t d6d_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t not_used1 : 1; + uint8_t emb_func_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_ia : 1; + uint8_t not_used1 : 1; + uint8_t sleep_change_ia : 1; + uint8_t d6d_ia : 1; + uint8_t not_used0 : 1; + uint8_t tap_ia : 1; + uint8_t wu_ia : 1; + uint8_t ff_ia : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_all_int_src_t; + +#define ISM330BX_STATUS_REG 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xlda : 1; + uint8_t gda : 1; + uint8_t tda : 1; + uint8_t ah_qvarda : 1; + uint8_t not_used0 : 3; + uint8_t timestamp_endcount : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp_endcount : 1; + uint8_t not_used0 : 3; + uint8_t ah_qvarda : 1; + uint8_t tda : 1; + uint8_t gda : 1; + uint8_t xlda : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_status_reg_t; + +#define ISM330BX_OUT_TEMP_L 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_out_temp_l_t; + +#define ISM330BX_OUT_TEMP_H 0x21U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_out_temp_h_t; + +#define ISM330BX_OUTX_L_G 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_g : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_outx_l_g_t; + +#define ISM330BX_OUTX_H_G 0x23U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_g : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_outx_h_g_t; + +#define ISM330BX_OUTY_L_G 0x24U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_g : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_outy_l_g_t; + +#define ISM330BX_OUTY_H_G 0x25U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_g : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_outy_h_g_t; + +#define ISM330BX_OUTZ_L_G 0x26U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_g : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_outz_l_g_t; + +#define ISM330BX_OUTZ_H_G 0x27U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_g : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_outz_h_g_t; + +#define ISM330BX_OUTZ_L_A 0x28U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_a : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_outz_l_a_t; + +#define ISM330BX_OUTZ_H_A 0x29U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_a : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_outz_h_a_t; + +#define ISM330BX_OUTY_L_A 0x2AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_a : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_outy_l_a_t; + +#define ISM330BX_OUTY_H_A 0x2BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_a : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_outy_h_a_t; + +#define ISM330BX_OUTX_L_A 0x2CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_a : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_outx_l_a_t; + +#define ISM330BX_OUTX_H_A 0x2DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_a : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_outx_h_a_t; + +#define ISM330BX_UI_OUTZ_L_A_DUALC 0x34U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outz_a_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outz_a_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_ui_outz_l_a_dualc_t; + +#define ISM330BX_UI_OUTZ_H_A_DUALC 0x35U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outz_a_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outz_a_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_ui_outz_h_a_dualc_t; + +#define ISM330BX_UI_OUTY_L_A_DUALC 0x36U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outy_a_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outy_a_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_ui_outy_l_a_dualc_t; + +#define ISM330BX_UI_OUTY_H_A_DUALC 0x37U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outy_a_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outy_a_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_ui_outy_h_a_dualc_t; + +#define ISM330BX_UI_OUTX_L_A_DUALC 0x38U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outx_a_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outx_a_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_ui_outx_l_a_dualc_t; + +#define ISM330BX_UI_OUTX_H_A_DUALC 0x39U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outx_a_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outx_a_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_ui_outx_h_a_dualc_t; + +#define ISM330BX_AH_QVAR_OUT_L 0x3AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ah_qvar : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ah_qvar : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_ah_qvar_out_l_t; + +#define ISM330BX_AH_QVAR_OUT_H 0x3BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ah_qvar : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ah_qvar : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_ah_qvar_out_h_t; + +#define ISM330BX_TIMESTAMP0 0x40U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_timestamp0_t; + +#define ISM330BX_TIMESTAMP1 0x41U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_timestamp1_t; + +#define ISM330BX_TIMESTAMP2 0x42U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_timestamp2_t; + +#define ISM330BX_TIMESTAMP3 0x43U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_timestamp3_t; + +#define ISM330BX_WAKE_UP_SRC 0x45U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t x_wu : 1; + uint8_t y_wu : 1; + uint8_t z_wu : 1; + uint8_t wu_ia : 1; + uint8_t sleep_state : 1; + uint8_t ff_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t sleep_change_ia : 1; + uint8_t ff_ia : 1; + uint8_t sleep_state : 1; + uint8_t wu_ia : 1; + uint8_t z_wu : 1; + uint8_t y_wu : 1; + uint8_t x_wu : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_wake_up_src_t; + +#define ISM330BX_TAP_SRC 0x46U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t x_tap : 1; + uint8_t y_tap : 1; + uint8_t z_tap : 1; + uint8_t tap_sign : 1; + uint8_t not_used0 : 1; + uint8_t double_tap : 1; + uint8_t single_tap : 1; + uint8_t tap_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tap_ia : 1; + uint8_t single_tap : 1; + uint8_t double_tap : 1; + uint8_t not_used0 : 1; + uint8_t tap_sign : 1; + uint8_t z_tap : 1; + uint8_t y_tap : 1; + uint8_t x_tap : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_tap_src_t; + +#define ISM330BX_D6D_SRC 0x47U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t zl : 1; + uint8_t zh : 1; + uint8_t yl : 1; + uint8_t yh : 1; + uint8_t xl : 1; + uint8_t xh : 1; + uint8_t d6d_ia : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t d6d_ia : 1; + uint8_t xh : 1; + uint8_t xl : 1; + uint8_t yh : 1; + uint8_t yl : 1; + uint8_t zh : 1; + uint8_t zl : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_d6d_src_t; + +#define ISM330BX_EMB_FUNC_STATUS_MAINPAGE 0x49U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t is_step_det : 1; + uint8_t is_tilt : 1; + uint8_t is_sigmot : 1; + uint8_t not_used1 : 1; + uint8_t is_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t is_sigmot : 1; + uint8_t is_tilt : 1; + uint8_t is_step_det : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_emb_func_status_mainpage_t; + +#define ISM330BX_FSM_STATUS_MAINPAGE 0x4AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm8 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fsm_status_mainpage_t; + +#define ISM330BX_MLC_STATUS_MAINPAGE 0x4BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_mlc1 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t is_mlc4 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_mlc_status_mainpage_t; + +#define ISM330BX_INTERNAL_FREQ 0x4FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t freq_fine : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t freq_fine : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_internal_freq_t; + +#define ISM330BX_FUNCTIONS_ENABLE 0x50U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t inact_en : 2; + uint8_t not_used0 : 1; + uint8_t dis_rst_lir_all_int : 1; + uint8_t not_used1 : 2; + uint8_t timestamp_en : 1; + uint8_t interrupts_enable : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t interrupts_enable : 1; + uint8_t timestamp_en : 1; + uint8_t not_used1 : 2; + uint8_t dis_rst_lir_all_int : 1; + uint8_t not_used0 : 1; + uint8_t inact_en : 2; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_functions_enable_t; + +#define ISM330BX_INACTIVITY_DUR 0x54U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t inact_dur : 2; + uint8_t xl_inact_odr : 2; + uint8_t wu_inact_ths_w : 3; + uint8_t sleep_status_on_int : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sleep_status_on_int : 1; + uint8_t wu_inact_ths_w : 3; + uint8_t xl_inact_odr : 2; + uint8_t inact_dur : 2; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_inactivity_dur_t; + +#define ISM330BX_INACTIVITY_THS 0x55U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t inact_ths : 6; + uint8_t not_used0 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 2; + uint8_t inact_ths : 6; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_inactivity_ths_t; + +#define ISM330BX_TAP_CFG0 0x56U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t lir : 1; + uint8_t tap_x_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_z_en : 1; + uint8_t slope_fds : 1; + uint8_t hw_func_mask_xl_settl : 1; + uint8_t low_pass_on_6d : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t low_pass_on_6d : 1; + uint8_t hw_func_mask_xl_settl : 1; + uint8_t slope_fds : 1; + uint8_t tap_z_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_x_en : 1; + uint8_t lir : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_tap_cfg0_t; + +#define ISM330BX_TAP_CFG1 0x57U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths_z : 5; + uint8_t tap_priority : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tap_priority : 3; + uint8_t tap_ths_z : 5; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_tap_cfg1_t; + +#define ISM330BX_TAP_CFG2 0x58U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths_y : 5; + uint8_t not_used0 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 3; + uint8_t tap_ths_y : 5; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_tap_cfg2_t; + +#define ISM330BX_TAP_THS_6D 0x59U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths_x : 5; + uint8_t sixd_ths : 2; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t sixd_ths : 2; + uint8_t tap_ths_x : 5; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_tap_ths_6d_t; + +#define ISM330BX_TAP_DUR 0x5AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t shock : 2; + uint8_t quiet : 2; + uint8_t dur : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dur : 4; + uint8_t quiet : 2; + uint8_t shock : 2; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_tap_dur_t; + +#define ISM330BX_WAKE_UP_THS 0x5BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wk_ths : 6; + uint8_t usr_off_on_wu : 1; + uint8_t single_double_tap : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t single_double_tap : 1; + uint8_t usr_off_on_wu : 1; + uint8_t wk_ths : 6; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_wake_up_ths_t; + +#define ISM330BX_WAKE_UP_DUR 0x5CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sleep_dur : 4; + uint8_t not_used0 : 1; + uint8_t wake_dur : 2; + uint8_t ff_dur : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 1; + uint8_t wake_dur : 2; + uint8_t not_used0 : 1; + uint8_t sleep_dur : 4; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_wake_up_dur_t; + +#define ISM330BX_FREE_FALL 0x5DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ths : 3; + uint8_t ff_dur : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 5; + uint8_t ff_ths : 3; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_free_fall_t; + +#define ISM330BX_MD1_CFG 0x5EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t int1_emb_func : 1; + uint8_t int1_6d : 1; + uint8_t int1_double_tap : 1; + uint8_t int1_ff : 1; + uint8_t int1_wu : 1; + uint8_t int1_single_tap : 1; + uint8_t int1_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_sleep_change : 1; + uint8_t int1_single_tap : 1; + uint8_t int1_wu : 1; + uint8_t int1_ff : 1; + uint8_t int1_double_tap : 1; + uint8_t int1_6d : 1; + uint8_t int1_emb_func : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_md1_cfg_t; + +#define ISM330BX_MD2_CFG 0x5FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_timestamp : 1; + uint8_t int2_emb_func : 1; + uint8_t int2_6d : 1; + uint8_t int2_double_tap : 1; + uint8_t int2_ff : 1; + uint8_t int2_wu : 1; + uint8_t int2_single_tap : 1; + uint8_t int2_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_sleep_change : 1; + uint8_t int2_single_tap : 1; + uint8_t int2_wu : 1; + uint8_t int2_ff : 1; + uint8_t int2_double_tap : 1; + uint8_t int2_6d : 1; + uint8_t int2_emb_func : 1; + uint8_t int2_timestamp : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_md2_cfg_t; + +#define ISM330BX_EMB_FUNC_CFG 0x63U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t emb_func_disable : 1; + uint8_t emb_func_irq_mask_xl_settl : 1; + uint8_t emb_func_irq_mask_g_settl : 1; + uint8_t not_used1 : 1; + uint8_t xl_dualc_batch_from_if : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t xl_dualc_batch_from_if : 1; + uint8_t not_used1 : 1; + uint8_t emb_func_irq_mask_g_settl : 1; + uint8_t emb_func_irq_mask_xl_settl : 1; + uint8_t emb_func_disable : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_emb_func_cfg_t; + +#define ISM330BX_TDM_CFG0 0x6CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tdm_wclk_bclk_sel : 1; + uint8_t tdm_wclk : 2; + uint8_t not_used0 : 1; + uint8_t tdm_slot_sel : 1; + uint8_t tdm_bclk_edge_sel : 1; + uint8_t tdm_delayed_cfg : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t tdm_delayed_cfg : 1; + uint8_t tdm_bclk_edge_sel : 1; + uint8_t tdm_slot_sel : 1; + uint8_t not_used0 : 1; + uint8_t tdm_wclk : 2; + uint8_t tdm_wclk_bclk_sel : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_tdm_cfg0_t; + +#define ISM330BX_TDM_CFG1 0x6DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t tdm_axes_ord_sel : 2; + uint8_t tdm_xl_z_en : 1; + uint8_t tdm_xl_y_en : 1; + uint8_t tdm_xl_x_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tdm_xl_x_en : 1; + uint8_t tdm_xl_y_en : 1; + uint8_t tdm_xl_z_en : 1; + uint8_t tdm_axes_ord_sel : 2; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_tdm_cfg1_t; + +#define ISM330BX_TDM_CFG2 0x6EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tdm_fs_xl : 2; + uint8_t not_used0 : 1; + uint8_t tdm_data_mask : 1; + uint8_t not_used1 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 4; + uint8_t tdm_data_mask : 1; + uint8_t not_used0 : 1; + uint8_t tdm_fs_xl : 2; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_tdm_cfg2_t; + +#define ISM330BX_Z_OFS_USR 0x73U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t z_ofs_usr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t z_ofs_usr : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_z_ofs_usr_t; + +#define ISM330BX_Y_OFS_USR 0x74U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t y_ofs_usr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t y_ofs_usr : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_y_ofs_usr_t; + +#define ISM330BX_X_OFS_USR 0x75U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t x_ofs_usr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t x_ofs_usr : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_x_ofs_usr_t; + +#define ISM330BX_FIFO_DATA_OUT_TAG 0x78U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t tag_cnt : 2; + uint8_t tag_sensor : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tag_sensor : 5; + uint8_t tag_cnt : 2; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fifo_data_out_tag_t; + +#define ISM330BX_FIFO_DATA_OUT_BYTE_0 0x79U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fifo_data_out_byte_0_t; + +#define ISM330BX_FIFO_DATA_OUT_BYTE_1 0x7AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fifo_data_out_byte_1_t; + +#define ISM330BX_FIFO_DATA_OUT_BYTE_2 0x7BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fifo_data_out_byte_2_t; + +#define ISM330BX_FIFO_DATA_OUT_BYTE_3 0x7CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fifo_data_out_byte_3_t; + +#define ISM330BX_FIFO_DATA_OUT_BYTE_4 0x7DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fifo_data_out_byte_4_t; + +#define ISM330BX_FIFO_DATA_OUT_BYTE_5 0x7EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fifo_data_out_byte_5_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page embedded + * @{ + * + */ + +#define ISM330BX_PAGE_SEL 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t page_sel : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_sel : 4; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_page_sel_t; + +#define ISM330BX_EMB_FUNC_EN_A 0x4U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used2 : 1; + uint8_t sflp_game_en : 1; + uint8_t not_used0 : 1; + uint8_t pedo_en : 1; + uint8_t tilt_en : 1; + uint8_t sign_motion_en : 1; + uint8_t not_used1 : 1; + uint8_t mlc_before_fsm_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_before_fsm_en : 1; + uint8_t not_used1 : 1; + uint8_t sign_motion_en : 1; + uint8_t tilt_en : 1; + uint8_t pedo_en : 1; + uint8_t not_used0 : 1; + uint8_t sflp_game_en : 1; + uint8_t not_used2 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_emb_func_en_a_t; + +#define ISM330BX_EMB_FUNC_EN_B 0x5U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_en : 1; + uint8_t not_used0 : 2; + uint8_t fifo_compr_en : 1; + uint8_t mlc_en : 1; + uint8_t not_used1 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 3; + uint8_t mlc_en : 1; + uint8_t fifo_compr_en : 1; + uint8_t not_used0 : 2; + uint8_t fsm_en : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_emb_func_en_b_t; + +#define ISM330BX_EMB_FUNC_EXEC_STATUS 0x7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t emb_func_endop : 1; + uint8_t emb_func_exec_ovr : 1; + uint8_t not_used0 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 6; + uint8_t emb_func_exec_ovr : 1; + uint8_t emb_func_endop : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_emb_func_exec_status_t; + +#define ISM330BX_PAGE_ADDRESS 0x8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t page_addr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_addr : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_page_address_t; + +#define ISM330BX_PAGE_VALUE 0x9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t page_value : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_value : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_page_value_t; + +#define ISM330BX_EMB_FUNC_INT1 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t int1_step_detector : 1; + uint8_t int1_tilt : 1; + uint8_t int1_sig_mot : 1; + uint8_t not_used1 : 1; + uint8_t int1_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t int1_sig_mot : 1; + uint8_t int1_tilt : 1; + uint8_t int1_step_detector : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_emb_func_int1_t; + +#define ISM330BX_FSM_INT1 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_fsm1 : 1; + uint8_t int1_fsm2 : 1; + uint8_t int1_fsm3 : 1; + uint8_t int1_fsm4 : 1; + uint8_t int1_fsm5 : 1; + uint8_t int1_fsm6 : 1; + uint8_t int1_fsm7 : 1; + uint8_t int1_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm8 : 1; + uint8_t int1_fsm7 : 1; + uint8_t int1_fsm6 : 1; + uint8_t int1_fsm5 : 1; + uint8_t int1_fsm4 : 1; + uint8_t int1_fsm3 : 1; + uint8_t int1_fsm2 : 1; + uint8_t int1_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fsm_int1_t; + +#define ISM330BX_MLC_INT1 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_mlc1 : 1; + uint8_t int1_mlc2 : 1; + uint8_t int1_mlc3 : 1; + uint8_t int1_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t int1_mlc4 : 1; + uint8_t int1_mlc3 : 1; + uint8_t int1_mlc2 : 1; + uint8_t int1_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_mlc_int1_t; + +#define ISM330BX_EMB_FUNC_INT2 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t int2_step_detector : 1; + uint8_t int2_tilt : 1; + uint8_t int2_sig_mot : 1; + uint8_t not_used1 : 1; + uint8_t int2_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t int2_sig_mot : 1; + uint8_t int2_tilt : 1; + uint8_t int2_step_detector : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_emb_func_int2_t; + +#define ISM330BX_FSM_INT2 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_fsm1 : 1; + uint8_t int2_fsm2 : 1; + uint8_t int2_fsm3 : 1; + uint8_t int2_fsm4 : 1; + uint8_t int2_fsm5 : 1; + uint8_t int2_fsm6 : 1; + uint8_t int2_fsm7 : 1; + uint8_t int2_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm8 : 1; + uint8_t int2_fsm7 : 1; + uint8_t int2_fsm6 : 1; + uint8_t int2_fsm5 : 1; + uint8_t int2_fsm4 : 1; + uint8_t int2_fsm3 : 1; + uint8_t int2_fsm2 : 1; + uint8_t int2_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fsm_int2_t; + +#define ISM330BX_MLC_INT2 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_mlc1 : 1; + uint8_t int2_mlc2 : 1; + uint8_t int2_mlc3 : 1; + uint8_t int2_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t int2_mlc4 : 1; + uint8_t int2_mlc3 : 1; + uint8_t int2_mlc2 : 1; + uint8_t int2_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_mlc_int2_t; + +#define ISM330BX_EMB_FUNC_STATUS 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t is_step_det : 1; + uint8_t is_tilt : 1; + uint8_t is_sigmot : 1; + uint8_t not_used1 : 1; + uint8_t is_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t is_sigmot : 1; + uint8_t is_tilt : 1; + uint8_t is_step_det : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_emb_func_status_t; + +#define ISM330BX_FSM_STATUS 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm8 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fsm_status_t; + +#define ISM330BX_MLC_STATUS 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_mlc1 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t is_mlc4 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_mlc_status_t; + +#define ISM330BX_PAGE_RW 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 5; + uint8_t page_read : 1; + uint8_t page_write : 1; + uint8_t emb_func_lir : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_lir : 1; + uint8_t page_write : 1; + uint8_t page_read : 1; + uint8_t not_used0 : 5; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_page_rw_t; + +#define ISM330BX_EMB_FUNC_FIFO_EN_A 0x44U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t sflp_game_fifo_en : 1; + uint8_t not_used1 : 2; + uint8_t sflp_gravity_fifo_en : 1; + uint8_t sflp_gbias_fifo_en : 1; + uint8_t step_counter_fifo_en : 1; + uint8_t mlc_fifo_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_fifo_en : 1; + uint8_t step_counter_fifo_en : 1; + uint8_t sflp_gbias_fifo_en : 1; + uint8_t sflp_gravity_fifo_en : 1; + uint8_t not_used1 : 2; + uint8_t sflp_game_fifo_en : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_emb_func_fifo_en_a_t; + +#define ISM330BX_EMB_FUNC_FIFO_EN_B 0x45U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t mlc_filter_feature_fifo_en : 1; + uint8_t not_used1 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 6; + uint8_t mlc_filter_feature_fifo_en : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_emb_func_fifo_en_b_t; + +#define ISM330BX_FSM_ENABLE 0x46U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm1_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm8_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm8_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm1_en : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fsm_enable_t; + +#define ISM330BX_FSM_LONG_COUNTER_L 0x48U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fsm_long_counter_l_t; + +#define ISM330BX_FSM_LONG_COUNTER_H 0x49U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fsm_long_counter_h_t; + +#define ISM330BX_INT_ACK_MASK 0x4BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t iack_mask : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t iack_mask : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_int_ack_mask_t; + +#define ISM330BX_FSM_OUTS1 0x4CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm1_n_v : 1; + uint8_t fsm1_p_v : 1; + uint8_t fsm1_n_3 : 1; + uint8_t fsm1_p_3 : 1; + uint8_t fsm1_n_2 : 1; + uint8_t fsm1_p_2 : 1; + uint8_t fsm1_n_1 : 1; + uint8_t fsm1_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm1_p_1 : 1; + uint8_t fsm1_n_1 : 1; + uint8_t fsm1_p_2 : 1; + uint8_t fsm1_n_2 : 1; + uint8_t fsm1_p_3 : 1; + uint8_t fsm1_n_3 : 1; + uint8_t fsm1_p_v : 1; + uint8_t fsm1_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fsm_outs1_t; + +#define ISM330BX_FSM_OUTS2 0x4DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm2_n_v : 1; + uint8_t fsm2_p_v : 1; + uint8_t fsm2_n_3 : 1; + uint8_t fsm2_p_3 : 1; + uint8_t fsm2_n_2 : 1; + uint8_t fsm2_p_2 : 1; + uint8_t fsm2_n_1 : 1; + uint8_t fsm2_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm2_p_1 : 1; + uint8_t fsm2_n_1 : 1; + uint8_t fsm2_p_2 : 1; + uint8_t fsm2_n_2 : 1; + uint8_t fsm2_p_3 : 1; + uint8_t fsm2_n_3 : 1; + uint8_t fsm2_p_v : 1; + uint8_t fsm2_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fsm_outs2_t; + +#define ISM330BX_FSM_OUTS3 0x4EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm3_n_v : 1; + uint8_t fsm3_p_v : 1; + uint8_t fsm3_n_3 : 1; + uint8_t fsm3_p_3 : 1; + uint8_t fsm3_n_2 : 1; + uint8_t fsm3_p_2 : 1; + uint8_t fsm3_n_1 : 1; + uint8_t fsm3_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm3_p_1 : 1; + uint8_t fsm3_n_1 : 1; + uint8_t fsm3_p_2 : 1; + uint8_t fsm3_n_2 : 1; + uint8_t fsm3_p_3 : 1; + uint8_t fsm3_n_3 : 1; + uint8_t fsm3_p_v : 1; + uint8_t fsm3_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fsm_outs3_t; + +#define ISM330BX_FSM_OUTS4 0x4FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm4_n_v : 1; + uint8_t fsm4_p_v : 1; + uint8_t fsm4_n_3 : 1; + uint8_t fsm4_p_3 : 1; + uint8_t fsm4_n_2 : 1; + uint8_t fsm4_p_2 : 1; + uint8_t fsm4_n_1 : 1; + uint8_t fsm4_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm4_p_1 : 1; + uint8_t fsm4_n_1 : 1; + uint8_t fsm4_p_2 : 1; + uint8_t fsm4_n_2 : 1; + uint8_t fsm4_p_3 : 1; + uint8_t fsm4_n_3 : 1; + uint8_t fsm4_p_v : 1; + uint8_t fsm4_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fsm_outs4_t; + +#define ISM330BX_FSM_OUTS5 0x50U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm5_n_v : 1; + uint8_t fsm5_p_v : 1; + uint8_t fsm5_n_3 : 1; + uint8_t fsm5_p_3 : 1; + uint8_t fsm5_n_2 : 1; + uint8_t fsm5_p_2 : 1; + uint8_t fsm5_n_1 : 1; + uint8_t fsm5_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm5_p_1 : 1; + uint8_t fsm5_n_1 : 1; + uint8_t fsm5_p_2 : 1; + uint8_t fsm5_n_2 : 1; + uint8_t fsm5_p_3 : 1; + uint8_t fsm5_n_3 : 1; + uint8_t fsm5_p_v : 1; + uint8_t fsm5_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fsm_outs5_t; + +#define ISM330BX_FSM_OUTS6 0x51U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm6_n_v : 1; + uint8_t fsm6_p_v : 1; + uint8_t fsm6_n_3 : 1; + uint8_t fsm6_p_3 : 1; + uint8_t fsm6_n_2 : 1; + uint8_t fsm6_p_2 : 1; + uint8_t fsm6_n_1 : 1; + uint8_t fsm6_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm6_p_1 : 1; + uint8_t fsm6_n_1 : 1; + uint8_t fsm6_p_2 : 1; + uint8_t fsm6_n_2 : 1; + uint8_t fsm6_p_3 : 1; + uint8_t fsm6_n_3 : 1; + uint8_t fsm6_p_v : 1; + uint8_t fsm6_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fsm_outs6_t; + +#define ISM330BX_FSM_OUTS7 0x52U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm7_n_v : 1; + uint8_t fsm7_p_v : 1; + uint8_t fsm7_n_3 : 1; + uint8_t fsm7_p_3 : 1; + uint8_t fsm7_n_2 : 1; + uint8_t fsm7_p_2 : 1; + uint8_t fsm7_n_1 : 1; + uint8_t fsm7_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm7_p_1 : 1; + uint8_t fsm7_n_1 : 1; + uint8_t fsm7_p_2 : 1; + uint8_t fsm7_n_2 : 1; + uint8_t fsm7_p_3 : 1; + uint8_t fsm7_n_3 : 1; + uint8_t fsm7_p_v : 1; + uint8_t fsm7_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fsm_outs7_t; + +#define ISM330BX_FSM_OUTS8 0x53U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm8_n_v : 1; + uint8_t fsm8_p_v : 1; + uint8_t fsm8_n_3 : 1; + uint8_t fsm8_p_3 : 1; + uint8_t fsm8_n_2 : 1; + uint8_t fsm8_p_2 : 1; + uint8_t fsm8_n_1 : 1; + uint8_t fsm8_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm8_p_1 : 1; + uint8_t fsm8_n_1 : 1; + uint8_t fsm8_p_2 : 1; + uint8_t fsm8_n_2 : 1; + uint8_t fsm8_p_3 : 1; + uint8_t fsm8_n_3 : 1; + uint8_t fsm8_p_v : 1; + uint8_t fsm8_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fsm_outs8_t; + +#define ISM330BX_SFLP_ODR 0x5EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t sflp_game_odr : 3; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t sflp_game_odr : 3; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_sflp_odr_t; + +#define ISM330BX_FSM_ODR 0x5FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t fsm_odr : 3; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t fsm_odr : 3; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fsm_odr_t; + +#define ISM330BX_MLC_ODR 0x60U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t mlc_odr : 3; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t mlc_odr : 3; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_mlc_odr_t; + +#define ISM330BX_STEP_COUNTER_L 0x62U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t step : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_step_counter_l_t; + +#define ISM330BX_STEP_COUNTER_H 0x63U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t step : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_step_counter_h_t; + +#define ISM330BX_EMB_FUNC_SRC 0x64U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t stepcounter_bit_set : 1; + uint8_t step_overflow : 1; + uint8_t step_count_delta_ia : 1; + uint8_t step_detected : 1; + uint8_t not_used1 : 1; + uint8_t pedo_rst_step : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pedo_rst_step : 1; + uint8_t not_used1 : 1; + uint8_t step_detected : 1; + uint8_t step_count_delta_ia : 1; + uint8_t step_overflow : 1; + uint8_t stepcounter_bit_set : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_emb_func_src_t; + +#define ISM330BX_EMB_FUNC_INIT_A 0x66U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t sflp_game_init : 1; + uint8_t not_used2 : 1; + uint8_t step_det_init : 1; + uint8_t tilt_init : 1; + uint8_t sig_mot_init : 1; + uint8_t not_used1 : 1; + uint8_t mlc_before_fsm_init : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_before_fsm_init : 1; + uint8_t not_used1 : 1; + uint8_t sig_mot_init : 1; + uint8_t tilt_init : 1; + uint8_t step_det_init : 1; + uint8_t not_used2 : 1; + uint8_t sflp_game_init : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_emb_func_init_a_t; + +#define ISM330BX_EMB_FUNC_INIT_B 0x67U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_init : 1; + uint8_t not_used0 : 2; + uint8_t fifo_compr_init : 1; + uint8_t mlc_init : 1; + uint8_t not_used1 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 3; + uint8_t mlc_init : 1; + uint8_t fifo_compr_init : 1; + uint8_t not_used0 : 2; + uint8_t fsm_init : 1; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_emb_func_init_b_t; + +#define ISM330BX_MLC1_SRC 0x70U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc1_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc1_src : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_mlc1_src_t; + +#define ISM330BX_MLC2_SRC 0x71U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc2_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc2_src : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_mlc2_src_t; + +#define ISM330BX_MLC3_SRC 0x72U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc3_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc3_src : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_mlc3_src_t; + +#define ISM330BX_MLC4_SRC 0x73U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc4_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc4_src : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_mlc4_src_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page pg0_emb_adv + * @{ + * + */ +#define ISM330BX_EMB_ADV_PG_0 0x000 + +#define ISM330BX_SFLP_GAME_GBIASX_L 0x6EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasx : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_sflp_game_gbiasx_l_t; + +#define ISM330BX_SFLP_GAME_GBIASX_H 0x6FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasx : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_sflp_game_gbiasx_h_t; + +#define ISM330BX_SFLP_GAME_GBIASY_L 0x70U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasy : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_sflp_game_gbiasy_l_t; + +#define ISM330BX_SFLP_GAME_GBIASY_H 0x71U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasy : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_sflp_game_gbiasy_h_t; + +#define ISM330BX_SFLP_GAME_GBIASZ_L 0x72U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasz : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_sflp_game_gbiasz_l_t; + +#define ISM330BX_SFLP_GAME_GBIASZ_H 0x73U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasz : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_sflp_game_gbiasz_h_t; + +#define ISM330BX_FSM_QVAR_SENSITIVITY_L 0xBAU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_qvar_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_qvar_s : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fsm_qvar_sensitivity_l_t; + +#define ISM330BX_FSM_QVAR_SENSITIVITY_H 0xBBU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_qvar_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_qvar_s : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fsm_qvar_sensitivity_h_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page pg1_emb_adv + * @{ + * + */ + +#define ISM330BX_EMB_ADV_PG_1 0x001 + +#define ISM330BX_FSM_LC_TIMEOUT_L 0x17AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc_timeout : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc_timeout : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fsm_lc_timeout_l_t; + +#define ISM330BX_FSM_LC_TIMEOUT_H 0x17BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc_timeout : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc_timeout : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fsm_lc_timeout_h_t; + +#define ISM330BX_FSM_PROGRAMS 0x17CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_n_prog : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_n_prog : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fsm_programs_t; + +#define ISM330BX_FSM_START_ADD_L 0x17EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_start : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_start : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fsm_start_add_l_t; + +#define ISM330BX_FSM_START_ADD_H 0x17FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_start : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_start : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_fsm_start_add_h_t; + +#define ISM330BX_PEDO_CMD_REG 0x183U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t fp_rejection_en : 1; + uint8_t carry_count_en : 1; + uint8_t not_used1 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 4; + uint8_t carry_count_en : 1; + uint8_t fp_rejection_en : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_pedo_cmd_reg_t; + +#define ISM330BX_PEDO_DEB_STEPS_CONF 0x184U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t deb_step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t deb_step : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_pedo_deb_steps_conf_t; + +#define ISM330BX_PEDO_SC_DELTAT_L 0x1D0U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t pd_sc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pd_sc : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_pedo_sc_deltat_l_t; + +#define ISM330BX_PEDO_SC_DELTAT_H 0x1D1U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t pd_sc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pd_sc : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_pedo_sc_deltat_h_t; + +#define ISM330BX_MLC_QVAR_SENSITIVITY_L 0x1E8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc_qvar_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_qvar_s : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_mlc_qvar_sensitivity_l_t; + +#define ISM330BX_MLC_QVAR_SENSITIVITY_H 0x1E9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc_qvar_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_qvar_s : 8; +#endif /* DRV_BYTE_ORDER */ +} ism330bx_mlc_qvar_sensitivity_h_t; + +/** + * @} + * + */ + +#define ISM330BX_START_FSM_ADD 0x035CU + +/** + * @defgroup ISM330BX_Register_Union + * @brief These unions group all the registers having a bit-field + * description. + * These unions are useful but it's not needed by the driver. + * + * REMOVING this unions you are compliant with: + * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " + * + * @{ + * + */ +typedef union +{ + ism330bx_func_cfg_access_t func_cfg_access; + ism330bx_pin_ctrl_t pin_ctrl; + ism330bx_if_cfg_t if_cfg; + ism330bx_fifo_ctrl1_t fifo_ctrl1; + ism330bx_fifo_ctrl2_t fifo_ctrl2; + ism330bx_fifo_ctrl3_t fifo_ctrl3; + ism330bx_fifo_ctrl4_t fifo_ctrl4; + ism330bx_counter_bdr_reg1_t counter_bdr_reg1; + ism330bx_counter_bdr_reg2_t counter_bdr_reg2; + ism330bx_int1_ctrl_t int1_ctrl; + ism330bx_int2_ctrl_t int2_ctrl; + ism330bx_who_am_i_t who_am_i; + ism330bx_ctrl1_t ctrl1; + ism330bx_ctrl2_t ctrl2; + ism330bx_ctrl3_t ctrl3; + ism330bx_ctrl4_t ctrl4; + ism330bx_ctrl5_t ctrl5; + ism330bx_ctrl6_t ctrl6; + ism330bx_ctrl7_t ctrl7; + ism330bx_ctrl8_t ctrl8; + ism330bx_ctrl9_t ctrl9; + ism330bx_ctrl10_t ctrl10; + ism330bx_fifo_status1_t fifo_status1; + ism330bx_fifo_status2_t fifo_status2; + ism330bx_all_int_src_t all_int_src; + ism330bx_status_reg_t status_reg; + ism330bx_out_temp_l_t out_temp_l; + ism330bx_out_temp_h_t out_temp_h; + ism330bx_outx_l_g_t outx_l_g; + ism330bx_outx_h_g_t outx_h_g; + ism330bx_outy_l_g_t outy_l_g; + ism330bx_outy_h_g_t outy_h_g; + ism330bx_outz_l_g_t outz_l_g; + ism330bx_outz_h_g_t outz_h_g; + ism330bx_outz_l_a_t outz_l_a; + ism330bx_outz_h_a_t outz_h_a; + ism330bx_outy_l_a_t outy_l_a; + ism330bx_outy_h_a_t outy_h_a; + ism330bx_outx_l_a_t outx_l_a; + ism330bx_outx_h_a_t outx_h_a; + ism330bx_ui_outz_l_a_dualc_t ui_outz_l_a_dualc; + ism330bx_ui_outz_h_a_dualc_t ui_outz_h_a_dualc; + ism330bx_ui_outy_l_a_dualc_t ui_outy_l_a_dualc; + ism330bx_ui_outy_h_a_dualc_t ui_outy_h_a_dualc; + ism330bx_ui_outx_l_a_dualc_t ui_outx_l_a_dualc; + ism330bx_ui_outx_h_a_dualc_t ui_outx_h_a_dualc; + ism330bx_ah_qvar_out_l_t ah_qvar_out_l; + ism330bx_ah_qvar_out_h_t ah_qvar_out_h; + ism330bx_timestamp0_t timestamp0; + ism330bx_timestamp1_t timestamp1; + ism330bx_timestamp2_t timestamp2; + ism330bx_timestamp3_t timestamp3; + ism330bx_wake_up_src_t wake_up_src; + ism330bx_tap_src_t tap_src; + ism330bx_d6d_src_t d6d_src; + ism330bx_emb_func_status_mainpage_t emb_func_status_mainpage; + ism330bx_fsm_status_mainpage_t fsm_status_mainpage; + ism330bx_mlc_status_mainpage_t mlc_status_mainpage; + ism330bx_internal_freq_t internal_freq; + ism330bx_functions_enable_t functions_enable; + ism330bx_inactivity_dur_t inactivity_dur; + ism330bx_inactivity_ths_t inactivity_ths; + ism330bx_tap_cfg0_t tap_cfg0; + ism330bx_tap_cfg1_t tap_cfg1; + ism330bx_tap_cfg2_t tap_cfg2; + ism330bx_tap_ths_6d_t tap_ths_6d; + ism330bx_tap_dur_t int_dur2; + ism330bx_wake_up_ths_t wake_up_ths; + ism330bx_wake_up_dur_t wake_up_dur; + ism330bx_free_fall_t free_fall; + ism330bx_md1_cfg_t md1_cfg; + ism330bx_md2_cfg_t md2_cfg; + ism330bx_emb_func_cfg_t emb_func_cfg; + ism330bx_tdm_cfg0_t tdm_cfg0; + ism330bx_tdm_cfg1_t tdm_cfg1; + ism330bx_tdm_cfg2_t tdm_cfg2; + ism330bx_z_ofs_usr_t z_ofs_usr; + ism330bx_y_ofs_usr_t y_ofs_usr; + ism330bx_x_ofs_usr_t x_ofs_usr; + ism330bx_fifo_data_out_tag_t fifo_data_out_tag; + ism330bx_fifo_data_out_byte_0_t fifo_data_out_byte_0; + ism330bx_fifo_data_out_byte_1_t fifo_data_out_byte_1; + ism330bx_fifo_data_out_byte_2_t fifo_data_out_byte_2; + ism330bx_fifo_data_out_byte_3_t fifo_data_out_byte_3; + ism330bx_fifo_data_out_byte_4_t fifo_data_out_byte_4; + ism330bx_fifo_data_out_byte_5_t fifo_data_out_byte_5; + ism330bx_page_sel_t page_sel; + ism330bx_emb_func_en_a_t emb_func_en_a; + ism330bx_emb_func_en_b_t emb_func_en_b; + ism330bx_emb_func_exec_status_t emb_func_exec_status; + ism330bx_page_address_t page_address; + ism330bx_page_value_t page_value; + ism330bx_emb_func_int1_t emb_func_int1; + ism330bx_fsm_int1_t fsm_int1; + ism330bx_mlc_int1_t mlc_int1; + ism330bx_emb_func_int2_t emb_func_int2; + ism330bx_fsm_int2_t fsm_int2; + ism330bx_mlc_int2_t mlc_int2; + ism330bx_emb_func_status_t emb_func_status; + ism330bx_fsm_status_t fsm_status; + ism330bx_mlc_status_t mlc_status; + ism330bx_page_rw_t page_rw; + ism330bx_emb_func_fifo_en_a_t emb_func_fifo_en_a; + ism330bx_emb_func_fifo_en_b_t emb_func_fifo_en_b; + ism330bx_fsm_enable_t fsm_enable; + ism330bx_fsm_long_counter_l_t fsm_long_counter_l; + ism330bx_fsm_long_counter_h_t fsm_long_counter_h; + ism330bx_fsm_outs1_t fsm_outs1; + ism330bx_fsm_outs2_t fsm_outs2; + ism330bx_fsm_outs3_t fsm_outs3; + ism330bx_fsm_outs4_t fsm_outs4; + ism330bx_fsm_outs5_t fsm_outs5; + ism330bx_fsm_outs6_t fsm_outs6; + ism330bx_fsm_outs7_t fsm_outs7; + ism330bx_fsm_outs8_t fsm_outs8; + ism330bx_fsm_odr_t fsm_odr; + ism330bx_mlc_odr_t mlc_odr; + ism330bx_step_counter_l_t step_counter_l; + ism330bx_step_counter_h_t step_counter_h; + ism330bx_emb_func_src_t emb_func_src; + ism330bx_emb_func_init_a_t emb_func_init_a; + ism330bx_emb_func_init_b_t emb_func_init_b; + ism330bx_mlc1_src_t mlc1_src; + ism330bx_mlc2_src_t mlc2_src; + ism330bx_mlc3_src_t mlc3_src; + ism330bx_mlc4_src_t mlc4_src; + ism330bx_fsm_qvar_sensitivity_l_t fsm_qvar_sensitivity_l; + ism330bx_fsm_qvar_sensitivity_h_t fsm_qvar_sensitivity_h; + ism330bx_fsm_lc_timeout_l_t fsm_lc_timeout_l; + ism330bx_fsm_lc_timeout_h_t fsm_lc_timeout_h; + ism330bx_fsm_programs_t fsm_programs; + ism330bx_fsm_start_add_l_t fsm_start_add_l; + ism330bx_fsm_start_add_h_t fsm_start_add_h; + ism330bx_pedo_cmd_reg_t pedo_cmd_reg; + ism330bx_pedo_deb_steps_conf_t pedo_deb_steps_conf; + ism330bx_pedo_sc_deltat_l_t pedo_sc_deltat_l; + ism330bx_pedo_sc_deltat_h_t pedo_sc_deltat_h; + ism330bx_mlc_qvar_sensitivity_l_t mlc_qvar_sensitivity_l; + ism330bx_mlc_qvar_sensitivity_h_t mlc_qvar_sensitivity_h; + bitwise_t bitwise; + uint8_t byte; +} ism330bx_reg_t; + + +/** + * @} + * + */ + +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + +int32_t ism330bx_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); +int32_t ism330bx_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); + +float_t ism330bx_from_sflp_to_mg(int16_t lsb); +float_t ism330bx_from_fs2_to_mg(int16_t lsb); +float_t ism330bx_from_fs4_to_mg(int16_t lsb); +float_t ism330bx_from_fs8_to_mg(int16_t lsb); +float_t ism330bx_from_fs16_to_mg(int16_t lsb); + +float_t ism330bx_from_fs125_to_mdps(int16_t lsb); +float_t ism330bx_from_fs500_to_mdps(int16_t lsb); +float_t ism330bx_from_fs250_to_mdps(int16_t lsb); +float_t ism330bx_from_fs1000_to_mdps(int16_t lsb); +float_t ism330bx_from_fs2000_to_mdps(int16_t lsb); +float_t ism330bx_from_fs4000_to_mdps(int16_t lsb); + +float_t ism330bx_from_lsb_to_celsius(int16_t lsb); + +uint64_t ism330bx_from_lsb_to_nsec(uint32_t lsb); + +float_t ism330bx_from_lsb_to_mv(int16_t lsb); + +typedef enum +{ + ISM330BX_READY = 0x0, + ISM330BX_GLOBAL_RST = 0x1, + ISM330BX_RESTORE_CAL_PARAM = 0x2, + ISM330BX_RESTORE_CTRL_REGS = 0x4, +} ism330bx_reset_t; +int32_t ism330bx_reset_set(const stmdev_ctx_t *ctx, ism330bx_reset_t val); +int32_t ism330bx_reset_get(const stmdev_ctx_t *ctx, ism330bx_reset_t *val); + +typedef enum +{ + ISM330BX_MAIN_MEM_BANK = 0x0, + ISM330BX_EMBED_FUNC_MEM_BANK = 0x1, +} ism330bx_mem_bank_t; +int32_t ism330bx_mem_bank_set(const stmdev_ctx_t *ctx, ism330bx_mem_bank_t val); +int32_t ism330bx_mem_bank_get(const stmdev_ctx_t *ctx, + ism330bx_mem_bank_t *val); + +int32_t ism330bx_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM330BX_XL_ODR_OFF = 0x0, + ISM330BX_XL_ODR_AT_1Hz875 = 0x1, + ISM330BX_XL_ODR_AT_7Hz5 = 0x2, + ISM330BX_XL_ODR_AT_15Hz = 0x3, + ISM330BX_XL_ODR_AT_30Hz = 0x4, + ISM330BX_XL_ODR_AT_60Hz = 0x5, + ISM330BX_XL_ODR_AT_120Hz = 0x6, + ISM330BX_XL_ODR_AT_240Hz = 0x7, + ISM330BX_XL_ODR_AT_480Hz = 0x8, + ISM330BX_XL_ODR_AT_960Hz = 0x9, + ISM330BX_XL_ODR_AT_1920Hz = 0xA, + ISM330BX_XL_ODR_AT_3840Hz = 0xB, +} ism330bx_xl_data_rate_t; +int32_t ism330bx_xl_data_rate_set(const stmdev_ctx_t *ctx, + ism330bx_xl_data_rate_t val); +int32_t ism330bx_xl_data_rate_get(const stmdev_ctx_t *ctx, + ism330bx_xl_data_rate_t *val); + +typedef enum +{ + ISM330BX_XL_HIGH_PERFORMANCE_MD = 0x0, + ISM330BX_XL_HIGH_PERFORMANCE_TDM_MD = 0x2, + ISM330BX_XL_LOW_POWER_2_AVG_MD = 0x4, + ISM330BX_XL_LOW_POWER_4_AVG_MD = 0x5, + ISM330BX_XL_LOW_POWER_8_AVG_MD = 0x6, +} ism330bx_xl_mode_t; +int32_t ism330bx_xl_mode_set(const stmdev_ctx_t *ctx, ism330bx_xl_mode_t val); +int32_t ism330bx_xl_mode_get(const stmdev_ctx_t *ctx, ism330bx_xl_mode_t *val); + +typedef enum +{ + ISM330BX_GY_ODR_OFF = 0x0, + ISM330BX_GY_ODR_AT_7Hz5 = 0x2, + ISM330BX_GY_ODR_AT_15Hz = 0x3, + ISM330BX_GY_ODR_AT_30Hz = 0x4, + ISM330BX_GY_ODR_AT_60Hz = 0x5, + ISM330BX_GY_ODR_AT_120Hz = 0x6, + ISM330BX_GY_ODR_AT_240Hz = 0x7, + ISM330BX_GY_ODR_AT_480Hz = 0x8, + ISM330BX_GY_ODR_AT_960Hz = 0x9, + ISM330BX_GY_ODR_AT_1920Hz = 0xa, + ISM330BX_GY_ODR_AT_3840Hz = 0xb, +} ism330bx_gy_data_rate_t; +int32_t ism330bx_gy_data_rate_set(const stmdev_ctx_t *ctx, + ism330bx_gy_data_rate_t val); +int32_t ism330bx_gy_data_rate_get(const stmdev_ctx_t *ctx, + ism330bx_gy_data_rate_t *val); + +typedef enum +{ + ISM330BX_GY_HIGH_PERFORMANCE_MD = 0x0, + ISM330BX_GY_SLEEP_MD = 0x4, + ISM330BX_GY_LOW_POWER_MD = 0x5, +} ism330bx_gy_mode_t; +int32_t ism330bx_gy_mode_set(const stmdev_ctx_t *ctx, ism330bx_gy_mode_t val); +int32_t ism330bx_gy_mode_get(const stmdev_ctx_t *ctx, ism330bx_gy_mode_t *val); + +int32_t ism330bx_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism330bx_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM330BX_DRDY_LATCHED = 0x0, + ISM330BX_DRDY_PULSED = 0x1, +} ism330bx_data_ready_mode_t; +int32_t ism330bx_data_ready_mode_set(const stmdev_ctx_t *ctx, + ism330bx_data_ready_mode_t val); +int32_t ism330bx_data_ready_mode_get(const stmdev_ctx_t *ctx, + ism330bx_data_ready_mode_t *val); + +typedef enum +{ + ISM330BX_125dps = 0x0, + ISM330BX_250dps = 0x1, + ISM330BX_500dps = 0x2, + ISM330BX_1000dps = 0x3, + ISM330BX_2000dps = 0x4, + ISM330BX_4000dps = 0xc, +} ism330bx_gy_full_scale_t; +int32_t ism330bx_gy_full_scale_set(const stmdev_ctx_t *ctx, + ism330bx_gy_full_scale_t val); +int32_t ism330bx_gy_full_scale_get(const stmdev_ctx_t *ctx, + ism330bx_gy_full_scale_t *val); + +typedef enum +{ + ISM330BX_2g = 0x0, + ISM330BX_4g = 0x1, + ISM330BX_8g = 0x2, +} ism330bx_xl_full_scale_t; +int32_t ism330bx_xl_full_scale_set(const stmdev_ctx_t *ctx, + ism330bx_xl_full_scale_t val); +int32_t ism330bx_xl_full_scale_get(const stmdev_ctx_t *ctx, + ism330bx_xl_full_scale_t *val); + +int32_t ism330bx_xl_dual_channel_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM330BX_XL_ST_DISABLE = 0x0, + ISM330BX_XL_ST_POSITIVE = 0x1, + ISM330BX_XL_ST_NEGATIVE = 0x2, + ISM330BX_XL_ST_OFFSET_POS = 0x5, + ISM330BX_XL_ST_OFFSET_NEG = 0x6, +} ism330bx_xl_self_test_t; +int32_t ism330bx_xl_self_test_set(const stmdev_ctx_t *ctx, + ism330bx_xl_self_test_t val); +int32_t ism330bx_xl_self_test_get(const stmdev_ctx_t *ctx, + ism330bx_xl_self_test_t *val); + +typedef enum +{ + ISM330BX_GY_ST_DISABLE = 0x0, + ISM330BX_GY_ST_POSITIVE = 0x1, + ISM330BX_GY_ST_NEGATIVE = 0x2, +} ism330bx_gy_self_test_t; +int32_t ism330bx_gy_self_test_set(const stmdev_ctx_t *ctx, + ism330bx_gy_self_test_t val); +int32_t ism330bx_gy_self_test_get(const stmdev_ctx_t *ctx, + ism330bx_gy_self_test_t *val); + +typedef struct +{ + uint8_t drdy_xl : 1; + uint8_t drdy_gy : 1; + uint8_t drdy_temp : 1; + uint8_t drdy_ah_qvar : 1; + uint8_t gy_settling : 1; + uint8_t den_flag : 1; + uint8_t timestamp : 1; + uint8_t free_fall : 1; + uint8_t wake_up : 1; + uint8_t wake_up_z : 1; + uint8_t wake_up_y : 1; + uint8_t wake_up_x : 1; + uint8_t single_tap : 1; + uint8_t double_tap : 1; + uint8_t tap_z : 1; + uint8_t tap_y : 1; + uint8_t tap_x : 1; + uint8_t tap_sign : 1; + uint8_t six_d : 1; + uint8_t six_d_xl : 1; + uint8_t six_d_xh : 1; + uint8_t six_d_yl : 1; + uint8_t six_d_yh : 1; + uint8_t six_d_zl : 1; + uint8_t six_d_zh : 1; + uint8_t sleep_change : 1; + uint8_t sleep_state : 1; + uint8_t step_detector : 1; + uint8_t step_count_inc : 1; + uint8_t step_count_overflow : 1; + uint8_t step_on_delta_time : 1; + uint8_t emb_func_stand_by : 1; + uint8_t emb_func_time_exceed: 1; + uint8_t tilt : 1; + uint8_t sig_mot : 1; + uint8_t fsm_lc : 1; + uint8_t fsm1 : 1; + uint8_t fsm2 : 1; + uint8_t fsm3 : 1; + uint8_t fsm4 : 1; + uint8_t fsm5 : 1; + uint8_t fsm6 : 1; + uint8_t fsm7 : 1; + uint8_t fsm8 : 1; + uint8_t mlc1 : 1; + uint8_t mlc2 : 1; + uint8_t mlc3 : 1; + uint8_t mlc4 : 1; + uint8_t fifo_bdr : 1; + uint8_t fifo_full : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_th : 1; +} ism330bx_all_sources_t; +int32_t ism330bx_all_sources_get(const stmdev_ctx_t *ctx, + ism330bx_all_sources_t *val); + +typedef struct +{ + uint8_t drdy_xl : 1; + uint8_t drdy_gy : 1; + uint8_t drdy_temp : 1; + uint8_t drdy_ah_qvar : 1; +} ism330bx_data_ready_t; +int32_t ism330bx_flag_data_ready_get(const stmdev_ctx_t *ctx, + ism330bx_data_ready_t *val); + +int32_t ism330bx_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t ism330bx_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t ism330bx_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t ism330bx_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t ism330bx_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, + int16_t *val); + +int32_t ism330bx_ah_qvar_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t ism330bx_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val); + +typedef struct +{ + uint8_t x : 1; + uint8_t y : 1; + uint8_t z : 1; +} ism330bx_tdm_xl_axis_t; +int32_t ism330bx_tdm_xl_axis_set(const stmdev_ctx_t *ctx, ism330bx_tdm_xl_axis_t val); +int32_t ism330bx_tdm_xl_axis_get(const stmdev_ctx_t *ctx, ism330bx_tdm_xl_axis_t *val); + +int32_t ism330bx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len); +int32_t ism330bx_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len); + +int32_t ism330bx_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism330bx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); + +typedef enum +{ + ISM330BX_AUTO = 0x0, + ISM330BX_ALWAYS_ACTIVE = 0x1, +} ism330bx_filt_anti_spike_t; +int32_t ism330bx_filt_anti_spike_set(const stmdev_ctx_t *ctx, + ism330bx_filt_anti_spike_t val); +int32_t ism330bx_filt_anti_spike_get(const stmdev_ctx_t *ctx, + ism330bx_filt_anti_spike_t *val); + +typedef struct +{ + uint8_t drdy : 1; + uint8_t irq_xl : 1; + uint8_t irq_g : 1; + uint8_t tdm_excep_code : 1; +} ism330bx_filt_settling_mask_t; +int32_t ism330bx_filt_settling_mask_set(const stmdev_ctx_t *ctx, + ism330bx_filt_settling_mask_t val); +int32_t ism330bx_filt_settling_mask_get(const stmdev_ctx_t *ctx, + ism330bx_filt_settling_mask_t *val); + +typedef enum +{ + ISM330BX_GY_ULTRA_LIGHT = 0x0, + ISM330BX_GY_VERY_LIGHT = 0x1, + ISM330BX_GY_LIGHT = 0x2, + ISM330BX_GY_MEDIUM = 0x3, + ISM330BX_GY_STRONG = 0x4, + ISM330BX_GY_VERY_STRONG = 0x5, + ISM330BX_GY_AGGRESSIVE = 0x6, + ISM330BX_GY_XTREME = 0x7, +} ism330bx_filt_gy_lp1_bandwidth_t; +int32_t ism330bx_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, + ism330bx_filt_gy_lp1_bandwidth_t val); +int32_t ism330bx_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, + ism330bx_filt_gy_lp1_bandwidth_t *val); + +int32_t ism330bx_filt_gy_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t hpf : 1; + uint8_t lpf : 1; +} ism330bx_filt_ah_qvar_conf_t; +int32_t ism330bx_filt_ah_qvar_conf_set(const stmdev_ctx_t *ctx, + ism330bx_filt_ah_qvar_conf_t val); +int32_t ism330bx_filt_ah_qvar_conf_get(const stmdev_ctx_t *ctx, + ism330bx_filt_ah_qvar_conf_t *val); + +typedef enum +{ + ISM330BX_XL_ULTRA_LIGHT = 0x0, + ISM330BX_XL_VERY_LIGHT = 0x1, + ISM330BX_XL_LIGHT = 0x2, + ISM330BX_XL_MEDIUM = 0x3, + ISM330BX_XL_STRONG = 0x4, + ISM330BX_XL_VERY_STRONG = 0x5, + ISM330BX_XL_AGGRESSIVE = 0x6, + ISM330BX_XL_XTREME = 0x7, +} ism330bx_filt_xl_lp2_bandwidth_t; +int32_t ism330bx_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, + ism330bx_filt_xl_lp2_bandwidth_t val); +int32_t ism330bx_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, + ism330bx_filt_xl_lp2_bandwidth_t *val); + +int32_t ism330bx_filt_xl_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism330bx_filt_xl_hp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism330bx_filt_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM330BX_HP_MD_NORMAL = 0x0, + ISM330BX_HP_MD_REFERENCE = 0x1, +} ism330bx_filt_xl_hp_mode_t; +int32_t ism330bx_filt_xl_hp_mode_set(const stmdev_ctx_t *ctx, + ism330bx_filt_xl_hp_mode_t val); +int32_t ism330bx_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx, + ism330bx_filt_xl_hp_mode_t *val); + +typedef enum +{ + ISM330BX_WK_FEED_SLOPE = 0x0, + ISM330BX_WK_FEED_HIGH_PASS = 0x1, + ISM330BX_WK_FEED_LP_WITH_OFFSET = 0x2, +} ism330bx_filt_wkup_act_feed_t; +int32_t ism330bx_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx, + ism330bx_filt_wkup_act_feed_t val); +int32_t ism330bx_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx, + ism330bx_filt_wkup_act_feed_t *val); + +int32_t ism330bx_mask_trigger_xl_settl_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM330BX_SIXD_FEED_ODR_DIV_2 = 0x0, + ISM330BX_SIXD_FEED_LOW_PASS = 0x1, +} ism330bx_filt_sixd_feed_t; +int32_t ism330bx_filt_sixd_feed_set(const stmdev_ctx_t *ctx, + ism330bx_filt_sixd_feed_t val); +int32_t ism330bx_filt_sixd_feed_get(const stmdev_ctx_t *ctx, + ism330bx_filt_sixd_feed_t *val); + +int32_t ism330bx_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM330BX_I2C_I3C_ENABLE = 0x0, + ISM330BX_I2C_I3C_DISABLE = 0x1, +} ism330bx_ui_i2c_i3c_mode_t; +int32_t ism330bx_ui_i2c_i3c_mode_set(const stmdev_ctx_t *ctx, + ism330bx_ui_i2c_i3c_mode_t val); +int32_t ism330bx_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx, + ism330bx_ui_i2c_i3c_mode_t *val); + +typedef enum +{ + ISM330BX_SPI_4_WIRE = 0x0, + ISM330BX_SPI_3_WIRE = 0x1, +} ism330bx_spi_mode_t; +int32_t ism330bx_spi_mode_set(const stmdev_ctx_t *ctx, ism330bx_spi_mode_t val); +int32_t ism330bx_spi_mode_get(const stmdev_ctx_t *ctx, + ism330bx_spi_mode_t *val); + +int32_t ism330bx_ui_sda_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM330BX_IBI_2us = 0x0, + ISM330BX_IBI_50us = 0x1, + ISM330BX_IBI_1ms = 0x2, + ISM330BX_IBI_25ms = 0x3, +} ism330bx_i3c_ibi_time_t; +int32_t ism330bx_i3c_ibi_time_set(const stmdev_ctx_t *ctx, + ism330bx_i3c_ibi_time_t val); +int32_t ism330bx_i3c_ibi_time_get(const stmdev_ctx_t *ctx, + ism330bx_i3c_ibi_time_t *val); + +typedef enum +{ + ISM330BX_PUSH_PULL = 0x0, + ISM330BX_OPEN_DRAIN = 0x1, +} ism330bx_int_pin_mode_t; +int32_t ism330bx_int_pin_mode_set(const stmdev_ctx_t *ctx, + ism330bx_int_pin_mode_t val); +int32_t ism330bx_int_pin_mode_get(const stmdev_ctx_t *ctx, + ism330bx_int_pin_mode_t *val); + +typedef enum +{ + ISM330BX_ACTIVE_HIGH = 0x0, + ISM330BX_ACTIVE_LOW = 0x1, +} ism330bx_pin_polarity_t; +int32_t ism330bx_pin_polarity_set(const stmdev_ctx_t *ctx, + ism330bx_pin_polarity_t val); +int32_t ism330bx_pin_polarity_get(const stmdev_ctx_t *ctx, + ism330bx_pin_polarity_t *val); + +typedef struct +{ + uint8_t boot : 1; + uint8_t drdy_xl : 1; + uint8_t drdy_gy : 1; + uint8_t drdy_temp : 1; + uint8_t drdy_ah_qvar : 1; + uint8_t fifo_th : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_full : 1; + uint8_t fifo_bdr : 1; + uint8_t den_flag : 1; + uint8_t timestamp : 1; // impact on int2 signals + uint8_t six_d : 1; + uint8_t double_tap : 1; + uint8_t free_fall : 1; + uint8_t wake_up : 1; + uint8_t single_tap : 1; + uint8_t sleep_change : 1; + uint8_t sleep_status : 1; + uint8_t step_detector : 1; + uint8_t step_count_overflow : 1; + uint8_t tilt : 1; + uint8_t sig_mot : 1; + uint8_t emb_func_stand_by : 1; // impact on int2 signals + uint8_t fsm_lc : 1; + uint8_t fsm1 : 1; + uint8_t fsm2 : 1; + uint8_t fsm3 : 1; + uint8_t fsm4 : 1; + uint8_t fsm5 : 1; + uint8_t fsm6 : 1; + uint8_t fsm7 : 1; + uint8_t fsm8 : 1; + uint8_t mlc1 : 1; + uint8_t mlc2 : 1; + uint8_t mlc3 : 1; + uint8_t mlc4 : 1; +} ism330bx_pin_int_route_t; +int32_t ism330bx_pin_int1_route_set(const stmdev_ctx_t *ctx, + ism330bx_pin_int_route_t val); +int32_t ism330bx_pin_int1_route_get(const stmdev_ctx_t *ctx, + ism330bx_pin_int_route_t *val); +int32_t ism330bx_pin_int2_route_set(const stmdev_ctx_t *ctx, + ism330bx_pin_int_route_t val); +int32_t ism330bx_pin_int2_route_get(const stmdev_ctx_t *ctx, + ism330bx_pin_int_route_t *val); + +int32_t ism330bx_pin_int_en_when_i2c_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_pin_int_en_when_i2c_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM330BX_ALL_INT_PULSED = 0x0, + ISM330BX_BASE_LATCHED_EMB_PULSED = 0x1, + ISM330BX_BASE_PULSED_EMB_LATCHED = 0x2, + ISM330BX_ALL_INT_LATCHED = 0x3, +} ism330bx_int_notification_t; +int32_t ism330bx_int_notification_set(const stmdev_ctx_t *ctx, + ism330bx_int_notification_t val); +int32_t ism330bx_int_notification_get(const stmdev_ctx_t *ctx, + ism330bx_int_notification_t *val); + +typedef enum +{ + ISM330BX_XL_AND_GY_NOT_AFFECTED = 0x0, + ISM330BX_XL_LOW_POWER_GY_NOT_AFFECTED = 0x1, + ISM330BX_XL_LOW_POWER_GY_SLEEP = 0x2, + ISM330BX_XL_LOW_POWER_GY_POWER_DOWN = 0x3, +} ism330bx_act_mode_t; +int32_t ism330bx_act_mode_set(const stmdev_ctx_t *ctx, ism330bx_act_mode_t val); +int32_t ism330bx_act_mode_get(const stmdev_ctx_t *ctx, + ism330bx_act_mode_t *val); + +typedef enum +{ + ISM330BX_SLEEP_TO_ACT_AT_1ST_SAMPLE = 0x0, + ISM330BX_SLEEP_TO_ACT_AT_2ND_SAMPLE = 0x1, + ISM330BX_SLEEP_TO_ACT_AT_3RD_SAMPLE = 0x2, + ISM330BX_SLEEP_TO_ACT_AT_4th_SAMPLE = 0x3, +} ism330bx_act_from_sleep_to_act_dur_t; +int32_t ism330bx_act_from_sleep_to_act_dur_set(const stmdev_ctx_t *ctx, + ism330bx_act_from_sleep_to_act_dur_t val); +int32_t ism330bx_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx, + ism330bx_act_from_sleep_to_act_dur_t *val); + +typedef enum +{ + ISM330BX_1Hz875 = 0x0, + ISM330BX_15Hz = 0x1, + ISM330BX_30Hz = 0x2, + ISM330BX_60Hz = 0x3, +} ism330bx_act_sleep_xl_odr_t; +int32_t ism330bx_act_sleep_xl_odr_set(const stmdev_ctx_t *ctx, + ism330bx_act_sleep_xl_odr_t val); +int32_t ism330bx_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx, + ism330bx_act_sleep_xl_odr_t *val); + +typedef struct +{ + uint32_t wk_ths_mg; + uint32_t inact_ths_mg; +} ism330bx_act_thresholds_t; +int32_t ism330bx_act_thresholds_set(const stmdev_ctx_t *ctx, + ism330bx_act_thresholds_t val); +int32_t ism330bx_act_thresholds_get(const stmdev_ctx_t *ctx, + ism330bx_act_thresholds_t *val); + +typedef struct +{ + uint8_t shock : 2; + uint8_t quiet : 4; +} ism330bx_act_wkup_time_windows_t; +int32_t ism330bx_act_wkup_time_windows_set(const stmdev_ctx_t *ctx, + ism330bx_act_wkup_time_windows_t val); +int32_t ism330bx_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, + ism330bx_act_wkup_time_windows_t *val); + +typedef struct +{ + uint8_t tap_x_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_z_en : 1; +} ism330bx_tap_detection_t; +int32_t ism330bx_tap_detection_set(const stmdev_ctx_t *ctx, + ism330bx_tap_detection_t val); +int32_t ism330bx_tap_detection_get(const stmdev_ctx_t *ctx, + ism330bx_tap_detection_t *val); + +typedef struct +{ + uint8_t x : 1; + uint8_t y : 1; + uint8_t z : 1; +} ism330bx_tap_thresholds_t; +int32_t ism330bx_tap_thresholds_set(const stmdev_ctx_t *ctx, + ism330bx_tap_thresholds_t val); +int32_t ism330bx_tap_thresholds_get(const stmdev_ctx_t *ctx, + ism330bx_tap_thresholds_t *val); + + +typedef enum +{ + ISM330BX_XYZ = 0x3, + ISM330BX_YXZ = 0x5, + ISM330BX_XZY = 0x6, + ISM330BX_ZYX = 0x0, + ISM330BX_YZX = 0x1, + ISM330BX_ZXY = 0x2, +} ism330bx_tap_axis_priority_t; +int32_t ism330bx_tap_axis_priority_set(const stmdev_ctx_t *ctx, + ism330bx_tap_axis_priority_t val); +int32_t ism330bx_tap_axis_priority_get(const stmdev_ctx_t *ctx, + ism330bx_tap_axis_priority_t *val); + +typedef struct +{ + uint8_t shock : 1; + uint8_t quiet : 1; + uint8_t tap_gap : 1; +} ism330bx_tap_time_windows_t; +int32_t ism330bx_tap_time_windows_set(const stmdev_ctx_t *ctx, + ism330bx_tap_time_windows_t val); +int32_t ism330bx_tap_time_windows_get(const stmdev_ctx_t *ctx, + ism330bx_tap_time_windows_t *val); + +typedef enum +{ + ISM330BX_ONLY_SINGLE = 0x0, + ISM330BX_BOTH_SINGLE_DOUBLE = 0x1, +} ism330bx_tap_mode_t; +int32_t ism330bx_tap_mode_set(const stmdev_ctx_t *ctx, ism330bx_tap_mode_t val); +int32_t ism330bx_tap_mode_get(const stmdev_ctx_t *ctx, + ism330bx_tap_mode_t *val); + +typedef enum +{ + ISM330BX_DEG_80 = 0x0, + ISM330BX_DEG_70 = 0x1, + ISM330BX_DEG_60 = 0x2, + ISM330BX_DEG_50 = 0x3, +} ism330bx_6d_threshold_t; +int32_t ism330bx_6d_threshold_set(const stmdev_ctx_t *ctx, + ism330bx_6d_threshold_t val); +int32_t ism330bx_6d_threshold_get(const stmdev_ctx_t *ctx, + ism330bx_6d_threshold_t *val); + +int32_t ism330bx_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM330BX_156_mg = 0x0, + ISM330BX_219_mg = 0x1, + ISM330BX_250_mg = 0x2, + ISM330BX_312_mg = 0x3, + ISM330BX_344_mg = 0x4, + ISM330BX_406_mg = 0x5, + ISM330BX_469_mg = 0x6, + ISM330BX_500_mg = 0x7, +} ism330bx_ff_thresholds_t; +int32_t ism330bx_ff_thresholds_set(const stmdev_ctx_t *ctx, + ism330bx_ff_thresholds_t val); +int32_t ism330bx_ff_thresholds_get(const stmdev_ctx_t *ctx, + ism330bx_ff_thresholds_t *val); + +int32_t ism330bx_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism330bx_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM330BX_CMP_DISABLE = 0x0, + ISM330BX_CMP_8_TO_1 = 0x1, + ISM330BX_CMP_16_TO_1 = 0x2, + ISM330BX_CMP_32_TO_1 = 0x3, +} ism330bx_fifo_compress_algo_t; +int32_t ism330bx_fifo_compress_algo_set(const stmdev_ctx_t *ctx, + ism330bx_fifo_compress_algo_t val); +int32_t ism330bx_fifo_compress_algo_get(const stmdev_ctx_t *ctx, + ism330bx_fifo_compress_algo_t *val); + +int32_t ism330bx_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, + uint8_t val); +int32_t ism330bx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t ism330bx_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, + uint8_t val); +int32_t ism330bx_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t ism330bx_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM330BX_XL_NOT_BATCHED = 0x0, + ISM330BX_XL_BATCHED_AT_1Hz875 = 0x1, + ISM330BX_XL_BATCHED_AT_7Hz5 = 0x2, + ISM330BX_XL_BATCHED_AT_15Hz = 0x3, + ISM330BX_XL_BATCHED_AT_30Hz = 0x4, + ISM330BX_XL_BATCHED_AT_60Hz = 0x5, + ISM330BX_XL_BATCHED_AT_120Hz = 0x6, + ISM330BX_XL_BATCHED_AT_240Hz = 0x7, + ISM330BX_XL_BATCHED_AT_480Hz = 0x8, + ISM330BX_XL_BATCHED_AT_960Hz = 0x9, + ISM330BX_XL_BATCHED_AT_1920Hz = 0xA, + ISM330BX_XL_BATCHED_AT_3840Hz = 0xB, +} ism330bx_fifo_xl_batch_t; +int32_t ism330bx_fifo_xl_batch_set(const stmdev_ctx_t *ctx, + ism330bx_fifo_xl_batch_t val); +int32_t ism330bx_fifo_xl_batch_get(const stmdev_ctx_t *ctx, + ism330bx_fifo_xl_batch_t *val); + +typedef enum +{ + ISM330BX_GY_NOT_BATCHED = 0x0, + ISM330BX_GY_BATCHED_AT_1Hz875 = 0x1, + ISM330BX_GY_BATCHED_AT_7Hz5 = 0x2, + ISM330BX_GY_BATCHED_AT_15Hz = 0x3, + ISM330BX_GY_BATCHED_AT_30Hz = 0x4, + ISM330BX_GY_BATCHED_AT_60Hz = 0x5, + ISM330BX_GY_BATCHED_AT_120Hz = 0x6, + ISM330BX_GY_BATCHED_AT_240Hz = 0x7, + ISM330BX_GY_BATCHED_AT_480Hz = 0x8, + ISM330BX_GY_BATCHED_AT_960Hz = 0x9, + ISM330BX_GY_BATCHED_AT_1920Hz = 0xa, + ISM330BX_GY_BATCHED_AT_3840Hz = 0xb, +} ism330bx_fifo_gy_batch_t; +int32_t ism330bx_fifo_gy_batch_set(const stmdev_ctx_t *ctx, + ism330bx_fifo_gy_batch_t val); +int32_t ism330bx_fifo_gy_batch_get(const stmdev_ctx_t *ctx, + ism330bx_fifo_gy_batch_t *val); + +typedef enum +{ + ISM330BX_BYPASS_MODE = 0x0, + ISM330BX_FIFO_MODE = 0x1, + ISM330BX_STREAM_WTM_TO_FULL_MODE = 0x2, + ISM330BX_STREAM_TO_FIFO_MODE = 0x3, + ISM330BX_BYPASS_TO_STREAM_MODE = 0x4, + ISM330BX_STREAM_MODE = 0x6, + ISM330BX_BYPASS_TO_FIFO_MODE = 0x7, +} ism330bx_fifo_mode_t; +int32_t ism330bx_fifo_mode_set(const stmdev_ctx_t *ctx, + ism330bx_fifo_mode_t val); +int32_t ism330bx_fifo_mode_get(const stmdev_ctx_t *ctx, + ism330bx_fifo_mode_t *val); + +typedef enum +{ + ISM330BX_TEMP_NOT_BATCHED = 0x0, + ISM330BX_TEMP_BATCHED_AT_1Hz875 = 0x1, + ISM330BX_TEMP_BATCHED_AT_15Hz = 0x2, + ISM330BX_TEMP_BATCHED_AT_60Hz = 0x3, +} ism330bx_fifo_temp_batch_t; +int32_t ism330bx_fifo_temp_batch_set(const stmdev_ctx_t *ctx, + ism330bx_fifo_temp_batch_t val); +int32_t ism330bx_fifo_temp_batch_get(const stmdev_ctx_t *ctx, + ism330bx_fifo_temp_batch_t *val); + +typedef enum +{ + ISM330BX_TMSTMP_NOT_BATCHED = 0x0, + ISM330BX_TMSTMP_DEC_1 = 0x1, + ISM330BX_TMSTMP_DEC_8 = 0x2, + ISM330BX_TMSTMP_DEC_32 = 0x3, +} ism330bx_fifo_timestamp_batch_t; +int32_t ism330bx_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx, + ism330bx_fifo_timestamp_batch_t val); +int32_t ism330bx_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, + ism330bx_fifo_timestamp_batch_t *val); + +int32_t ism330bx_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx, + uint16_t val); +int32_t ism330bx_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx, + uint16_t *val); + +int32_t ism330bx_fifo_batch_ah_qvar_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_fifo_batch_ah_qvar_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM330BX_XL_BATCH_EVENT = 0x0, + ISM330BX_GY_BATCH_EVENT = 0x1, +} ism330bx_fifo_batch_cnt_event_t; +int32_t ism330bx_fifo_batch_cnt_event_set(const stmdev_ctx_t *ctx, + ism330bx_fifo_batch_cnt_event_t val); +int32_t ism330bx_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx, + ism330bx_fifo_batch_cnt_event_t *val); + +typedef struct +{ + uint8_t game_rotation : 1; + uint8_t gravity : 1; + uint8_t gbias : 1; +} ism330bx_fifo_sflp_raw_t; +int32_t ism330bx_fifo_sflp_batch_set(const stmdev_ctx_t *ctx, + ism330bx_fifo_sflp_raw_t val); +int32_t ism330bx_fifo_sflp_batch_get(const stmdev_ctx_t *ctx, + ism330bx_fifo_sflp_raw_t *val); + +typedef struct +{ + uint16_t fifo_level : 9; + uint8_t fifo_bdr : 1; + uint8_t fifo_full : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_th : 1; +} ism330bx_fifo_status_t; + +int32_t ism330bx_fifo_status_get(const stmdev_ctx_t *ctx, + ism330bx_fifo_status_t *val); + +typedef struct +{ + enum + { + ISM330BX_FIFO_EMPTY = 0x0, + ISM330BX_GY_NC_TAG = 0x1, + ISM330BX_XL_NC_TAG = 0x2, + ISM330BX_TEMPERATURE_TAG = 0x3, + ISM330BX_TIMESTAMP_TAG = 0x4, + ISM330BX_CFG_CHANGE_TAG = 0x5, + ISM330BX_XL_NC_T_2_TAG = 0x6, + ISM330BX_XL_NC_T_1_TAG = 0x7, + ISM330BX_XL_2XC_TAG = 0x8, + ISM330BX_XL_3XC_TAG = 0x9, + ISM330BX_GY_NC_T_2_TAG = 0xA, + ISM330BX_GY_NC_T_1_TAG = 0xB, + ISM330BX_GY_2XC_TAG = 0xC, + ISM330BX_GY_3XC_TAG = 0xD, + ISM330BX_STEP_COUNTER_TAG = 0x12, + ISM330BX_SFLP_GAME_ROTATION_VECTOR_TAG = 0x13, + ISM330BX_SFLP_GYROSCOPE_BIAS_TAG = 0x16, + ISM330BX_SFLP_GRAVITY_VECTOR_TAG = 0x17, + ISM330BX_MLC_RESULT_TAG = 0x1A, + ISM330BX_MLC_FILTER = 0x1B, + ISM330BX_MLC_FEATURE = 0x1C, + ISM330BX_XL_DUAL_CORE = 0x1D, + ISM330BX_AH_QVAR = 0x1F, + } tag; + uint8_t cnt; + uint8_t data[6]; +} ism330bx_fifo_out_raw_t; +int32_t ism330bx_fifo_out_raw_get(const stmdev_ctx_t *ctx, + ism330bx_fifo_out_raw_t *val); + +int32_t ism330bx_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism330bx_fifo_mlc_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_fifo_mlc_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism330bx_fifo_mlc_filt_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_fifo_mlc_filt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t step_counter_enable : 1; + uint8_t false_step_rej : 1; +} ism330bx_stpcnt_mode_t; +int32_t ism330bx_stpcnt_mode_set(const stmdev_ctx_t *ctx, + ism330bx_stpcnt_mode_t val); +int32_t ism330bx_stpcnt_mode_get(const stmdev_ctx_t *ctx, + ism330bx_stpcnt_mode_t *val); + +int32_t ism330bx_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t ism330bx_stpcnt_rst_step_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism330bx_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism330bx_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t ism330bx_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t ism330bx_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism330bx_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism330bx_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t ism330bx_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint16_t *val); + +typedef struct +{ + float_t gbias_x; /* dps */ + float_t gbias_y; /* dps */ + float_t gbias_z; /* dps */ +} ism330bx_sflp_gbias_t; +int32_t ism330bx_sflp_game_gbias_set(const stmdev_ctx_t *ctx, + ism330bx_sflp_gbias_t *val); + +int32_t ism330bx_sflp_configure(const stmdev_ctx_t *ctx); + +typedef enum +{ + ISM330BX_SFLP_15Hz = 0x0, + ISM330BX_SFLP_30Hz = 0x1, + ISM330BX_SFLP_60Hz = 0x2, + ISM330BX_SFLP_120Hz = 0x3, + ISM330BX_SFLP_240Hz = 0x4, + ISM330BX_SFLP_480Hz = 0x5, +} ism330bx_sflp_data_rate_t; +int32_t ism330bx_sflp_data_rate_set(const stmdev_ctx_t *ctx, + ism330bx_sflp_data_rate_t val); +int32_t ism330bx_sflp_data_rate_get(const stmdev_ctx_t *ctx, + ism330bx_sflp_data_rate_t *val); + +typedef enum +{ + ISM330BX_PROTECT_CTRL_REGS = 0x0, + ISM330BX_WRITE_CTRL_REG = 0x1, +} ism330bx_fsm_permission_t; +int32_t ism330bx_fsm_permission_set(const stmdev_ctx_t *ctx, + ism330bx_fsm_permission_t val); +int32_t ism330bx_fsm_permission_get(const stmdev_ctx_t *ctx, + ism330bx_fsm_permission_t *val); + +typedef enum +{ + ISM330BX_STD_IF_CONTROL = 0x0, + ISM330BX_FSM_CONTROL = 0x1, +} ism330bx_fsm_permission_status_t; +int32_t ism330bx_fsm_permission_status(const stmdev_ctx_t *ctx, + ism330bx_fsm_permission_status_t *val); + +typedef struct +{ + uint8_t fsm1_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm8_en : 1; +} ism330bx_fsm_mode_t; +int32_t ism330bx_fsm_mode_set(const stmdev_ctx_t *ctx, ism330bx_fsm_mode_t val); +int32_t ism330bx_fsm_mode_get(const stmdev_ctx_t *ctx, + ism330bx_fsm_mode_t *val); + +int32_t ism330bx_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t ism330bx_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); + +typedef struct +{ + uint8_t fsm_outs1; + uint8_t fsm_outs2; + uint8_t fsm_outs3; + uint8_t fsm_outs4; + uint8_t fsm_outs5; + uint8_t fsm_outs6; + uint8_t fsm_outs7; + uint8_t fsm_outs8; +} ism330bx_fsm_out_t; +int32_t ism330bx_fsm_out_get(const stmdev_ctx_t *ctx, ism330bx_fsm_out_t *val); + +typedef enum +{ + ISM330BX_FSM_15Hz = 0x0, + ISM330BX_FSM_30Hz = 0x1, + ISM330BX_FSM_60Hz = 0x2, + ISM330BX_FSM_120Hz = 0x3, + ISM330BX_FSM_240Hz = 0x4, + ISM330BX_FSM_480Hz = 0x5, + ISM330BX_FSM_960Hz = 0x6, +} ism330bx_fsm_data_rate_t; +int32_t ism330bx_fsm_data_rate_set(const stmdev_ctx_t *ctx, + ism330bx_fsm_data_rate_t val); +int32_t ism330bx_fsm_data_rate_get(const stmdev_ctx_t *ctx, + ism330bx_fsm_data_rate_t *val); + +int32_t ism330bx_fsm_long_cnt_timeout_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t ism330bx_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t ism330bx_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism330bx_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t ism330bx_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); + +typedef enum +{ + ISM330BX_MLC_OFF = 0x0, + ISM330BX_MLC_ON = 0x1, + ISM330BX_MLC_ON_BEFORE_FSM = 0x2, +} ism330bx_mlc_mode_t; +int32_t ism330bx_mlc_set(const stmdev_ctx_t *ctx, ism330bx_mlc_mode_t val); +int32_t ism330bx_mlc_get(const stmdev_ctx_t *ctx, ism330bx_mlc_mode_t *val); + +typedef enum +{ + ISM330BX_MLC_15Hz = 0x0, + ISM330BX_MLC_30Hz = 0x1, + ISM330BX_MLC_60Hz = 0x2, + ISM330BX_MLC_120Hz = 0x3, + ISM330BX_MLC_240Hz = 0x4, + ISM330BX_MLC_480Hz = 0x5, + ISM330BX_MLC_960Hz = 0x6, +} ism330bx_mlc_data_rate_t; +int32_t ism330bx_mlc_data_rate_set(const stmdev_ctx_t *ctx, + ism330bx_mlc_data_rate_t val); +int32_t ism330bx_mlc_data_rate_get(const stmdev_ctx_t *ctx, + ism330bx_mlc_data_rate_t *val); + +typedef struct +{ + uint8_t mlc1_src; + uint8_t mlc2_src; + uint8_t mlc3_src; + uint8_t mlc4_src; +} ism330bx_mlc_out_t; +int32_t ism330bx_mlc_out_get(const stmdev_ctx_t *ctx, ism330bx_mlc_out_t *val); + +int32_t ism330bx_mlc_qvar_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t ism330bx_mlc_qvar_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t ism330bx_xl_offset_on_out_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + float_t z_mg; + float_t y_mg; + float_t x_mg; +} ism330bx_xl_offset_mg_t; +int32_t ism330bx_xl_offset_mg_set(const stmdev_ctx_t *ctx, + ism330bx_xl_offset_mg_t val); +int32_t ism330bx_xl_offset_mg_get(const stmdev_ctx_t *ctx, + ism330bx_xl_offset_mg_t *val); + +typedef struct +{ + uint8_t ah_qvar1_en : 1; + uint8_t ah_qvar2_en : 1; + uint8_t swaps : 1; +} ism330bx_ah_qvar_mode_t; +int32_t ism330bx_ah_qvar_mode_set(const stmdev_ctx_t *ctx, + ism330bx_ah_qvar_mode_t val); +int32_t ism330bx_ah_qvar_mode_get(const stmdev_ctx_t *ctx, + ism330bx_ah_qvar_mode_t *val); + +typedef enum +{ + ISM330BX_2400MOhm = 0x0, + ISM330BX_730MOhm = 0x1, + ISM330BX_300MOhm = 0x2, + ISM330BX_255MOhm = 0x3, +} ism330bx_ah_qvar_zin_t; +int32_t ism330bx_ah_qvar_zin_set(const stmdev_ctx_t *ctx, + ism330bx_ah_qvar_zin_t val); +int32_t ism330bx_ah_qvar_zin_get(const stmdev_ctx_t *ctx, + ism330bx_ah_qvar_zin_t *val); + +int32_t ism330bx_fsm_qvar_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t ism330bx_fsm_qvar_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); + +typedef enum +{ + ISM330BX_SW_RST_DYN_ADDRESS_RST = 0x0, + ISM330BX_I3C_GLOBAL_RST = 0x1, +} ism330bx_i3c_reset_mode_t; +int32_t ism330bx_i3c_reset_mode_set(const stmdev_ctx_t *ctx, + ism330bx_i3c_reset_mode_t val); +int32_t ism330bx_i3c_reset_mode_get(const stmdev_ctx_t *ctx, + ism330bx_i3c_reset_mode_t *val); + +int32_t ism330bx_tdm_dis_wclk_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_tdm_dis_wclk_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t ism330bx_tdm_tdmout_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_tdm_tdmout_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM330BX_WCLK_16kHZ_BCLK_2048kHz = 0x1, + ISM330BX_WCLK_8kHZ_BCLK_2048kHz = 0x4, +} ism330bx_tdm_wclk_bclk_t; +int32_t ism330bx_tdm_wclk_bclk_set(const stmdev_ctx_t *ctx, + ism330bx_tdm_wclk_bclk_t val); +int32_t ism330bx_tdm_wclk_bclk_get(const stmdev_ctx_t *ctx, + ism330bx_tdm_wclk_bclk_t *val); + +typedef enum +{ + ISM330BX_SLOT_012 = 0x0, + ISM330BX_SLOT_456 = 0x1, +} ism330bx_tdm_slot_t; +int32_t ism330bx_tdm_slot_set(const stmdev_ctx_t *ctx, ism330bx_tdm_slot_t val); +int32_t ism330bx_tdm_slot_get(const stmdev_ctx_t *ctx, + ism330bx_tdm_slot_t *val); + +typedef enum +{ + ISM330BX_BCLK_RISING = 0x0, + ISM330BX_BCLK_FALLING = 0x1, +} ism330bx_tdm_bclk_edge_t; +int32_t ism330bx_tdm_bclk_edge_set(const stmdev_ctx_t *ctx, + ism330bx_tdm_bclk_edge_t val); +int32_t ism330bx_tdm_bclk_edge_get(const stmdev_ctx_t *ctx, + ism330bx_tdm_bclk_edge_t *val); + +int32_t ism330bx_tdm_delayed_conf_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330bx_tdm_delayed_conf_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ISM330BX_TDM_ORDER_ZYX = 0x0, + ISM330BX_TDM_ORDER_XZY = 0x1, + ISM330BX_TDM_ORDER_XYZ = 0x2, +} ism330bx_tdm_axis_order_t; +int32_t ism330bx_tdm_axis_order_set(const stmdev_ctx_t *ctx, + ism330bx_tdm_axis_order_t val); +int32_t ism330bx_tdm_axis_order_get(const stmdev_ctx_t *ctx, + ism330bx_tdm_axis_order_t *val); + +typedef enum +{ + ISM330BX_TDM_2g = 0x0, + ISM330BX_TDM_4g = 0x1, + ISM330BX_TDM_8g = 0x2, +} ism330bx_tdm_xl_full_scale_t; +int32_t ism330bx_tdm_xl_full_scale_set(const stmdev_ctx_t *ctx, + ism330bx_tdm_xl_full_scale_t val); +int32_t ism330bx_tdm_xl_full_scale_get(const stmdev_ctx_t *ctx, + ism330bx_tdm_xl_full_scale_t *val); + +/** + * @} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /*ISM330BX_DRIVER_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.c b/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.c index 4a785df2..bc38955a 100644 --- a/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.c +++ b/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.c @@ -46,11 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak ism330dhcx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak ism330dhcx_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -66,11 +72,17 @@ int32_t __weak ism330dhcx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak ism330dhcx_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak ism330dhcx_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -169,7 +181,7 @@ float_t ism330dhcx_from_lsb_to_nsec(int32_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_full_scale_set(const stmdev_ctx_t *ctx, ism330dhcx_fs_xl_t val) { ism330dhcx_ctrl1_xl_t ctrl1_xl; @@ -195,7 +207,7 @@ int32_t ism330dhcx_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_full_scale_get(const stmdev_ctx_t *ctx, ism330dhcx_fs_xl_t *val) { ism330dhcx_ctrl1_xl_t ctrl1_xl; @@ -237,7 +249,7 @@ int32_t ism330dhcx_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_data_rate_set(const stmdev_ctx_t *ctx, ism330dhcx_odr_xl_t val) { ism330dhcx_odr_xl_t odr_xl = val; @@ -494,7 +506,7 @@ int32_t ism330dhcx_xl_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_data_rate_get(const stmdev_ctx_t *ctx, ism330dhcx_odr_xl_t *val) { ism330dhcx_ctrl1_xl_t ctrl1_xl; @@ -568,7 +580,7 @@ int32_t ism330dhcx_xl_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_gy_full_scale_set(const stmdev_ctx_t *ctx, ism330dhcx_fs_g_t val) { ism330dhcx_ctrl2_g_t ctrl2_g; @@ -594,7 +606,7 @@ int32_t ism330dhcx_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_gy_full_scale_get(const stmdev_ctx_t *ctx, ism330dhcx_fs_g_t *val) { ism330dhcx_ctrl2_g_t ctrl2_g; @@ -644,7 +656,7 @@ int32_t ism330dhcx_gy_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_gy_data_rate_set(const stmdev_ctx_t *ctx, ism330dhcx_odr_g_t val) { ism330dhcx_odr_g_t odr_gy = val; @@ -901,7 +913,7 @@ int32_t ism330dhcx_gy_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_gy_data_rate_get(const stmdev_ctx_t *ctx, ism330dhcx_odr_g_t *val) { ism330dhcx_ctrl2_g_t ctrl2_g; @@ -971,7 +983,7 @@ int32_t ism330dhcx_gy_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_block_data_update_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_ctrl3_c_t ctrl3_c; @@ -997,7 +1009,7 @@ int32_t ism330dhcx_block_data_update_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_block_data_update_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_ctrl3_c_t ctrl3_c; @@ -1018,7 +1030,7 @@ int32_t ism330dhcx_block_data_update_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_offset_weight_set(const stmdev_ctx_t *ctx, ism330dhcx_usr_off_w_t val) { ism330dhcx_ctrl6_c_t ctrl6_c; @@ -1045,7 +1057,7 @@ int32_t ism330dhcx_xl_offset_weight_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_offset_weight_get(const stmdev_ctx_t *ctx, ism330dhcx_usr_off_w_t *val) { ism330dhcx_ctrl6_c_t ctrl6_c; @@ -1079,7 +1091,7 @@ int32_t ism330dhcx_xl_offset_weight_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_power_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_power_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_xl_hm_mode_t val) { ism330dhcx_ctrl6_c_t ctrl6_c; @@ -1105,7 +1117,7 @@ int32_t ism330dhcx_xl_power_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_power_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_power_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_xl_hm_mode_t *val) { ism330dhcx_ctrl6_c_t ctrl6_c; @@ -1139,7 +1151,7 @@ int32_t ism330dhcx_xl_power_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_gy_power_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_gy_power_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_g_hm_mode_t val) { ism330dhcx_ctrl7_g_t ctrl7_g; @@ -1165,7 +1177,7 @@ int32_t ism330dhcx_gy_power_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_gy_power_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_gy_power_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_g_hm_mode_t *val) { ism330dhcx_ctrl7_g_t ctrl7_g; @@ -1201,7 +1213,7 @@ int32_t ism330dhcx_gy_power_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_all_sources_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_all_sources_get(const stmdev_ctx_t *ctx, ism330dhcx_all_sources_t *val) { int32_t ret; @@ -1271,7 +1283,7 @@ int32_t ism330dhcx_all_sources_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_status_reg_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_status_reg_get(const stmdev_ctx_t *ctx, ism330dhcx_status_reg_t *val) { int32_t ret; @@ -1288,7 +1300,7 @@ int32_t ism330dhcx_status_reg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_status_reg_t status_reg; @@ -1308,7 +1320,7 @@ int32_t ism330dhcx_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_status_reg_t status_reg; @@ -1328,7 +1340,7 @@ int32_t ism330dhcx_gy_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_status_reg_t status_reg; @@ -1350,7 +1362,7 @@ int32_t ism330dhcx_temp_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_usr_offset_x_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1369,7 +1381,7 @@ int32_t ism330dhcx_xl_usr_offset_x_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_usr_offset_x_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1388,7 +1400,7 @@ int32_t ism330dhcx_xl_usr_offset_x_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_usr_offset_y_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1407,7 +1419,7 @@ int32_t ism330dhcx_xl_usr_offset_y_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_usr_offset_y_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1426,7 +1438,7 @@ int32_t ism330dhcx_xl_usr_offset_y_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_usr_offset_z_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1445,7 +1457,7 @@ int32_t ism330dhcx_xl_usr_offset_z_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_usr_offset_z_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1462,7 +1474,7 @@ int32_t ism330dhcx_xl_usr_offset_z_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_ctrl7_g_t ctrl7_g; int32_t ret; @@ -1487,7 +1499,7 @@ int32_t ism330dhcx_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_ctrl7_g_t ctrl7_g; int32_t ret; @@ -1518,7 +1530,7 @@ int32_t ism330dhcx_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_timestamp_rst(stmdev_ctx_t *ctx) +int32_t ism330dhcx_timestamp_rst(const stmdev_ctx_t *ctx) { uint8_t rst_val = 0xAA; return ism330dhcx_write_reg(ctx, ISM330DHCX_TIMESTAMP2, &rst_val, 1); @@ -1532,7 +1544,7 @@ int32_t ism330dhcx_timestamp_rst(stmdev_ctx_t *ctx) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_ctrl10_c_t ctrl10_c; int32_t ret; @@ -1557,7 +1569,7 @@ int32_t ism330dhcx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_ctrl10_c_t ctrl10_c; int32_t ret; @@ -1578,7 +1590,7 @@ int32_t ism330dhcx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t ism330dhcx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; @@ -1611,7 +1623,7 @@ int32_t ism330dhcx_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_rounding_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_rounding_t val) { ism330dhcx_ctrl5_c_t ctrl5_c; @@ -1637,7 +1649,7 @@ int32_t ism330dhcx_rounding_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_rounding_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_rounding_t *val) { ism330dhcx_ctrl5_c_t ctrl5_c; @@ -1681,7 +1693,7 @@ int32_t ism330dhcx_rounding_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; @@ -1702,7 +1714,7 @@ int32_t ism330dhcx_temperature_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_angular_rate_raw_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -1727,7 +1739,7 @@ int32_t ism330dhcx_angular_rate_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -1751,7 +1763,7 @@ int32_t ism330dhcx_acceleration_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ism330dhcx_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_FIFO_DATA_OUT_X_L, buff, 6); @@ -1767,7 +1779,7 @@ int32_t ism330dhcx_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_number_of_steps_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_number_of_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -1796,7 +1808,7 @@ int32_t ism330dhcx_number_of_steps_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_steps_reset(stmdev_ctx_t *ctx) +int32_t ism330dhcx_steps_reset(const stmdev_ctx_t *ctx) { ism330dhcx_emb_func_src_t emb_func_src; int32_t ret; @@ -1830,7 +1842,7 @@ int32_t ism330dhcx_steps_reset(stmdev_ctx_t *ctx) * @param uint8_t * : buffer that stores data read * */ -int32_t ism330dhcx_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ism330dhcx_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; ret = ism330dhcx_mem_bank_set(ctx, ISM330DHCX_EMBEDDED_FUNC_BANK); @@ -1868,7 +1880,7 @@ int32_t ism330dhcx_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_device_conf_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_device_conf_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -1893,7 +1905,7 @@ int32_t ism330dhcx_device_conf_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_device_conf_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_device_conf_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -1914,7 +1926,7 @@ int32_t ism330dhcx_device_conf_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_internal_freq_fine_t internal_freq_fine; int32_t ret; @@ -1941,7 +1953,7 @@ int32_t ism330dhcx_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_internal_freq_fine_t internal_freq_fine; int32_t ret; @@ -1961,7 +1973,7 @@ int32_t ism330dhcx_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_mem_bank_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mem_bank_set(const stmdev_ctx_t *ctx, ism330dhcx_reg_access_t val) { ism330dhcx_func_cfg_access_t func_cfg_access; @@ -1988,7 +2000,7 @@ int32_t ism330dhcx_mem_bank_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_mem_bank_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mem_bank_get(const stmdev_ctx_t *ctx, ism330dhcx_reg_access_t *val) { ism330dhcx_func_cfg_access_t func_cfg_access; @@ -2027,7 +2039,7 @@ int32_t ism330dhcx_mem_bank_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add, +int32_t ism330dhcx_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t add, uint8_t *val) { ism330dhcx_page_rw_t page_rw; @@ -2106,7 +2118,7 @@ int32_t ism330dhcx_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add, +int32_t ism330dhcx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t add, uint8_t *buf, uint8_t len) { ism330dhcx_page_rw_t page_rw; @@ -2221,7 +2233,7 @@ int32_t ism330dhcx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add, +int32_t ism330dhcx_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, uint8_t *val) { ism330dhcx_page_rw_t page_rw; @@ -2299,7 +2311,7 @@ int32_t ism330dhcx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_data_ready_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_dataready_pulsed_t val) { ism330dhcx_counter_bdr_reg1_t counter_bdr_reg1; @@ -2326,7 +2338,7 @@ int32_t ism330dhcx_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_data_ready_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_dataready_pulsed_t *val) { ism330dhcx_counter_bdr_reg1_t counter_bdr_reg1; @@ -2360,7 +2372,7 @@ int32_t ism330dhcx_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ism330dhcx_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; ret = ism330dhcx_read_reg(ctx, ISM330DHCX_WHO_AM_I, buff, 1); @@ -2376,7 +2388,7 @@ int32_t ism330dhcx_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2401,7 +2413,7 @@ int32_t ism330dhcx_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2421,7 +2433,7 @@ int32_t ism330dhcx_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2447,7 +2459,7 @@ int32_t ism330dhcx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2466,7 +2478,7 @@ int32_t ism330dhcx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2491,7 +2503,7 @@ int32_t ism330dhcx_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2512,7 +2524,7 @@ int32_t ism330dhcx_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_self_test_set(const stmdev_ctx_t *ctx, ism330dhcx_st_xl_t val) { ism330dhcx_ctrl5_c_t ctrl5_c; @@ -2538,7 +2550,7 @@ int32_t ism330dhcx_xl_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_self_test_get(const stmdev_ctx_t *ctx, ism330dhcx_st_xl_t *val) { ism330dhcx_ctrl5_c_t ctrl5_c; @@ -2576,7 +2588,7 @@ int32_t ism330dhcx_xl_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_gy_self_test_set(const stmdev_ctx_t *ctx, ism330dhcx_st_g_t val) { ism330dhcx_ctrl5_c_t ctrl5_c; @@ -2602,7 +2614,7 @@ int32_t ism330dhcx_gy_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_gy_self_test_get(const stmdev_ctx_t *ctx, ism330dhcx_st_g_t *val) { ism330dhcx_ctrl5_c_t ctrl5_c; @@ -2653,7 +2665,7 @@ int32_t ism330dhcx_gy_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_ctrl1_xl_t ctrl1_xl; int32_t ret; @@ -2678,7 +2690,7 @@ int32_t ism330dhcx_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_ctrl1_xl_t ctrl1_xl; int32_t ret; @@ -2698,7 +2710,7 @@ int32_t ism330dhcx_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_ctrl4_c_t ctrl4_c; int32_t ret; @@ -2724,7 +2736,7 @@ int32_t ism330dhcx_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_ctrl4_c_t ctrl4_c; int32_t ret; @@ -2744,7 +2756,7 @@ int32_t ism330dhcx_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_ctrl4_c_t ctrl4_c; @@ -2771,7 +2783,7 @@ int32_t ism330dhcx_filter_settling_mask_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_ctrl4_c_t ctrl4_c; @@ -2791,7 +2803,7 @@ int32_t ism330dhcx_filter_settling_mask_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, ism330dhcx_ftype_t val) { ism330dhcx_ctrl6_c_t ctrl6_c; @@ -2817,7 +2829,7 @@ int32_t ism330dhcx_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, ism330dhcx_ftype_t *val) { ism330dhcx_ctrl6_c_t ctrl6_c; @@ -2875,7 +2887,7 @@ int32_t ism330dhcx_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -2900,7 +2912,7 @@ int32_t ism330dhcx_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -2920,7 +2932,7 @@ int32_t ism330dhcx_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, ism330dhcx_hp_slope_xl_en_t val) { ism330dhcx_ctrl8_xl_t ctrl8_xl; @@ -2949,7 +2961,7 @@ int32_t ism330dhcx_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, ism330dhcx_hp_slope_xl_en_t *val) { ism330dhcx_ctrl8_xl_t ctrl8_xl; @@ -3071,7 +3083,7 @@ int32_t ism330dhcx_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_fast_settling_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_ctrl8_xl_t ctrl8_xl; @@ -3099,7 +3111,7 @@ int32_t ism330dhcx_xl_fast_settling_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_fast_settling_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_ctrl8_xl_t ctrl8_xl; @@ -3120,7 +3132,7 @@ int32_t ism330dhcx_xl_fast_settling_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, ism330dhcx_slope_fds_t val) { ism330dhcx_tap_cfg0_t tap_cfg0; @@ -3147,7 +3159,7 @@ int32_t ism330dhcx_xl_hp_path_internal_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, ism330dhcx_slope_fds_t *val) { ism330dhcx_tap_cfg0_t tap_cfg0; @@ -3182,7 +3194,7 @@ int32_t ism330dhcx_xl_hp_path_internal_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_gy_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, ism330dhcx_hpm_g_t val) { ism330dhcx_ctrl7_g_t ctrl7_g; @@ -3210,7 +3222,7 @@ int32_t ism330dhcx_gy_hp_path_internal_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_gy_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, ism330dhcx_hpm_g_t *val) { ism330dhcx_ctrl7_g_t ctrl7_g; @@ -3270,7 +3282,7 @@ int32_t ism330dhcx_gy_hp_path_internal_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_sdo_ocs_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_ois_pu_dis_t val) { ism330dhcx_pin_ctrl_t pin_ctrl; @@ -3297,7 +3309,7 @@ int32_t ism330dhcx_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_sdo_ocs_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_ois_pu_dis_t *val) { ism330dhcx_pin_ctrl_t pin_ctrl; @@ -3331,7 +3343,7 @@ int32_t ism330dhcx_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_pw_on_ctrl_set(const stmdev_ctx_t *ctx, ism330dhcx_ois_on_t val) { ism330dhcx_ctrl7_g_t ctrl7_g; @@ -3358,7 +3370,7 @@ int32_t ism330dhcx_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_pw_on_ctrl_get(const stmdev_ctx_t *ctx, ism330dhcx_ois_on_t *val) { ism330dhcx_ctrl7_g_t ctrl7_g; @@ -3392,7 +3404,7 @@ int32_t ism330dhcx_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_status_reg_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_status_reg_get(const stmdev_ctx_t *ctx, ism330dhcx_status_spiaux_t *val) { int32_t ret; @@ -3410,7 +3422,7 @@ int32_t ism330dhcx_aux_status_reg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_status_spiaux_t status_spiaux; @@ -3430,7 +3442,7 @@ int32_t ism330dhcx_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_status_spiaux_t status_spiaux; @@ -3450,7 +3462,7 @@ int32_t ism330dhcx_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_status_spiaux_t status_spiaux; @@ -3471,7 +3483,7 @@ int32_t ism330dhcx_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_xl_self_test_set(const stmdev_ctx_t *ctx, ism330dhcx_st_xl_ois_t val) { ism330dhcx_int_ois_t int_ois; @@ -3498,7 +3510,7 @@ int32_t ism330dhcx_aux_xl_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_xl_self_test_get(const stmdev_ctx_t *ctx, ism330dhcx_st_xl_ois_t *val) { ism330dhcx_int_ois_t int_ois; @@ -3536,7 +3548,7 @@ int32_t ism330dhcx_aux_xl_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_den_polarity_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_den_polarity_set(const stmdev_ctx_t *ctx, ism330dhcx_den_lh_ois_t val) { ism330dhcx_int_ois_t int_ois; @@ -3562,7 +3574,7 @@ int32_t ism330dhcx_aux_den_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_den_polarity_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_den_polarity_get(const stmdev_ctx_t *ctx, ism330dhcx_den_lh_ois_t *val) { ism330dhcx_int_ois_t int_ois; @@ -3596,7 +3608,7 @@ int32_t ism330dhcx_aux_den_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_den_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_den_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_lvl2_ois_t val) { ism330dhcx_int_ois_t int_ois; @@ -3636,7 +3648,7 @@ int32_t ism330dhcx_aux_den_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_den_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_den_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_lvl2_ois_t *val) { ism330dhcx_int_ois_t int_ois; @@ -3682,7 +3694,7 @@ int32_t ism330dhcx_aux_den_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_int_ois_t int_ois; @@ -3709,7 +3721,7 @@ int32_t ism330dhcx_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_int_ois_t int_ois; @@ -3734,7 +3746,7 @@ int32_t ism330dhcx_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_ois_en_spi2_t val) { ism330dhcx_ctrl1_ois_t ctrl1_ois; @@ -3767,7 +3779,7 @@ int32_t ism330dhcx_aux_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_ois_en_spi2_t *val) { ism330dhcx_ctrl1_ois_t ctrl1_ois; @@ -3805,7 +3817,7 @@ int32_t ism330dhcx_aux_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_gy_full_scale_set(const stmdev_ctx_t *ctx, ism330dhcx_fs_g_ois_t val) { ism330dhcx_ctrl1_ois_t ctrl1_ois; @@ -3832,7 +3844,7 @@ int32_t ism330dhcx_aux_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_gy_full_scale_get(const stmdev_ctx_t *ctx, ism330dhcx_fs_g_ois_t *val) { ism330dhcx_ctrl1_ois_t ctrl1_ois; @@ -3878,7 +3890,7 @@ int32_t ism330dhcx_aux_gy_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_spi_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_spi_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_sim_ois_t val) { ism330dhcx_ctrl1_ois_t ctrl1_ois; @@ -3904,7 +3916,7 @@ int32_t ism330dhcx_aux_spi_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_spi_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_spi_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_sim_ois_t *val) { ism330dhcx_ctrl1_ois_t ctrl1_ois; @@ -3938,7 +3950,7 @@ int32_t ism330dhcx_aux_spi_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, ism330dhcx_ftype_ois_t val) { ism330dhcx_ctrl2_ois_t ctrl2_ois; @@ -3964,7 +3976,7 @@ int32_t ism330dhcx_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, ism330dhcx_ftype_ois_t *val) { ism330dhcx_ctrl2_ois_t ctrl2_ois; @@ -4006,7 +4018,7 @@ int32_t ism330dhcx_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_gy_hp_bandwidth_set(const stmdev_ctx_t *ctx, ism330dhcx_hpm_ois_t val) { ism330dhcx_ctrl2_ois_t ctrl2_ois; @@ -4033,7 +4045,7 @@ int32_t ism330dhcx_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_gy_hp_bandwidth_get(const stmdev_ctx_t *ctx, ism330dhcx_hpm_ois_t *val) { ism330dhcx_ctrl2_ois_t ctrl2_ois; @@ -4081,7 +4093,7 @@ int32_t ism330dhcx_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_gy_clamp_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_gy_clamp_set(const stmdev_ctx_t *ctx, ism330dhcx_st_ois_clampdis_t val) { ism330dhcx_ctrl3_ois_t ctrl3_ois; @@ -4109,7 +4121,7 @@ int32_t ism330dhcx_aux_gy_clamp_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_gy_clamp_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_gy_clamp_get(const stmdev_ctx_t *ctx, ism330dhcx_st_ois_clampdis_t *val) { ism330dhcx_ctrl3_ois_t ctrl3_ois; @@ -4143,7 +4155,7 @@ int32_t ism330dhcx_aux_gy_clamp_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_gy_self_test_set(const stmdev_ctx_t *ctx, ism330dhcx_st_ois_t val) { ism330dhcx_ctrl3_ois_t ctrl3_ois; @@ -4169,7 +4181,7 @@ int32_t ism330dhcx_aux_gy_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_gy_self_test_get(const stmdev_ctx_t *ctx, ism330dhcx_st_ois_t *val) { ism330dhcx_ctrl3_ois_t ctrl3_ois; @@ -4207,7 +4219,7 @@ int32_t ism330dhcx_aux_gy_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_xl_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_xl_bandwidth_set(const stmdev_ctx_t *ctx, ism330dhcx_filter_xl_conf_ois_t val) { ism330dhcx_ctrl3_ois_t ctrl3_ois; @@ -4233,7 +4245,7 @@ int32_t ism330dhcx_aux_xl_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_xl_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_xl_bandwidth_get(const stmdev_ctx_t *ctx, ism330dhcx_filter_xl_conf_ois_t *val) { ism330dhcx_ctrl3_ois_t ctrl3_ois; @@ -4291,7 +4303,7 @@ int32_t ism330dhcx_aux_xl_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_xl_full_scale_set(const stmdev_ctx_t *ctx, ism330dhcx_fs_xl_ois_t val) { ism330dhcx_ctrl3_ois_t ctrl3_ois; @@ -4317,7 +4329,7 @@ int32_t ism330dhcx_aux_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_aux_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_xl_full_scale_get(const stmdev_ctx_t *ctx, ism330dhcx_fs_xl_ois_t *val) { ism330dhcx_ctrl3_ois_t ctrl3_ois; @@ -4372,7 +4384,7 @@ int32_t ism330dhcx_aux_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_sdo_pu_en_t val) { ism330dhcx_pin_ctrl_t pin_ctrl; @@ -4398,7 +4410,7 @@ int32_t ism330dhcx_sdo_sa0_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_sdo_pu_en_t *val) { ism330dhcx_pin_ctrl_t pin_ctrl; @@ -4432,7 +4444,7 @@ int32_t ism330dhcx_sdo_sa0_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_spi_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_spi_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_sim_t val) { ism330dhcx_ctrl3_c_t ctrl3_c; @@ -4458,7 +4470,7 @@ int32_t ism330dhcx_spi_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_spi_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_spi_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_sim_t *val) { ism330dhcx_ctrl3_c_t ctrl3_c; @@ -4492,7 +4504,7 @@ int32_t ism330dhcx_spi_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_i2c_interface_set(const stmdev_ctx_t *ctx, ism330dhcx_i2c_disable_t val) { ism330dhcx_ctrl4_c_t ctrl4_c; @@ -4518,7 +4530,7 @@ int32_t ism330dhcx_i2c_interface_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_i2c_interface_get(const stmdev_ctx_t *ctx, ism330dhcx_i2c_disable_t *val) { ism330dhcx_ctrl4_c_t ctrl4_c; @@ -4566,7 +4578,7 @@ int32_t ism330dhcx_i2c_interface_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pin_int1_route_set(const stmdev_ctx_t *ctx, ism330dhcx_pin_int1_route_t *val) { ism330dhcx_tap_cfg2_t tap_cfg2; @@ -4699,7 +4711,7 @@ int32_t ism330dhcx_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pin_int1_route_get(const stmdev_ctx_t *ctx, ism330dhcx_pin_int1_route_t *val) { int32_t ret; @@ -4758,7 +4770,7 @@ int32_t ism330dhcx_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pin_int2_route_set(const stmdev_ctx_t *ctx, ism330dhcx_pin_int2_route_t *val) { ism330dhcx_tap_cfg2_t tap_cfg2; @@ -4889,7 +4901,7 @@ int32_t ism330dhcx_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pin_int2_route_get(const stmdev_ctx_t *ctx, ism330dhcx_pin_int2_route_t *val) { int32_t ret; @@ -4947,7 +4959,7 @@ int32_t ism330dhcx_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_pin_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pin_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_pp_od_t val) { ism330dhcx_ctrl3_c_t ctrl3_c; @@ -4973,7 +4985,7 @@ int32_t ism330dhcx_pin_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_pin_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pin_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_pp_od_t *val) { ism330dhcx_ctrl3_c_t ctrl3_c; @@ -5007,7 +5019,7 @@ int32_t ism330dhcx_pin_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pin_polarity_set(const stmdev_ctx_t *ctx, ism330dhcx_h_lactive_t val) { ism330dhcx_ctrl3_c_t ctrl3_c; @@ -5033,7 +5045,7 @@ int32_t ism330dhcx_pin_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pin_polarity_get(const stmdev_ctx_t *ctx, ism330dhcx_h_lactive_t *val) { ism330dhcx_ctrl3_c_t ctrl3_c; @@ -5067,7 +5079,7 @@ int32_t ism330dhcx_pin_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_ctrl4_c_t ctrl4_c; int32_t ret; @@ -5092,7 +5104,7 @@ int32_t ism330dhcx_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_ctrl4_c_t ctrl4_c; int32_t ret; @@ -5111,7 +5123,7 @@ int32_t ism330dhcx_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_int_notification_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_int_notification_set(const stmdev_ctx_t *ctx, ism330dhcx_lir_t val) { ism330dhcx_tap_cfg0_t tap_cfg0; @@ -5162,7 +5174,7 @@ int32_t ism330dhcx_int_notification_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_int_notification_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_int_notification_get(const stmdev_ctx_t *ctx, ism330dhcx_lir_t *val) { ism330dhcx_tap_cfg0_t tap_cfg0; @@ -5237,7 +5249,7 @@ int32_t ism330dhcx_int_notification_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_wkup_ths_weight_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_wkup_ths_weight_set(const stmdev_ctx_t *ctx, ism330dhcx_wake_ths_w_t val) { ism330dhcx_wake_up_dur_t wake_up_dur; @@ -5265,7 +5277,7 @@ int32_t ism330dhcx_wkup_ths_weight_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_wkup_ths_weight_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_wkup_ths_weight_get(const stmdev_ctx_t *ctx, ism330dhcx_wake_ths_w_t *val) { ism330dhcx_wake_up_dur_t wake_up_dur; @@ -5300,7 +5312,7 @@ int32_t ism330dhcx_wkup_ths_weight_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_wake_up_ths_t wake_up_ths; int32_t ret; @@ -5326,7 +5338,7 @@ int32_t ism330dhcx_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_wake_up_ths_t wake_up_ths; int32_t ret; @@ -5345,7 +5357,7 @@ int32_t ism330dhcx_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_wake_up_ths_t wake_up_ths; @@ -5371,7 +5383,7 @@ int32_t ism330dhcx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_wake_up_ths_t wake_up_ths; @@ -5391,7 +5403,7 @@ int32_t ism330dhcx_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_wake_up_dur_t wake_up_dur; int32_t ret; @@ -5416,7 +5428,7 @@ int32_t ism330dhcx_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_wake_up_dur_t wake_up_dur; int32_t ret; @@ -5448,7 +5460,7 @@ int32_t ism330dhcx_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_ctrl4_c_t ctrl4_c; int32_t ret; @@ -5473,7 +5485,7 @@ int32_t ism330dhcx_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_ctrl4_c_t ctrl4_c; int32_t ret; @@ -5494,7 +5506,7 @@ int32_t ism330dhcx_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_act_pin_notification_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_act_pin_notification_set(const stmdev_ctx_t *ctx, ism330dhcx_sleep_status_on_int_t val) { ism330dhcx_tap_cfg0_t tap_cfg0; @@ -5522,7 +5534,7 @@ int32_t ism330dhcx_act_pin_notification_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_act_pin_notification_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_act_pin_notification_get(const stmdev_ctx_t *ctx, ism330dhcx_sleep_status_on_int_t *val) { ism330dhcx_tap_cfg0_t tap_cfg0; @@ -5556,7 +5568,7 @@ int32_t ism330dhcx_act_pin_notification_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_act_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_act_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_inact_en_t val) { ism330dhcx_tap_cfg2_t tap_cfg2; @@ -5582,7 +5594,7 @@ int32_t ism330dhcx_act_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_act_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_act_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_inact_en_t *val) { ism330dhcx_tap_cfg2_t tap_cfg2; @@ -5624,7 +5636,7 @@ int32_t ism330dhcx_act_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_wake_up_dur_t wake_up_dur; int32_t ret; @@ -5649,7 +5661,7 @@ int32_t ism330dhcx_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_wake_up_dur_t wake_up_dur; int32_t ret; @@ -5681,7 +5693,7 @@ int32_t ism330dhcx_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_tap_cfg0_t tap_cfg0; @@ -5707,7 +5719,7 @@ int32_t ism330dhcx_tap_detection_on_z_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_tap_cfg0_t tap_cfg0; @@ -5727,7 +5739,7 @@ int32_t ism330dhcx_tap_detection_on_z_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_tap_cfg0_t tap_cfg0; @@ -5753,7 +5765,7 @@ int32_t ism330dhcx_tap_detection_on_y_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_tap_cfg0_t tap_cfg0; @@ -5773,7 +5785,7 @@ int32_t ism330dhcx_tap_detection_on_y_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_tap_cfg0_t tap_cfg0; @@ -5799,7 +5811,7 @@ int32_t ism330dhcx_tap_detection_on_x_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_tap_cfg0_t tap_cfg0; @@ -5819,7 +5831,7 @@ int32_t ism330dhcx_tap_detection_on_x_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_tap_cfg1_t tap_cfg1; int32_t ret; @@ -5844,7 +5856,7 @@ int32_t ism330dhcx_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_threshold_x_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_tap_cfg1_t tap_cfg1; @@ -5864,7 +5876,7 @@ int32_t ism330dhcx_tap_threshold_x_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_axis_priority_set(const stmdev_ctx_t *ctx, ism330dhcx_tap_priority_t val) { ism330dhcx_tap_cfg1_t tap_cfg1; @@ -5890,7 +5902,7 @@ int32_t ism330dhcx_tap_axis_priority_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_axis_priority_get(const stmdev_ctx_t *ctx, ism330dhcx_tap_priority_t *val) { ism330dhcx_tap_cfg1_t tap_cfg1; @@ -5940,7 +5952,7 @@ int32_t ism330dhcx_tap_axis_priority_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_tap_cfg2_t tap_cfg2; int32_t ret; @@ -5965,7 +5977,7 @@ int32_t ism330dhcx_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_threshold_y_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_tap_cfg2_t tap_cfg2; @@ -5985,7 +5997,7 @@ int32_t ism330dhcx_tap_threshold_y_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -6010,7 +6022,7 @@ int32_t ism330dhcx_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_threshold_z_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_tap_ths_6d_t tap_ths_6d; @@ -6034,7 +6046,7 @@ int32_t ism330dhcx_tap_threshold_z_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_int_dur2_t int_dur2; int32_t ret; @@ -6063,7 +6075,7 @@ int32_t ism330dhcx_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_int_dur2_t int_dur2; int32_t ret; @@ -6086,7 +6098,7 @@ int32_t ism330dhcx_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_int_dur2_t int_dur2; int32_t ret; @@ -6115,7 +6127,7 @@ int32_t ism330dhcx_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_int_dur2_t int_dur2; int32_t ret; @@ -6140,7 +6152,7 @@ int32_t ism330dhcx_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_int_dur2_t int_dur2; int32_t ret; @@ -6169,7 +6181,7 @@ int32_t ism330dhcx_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_int_dur2_t int_dur2; int32_t ret; @@ -6188,7 +6200,7 @@ int32_t ism330dhcx_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_single_double_tap_t val) { ism330dhcx_wake_up_ths_t wake_up_ths; @@ -6214,7 +6226,7 @@ int32_t ism330dhcx_tap_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tap_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_single_double_tap_t *val) { ism330dhcx_wake_up_ths_t wake_up_ths; @@ -6261,7 +6273,7 @@ int32_t ism330dhcx_tap_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_6d_threshold_set(const stmdev_ctx_t *ctx, ism330dhcx_sixd_ths_t val) { ism330dhcx_tap_ths_6d_t tap_ths_6d; @@ -6287,7 +6299,7 @@ int32_t ism330dhcx_6d_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_6d_threshold_get(const stmdev_ctx_t *ctx, ism330dhcx_sixd_ths_t *val) { ism330dhcx_tap_ths_6d_t tap_ths_6d; @@ -6329,7 +6341,7 @@ int32_t ism330dhcx_6d_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -6354,7 +6366,7 @@ int32_t ism330dhcx_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -6386,7 +6398,7 @@ int32_t ism330dhcx_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_ff_threshold_set(const stmdev_ctx_t *ctx, ism330dhcx_ff_ths_t val) { ism330dhcx_free_fall_t free_fall; @@ -6412,7 +6424,7 @@ int32_t ism330dhcx_ff_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_ff_threshold_get(const stmdev_ctx_t *ctx, ism330dhcx_ff_ths_t *val) { ism330dhcx_free_fall_t free_fall; @@ -6470,7 +6482,7 @@ int32_t ism330dhcx_ff_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_wake_up_dur_t wake_up_dur; ism330dhcx_free_fall_t free_fall; @@ -6509,7 +6521,7 @@ int32_t ism330dhcx_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_wake_up_dur_t wake_up_dur; ism330dhcx_free_fall_t free_fall; @@ -6549,7 +6561,7 @@ int32_t ism330dhcx_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t ism330dhcx_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val) { ism330dhcx_fifo_ctrl1_t fifo_ctrl1; ism330dhcx_fifo_ctrl2_t fifo_ctrl2; @@ -6582,7 +6594,7 @@ int32_t ism330dhcx_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_watermark_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) { ism330dhcx_fifo_ctrl1_t fifo_ctrl1; @@ -6611,7 +6623,7 @@ int32_t ism330dhcx_fifo_watermark_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_compression_algo_init_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_compression_algo_init_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_emb_func_init_b_t emb_func_init_b; @@ -6648,7 +6660,7 @@ int32_t ism330dhcx_compression_algo_init_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_compression_algo_init_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_compression_algo_init_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_emb_func_init_b_t emb_func_init_b; @@ -6678,7 +6690,7 @@ int32_t ism330dhcx_compression_algo_init_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_compression_algo_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_compression_algo_set(const stmdev_ctx_t *ctx, ism330dhcx_uncoptr_rate_t val) { ism330dhcx_fifo_ctrl2_t fifo_ctrl2; @@ -6733,7 +6745,7 @@ int32_t ism330dhcx_compression_algo_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_compression_algo_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_compression_algo_get(const stmdev_ctx_t *ctx, ism330dhcx_uncoptr_rate_t *val) { ism330dhcx_fifo_ctrl2_t fifo_ctrl2; @@ -6780,7 +6792,7 @@ int32_t ism330dhcx_compression_algo_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_fifo_ctrl2_t fifo_ctrl2; @@ -6806,7 +6818,7 @@ int32_t ism330dhcx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_fifo_ctrl2_t fifo_ctrl2; @@ -6826,7 +6838,7 @@ int32_t ism330dhcx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_compression_algo_real_time_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_compression_algo_real_time_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_fifo_ctrl2_t fifo_ctrl2; @@ -6852,7 +6864,7 @@ int32_t ism330dhcx_compression_algo_real_time_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_compression_algo_real_time_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_compression_algo_real_time_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_fifo_ctrl2_t fifo_ctrl2; @@ -6873,7 +6885,7 @@ int32_t ism330dhcx_compression_algo_real_time_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_fifo_ctrl2_t fifo_ctrl2; @@ -6900,7 +6912,7 @@ int32_t ism330dhcx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_fifo_ctrl2_t fifo_ctrl2; @@ -6921,7 +6933,7 @@ int32_t ism330dhcx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_xl_batch_set(const stmdev_ctx_t *ctx, ism330dhcx_bdr_xl_t val) { ism330dhcx_fifo_ctrl3_t fifo_ctrl3; @@ -6948,7 +6960,7 @@ int32_t ism330dhcx_fifo_xl_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_xl_batch_get(const stmdev_ctx_t *ctx, ism330dhcx_bdr_xl_t *val) { ism330dhcx_fifo_ctrl3_t fifo_ctrl3; @@ -7023,7 +7035,7 @@ int32_t ism330dhcx_fifo_xl_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_gy_batch_set(const stmdev_ctx_t *ctx, ism330dhcx_bdr_gy_t val) { ism330dhcx_fifo_ctrl3_t fifo_ctrl3; @@ -7050,7 +7062,7 @@ int32_t ism330dhcx_fifo_gy_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_gy_batch_get(const stmdev_ctx_t *ctx, ism330dhcx_bdr_gy_t *val) { ism330dhcx_fifo_ctrl3_t fifo_ctrl3; @@ -7124,7 +7136,7 @@ int32_t ism330dhcx_fifo_gy_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_fifo_mode_t val) { ism330dhcx_fifo_ctrl4_t fifo_ctrl4; @@ -7150,7 +7162,7 @@ int32_t ism330dhcx_fifo_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_fifo_mode_t *val) { ism330dhcx_fifo_ctrl4_t fifo_ctrl4; @@ -7201,7 +7213,7 @@ int32_t ism330dhcx_fifo_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_temp_batch_set(const stmdev_ctx_t *ctx, ism330dhcx_odr_t_batch_t val) { ism330dhcx_fifo_ctrl4_t fifo_ctrl4; @@ -7228,7 +7240,7 @@ int32_t ism330dhcx_fifo_temp_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_temp_batch_get(const stmdev_ctx_t *ctx, ism330dhcx_odr_t_batch_t *val) { ism330dhcx_fifo_ctrl4_t fifo_ctrl4; @@ -7272,7 +7284,7 @@ int32_t ism330dhcx_fifo_temp_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, ism330dhcx_odr_ts_batch_t val) { ism330dhcx_fifo_ctrl4_t fifo_ctrl4; @@ -7301,7 +7313,7 @@ int32_t ism330dhcx_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, ism330dhcx_odr_ts_batch_t *val) { ism330dhcx_fifo_ctrl4_t fifo_ctrl4; @@ -7345,7 +7357,7 @@ int32_t ism330dhcx_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, ism330dhcx_trig_counter_bdr_t val) { ism330dhcx_counter_bdr_reg1_t counter_bdr_reg1; @@ -7373,7 +7385,7 @@ int32_t ism330dhcx_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, ism330dhcx_trig_counter_bdr_t *val) { ism330dhcx_counter_bdr_reg1_t counter_bdr_reg1; @@ -7408,7 +7420,7 @@ int32_t ism330dhcx_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_rst_batch_counter_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_counter_bdr_reg1_t counter_bdr_reg1; @@ -7435,7 +7447,7 @@ int32_t ism330dhcx_rst_batch_counter_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_rst_batch_counter_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_counter_bdr_reg1_t counter_bdr_reg1; @@ -7456,7 +7468,7 @@ int32_t ism330dhcx_rst_batch_counter_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_batch_counter_threshold_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { ism330dhcx_counter_bdr_reg2_t counter_bdr_reg1; @@ -7492,7 +7504,7 @@ int32_t ism330dhcx_batch_counter_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { ism330dhcx_counter_bdr_reg1_t counter_bdr_reg1; @@ -7521,7 +7533,7 @@ int32_t ism330dhcx_batch_counter_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_data_level_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) { ism330dhcx_fifo_status1_t fifo_status1; @@ -7549,7 +7561,7 @@ int32_t ism330dhcx_fifo_data_level_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_status_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_status_get(const stmdev_ctx_t *ctx, ism330dhcx_fifo_status2_t *val) { int32_t ret; @@ -7567,7 +7579,7 @@ int32_t ism330dhcx_fifo_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_fifo_status2_t fifo_status2; int32_t ret; @@ -7587,7 +7599,7 @@ int32_t ism330dhcx_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_fifo_status2_t fifo_status2; int32_t ret; @@ -7606,7 +7618,7 @@ int32_t ism330dhcx_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_fifo_status2_t fifo_status2; int32_t ret; @@ -7625,7 +7637,7 @@ int32_t ism330dhcx_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_sensor_tag_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, ism330dhcx_fifo_tag_t *val) { ism330dhcx_fifo_data_out_tag_t fifo_data_out_tag; @@ -7740,7 +7752,7 @@ int32_t ism330dhcx_fifo_sensor_tag_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_emb_func_fifo_cfg_t emb_func_fifo_cfg; int32_t ret; @@ -7776,7 +7788,7 @@ int32_t ism330dhcx_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fifo_pedo_batch_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_emb_func_fifo_cfg_t emb_func_fifo_cfg; @@ -7806,7 +7818,7 @@ int32_t ism330dhcx_fifo_pedo_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_batch_slave_0_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_slv0_config_t slv0_config; @@ -7843,7 +7855,7 @@ int32_t ism330dhcx_sh_batch_slave_0_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_batch_slave_0_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_slv0_config_t slv0_config; @@ -7874,7 +7886,7 @@ int32_t ism330dhcx_sh_batch_slave_0_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_batch_slave_1_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_slv1_config_t slv1_config; @@ -7911,7 +7923,7 @@ int32_t ism330dhcx_sh_batch_slave_1_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_batch_slave_1_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_slv1_config_t slv1_config; @@ -7942,7 +7954,7 @@ int32_t ism330dhcx_sh_batch_slave_1_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_batch_slave_2_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_slv2_config_t slv2_config; @@ -7979,7 +7991,7 @@ int32_t ism330dhcx_sh_batch_slave_2_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_batch_slave_2_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_slv2_config_t slv2_config; @@ -8010,7 +8022,7 @@ int32_t ism330dhcx_sh_batch_slave_2_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_batch_slave_3_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_slv3_config_t slv3_config; @@ -8047,7 +8059,7 @@ int32_t ism330dhcx_sh_batch_slave_3_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_batch_slave_3_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_slv3_config_t slv3_config; @@ -8090,7 +8102,7 @@ int32_t ism330dhcx_sh_batch_slave_3_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_den_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_den_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_den_mode_t val) { ism330dhcx_ctrl6_c_t ctrl6_c; @@ -8116,7 +8128,7 @@ int32_t ism330dhcx_den_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_den_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_den_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_den_mode_t *val) { ism330dhcx_ctrl6_c_t ctrl6_c; @@ -8162,7 +8174,7 @@ int32_t ism330dhcx_den_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_den_polarity_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_den_polarity_set(const stmdev_ctx_t *ctx, ism330dhcx_den_lh_t val) { ism330dhcx_ctrl9_xl_t ctrl9_xl; @@ -8188,7 +8200,7 @@ int32_t ism330dhcx_den_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_den_polarity_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_den_polarity_get(const stmdev_ctx_t *ctx, ism330dhcx_den_lh_t *val) { ism330dhcx_ctrl9_xl_t ctrl9_xl; @@ -8222,7 +8234,7 @@ int32_t ism330dhcx_den_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_den_enable_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_den_enable_set(const stmdev_ctx_t *ctx, ism330dhcx_den_xl_g_t val) { ism330dhcx_ctrl9_xl_t ctrl9_xl; @@ -8248,7 +8260,7 @@ int32_t ism330dhcx_den_enable_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_den_enable_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_den_enable_get(const stmdev_ctx_t *ctx, ism330dhcx_den_xl_g_t *val) { ism330dhcx_ctrl9_xl_t ctrl9_xl; @@ -8286,7 +8298,7 @@ int32_t ism330dhcx_den_enable_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -8311,7 +8323,7 @@ int32_t ism330dhcx_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_den_mark_axis_x_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_ctrl9_xl_t ctrl9_xl; @@ -8331,7 +8343,7 @@ int32_t ism330dhcx_den_mark_axis_x_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -8356,7 +8368,7 @@ int32_t ism330dhcx_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_den_mark_axis_y_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_ctrl9_xl_t ctrl9_xl; @@ -8376,7 +8388,7 @@ int32_t ism330dhcx_den_mark_axis_y_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -8401,7 +8413,7 @@ int32_t ism330dhcx_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_den_mark_axis_z_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_ctrl9_xl_t ctrl9_xl; @@ -8433,7 +8445,7 @@ int32_t ism330dhcx_den_mark_axis_z_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -8468,7 +8480,7 @@ int32_t ism330dhcx_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -8497,7 +8509,7 @@ int32_t ism330dhcx_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_pedo_step_detect_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pedo_step_detect_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_emb_func_status_t emb_func_status; @@ -8527,7 +8539,7 @@ int32_t ism330dhcx_pedo_step_detect_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_pedo_debounce_steps_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -8545,7 +8557,7 @@ int32_t ism330dhcx_pedo_debounce_steps_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_pedo_debounce_steps_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -8563,7 +8575,7 @@ int32_t ism330dhcx_pedo_debounce_steps_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_pedo_steps_period_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pedo_steps_period_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; @@ -8590,7 +8602,7 @@ int32_t ism330dhcx_pedo_steps_period_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_pedo_steps_period_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pedo_steps_period_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -8618,7 +8630,7 @@ int32_t ism330dhcx_pedo_steps_period_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_pedo_int_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pedo_int_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_carry_count_en_t val) { ism330dhcx_pedo_cmd_reg_t pedo_cmd_reg; @@ -8645,7 +8657,7 @@ int32_t ism330dhcx_pedo_int_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_pedo_int_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pedo_int_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_carry_count_en_t *val) { ism330dhcx_pedo_cmd_reg_t pedo_cmd_reg; @@ -8692,7 +8704,7 @@ int32_t ism330dhcx_pedo_int_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -8727,7 +8739,7 @@ int32_t ism330dhcx_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -8756,7 +8768,7 @@ int32_t ism330dhcx_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_motion_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_motion_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_emb_func_status_t emb_func_status; @@ -8799,7 +8811,7 @@ int32_t ism330dhcx_motion_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -8834,7 +8846,7 @@ int32_t ism330dhcx_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -8863,7 +8875,7 @@ int32_t ism330dhcx_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_emb_func_status_t emb_func_status; @@ -8906,7 +8918,7 @@ int32_t ism330dhcx_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_mag_sensitivity_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; @@ -8933,7 +8945,7 @@ int32_t ism330dhcx_mag_sensitivity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_mag_sensitivity_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -8960,7 +8972,7 @@ int32_t ism330dhcx_mag_sensitivity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val) +int32_t ism330dhcx_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -9021,7 +9033,7 @@ int32_t ism330dhcx_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t ism330dhcx_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -9088,7 +9100,7 @@ int32_t ism330dhcx_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_mag_soft_iron_set(stmdev_ctx_t *ctx, uint16_t *val) +int32_t ism330dhcx_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[12]; int32_t ret; @@ -9202,7 +9214,7 @@ int32_t ism330dhcx_mag_soft_iron_set(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t ism330dhcx_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[12]; int32_t ret; @@ -9313,7 +9325,7 @@ int32_t ism330dhcx_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_mag_z_orient_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mag_z_orient_set(const stmdev_ctx_t *ctx, ism330dhcx_mag_z_axis_t val) { ism330dhcx_mag_cfg_a_t mag_cfg_a; @@ -9340,7 +9352,7 @@ int32_t ism330dhcx_mag_z_orient_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_mag_z_orient_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mag_z_orient_get(const stmdev_ctx_t *ctx, ism330dhcx_mag_z_axis_t *val) { ism330dhcx_mag_cfg_a_t mag_cfg_a; @@ -9392,7 +9404,7 @@ int32_t ism330dhcx_mag_z_orient_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_mag_y_orient_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mag_y_orient_set(const stmdev_ctx_t *ctx, ism330dhcx_mag_y_axis_t val) { ism330dhcx_mag_cfg_a_t mag_cfg_a; @@ -9419,7 +9431,7 @@ int32_t ism330dhcx_mag_y_orient_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_mag_y_orient_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mag_y_orient_get(const stmdev_ctx_t *ctx, ism330dhcx_mag_y_axis_t *val) { ism330dhcx_mag_cfg_a_t mag_cfg_a; @@ -9470,7 +9482,7 @@ int32_t ism330dhcx_mag_y_orient_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_mag_x_orient_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mag_x_orient_set(const stmdev_ctx_t *ctx, ism330dhcx_mag_x_axis_t val) { ism330dhcx_mag_cfg_b_t mag_cfg_b; @@ -9497,7 +9509,7 @@ int32_t ism330dhcx_mag_x_orient_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_mag_x_orient_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mag_x_orient_get(const stmdev_ctx_t *ctx, ism330dhcx_mag_x_axis_t *val) { ism330dhcx_mag_cfg_b_t mag_cfg_b; @@ -9561,7 +9573,7 @@ int32_t ism330dhcx_mag_x_orient_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_emb_func_status_t emb_func_status; @@ -9591,7 +9603,7 @@ int32_t ism330dhcx_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; ism330dhcx_emb_func_en_b_t emb_func_en_b; @@ -9626,7 +9638,7 @@ int32_t ism330dhcx_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; ism330dhcx_emb_func_en_b_t emb_func_en_b; @@ -9661,7 +9673,7 @@ int32_t ism330dhcx_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fsm_enable_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fsm_enable_set(const stmdev_ctx_t *ctx, ism330dhcx_emb_fsm_enable_t *val) { ism330dhcx_emb_func_en_b_t emb_func_en_b; @@ -9736,7 +9748,7 @@ int32_t ism330dhcx_fsm_enable_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fsm_enable_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fsm_enable_get(const stmdev_ctx_t *ctx, ism330dhcx_emb_fsm_enable_t *val) { int32_t ret; @@ -9771,7 +9783,7 @@ int32_t ism330dhcx_fsm_enable_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t ism330dhcx_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -9802,7 +9814,7 @@ int32_t ism330dhcx_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t ism330dhcx_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -9833,7 +9845,7 @@ int32_t ism330dhcx_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_long_clr_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_long_clr_set(const stmdev_ctx_t *ctx, ism330dhcx_fsm_lc_clr_t val) { ism330dhcx_fsm_long_counter_clear_t fsm_long_counter_clear; @@ -9869,7 +9881,7 @@ int32_t ism330dhcx_long_clr_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_long_clr_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_long_clr_get(const stmdev_ctx_t *ctx, ism330dhcx_fsm_lc_clr_t *val) { ism330dhcx_fsm_long_counter_clear_t fsm_long_counter_clear; @@ -9917,7 +9929,7 @@ int32_t ism330dhcx_long_clr_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fsm_out_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fsm_out_get(const stmdev_ctx_t *ctx, ism330dhcx_fsm_out_t *val) { int32_t ret; @@ -9945,7 +9957,7 @@ int32_t ism330dhcx_fsm_out_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fsm_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fsm_data_rate_set(const stmdev_ctx_t *ctx, ism330dhcx_fsm_odr_t val) { ism330dhcx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; @@ -9983,7 +9995,7 @@ int32_t ism330dhcx_fsm_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fsm_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fsm_data_rate_get(const stmdev_ctx_t *ctx, ism330dhcx_fsm_odr_t *val) { ism330dhcx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; @@ -10035,7 +10047,7 @@ int32_t ism330dhcx_fsm_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_emb_func_init_b_t emb_func_init_b; int32_t ret; @@ -10070,7 +10082,7 @@ int32_t ism330dhcx_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_emb_func_init_b_t emb_func_init_b; int32_t ret; @@ -10102,7 +10114,7 @@ int32_t ism330dhcx_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_long_cnt_int_value_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; @@ -10135,7 +10147,7 @@ int32_t ism330dhcx_long_cnt_int_value_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_long_cnt_int_value_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -10165,7 +10177,7 @@ int32_t ism330dhcx_long_cnt_int_value_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fsm_number_of_programs_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -10189,7 +10201,7 @@ int32_t ism330dhcx_fsm_number_of_programs_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fsm_number_of_programs_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -10207,7 +10219,7 @@ int32_t ism330dhcx_fsm_number_of_programs_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fsm_start_address_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; @@ -10238,7 +10250,7 @@ int32_t ism330dhcx_fsm_start_address_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_fsm_start_address_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -10282,7 +10294,7 @@ int32_t ism330dhcx_fsm_start_address_get(stmdev_ctx_t *ctx, * in EMB_FUNC_INIT_B * */ -int32_t ism330dhcx_mlc_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_mlc_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_emb_func_en_b_t reg; int32_t ret; @@ -10330,7 +10342,7 @@ int32_t ism330dhcx_mlc_set(stmdev_ctx_t *ctx, uint8_t val) * reg EMB_FUNC_EN_B * */ -int32_t ism330dhcx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_emb_func_en_b_t reg; int32_t ret; @@ -10358,7 +10370,7 @@ int32_t ism330dhcx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val) * @param val register MLC_STATUS_MAINPAGE * */ -int32_t ism330dhcx_mlc_status_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mlc_status_get(const stmdev_ctx_t *ctx, ism330dhcx_mlc_status_mainpage_t *val) { return ism330dhcx_read_reg(ctx, ISM330DHCX_MLC_STATUS_MAINPAGE, @@ -10373,7 +10385,7 @@ int32_t ism330dhcx_mlc_status_get(stmdev_ctx_t *ctx, * reg EMB_FUNC_ODR_CFG_C * */ -int32_t ism330dhcx_mlc_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mlc_data_rate_set(const stmdev_ctx_t *ctx, ism330dhcx_mlc_odr_t val) { ism330dhcx_emb_func_odr_cfg_c_t reg; @@ -10409,7 +10421,7 @@ int32_t ism330dhcx_mlc_data_rate_set(stmdev_ctx_t *ctx, * reg EMB_FUNC_ODR_CFG_C * */ -int32_t ism330dhcx_mlc_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mlc_data_rate_get(const stmdev_ctx_t *ctx, ism330dhcx_mlc_odr_t *val) { ism330dhcx_emb_func_odr_cfg_c_t reg; @@ -10474,7 +10486,7 @@ int32_t ism330dhcx_mlc_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_read_data_raw_get(const stmdev_ctx_t *ctx, ism330dhcx_emb_sh_read_t *val, uint8_t len) { @@ -10503,7 +10515,7 @@ int32_t ism330dhcx_sh_read_data_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_slave_connected_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_slave_connected_set(const stmdev_ctx_t *ctx, ism330dhcx_aux_sens_on_t val) { ism330dhcx_master_config_t master_config; @@ -10539,7 +10551,7 @@ int32_t ism330dhcx_sh_slave_connected_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_slave_connected_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_slave_connected_get(const stmdev_ctx_t *ctx, ism330dhcx_aux_sens_on_t *val) { ism330dhcx_master_config_t master_config; @@ -10591,7 +10603,7 @@ int32_t ism330dhcx_sh_slave_connected_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_master_config_t master_config; int32_t ret; @@ -10626,7 +10638,7 @@ int32_t ism330dhcx_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_master_config_t master_config; int32_t ret; @@ -10655,7 +10667,7 @@ int32_t ism330dhcx_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_pin_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_shub_pu_en_t val) { ism330dhcx_master_config_t master_config; @@ -10691,7 +10703,7 @@ int32_t ism330dhcx_sh_pin_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_pin_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_shub_pu_en_t *val) { ism330dhcx_master_config_t master_config; @@ -10735,7 +10747,7 @@ int32_t ism330dhcx_sh_pin_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dhcx_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dhcx_master_config_t master_config; int32_t ret; @@ -10770,7 +10782,7 @@ int32_t ism330dhcx_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_pass_through_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_master_config_t master_config; @@ -10800,7 +10812,7 @@ int32_t ism330dhcx_sh_pass_through_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_syncro_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_start_config_t val) { ism330dhcx_master_config_t master_config; @@ -10836,7 +10848,7 @@ int32_t ism330dhcx_sh_syncro_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_syncro_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_start_config_t *val) { ism330dhcx_master_config_t master_config; @@ -10881,7 +10893,7 @@ int32_t ism330dhcx_sh_syncro_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_write_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_write_once_t val) { ism330dhcx_master_config_t master_config; @@ -10918,7 +10930,7 @@ int32_t ism330dhcx_sh_write_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_write_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_write_once_t *val) { ism330dhcx_master_config_t master_config; @@ -10961,7 +10973,7 @@ int32_t ism330dhcx_sh_write_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_reset_set(stmdev_ctx_t *ctx) +int32_t ism330dhcx_sh_reset_set(const stmdev_ctx_t *ctx) { ism330dhcx_master_config_t master_config; int32_t ret; @@ -11003,7 +11015,7 @@ int32_t ism330dhcx_sh_reset_set(stmdev_ctx_t *ctx) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dhcx_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dhcx_master_config_t master_config; int32_t ret; @@ -11032,7 +11044,7 @@ int32_t ism330dhcx_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_data_rate_set(const stmdev_ctx_t *ctx, ism330dhcx_shub_odr_t val) { ism330dhcx_slv0_config_t slv0_config; @@ -11068,7 +11080,7 @@ int32_t ism330dhcx_sh_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_data_rate_get(const stmdev_ctx_t *ctx, ism330dhcx_shub_odr_t *val) { ism330dhcx_slv0_config_t slv0_config; @@ -11123,7 +11135,7 @@ int32_t ism330dhcx_sh_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_cfg_write(const stmdev_ctx_t *ctx, ism330dhcx_sh_cfg_write_t *val) { ism330dhcx_slv0_add_t slv0_add; @@ -11169,7 +11181,7 @@ int32_t ism330dhcx_sh_cfg_write(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_slv0_cfg_read(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, ism330dhcx_sh_cfg_read_t *val) { ism330dhcx_slv0_config_t slv0_config; @@ -11223,7 +11235,7 @@ int32_t ism330dhcx_sh_slv0_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_slv1_cfg_read(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, ism330dhcx_sh_cfg_read_t *val) { ism330dhcx_slv1_config_t slv1_config; @@ -11277,7 +11289,7 @@ int32_t ism330dhcx_sh_slv1_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_slv2_cfg_read(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, ism330dhcx_sh_cfg_read_t *val) { ism330dhcx_slv2_config_t slv2_config; @@ -11331,7 +11343,7 @@ int32_t ism330dhcx_sh_slv2_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_slv3_cfg_read(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, ism330dhcx_sh_cfg_read_t *val) { ism330dhcx_slv3_config_t slv3_config; @@ -11382,7 +11394,7 @@ int32_t ism330dhcx_sh_slv3_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dhcx_sh_status_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_status_get(const stmdev_ctx_t *ctx, ism330dhcx_status_master_t *val) { int32_t ret; diff --git a/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.h b/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.h index 4007172e..4f7190d8 100644 --- a/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.h +++ b/sensor/stmemsc/ism330dhcx_STdC/driver/ism330dhcx_reg.h @@ -185,11 +185,9 @@ typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t not_used_01 : 6; -uint8_t reg_access : - 2; /* shub_reg_access + func_cfg_access */ + uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */ #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN -uint8_t reg_access : - 2; /* shub_reg_access + func_cfg_access */ + uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */ uint8_t not_used_01 : 6; #endif /* DRV_BYTE_ORDER */ } ism330dhcx_func_cfg_access_t; @@ -438,11 +436,9 @@ typedef struct uint8_t ftype : 3; uint8_t usr_off_w : 1; uint8_t xl_hm_mode : 1; -uint8_t den_mode : - 3; /* trig_en + lvl1_en + lvl2_en */ + uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN -uint8_t den_mode : - 3; /* trig_en + lvl1_en + lvl2_en */ + uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ uint8_t xl_hm_mode : 1; uint8_t usr_off_w : 1; uint8_t ftype : 3; @@ -1504,13 +1500,11 @@ typedef struct typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN -uint8_t fsm_lc_clr : - 2; /* fsm_lc_cleared + fsm_lc_clear */ + uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ uint8_t not_used_01 : 6; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN uint8_t not_used_01 : 6; -uint8_t fsm_lc_clr : - 2; /* fsm_lc_cleared + fsm_lc_clear */ + uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ #endif /* DRV_BYTE_ORDER */ } ism330dhcx_fsm_long_counter_clear_t; @@ -2836,10 +2830,10 @@ typedef union * The __weak directive allows the final application to overwrite * them with a custom implementation. */ -int32_t ism330dhcx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t ism330dhcx_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t ism330dhcx_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t ism330dhcx_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -2866,9 +2860,9 @@ typedef enum ISM330DHCX_4g = 2, ISM330DHCX_8g = 3, } ism330dhcx_fs_xl_t; -int32_t ism330dhcx_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_full_scale_set(const stmdev_ctx_t *ctx, ism330dhcx_fs_xl_t val); -int32_t ism330dhcx_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_full_scale_get(const stmdev_ctx_t *ctx, ism330dhcx_fs_xl_t *val); typedef enum @@ -2886,9 +2880,9 @@ typedef enum ISM330DHCX_XL_ODR_6667Hz = 10, ISM330DHCX_XL_ODR_1Hz6 = 11, /* (low power only) */ } ism330dhcx_odr_xl_t; -int32_t ism330dhcx_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_data_rate_set(const stmdev_ctx_t *ctx, ism330dhcx_odr_xl_t val); -int32_t ism330dhcx_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_data_rate_get(const stmdev_ctx_t *ctx, ism330dhcx_odr_xl_t *val); typedef enum @@ -2900,9 +2894,9 @@ typedef enum ISM330DHCX_2000dps = 12, ISM330DHCX_4000dps = 1, } ism330dhcx_fs_g_t; -int32_t ism330dhcx_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_gy_full_scale_set(const stmdev_ctx_t *ctx, ism330dhcx_fs_g_t val); -int32_t ism330dhcx_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_gy_full_scale_get(const stmdev_ctx_t *ctx, ism330dhcx_fs_g_t *val); typedef enum @@ -2919,14 +2913,14 @@ typedef enum ISM330DHCX_GY_ODR_3332Hz = 9, ISM330DHCX_GY_ODR_6667Hz = 10, } ism330dhcx_odr_g_t; -int32_t ism330dhcx_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_gy_data_rate_set(const stmdev_ctx_t *ctx, ism330dhcx_odr_g_t val); -int32_t ism330dhcx_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_gy_data_rate_get(const stmdev_ctx_t *ctx, ism330dhcx_odr_g_t *val); -int32_t ism330dhcx_block_data_update_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_block_data_update_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2934,9 +2928,9 @@ typedef enum ISM330DHCX_LSb_1mg = 0, ISM330DHCX_LSb_16mg = 1, } ism330dhcx_usr_off_w_t; -int32_t ism330dhcx_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_offset_weight_set(const stmdev_ctx_t *ctx, ism330dhcx_usr_off_w_t val); -int32_t ism330dhcx_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_offset_weight_get(const stmdev_ctx_t *ctx, ism330dhcx_usr_off_w_t *val); typedef enum @@ -2944,9 +2938,9 @@ typedef enum ISM330DHCX_HIGH_PERFORMANCE_MD = 0, ISM330DHCX_LOW_NORMAL_POWER_MD = 1, } ism330dhcx_xl_hm_mode_t; -int32_t ism330dhcx_xl_power_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_power_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_xl_hm_mode_t val); -int32_t ism330dhcx_xl_power_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_power_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_xl_hm_mode_t *val); typedef enum @@ -2954,9 +2948,9 @@ typedef enum ISM330DHCX_GY_HIGH_PERFORMANCE = 0, ISM330DHCX_GY_NORMAL = 1, } ism330dhcx_g_hm_mode_t; -int32_t ism330dhcx_gy_power_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_gy_power_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_g_hm_mode_t val); -int32_t ism330dhcx_gy_power_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_gy_power_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_g_hm_mode_t *val); typedef struct @@ -2970,45 +2964,45 @@ typedef struct ism330dhcx_fsm_status_a_t fsm_status_a; ism330dhcx_fsm_status_b_t fsm_status_b; } ism330dhcx_all_sources_t; -int32_t ism330dhcx_all_sources_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_all_sources_get(const stmdev_ctx_t *ctx, ism330dhcx_all_sources_t *val); -int32_t ism330dhcx_status_reg_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_status_reg_get(const stmdev_ctx_t *ctx, ism330dhcx_status_reg_t *val); -int32_t ism330dhcx_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_xl_usr_offset_x_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ism330dhcx_xl_usr_offset_x_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ism330dhcx_xl_usr_offset_y_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ism330dhcx_xl_usr_offset_y_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ism330dhcx_xl_usr_offset_z_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ism330dhcx_xl_usr_offset_z_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ism330dhcx_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dhcx_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_timestamp_rst(stmdev_ctx_t *ctx); +int32_t ism330dhcx_timestamp_rst(const stmdev_ctx_t *ctx); -int32_t ism330dhcx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dhcx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_timestamp_raw_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); typedef enum @@ -3018,34 +3012,34 @@ typedef enum ISM330DHCX_ROUND_GY = 2, ISM330DHCX_ROUND_GY_XL = 3, } ism330dhcx_rounding_t; -int32_t ism330dhcx_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_rounding_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_rounding_t val); -int32_t ism330dhcx_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_rounding_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_rounding_t *val); -int32_t ism330dhcx_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t ism330dhcx_angular_rate_raw_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t ism330dhcx_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t ism330dhcx_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t ism330dhcx_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ism330dhcx_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t ism330dhcx_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ism330dhcx_device_conf_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_device_conf_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_device_conf_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dhcx_device_conf_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dhcx_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_number_of_steps_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_number_of_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t ism330dhcx_steps_reset(stmdev_ctx_t *ctx); +int32_t ism330dhcx_steps_reset(const stmdev_ctx_t *ctx); typedef enum { @@ -3053,19 +3047,19 @@ typedef enum ISM330DHCX_SENSOR_HUB_BANK = 1, ISM330DHCX_EMBEDDED_FUNC_BANK = 2, } ism330dhcx_reg_access_t; -int32_t ism330dhcx_mem_bank_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mem_bank_set(const stmdev_ctx_t *ctx, ism330dhcx_reg_access_t val); -int32_t ism330dhcx_mem_bank_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mem_bank_get(const stmdev_ctx_t *ctx, ism330dhcx_reg_access_t *val); -int32_t ism330dhcx_ln_pg_write_byte(stmdev_ctx_t *ctx, +int32_t ism330dhcx_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val); -int32_t ism330dhcx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, +int32_t ism330dhcx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); -int32_t ism330dhcx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add, +int32_t ism330dhcx_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, uint8_t *val); -int32_t ism330dhcx_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, +int32_t ism330dhcx_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val); typedef enum @@ -3073,22 +3067,22 @@ typedef enum ISM330DHCX_DRDY_LATCHED = 0, ISM330DHCX_DRDY_PULSED = 1, } ism330dhcx_dataready_pulsed_t; -int32_t ism330dhcx_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_data_ready_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_dataready_pulsed_t val); -int32_t ism330dhcx_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_data_ready_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_dataready_pulsed_t *val); -int32_t ism330dhcx_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t ism330dhcx_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ism330dhcx_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dhcx_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_auto_increment_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dhcx_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dhcx_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3096,9 +3090,9 @@ typedef enum ISM330DHCX_XL_ST_POSITIVE = 1, ISM330DHCX_XL_ST_NEGATIVE = 2, } ism330dhcx_st_xl_t; -int32_t ism330dhcx_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_self_test_set(const stmdev_ctx_t *ctx, ism330dhcx_st_xl_t val); -int32_t ism330dhcx_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_self_test_get(const stmdev_ctx_t *ctx, ism330dhcx_st_xl_t *val); typedef enum @@ -3107,20 +3101,20 @@ typedef enum ISM330DHCX_GY_ST_POSITIVE = 1, ISM330DHCX_GY_ST_NEGATIVE = 3, } ism330dhcx_st_g_t; -int32_t ism330dhcx_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_gy_self_test_set(const stmdev_ctx_t *ctx, ism330dhcx_st_g_t val); -int32_t ism330dhcx_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_gy_self_test_get(const stmdev_ctx_t *ctx, ism330dhcx_st_g_t *val); -int32_t ism330dhcx_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dhcx_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dhcx_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3134,13 +3128,13 @@ typedef enum ISM330DHCX_AGGRESSIVE = 6, ISM330DHCX_XTREME = 7, } ism330dhcx_ftype_t; -int32_t ism330dhcx_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, ism330dhcx_ftype_t val); -int32_t ism330dhcx_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, ism330dhcx_ftype_t *val); -int32_t ism330dhcx_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dhcx_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3168,14 +3162,14 @@ typedef enum ISM330DHCX_LP_ODR_DIV_400 = 0x06, ISM330DHCX_LP_ODR_DIV_800 = 0x07, } ism330dhcx_hp_slope_xl_en_t; -int32_t ism330dhcx_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, ism330dhcx_hp_slope_xl_en_t val); -int32_t ism330dhcx_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, ism330dhcx_hp_slope_xl_en_t *val); -int32_t ism330dhcx_xl_fast_settling_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_xl_fast_settling_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3183,9 +3177,9 @@ typedef enum ISM330DHCX_USE_SLOPE = 0, ISM330DHCX_USE_HPF = 1, } ism330dhcx_slope_fds_t; -int32_t ism330dhcx_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, ism330dhcx_slope_fds_t val); -int32_t ism330dhcx_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, ism330dhcx_slope_fds_t *val); typedef enum @@ -3196,9 +3190,9 @@ typedef enum ISM330DHCX_HP_FILTER_260mHz = 0x82, ISM330DHCX_HP_FILTER_1Hz04 = 0x83, } ism330dhcx_hpm_g_t; -int32_t ism330dhcx_gy_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, ism330dhcx_hpm_g_t val); -int32_t ism330dhcx_gy_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, ism330dhcx_hpm_g_t *val); typedef enum @@ -3206,9 +3200,9 @@ typedef enum ISM330DHCX_AUX_PULL_UP_DISC = 0, ISM330DHCX_AUX_PULL_UP_CONNECT = 1, } ism330dhcx_ois_pu_dis_t; -int32_t ism330dhcx_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_sdo_ocs_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_ois_pu_dis_t val); -int32_t ism330dhcx_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_sdo_ocs_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_ois_pu_dis_t *val); typedef enum @@ -3216,21 +3210,21 @@ typedef enum ISM330DHCX_AUX_ON = 1, ISM330DHCX_AUX_ON_BY_AUX_INTERFACE = 0, } ism330dhcx_ois_on_t; -int32_t ism330dhcx_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_pw_on_ctrl_set(const stmdev_ctx_t *ctx, ism330dhcx_ois_on_t val); -int32_t ism330dhcx_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_pw_on_ctrl_get(const stmdev_ctx_t *ctx, ism330dhcx_ois_on_t *val); -int32_t ism330dhcx_aux_status_reg_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_status_reg_get(const stmdev_ctx_t *ctx, ism330dhcx_status_spiaux_t *val); -int32_t ism330dhcx_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3239,9 +3233,9 @@ typedef enum ISM330DHCX_AUX_XL_POS = 1, ISM330DHCX_AUX_XL_NEG = 2, } ism330dhcx_st_xl_ois_t; -int32_t ism330dhcx_aux_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_xl_self_test_set(const stmdev_ctx_t *ctx, ism330dhcx_st_xl_ois_t val); -int32_t ism330dhcx_aux_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_xl_self_test_get(const stmdev_ctx_t *ctx, ism330dhcx_st_xl_ois_t *val); typedef enum @@ -3249,9 +3243,9 @@ typedef enum ISM330DHCX_AUX_DEN_ACTIVE_LOW = 0, ISM330DHCX_AUX_DEN_ACTIVE_HIGH = 1, } ism330dhcx_den_lh_ois_t; -int32_t ism330dhcx_aux_den_polarity_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_den_polarity_set(const stmdev_ctx_t *ctx, ism330dhcx_den_lh_ois_t val); -int32_t ism330dhcx_aux_den_polarity_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_den_polarity_get(const stmdev_ctx_t *ctx, ism330dhcx_den_lh_ois_t *val); typedef enum @@ -3260,14 +3254,14 @@ typedef enum ISM330DHCX_AUX_DEN_LEVEL_LATCH = 3, ISM330DHCX_AUX_DEN_LEVEL_TRIG = 2, } ism330dhcx_lvl2_ois_t; -int32_t ism330dhcx_aux_den_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_den_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_lvl2_ois_t val); -int32_t ism330dhcx_aux_den_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_den_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_lvl2_ois_t *val); -int32_t ism330dhcx_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3276,9 +3270,9 @@ typedef enum ISM330DHCX_MODE_3_GY = 1, ISM330DHCX_MODE_4_GY_XL = 3, } ism330dhcx_ois_en_spi2_t; -int32_t ism330dhcx_aux_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_ois_en_spi2_t val); -int32_t ism330dhcx_aux_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_ois_en_spi2_t *val); typedef enum @@ -3289,9 +3283,9 @@ typedef enum ISM330DHCX_1000dps_AUX = 0x02, ISM330DHCX_2000dps_AUX = 0x03, } ism330dhcx_fs_g_ois_t; -int32_t ism330dhcx_aux_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_gy_full_scale_set(const stmdev_ctx_t *ctx, ism330dhcx_fs_g_ois_t val); -int32_t ism330dhcx_aux_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_gy_full_scale_get(const stmdev_ctx_t *ctx, ism330dhcx_fs_g_ois_t *val); typedef enum @@ -3299,9 +3293,9 @@ typedef enum ISM330DHCX_AUX_SPI_4_WIRE = 0, ISM330DHCX_AUX_SPI_3_WIRE = 1, } ism330dhcx_sim_ois_t; -int32_t ism330dhcx_aux_spi_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_spi_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_sim_ois_t val); -int32_t ism330dhcx_aux_spi_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_spi_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_sim_ois_t *val); typedef enum @@ -3311,9 +3305,9 @@ typedef enum ISM330DHCX_172Hz70 = 2, ISM330DHCX_937Hz91 = 3, } ism330dhcx_ftype_ois_t; -int32_t ism330dhcx_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, ism330dhcx_ftype_ois_t val); -int32_t ism330dhcx_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, ism330dhcx_ftype_ois_t *val); typedef enum @@ -3324,9 +3318,9 @@ typedef enum ISM330DHCX_AUX_HP_Hz260 = 0x12, ISM330DHCX_AUX_HP_1Hz040 = 0x13, } ism330dhcx_hpm_ois_t; -int32_t ism330dhcx_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_gy_hp_bandwidth_set(const stmdev_ctx_t *ctx, ism330dhcx_hpm_ois_t val); -int32_t ism330dhcx_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_gy_hp_bandwidth_get(const stmdev_ctx_t *ctx, ism330dhcx_hpm_ois_t *val); typedef enum @@ -3334,9 +3328,9 @@ typedef enum ISM330DHCX_ENABLE_CLAMP = 0, ISM330DHCX_DISABLE_CLAMP = 1, } ism330dhcx_st_ois_clampdis_t; -int32_t ism330dhcx_aux_gy_clamp_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_gy_clamp_set(const stmdev_ctx_t *ctx, ism330dhcx_st_ois_clampdis_t val); -int32_t ism330dhcx_aux_gy_clamp_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_gy_clamp_get(const stmdev_ctx_t *ctx, ism330dhcx_st_ois_clampdis_t *val); typedef enum @@ -3345,9 +3339,9 @@ typedef enum ISM330DHCX_AUX_GY_POS = 1, ISM330DHCX_AUX_GY_NEG = 3, } ism330dhcx_st_ois_t; -int32_t ism330dhcx_aux_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_gy_self_test_set(const stmdev_ctx_t *ctx, ism330dhcx_st_ois_t val); -int32_t ism330dhcx_aux_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_gy_self_test_get(const stmdev_ctx_t *ctx, ism330dhcx_st_ois_t *val); typedef enum @@ -3361,9 +3355,9 @@ typedef enum ISM330DHCX_8Hz3 = 6, ISM330DHCX_4Hz11 = 7, } ism330dhcx_filter_xl_conf_ois_t; -int32_t ism330dhcx_aux_xl_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_xl_bandwidth_set(const stmdev_ctx_t *ctx, ism330dhcx_filter_xl_conf_ois_t val); -int32_t ism330dhcx_aux_xl_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_xl_bandwidth_get(const stmdev_ctx_t *ctx, ism330dhcx_filter_xl_conf_ois_t *val); typedef enum @@ -3373,9 +3367,9 @@ typedef enum ISM330DHCX_AUX_4g = 2, ISM330DHCX_AUX_8g = 3, } ism330dhcx_fs_xl_ois_t; -int32_t ism330dhcx_aux_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_xl_full_scale_set(const stmdev_ctx_t *ctx, ism330dhcx_fs_xl_ois_t val); -int32_t ism330dhcx_aux_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_aux_xl_full_scale_get(const stmdev_ctx_t *ctx, ism330dhcx_fs_xl_ois_t *val); typedef enum @@ -3383,9 +3377,9 @@ typedef enum ISM330DHCX_PULL_UP_DISC = 0, ISM330DHCX_PULL_UP_CONNECT = 1, } ism330dhcx_sdo_pu_en_t; -int32_t ism330dhcx_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_sdo_pu_en_t val); -int32_t ism330dhcx_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_sdo_pu_en_t *val); typedef enum @@ -3393,9 +3387,9 @@ typedef enum ISM330DHCX_SPI_4_WIRE = 0, ISM330DHCX_SPI_3_WIRE = 1, } ism330dhcx_sim_t; -int32_t ism330dhcx_spi_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_spi_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_sim_t val); -int32_t ism330dhcx_spi_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_spi_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_sim_t *val); typedef enum @@ -3403,9 +3397,9 @@ typedef enum ISM330DHCX_I2C_ENABLE = 0, ISM330DHCX_I2C_DISABLE = 1, } ism330dhcx_i2c_disable_t; -int32_t ism330dhcx_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_i2c_interface_set(const stmdev_ctx_t *ctx, ism330dhcx_i2c_disable_t val); -int32_t ism330dhcx_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_i2c_interface_get(const stmdev_ctx_t *ctx, ism330dhcx_i2c_disable_t *val); typedef struct @@ -3417,9 +3411,9 @@ typedef struct ism330dhcx_fsm_int1_b_t fsm_int1_b; ism330dhcx_mlc_int1_t mlc_int1; } ism330dhcx_pin_int1_route_t; -int32_t ism330dhcx_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pin_int1_route_set(const stmdev_ctx_t *ctx, ism330dhcx_pin_int1_route_t *val); -int32_t ism330dhcx_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pin_int1_route_get(const stmdev_ctx_t *ctx, ism330dhcx_pin_int1_route_t *val); typedef struct @@ -3431,9 +3425,9 @@ typedef struct ism330dhcx_fsm_int2_b_t fsm_int2_b; ism330dhcx_mlc_int2_t mlc_int2; } ism330dhcx_pin_int2_route_t; -int32_t ism330dhcx_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pin_int2_route_set(const stmdev_ctx_t *ctx, ism330dhcx_pin_int2_route_t *val); -int32_t ism330dhcx_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pin_int2_route_get(const stmdev_ctx_t *ctx, ism330dhcx_pin_int2_route_t *val); typedef enum @@ -3441,9 +3435,9 @@ typedef enum ISM330DHCX_PUSH_PULL = 0, ISM330DHCX_OPEN_DRAIN = 1, } ism330dhcx_pp_od_t; -int32_t ism330dhcx_pin_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pin_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_pp_od_t val); -int32_t ism330dhcx_pin_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pin_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_pp_od_t *val); typedef enum @@ -3451,13 +3445,13 @@ typedef enum ISM330DHCX_ACTIVE_HIGH = 0, ISM330DHCX_ACTIVE_LOW = 1, } ism330dhcx_h_lactive_t; -int32_t ism330dhcx_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pin_polarity_set(const stmdev_ctx_t *ctx, ism330dhcx_h_lactive_t val); -int32_t ism330dhcx_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pin_polarity_get(const stmdev_ctx_t *ctx, ism330dhcx_h_lactive_t *val); -int32_t ism330dhcx_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dhcx_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3466,9 +3460,9 @@ typedef enum ISM330DHCX_BASE_PULSED_EMB_LATCHED = 2, ISM330DHCX_ALL_INT_LATCHED = 3, } ism330dhcx_lir_t; -int32_t ism330dhcx_int_notification_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_int_notification_set(const stmdev_ctx_t *ctx, ism330dhcx_lir_t val); -int32_t ism330dhcx_int_notification_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_int_notification_get(const stmdev_ctx_t *ctx, ism330dhcx_lir_t *val); typedef enum @@ -3476,34 +3470,34 @@ typedef enum ISM330DHCX_LSb_FS_DIV_64 = 0, ISM330DHCX_LSb_FS_DIV_256 = 1, } ism330dhcx_wake_ths_w_t; -int32_t ism330dhcx_wkup_ths_weight_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_wkup_ths_weight_set(const stmdev_ctx_t *ctx, ism330dhcx_wake_ths_w_t val); -int32_t ism330dhcx_wkup_ths_weight_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_wkup_ths_weight_get(const stmdev_ctx_t *ctx, ism330dhcx_wake_ths_w_t *val); -int32_t ism330dhcx_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_wkup_threshold_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dhcx_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dhcx_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dhcx_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { ISM330DHCX_DRIVE_SLEEP_CHG_EVENT = 0, ISM330DHCX_DRIVE_SLEEP_STATUS = 1, } ism330dhcx_sleep_status_on_int_t; -int32_t ism330dhcx_act_pin_notification_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_act_pin_notification_set(const stmdev_ctx_t *ctx, ism330dhcx_sleep_status_on_int_t val); -int32_t ism330dhcx_act_pin_notification_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_act_pin_notification_get(const stmdev_ctx_t *ctx, ism330dhcx_sleep_status_on_int_t *val); typedef enum @@ -3513,32 +3507,32 @@ typedef enum ISM330DHCX_XL_12Hz5_GY_SLEEP = 2, ISM330DHCX_XL_12Hz5_GY_PD = 3, } ism330dhcx_inact_en_t; -int32_t ism330dhcx_act_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_act_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_inact_en_t val); -int32_t ism330dhcx_act_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_act_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_inact_en_t *val); -int32_t ism330dhcx_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dhcx_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_tap_threshold_x_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_tap_threshold_x_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3550,38 +3544,38 @@ typedef enum ISM330DHCX_YZX = 5, ISM330DHCX_ZXY = 6, } ism330dhcx_tap_priority_t; -int32_t ism330dhcx_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_axis_priority_set(const stmdev_ctx_t *ctx, ism330dhcx_tap_priority_t val); -int32_t ism330dhcx_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_axis_priority_get(const stmdev_ctx_t *ctx, ism330dhcx_tap_priority_t *val); -int32_t ism330dhcx_tap_threshold_y_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_tap_threshold_y_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_tap_threshold_z_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_tap_threshold_z_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dhcx_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dhcx_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dhcx_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { ISM330DHCX_ONLY_SINGLE = 0, ISM330DHCX_BOTH_SINGLE_DOUBLE = 1, } ism330dhcx_single_double_tap_t; -int32_t ism330dhcx_tap_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_single_double_tap_t val); -int32_t ism330dhcx_tap_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tap_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_single_double_tap_t *val); typedef enum @@ -3591,13 +3585,13 @@ typedef enum ISM330DHCX_DEG_60 = 2, ISM330DHCX_DEG_50 = 3, } ism330dhcx_sixd_ths_t; -int32_t ism330dhcx_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_6d_threshold_set(const stmdev_ctx_t *ctx, ism330dhcx_sixd_ths_t val); -int32_t ism330dhcx_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_6d_threshold_get(const stmdev_ctx_t *ctx, ism330dhcx_sixd_ths_t *val); -int32_t ism330dhcx_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dhcx_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3610,22 +3604,22 @@ typedef enum ISM330DHCX_FF_TSH_469mg = 6, ISM330DHCX_FF_TSH_500mg = 7, } ism330dhcx_ff_ths_t; -int32_t ism330dhcx_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_ff_threshold_set(const stmdev_ctx_t *ctx, ism330dhcx_ff_ths_t val); -int32_t ism330dhcx_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_ff_threshold_get(const stmdev_ctx_t *ctx, ism330dhcx_ff_ths_t *val); -int32_t ism330dhcx_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dhcx_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_fifo_watermark_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t ism330dhcx_fifo_watermark_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t ism330dhcx_compression_algo_init_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_compression_algo_init_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_compression_algo_init_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_compression_algo_init_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3636,24 +3630,24 @@ typedef enum ISM330DHCX_CMP_16_TO_1 = 0x06, ISM330DHCX_CMP_32_TO_1 = 0x07, } ism330dhcx_uncoptr_rate_t; -int32_t ism330dhcx_compression_algo_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_compression_algo_set(const stmdev_ctx_t *ctx, ism330dhcx_uncoptr_rate_t val); -int32_t ism330dhcx_compression_algo_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_compression_algo_get(const stmdev_ctx_t *ctx, ism330dhcx_uncoptr_rate_t *val); -int32_t ism330dhcx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_compression_algo_real_time_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_compression_algo_real_time_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_compression_algo_real_time_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_compression_algo_real_time_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3671,9 +3665,9 @@ typedef enum ISM330DHCX_XL_BATCHED_AT_6667Hz = 10, ISM330DHCX_XL_BATCHED_AT_6Hz5 = 11, } ism330dhcx_bdr_xl_t; -int32_t ism330dhcx_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_xl_batch_set(const stmdev_ctx_t *ctx, ism330dhcx_bdr_xl_t val); -int32_t ism330dhcx_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_xl_batch_get(const stmdev_ctx_t *ctx, ism330dhcx_bdr_xl_t *val); typedef enum @@ -3691,9 +3685,9 @@ typedef enum ISM330DHCX_GY_BATCHED_AT_6667Hz = 10, ISM330DHCX_GY_BATCHED_6Hz5 = 11, } ism330dhcx_bdr_gy_t; -int32_t ism330dhcx_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_gy_batch_set(const stmdev_ctx_t *ctx, ism330dhcx_bdr_gy_t val); -int32_t ism330dhcx_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_gy_batch_get(const stmdev_ctx_t *ctx, ism330dhcx_bdr_gy_t *val); typedef enum @@ -3705,9 +3699,9 @@ typedef enum ISM330DHCX_STREAM_MODE = 6, ISM330DHCX_BYPASS_TO_FIFO_MODE = 7, } ism330dhcx_fifo_mode_t; -int32_t ism330dhcx_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_fifo_mode_t val); -int32_t ism330dhcx_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_fifo_mode_t *val); typedef enum @@ -3717,9 +3711,9 @@ typedef enum ISM330DHCX_TEMP_BATCHED_AT_12Hz5 = 2, ISM330DHCX_TEMP_BATCHED_AT_1Hz6 = 3, } ism330dhcx_odr_t_batch_t; -int32_t ism330dhcx_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_temp_batch_set(const stmdev_ctx_t *ctx, ism330dhcx_odr_t_batch_t val); -int32_t ism330dhcx_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_temp_batch_get(const stmdev_ctx_t *ctx, ism330dhcx_odr_t_batch_t *val); typedef enum @@ -3729,9 +3723,9 @@ typedef enum ISM330DHCX_DEC_8 = 2, ISM330DHCX_DEC_32 = 3, } ism330dhcx_odr_ts_batch_t; -int32_t ism330dhcx_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, ism330dhcx_odr_ts_batch_t val); -int32_t ism330dhcx_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, ism330dhcx_odr_ts_batch_t *val); typedef enum @@ -3739,33 +3733,33 @@ typedef enum ISM330DHCX_XL_BATCH_EVENT = 0, ISM330DHCX_GYRO_BATCH_EVENT = 1, } ism330dhcx_trig_counter_bdr_t; -int32_t ism330dhcx_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, ism330dhcx_trig_counter_bdr_t val); -int32_t ism330dhcx_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, ism330dhcx_trig_counter_bdr_t *val); -int32_t ism330dhcx_rst_batch_counter_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_rst_batch_counter_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_batch_counter_threshold_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t ism330dhcx_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t ism330dhcx_fifo_data_level_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t ism330dhcx_fifo_status_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_status_get(const stmdev_ctx_t *ctx, ism330dhcx_fifo_status2_t *val); -int32_t ism330dhcx_fifo_full_flag_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3792,32 +3786,32 @@ typedef enum ISM330DHCX_ROTATION_TAG, ISM330DHCX_SENSORHUB_NACK_TAG = 0x19, } ism330dhcx_fifo_tag_t; -int32_t ism330dhcx_fifo_sensor_tag_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, ism330dhcx_fifo_tag_t *val); -int32_t ism330dhcx_fifo_pedo_batch_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_fifo_pedo_batch_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_sh_batch_slave_0_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_sh_batch_slave_0_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_sh_batch_slave_1_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_sh_batch_slave_1_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_sh_batch_slave_2_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_sh_batch_slave_2_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_sh_batch_slave_3_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_sh_batch_slave_3_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3828,9 +3822,9 @@ typedef enum ISM330DHCX_LEVEL_TRIGGER = 2, ISM330DHCX_EDGE_TRIGGER = 4, } ism330dhcx_den_mode_t; -int32_t ism330dhcx_den_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_den_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_den_mode_t val); -int32_t ism330dhcx_den_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_den_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_den_mode_t *val); typedef enum @@ -3838,9 +3832,9 @@ typedef enum ISM330DHCX_DEN_ACT_LOW = 0, ISM330DHCX_DEN_ACT_HIGH = 1, } ism330dhcx_den_lh_t; -int32_t ism330dhcx_den_polarity_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_den_polarity_set(const stmdev_ctx_t *ctx, ism330dhcx_den_lh_t val); -int32_t ism330dhcx_den_polarity_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_den_polarity_get(const stmdev_ctx_t *ctx, ism330dhcx_den_lh_t *val); typedef enum @@ -3849,40 +3843,40 @@ typedef enum ISM330DHCX_STAMP_IN_XL_DATA = 1, ISM330DHCX_STAMP_IN_GY_XL_DATA = 2, } ism330dhcx_den_xl_g_t; -int32_t ism330dhcx_den_enable_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_den_enable_set(const stmdev_ctx_t *ctx, ism330dhcx_den_xl_g_t val); -int32_t ism330dhcx_den_enable_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_den_enable_get(const stmdev_ctx_t *ctx, ism330dhcx_den_xl_g_t *val); -int32_t ism330dhcx_den_mark_axis_x_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_den_mark_axis_x_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_den_mark_axis_y_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_den_mark_axis_y_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_den_mark_axis_z_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_den_mark_axis_z_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dhcx_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_pedo_step_detect_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pedo_step_detect_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_pedo_debounce_steps_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ism330dhcx_pedo_debounce_steps_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ism330dhcx_pedo_steps_period_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pedo_steps_period_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t ism330dhcx_pedo_steps_period_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pedo_steps_period_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum @@ -3890,34 +3884,34 @@ typedef enum ISM330DHCX_EVERY_STEP = 0, ISM330DHCX_COUNT_OVERFLOW = 1, } ism330dhcx_carry_count_en_t; -int32_t ism330dhcx_pedo_int_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pedo_int_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_carry_count_en_t val); -int32_t ism330dhcx_pedo_int_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_pedo_int_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_carry_count_en_t *val); -int32_t ism330dhcx_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dhcx_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_motion_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_motion_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dhcx_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_mag_sensitivity_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t ism330dhcx_mag_sensitivity_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t ism330dhcx_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val); -int32_t ism330dhcx_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t ism330dhcx_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val); +int32_t ism330dhcx_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t ism330dhcx_mag_soft_iron_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t ism330dhcx_mag_soft_iron_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum @@ -3929,9 +3923,9 @@ typedef enum ISM330DHCX_Z_EQ_MIN_Z = 4, ISM330DHCX_Z_EQ_Z = 5, } ism330dhcx_mag_z_axis_t; -int32_t ism330dhcx_mag_z_orient_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mag_z_orient_set(const stmdev_ctx_t *ctx, ism330dhcx_mag_z_axis_t val); -int32_t ism330dhcx_mag_z_orient_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mag_z_orient_get(const stmdev_ctx_t *ctx, ism330dhcx_mag_z_axis_t *val); typedef enum @@ -3943,9 +3937,9 @@ typedef enum ISM330DHCX_Y_EQ_MIN_Z = 4, ISM330DHCX_Y_EQ_Z = 5, } ism330dhcx_mag_y_axis_t; -int32_t ism330dhcx_mag_y_orient_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mag_y_orient_set(const stmdev_ctx_t *ctx, ism330dhcx_mag_y_axis_t val); -int32_t ism330dhcx_mag_y_orient_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mag_y_orient_get(const stmdev_ctx_t *ctx, ism330dhcx_mag_y_axis_t *val); typedef enum @@ -3957,29 +3951,29 @@ typedef enum ISM330DHCX_X_EQ_MIN_Z = 4, ISM330DHCX_X_EQ_Z = 5, } ism330dhcx_mag_x_axis_t; -int32_t ism330dhcx_mag_x_orient_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mag_x_orient_set(const stmdev_ctx_t *ctx, ism330dhcx_mag_x_axis_t val); -int32_t ism330dhcx_mag_x_orient_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mag_x_orient_get(const stmdev_ctx_t *ctx, ism330dhcx_mag_x_axis_t *val); -int32_t ism330dhcx_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dhcx_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { ism330dhcx_fsm_enable_a_t fsm_enable_a; ism330dhcx_fsm_enable_b_t fsm_enable_b; } ism330dhcx_emb_fsm_enable_t; -int32_t ism330dhcx_fsm_enable_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fsm_enable_set(const stmdev_ctx_t *ctx, ism330dhcx_emb_fsm_enable_t *val); -int32_t ism330dhcx_fsm_enable_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fsm_enable_get(const stmdev_ctx_t *ctx, ism330dhcx_emb_fsm_enable_t *val); -int32_t ism330dhcx_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t ism330dhcx_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t ism330dhcx_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t ism330dhcx_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum { @@ -3987,9 +3981,9 @@ typedef enum ISM330DHCX_LC_CLEAR = 1, ISM330DHCX_LC_CLEAR_DONE = 2, } ism330dhcx_fsm_lc_clr_t; -int32_t ism330dhcx_long_clr_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_long_clr_set(const stmdev_ctx_t *ctx, ism330dhcx_fsm_lc_clr_t val); -int32_t ism330dhcx_long_clr_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_long_clr_get(const stmdev_ctx_t *ctx, ism330dhcx_fsm_lc_clr_t *val); typedef struct @@ -4011,7 +4005,7 @@ typedef struct ism330dhcx_fsm_outs15_t fsm_outs15; ism330dhcx_fsm_outs16_t fsm_outs16; } ism330dhcx_fsm_out_t; -int32_t ism330dhcx_fsm_out_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fsm_out_get(const stmdev_ctx_t *ctx, ism330dhcx_fsm_out_t *val); typedef enum @@ -4021,33 +4015,33 @@ typedef enum ISM330DHCX_ODR_FSM_52Hz = 2, ISM330DHCX_ODR_FSM_104Hz = 3, } ism330dhcx_fsm_odr_t; -int32_t ism330dhcx_fsm_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fsm_data_rate_set(const stmdev_ctx_t *ctx, ism330dhcx_fsm_odr_t val); -int32_t ism330dhcx_fsm_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fsm_data_rate_get(const stmdev_ctx_t *ctx, ism330dhcx_fsm_odr_t *val); -int32_t ism330dhcx_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dhcx_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_long_cnt_int_value_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t ism330dhcx_long_cnt_int_value_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t ism330dhcx_fsm_number_of_programs_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ism330dhcx_fsm_number_of_programs_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ism330dhcx_fsm_start_address_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t ism330dhcx_fsm_start_address_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t ism330dhcx_mlc_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_mlc_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dhcx_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dhcx_mlc_status_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mlc_status_get(const stmdev_ctx_t *ctx, ism330dhcx_mlc_status_mainpage_t *val); typedef enum @@ -4057,9 +4051,9 @@ typedef enum ISM330DHCX_ODR_PRGS_52Hz = 2, ISM330DHCX_ODR_PRGS_104Hz = 3, } ism330dhcx_mlc_odr_t; -int32_t ism330dhcx_mlc_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mlc_data_rate_set(const stmdev_ctx_t *ctx, ism330dhcx_mlc_odr_t val); -int32_t ism330dhcx_mlc_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_mlc_data_rate_get(const stmdev_ctx_t *ctx, ism330dhcx_mlc_odr_t *val); typedef struct @@ -4083,7 +4077,7 @@ typedef struct ism330dhcx_sensor_hub_17_t sh_byte_17; ism330dhcx_sensor_hub_18_t sh_byte_18; } ism330dhcx_emb_sh_read_t; -int32_t ism330dhcx_sh_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_read_data_raw_get(const stmdev_ctx_t *ctx, ism330dhcx_emb_sh_read_t *val, uint8_t len); @@ -4094,27 +4088,27 @@ typedef enum ISM330DHCX_SLV_0_1_2 = 2, ISM330DHCX_SLV_0_1_2_3 = 3, } ism330dhcx_aux_sens_on_t; -int32_t ism330dhcx_sh_slave_connected_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_slave_connected_set(const stmdev_ctx_t *ctx, ism330dhcx_aux_sens_on_t val); -int32_t ism330dhcx_sh_slave_connected_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_slave_connected_get(const stmdev_ctx_t *ctx, ism330dhcx_aux_sens_on_t *val); -int32_t ism330dhcx_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dhcx_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { ISM330DHCX_EXT_PULL_UP = 0, ISM330DHCX_INTERNAL_PULL_UP = 1, } ism330dhcx_shub_pu_en_t; -int32_t ism330dhcx_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_pin_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_shub_pu_en_t val); -int32_t ism330dhcx_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_pin_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_shub_pu_en_t *val); -int32_t ism330dhcx_sh_pass_through_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dhcx_sh_pass_through_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -4122,9 +4116,9 @@ typedef enum ISM330DHCX_EXT_ON_INT2_PIN = 1, ISM330DHCX_XL_GY_DRDY = 0, } ism330dhcx_start_config_t; -int32_t ism330dhcx_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_syncro_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_start_config_t val); -int32_t ism330dhcx_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_syncro_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_start_config_t *val); typedef enum @@ -4132,13 +4126,13 @@ typedef enum ISM330DHCX_EACH_SH_CYCLE = 0, ISM330DHCX_ONLY_FIRST_CYCLE = 1, } ism330dhcx_write_once_t; -int32_t ism330dhcx_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_write_mode_set(const stmdev_ctx_t *ctx, ism330dhcx_write_once_t val); -int32_t ism330dhcx_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_write_mode_get(const stmdev_ctx_t *ctx, ism330dhcx_write_once_t *val); -int32_t ism330dhcx_sh_reset_set(stmdev_ctx_t *ctx); -int32_t ism330dhcx_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dhcx_sh_reset_set(const stmdev_ctx_t *ctx); +int32_t ism330dhcx_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -4147,9 +4141,9 @@ typedef enum ISM330DHCX_SH_ODR_26Hz = 2, ISM330DHCX_SH_ODR_13Hz = 3, } ism330dhcx_shub_odr_t; -int32_t ism330dhcx_sh_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_data_rate_set(const stmdev_ctx_t *ctx, ism330dhcx_shub_odr_t val); -int32_t ism330dhcx_sh_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_data_rate_get(const stmdev_ctx_t *ctx, ism330dhcx_shub_odr_t *val); typedef struct @@ -4158,7 +4152,7 @@ typedef struct uint8_t slv0_subadd; uint8_t slv0_data; } ism330dhcx_sh_cfg_write_t; -int32_t ism330dhcx_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_cfg_write(const stmdev_ctx_t *ctx, ism330dhcx_sh_cfg_write_t *val); typedef struct @@ -4167,16 +4161,16 @@ typedef struct uint8_t slv_subadd; uint8_t slv_len; } ism330dhcx_sh_cfg_read_t; -int32_t ism330dhcx_sh_slv0_cfg_read(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, ism330dhcx_sh_cfg_read_t *val); -int32_t ism330dhcx_sh_slv1_cfg_read(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, ism330dhcx_sh_cfg_read_t *val); -int32_t ism330dhcx_sh_slv2_cfg_read(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, ism330dhcx_sh_cfg_read_t *val); -int32_t ism330dhcx_sh_slv3_cfg_read(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, ism330dhcx_sh_cfg_read_t *val); -int32_t ism330dhcx_sh_status_get(stmdev_ctx_t *ctx, +int32_t ism330dhcx_sh_status_get(const stmdev_ctx_t *ctx, ism330dhcx_status_master_t *val); /** diff --git a/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.c b/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.c index 0c3e753f..82ea4cda 100644 --- a/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.c +++ b/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.c @@ -46,11 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak ism330dlc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak ism330dlc_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -66,11 +72,17 @@ int32_t __weak ism330dlc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak ism330dlc_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak ism330dlc_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -159,7 +171,7 @@ float_t ism330dlc_from_lsb_to_celsius(int16_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_full_scale_set(const stmdev_ctx_t *ctx, ism330dlc_fs_xl_t val) { ism330dlc_ctrl1_xl_t ctrl1_xl; @@ -185,7 +197,7 @@ int32_t ism330dlc_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_full_scale_get(const stmdev_ctx_t *ctx, ism330dlc_fs_xl_t *val) { ism330dlc_ctrl1_xl_t ctrl1_xl; @@ -227,7 +239,7 @@ int32_t ism330dlc_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_data_rate_set(const stmdev_ctx_t *ctx, ism330dlc_odr_xl_t val) { ism330dlc_ctrl1_xl_t ctrl1_xl; @@ -253,7 +265,7 @@ int32_t ism330dlc_xl_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_data_rate_get(const stmdev_ctx_t *ctx, ism330dlc_odr_xl_t *val) { ism330dlc_ctrl1_xl_t ctrl1_xl; @@ -327,7 +339,7 @@ int32_t ism330dlc_xl_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_gy_full_scale_set(const stmdev_ctx_t *ctx, ism330dlc_fs_g_t val) { ism330dlc_ctrl2_g_t ctrl2_g; @@ -351,7 +363,7 @@ int32_t ism330dlc_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_gy_full_scale_get(const stmdev_ctx_t *ctx, ism330dlc_fs_g_t *val) { ism330dlc_ctrl2_g_t ctrl2_g; @@ -396,7 +408,7 @@ int32_t ism330dlc_gy_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_gy_data_rate_set(const stmdev_ctx_t *ctx, ism330dlc_odr_g_t val) { ism330dlc_ctrl2_g_t ctrl2_g; @@ -420,7 +432,7 @@ int32_t ism330dlc_gy_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_gy_data_rate_get(const stmdev_ctx_t *ctx, ism330dlc_odr_g_t *val) { ism330dlc_ctrl2_g_t ctrl2_g; @@ -489,7 +501,7 @@ int32_t ism330dlc_gy_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_block_data_update_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_ctrl3_c_t ctrl3_c; @@ -513,7 +525,7 @@ int32_t ism330dlc_block_data_update_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_block_data_update_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_ctrl3_c_t ctrl3_c; @@ -533,7 +545,7 @@ int32_t ism330dlc_block_data_update_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_offset_weight_set(const stmdev_ctx_t *ctx, ism330dlc_usr_off_w_t val) { ism330dlc_ctrl6_c_t ctrl6_c; @@ -558,7 +570,7 @@ int32_t ism330dlc_xl_offset_weight_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_offset_weight_get(const stmdev_ctx_t *ctx, ism330dlc_usr_off_w_t *val) { ism330dlc_ctrl6_c_t ctrl6_c; @@ -591,7 +603,7 @@ int32_t ism330dlc_xl_offset_weight_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_power_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_power_mode_set(const stmdev_ctx_t *ctx, ism330dlc_xl_hm_mode_t val) { ism330dlc_ctrl6_c_t ctrl6_c; @@ -615,7 +627,7 @@ int32_t ism330dlc_xl_power_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_power_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_power_mode_get(const stmdev_ctx_t *ctx, ism330dlc_xl_hm_mode_t *val) { ism330dlc_ctrl6_c_t ctrl6_c; @@ -650,7 +662,7 @@ int32_t ism330dlc_xl_power_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_rounding_on_status_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_rounding_on_status_set(const stmdev_ctx_t *ctx, ism330dlc_rounding_status_t val) { ism330dlc_ctrl7_g_t ctrl7_g; @@ -676,7 +688,7 @@ int32_t ism330dlc_rounding_on_status_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_rounding_on_status_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_rounding_on_status_get(const stmdev_ctx_t *ctx, ism330dlc_rounding_status_t *val) { ism330dlc_ctrl7_g_t ctrl7_g; @@ -709,7 +721,7 @@ int32_t ism330dlc_rounding_on_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_gy_power_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_gy_power_mode_set(const stmdev_ctx_t *ctx, ism330dlc_g_hm_mode_t val) { ism330dlc_ctrl7_g_t ctrl7_g; @@ -733,7 +745,7 @@ int32_t ism330dlc_gy_power_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_gy_power_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_gy_power_mode_get(const stmdev_ctx_t *ctx, ism330dlc_g_hm_mode_t *val) { ism330dlc_ctrl7_g_t ctrl7_g; @@ -767,7 +779,7 @@ int32_t ism330dlc_gy_power_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_all_sources_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_all_sources_get(const stmdev_ctx_t *ctx, ism330dlc_all_sources_t *val) { int32_t ret; @@ -819,7 +831,7 @@ int32_t ism330dlc_all_sources_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_status_reg_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_status_reg_get(const stmdev_ctx_t *ctx, ism330dlc_status_reg_t *val) { int32_t ret; @@ -836,7 +848,7 @@ int32_t ism330dlc_status_reg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_status_reg_t status_reg; @@ -856,7 +868,7 @@ int32_t ism330dlc_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_status_reg_t status_reg; @@ -876,7 +888,7 @@ int32_t ism330dlc_gy_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_status_reg_t status_reg; @@ -898,7 +910,7 @@ int32_t ism330dlc_temp_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ism330dlc_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; ret = ism330dlc_write_reg(ctx, ISM330DLC_X_OFS_USR, buff, 3); @@ -916,7 +928,7 @@ int32_t ism330dlc_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ism330dlc_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_X_OFS_USR, buff, 3); @@ -946,7 +958,7 @@ int32_t ism330dlc_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_ctrl10_c_t ctrl10_c; int32_t ret; @@ -977,7 +989,7 @@ int32_t ism330dlc_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dlc_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_ctrl10_c_t ctrl10_c; int32_t ret; @@ -1001,7 +1013,7 @@ int32_t ism330dlc_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_timestamp_res_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_timestamp_res_set(const stmdev_ctx_t *ctx, ism330dlc_timer_hr_t val) { ism330dlc_wake_up_dur_t wake_up_dur; @@ -1032,7 +1044,7 @@ int32_t ism330dlc_timestamp_res_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_timestamp_res_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_timestamp_res_get(const stmdev_ctx_t *ctx, ism330dlc_timer_hr_t *val) { ism330dlc_wake_up_dur_t wake_up_dur; @@ -1079,7 +1091,7 @@ int32_t ism330dlc_timestamp_res_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_rounding_mode_set(const stmdev_ctx_t *ctx, ism330dlc_rounding_t val) { ism330dlc_ctrl5_c_t ctrl5_c; @@ -1104,7 +1116,7 @@ int32_t ism330dlc_rounding_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_rounding_mode_get(const stmdev_ctx_t *ctx, ism330dlc_rounding_t *val) { ism330dlc_ctrl5_c_t ctrl5_c; @@ -1162,7 +1174,7 @@ int32_t ism330dlc_rounding_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t ism330dlc_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1182,7 +1194,7 @@ int32_t ism330dlc_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_angular_rate_raw_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -1207,7 +1219,7 @@ int32_t ism330dlc_angular_rate_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -1231,7 +1243,7 @@ int32_t ism330dlc_acceleration_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_mag_calibrated_raw_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_mag_calibrated_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -1256,7 +1268,7 @@ int32_t ism330dlc_mag_calibrated_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_fifo_raw_data_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_raw_data_get(const stmdev_ctx_t *ctx, uint8_t *buffer, uint8_t len) { @@ -1287,7 +1299,7 @@ int32_t ism330dlc_fifo_raw_data_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_mem_bank_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_mem_bank_set(const stmdev_ctx_t *ctx, ism330dlc_func_cfg_en_t val) { ism330dlc_func_cfg_access_t func_cfg_access; @@ -1314,7 +1326,7 @@ int32_t ism330dlc_mem_bank_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_mem_bank_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_mem_bank_get(const stmdev_ctx_t *ctx, ism330dlc_func_cfg_en_t *val) { ism330dlc_func_cfg_access_t func_cfg_access; @@ -1344,7 +1356,7 @@ int32_t ism330dlc_mem_bank_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_data_ready_mode_set(const stmdev_ctx_t *ctx, ism330dlc_drdy_pulsed_t val) { ism330dlc_drdy_pulse_cfg_t drdy_pulse_cfg_g; @@ -1370,7 +1382,7 @@ int32_t ism330dlc_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_data_ready_mode_get(const stmdev_ctx_t *ctx, ism330dlc_drdy_pulsed_t *val) { ism330dlc_drdy_pulse_cfg_t drdy_pulse_cfg_g; @@ -1404,7 +1416,7 @@ int32_t ism330dlc_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t ism330dlc_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; ret = ism330dlc_read_reg(ctx, ISM330DLC_WHO_AM_I, buff, 1); @@ -1420,7 +1432,7 @@ int32_t ism330dlc_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1443,7 +1455,7 @@ int32_t ism330dlc_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dlc_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1461,7 +1473,7 @@ int32_t ism330dlc_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_data_format_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_data_format_set(const stmdev_ctx_t *ctx, ism330dlc_ble_t val) { ism330dlc_ctrl3_c_t ctrl3_c; @@ -1485,7 +1497,7 @@ int32_t ism330dlc_data_format_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_data_format_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_data_format_get(const stmdev_ctx_t *ctx, ism330dlc_ble_t *val) { ism330dlc_ctrl3_c_t ctrl3_c; @@ -1519,7 +1531,7 @@ int32_t ism330dlc_data_format_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1543,7 +1555,7 @@ int32_t ism330dlc_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dlc_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1561,7 +1573,7 @@ int32_t ism330dlc_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1584,7 +1596,7 @@ int32_t ism330dlc_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dlc_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1602,7 +1614,7 @@ int32_t ism330dlc_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_self_test_set(const stmdev_ctx_t *ctx, ism330dlc_st_xl_t val) { ism330dlc_ctrl5_c_t ctrl5_c; @@ -1626,7 +1638,7 @@ int32_t ism330dlc_xl_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_self_test_get(const stmdev_ctx_t *ctx, ism330dlc_st_xl_t *val) { ism330dlc_ctrl5_c_t ctrl5_c; @@ -1663,7 +1675,7 @@ int32_t ism330dlc_xl_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_gy_self_test_set(const stmdev_ctx_t *ctx, ism330dlc_st_g_t val) { ism330dlc_ctrl5_c_t ctrl5_c; @@ -1687,7 +1699,7 @@ int32_t ism330dlc_gy_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_gy_self_test_get(const stmdev_ctx_t *ctx, ism330dlc_st_g_t *val) { ism330dlc_ctrl5_c_t ctrl5_c; @@ -1738,7 +1750,7 @@ int32_t ism330dlc_gy_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_ctrl4_c_t ctrl4_c; @@ -1763,7 +1775,7 @@ int32_t ism330dlc_filter_settling_mask_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_ctrl4_c_t ctrl4_c; @@ -1783,7 +1795,7 @@ int32_t ism330dlc_filter_settling_mask_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, ism330dlc_slope_fds_t val) { ism330dlc_tap_cfg_t tap_cfg; @@ -1808,7 +1820,7 @@ int32_t ism330dlc_xl_hp_path_internal_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, ism330dlc_slope_fds_t *val) { ism330dlc_tap_cfg_t tap_cfg; @@ -1855,7 +1867,7 @@ int32_t ism330dlc_xl_hp_path_internal_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_filter_analog_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_filter_analog_set(const stmdev_ctx_t *ctx, ism330dlc_bw0_xl_t val) { ism330dlc_ctrl1_xl_t ctrl1_xl; @@ -1882,7 +1894,7 @@ int32_t ism330dlc_xl_filter_analog_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_filter_analog_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_filter_analog_get(const stmdev_ctx_t *ctx, ism330dlc_bw0_xl_t *val) { ism330dlc_ctrl1_xl_t ctrl1_xl; @@ -1930,7 +1942,7 @@ int32_t ism330dlc_xl_filter_analog_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_lp1_bandwidth_set(const stmdev_ctx_t *ctx, ism330dlc_lpf1_bw_sel_t val) { ism330dlc_ctrl1_xl_t ctrl1_xl; @@ -1972,7 +1984,7 @@ int32_t ism330dlc_xl_lp1_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_lp1_bandwidth_get(const stmdev_ctx_t *ctx, ism330dlc_lpf1_bw_sel_t *val) { ism330dlc_ctrl1_xl_t ctrl1_xl; @@ -2022,7 +2034,7 @@ int32_t ism330dlc_xl_lp1_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, ism330dlc_input_composite_t val) { ism330dlc_ctrl8_xl_t ctrl8_xl; @@ -2051,7 +2063,7 @@ int32_t ism330dlc_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, ism330dlc_input_composite_t *val) { ism330dlc_ctrl8_xl_t ctrl8_xl; @@ -2121,7 +2133,7 @@ int32_t ism330dlc_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_reference_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_ctrl8_xl_t ctrl8_xl; @@ -2147,7 +2159,7 @@ int32_t ism330dlc_xl_reference_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_reference_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_ctrl8_xl_t ctrl8_xl; @@ -2167,7 +2179,7 @@ int32_t ism330dlc_xl_reference_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_hp_bandwidth_set(const stmdev_ctx_t *ctx, ism330dlc_hpcf_xl_t val) { ism330dlc_ctrl8_xl_t ctrl8_xl; @@ -2195,7 +2207,7 @@ int32_t ism330dlc_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_hp_bandwidth_get(const stmdev_ctx_t *ctx, ism330dlc_hpcf_xl_t *val) { ism330dlc_ctrl8_xl_t ctrl8_xl; @@ -2257,7 +2269,7 @@ int32_t ism330dlc_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_ui_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_ui_lp1_bandwidth_set(const stmdev_ctx_t *ctx, ism330dlc_ui_lpf1_bw_sel_t val) { ism330dlc_ctrl1_xl_t ctrl1_xl; @@ -2299,7 +2311,7 @@ int32_t ism330dlc_xl_ui_lp1_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_ui_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_ui_lp1_bandwidth_get(const stmdev_ctx_t *ctx, ism330dlc_ui_lpf1_bw_sel_t *val) { ism330dlc_ctrl1_xl_t ctrl1_xl; @@ -2349,7 +2361,7 @@ int32_t ism330dlc_xl_ui_lp1_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_ui_slope_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_xl_ui_slope_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_ctrl8_xl_t reg; int32_t ret; @@ -2372,7 +2384,7 @@ int32_t ism330dlc_xl_ui_slope_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_ui_slope_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dlc_xl_ui_slope_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_ctrl8_xl_t reg; int32_t ret; @@ -2403,7 +2415,7 @@ int32_t ism330dlc_xl_ui_slope_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_aux_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_aux_lp_bandwidth_set(const stmdev_ctx_t *ctx, ism330dlc_filter_xl_conf_ois_t val) { ism330dlc_ctrl3_ois_t reg; @@ -2440,7 +2452,7 @@ int32_t ism330dlc_xl_aux_lp_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_xl_aux_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_aux_lp_bandwidth_get(const stmdev_ctx_t *ctx, ism330dlc_filter_xl_conf_ois_t *val) { ism330dlc_ctrl3_ois_t reg; @@ -2495,7 +2507,7 @@ int32_t ism330dlc_xl_aux_lp_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_gy_band_pass_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_gy_band_pass_set(const stmdev_ctx_t *ctx, ism330dlc_lpf1_sel_g_t val) { ism330dlc_ctrl4_c_t ctrl4_c; @@ -2547,7 +2559,7 @@ int32_t ism330dlc_gy_band_pass_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_gy_band_pass_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_gy_band_pass_get(const stmdev_ctx_t *ctx, ism330dlc_lpf1_sel_g_t *val) { ism330dlc_ctrl4_c_t ctrl4_c; @@ -2648,7 +2660,7 @@ int32_t ism330dlc_gy_band_pass_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_gy_ui_high_pass_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_gy_ui_high_pass_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_ctrl7_g_t reg; int32_t ret; @@ -2672,7 +2684,7 @@ int32_t ism330dlc_gy_ui_high_pass_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_gy_ui_high_pass_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dlc_gy_ui_high_pass_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_ctrl7_g_t reg; int32_t ret; @@ -2693,7 +2705,7 @@ int32_t ism330dlc_gy_ui_high_pass_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_gy_aux_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_gy_aux_bandwidth_set(const stmdev_ctx_t *ctx, ism330dlc_hp_en_ois_t val) { ism330dlc_ctrl7_g_t ctrl7_g; @@ -2735,7 +2747,7 @@ int32_t ism330dlc_gy_aux_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_gy_aux_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_gy_aux_bandwidth_get(const stmdev_ctx_t *ctx, ism330dlc_hp_en_ois_t *val) { ism330dlc_ctrl2_ois_t reg; @@ -2806,7 +2818,7 @@ int32_t ism330dlc_gy_aux_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_aux_status_reg_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_status_reg_get(const stmdev_ctx_t *ctx, ism330dlc_status_spiaux_t *val) { int32_t ret; @@ -2824,7 +2836,7 @@ int32_t ism330dlc_aux_status_reg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_status_spiaux_t reg; @@ -2844,7 +2856,7 @@ int32_t ism330dlc_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_status_spiaux_t reg; @@ -2864,7 +2876,7 @@ int32_t ism330dlc_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_status_spiaux_t reg; @@ -2884,7 +2896,7 @@ int32_t ism330dlc_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_aux_den_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_den_mode_set(const stmdev_ctx_t *ctx, ism330dlc_lvl_ois_t val) { ism330dlc_ctrl1_ois_t ctrl1_ois; @@ -2923,7 +2935,7 @@ int32_t ism330dlc_aux_den_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_aux_den_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_den_mode_get(const stmdev_ctx_t *ctx, ism330dlc_lvl_ois_t *val) { ism330dlc_ctrl1_ois_t ctrl1_ois; @@ -2968,7 +2980,7 @@ int32_t ism330dlc_aux_den_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_aux_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_int_ois_t reg; int32_t ret; @@ -2992,7 +3004,7 @@ int32_t ism330dlc_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_int_ois_t reg; @@ -3018,7 +3030,7 @@ int32_t ism330dlc_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_aux_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_mode_set(const stmdev_ctx_t *ctx, ism330dlc_ois_en_spi2_t val) { ism330dlc_ctrl1_ois_t reg; @@ -3050,7 +3062,7 @@ int32_t ism330dlc_aux_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_aux_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_mode_get(const stmdev_ctx_t *ctx, ism330dlc_ois_en_spi2_t *val) { ism330dlc_ctrl1_ois_t reg; @@ -3087,7 +3099,7 @@ int32_t ism330dlc_aux_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_aux_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_gy_full_scale_set(const stmdev_ctx_t *ctx, ism330dlc_fs_g_ois_t val) { ism330dlc_ctrl1_ois_t reg; @@ -3111,7 +3123,7 @@ int32_t ism330dlc_aux_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_aux_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_gy_full_scale_get(const stmdev_ctx_t *ctx, ism330dlc_fs_g_ois_t *val) { ism330dlc_ctrl1_ois_t reg; @@ -3156,7 +3168,7 @@ int32_t ism330dlc_aux_gy_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_aux_spi_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_spi_mode_set(const stmdev_ctx_t *ctx, ism330dlc_sim_ois_t val) { ism330dlc_ctrl1_ois_t reg; @@ -3180,7 +3192,7 @@ int32_t ism330dlc_aux_spi_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_aux_spi_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_spi_mode_get(const stmdev_ctx_t *ctx, ism330dlc_sim_ois_t *val) { ism330dlc_ctrl1_ois_t reg; @@ -3213,7 +3225,7 @@ int32_t ism330dlc_aux_spi_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_aux_data_format_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_data_format_set(const stmdev_ctx_t *ctx, ism330dlc_ble_ois_t val) { ism330dlc_ctrl1_ois_t reg; @@ -3237,7 +3249,7 @@ int32_t ism330dlc_aux_data_format_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_aux_data_format_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_data_format_get(const stmdev_ctx_t *ctx, ism330dlc_ble_ois_t *val) { ism330dlc_ctrl1_ois_t reg; @@ -3273,7 +3285,7 @@ int32_t ism330dlc_aux_data_format_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_aux_gy_clamp_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_gy_clamp_set(const stmdev_ctx_t *ctx, ism330dlc_st_ois_clampdis_t val) { ism330dlc_ctrl3_ois_t reg; @@ -3300,7 +3312,7 @@ int32_t ism330dlc_aux_gy_clamp_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_aux_gy_clamp_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_gy_clamp_get(const stmdev_ctx_t *ctx, ism330dlc_st_ois_clampdis_t *val) { ism330dlc_ctrl3_ois_t reg; @@ -3333,7 +3345,7 @@ int32_t ism330dlc_aux_gy_clamp_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_aux_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_gy_self_test_set(const stmdev_ctx_t *ctx, ism330dlc_st_ois_t val) { ism330dlc_ctrl3_ois_t reg; @@ -3357,7 +3369,7 @@ int32_t ism330dlc_aux_gy_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_aux_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_gy_self_test_get(const stmdev_ctx_t *ctx, ism330dlc_st_ois_t *val) { ism330dlc_ctrl3_ois_t reg; @@ -3394,7 +3406,7 @@ int32_t ism330dlc_aux_gy_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_aux_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_xl_full_scale_set(const stmdev_ctx_t *ctx, ism330dlc_fs_xl_ois_t val) { ism330dlc_ctrl3_ois_t reg; @@ -3418,7 +3430,7 @@ int32_t ism330dlc_aux_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_aux_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_xl_full_scale_get(const stmdev_ctx_t *ctx, ism330dlc_fs_xl_ois_t *val) { ism330dlc_ctrl3_ois_t reg; @@ -3459,7 +3471,7 @@ int32_t ism330dlc_aux_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_aux_den_polarity_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_den_polarity_set(const stmdev_ctx_t *ctx, ism330dlc_den_lh_ois_t val) { ism330dlc_ctrl3_ois_t reg; @@ -3483,7 +3495,7 @@ int32_t ism330dlc_aux_den_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_aux_den_polarity_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_den_polarity_get(const stmdev_ctx_t *ctx, ism330dlc_den_lh_ois_t *val) { ism330dlc_ctrl3_ois_t reg; @@ -3529,7 +3541,7 @@ int32_t ism330dlc_aux_den_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_spi_mode_set(stmdev_ctx_t *ctx, ism330dlc_sim_t val) +int32_t ism330dlc_spi_mode_set(const stmdev_ctx_t *ctx, ism330dlc_sim_t val) { ism330dlc_ctrl3_c_t ctrl3_c; int32_t ret; @@ -3552,7 +3564,7 @@ int32_t ism330dlc_spi_mode_set(stmdev_ctx_t *ctx, ism330dlc_sim_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_spi_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_spi_mode_get(const stmdev_ctx_t *ctx, ism330dlc_sim_t *val) { ism330dlc_ctrl3_c_t ctrl3_c; @@ -3585,7 +3597,7 @@ int32_t ism330dlc_spi_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_i2c_interface_set(const stmdev_ctx_t *ctx, ism330dlc_i2c_disable_t val) { ism330dlc_ctrl4_c_t ctrl4_c; @@ -3609,7 +3621,7 @@ int32_t ism330dlc_i2c_interface_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_i2c_interface_get(const stmdev_ctx_t *ctx, ism330dlc_i2c_disable_t *val) { ism330dlc_ctrl4_c_t ctrl4_c; @@ -3656,7 +3668,7 @@ int32_t ism330dlc_i2c_interface_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_pin_int1_route_set(const stmdev_ctx_t *ctx, ism330dlc_int1_route_t val) { ism330dlc_master_config_t master_config; @@ -3771,7 +3783,7 @@ int32_t ism330dlc_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_pin_int1_route_get(const stmdev_ctx_t *ctx, ism330dlc_int1_route_t *val) { ism330dlc_master_config_t master_config; @@ -3824,7 +3836,7 @@ int32_t ism330dlc_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_pin_int2_route_set(const stmdev_ctx_t *ctx, ism330dlc_int2_route_t val) { ism330dlc_int2_ctrl_t int2_ctrl; @@ -3927,7 +3939,7 @@ int32_t ism330dlc_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_pin_int2_route_get(const stmdev_ctx_t *ctx, ism330dlc_int2_route_t *val) { ism330dlc_int2_ctrl_t int2_ctrl; @@ -3970,7 +3982,7 @@ int32_t ism330dlc_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_pin_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_pin_mode_set(const stmdev_ctx_t *ctx, ism330dlc_pp_od_t val) { ism330dlc_ctrl3_c_t ctrl3_c; @@ -3994,7 +4006,7 @@ int32_t ism330dlc_pin_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_pin_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_pin_mode_get(const stmdev_ctx_t *ctx, ism330dlc_pp_od_t *val) { ism330dlc_ctrl3_c_t ctrl3_c; @@ -4027,7 +4039,7 @@ int32_t ism330dlc_pin_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_pin_polarity_set(const stmdev_ctx_t *ctx, ism330dlc_h_lactive_t val) { ism330dlc_ctrl3_c_t ctrl3_c; @@ -4051,7 +4063,7 @@ int32_t ism330dlc_pin_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_pin_polarity_get(const stmdev_ctx_t *ctx, ism330dlc_h_lactive_t *val) { ism330dlc_ctrl3_c_t ctrl3_c; @@ -4084,7 +4096,7 @@ int32_t ism330dlc_pin_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_ctrl4_c_t ctrl4_c; int32_t ret; @@ -4107,7 +4119,7 @@ int32_t ism330dlc_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dlc_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_ctrl4_c_t ctrl4_c; int32_t ret; @@ -4125,7 +4137,7 @@ int32_t ism330dlc_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_int_notification_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_int_notification_set(const stmdev_ctx_t *ctx, ism330dlc_lir_t val) { ism330dlc_tap_cfg_t tap_cfg; @@ -4149,7 +4161,7 @@ int32_t ism330dlc_int_notification_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_int_notification_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_int_notification_get(const stmdev_ctx_t *ctx, ism330dlc_lir_t *val) { ism330dlc_tap_cfg_t tap_cfg; @@ -4195,7 +4207,7 @@ int32_t ism330dlc_int_notification_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_wake_up_ths_t wake_up_ths; int32_t ret; @@ -4220,7 +4232,7 @@ int32_t ism330dlc_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dlc_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_wake_up_ths_t wake_up_ths; int32_t ret; @@ -4239,7 +4251,7 @@ int32_t ism330dlc_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_wake_up_dur_t wake_up_dur; int32_t ret; @@ -4264,7 +4276,7 @@ int32_t ism330dlc_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dlc_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_wake_up_dur_t wake_up_dur; int32_t ret; @@ -4296,7 +4308,7 @@ int32_t ism330dlc_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_ctrl4_c_t ctrl4_c; int32_t ret; @@ -4319,7 +4331,7 @@ int32_t ism330dlc_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dlc_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_ctrl4_c_t ctrl4_c; int32_t ret; @@ -4337,7 +4349,7 @@ int32_t ism330dlc_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_act_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_act_mode_set(const stmdev_ctx_t *ctx, ism330dlc_inact_en_t val) { ism330dlc_tap_cfg_t tap_cfg; @@ -4361,7 +4373,7 @@ int32_t ism330dlc_act_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_act_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_act_mode_get(const stmdev_ctx_t *ctx, ism330dlc_inact_en_t *val) { ism330dlc_tap_cfg_t tap_cfg; @@ -4402,7 +4414,7 @@ int32_t ism330dlc_act_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_wake_up_dur_t wake_up_dur; int32_t ret; @@ -4427,7 +4439,7 @@ int32_t ism330dlc_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dlc_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_wake_up_dur_t wake_up_dur; int32_t ret; @@ -4459,7 +4471,7 @@ int32_t ism330dlc_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_tap_src_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_tap_src_get(const stmdev_ctx_t *ctx, ism330dlc_tap_src_t *val) { int32_t ret; @@ -4475,7 +4487,7 @@ int32_t ism330dlc_tap_src_get(stmdev_ctx_t *ctx, * @param val Change the values of tap_z_en in reg TAP_CFG * */ -int32_t ism330dlc_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_tap_cfg_t tap_cfg; @@ -4499,7 +4511,7 @@ int32_t ism330dlc_tap_detection_on_z_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_tap_cfg_t tap_cfg; @@ -4518,7 +4530,7 @@ int32_t ism330dlc_tap_detection_on_z_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_tap_cfg_t tap_cfg; @@ -4542,7 +4554,7 @@ int32_t ism330dlc_tap_detection_on_y_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_tap_cfg_t tap_cfg; @@ -4561,7 +4573,7 @@ int32_t ism330dlc_tap_detection_on_y_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_tap_cfg_t tap_cfg; @@ -4585,7 +4597,7 @@ int32_t ism330dlc_tap_detection_on_x_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_tap_cfg_t tap_cfg; @@ -4604,7 +4616,7 @@ int32_t ism330dlc_tap_detection_on_x_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -4629,7 +4641,7 @@ int32_t ism330dlc_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dlc_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -4653,7 +4665,7 @@ int32_t ism330dlc_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_int_dur2_t int_dur2; int32_t ret; @@ -4683,7 +4695,7 @@ int32_t ism330dlc_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dlc_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_int_dur2_t int_dur2; int32_t ret; @@ -4707,7 +4719,7 @@ int32_t ism330dlc_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_int_dur2_t int_dur2; int32_t ret; @@ -4737,7 +4749,7 @@ int32_t ism330dlc_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dlc_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_int_dur2_t int_dur2; int32_t ret; @@ -4762,7 +4774,7 @@ int32_t ism330dlc_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_int_dur2_t int_dur2; int32_t ret; @@ -4793,7 +4805,7 @@ int32_t ism330dlc_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dlc_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_int_dur2_t int_dur2; int32_t ret; @@ -4812,7 +4824,7 @@ int32_t ism330dlc_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_tap_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_tap_mode_set(const stmdev_ctx_t *ctx, ism330dlc_single_double_tap_t val) { ism330dlc_wake_up_ths_t wake_up_ths; @@ -4838,7 +4850,7 @@ int32_t ism330dlc_tap_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_tap_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_tap_mode_get(const stmdev_ctx_t *ctx, ism330dlc_single_double_tap_t *val) { ism330dlc_wake_up_ths_t wake_up_ths; @@ -4885,7 +4897,7 @@ int32_t ism330dlc_tap_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_6d_feed_data_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_6d_feed_data_set(const stmdev_ctx_t *ctx, ism330dlc_low_pass_on_6d_t val) { ism330dlc_ctrl8_xl_t ctrl8_xl; @@ -4911,7 +4923,7 @@ int32_t ism330dlc_6d_feed_data_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_6d_feed_data_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_6d_feed_data_get(const stmdev_ctx_t *ctx, ism330dlc_low_pass_on_6d_t *val) { ism330dlc_ctrl8_xl_t ctrl8_xl; @@ -4945,7 +4957,7 @@ int32_t ism330dlc_6d_feed_data_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_6d_threshold_set(const stmdev_ctx_t *ctx, ism330dlc_sixd_ths_t val) { ism330dlc_tap_ths_6d_t tap_ths_6d; @@ -4971,7 +4983,7 @@ int32_t ism330dlc_6d_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_6d_threshold_get(const stmdev_ctx_t *ctx, ism330dlc_sixd_ths_t *val) { ism330dlc_tap_ths_6d_t tap_ths_6d; @@ -5013,7 +5025,7 @@ int32_t ism330dlc_6d_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -5038,7 +5050,7 @@ int32_t ism330dlc_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dlc_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -5070,7 +5082,7 @@ int32_t ism330dlc_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_wake_up_dur_t wake_up_dur; ism330dlc_free_fall_t free_fall; @@ -5109,7 +5121,7 @@ int32_t ism330dlc_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dlc_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_wake_up_dur_t wake_up_dur; ism330dlc_free_fall_t free_fall; @@ -5136,7 +5148,7 @@ int32_t ism330dlc_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_ff_threshold_set(const stmdev_ctx_t *ctx, ism330dlc_ff_ths_t val) { ism330dlc_free_fall_t free_fall; @@ -5162,7 +5174,7 @@ int32_t ism330dlc_ff_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_ff_threshold_get(const stmdev_ctx_t *ctx, ism330dlc_ff_ths_t *val) { ism330dlc_free_fall_t free_fall; @@ -5233,7 +5245,7 @@ int32_t ism330dlc_ff_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t ism330dlc_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val) { ism330dlc_fifo_ctrl1_t fifo_ctrl1; ism330dlc_fifo_ctrl2_t fifo_ctrl2; @@ -5266,7 +5278,7 @@ int32_t ism330dlc_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t ism330dlc_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) { ism330dlc_fifo_ctrl1_t fifo_ctrl1; ism330dlc_fifo_ctrl2_t fifo_ctrl2; @@ -5296,7 +5308,7 @@ int32_t ism330dlc_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_fifo_data_level_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) { ism330dlc_fifo_status1_t fifo_status1; @@ -5324,7 +5336,7 @@ int32_t ism330dlc_fifo_data_level_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dlc_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_fifo_status2_t fifo_status2; int32_t ret; @@ -5344,7 +5356,7 @@ int32_t ism330dlc_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t ism330dlc_fifo_pattern_get(const stmdev_ctx_t *ctx, uint16_t *val) { ism330dlc_fifo_status3_t fifo_status3; ism330dlc_fifo_status4_t fifo_status4; @@ -5371,7 +5383,7 @@ int32_t ism330dlc_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_fifo_temp_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -5396,7 +5408,7 @@ int32_t ism330dlc_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dlc_fifo_temp_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -5416,7 +5428,7 @@ int32_t ism330dlc_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_fifo_write_trigger_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_write_trigger_set(const stmdev_ctx_t *ctx, ism330dlc_trigger_fifo_t val) { ism330dlc_master_config_t master_config; @@ -5443,7 +5455,7 @@ int32_t ism330dlc_fifo_write_trigger_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_xl_batch_set(const stmdev_ctx_t *ctx, ism330dlc_dec_fifo_xl_t val) { ism330dlc_fifo_ctrl3_t fifo_ctrl3; @@ -5470,7 +5482,7 @@ int32_t ism330dlc_fifo_xl_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_xl_batch_get(const stmdev_ctx_t *ctx, ism330dlc_dec_fifo_xl_t *val) { ism330dlc_fifo_ctrl3_t fifo_ctrl3; @@ -5529,7 +5541,7 @@ int32_t ism330dlc_fifo_xl_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_gy_batch_set(const stmdev_ctx_t *ctx, ism330dlc_dec_fifo_gyro_t val) { ism330dlc_fifo_ctrl3_t fifo_ctrl3; @@ -5556,7 +5568,7 @@ int32_t ism330dlc_fifo_gy_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_gy_batch_get(const stmdev_ctx_t *ctx, ism330dlc_dec_fifo_gyro_t *val) { ism330dlc_fifo_ctrl3_t fifo_ctrl3; @@ -5615,7 +5627,7 @@ int32_t ism330dlc_fifo_gy_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_dataset_3_batch_set(const stmdev_ctx_t *ctx, ism330dlc_dec_ds3_fifo_t val) { ism330dlc_fifo_ctrl4_t fifo_ctrl4; @@ -5642,7 +5654,7 @@ int32_t ism330dlc_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_dataset_3_batch_get(const stmdev_ctx_t *ctx, ism330dlc_dec_ds3_fifo_t *val) { ism330dlc_fifo_ctrl4_t fifo_ctrl4; @@ -5701,7 +5713,7 @@ int32_t ism330dlc_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_dataset_4_batch_set(const stmdev_ctx_t *ctx, ism330dlc_dec_ds4_fifo_t val) { ism330dlc_fifo_ctrl4_t fifo_ctrl4; @@ -5728,7 +5740,7 @@ int32_t ism330dlc_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_dataset_4_batch_get(const stmdev_ctx_t *ctx, ism330dlc_dec_ds4_fifo_t *val) { ism330dlc_fifo_ctrl4_t fifo_ctrl4; @@ -5786,7 +5798,7 @@ int32_t ism330dlc_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_xl_gy_8bit_format_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_fifo_ctrl4_t fifo_ctrl4; @@ -5812,7 +5824,7 @@ int32_t ism330dlc_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_xl_gy_8bit_format_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_fifo_ctrl4_t fifo_ctrl4; @@ -5833,7 +5845,7 @@ int32_t ism330dlc_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_fifo_ctrl4_t fifo_ctrl4; int32_t ret; @@ -5859,7 +5871,7 @@ int32_t ism330dlc_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_fifo_ctrl4_t fifo_ctrl4; @@ -5879,7 +5891,7 @@ int32_t ism330dlc_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_mode_set(const stmdev_ctx_t *ctx, ism330dlc_fifo_mode_t val) { ism330dlc_fifo_ctrl5_t fifo_ctrl5; @@ -5905,7 +5917,7 @@ int32_t ism330dlc_fifo_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_mode_get(const stmdev_ctx_t *ctx, ism330dlc_fifo_mode_t *val) { ism330dlc_fifo_ctrl5_t fifo_ctrl5; @@ -5951,7 +5963,7 @@ int32_t ism330dlc_fifo_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_fifo_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_data_rate_set(const stmdev_ctx_t *ctx, ism330dlc_odr_fifo_t val) { ism330dlc_fifo_ctrl5_t fifo_ctrl5; @@ -5977,7 +5989,7 @@ int32_t ism330dlc_fifo_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_fifo_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_data_rate_get(const stmdev_ctx_t *ctx, ism330dlc_odr_fifo_t *val) { ism330dlc_fifo_ctrl5_t fifo_ctrl5; @@ -6060,7 +6072,7 @@ int32_t ism330dlc_fifo_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_den_polarity_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_den_polarity_set(const stmdev_ctx_t *ctx, ism330dlc_den_lh_t val) { ism330dlc_ctrl5_c_t ctrl5_c; @@ -6084,7 +6096,7 @@ int32_t ism330dlc_den_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_den_polarity_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_den_polarity_get(const stmdev_ctx_t *ctx, ism330dlc_den_lh_t *val) { ism330dlc_ctrl5_c_t ctrl5_c; @@ -6117,7 +6129,7 @@ int32_t ism330dlc_den_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_den_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_den_mode_set(const stmdev_ctx_t *ctx, ism330dlc_den_mode_t val) { ism330dlc_ctrl6_c_t ctrl6_c; @@ -6141,7 +6153,7 @@ int32_t ism330dlc_den_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_den_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_den_mode_get(const stmdev_ctx_t *ctx, ism330dlc_den_mode_t *val) { ism330dlc_ctrl6_c_t ctrl6_c; @@ -6183,7 +6195,7 @@ int32_t ism330dlc_den_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_den_enable_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_den_enable_set(const stmdev_ctx_t *ctx, ism330dlc_den_xl_en_t val) { ism330dlc_ctrl4_c_t ctrl4_c; @@ -6224,7 +6236,7 @@ int32_t ism330dlc_den_enable_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_den_enable_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_den_enable_get(const stmdev_ctx_t *ctx, ism330dlc_den_xl_en_t *val) { ism330dlc_ctrl4_c_t ctrl4_c; @@ -6268,7 +6280,7 @@ int32_t ism330dlc_den_enable_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -6293,7 +6305,7 @@ int32_t ism330dlc_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dlc_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -6312,7 +6324,7 @@ int32_t ism330dlc_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -6337,7 +6349,7 @@ int32_t ism330dlc_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dlc_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -6356,7 +6368,7 @@ int32_t ism330dlc_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -6381,7 +6393,7 @@ int32_t ism330dlc_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dlc_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -6413,7 +6425,7 @@ int32_t ism330dlc_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -6438,7 +6450,7 @@ int32_t ism330dlc_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dlc_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -6457,7 +6469,7 @@ int32_t ism330dlc_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_mag_hard_iron_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_master_config_t master_config; ism330dlc_ctrl10_c_t ctrl10_c; @@ -6500,7 +6512,7 @@ int32_t ism330dlc_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dlc_mag_hard_iron_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_master_config_t master_config; int32_t ret; @@ -6520,7 +6532,7 @@ int32_t ism330dlc_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_mag_soft_iron_mat_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -6548,7 +6560,7 @@ int32_t ism330dlc_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_mag_soft_iron_mat_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_mag_soft_iron_mat_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -6576,7 +6588,7 @@ int32_t ism330dlc_mag_soft_iron_mat_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val) +int32_t ism330dlc_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -6610,7 +6622,7 @@ int32_t ism330dlc_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t ism330dlc_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -6657,7 +6669,7 @@ int32_t ism330dlc_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_sync_sens_frame_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_sensor_sync_time_frame_t sensor_sync_time_frame; @@ -6684,7 +6696,7 @@ int32_t ism330dlc_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_sync_sens_frame_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_sensor_sync_time_frame_t sensor_sync_time_frame; @@ -6704,7 +6716,7 @@ int32_t ism330dlc_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_sync_sens_ratio_set(const stmdev_ctx_t *ctx, ism330dlc_rr_t val) { ism330dlc_sensor_sync_res_ratio_t sensor_sync_res_ratio; @@ -6730,7 +6742,7 @@ int32_t ism330dlc_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_sync_sens_ratio_get(const stmdev_ctx_t *ctx, ism330dlc_rr_t *val) { ism330dlc_sensor_sync_res_ratio_t sensor_sync_res_ratio; @@ -6772,7 +6784,7 @@ int32_t ism330dlc_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_master_config_t master_config; int32_t ret; @@ -6797,7 +6809,7 @@ int32_t ism330dlc_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dlc_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_master_config_t master_config; int32_t ret; @@ -6816,7 +6828,7 @@ int32_t ism330dlc_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_master_config_t master_config; int32_t ret; @@ -6841,7 +6853,7 @@ int32_t ism330dlc_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dlc_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_master_config_t master_config; int32_t ret; @@ -6860,7 +6872,7 @@ int32_t ism330dlc_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_pin_mode_set(const stmdev_ctx_t *ctx, ism330dlc_pull_up_en_t val) { ism330dlc_master_config_t master_config; @@ -6886,7 +6898,7 @@ int32_t ism330dlc_sh_pin_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_pin_mode_get(const stmdev_ctx_t *ctx, ism330dlc_pull_up_en_t *val) { ism330dlc_master_config_t master_config; @@ -6920,7 +6932,7 @@ int32_t ism330dlc_sh_pin_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_syncro_mode_set(const stmdev_ctx_t *ctx, ism330dlc_start_config_t val) { ism330dlc_master_config_t master_config; @@ -6946,7 +6958,7 @@ int32_t ism330dlc_sh_syncro_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_syncro_mode_get(const stmdev_ctx_t *ctx, ism330dlc_start_config_t *val) { ism330dlc_master_config_t master_config; @@ -6980,7 +6992,7 @@ int32_t ism330dlc_sh_syncro_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_sh_drdy_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_master_config_t master_config; int32_t ret; @@ -7005,7 +7017,7 @@ int32_t ism330dlc_sh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330dlc_sh_drdy_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_master_config_t master_config; int32_t ret; @@ -7024,7 +7036,7 @@ int32_t ism330dlc_sh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_read_data_raw_get(const stmdev_ctx_t *ctx, ism330dlc_emb_sh_read_t *val) { int32_t ret; @@ -7049,7 +7061,7 @@ int32_t ism330dlc_sh_read_data_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330dlc_sh_cmd_sens_sync_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_master_cmd_code_t master_cmd_code; int32_t ret; @@ -7075,7 +7087,7 @@ int32_t ism330dlc_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_cmd_sens_sync_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_master_cmd_code_t master_cmd_code; @@ -7096,7 +7108,7 @@ int32_t ism330dlc_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_spi_sync_error_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_spi_sync_error_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330dlc_sens_sync_spi_error_code_t sens_sync_spi_error_code; @@ -7123,7 +7135,7 @@ int32_t ism330dlc_sh_spi_sync_error_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_spi_sync_error_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_spi_sync_error_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330dlc_sens_sync_spi_error_code_t sens_sync_spi_error_code; @@ -7143,7 +7155,7 @@ int32_t ism330dlc_sh_spi_sync_error_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_num_of_dev_connected_set(const stmdev_ctx_t *ctx, ism330dlc_aux_sens_on_t val) { ism330dlc_slave0_config_t slave0_config; @@ -7179,7 +7191,7 @@ int32_t ism330dlc_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_num_of_dev_connected_get(const stmdev_ctx_t *ctx, ism330dlc_aux_sens_on_t *val) { ism330dlc_slave0_config_t slave0_config; @@ -7234,7 +7246,7 @@ int32_t ism330dlc_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_cfg_write(const stmdev_ctx_t *ctx, ism330dlc_sh_cfg_write_t *val) { ism330dlc_slv0_add_t slv0_add; @@ -7280,7 +7292,7 @@ int32_t ism330dlc_sh_cfg_write(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_slv0_cfg_read(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, ism330dlc_sh_cfg_read_t *val) { ism330dlc_slave0_config_t slave0_config; @@ -7334,7 +7346,7 @@ int32_t ism330dlc_sh_slv0_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_slv1_cfg_read(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, ism330dlc_sh_cfg_read_t *val) { ism330dlc_slave1_config_t slave1_config; @@ -7388,7 +7400,7 @@ int32_t ism330dlc_sh_slv1_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_slv2_cfg_read(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, ism330dlc_sh_cfg_read_t *val) { ism330dlc_slv2_add_t slv2_add; @@ -7442,7 +7454,7 @@ int32_t ism330dlc_sh_slv2_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_slv3_cfg_read(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, ism330dlc_sh_cfg_read_t *val) { ism330dlc_slave3_config_t slave3_config; @@ -7494,7 +7506,7 @@ int32_t ism330dlc_sh_slv3_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_slave_0_dec_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_slave_0_dec_set(const stmdev_ctx_t *ctx, ism330dlc_slave0_rate_t val) { ism330dlc_slave0_config_t slave0_config; @@ -7531,7 +7543,7 @@ int32_t ism330dlc_sh_slave_0_dec_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_slave_0_dec_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_slave_0_dec_get(const stmdev_ctx_t *ctx, ism330dlc_slave0_rate_t *val) { ism330dlc_slave0_config_t slave0_config; @@ -7586,7 +7598,7 @@ int32_t ism330dlc_sh_slave_0_dec_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_write_mode_set(const stmdev_ctx_t *ctx, ism330dlc_write_once_t val) { ism330dlc_slave1_config_t slave1_config; @@ -7625,7 +7637,7 @@ int32_t ism330dlc_sh_write_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_write_mode_get(const stmdev_ctx_t *ctx, ism330dlc_write_once_t *val) { ism330dlc_slave1_config_t slave1_config; @@ -7670,7 +7682,7 @@ int32_t ism330dlc_sh_write_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_slave_1_dec_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_slave_1_dec_set(const stmdev_ctx_t *ctx, ism330dlc_slave1_rate_t val) { ism330dlc_slave1_config_t slave1_config; @@ -7706,7 +7718,7 @@ int32_t ism330dlc_sh_slave_1_dec_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_slave_1_dec_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_slave_1_dec_get(const stmdev_ctx_t *ctx, ism330dlc_slave1_rate_t *val) { ism330dlc_slave1_config_t slave1_config; @@ -7759,7 +7771,7 @@ int32_t ism330dlc_sh_slave_1_dec_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_slave_2_dec_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_slave_2_dec_set(const stmdev_ctx_t *ctx, ism330dlc_slave2_rate_t val) { ism330dlc_slave2_config_t slave2_config; @@ -7796,7 +7808,7 @@ int32_t ism330dlc_sh_slave_2_dec_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_slave_2_dec_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_slave_2_dec_get(const stmdev_ctx_t *ctx, ism330dlc_slave2_rate_t *val) { ism330dlc_slave2_config_t slave2_config; @@ -7849,7 +7861,7 @@ int32_t ism330dlc_sh_slave_2_dec_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_slave_3_dec_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_slave_3_dec_set(const stmdev_ctx_t *ctx, ism330dlc_slave3_rate_t val) { ism330dlc_slave3_config_t slave3_config; @@ -7886,7 +7898,7 @@ int32_t ism330dlc_sh_slave_3_dec_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330dlc_sh_slave_3_dec_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_slave_3_dec_get(const stmdev_ctx_t *ctx, ism330dlc_slave3_rate_t *val) { ism330dlc_slave3_config_t slave3_config; diff --git a/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.h b/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.h index 2c506a24..d9be4825 100644 --- a/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.h +++ b/sensor/stmemsc/ism330dlc_STdC/driver/ism330dlc_reg.h @@ -441,11 +441,9 @@ typedef struct uint8_t not_used_01 : 1; uint8_t usr_off_w : 1; uint8_t xl_hm_mode : 1; -uint8_t den_mode : - 3; /* trig_en + lvl_en + lvl2_en */ + uint8_t den_mode : 3; /* trig_en + lvl_en + lvl2_en */ #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN -uint8_t den_mode : - 3; /* trig_en + lvl_en + lvl2_en */ + uint8_t den_mode : 3; /* trig_en + lvl_en + lvl2_en */ uint8_t xl_hm_mode : 1; uint8_t usr_off_w : 1; uint8_t not_used_01 : 1; @@ -994,21 +992,18 @@ typedef struct #define ISM330DLC_FIFO_STATUS3 0x3CU typedef struct { -uint8_t fifo_pattern : - 8; /* + FIFO_STATUS4(fifo_pattern) */ + uint8_t fifo_pattern : 8; /* + FIFO_STATUS4(fifo_pattern) */ } ism330dlc_fifo_status3_t; #define ISM330DLC_FIFO_STATUS4 0x3DU typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN -uint8_t fifo_pattern : - 2; /* + FIFO_STATUS3(fifo_pattern) */ + uint8_t fifo_pattern : 2; /* + FIFO_STATUS3(fifo_pattern) */ uint8_t not_used_01 : 6; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN uint8_t not_used_01 : 6; -uint8_t fifo_pattern : - 2; /* + FIFO_STATUS3(fifo_pattern) */ + uint8_t fifo_pattern : 2; /* + FIFO_STATUS3(fifo_pattern) */ #endif /* DRV_BYTE_ORDER */ } ism330dlc_fifo_status4_t; @@ -1702,10 +1697,10 @@ typedef union * them with a custom implementation. */ -int32_t ism330dlc_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t ism330dlc_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t ism330dlc_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t ism330dlc_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -1730,9 +1725,9 @@ typedef enum ISM330DLC_8g = 3, ISM330DLC_XL_FS_ND = 4, /* ERROR CODE */ } ism330dlc_fs_xl_t; -int32_t ism330dlc_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_full_scale_set(const stmdev_ctx_t *ctx, ism330dlc_fs_xl_t val); -int32_t ism330dlc_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_full_scale_get(const stmdev_ctx_t *ctx, ism330dlc_fs_xl_t *val); typedef enum @@ -1750,9 +1745,9 @@ typedef enum ISM330DLC_XL_ODR_6k66Hz = 10, ISM330DLC_XL_ODR_1Hz6 = 11, } ism330dlc_odr_xl_t; -int32_t ism330dlc_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_data_rate_set(const stmdev_ctx_t *ctx, ism330dlc_odr_xl_t val); -int32_t ism330dlc_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_data_rate_get(const stmdev_ctx_t *ctx, ism330dlc_odr_xl_t *val); typedef enum @@ -1763,9 +1758,9 @@ typedef enum ISM330DLC_1000dps = 4, ISM330DLC_2000dps = 6, } ism330dlc_fs_g_t; -int32_t ism330dlc_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_gy_full_scale_set(const stmdev_ctx_t *ctx, ism330dlc_fs_g_t val); -int32_t ism330dlc_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_gy_full_scale_get(const stmdev_ctx_t *ctx, ism330dlc_fs_g_t *val); typedef enum @@ -1782,14 +1777,14 @@ typedef enum ISM330DLC_GY_ODR_3k33Hz = 9, ISM330DLC_GY_ODR_6k66Hz = 10, } ism330dlc_odr_g_t; -int32_t ism330dlc_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_gy_data_rate_set(const stmdev_ctx_t *ctx, ism330dlc_odr_g_t val); -int32_t ism330dlc_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_gy_data_rate_get(const stmdev_ctx_t *ctx, ism330dlc_odr_g_t *val); -int32_t ism330dlc_block_data_update_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_block_data_update_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -1797,9 +1792,9 @@ typedef enum ISM330DLC_LSb_1mg = 0, ISM330DLC_LSb_16mg = 1, } ism330dlc_usr_off_w_t; -int32_t ism330dlc_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_offset_weight_set(const stmdev_ctx_t *ctx, ism330dlc_usr_off_w_t val); -int32_t ism330dlc_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_offset_weight_get(const stmdev_ctx_t *ctx, ism330dlc_usr_off_w_t *val); typedef enum @@ -1807,9 +1802,9 @@ typedef enum ISM330DLC_XL_HIGH_PERFORMANCE = 0, ISM330DLC_XL_NORMAL = 1, } ism330dlc_xl_hm_mode_t; -int32_t ism330dlc_xl_power_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_power_mode_set(const stmdev_ctx_t *ctx, ism330dlc_xl_hm_mode_t val); -int32_t ism330dlc_xl_power_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_power_mode_get(const stmdev_ctx_t *ctx, ism330dlc_xl_hm_mode_t *val); typedef enum @@ -1817,9 +1812,9 @@ typedef enum ISM330DLC_STAT_RND_DISABLE = 0, ISM330DLC_STAT_RND_ENABLE = 1, } ism330dlc_rounding_status_t; -int32_t ism330dlc_rounding_on_status_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_rounding_on_status_set(const stmdev_ctx_t *ctx, ism330dlc_rounding_status_t val); -int32_t ism330dlc_rounding_on_status_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_rounding_on_status_get(const stmdev_ctx_t *ctx, ism330dlc_rounding_status_t *val); typedef enum @@ -1827,9 +1822,9 @@ typedef enum ISM330DLC_GY_HIGH_PERFORMANCE = 0, ISM330DLC_GY_NORMAL = 1, } ism330dlc_g_hm_mode_t; -int32_t ism330dlc_gy_power_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_gy_power_mode_set(const stmdev_ctx_t *ctx, ism330dlc_g_hm_mode_t val); -int32_t ism330dlc_gy_power_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_gy_power_mode_get(const stmdev_ctx_t *ctx, ism330dlc_g_hm_mode_t *val); typedef struct @@ -1841,34 +1836,34 @@ typedef struct ism330dlc_func_src1_t func_src1; ism330dlc_func_src2_t func_src2; } ism330dlc_all_sources_t; -int32_t ism330dlc_all_sources_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_all_sources_get(const stmdev_ctx_t *ctx, ism330dlc_all_sources_t *val); -int32_t ism330dlc_status_reg_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_status_reg_get(const stmdev_ctx_t *ctx, ism330dlc_status_reg_t *val); -int32_t ism330dlc_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dlc_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dlc_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dlc_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ism330dlc_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ism330dlc_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dlc_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t ism330dlc_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t ism330dlc_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dlc_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { ISM330DLC_LSB_6ms4 = 0, ISM330DLC_LSB_25us = 1, } ism330dlc_timer_hr_t; -int32_t ism330dlc_timestamp_res_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_timestamp_res_set(const stmdev_ctx_t *ctx, ism330dlc_timer_hr_t val); -int32_t ism330dlc_timestamp_res_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_timestamp_res_get(const stmdev_ctx_t *ctx, ism330dlc_timer_hr_t *val); typedef enum @@ -1882,24 +1877,24 @@ typedef enum ISM330DLC_ROUND_GY_XL_SH1_TO_SH12 = 6, ISM330DLC_ROUND_GY_XL_SH1_TO_SH6 = 7, } ism330dlc_rounding_t; -int32_t ism330dlc_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_rounding_mode_set(const stmdev_ctx_t *ctx, ism330dlc_rounding_t val); -int32_t ism330dlc_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_rounding_mode_get(const stmdev_ctx_t *ctx, ism330dlc_rounding_t *val); -int32_t ism330dlc_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t ism330dlc_angular_rate_raw_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t ism330dlc_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t ism330dlc_mag_calibrated_raw_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_mag_calibrated_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t ism330dlc_fifo_raw_data_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_raw_data_get(const stmdev_ctx_t *ctx, uint8_t *buffer, uint8_t len); @@ -1908,9 +1903,9 @@ typedef enum ISM330DLC_USER_BANK = 0, ISM330DLC_BANK_A = 1, } ism330dlc_func_cfg_en_t; -int32_t ism330dlc_mem_bank_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_mem_bank_set(const stmdev_ctx_t *ctx, ism330dlc_func_cfg_en_t val); -int32_t ism330dlc_mem_bank_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_mem_bank_get(const stmdev_ctx_t *ctx, ism330dlc_func_cfg_en_t *val); typedef enum @@ -1918,30 +1913,30 @@ typedef enum ISM330DLC_DRDY_LATCHED = 0, ISM330DLC_DRDY_PULSED = 1, } ism330dlc_drdy_pulsed_t; -int32_t ism330dlc_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_data_ready_mode_set(const stmdev_ctx_t *ctx, ism330dlc_drdy_pulsed_t val); -int32_t ism330dlc_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_data_ready_mode_get(const stmdev_ctx_t *ctx, ism330dlc_drdy_pulsed_t *val); -int32_t ism330dlc_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ism330dlc_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dlc_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t ism330dlc_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dlc_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { ISM330DLC_LSB_AT_LOW_ADD = 0, ISM330DLC_MSB_AT_LOW_ADD = 1, } ism330dlc_ble_t; -int32_t ism330dlc_data_format_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_data_format_set(const stmdev_ctx_t *ctx, ism330dlc_ble_t val); -int32_t ism330dlc_data_format_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_data_format_get(const stmdev_ctx_t *ctx, ism330dlc_ble_t *val); -int32_t ism330dlc_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dlc_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dlc_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dlc_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dlc_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dlc_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -1949,9 +1944,9 @@ typedef enum ISM330DLC_XL_ST_POSITIVE = 1, ISM330DLC_XL_ST_NEGATIVE = 2, } ism330dlc_st_xl_t; -int32_t ism330dlc_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_self_test_set(const stmdev_ctx_t *ctx, ism330dlc_st_xl_t val); -int32_t ism330dlc_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_self_test_get(const stmdev_ctx_t *ctx, ism330dlc_st_xl_t *val); typedef enum @@ -1960,14 +1955,14 @@ typedef enum ISM330DLC_GY_ST_POSITIVE = 1, ISM330DLC_GY_ST_NEGATIVE = 3, } ism330dlc_st_g_t; -int32_t ism330dlc_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_gy_self_test_set(const stmdev_ctx_t *ctx, ism330dlc_st_g_t val); -int32_t ism330dlc_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_gy_self_test_get(const stmdev_ctx_t *ctx, ism330dlc_st_g_t *val); -int32_t ism330dlc_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -1975,9 +1970,9 @@ typedef enum ISM330DLC_USE_SLOPE = 0, ISM330DLC_USE_HPF = 1, } ism330dlc_slope_fds_t; -int32_t ism330dlc_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, ism330dlc_slope_fds_t val); -int32_t ism330dlc_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, ism330dlc_slope_fds_t *val); typedef enum @@ -1985,9 +1980,9 @@ typedef enum ISM330DLC_XL_ANA_BW_1k5Hz = 0, ISM330DLC_XL_ANA_BW_400Hz = 1, } ism330dlc_bw0_xl_t; -int32_t ism330dlc_xl_filter_analog_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_filter_analog_set(const stmdev_ctx_t *ctx, ism330dlc_bw0_xl_t val); -int32_t ism330dlc_xl_filter_analog_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_filter_analog_get(const stmdev_ctx_t *ctx, ism330dlc_bw0_xl_t *val); typedef enum @@ -1996,9 +1991,9 @@ typedef enum ISM330DLC_XL_LP1_ODR_DIV_4 = 1, ISM330DLC_XL_LP1_NA = 2, } ism330dlc_lpf1_bw_sel_t; -int32_t ism330dlc_xl_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_lp1_bandwidth_set(const stmdev_ctx_t *ctx, ism330dlc_lpf1_bw_sel_t val); -int32_t ism330dlc_xl_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_lp1_bandwidth_get(const stmdev_ctx_t *ctx, ism330dlc_lpf1_bw_sel_t *val); typedef enum @@ -2013,14 +2008,14 @@ typedef enum ISM330DLC_XL_LOW_NOISE_LP_ODR_DIV_400 = 0x13, ISM330DLC_XL_LP_NA = 0x14 } ism330dlc_input_composite_t; -int32_t ism330dlc_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, ism330dlc_input_composite_t val); -int32_t ism330dlc_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, ism330dlc_input_composite_t *val); -int32_t ism330dlc_xl_reference_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_xl_reference_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2031,9 +2026,9 @@ typedef enum ISM330DLC_XL_HP_ODR_DIV_400 = 0x03, ISM330DLC_XL_HP_NA = 0x04, } ism330dlc_hpcf_xl_t; -int32_t ism330dlc_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_hp_bandwidth_set(const stmdev_ctx_t *ctx, ism330dlc_hpcf_xl_t val); -int32_t ism330dlc_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_hp_bandwidth_get(const stmdev_ctx_t *ctx, ism330dlc_hpcf_xl_t *val); typedef enum @@ -2042,13 +2037,13 @@ typedef enum ISM330DLC_XL_UI_LP1_ODR_DIV_4 = 1, ISM330DLC_XL_UI_LP1_NA = 2, /* ERROR CODE */ } ism330dlc_ui_lpf1_bw_sel_t; -int32_t ism330dlc_xl_ui_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_ui_lp1_bandwidth_set(const stmdev_ctx_t *ctx, ism330dlc_ui_lpf1_bw_sel_t val); -int32_t ism330dlc_xl_ui_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_ui_lp1_bandwidth_get(const stmdev_ctx_t *ctx, ism330dlc_ui_lpf1_bw_sel_t *val); -int32_t ism330dlc_xl_ui_slope_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_xl_ui_slope_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dlc_xl_ui_slope_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dlc_xl_ui_slope_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2057,9 +2052,9 @@ typedef enum ISM330DLC_AUX_LP_STRONG = 0, ISM330DLC_AUX_LP_AGGRESSIVE = 1, } ism330dlc_filter_xl_conf_ois_t; -int32_t ism330dlc_xl_aux_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_aux_lp_bandwidth_set(const stmdev_ctx_t *ctx, ism330dlc_filter_xl_conf_ois_t val); -int32_t ism330dlc_xl_aux_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_xl_aux_lp_bandwidth_get(const stmdev_ctx_t *ctx, ism330dlc_filter_xl_conf_ois_t *val); typedef enum @@ -2081,13 +2076,13 @@ typedef enum ISM330DLC_HP_260mHz_LP1_STRONG = 0xA8, ISM330DLC_HP_1Hz04_LP1_AGGRESSIVE = 0xBB, } ism330dlc_lpf1_sel_g_t; -int32_t ism330dlc_gy_band_pass_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_gy_band_pass_set(const stmdev_ctx_t *ctx, ism330dlc_lpf1_sel_g_t val); -int32_t ism330dlc_gy_band_pass_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_gy_band_pass_get(const stmdev_ctx_t *ctx, ism330dlc_lpf1_sel_g_t *val); -int32_t ism330dlc_gy_ui_high_pass_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_gy_ui_high_pass_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_gy_ui_high_pass_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dlc_gy_ui_high_pass_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2102,21 +2097,21 @@ typedef enum ISM330DLC_HP_260mHz_LP_351Hz = 0xA0, ISM330DLC_HP_1Hz04_LP_937Hz = 0xB3, } ism330dlc_hp_en_ois_t; -int32_t ism330dlc_gy_aux_bandwidth_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_gy_aux_bandwidth_set(const stmdev_ctx_t *ctx, ism330dlc_hp_en_ois_t val); -int32_t ism330dlc_gy_aux_bandwidth_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_gy_aux_bandwidth_get(const stmdev_ctx_t *ctx, ism330dlc_hp_en_ois_t *val); -int32_t ism330dlc_aux_status_reg_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_status_reg_get(const stmdev_ctx_t *ctx, ism330dlc_status_spiaux_t *val); -int32_t ism330dlc_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dlc_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dlc_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2125,14 +2120,14 @@ typedef enum ISM330DLC_AUX_DEN_LEVEL_LATCH = 3, ISM330DLC_AUX_DEN_LEVEL_TRIG = 2, } ism330dlc_lvl_ois_t; -int32_t ism330dlc_aux_den_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_den_mode_set(const stmdev_ctx_t *ctx, ism330dlc_lvl_ois_t val); -int32_t ism330dlc_aux_den_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_den_mode_get(const stmdev_ctx_t *ctx, ism330dlc_lvl_ois_t *val); -int32_t ism330dlc_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2141,9 +2136,9 @@ typedef enum ISM330DLC_MODE_3_GY = 1, ISM330DLC_MODE_4_GY_XL = 3, } ism330dlc_ois_en_spi2_t; -int32_t ism330dlc_aux_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_mode_set(const stmdev_ctx_t *ctx, ism330dlc_ois_en_spi2_t val); -int32_t ism330dlc_aux_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_mode_get(const stmdev_ctx_t *ctx, ism330dlc_ois_en_spi2_t *val); typedef enum @@ -2154,9 +2149,9 @@ typedef enum ISM330DLC_1000dps_AUX = 4, ISM330DLC_2000dps_AUX = 6, } ism330dlc_fs_g_ois_t; -int32_t ism330dlc_aux_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_gy_full_scale_set(const stmdev_ctx_t *ctx, ism330dlc_fs_g_ois_t val); -int32_t ism330dlc_aux_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_gy_full_scale_get(const stmdev_ctx_t *ctx, ism330dlc_fs_g_ois_t *val); typedef enum @@ -2164,9 +2159,9 @@ typedef enum ISM330DLC_AUX_SPI_4_WIRE = 0, ISM330DLC_AUX_SPI_3_WIRE = 1, } ism330dlc_sim_ois_t; -int32_t ism330dlc_aux_spi_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_spi_mode_set(const stmdev_ctx_t *ctx, ism330dlc_sim_ois_t val); -int32_t ism330dlc_aux_spi_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_spi_mode_get(const stmdev_ctx_t *ctx, ism330dlc_sim_ois_t *val); typedef enum @@ -2174,9 +2169,9 @@ typedef enum ISM330DLC_AUX_LSB_AT_LOW_ADD = 0, ISM330DLC_AUX_MSB_AT_LOW_ADD = 1, } ism330dlc_ble_ois_t; -int32_t ism330dlc_aux_data_format_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_data_format_set(const stmdev_ctx_t *ctx, ism330dlc_ble_ois_t val); -int32_t ism330dlc_aux_data_format_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_data_format_get(const stmdev_ctx_t *ctx, ism330dlc_ble_ois_t *val); typedef enum @@ -2184,9 +2179,9 @@ typedef enum ISM330DLC_ENABLE_CLAMP = 0, ISM330DLC_DISABLE_CLAMP = 1, } ism330dlc_st_ois_clampdis_t; -int32_t ism330dlc_aux_gy_clamp_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_gy_clamp_set(const stmdev_ctx_t *ctx, ism330dlc_st_ois_clampdis_t val); -int32_t ism330dlc_aux_gy_clamp_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_gy_clamp_get(const stmdev_ctx_t *ctx, ism330dlc_st_ois_clampdis_t *val); typedef enum @@ -2195,9 +2190,9 @@ typedef enum ISM330DLC_AUX_GY_POS = 1, ISM330DLC_AUX_GY_NEG = 3, } ism330dlc_st_ois_t; -int32_t ism330dlc_aux_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_gy_self_test_set(const stmdev_ctx_t *ctx, ism330dlc_st_ois_t val); -int32_t ism330dlc_aux_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_gy_self_test_get(const stmdev_ctx_t *ctx, ism330dlc_st_ois_t *val); typedef enum @@ -2207,9 +2202,9 @@ typedef enum ISM330DLC_AUX_4g = 2, ISM330DLC_AUX_8g = 3, } ism330dlc_fs_xl_ois_t; -int32_t ism330dlc_aux_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_xl_full_scale_set(const stmdev_ctx_t *ctx, ism330dlc_fs_xl_ois_t val); -int32_t ism330dlc_aux_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_xl_full_scale_get(const stmdev_ctx_t *ctx, ism330dlc_fs_xl_ois_t *val); typedef enum @@ -2217,9 +2212,9 @@ typedef enum ISM330DLC_AUX_DEN_ACTIVE_LOW = 0, ISM330DLC_AUX_DEN_ACTIVE_HIGH = 1, } ism330dlc_den_lh_ois_t; -int32_t ism330dlc_aux_den_polarity_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_den_polarity_set(const stmdev_ctx_t *ctx, ism330dlc_den_lh_ois_t val); -int32_t ism330dlc_aux_den_polarity_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_aux_den_polarity_get(const stmdev_ctx_t *ctx, ism330dlc_den_lh_ois_t *val); typedef enum @@ -2227,9 +2222,9 @@ typedef enum ISM330DLC_SPI_4_WIRE = 0, ISM330DLC_SPI_3_WIRE = 1, } ism330dlc_sim_t; -int32_t ism330dlc_spi_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_spi_mode_set(const stmdev_ctx_t *ctx, ism330dlc_sim_t val); -int32_t ism330dlc_spi_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_spi_mode_get(const stmdev_ctx_t *ctx, ism330dlc_sim_t *val); typedef enum @@ -2237,9 +2232,9 @@ typedef enum ISM330DLC_I2C_ENABLE = 0, ISM330DLC_I2C_DISABLE = 1, } ism330dlc_i2c_disable_t; -int32_t ism330dlc_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_i2c_interface_set(const stmdev_ctx_t *ctx, ism330dlc_i2c_disable_t val); -int32_t ism330dlc_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_i2c_interface_get(const stmdev_ctx_t *ctx, ism330dlc_i2c_disable_t *val); typedef struct @@ -2260,9 +2255,9 @@ typedef struct uint8_t den_drdy_int1 : 1; uint8_t drdy_on_int1 : 1; } ism330dlc_int1_route_t; -int32_t ism330dlc_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_pin_int1_route_set(const stmdev_ctx_t *ctx, ism330dlc_int1_route_t val); -int32_t ism330dlc_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_pin_int1_route_get(const stmdev_ctx_t *ctx, ism330dlc_int1_route_t *val); typedef struct @@ -2282,9 +2277,9 @@ typedef struct uint8_t int2_single_tap : 1; uint8_t int2_inact_state : 1; } ism330dlc_int2_route_t; -int32_t ism330dlc_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_pin_int2_route_set(const stmdev_ctx_t *ctx, ism330dlc_int2_route_t val); -int32_t ism330dlc_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_pin_int2_route_get(const stmdev_ctx_t *ctx, ism330dlc_int2_route_t *val); typedef enum @@ -2292,9 +2287,9 @@ typedef enum ISM330DLC_PUSH_PULL = 0, ISM330DLC_OPEN_DRAIN = 1, } ism330dlc_pp_od_t; -int32_t ism330dlc_pin_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_pin_mode_set(const stmdev_ctx_t *ctx, ism330dlc_pp_od_t val); -int32_t ism330dlc_pin_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_pin_mode_get(const stmdev_ctx_t *ctx, ism330dlc_pp_od_t *val); typedef enum @@ -2302,32 +2297,32 @@ typedef enum ISM330DLC_ACTIVE_HIGH = 0, ISM330DLC_ACTIVE_LOW = 1, } ism330dlc_h_lactive_t; -int32_t ism330dlc_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_pin_polarity_set(const stmdev_ctx_t *ctx, ism330dlc_h_lactive_t val); -int32_t ism330dlc_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_pin_polarity_get(const stmdev_ctx_t *ctx, ism330dlc_h_lactive_t *val); -int32_t ism330dlc_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dlc_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dlc_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { ISM330DLC_INT_PULSED = 0, ISM330DLC_INT_LATCHED = 1, } ism330dlc_lir_t; -int32_t ism330dlc_int_notification_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_int_notification_set(const stmdev_ctx_t *ctx, ism330dlc_lir_t val); -int32_t ism330dlc_int_notification_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_int_notification_get(const stmdev_ctx_t *ctx, ism330dlc_lir_t *val); -int32_t ism330dlc_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dlc_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dlc_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dlc_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dlc_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dlc_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dlc_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dlc_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dlc_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2336,53 +2331,53 @@ typedef enum ISM330DLC_XL_12Hz5_GY_SLEEP = 2, ISM330DLC_XL_12Hz5_GY_PD = 3, } ism330dlc_inact_en_t; -int32_t ism330dlc_act_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_act_mode_set(const stmdev_ctx_t *ctx, ism330dlc_inact_en_t val); -int32_t ism330dlc_act_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_act_mode_get(const stmdev_ctx_t *ctx, ism330dlc_inact_en_t *val); -int32_t ism330dlc_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dlc_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dlc_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dlc_tap_src_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_tap_src_get(const stmdev_ctx_t *ctx, ism330dlc_tap_src_t *val); -int32_t ism330dlc_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dlc_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dlc_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dlc_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_tap_threshold_x_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dlc_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dlc_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dlc_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dlc_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dlc_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dlc_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dlc_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dlc_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dlc_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dlc_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { ISM330DLC_ONLY_SINGLE = 0, ISM330DLC_BOTH_SINGLE_DOUBLE = 1, } ism330dlc_single_double_tap_t; -int32_t ism330dlc_tap_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_tap_mode_set(const stmdev_ctx_t *ctx, ism330dlc_single_double_tap_t val); -int32_t ism330dlc_tap_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_tap_mode_get(const stmdev_ctx_t *ctx, ism330dlc_single_double_tap_t *val); typedef enum @@ -2390,9 +2385,9 @@ typedef enum ISM330DLC_ODR_DIV_2_FEED = 0, ISM330DLC_LPF2_FEED = 1, } ism330dlc_low_pass_on_6d_t; -int32_t ism330dlc_6d_feed_data_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_6d_feed_data_set(const stmdev_ctx_t *ctx, ism330dlc_low_pass_on_6d_t val); -int32_t ism330dlc_6d_feed_data_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_6d_feed_data_get(const stmdev_ctx_t *ctx, ism330dlc_low_pass_on_6d_t *val); typedef enum @@ -2402,16 +2397,16 @@ typedef enum ISM330DLC_DEG_60 = 2, ISM330DLC_DEG_50 = 3, } ism330dlc_sixd_ths_t; -int32_t ism330dlc_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_6d_threshold_set(const stmdev_ctx_t *ctx, ism330dlc_sixd_ths_t val); -int32_t ism330dlc_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_6d_threshold_get(const stmdev_ctx_t *ctx, ism330dlc_sixd_ths_t *val); -int32_t ism330dlc_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dlc_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dlc_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dlc_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dlc_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dlc_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2424,24 +2419,24 @@ typedef enum ISM330DLC_FF_TSH_469mg = 6, ISM330DLC_FF_TSH_500mg = 7, } ism330dlc_ff_ths_t; -int32_t ism330dlc_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_ff_threshold_set(const stmdev_ctx_t *ctx, ism330dlc_ff_ths_t val); -int32_t ism330dlc_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_ff_threshold_get(const stmdev_ctx_t *ctx, ism330dlc_ff_ths_t *val); -int32_t ism330dlc_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t ism330dlc_fifo_watermark_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t ism330dlc_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t ism330dlc_fifo_data_level_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t ism330dlc_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dlc_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dlc_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t ism330dlc_fifo_pattern_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t ism330dlc_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_temp_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dlc_fifo_temp_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2449,9 +2444,9 @@ typedef enum ISM330DLC_TRG_XL_GY_DRDY = 0, ISM330DLC_TRG_SH_DRDY = 1, } ism330dlc_trigger_fifo_t; -int32_t ism330dlc_fifo_write_trigger_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_write_trigger_set(const stmdev_ctx_t *ctx, ism330dlc_trigger_fifo_t val); -int32_t ism330dlc_fifo_write_trigger_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_write_trigger_get(const stmdev_ctx_t *ctx, ism330dlc_trigger_fifo_t *val); typedef enum @@ -2465,9 +2460,9 @@ typedef enum ISM330DLC_FIFO_XL_DEC_16 = 6, ISM330DLC_FIFO_XL_DEC_32 = 7, } ism330dlc_dec_fifo_xl_t; -int32_t ism330dlc_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_xl_batch_set(const stmdev_ctx_t *ctx, ism330dlc_dec_fifo_xl_t val); -int32_t ism330dlc_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_xl_batch_get(const stmdev_ctx_t *ctx, ism330dlc_dec_fifo_xl_t *val); typedef enum @@ -2481,9 +2476,9 @@ typedef enum ISM330DLC_FIFO_GY_DEC_16 = 6, ISM330DLC_FIFO_GY_DEC_32 = 7, } ism330dlc_dec_fifo_gyro_t; -int32_t ism330dlc_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_gy_batch_set(const stmdev_ctx_t *ctx, ism330dlc_dec_fifo_gyro_t val); -int32_t ism330dlc_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_gy_batch_get(const stmdev_ctx_t *ctx, ism330dlc_dec_fifo_gyro_t *val); typedef enum @@ -2497,9 +2492,9 @@ typedef enum ISM330DLC_FIFO_DS3_DEC_16 = 6, ISM330DLC_FIFO_DS3_DEC_32 = 7, } ism330dlc_dec_ds3_fifo_t; -int32_t ism330dlc_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_dataset_3_batch_set(const stmdev_ctx_t *ctx, ism330dlc_dec_ds3_fifo_t val); -int32_t ism330dlc_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_dataset_3_batch_get(const stmdev_ctx_t *ctx, ism330dlc_dec_ds3_fifo_t *val); typedef enum @@ -2513,19 +2508,19 @@ typedef enum ISM330DLC_FIFO_DS4_DEC_16 = 6, ISM330DLC_FIFO_DS4_DEC_32 = 7, } ism330dlc_dec_ds4_fifo_t; -int32_t ism330dlc_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_dataset_4_batch_set(const stmdev_ctx_t *ctx, ism330dlc_dec_ds4_fifo_t val); -int32_t ism330dlc_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_dataset_4_batch_get(const stmdev_ctx_t *ctx, ism330dlc_dec_ds4_fifo_t *val); -int32_t ism330dlc_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_xl_gy_8bit_format_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_xl_gy_8bit_format_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dlc_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2536,9 +2531,9 @@ typedef enum ISM330DLC_BYPASS_TO_STREAM_MODE = 4, ISM330DLC_STREAM_MODE = 6, } ism330dlc_fifo_mode_t; -int32_t ism330dlc_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_mode_set(const stmdev_ctx_t *ctx, ism330dlc_fifo_mode_t val); -int32_t ism330dlc_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_mode_get(const stmdev_ctx_t *ctx, ism330dlc_fifo_mode_t *val); typedef enum @@ -2555,9 +2550,9 @@ typedef enum ISM330DLC_FIFO_3k33Hz = 9, ISM330DLC_FIFO_6k66Hz = 10, } ism330dlc_odr_fifo_t; -int32_t ism330dlc_fifo_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_data_rate_set(const stmdev_ctx_t *ctx, ism330dlc_odr_fifo_t val); -int32_t ism330dlc_fifo_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_fifo_data_rate_get(const stmdev_ctx_t *ctx, ism330dlc_odr_fifo_t *val); typedef enum @@ -2565,9 +2560,9 @@ typedef enum ISM330DLC_DEN_ACT_LOW = 0, ISM330DLC_DEN_ACT_HIGH = 1, } ism330dlc_den_lh_t; -int32_t ism330dlc_den_polarity_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_den_polarity_set(const stmdev_ctx_t *ctx, ism330dlc_den_lh_t val); -int32_t ism330dlc_den_polarity_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_den_polarity_get(const stmdev_ctx_t *ctx, ism330dlc_den_lh_t *val); typedef enum @@ -2578,9 +2573,9 @@ typedef enum ISM330DLC_LEVEL_TRIGGER = 2, ISM330DLC_EDGE_TRIGGER = 4, } ism330dlc_den_mode_t; -int32_t ism330dlc_den_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_den_mode_set(const stmdev_ctx_t *ctx, ism330dlc_den_mode_t val); -int32_t ism330dlc_den_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_den_mode_get(const stmdev_ctx_t *ctx, ism330dlc_den_mode_t *val); typedef enum @@ -2589,40 +2584,40 @@ typedef enum ISM330DLC_STAMP_IN_XL_DATA = 1, ISM330DLC_STAMP_IN_GY_XL_DATA = 2, } ism330dlc_den_xl_en_t; -int32_t ism330dlc_den_enable_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_den_enable_set(const stmdev_ctx_t *ctx, ism330dlc_den_xl_en_t val); -int32_t ism330dlc_den_enable_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_den_enable_get(const stmdev_ctx_t *ctx, ism330dlc_den_xl_en_t *val); -int32_t ism330dlc_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_den_mark_axis_z_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dlc_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dlc_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_den_mark_axis_y_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dlc_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dlc_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_den_mark_axis_x_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dlc_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dlc_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dlc_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dlc_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dlc_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dlc_mag_hard_iron_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dlc_mag_hard_iron_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dlc_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_mag_soft_iron_mat_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ism330dlc_mag_soft_iron_mat_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_mag_soft_iron_mat_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t ism330dlc_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val); -int32_t ism330dlc_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t ism330dlc_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val); +int32_t ism330dlc_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t ism330dlc_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_sync_sens_frame_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_sync_sens_frame_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2632,16 +2627,16 @@ typedef enum ISM330DLC_RES_RATIO_2_13 = 2, ISM330DLC_RES_RATIO_2_14 = 3, } ism330dlc_rr_t; -int32_t ism330dlc_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_sync_sens_ratio_set(const stmdev_ctx_t *ctx, ism330dlc_rr_t val); -int32_t ism330dlc_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_sync_sens_ratio_get(const stmdev_ctx_t *ctx, ism330dlc_rr_t *val); -int32_t ism330dlc_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330dlc_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dlc_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dlc_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_sh_pass_through_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dlc_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2649,9 +2644,9 @@ typedef enum ISM330DLC_EXT_PULL_UP = 0, ISM330DLC_INTERNAL_PULL_UP = 1, } ism330dlc_pull_up_en_t; -int32_t ism330dlc_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_pin_mode_set(const stmdev_ctx_t *ctx, ism330dlc_pull_up_en_t val); -int32_t ism330dlc_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_pin_mode_get(const stmdev_ctx_t *ctx, ism330dlc_pull_up_en_t *val); typedef enum @@ -2659,13 +2654,13 @@ typedef enum ISM330DLC_XL_GY_DRDY = 1, ISM330DLC_EXT_ON_INT2_PIN = 0, } ism330dlc_start_config_t; -int32_t ism330dlc_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_syncro_mode_set(const stmdev_ctx_t *ctx, ism330dlc_start_config_t val); -int32_t ism330dlc_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_syncro_mode_get(const stmdev_ctx_t *ctx, ism330dlc_start_config_t *val); -int32_t ism330dlc_sh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_sh_drdy_on_int1_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_drdy_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330dlc_sh_drdy_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct @@ -2689,17 +2684,17 @@ typedef struct ism330dlc_sensorhub17_reg_t sh_byte_17; ism330dlc_sensorhub18_reg_t sh_byte_18; } ism330dlc_emb_sh_read_t; -int32_t ism330dlc_sh_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_read_data_raw_get(const stmdev_ctx_t *ctx, ism330dlc_emb_sh_read_t *val); -int32_t ism330dlc_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_cmd_sens_sync_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_cmd_sens_sync_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330dlc_sh_spi_sync_error_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_spi_sync_error_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330dlc_sh_spi_sync_error_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_spi_sync_error_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2707,9 +2702,9 @@ typedef enum ISM330DLC_NORMAL_MODE_READ = 0, ISM330DLC_SRC_MODE_READ = 1, } ism330dlc_src_mode_t; -int32_t ism330dlc_sh_cfg_slave_0_rd_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_cfg_slave_0_rd_mode_set(const stmdev_ctx_t *ctx, ism330dlc_src_mode_t val); -int32_t ism330dlc_sh_cfg_slave_0_rd_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_cfg_slave_0_rd_mode_get(const stmdev_ctx_t *ctx, ism330dlc_src_mode_t *val); typedef enum @@ -2719,9 +2714,9 @@ typedef enum ISM330DLC_SLV_0_1_2 = 2, ISM330DLC_SLV_0_1_2_3 = 3, } ism330dlc_aux_sens_on_t; -int32_t ism330dlc_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_num_of_dev_connected_set(const stmdev_ctx_t *ctx, ism330dlc_aux_sens_on_t val); -int32_t ism330dlc_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_num_of_dev_connected_get(const stmdev_ctx_t *ctx, ism330dlc_aux_sens_on_t *val); typedef struct @@ -2730,7 +2725,7 @@ typedef struct uint8_t slv0_subadd; uint8_t slv0_data; } ism330dlc_sh_cfg_write_t; -int32_t ism330dlc_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_cfg_write(const stmdev_ctx_t *ctx, ism330dlc_sh_cfg_write_t *val); typedef struct @@ -2739,13 +2734,13 @@ typedef struct uint8_t slv_subadd; uint8_t slv_len; } ism330dlc_sh_cfg_read_t; -int32_t ism330dlc_sh_slv0_cfg_read(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, ism330dlc_sh_cfg_read_t *val); -int32_t ism330dlc_sh_slv1_cfg_read(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, ism330dlc_sh_cfg_read_t *val); -int32_t ism330dlc_sh_slv2_cfg_read(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, ism330dlc_sh_cfg_read_t *val); -int32_t ism330dlc_sh_slv3_cfg_read(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, ism330dlc_sh_cfg_read_t *val); typedef enum @@ -2755,9 +2750,9 @@ typedef enum ISM330DLC_SL0_DEC_4 = 2, ISM330DLC_SL0_DEC_8 = 3, } ism330dlc_slave0_rate_t; -int32_t ism330dlc_sh_slave_0_dec_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_slave_0_dec_set(const stmdev_ctx_t *ctx, ism330dlc_slave0_rate_t val); -int32_t ism330dlc_sh_slave_0_dec_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_slave_0_dec_get(const stmdev_ctx_t *ctx, ism330dlc_slave0_rate_t *val); typedef enum @@ -2765,9 +2760,9 @@ typedef enum ISM330DLC_EACH_SH_CYCLE = 0, ISM330DLC_ONLY_FIRST_CYCLE = 1, } ism330dlc_write_once_t; -int32_t ism330dlc_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_write_mode_set(const stmdev_ctx_t *ctx, ism330dlc_write_once_t val); -int32_t ism330dlc_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_write_mode_get(const stmdev_ctx_t *ctx, ism330dlc_write_once_t *val); typedef enum @@ -2777,9 +2772,9 @@ typedef enum ISM330DLC_SL1_DEC_4 = 2, ISM330DLC_SL1_DEC_8 = 3, } ism330dlc_slave1_rate_t; -int32_t ism330dlc_sh_slave_1_dec_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_slave_1_dec_set(const stmdev_ctx_t *ctx, ism330dlc_slave1_rate_t val); -int32_t ism330dlc_sh_slave_1_dec_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_slave_1_dec_get(const stmdev_ctx_t *ctx, ism330dlc_slave1_rate_t *val); typedef enum @@ -2789,9 +2784,9 @@ typedef enum ISM330DLC_SL2_DEC_4 = 2, ISM330DLC_SL2_DEC_8 = 3, } ism330dlc_slave2_rate_t; -int32_t ism330dlc_sh_slave_2_dec_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_slave_2_dec_set(const stmdev_ctx_t *ctx, ism330dlc_slave2_rate_t val); -int32_t ism330dlc_sh_slave_2_dec_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_slave_2_dec_get(const stmdev_ctx_t *ctx, ism330dlc_slave2_rate_t *val); typedef enum @@ -2801,9 +2796,9 @@ typedef enum ISM330DLC_SL3_DEC_4 = 2, ISM330DLC_SL3_DEC_8 = 3, } ism330dlc_slave3_rate_t; -int32_t ism330dlc_sh_slave_3_dec_set(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_slave_3_dec_set(const stmdev_ctx_t *ctx, ism330dlc_slave3_rate_t val); -int32_t ism330dlc_sh_slave_3_dec_get(stmdev_ctx_t *ctx, +int32_t ism330dlc_sh_slave_3_dec_get(const stmdev_ctx_t *ctx, ism330dlc_slave3_rate_t *val); /** diff --git a/sensor/stmemsc/ism330is_STdC/driver/ism330is_reg.c b/sensor/stmemsc/ism330is_STdC/driver/ism330is_reg.c index cc5b7b20..7e9e1372 100644 --- a/sensor/stmemsc/ism330is_STdC/driver/ism330is_reg.c +++ b/sensor/stmemsc/ism330is_STdC/driver/ism330is_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak ism330is_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak ism330is_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak ism330is_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak ism330is_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak ism330is_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -157,7 +167,7 @@ float_t ism330is_from_lsb_to_celsius(int16_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330is_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330is_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330is_internal_freq_fine_t internal_freq_fine; int32_t ret; @@ -185,7 +195,7 @@ int32_t ism330is_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330is_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330is_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330is_internal_freq_fine_t internal_freq_fine; int32_t ret; @@ -205,7 +215,7 @@ int32_t ism330is_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_mem_bank_set(stmdev_ctx_t *ctx, ism330is_mem_bank_t val) +int32_t ism330is_mem_bank_set(const stmdev_ctx_t *ctx, ism330is_mem_bank_t val) { ism330is_func_cfg_access_t func_cfg_access = {0x0}; int32_t ret; @@ -226,7 +236,7 @@ int32_t ism330is_mem_bank_set(stmdev_ctx_t *ctx, ism330is_mem_bank_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_mem_bank_get(stmdev_ctx_t *ctx, ism330is_mem_bank_t *val) +int32_t ism330is_mem_bank_get(const stmdev_ctx_t *ctx, ism330is_mem_bank_t *val) { ism330is_func_cfg_access_t func_cfg_access; int32_t ret; @@ -257,7 +267,7 @@ int32_t ism330is_mem_bank_get(stmdev_ctx_t *ctx, ism330is_mem_bank_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t ism330is_data_ready_mode_set(const stmdev_ctx_t *ctx, ism330is_data_ready_mode_t val) { ism330is_drdy_pulsed_reg_t drdy_pulsed_reg; @@ -282,7 +292,7 @@ int32_t ism330is_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t ism330is_data_ready_mode_get(const stmdev_ctx_t *ctx, ism330is_data_ready_mode_t *val) { ism330is_drdy_pulsed_reg_t drdy_pulsed_reg; @@ -315,7 +325,7 @@ int32_t ism330is_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_device_id_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330is_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -331,7 +341,7 @@ int32_t ism330is_device_id_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330is_software_reset(stmdev_ctx_t *ctx) +int32_t ism330is_software_reset(const stmdev_ctx_t *ctx) { ism330is_ctrl3_c_t ctrl3_c; int32_t ret; @@ -346,7 +356,8 @@ int32_t ism330is_software_reset(stmdev_ctx_t *ctx) ctrl3_c.sw_reset = PROPERTY_ENABLE; ret += ism330is_write_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - do { + do + { ret += ism330is_read_reg(ctx, ISM330IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); } while (ret == 0 && ctrl3_c.sw_reset == PROPERTY_ENABLE); } @@ -362,7 +373,7 @@ int32_t ism330is_software_reset(stmdev_ctx_t *ctx) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330is_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330is_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330is_ctrl3_c_t ctrl3_c; int32_t ret; @@ -386,7 +397,7 @@ int32_t ism330is_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330is_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330is_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330is_ctrl3_c_t ctrl3_c; int32_t ret; @@ -405,7 +416,7 @@ int32_t ism330is_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_xl_hm_mode_set(stmdev_ctx_t *ctx, ism330is_hm_mode_t val) +int32_t ism330is_xl_hm_mode_set(const stmdev_ctx_t *ctx, ism330is_hm_mode_t val) { ism330is_ctrl6_c_t ctrl6_c; int32_t ret; @@ -429,7 +440,7 @@ int32_t ism330is_xl_hm_mode_set(stmdev_ctx_t *ctx, ism330is_hm_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_xl_hm_mode_get(stmdev_ctx_t *ctx, ism330is_hm_mode_t *val) +int32_t ism330is_xl_hm_mode_get(const stmdev_ctx_t *ctx, ism330is_hm_mode_t *val) { ism330is_ctrl6_c_t ctrl6_c; int32_t ret; @@ -461,7 +472,7 @@ int32_t ism330is_xl_hm_mode_get(stmdev_ctx_t *ctx, ism330is_hm_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t ism330is_xl_full_scale_set(const stmdev_ctx_t *ctx, ism330is_xl_full_scale_t val) { ism330is_ctrl1_xl_t ctrl1_xl; @@ -486,7 +497,7 @@ int32_t ism330is_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t ism330is_xl_full_scale_get(const stmdev_ctx_t *ctx, ism330is_xl_full_scale_t *val) { ism330is_ctrl1_xl_t ctrl1_xl; @@ -527,7 +538,7 @@ int32_t ism330is_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism330is_xl_data_rate_set(const stmdev_ctx_t *ctx, ism330is_xl_data_rate_t val) { ism330is_ctrl1_xl_t ctrl1_xl; @@ -561,7 +572,7 @@ int32_t ism330is_xl_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism330is_xl_data_rate_get(const stmdev_ctx_t *ctx, ism330is_xl_data_rate_t *val) { ism330is_ctrl1_xl_t ctrl1_xl; @@ -677,7 +688,7 @@ int32_t ism330is_xl_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_gy_hm_mode_set(stmdev_ctx_t *ctx, ism330is_hm_mode_t val) +int32_t ism330is_gy_hm_mode_set(const stmdev_ctx_t *ctx, ism330is_hm_mode_t val) { ism330is_ctrl7_g_t ctrl7_g; int32_t ret; @@ -701,7 +712,7 @@ int32_t ism330is_gy_hm_mode_set(stmdev_ctx_t *ctx, ism330is_hm_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_gy_hm_mode_get(stmdev_ctx_t *ctx, ism330is_hm_mode_t *val) +int32_t ism330is_gy_hm_mode_get(const stmdev_ctx_t *ctx, ism330is_hm_mode_t *val) { ism330is_ctrl7_g_t ctrl7_g; int32_t ret; @@ -733,7 +744,7 @@ int32_t ism330is_gy_hm_mode_get(stmdev_ctx_t *ctx, ism330is_hm_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t ism330is_gy_full_scale_set(const stmdev_ctx_t *ctx, ism330is_gy_full_scale_t val) { ism330is_ctrl2_g_t ctrl2_g; @@ -759,7 +770,7 @@ int32_t ism330is_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t ism330is_gy_full_scale_get(const stmdev_ctx_t *ctx, ism330is_gy_full_scale_t *val) { ism330is_ctrl2_g_t ctrl2_g; @@ -804,7 +815,7 @@ int32_t ism330is_gy_full_scale_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism330is_gy_data_rate_set(const stmdev_ctx_t *ctx, ism330is_gy_data_rate_t val) { ism330is_ctrl2_g_t ctrl2_g; @@ -838,7 +849,7 @@ int32_t ism330is_gy_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism330is_gy_data_rate_get(const stmdev_ctx_t *ctx, ism330is_gy_data_rate_t *val) { ism330is_ctrl2_g_t ctrl2_g; @@ -950,7 +961,7 @@ int32_t ism330is_gy_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330is_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330is_ctrl3_c_t ctrl3_c; int32_t ret; @@ -974,7 +985,7 @@ int32_t ism330is_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330is_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330is_ctrl3_c_t ctrl3_c; int32_t ret; @@ -994,7 +1005,7 @@ int32_t ism330is_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330is_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330is_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1018,7 +1029,7 @@ int32_t ism330is_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330is_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330is_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1038,7 +1049,7 @@ int32_t ism330is_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_sleep_set(stmdev_ctx_t *ctx, ism330is_sleep_t val) +int32_t ism330is_sleep_set(const stmdev_ctx_t *ctx, ism330is_sleep_t val) { ism330is_ctrl4_c_t ctrl4_c; int32_t ret; @@ -1062,7 +1073,7 @@ int32_t ism330is_sleep_set(stmdev_ctx_t *ctx, ism330is_sleep_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_sleep_get(stmdev_ctx_t *ctx, ism330is_sleep_t *val) +int32_t ism330is_sleep_get(const stmdev_ctx_t *ctx, ism330is_sleep_t *val) { ism330is_ctrl4_c_t ctrl4_c; int32_t ret; @@ -1094,7 +1105,7 @@ int32_t ism330is_sleep_get(stmdev_ctx_t *ctx, ism330is_sleep_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t ism330is_xl_self_test_set(const stmdev_ctx_t *ctx, ism330is_xl_self_test_t val) { ism330is_ctrl5_c_t ctrl5_c; @@ -1119,7 +1130,7 @@ int32_t ism330is_xl_self_test_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t ism330is_xl_self_test_get(const stmdev_ctx_t *ctx, ism330is_xl_self_test_t *val) { ism330is_ctrl5_c_t ctrl5_c; @@ -1156,7 +1167,7 @@ int32_t ism330is_xl_self_test_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t ism330is_gy_self_test_set(const stmdev_ctx_t *ctx, ism330is_gy_self_test_t val) { ism330is_ctrl5_c_t ctrl5_c; @@ -1181,7 +1192,7 @@ int32_t ism330is_gy_self_test_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t ism330is_gy_self_test_get(const stmdev_ctx_t *ctx, ism330is_gy_self_test_t *val) { ism330is_ctrl5_c_t ctrl5_c; @@ -1224,7 +1235,7 @@ int32_t ism330is_gy_self_test_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330is_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330is_pin_ctrl_t pin_ctrl; int32_t ret; @@ -1248,7 +1259,7 @@ int32_t ism330is_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330is_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330is_pin_ctrl_t pin_ctrl; int32_t ret; @@ -1268,7 +1279,7 @@ int32_t ism330is_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_spi_mode_set(stmdev_ctx_t *ctx, ism330is_spi_mode_t val) +int32_t ism330is_spi_mode_set(const stmdev_ctx_t *ctx, ism330is_spi_mode_t val) { ism330is_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1292,7 +1303,7 @@ int32_t ism330is_spi_mode_set(stmdev_ctx_t *ctx, ism330is_spi_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_spi_mode_get(stmdev_ctx_t *ctx, ism330is_spi_mode_t *val) +int32_t ism330is_spi_mode_get(const stmdev_ctx_t *ctx, ism330is_spi_mode_t *val) { ism330is_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1324,7 +1335,7 @@ int32_t ism330is_spi_mode_get(stmdev_ctx_t *ctx, ism330is_spi_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ui_i2c_mode_set(stmdev_ctx_t *ctx, ism330is_ui_i2c_mode_t val) +int32_t ism330is_ui_i2c_mode_set(const stmdev_ctx_t *ctx, ism330is_ui_i2c_mode_t val) { ism330is_ctrl4_c_t ctrl4_c; int32_t ret; @@ -1348,7 +1359,7 @@ int32_t ism330is_ui_i2c_mode_set(stmdev_ctx_t *ctx, ism330is_ui_i2c_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ui_i2c_mode_get(stmdev_ctx_t *ctx, ism330is_ui_i2c_mode_t *val) +int32_t ism330is_ui_i2c_mode_get(const stmdev_ctx_t *ctx, ism330is_ui_i2c_mode_t *val) { ism330is_ctrl4_c_t ctrl4_c; int32_t ret; @@ -1391,7 +1402,7 @@ int32_t ism330is_ui_i2c_mode_get(stmdev_ctx_t *ctx, ism330is_ui_i2c_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330is_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330is_ctrl10_c_t ctrl10_c; int32_t ret; @@ -1415,7 +1426,7 @@ int32_t ism330is_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330is_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330is_ctrl10_c_t ctrl10_c; int32_t ret; @@ -1435,7 +1446,7 @@ int32_t ism330is_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t ism330is_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; @@ -1463,7 +1474,7 @@ int32_t ism330is_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_all_sources_get(stmdev_ctx_t *ctx, ism330is_all_sources_t *val) +int32_t ism330is_all_sources_get(const stmdev_ctx_t *ctx, ism330is_all_sources_t *val) { ism330is_status_reg_t status_reg; ism330is_status_master_mainpage_t status_sh; @@ -1471,14 +1482,20 @@ int32_t ism330is_all_sources_get(stmdev_ctx_t *ctx, ism330is_all_sources_t *val) int32_t ret; ret = ism330is_read_reg(ctx, ISM330IS_STATUS_REG, (uint8_t *)&status_reg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->drdy_xl = status_reg.xlda; val->drdy_gy = status_reg.gda; val->drdy_temp = status_reg.tda; ret = ism330is_read_reg(ctx, ISM330IS_STATUS_MASTER_MAINPAGE, (uint8_t *)&status_sh, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->sh_endop = status_sh.sens_hub_endop; val->sh_slave0_nack = status_sh.sens_hub_endop; @@ -1488,7 +1505,10 @@ int32_t ism330is_all_sources_get(stmdev_ctx_t *ctx, ism330is_all_sources_t *val) val->sh_wr_once = status_sh.sens_hub_endop; ret = ism330is_read_reg(ctx, ISM330IS_ISPU_INT_STATUS0_MAINPAGE, (uint8_t *)&status_ispu, 4); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->ispu = status_ispu; @@ -1503,7 +1523,7 @@ int32_t ism330is_all_sources_get(stmdev_ctx_t *ctx, ism330is_all_sources_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330is_status_reg_get(stmdev_ctx_t *ctx, +int32_t ism330is_status_reg_get(const stmdev_ctx_t *ctx, ism330is_status_reg_t *val) { int32_t ret; @@ -1520,7 +1540,7 @@ int32_t ism330is_status_reg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330is_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330is_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330is_status_reg_t status_reg; @@ -1540,7 +1560,7 @@ int32_t ism330is_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330is_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330is_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330is_status_reg_t status_reg; @@ -1560,7 +1580,7 @@ int32_t ism330is_gy_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330is_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330is_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330is_status_reg_t status_reg; @@ -1580,7 +1600,7 @@ int32_t ism330is_temp_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t ism330is_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1600,7 +1620,7 @@ int32_t ism330is_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t ism330is_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1624,7 +1644,7 @@ int32_t ism330is_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t ism330is_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1659,7 +1679,7 @@ int32_t ism330is_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t ism330is_pin_int1_route_set(const stmdev_ctx_t *ctx, ism330is_pin_int1_route_t val) { ism330is_int1_ctrl_t int1_ctrl; @@ -1668,13 +1688,16 @@ int32_t ism330is_pin_int1_route_set(stmdev_ctx_t *ctx, ret = ism330is_read_reg(ctx, ISM330IS_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); ret += ism330is_read_reg(ctx, ISM330IS_MD1_CFG, (uint8_t *)&md1_cfg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } int1_ctrl.int1_drdy_xl = val.drdy_xl; int1_ctrl.int1_drdy_g = val.drdy_gy; int1_ctrl.int1_boot = val.boot; ret += ism330is_write_reg(ctx, ISM330IS_INT1_CTRL, (uint8_t *)&int1_ctrl, - 1); + 1); md1_cfg.int1_shub = val.sh_endop; md1_cfg.int1_ispu = val.ispu; @@ -1691,7 +1714,7 @@ int32_t ism330is_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t ism330is_pin_int1_route_get(const stmdev_ctx_t *ctx, ism330is_pin_int1_route_t *val) { ism330is_int1_ctrl_t int1_ctrl; @@ -1700,7 +1723,10 @@ int32_t ism330is_pin_int1_route_get(stmdev_ctx_t *ctx, ret = ism330is_read_reg(ctx, ISM330IS_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); ret += ism330is_read_reg(ctx, ISM330IS_MD1_CFG, (uint8_t *)&md1_cfg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->drdy_xl = int1_ctrl.int1_drdy_xl; val->drdy_gy = int1_ctrl.int1_drdy_g; @@ -1719,7 +1745,7 @@ int32_t ism330is_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t ism330is_pin_int2_route_set(const stmdev_ctx_t *ctx, ism330is_pin_int2_route_t val) { ism330is_int2_ctrl_t int2_ctrl; @@ -1728,7 +1754,10 @@ int32_t ism330is_pin_int2_route_set(stmdev_ctx_t *ctx, ret = ism330is_read_reg(ctx, ISM330IS_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); ret += ism330is_read_reg(ctx, ISM330IS_MD2_CFG, (uint8_t *)&md2_cfg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } int2_ctrl.int2_drdy_xl = val.drdy_xl; int2_ctrl.int2_drdy_g = val.drdy_gy; @@ -1751,7 +1780,7 @@ int32_t ism330is_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t ism330is_pin_int2_route_get(const stmdev_ctx_t *ctx, ism330is_pin_int2_route_t *val) { ism330is_int2_ctrl_t int2_ctrl; @@ -1760,7 +1789,10 @@ int32_t ism330is_pin_int2_route_get(stmdev_ctx_t *ctx, ret = ism330is_read_reg(ctx, ISM330IS_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); ret += ism330is_read_reg(ctx, ISM330IS_MD2_CFG, (uint8_t *)&md2_cfg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->drdy_xl = int2_ctrl.int2_drdy_xl; val->drdy_gy = int2_ctrl.int2_drdy_g; @@ -1780,7 +1812,7 @@ int32_t ism330is_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_int_pin_mode_set(stmdev_ctx_t *ctx, +int32_t ism330is_int_pin_mode_set(const stmdev_ctx_t *ctx, ism330is_int_pin_mode_t val) { ism330is_ctrl3_c_t ctrl3_c; @@ -1805,7 +1837,7 @@ int32_t ism330is_int_pin_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_int_pin_mode_get(stmdev_ctx_t *ctx, +int32_t ism330is_int_pin_mode_get(const stmdev_ctx_t *ctx, ism330is_int_pin_mode_t *val) { ism330is_ctrl3_c_t ctrl3_c; @@ -1838,7 +1870,7 @@ int32_t ism330is_int_pin_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t ism330is_pin_polarity_set(const stmdev_ctx_t *ctx, ism330is_pin_polarity_t val) { ism330is_ctrl3_c_t ctrl3_c; @@ -1863,7 +1895,7 @@ int32_t ism330is_pin_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t ism330is_pin_polarity_get(const stmdev_ctx_t *ctx, ism330is_pin_polarity_t *val) { ism330is_ctrl3_c_t ctrl3_c; @@ -1909,7 +1941,7 @@ int32_t ism330is_pin_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val, +int32_t ism330is_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, uint8_t len) { int32_t ret; @@ -1929,7 +1961,7 @@ int32_t ism330is_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_sh_slave_connected_set(stmdev_ctx_t *ctx, +int32_t ism330is_sh_slave_connected_set(const stmdev_ctx_t *ctx, ism330is_sh_slave_connected_t val) { ism330is_master_config_t master_config; @@ -1937,7 +1969,10 @@ int32_t ism330is_sh_slave_connected_set(stmdev_ctx_t *ctx, ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } master_config.aux_sens_on = (uint8_t)val & 0x3U; ret = ism330is_write_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); @@ -1956,7 +1991,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_sh_slave_connected_get(stmdev_ctx_t *ctx, +int32_t ism330is_sh_slave_connected_get(const stmdev_ctx_t *ctx, ism330is_sh_slave_connected_t *val) { ism330is_master_config_t master_config; @@ -1965,7 +2000,10 @@ int32_t ism330is_sh_slave_connected_get(stmdev_ctx_t *ctx, ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (master_config.aux_sens_on) { @@ -2001,14 +2039,17 @@ int32_t ism330is_sh_slave_connected_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330is_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330is_master_config_t master_config; int32_t ret; ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } master_config.master_on = val; ret = ism330is_write_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); @@ -2027,14 +2068,17 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330is_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330is_master_config_t master_config; int32_t ret; ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } *val = master_config.master_on; @@ -2051,14 +2095,17 @@ int32_t ism330is_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_sh_master_interface_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330is_sh_master_interface_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330is_master_config_t master_config; int32_t ret; ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } master_config.shub_pu_en = val; ret = ism330is_write_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); @@ -2077,7 +2124,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_sh_master_interface_pull_up_get(stmdev_ctx_t *ctx, +int32_t ism330is_sh_master_interface_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330is_master_config_t master_config; @@ -2085,7 +2132,10 @@ int32_t ism330is_sh_master_interface_pull_up_get(stmdev_ctx_t *ctx, ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } *val = master_config.shub_pu_en; @@ -2102,14 +2152,17 @@ int32_t ism330is_sh_master_interface_pull_up_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330is_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330is_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330is_master_config_t master_config; int32_t ret; ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } master_config.pass_through_mode = (uint8_t)val; ret = ism330is_write_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); @@ -2128,7 +2181,7 @@ exit: * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t ism330is_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330is_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330is_master_config_t master_config; int32_t ret; @@ -2150,7 +2203,7 @@ int32_t ism330is_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t ism330is_sh_syncro_mode_set(const stmdev_ctx_t *ctx, ism330is_sh_syncro_mode_t val) { ism330is_master_config_t master_config; @@ -2158,7 +2211,10 @@ int32_t ism330is_sh_syncro_mode_set(stmdev_ctx_t *ctx, ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } master_config.start_config = (uint8_t)val & 0x01U; ret = ism330is_write_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); @@ -2177,7 +2233,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t ism330is_sh_syncro_mode_get(const stmdev_ctx_t *ctx, ism330is_sh_syncro_mode_t *val) { ism330is_master_config_t master_config; @@ -2186,7 +2242,10 @@ int32_t ism330is_sh_syncro_mode_get(stmdev_ctx_t *ctx, ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (master_config.start_config) { @@ -2214,7 +2273,7 @@ int32_t ism330is_sh_syncro_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t ism330is_sh_write_mode_set(const stmdev_ctx_t *ctx, ism330is_sh_write_mode_t val) { ism330is_master_config_t master_config; @@ -2222,7 +2281,10 @@ int32_t ism330is_sh_write_mode_set(stmdev_ctx_t *ctx, ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } master_config.write_once = (uint8_t)val & 0x01U; ret = ism330is_write_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); @@ -2241,7 +2303,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t ism330is_sh_write_mode_get(const stmdev_ctx_t *ctx, ism330is_sh_write_mode_t *val) { ism330is_master_config_t master_config; @@ -2250,7 +2312,10 @@ int32_t ism330is_sh_write_mode_get(stmdev_ctx_t *ctx, ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (master_config.write_once) { @@ -2278,14 +2343,17 @@ int32_t ism330is_sh_write_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_sh_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330is_sh_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330is_master_config_t master_config; int32_t ret; ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } master_config.rst_master_regs = val; ret = ism330is_write_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); @@ -2304,14 +2372,17 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330is_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330is_master_config_t master_config; int32_t ret; ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); ret += ism330is_read_reg(ctx, ISM330IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } *val = master_config.rst_master_regs; @@ -2331,26 +2402,35 @@ int32_t ism330is_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t ism330is_sh_cfg_write(const stmdev_ctx_t *ctx, ism330is_sh_cfg_write_t *val) { ism330is_slv0_add_t reg; int32_t ret; ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } reg.slave0_add = val->slv0_add; reg.rw_0 = 0; ret = ism330is_write_reg(ctx, ISM330IS_SLV0_ADD, (uint8_t *)®, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } ret = ism330is_write_reg(ctx, ISM330IS_SLV0_SUBADD, - &(val->slv0_subadd), 1); - if (ret != 0) { goto exit; } + &(val->slv0_subadd), 1); + if (ret != 0) + { + goto exit; + } ret = ism330is_write_reg(ctx, ISM330IS_DATAWRITE_SLV0, - &(val->slv0_data), 1); + &(val->slv0_data), 1); exit: ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); @@ -2366,7 +2446,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_sh_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism330is_sh_data_rate_set(const stmdev_ctx_t *ctx, ism330is_sh_data_rate_t val) { ism330is_slv0_config_t slv0_config; @@ -2374,7 +2454,10 @@ int32_t ism330is_sh_data_rate_set(stmdev_ctx_t *ctx, ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); ret += ism330is_read_reg(ctx, ISM330IS_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } slv0_config.shub_odr = (uint8_t)val & 0x07U; ret = ism330is_write_reg(ctx, ISM330IS_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); @@ -2393,7 +2476,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_sh_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism330is_sh_data_rate_get(const stmdev_ctx_t *ctx, ism330is_sh_data_rate_t *val) { ism330is_slv0_config_t slv0_config; @@ -2402,7 +2485,10 @@ int32_t ism330is_sh_data_rate_get(stmdev_ctx_t *ctx, ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); ret += ism330is_read_reg(ctx, ISM330IS_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (slv0_config.shub_odr) { @@ -2441,7 +2527,7 @@ int32_t ism330is_sh_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_sh_slv_cfg_read(stmdev_ctx_t *ctx, uint8_t idx, +int32_t ism330is_sh_slv_cfg_read(const stmdev_ctx_t *ctx, uint8_t idx, ism330is_sh_cfg_read_t *val) { ism330is_slv0_add_t slv_add; @@ -2449,25 +2535,37 @@ int32_t ism330is_sh_slv_cfg_read(stmdev_ctx_t *ctx, uint8_t idx, int32_t ret; ret = ism330is_mem_bank_set(ctx, ISM330IS_SENSOR_HUB_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } slv_add.slave0_add = val->slv_add; slv_add.rw_0 = 1; - ret = ism330is_write_reg(ctx, ISM330IS_SLV0_ADD + idx*3U, - (uint8_t *)&slv_add, 1); - if (ret != 0) { goto exit; } + ret = ism330is_write_reg(ctx, ISM330IS_SLV0_ADD + idx * 3U, + (uint8_t *)&slv_add, 1); + if (ret != 0) + { + goto exit; + } - ret = ism330is_write_reg(ctx, ISM330IS_SLV0_SUBADD + idx*3U, - &(val->slv_subadd), 1); - if (ret != 0) { goto exit; } + ret = ism330is_write_reg(ctx, ISM330IS_SLV0_SUBADD + idx * 3U, + &(val->slv_subadd), 1); + if (ret != 0) + { + goto exit; + } - ret = ism330is_read_reg(ctx, ISM330IS_SLV0_CONFIG + idx*3U, - (uint8_t *)&slv_config, 1); - if (ret != 0) { goto exit; } + ret = ism330is_read_reg(ctx, ISM330IS_SLV0_CONFIG + idx * 3U, + (uint8_t *)&slv_config, 1); + if (ret != 0) + { + goto exit; + } slv_config.slave0_numop = val->slv_len; - ret = ism330is_write_reg(ctx, ISM330IS_SLV0_CONFIG + idx*3U, - (uint8_t *)&slv_config, 1); + ret = ism330is_write_reg(ctx, ISM330IS_SLV0_CONFIG + idx * 3U, + (uint8_t *)&slv_config, 1); exit: ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); @@ -2483,7 +2581,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_sh_status_get(stmdev_ctx_t *ctx, +int32_t ism330is_sh_status_get(const stmdev_ctx_t *ctx, ism330is_status_master_t *val) { int32_t ret; @@ -2512,7 +2610,7 @@ int32_t ism330is_sh_status_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ispu_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t ism330is_ispu_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { ism330is_func_cfg_access_t func_cfg_access; int32_t ret; @@ -2536,7 +2634,7 @@ int32_t ism330is_ispu_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ispu_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t ism330is_ispu_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { ism330is_func_cfg_access_t func_cfg_access; int32_t ret; @@ -2549,7 +2647,7 @@ int32_t ism330is_ispu_reset_get(stmdev_ctx_t *ctx, uint8_t *val) return ret; } -int32_t ism330is_ispu_clock_set(stmdev_ctx_t *ctx, +int32_t ism330is_ispu_clock_set(const stmdev_ctx_t *ctx, ism330is_ispu_clock_sel_t val) { ism330is_ctrl10_c_t ctrl10_c; @@ -2566,7 +2664,7 @@ int32_t ism330is_ispu_clock_set(stmdev_ctx_t *ctx, return ret; } -int32_t ism330is_ispu_clock_get(stmdev_ctx_t *ctx, +int32_t ism330is_ispu_clock_get(const stmdev_ctx_t *ctx, ism330is_ispu_clock_sel_t *val) { ism330is_ctrl10_c_t ctrl10_c; @@ -2598,7 +2696,7 @@ int32_t ism330is_ispu_clock_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ispu_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism330is_ispu_data_rate_set(const stmdev_ctx_t *ctx, ism330is_ispu_data_rate_t val) { ism330is_ctrl9_c_t ctrl9_c; @@ -2625,7 +2723,7 @@ int32_t ism330is_ispu_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ispu_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism330is_ispu_data_rate_get(const stmdev_ctx_t *ctx, ism330is_ispu_data_rate_t *val) { ism330is_ctrl9_c_t ctrl9_c; @@ -2694,7 +2792,7 @@ int32_t ism330is_ispu_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ispu_bdu_set(stmdev_ctx_t *ctx, ism330is_ispu_bdu_t val) +int32_t ism330is_ispu_bdu_set(const stmdev_ctx_t *ctx, ism330is_ispu_bdu_t val) { ism330is_ctrl9_c_t ctrl9_c; int32_t ret; @@ -2718,7 +2816,7 @@ int32_t ism330is_ispu_bdu_set(stmdev_ctx_t *ctx, ism330is_ispu_bdu_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ispu_bdu_get(stmdev_ctx_t *ctx, ism330is_ispu_bdu_t *val) +int32_t ism330is_ispu_bdu_get(const stmdev_ctx_t *ctx, ism330is_ispu_bdu_t *val) { ism330is_ctrl9_c_t ctrl9_c; int32_t ret; @@ -2758,7 +2856,7 @@ int32_t ism330is_ispu_bdu_get(stmdev_ctx_t *ctx, ism330is_ispu_bdu_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ia_ispu_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t ism330is_ia_ispu_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; @@ -2783,7 +2881,7 @@ int32_t ism330is_ia_ispu_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ispu_write_dummy_cfg(stmdev_ctx_t *ctx, uint8_t offset, +int32_t ism330is_ispu_write_dummy_cfg(const stmdev_ctx_t *ctx, uint8_t offset, uint8_t *val, uint8_t len) { int32_t ret; @@ -2809,7 +2907,7 @@ int32_t ism330is_ispu_write_dummy_cfg(stmdev_ctx_t *ctx, uint8_t offset, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ispu_read_dummy_cfg(stmdev_ctx_t *ctx, uint8_t offset, +int32_t ism330is_ispu_read_dummy_cfg(const stmdev_ctx_t *ctx, uint8_t offset, uint8_t *val, uint8_t len) { int32_t ret; @@ -2833,17 +2931,23 @@ int32_t ism330is_ispu_read_dummy_cfg(stmdev_ctx_t *ctx, uint8_t offset, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ispu_boot_set(stmdev_ctx_t *ctx, +int32_t ism330is_ispu_boot_set(const stmdev_ctx_t *ctx, ism330is_ispu_boot_latched_t val) { ism330is_ispu_config_t ispu_config; int32_t ret; ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = ism330is_read_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } ispu_config.ispu_rst_n = (uint8_t)val; ispu_config.clk_dis = (uint8_t)val; @@ -2863,17 +2967,23 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ispu_boot_get(stmdev_ctx_t *ctx, +int32_t ism330is_ispu_boot_get(const stmdev_ctx_t *ctx, ism330is_ispu_boot_latched_t *val) { ism330is_ispu_config_t ispu_config; int32_t ret; ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret += ism330is_read_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } *val = ISM330IS_ISPU_TURN_OFF; if (ispu_config.ispu_rst_n == 1U || ispu_config.clk_dis == 1U) @@ -2895,17 +3005,23 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ispu_int_latched_set(stmdev_ctx_t *ctx, +int32_t ism330is_ispu_int_latched_set(const stmdev_ctx_t *ctx, ism330is_ispu_int_latched_t val) { ism330is_ispu_config_t ispu_config; int32_t ret; ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret += ism330is_read_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } ispu_config.latched = ((uint8_t)val & 0x1U); ret += ism330is_write_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1); @@ -2924,7 +3040,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ispu_int_latched_get(stmdev_ctx_t *ctx, +int32_t ism330is_ispu_int_latched_get(const stmdev_ctx_t *ctx, ism330is_ispu_int_latched_t *val) { ism330is_ispu_config_t ispu_config; @@ -2933,7 +3049,10 @@ int32_t ism330is_ispu_int_latched_get(stmdev_ctx_t *ctx, ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); ret += ism330is_read_reg(ctx, ISM330IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1); ret += ism330is_mem_bank_set(ctx, ISM330IS_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch ((ispu_config.latched)) { @@ -2961,14 +3080,17 @@ int32_t ism330is_ispu_int_latched_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ispu_get_boot_status(stmdev_ctx_t *ctx, +int32_t ism330is_ispu_get_boot_status(const stmdev_ctx_t *ctx, ism330is_ispu_boot_end_t *val) { ism330is_ispu_status_t ispu_boot_status; int32_t ret; ret = ism330is_mem_bank_set(ctx, ISM330IS_ISPU_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = ism330is_read_reg(ctx, ISM330IS_ISPU_STATUS, (uint8_t *)&ispu_boot_status, 1); *val = (ism330is_ispu_boot_end_t)ispu_boot_status.boot_end; @@ -2977,7 +3099,7 @@ int32_t ism330is_ispu_get_boot_status(stmdev_ctx_t *ctx, return ret; } -static int32_t ism330is_ispu_sel_memory_addr(stmdev_ctx_t *ctx, uint16_t mem_addr) +static int32_t ism330is_ispu_sel_memory_addr(const stmdev_ctx_t *ctx, uint16_t mem_addr) { uint8_t mem_addr_l, mem_addr_h; int32_t ret = 0; @@ -3003,7 +3125,7 @@ static int32_t ism330is_ispu_sel_memory_addr(stmdev_ctx_t *ctx, uint16_t mem_add * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ispu_write_memory(stmdev_ctx_t *ctx, +int32_t ism330is_ispu_write_memory(const stmdev_ctx_t *ctx, ism330is_ispu_memory_type_t mem_sel, uint16_t mem_addr, uint8_t *mem_data, uint16_t len) { @@ -3054,9 +3176,11 @@ int32_t ism330is_ispu_write_memory(stmdev_ctx_t *ctx, { ret += ism330is_ispu_sel_memory_addr(ctx, addr_s[i]); ret += ism330is_write_reg(ctx, ISM330IS_ISPU_MEM_DATA, &mem_data[k], len_s[i]); - k+=len_s[i]; + k += len_s[i]; } - } else { + } + else + { /* select memory address */ ret += ism330is_ispu_sel_memory_addr(ctx, mem_addr); ret += ism330is_write_reg(ctx, ISM330IS_ISPU_MEM_DATA, &mem_data[0], len); @@ -3083,7 +3207,7 @@ int32_t ism330is_ispu_write_memory(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ispu_read_memory(stmdev_ctx_t *ctx, +int32_t ism330is_ispu_read_memory(const stmdev_ctx_t *ctx, ism330is_ispu_memory_type_t mem_sel, uint16_t mem_addr, uint8_t *mem_data, uint16_t len) { @@ -3132,7 +3256,7 @@ int32_t ism330is_ispu_read_memory(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ispu_write_flags(stmdev_ctx_t *ctx, uint16_t data) +int32_t ism330is_ispu_write_flags(const stmdev_ctx_t *ctx, uint16_t data) { ism330is_ispu_if2s_flag_l_t flag_l; ism330is_ispu_if2s_flag_h_t flag_h; @@ -3163,7 +3287,7 @@ int32_t ism330is_ispu_write_flags(stmdev_ctx_t *ctx, uint16_t data) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ispu_read_flags(stmdev_ctx_t *ctx, uint16_t *data) +int32_t ism330is_ispu_read_flags(const stmdev_ctx_t *ctx, uint16_t *data) { uint8_t buff[2]; int32_t ret; @@ -3189,7 +3313,7 @@ int32_t ism330is_ispu_read_flags(stmdev_ctx_t *ctx, uint16_t *data) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ispu_clear_flags(stmdev_ctx_t *ctx) +int32_t ism330is_ispu_clear_flags(const stmdev_ctx_t *ctx) { uint8_t data = 1; int32_t ret; @@ -3213,7 +3337,7 @@ int32_t ism330is_ispu_clear_flags(stmdev_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ispu_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t ism330is_ispu_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, uint8_t len) { @@ -3239,7 +3363,7 @@ int32_t ism330is_ispu_read_data_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ispu_int1_ctrl_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t ism330is_ispu_int1_ctrl_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; @@ -3269,7 +3393,7 @@ int32_t ism330is_ispu_int1_ctrl_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ispu_int1_ctrl_set(stmdev_ctx_t *ctx, uint32_t val) +int32_t ism330is_ispu_int1_ctrl_set(const stmdev_ctx_t *ctx, uint32_t val) { ism330is_ispu_int1_ctrl0_t int1_ctrl0; ism330is_ispu_int1_ctrl1_t int1_ctrl1; @@ -3311,7 +3435,7 @@ int32_t ism330is_ispu_int1_ctrl_set(stmdev_ctx_t *ctx, uint32_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ispu_int2_ctrl_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t ism330is_ispu_int2_ctrl_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; @@ -3341,7 +3465,7 @@ int32_t ism330is_ispu_int2_ctrl_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ispu_int2_ctrl_set(stmdev_ctx_t *ctx, uint32_t val) +int32_t ism330is_ispu_int2_ctrl_set(const stmdev_ctx_t *ctx, uint32_t val) { ism330is_ispu_int2_ctrl0_t int2_ctrl0; ism330is_ispu_int2_ctrl1_t int2_ctrl1; @@ -3383,7 +3507,7 @@ int32_t ism330is_ispu_int2_ctrl_set(stmdev_ctx_t *ctx, uint32_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ispu_int_status_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t ism330is_ispu_int_status_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; @@ -3413,7 +3537,7 @@ int32_t ism330is_ispu_int_status_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ispu_algo_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t ism330is_ispu_algo_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; @@ -3443,7 +3567,7 @@ int32_t ism330is_ispu_algo_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t ism330is_ispu_algo_set(stmdev_ctx_t *ctx, uint32_t val) +int32_t ism330is_ispu_algo_set(const stmdev_ctx_t *ctx, uint32_t val) { ism330is_ispu_algo0_t algo0; ism330is_ispu_algo1_t algo1; diff --git a/sensor/stmemsc/ism330is_STdC/driver/ism330is_reg.h b/sensor/stmemsc/ism330is_STdC/driver/ism330is_reg.h index d65ba52a..0762763d 100644 --- a/sensor/stmemsc/ism330is_STdC/driver/ism330is_reg.h +++ b/sensor/stmemsc/ism330is_STdC/driver/ism330is_reg.h @@ -2315,10 +2315,10 @@ typedef union * them with a custom implementation. */ -int32_t ism330is_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t ism330is_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t ism330is_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t ism330is_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -2341,36 +2341,36 @@ typedef enum ISM330IS_SENSOR_HUB_MEM_BANK = 0x2, ISM330IS_ISPU_MEM_BANK = 0x3, } ism330is_mem_bank_t; -int32_t ism330is_mem_bank_set(stmdev_ctx_t *ctx, ism330is_mem_bank_t val); -int32_t ism330is_mem_bank_get(stmdev_ctx_t *ctx, ism330is_mem_bank_t *val); +int32_t ism330is_mem_bank_set(const stmdev_ctx_t *ctx, ism330is_mem_bank_t val); +int32_t ism330is_mem_bank_get(const stmdev_ctx_t *ctx, ism330is_mem_bank_t *val); typedef enum { ISM330IS_DRDY_LATCHED = 0x0, ISM330IS_DRDY_PULSED = 0x1, } ism330is_data_ready_mode_t; -int32_t ism330is_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t ism330is_data_ready_mode_set(const stmdev_ctx_t *ctx, ism330is_data_ready_mode_t val); -int32_t ism330is_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t ism330is_data_ready_mode_get(const stmdev_ctx_t *ctx, ism330is_data_ready_mode_t *val); -int32_t ism330is_device_id_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330is_device_id_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330is_device_id_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330is_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330is_software_reset(stmdev_ctx_t *ctx); +int32_t ism330is_software_reset(const stmdev_ctx_t *ctx); -int32_t ism330is_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330is_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330is_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330is_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { ISM330IS_HIGH_PERFOMANCE_MODE_ENABLED = 0x0, ISM330IS_HIGH_PERFOMANCE_MODE_DISABLED = 0x1, } ism330is_hm_mode_t; -int32_t ism330is_xl_hm_mode_set(stmdev_ctx_t *ctx, ism330is_hm_mode_t val); -int32_t ism330is_xl_hm_mode_get(stmdev_ctx_t *ctx, ism330is_hm_mode_t *val); -int32_t ism330is_gy_hm_mode_set(stmdev_ctx_t *ctx, ism330is_hm_mode_t val); -int32_t ism330is_gy_hm_mode_get(stmdev_ctx_t *ctx, ism330is_hm_mode_t *val); +int32_t ism330is_xl_hm_mode_set(const stmdev_ctx_t *ctx, ism330is_hm_mode_t val); +int32_t ism330is_xl_hm_mode_get(const stmdev_ctx_t *ctx, ism330is_hm_mode_t *val); +int32_t ism330is_gy_hm_mode_set(const stmdev_ctx_t *ctx, ism330is_hm_mode_t val); +int32_t ism330is_gy_hm_mode_get(const stmdev_ctx_t *ctx, ism330is_hm_mode_t *val); typedef enum { @@ -2379,9 +2379,9 @@ typedef enum ISM330IS_4g = 0x2, ISM330IS_8g = 0x3, } ism330is_xl_full_scale_t; -int32_t ism330is_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t ism330is_xl_full_scale_set(const stmdev_ctx_t *ctx, ism330is_xl_full_scale_t val); -int32_t ism330is_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t ism330is_xl_full_scale_get(const stmdev_ctx_t *ctx, ism330is_xl_full_scale_t *val); typedef enum @@ -2409,9 +2409,9 @@ typedef enum ISM330IS_XL_ODR_AT_6667Hz_LP = 0x1a, ISM330IS_XL_ODR_AT_1Hz6_LP = 0x1b, } ism330is_xl_data_rate_t; -int32_t ism330is_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism330is_xl_data_rate_set(const stmdev_ctx_t *ctx, ism330is_xl_data_rate_t val); -int32_t ism330is_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism330is_xl_data_rate_get(const stmdev_ctx_t *ctx, ism330is_xl_data_rate_t *val); typedef enum @@ -2422,9 +2422,9 @@ typedef enum ISM330IS_2000dps = 0x3, ISM330IS_125dps = 0x10, } ism330is_gy_full_scale_t; -int32_t ism330is_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t ism330is_gy_full_scale_set(const stmdev_ctx_t *ctx, ism330is_gy_full_scale_t val); -int32_t ism330is_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t ism330is_gy_full_scale_get(const stmdev_ctx_t *ctx, ism330is_gy_full_scale_t *val); typedef enum @@ -2451,24 +2451,24 @@ typedef enum ISM330IS_GY_ODR_AT_3333Hz_LP = 0x19, ISM330IS_GY_ODR_AT_6667Hz_LP = 0x1a, } ism330is_gy_data_rate_t; -int32_t ism330is_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism330is_gy_data_rate_set(const stmdev_ctx_t *ctx, ism330is_gy_data_rate_t val); -int32_t ism330is_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism330is_gy_data_rate_get(const stmdev_ctx_t *ctx, ism330is_gy_data_rate_t *val); -int32_t ism330is_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330is_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330is_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330is_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330is_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330is_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330is_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330is_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { ISM330IS_SLEEP_G_ENABLE = 0x0, ISM330IS_SLEEP_G_DISABLE = 0x1, } ism330is_sleep_t; -int32_t ism330is_sleep_set(stmdev_ctx_t *ctx, ism330is_sleep_t val); -int32_t ism330is_sleep_get(stmdev_ctx_t *ctx, ism330is_sleep_t *val); +int32_t ism330is_sleep_set(const stmdev_ctx_t *ctx, ism330is_sleep_t val); +int32_t ism330is_sleep_get(const stmdev_ctx_t *ctx, ism330is_sleep_t *val); typedef enum { @@ -2476,9 +2476,9 @@ typedef enum ISM330IS_XL_ST_POSITIVE = 0x1, ISM330IS_XL_ST_NEGATIVE = 0x2, } ism330is_xl_self_test_t; -int32_t ism330is_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t ism330is_xl_self_test_set(const stmdev_ctx_t *ctx, ism330is_xl_self_test_t val); -int32_t ism330is_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t ism330is_xl_self_test_get(const stmdev_ctx_t *ctx, ism330is_xl_self_test_t *val); typedef enum @@ -2487,36 +2487,36 @@ typedef enum ISM330IS_GY_ST_POSITIVE = 0x1, ISM330IS_GY_ST_NEGATIVE = 0x3, } ism330is_gy_self_test_t; -int32_t ism330is_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t ism330is_gy_self_test_set(const stmdev_ctx_t *ctx, ism330is_gy_self_test_t val); -int32_t ism330is_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t ism330is_gy_self_test_get(const stmdev_ctx_t *ctx, ism330is_gy_self_test_t *val); -int32_t ism330is_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330is_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330is_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330is_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { ISM330IS_SPI_4_WIRE = 0x0, ISM330IS_SPI_3_WIRE = 0x1, } ism330is_spi_mode_t; -int32_t ism330is_spi_mode_set(stmdev_ctx_t *ctx, ism330is_spi_mode_t val); -int32_t ism330is_spi_mode_get(stmdev_ctx_t *ctx, ism330is_spi_mode_t *val); +int32_t ism330is_spi_mode_set(const stmdev_ctx_t *ctx, ism330is_spi_mode_t val); +int32_t ism330is_spi_mode_get(const stmdev_ctx_t *ctx, ism330is_spi_mode_t *val); typedef enum { ISM330IS_I2C_ENABLE = 0x0, ISM330IS_I2C_DISABLE = 0x1, } ism330is_ui_i2c_mode_t; -int32_t ism330is_ui_i2c_mode_set(stmdev_ctx_t *ctx, ism330is_ui_i2c_mode_t val); -int32_t ism330is_ui_i2c_mode_get(stmdev_ctx_t *ctx, +int32_t ism330is_ui_i2c_mode_set(const stmdev_ctx_t *ctx, ism330is_ui_i2c_mode_t val); +int32_t ism330is_ui_i2c_mode_get(const stmdev_ctx_t *ctx, ism330is_ui_i2c_mode_t *val); -int32_t ism330is_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330is_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330is_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330is_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330is_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); +int32_t ism330is_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); typedef struct { @@ -2526,9 +2526,9 @@ typedef struct uint8_t sh_endop : 1; uint8_t ispu : 1; } ism330is_pin_int1_route_t; -int32_t ism330is_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t ism330is_pin_int1_route_set(const stmdev_ctx_t *ctx, ism330is_pin_int1_route_t val); -int32_t ism330is_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t ism330is_pin_int1_route_get(const stmdev_ctx_t *ctx, ism330is_pin_int1_route_t *val); typedef struct @@ -2540,9 +2540,9 @@ typedef struct uint8_t ispu_sleep : 1; uint8_t ispu : 1; } ism330is_pin_int2_route_t; -int32_t ism330is_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t ism330is_pin_int2_route_set(const stmdev_ctx_t *ctx, ism330is_pin_int2_route_t val); -int32_t ism330is_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t ism330is_pin_int2_route_get(const stmdev_ctx_t *ctx, ism330is_pin_int2_route_t *val); typedef enum @@ -2550,9 +2550,9 @@ typedef enum ISM330IS_PUSH_PULL = 0x0, ISM330IS_OPEN_DRAIN = 0x1, } ism330is_int_pin_mode_t; -int32_t ism330is_int_pin_mode_set(stmdev_ctx_t *ctx, +int32_t ism330is_int_pin_mode_set(const stmdev_ctx_t *ctx, ism330is_int_pin_mode_t val); -int32_t ism330is_int_pin_mode_get(stmdev_ctx_t *ctx, +int32_t ism330is_int_pin_mode_get(const stmdev_ctx_t *ctx, ism330is_int_pin_mode_t *val); typedef enum @@ -2560,9 +2560,9 @@ typedef enum ISM330IS_ACTIVE_HIGH = 0x0, ISM330IS_ACTIVE_LOW = 0x1, } ism330is_pin_polarity_t; -int32_t ism330is_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t ism330is_pin_polarity_set(const stmdev_ctx_t *ctx, ism330is_pin_polarity_t val); -int32_t ism330is_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t ism330is_pin_polarity_get(const stmdev_ctx_t *ctx, ism330is_pin_polarity_t *val); typedef struct @@ -2578,31 +2578,31 @@ typedef struct uint8_t sh_wr_once : 1; uint32_t ispu : 30; } ism330is_all_sources_t; -int32_t ism330is_all_sources_get(stmdev_ctx_t *ctx, +int32_t ism330is_all_sources_get(const stmdev_ctx_t *ctx, ism330is_all_sources_t *val); -int32_t ism330is_status_reg_get(stmdev_ctx_t *ctx, +int32_t ism330is_status_reg_get(const stmdev_ctx_t *ctx, ism330is_status_reg_t *val); -int32_t ism330is_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330is_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330is_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330is_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330is_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t ism330is_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330is_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t ism330is_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t ism330is_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t ism330is_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t ism330is_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t ism330is_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t ism330is_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330is_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330is_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330is_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330is_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val, +int32_t ism330is_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, uint8_t len); typedef enum @@ -2612,30 +2612,30 @@ typedef enum ISM330IS_SLV_0_1_2 = 0x2, ISM330IS_SLV_0_1_2_3 = 0x3, } ism330is_sh_slave_connected_t; -int32_t ism330is_sh_slave_connected_set(stmdev_ctx_t *ctx, +int32_t ism330is_sh_slave_connected_set(const stmdev_ctx_t *ctx, ism330is_sh_slave_connected_t val); -int32_t ism330is_sh_slave_connected_get(stmdev_ctx_t *ctx, +int32_t ism330is_sh_slave_connected_get(const stmdev_ctx_t *ctx, ism330is_sh_slave_connected_t *val); -int32_t ism330is_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330is_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330is_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330is_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330is_sh_master_interface_pull_up_set(stmdev_ctx_t *ctx, +int32_t ism330is_sh_master_interface_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330is_sh_master_interface_pull_up_get(stmdev_ctx_t *ctx, +int32_t ism330is_sh_master_interface_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t ism330is_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330is_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330is_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330is_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { ISM330IS_SH_TRG_XL_GY_DRDY = 0x0, ISM330IS_SH_TRIG_INT2 = 0x1, } ism330is_sh_syncro_mode_t; -int32_t ism330is_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t ism330is_sh_syncro_mode_set(const stmdev_ctx_t *ctx, ism330is_sh_syncro_mode_t val); -int32_t ism330is_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t ism330is_sh_syncro_mode_get(const stmdev_ctx_t *ctx, ism330is_sh_syncro_mode_t *val); typedef enum @@ -2643,13 +2643,13 @@ typedef enum ISM330IS_EACH_SH_CYCLE = 0x0, ISM330IS_ONLY_FIRST_CYCLE = 0x1, } ism330is_sh_write_mode_t; -int32_t ism330is_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t ism330is_sh_write_mode_set(const stmdev_ctx_t *ctx, ism330is_sh_write_mode_t val); -int32_t ism330is_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t ism330is_sh_write_mode_get(const stmdev_ctx_t *ctx, ism330is_sh_write_mode_t *val); -int32_t ism330is_sh_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330is_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330is_sh_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330is_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -2657,7 +2657,7 @@ typedef struct uint8_t slv0_subadd; uint8_t slv0_data; } ism330is_sh_cfg_write_t; -int32_t ism330is_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t ism330is_sh_cfg_write(const stmdev_ctx_t *ctx, ism330is_sh_cfg_write_t *val); typedef enum { @@ -2666,9 +2666,9 @@ typedef enum ISM330IS_SH_26Hz = 0x2, ISM330IS_SH_12_5Hz = 0x3, } ism330is_sh_data_rate_t; -int32_t ism330is_sh_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism330is_sh_data_rate_set(const stmdev_ctx_t *ctx, ism330is_sh_data_rate_t val); -int32_t ism330is_sh_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism330is_sh_data_rate_get(const stmdev_ctx_t *ctx, ism330is_sh_data_rate_t *val); typedef struct @@ -2677,23 +2677,23 @@ typedef struct uint8_t slv_subadd; uint8_t slv_len; } ism330is_sh_cfg_read_t; -int32_t ism330is_sh_slv_cfg_read(stmdev_ctx_t *ctx, uint8_t idx, +int32_t ism330is_sh_slv_cfg_read(const stmdev_ctx_t *ctx, uint8_t idx, ism330is_sh_cfg_read_t *val); -int32_t ism330is_sh_status_get(stmdev_ctx_t *ctx, +int32_t ism330is_sh_status_get(const stmdev_ctx_t *ctx, ism330is_status_master_t *val); -int32_t ism330is_ispu_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t ism330is_ispu_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t ism330is_ispu_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t ism330is_ispu_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { ISM330IS_ISPU_CLK_5MHz = 0x0, ISM330IS_ISPU_CLK_10MHz = 0x1, } ism330is_ispu_clock_sel_t; -int32_t ism330is_ispu_clock_set(stmdev_ctx_t *ctx, +int32_t ism330is_ispu_clock_set(const stmdev_ctx_t *ctx, ism330is_ispu_clock_sel_t val); -int32_t ism330is_ispu_clock_get(stmdev_ctx_t *ctx, +int32_t ism330is_ispu_clock_get(const stmdev_ctx_t *ctx, ism330is_ispu_clock_sel_t *val); typedef enum @@ -2710,9 +2710,9 @@ typedef enum ISM330IS_ISPU_ODR_AT_3333Hz = 0x9, ISM330IS_ISPU_ODR_AT_6667Hz = 0xa, } ism330is_ispu_data_rate_t; -int32_t ism330is_ispu_data_rate_set(stmdev_ctx_t *ctx, +int32_t ism330is_ispu_data_rate_set(const stmdev_ctx_t *ctx, ism330is_ispu_data_rate_t val); -int32_t ism330is_ispu_data_rate_get(stmdev_ctx_t *ctx, +int32_t ism330is_ispu_data_rate_get(const stmdev_ctx_t *ctx, ism330is_ispu_data_rate_t *val); typedef enum @@ -2722,14 +2722,14 @@ typedef enum ISM330IS_ISPU_BDU_ON_2B_2B = 0x2, ISM330IS_ISPU_BDU_ON_4B_4B = 0x3, } ism330is_ispu_bdu_t; -int32_t ism330is_ispu_bdu_set(stmdev_ctx_t *ctx, ism330is_ispu_bdu_t val); -int32_t ism330is_ispu_bdu_get(stmdev_ctx_t *ctx, ism330is_ispu_bdu_t *val); +int32_t ism330is_ispu_bdu_set(const stmdev_ctx_t *ctx, ism330is_ispu_bdu_t val); +int32_t ism330is_ispu_bdu_get(const stmdev_ctx_t *ctx, ism330is_ispu_bdu_t *val); -int32_t ism330is_ia_ispu_get(stmdev_ctx_t *ctx, uint32_t *val); +int32_t ism330is_ia_ispu_get(const stmdev_ctx_t *ctx, uint32_t *val); -int32_t ism330is_ispu_write_dummy_cfg(stmdev_ctx_t *ctx, uint8_t offset, +int32_t ism330is_ispu_write_dummy_cfg(const stmdev_ctx_t *ctx, uint8_t offset, uint8_t *val, uint8_t len); -int32_t ism330is_ispu_read_dummy_cfg(stmdev_ctx_t *ctx, uint8_t offset, +int32_t ism330is_ispu_read_dummy_cfg(const stmdev_ctx_t *ctx, uint8_t offset, uint8_t *val, uint8_t len); typedef enum @@ -2737,9 +2737,9 @@ typedef enum ISM330IS_ISPU_TURN_ON = 0x0, ISM330IS_ISPU_TURN_OFF = 0x1, } ism330is_ispu_boot_latched_t; -int32_t ism330is_ispu_boot_set(stmdev_ctx_t *ctx, +int32_t ism330is_ispu_boot_set(const stmdev_ctx_t *ctx, ism330is_ispu_boot_latched_t val); -int32_t ism330is_ispu_boot_get(stmdev_ctx_t *ctx, +int32_t ism330is_ispu_boot_get(const stmdev_ctx_t *ctx, ism330is_ispu_boot_latched_t *val); typedef enum @@ -2747,9 +2747,9 @@ typedef enum ISM330IS_ISPU_INT_PULSED = 0x0, ISM330IS_ISPU_INT_LATCHED = 0x1, } ism330is_ispu_int_latched_t; -int32_t ism330is_ispu_int_latched_set(stmdev_ctx_t *ctx, +int32_t ism330is_ispu_int_latched_set(const stmdev_ctx_t *ctx, ism330is_ispu_int_latched_t val); -int32_t ism330is_ispu_int_latched_get(stmdev_ctx_t *ctx, +int32_t ism330is_ispu_int_latched_get(const stmdev_ctx_t *ctx, ism330is_ispu_int_latched_t *val); typedef enum @@ -2757,7 +2757,7 @@ typedef enum ISM330IS_ISPU_BOOT_IN_PROGRESS = 0x0, ISM330IS_ISPU_BOOT_ENDED = 0x1, } ism330is_ispu_boot_end_t; -int32_t ism330is_ispu_get_boot_status(stmdev_ctx_t *ctx, +int32_t ism330is_ispu_get_boot_status(const stmdev_ctx_t *ctx, ism330is_ispu_boot_end_t *val); typedef enum @@ -2765,34 +2765,34 @@ typedef enum ISM330IS_ISPU_DATA_RAM_MEMORY = 0x0, ISM330IS_ISPU_PROGRAM_RAM_MEMORY = 0x1, } ism330is_ispu_memory_type_t; -int32_t ism330is_ispu_read_memory_enable(stmdev_ctx_t *ctx, +int32_t ism330is_ispu_read_memory_enable(const stmdev_ctx_t *ctx, ism330is_ispu_memory_type_t val); -int32_t ism330is_ispu_read_memory_disable(stmdev_ctx_t *ctx); +int32_t ism330is_ispu_read_memory_disable(const stmdev_ctx_t *ctx); -int32_t ism330is_ispu_write_memory(stmdev_ctx_t *ctx, +int32_t ism330is_ispu_write_memory(const stmdev_ctx_t *ctx, ism330is_ispu_memory_type_t mem_sel, uint16_t mem_addr, uint8_t *mem_data, uint16_t len); -int32_t ism330is_ispu_read_memory(stmdev_ctx_t *ctx, +int32_t ism330is_ispu_read_memory(const stmdev_ctx_t *ctx, ism330is_ispu_memory_type_t mem_sel, uint16_t mem_addr, uint8_t *mem_data, uint16_t len); -int32_t ism330is_ispu_write_flags(stmdev_ctx_t *ctx, uint16_t data); -int32_t ism330is_ispu_read_flags(stmdev_ctx_t *ctx, uint16_t *data); -int32_t ism330is_ispu_clear_flags(stmdev_ctx_t *ctx); +int32_t ism330is_ispu_write_flags(const stmdev_ctx_t *ctx, uint16_t data); +int32_t ism330is_ispu_read_flags(const stmdev_ctx_t *ctx, uint16_t *data); +int32_t ism330is_ispu_clear_flags(const stmdev_ctx_t *ctx); -int32_t ism330is_ispu_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t ism330is_ispu_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, uint8_t len); -int32_t ism330is_ispu_int1_ctrl_get(stmdev_ctx_t *ctx, uint32_t *val); -int32_t ism330is_ispu_int1_ctrl_set(stmdev_ctx_t *ctx, uint32_t val); -int32_t ism330is_ispu_int2_ctrl_get(stmdev_ctx_t *ctx, uint32_t *val); -int32_t ism330is_ispu_int2_ctrl_set(stmdev_ctx_t *ctx, uint32_t val); +int32_t ism330is_ispu_int1_ctrl_get(const stmdev_ctx_t *ctx, uint32_t *val); +int32_t ism330is_ispu_int1_ctrl_set(const stmdev_ctx_t *ctx, uint32_t val); +int32_t ism330is_ispu_int2_ctrl_get(const stmdev_ctx_t *ctx, uint32_t *val); +int32_t ism330is_ispu_int2_ctrl_set(const stmdev_ctx_t *ctx, uint32_t val); -int32_t ism330is_ispu_int_status_get(stmdev_ctx_t *ctx, uint32_t *val); +int32_t ism330is_ispu_int_status_get(const stmdev_ctx_t *ctx, uint32_t *val); -int32_t ism330is_ispu_algo_get(stmdev_ctx_t *ctx, uint32_t *val); -int32_t ism330is_ispu_algo_set(stmdev_ctx_t *ctx, uint32_t val); +int32_t ism330is_ispu_algo_get(const stmdev_ctx_t *ctx, uint32_t *val); +int32_t ism330is_ispu_algo_set(const stmdev_ctx_t *ctx, uint32_t val); /** * @} * diff --git a/sensor/stmemsc/l20g20is_STdC/driver/l20g20is_reg.c b/sensor/stmemsc/l20g20is_STdC/driver/l20g20is_reg.c deleted file mode 100644 index f3598ecf..00000000 --- a/sensor/stmemsc/l20g20is_STdC/driver/l20g20is_reg.c +++ /dev/null @@ -1,1343 +0,0 @@ -/** - ****************************************************************************** - * @file l20g20is_reg.c - * @author Sensors Software Solution Team - * @brief L20G20IS driver file - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -#include "l20g20is_reg.h" - -/** - * @defgroup L20G20IS - * @brief This file provides a set of functions needed to drive the - * l20g20is enhanced inertial module. - * @{ - * - */ - -/** - * @defgroup L20G20IS_Interfaces_Functions - * @brief This section provide a set of functions used to read and - * write a generic register of the device. - * MANDATORY: return 0 -> no Error. - * @{ - * - */ - -/** - * @brief Read generic device register - * - * @param ctx read / write interface definitions(ptr) - * @param reg register to read - * @param data pointer to buffer that store the data read(ptr) - * @param len number of consecutive register to read - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t __weak l20g20is_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) -{ - int32_t ret; - ret = ctx->read_reg(ctx->handle, reg, data, len); - - return ret; -} - -/** - * @brief Write generic device register - * - * @param ctx read / write interface definitions(ptr) - * @param reg register to write - * @param data pointer to data to write in register reg(ptr) - * @param len number of consecutive register to write - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t __weak l20g20is_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) -{ - int32_t ret; - ret = ctx->write_reg(ctx->handle, reg, data, len); - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup L20G20IS_Sensitivity - * @brief These functions convert raw-data into engineering units. - * @{ - * - */ - -float_t l20g20is_from_fs100dps_to_mdps(int16_t lsb) -{ - return (((float_t)lsb * 1000.0f) / 262.0f); -} - -float_t l20g20is_from_fs200dps_to_mdps(int16_t lsb) -{ - return (((float_t)lsb * 1000.0f) / 131.0f); -} - -float_t l20g20is_from_lsb_to_celsius(int16_t lsb) -{ - return (((float_t)lsb * 0.0625f) + 25.0f); -} - -/** - * @} - * - */ - -/** - * @defgroup L20G20IS_Data_generation - * @brief This section groups all the functions concerning data - * generation. - * @{ - * - */ - -/** - * @brief Gyroscope new data available.[get] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Iet the values of "xyda_ois" in reg DATA_STATUS_OIS.(ptr) - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_gy_flag_data_ready_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - l20g20is_data_status_ois_t data_status_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_DATA_STATUS_OIS, - (uint8_t *)&data_status_ois, 1); - *val = data_status_ois.xyda_ois; - - return ret; -} - -/** - * @brief Gyroscope data rate selection.[set] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of "pw" in reg L20G20IS. - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_gy_data_rate_set(stmdev_ctx_t *ctx, - l20g20is_gy_data_rate_t val) -{ - l20g20is_ctrl1_ois_t ctrl1_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, - (uint8_t *)&ctrl1_ois, 1); - - if (ret == 0) - { - ctrl1_ois.pw = (uint8_t)val; - ret = l20g20is_write_reg(ctx, L20G20IS_CTRL1_OIS, - (uint8_t *)&ctrl1_ois, 1); - } - - return ret; -} - -/** - * @brief Gyroscope data rate selection.[get] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Get the values of pw in reg CTRL1_OIS.(ptr) - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_gy_data_rate_get(stmdev_ctx_t *ctx, - l20g20is_gy_data_rate_t *val) -{ - l20g20is_ctrl1_ois_t ctrl1_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, - (uint8_t *)&ctrl1_ois, 1); - - switch (ctrl1_ois.pw) - { - case L20G20IS_GY_OFF: - *val = L20G20IS_GY_OFF; - break; - - case L20G20IS_GY_SLEEP: - *val = L20G20IS_GY_SLEEP; - break; - - case L20G20IS_GY_9k33Hz: - *val = L20G20IS_GY_9k33Hz; - break; - - default: - *val = L20G20IS_GY_OFF; - break; - } - - return ret; -} - -/** - * @brief Directional user orientation selection.[set] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val "orient" Swap X axis with Y axis. - * "signy" Y-axis angular rate sign selection. - * "signx" X-axis angular rate sign selection. - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_gy_orient_set(stmdev_ctx_t *ctx, - l20g20is_gy_orient_t val) -{ - l20g20is_ctrl1_ois_t ctrl1_ois; - l20g20is_ctrl2_ois_t ctrl2_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, - (uint8_t *)&ctrl1_ois, 1); - - if (ret == 0) - { - ctrl1_ois.orient = val.orient; - ret = l20g20is_write_reg(ctx, L20G20IS_CTRL1_OIS, - (uint8_t *)&ctrl1_ois, 1); - } - - if (ret == 0) - { - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS, - (uint8_t *)&ctrl2_ois, 1); - } - - if (ret == 0) - { - ctrl2_ois.signx = val.signx; - ctrl2_ois.signy = val.signy; - ret = l20g20is_write_reg(ctx, L20G20IS_CTRL2_OIS, - (uint8_t *)&ctrl2_ois, 1); - } - - return ret; -} - -/** - * @brief Directional user orientation selection.[get] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val "orient" Swap X axis with Y axis. - * "signy" Y-axis angular rate sign selection. - * "signx" X-axis angular rate sign selection. - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_gy_orient_get(stmdev_ctx_t *ctx, - l20g20is_gy_orient_t *val) -{ - l20g20is_ctrl1_ois_t ctrl1_ois; - l20g20is_ctrl2_ois_t ctrl2_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, - (uint8_t *)&ctrl1_ois, 1); - - if (ret == 0) - { - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS, - (uint8_t *)&ctrl2_ois, 1); - val->orient = ctrl1_ois.orient; - val->signy = ctrl2_ois.signy; - val->signy = ctrl2_ois.signy; - } - - return ret; -} - -/** - * @brief Block data update.[set] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of odu in reg CTRL1_OIS. - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) -{ - l20g20is_ctrl1_ois_t ctrl1_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, - (uint8_t *)&ctrl1_ois, 1); - - if (ret == 0) - { - ctrl1_ois.odu = (uint8_t)val; - ret = l20g20is_write_reg(ctx, L20G20IS_CTRL1_OIS, - (uint8_t *)&ctrl1_ois, 1); - } - - return ret; -} - -/** - * @brief Blockdataupdate.[get] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Get the values of odu in reg CTRL1_OIS.(ptr) - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_block_data_update_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - l20g20is_ctrl1_ois_t ctrl1_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, - (uint8_t *)&ctrl1_ois, 1); - *val = (uint8_t)ctrl1_ois.odu; - - return ret; -} - -/** - * @brief User offset correction.[set] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val "offx" offset on X axis. - "offy" offset on Y axis. - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_angular_rate_offset_set(stmdev_ctx_t *ctx, - l20g20is_off_t val) -{ - l20g20is_off_x_t off_x; - l20g20is_off_y_t off_y; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_OFF_X, (uint8_t *)&off_x, 1); - - if (ret == 0) - { - off_x.offx = val.offx; - ret = l20g20is_write_reg(ctx, L20G20IS_OFF_X, (uint8_t *)&off_x, 1); - } - - if (ret == 0) - { - ret = l20g20is_read_reg(ctx, L20G20IS_OFF_Y, (uint8_t *)&off_y, 1); - } - - if (ret == 0) - { - off_y.offy = val.offy; - ret = l20g20is_write_reg(ctx, L20G20IS_OFF_Y, (uint8_t *)&off_y, 1); - } - - return ret; -} - -/** - * @brief User offset correction.[get] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val "offx" offset on X axis. - "offy" offset on Y axis. - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_angular_rate_offset_get(stmdev_ctx_t *ctx, - l20g20is_off_t *val) -{ - l20g20is_off_x_t off_x; - l20g20is_off_y_t off_y; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_OFF_X, (uint8_t *)&off_x, 1); - - if (ret == 0) - { - ret = l20g20is_read_reg(ctx, L20G20IS_OFF_Y, (uint8_t *)&off_y, 1); - val->offx = off_x.offx; - val->offy = off_y.offy; - } - - return ret; -} - -/** - * @brief Gyroscope full-scale selection.[set] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of "fs_sel" in reg L20G20IS. - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_gy_full_scale_set(stmdev_ctx_t *ctx, - l20g20is_gy_fs_t val) -{ - l20g20is_ois_cfg_reg_t ois_cfg_reg; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_OIS_CFG_REG, - (uint8_t *)&ois_cfg_reg, 1); - - if (ret == 0) - { - ois_cfg_reg.fs_sel = (uint8_t)val; - ret = l20g20is_write_reg(ctx, L20G20IS_OIS_CFG_REG, - (uint8_t *)&ois_cfg_reg, 1); - } - - return ret; -} - -/** - * @brief Gyroscope full-scale selection.[get] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Get the values of fs_sel in reg OIS_CFG_REG.(ptr) - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_gy_full_scale_get(stmdev_ctx_t *ctx, - l20g20is_gy_fs_t *val) -{ - l20g20is_ois_cfg_reg_t ois_cfg_reg; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_OIS_CFG_REG, - (uint8_t *)&ois_cfg_reg, 1); - - switch (ois_cfg_reg.fs_sel) - { - case L20G20IS_100dps: - *val = L20G20IS_100dps; - break; - - case L20G20IS_200dps: - *val = L20G20IS_200dps; - break; - - default: - *val = L20G20IS_100dps; - break; - } - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup L20G20IS_Dataoutput - * @brief This section groups all the data output functions. - * @{ - * - */ - -/** - * @brief Temperature data output register (r). L and H registers together - * express a 16-bit word in two’s complement.[get] - * - * @param ctx Read / write interface definitions.(ptr) - * @param buff Buffer that stores the data read.(ptr) - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) -{ - uint8_t buff[2]; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_TEMP_OUT_L, buff, 2); - *val = (int16_t)buff[1]; - *val = (*val * 256) + (int16_t)buff[0]; - - return ret; -} - -/** - * @brief Angular rate sensor. The value is expressed as a 16-bit word in - * two’s complement.[get] - * - * @param ctx Read / write interface definitions.(ptr) - * @param buff Buffer that stores the data read.(ptr) - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) -{ - uint8_t buff[4]; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_OUT_X_L, buff, 4); - val[0] = (int16_t)buff[1]; - val[0] = (val[0] * 256) + (int16_t)buff[0]; - val[1] = (int16_t)buff[3]; - val[1] = (val[1] * 256) + (int16_t)buff[2]; - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup L20G20IS_Common - * @brief This section groups common useful functions. - * @{ - * - */ - -/** - * @brief DeviceWhoamI.[get] - * - * @param ctx Read / write interface definitions.(ptr) - * @param buff Buffer that stores the data read.(ptr) - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_dev_id_get(stmdev_ctx_t *ctx, uint8_t *buff) -{ - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_WHO_AM_I, buff, 1); - - return ret; -} - -/** - * @brief Device status register.[get] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Data available on all axis.(ptr) - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_dev_status_get(stmdev_ctx_t *ctx, - l20g20is_dev_status_t *val) -{ - l20g20is_data_status_ois_t data_status_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_DATA_STATUS_OIS, - (uint8_t *)&data_status_ois, 1); - val->xyda_ois = data_status_ois.xyda_ois; - - return ret; -} - -/** - * @brief Big/Little Endian data selection.[set] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of "ble" in reg L20G20IS. - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_dev_data_format_set(stmdev_ctx_t *ctx, - l20g20is_ble_t val) -{ - l20g20is_ctrl1_ois_t ctrl1_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, - (uint8_t *)&ctrl1_ois, 1); - - if (ret == 0) - { - ctrl1_ois.ble = (uint8_t)val; - ret = l20g20is_write_reg(ctx, L20G20IS_CTRL1_OIS, - (uint8_t *)&ctrl1_ois, 1); - } - - return ret; -} - -/** - * @brief Big/Little Endian data selection.[get] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Get the values of ble in reg CTRL1_OIS.(ptr) - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_dev_data_format_get(stmdev_ctx_t *ctx, - l20g20is_ble_t *val) -{ - l20g20is_ctrl1_ois_t ctrl1_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, - (uint8_t *)&ctrl1_ois, 1); - - switch (ctrl1_ois.ble) - { - case L20G20IS_LSB_LOW_ADDRESS: - *val = L20G20IS_LSB_LOW_ADDRESS; - break; - - case L20G20IS_MSB_LOW_ADDRESS: - *val = L20G20IS_MSB_LOW_ADDRESS; - break; - - default: - *val = L20G20IS_LSB_LOW_ADDRESS; - break; - } - - return ret; -} - -/** - * @brief Reboot memory content. Reload the calibration parameters.[set] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of boot in reg CTRL1_OIS. - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_dev_boot_set(stmdev_ctx_t *ctx, uint8_t val) -{ - l20g20is_ctrl1_ois_t ctrl1_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, - (uint8_t *)&ctrl1_ois, 1); - - if (ret == 0) - { - ctrl1_ois.boot = (uint8_t)val; - ret = l20g20is_write_reg(ctx, L20G20IS_CTRL1_OIS, - (uint8_t *)&ctrl1_ois, 1); - } - - return ret; -} - -/** - * @brief Reboot memory content. Reload the calibration parameters.[get] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Get the values of boot in reg CTRL1_OIS.(ptr) - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_dev_boot_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - l20g20is_ctrl1_ois_t ctrl1_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, - (uint8_t *)&ctrl1_ois, 1); - *val = (uint8_t)ctrl1_ois.boot; - - return ret; -} - -/** - * @brief Software reset. Restore the default values in user registers.[set] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of sw_rst in reg CTRL2_OIS. - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_dev_reset_set(stmdev_ctx_t *ctx, uint8_t val) -{ - l20g20is_ctrl2_ois_t ctrl2_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS, - (uint8_t *)&ctrl2_ois, 1); - - if (ret == 0) - { - ctrl2_ois.sw_rst = (uint8_t)val; - ret = l20g20is_write_reg(ctx, L20G20IS_CTRL2_OIS, - (uint8_t *)&ctrl2_ois, 1); - } - - return ret; -} - -/** - * @brief Software reset. Restore the default values in user - * registers.[get] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Get the values of sw_rst in reg CTRL2_OIS.(ptr) - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_dev_reset_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - l20g20is_ctrl2_ois_t ctrl2_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS, - (uint8_t *)&ctrl2_ois, 1); - *val = (uint8_t)ctrl2_ois.sw_rst; - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup L20G20IS_Filters - * @brief This section group all the functions concerning the - * filters configuration. - * @{ - * - */ - -/** - * @brief Gyroscope high-pass filter bandwidth selection.[set] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of "hpf" in reg L20G20IS. - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_gy_filter_hp_bandwidth_set(stmdev_ctx_t *ctx, - l20g20is_gy_hp_bw_t val) -{ - l20g20is_ctrl2_ois_t ctrl2_ois; - l20g20is_ois_cfg_reg_t ois_cfg_reg; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS, - (uint8_t *)&ctrl2_ois, 1); - - if (ret == 0) - { - ctrl2_ois.hpf = ((uint8_t)val & 0x80U) >> 4; - ret = l20g20is_write_reg(ctx, L20G20IS_CTRL2_OIS, - (uint8_t *)&ctrl2_ois, 1); - } - - if (ret == 0) - { - ret = l20g20is_read_reg(ctx, L20G20IS_OIS_CFG_REG, - (uint8_t *)&ois_cfg_reg, 1); - } - - if (ret == 0) - { - ois_cfg_reg.hpf_bw = (uint8_t)val & 0x03U; - ret = l20g20is_write_reg(ctx, L20G20IS_OIS_CFG_REG, - (uint8_t *)&ois_cfg_reg, 1); - } - - return ret; -} - -/** - * @brief Gyroscope high-pass filter bandwidth selection.[get] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Get the values of hpf in reg CTRL2_OIS.(ptr) - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_gy_filter_hp_bandwidth_get(stmdev_ctx_t *ctx, - l20g20is_gy_hp_bw_t *val) -{ - l20g20is_ctrl2_ois_t ctrl2_ois; - l20g20is_ois_cfg_reg_t ois_cfg_reg; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS, - (uint8_t *)&ctrl2_ois, 1); - - if (ret == 0) - { - ret = l20g20is_read_reg(ctx, L20G20IS_OIS_CFG_REG, - (uint8_t *)&ois_cfg_reg, 1); - - switch ((ctrl2_ois.hpf << 4) + ois_cfg_reg.hpf_bw) - { - case L20G20IS_HPF_BYPASS: - *val = L20G20IS_HPF_BYPASS; - break; - - case L20G20IS_HPF_BW_23mHz: - *val = L20G20IS_HPF_BW_23mHz; - break; - - case L20G20IS_HPF_BW_91mHz: - *val = L20G20IS_HPF_BW_91mHz; - break; - - case L20G20IS_HPF_BW_324mHz: - *val = L20G20IS_HPF_BW_324mHz; - break; - - case L20G20IS_HPF_BW_1Hz457: - *val = L20G20IS_HPF_BW_1Hz457; - break; - - default: - *val = L20G20IS_HPF_BYPASS; - break; - } - } - - return ret; -} - -/** - * @brief Gyroscope high-pass filter reset.[set] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of hp_rst in reg CTRL2_OIS. - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_gy_filter_hp_reset_set(stmdev_ctx_t *ctx, - uint8_t val) -{ - l20g20is_ctrl2_ois_t ctrl2_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS, - (uint8_t *)&ctrl2_ois, 1); - - if (ret == 0) - { - ctrl2_ois.hp_rst = (uint8_t)val; - ret = l20g20is_write_reg(ctx, L20G20IS_CTRL2_OIS, - (uint8_t *)&ctrl2_ois, 1); - } - - return ret; -} - -/** - * @brief Gyroscope high-pass filter reset.[get] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Get the values of hp_rst in reg CTRL2_OIS.(ptr) - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_gy_filter_hp_reset_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - l20g20is_ctrl2_ois_t ctrl2_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS, - (uint8_t *)&ctrl2_ois, 1); - *val = (uint8_t)ctrl2_ois.hp_rst; - - return ret; -} - -/** - * @brief Gyroscope filter low pass cutoff frequency selection.[set] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of "lpf_bw" in reg L20G20IS. - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_gy_filter_lp_bandwidth_set(stmdev_ctx_t *ctx, - l20g20is_gy_lp_bw_t val) -{ - l20g20is_ctrl2_ois_t ctrl2_ois; - l20g20is_ctrl3_ois_t ctrl3_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS, - (uint8_t *)&ctrl2_ois, 1); - - if (ret == 0) - { - ctrl2_ois.lpf_bw = (uint8_t)val & 0x03U; - ret = l20g20is_write_reg(ctx, L20G20IS_CTRL2_OIS, - (uint8_t *)&ctrl2_ois, 1); - } - - if (ret == 0) - { - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL3_OIS, - (uint8_t *)&ctrl3_ois, 1); - } - - if (ret == 0) - { - ctrl3_ois.lpf_bw = ((uint8_t)val & 0x04U) >> 2; - ret = l20g20is_write_reg(ctx, L20G20IS_CTRL3_OIS, - (uint8_t *)&ctrl3_ois, 1); - } - - return ret; -} - -/** - * @brief Gyroscope filter low pass cutoff frequency selection.[get] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Get the values of lpf_bw in reg CTRL2_OIS.(ptr) - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_gy_filter_lp_bandwidth_get(stmdev_ctx_t *ctx, - l20g20is_gy_lp_bw_t *val) -{ - l20g20is_ctrl2_ois_t ctrl2_ois; - l20g20is_ctrl3_ois_t ctrl3_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL3_OIS, - (uint8_t *)&ctrl3_ois, 1); - - if (ret == 0) - { - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL2_OIS, - (uint8_t *)&ctrl2_ois, 1); - - switch ((ctrl3_ois.lpf_bw << 2) + ctrl2_ois.lpf_bw) - { - case L20G20IS_LPF_BW_1150Hz: - *val = L20G20IS_LPF_BW_1150Hz; - break; - - case L20G20IS_LPF_BW_290Hz: - *val = L20G20IS_LPF_BW_290Hz; - break; - - case L20G20IS_LPF_BW_210Hz: - *val = L20G20IS_LPF_BW_210Hz; - break; - - case L20G20IS_LPF_BW_160Hz: - *val = L20G20IS_LPF_BW_160Hz; - break; - - case L20G20IS_LPF_BW_450Hz: - *val = L20G20IS_LPF_BW_450Hz; - break; - - default: - *val = L20G20IS_LPF_BW_290Hz; - break; - } - } - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup L20G20IS_Serial_interface - * @brief This section groups all the functions concerning main - * serial interface management. - * @{ - * - */ - -/** - * @brief SPI Serial Interface Mode selection.[set] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of "sim" in reg L20G20IS. - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_spi_mode_set(stmdev_ctx_t *ctx, l20g20is_sim_t val) -{ - l20g20is_ctrl1_ois_t ctrl1_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, - (uint8_t *)&ctrl1_ois, 1); - - if (ret == 0) - { - ctrl1_ois.sim = (uint8_t)val; - ret = l20g20is_write_reg(ctx, L20G20IS_CTRL1_OIS, - (uint8_t *)&ctrl1_ois, 1); - } - - return ret; -} - -/** - * @brief SPI Serial Interface Mode selection.[get] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Get the values of sim in reg CTRL1_OIS.(ptr) - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_spi_mode_get(stmdev_ctx_t *ctx, l20g20is_sim_t *val) -{ - l20g20is_ctrl1_ois_t ctrl1_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, - (uint8_t *)&ctrl1_ois, 1); - - switch (ctrl1_ois.sim) - { - case L20G20IS_SPI_4_WIRE: - *val = L20G20IS_SPI_4_WIRE; - break; - - case L20G20IS_SPI_3_WIRE: - *val = L20G20IS_SPI_3_WIRE; - break; - - default: - *val = L20G20IS_SPI_4_WIRE; - break; - } - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup L20G20IS_Interrupt_pins - * @brief This section groups all the functions that manage - * interrupt pins. - * @{ - * - */ - -/** - * @brief Latched/pulsed interrupt.[set] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of "dr_pulsed" in reg L20G20IS. - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_pin_notification_set(stmdev_ctx_t *ctx, - l20g20is_lir_t val) -{ - l20g20is_ctrl1_ois_t ctrl1_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, - (uint8_t *)&ctrl1_ois, 1); - - if (ret == 0) - { - ctrl1_ois.dr_pulsed = (uint8_t)val; - ret = l20g20is_write_reg(ctx, L20G20IS_CTRL1_OIS, - (uint8_t *)&ctrl1_ois, 1); - } - - return ret; -} - -/** - * @brief Latched/pulsed interrupt.[get] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Get the values of dr_pulsed in reg CTRL1_OIS.(ptr) - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_pin_notification_get(stmdev_ctx_t *ctx, - l20g20is_lir_t *val) -{ - l20g20is_ctrl1_ois_t ctrl1_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL1_OIS, - (uint8_t *)&ctrl1_ois, 1); - - switch (ctrl1_ois.dr_pulsed) - { - case L20G20IS_INT_LATCHED: - *val = L20G20IS_INT_LATCHED; - break; - - case L20G20IS_INT_PULSED: - *val = L20G20IS_INT_PULSED; - break; - - default: - *val = L20G20IS_INT_LATCHED; - break; - } - - return ret; -} - -/** - * @brief Interrupt pin active-high/low.Interrupt active-high/low.[set] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of "h_l_active" in reg L20G20IS. - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_pin_polarity_set(stmdev_ctx_t *ctx, - l20g20is_pin_pol_t val) -{ - l20g20is_ctrl3_ois_t ctrl3_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL3_OIS, - (uint8_t *)&ctrl3_ois, 1); - - if (ret == 0) - { - ctrl3_ois.h_l_active = (uint8_t)val; - ret = l20g20is_write_reg(ctx, L20G20IS_CTRL3_OIS, - (uint8_t *)&ctrl3_ois, 1); - } - - return ret; -} - -/** - * @brief Interrupt pin active-high/low.Interrupt active-high/low.[get] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Get the values of h_l_active in reg CTRL3_OIS.(ptr) - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_pin_polarity_get(stmdev_ctx_t *ctx, - l20g20is_pin_pol_t *val) -{ - l20g20is_ctrl3_ois_t ctrl3_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL3_OIS, - (uint8_t *)&ctrl3_ois, 1); - - switch (ctrl3_ois.h_l_active) - { - case L20G20IS_ACTIVE_HIGH: - *val = L20G20IS_ACTIVE_HIGH; - break; - - case L20G20IS_ACTIVE_LOW: - *val = L20G20IS_ACTIVE_LOW; - break; - - default: - *val = L20G20IS_ACTIVE_HIGH; - break; - } - - return ret; -} - -/** - * @brief Push-pull/open drain selection on interrupt pads.[set] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of "drdy_od" in reg L20G20IS. - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_pin_mode_set(stmdev_ctx_t *ctx, l20g20is_pp_od_t val) -{ - l20g20is_ctrl4_ois_t ctrl4_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL4_OIS, - (uint8_t *)&ctrl4_ois, 1); - - if (ret == 0) - { - ctrl4_ois.drdy_od = (uint8_t)val; - ret = l20g20is_write_reg(ctx, L20G20IS_CTRL4_OIS, - (uint8_t *)&ctrl4_ois, 1); - } - - return ret; -} - -/** - * @brief Push-pull/open drain selection on interrupt pads.[get] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Get the values of drdy_od in reg CTRL4_OIS.(ptr) - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_pin_mode_get(stmdev_ctx_t *ctx, - l20g20is_pp_od_t *val) -{ - l20g20is_ctrl4_ois_t ctrl4_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL4_OIS, - (uint8_t *)&ctrl4_ois, 1); - - switch (ctrl4_ois.drdy_od) - { - case L20G20IS_PUSH_PULL: - *val = L20G20IS_PUSH_PULL; - break; - - case L20G20IS_OPEN_DRAIN: - *val = L20G20IS_OPEN_DRAIN; - break; - - default: - *val = L20G20IS_PUSH_PULL; - break; - } - - return ret; -} - -/** - * @brief Route a signal on DRDY pin.[set] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val "temp_data_on_drdy" Temperature data-ready signal. - * "drdy_en" Angular rate data-ready signal. - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_pin_drdy_route_set(stmdev_ctx_t *ctx, - l20g20is_pin_drdy_route_t val) -{ - l20g20is_ctrl4_ois_t ctrl4_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL4_OIS, - (uint8_t *)&ctrl4_ois, 1); - - if (ret == 0) - { - ctrl4_ois.drdy_en = val.drdy_en; - ctrl4_ois.temp_data_on_drdy = val.temp_data_on_drdy; - ret = l20g20is_write_reg(ctx, L20G20IS_CTRL4_OIS, - (uint8_t *)&ctrl4_ois, 1); - } - - return ret; -} - -/** - * @brief Route a signal on DRDY pin.[get] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val "temp_data_on_drdy" Temperature data-ready signal. - * "drdy_en" Angular rate data-ready signal. - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_pin_drdy_route_get(stmdev_ctx_t *ctx, - l20g20is_pin_drdy_route_t *val) -{ - l20g20is_ctrl4_ois_t ctrl4_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL4_OIS, - (uint8_t *)&ctrl4_ois, 1); - val->temp_data_on_drdy = ctrl4_ois.temp_data_on_drdy; - val->drdy_en = ctrl4_ois.drdy_en; - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup L20G20IS_Self_test - * @brief This section groups all the functions that manage self - * test configuration. - * @{ - * - */ - -/** - * @brief Enable/disable self-test mode for gyroscope.[set] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Change the values of "st_en" in reg L20G20IS. - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_gy_self_test_set(stmdev_ctx_t *ctx, - l20g20is_gy_self_test_t val) -{ - l20g20is_ctrl3_ois_t ctrl3_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL3_OIS, - (uint8_t *)&ctrl3_ois, 1); - - if (ret == 0) - { - ctrl3_ois.st_en = ((uint8_t)val & 0x02U) >> 1; - ctrl3_ois.st_sign = (uint8_t)val & 0x01U; - ret = l20g20is_write_reg(ctx, L20G20IS_CTRL3_OIS, - (uint8_t *)&ctrl3_ois, 1); - } - - return ret; -} - -/** - * @brief Enable/disable self-test mode for gyroscope.[get] - * - * @param ctx Read / write interface definitions.(ptr) - * @param val Get the values of st_en in reg CTRL3_OIS.(ptr) - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t l20g20is_gy_self_test_get(stmdev_ctx_t *ctx, - l20g20is_gy_self_test_t *val) -{ - l20g20is_ctrl3_ois_t ctrl3_ois; - int32_t ret; - ret = l20g20is_read_reg(ctx, L20G20IS_CTRL3_OIS, - (uint8_t *)&ctrl3_ois, 1); - - switch ((ctrl3_ois.st_en << 1) + ctrl3_ois.st_sign) - { - case L20G20IS_ST_DISABLE: - *val = L20G20IS_ST_DISABLE; - break; - - case L20G20IS_ST_POSITIVE: - *val = L20G20IS_ST_POSITIVE; - break; - - case L20G20IS_ST_NEGATIVE: - *val = L20G20IS_ST_NEGATIVE; - break; - - default: - *val = L20G20IS_ST_DISABLE; - break; - } - - return ret; -} - -/** - * @} - * - */ - -/** - * @} - * - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/l20g20is_STdC/driver/l20g20is_reg.h b/sensor/stmemsc/l20g20is_STdC/driver/l20g20is_reg.h deleted file mode 100644 index f0810f7c..00000000 --- a/sensor/stmemsc/l20g20is_STdC/driver/l20g20is_reg.h +++ /dev/null @@ -1,572 +0,0 @@ -/** - ****************************************************************************** - * @file l20g20is_reg.h - * @author Sensors Software Solution Team - * @brief This file contains all the functions prototypes for the - * l20g20is_reg.c driver. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef L20G20IS_REGS_H -#define L20G20IS_REGS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include -#include -#include - -/** @addtogroup L20G20IS - * @{ - * - */ - -/** @defgroup Endianness definitions - * @{ - * - */ - -#ifndef DRV_BYTE_ORDER -#ifndef __BYTE_ORDER__ - -#define DRV_LITTLE_ENDIAN 1234 -#define DRV_BIG_ENDIAN 4321 - -/** if _BYTE_ORDER is not defined, choose the endianness of your architecture - * by uncommenting the define which fits your platform endianness - */ -//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN -#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN - -#else /* defined __BYTE_ORDER__ */ - -#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ -#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ -#define DRV_BYTE_ORDER __BYTE_ORDER__ - -#endif /* __BYTE_ORDER__*/ -#endif /* DRV_BYTE_ORDER */ - -/** - * @} - * - */ - -/** @defgroup STMicroelectronics sensors common types - * @{ - * - */ - -#ifndef MEMS_SHARED_TYPES -#define MEMS_SHARED_TYPES - -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t bit0 : 1; - uint8_t bit1 : 1; - uint8_t bit2 : 1; - uint8_t bit3 : 1; - uint8_t bit4 : 1; - uint8_t bit5 : 1; - uint8_t bit6 : 1; - uint8_t bit7 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t bit7 : 1; - uint8_t bit6 : 1; - uint8_t bit5 : 1; - uint8_t bit4 : 1; - uint8_t bit3 : 1; - uint8_t bit2 : 1; - uint8_t bit1 : 1; - uint8_t bit0 : 1; -#endif /* DRV_BYTE_ORDER */ -} bitwise_t; - -#define PROPERTY_DISABLE (0U) -#define PROPERTY_ENABLE (1U) - -/** @addtogroup Interfaces_Functions - * @brief This section provide a set of functions used to read and - * write a generic register of the device. - * MANDATORY: return 0 -> no Error. - * @{ - * - */ - -typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); -typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); -typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); - -typedef struct -{ - /** Component mandatory fields **/ - stmdev_write_ptr write_reg; - stmdev_read_ptr read_reg; - /** Component optional fields **/ - stmdev_mdelay_ptr mdelay; - /** Customizable optional pointer **/ - void *handle; -} stmdev_ctx_t; - -/** - * @} - * - */ - -#endif /* MEMS_SHARED_TYPES */ - -#ifndef MEMS_UCF_SHARED_TYPES -#define MEMS_UCF_SHARED_TYPES - -/** @defgroup Generic address-data structure definition - * @brief This structure is useful to load a predefined configuration - * of a sensor. - * You can create a sensor configuration by your own or using - * Unico / Unicleo tools available on STMicroelectronics - * web site. - * - * @{ - * - */ - -typedef struct -{ - uint8_t address; - uint8_t data; -} ucf_line_t; - -/** - * @} - * - */ - -#endif /* MEMS_UCF_SHARED_TYPES */ - -/** - * @} - * - */ - -/** @defgroup L20G20IS_Infos - * @{ - * - */ - -/** Device Identification (Who am I) **/ -#define L20G20IS_ID 0xDAU - -/** - * @} - * - */ - -#define L20G20IS_WHO_AM_I 0x00U -#define L20G20IS_TEMP_OUT_L 0x01U -#define L20G20IS_TEMP_OUT_H 0x02U -#define L20G20IS_OUT_X_L 0x03U -#define L20G20IS_OUT_X_H 0x04U -#define L20G20IS_OUT_Y_L 0x05U -#define L20G20IS_OUT_Y_H 0x06U -#define L20G20IS_DATA_STATUS_OIS 0x0AU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t not_used_01 : 1; - uint8_t yda_ois : 1; - uint8_t xda_ois : 1; - uint8_t xyda_ois : 1; - uint8_t not_used_02 : 1; - uint8_t yor_ois : 1; - uint8_t xor_ois : 1; - uint8_t xyor_ois : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t xyor_ois : 1; - uint8_t xor_ois : 1; - uint8_t yor_ois : 1; - uint8_t not_used_02 : 1; - uint8_t xyda_ois : 1; - uint8_t xda_ois : 1; - uint8_t yda_ois : 1; - uint8_t not_used_01 : 1; -#endif /* DRV_BYTE_ORDER */ -} l20g20is_data_status_ois_t; - -#define L20G20IS_CTRL1_OIS 0x0BU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t pw : 2; - uint8_t orient : 1; - uint8_t odu : 1; - uint8_t sim : 1; - uint8_t ble : 1; - uint8_t dr_pulsed : 1; - uint8_t boot : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t boot : 1; - uint8_t dr_pulsed : 1; - uint8_t ble : 1; - uint8_t sim : 1; - uint8_t odu : 1; - uint8_t orient : 1; - uint8_t pw : 2; -#endif /* DRV_BYTE_ORDER */ -} l20g20is_ctrl1_ois_t; - -#define L20G20IS_CTRL2_OIS 0x0CU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t hpf : 1; - uint8_t sw_rst : 1; - uint8_t hp_rst : 1; - uint8_t not_used_01 : 1; - uint8_t lpf_bw : 2; - uint8_t signy : 1; - uint8_t signx : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t signx : 1; - uint8_t signy : 1; - uint8_t lpf_bw : 2; - uint8_t not_used_01 : 1; - uint8_t hp_rst : 1; - uint8_t sw_rst : 1; - uint8_t hpf : 1; -#endif /* DRV_BYTE_ORDER */ -} l20g20is_ctrl2_ois_t; - -#define L20G20IS_CTRL3_OIS 0x0DU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t lpf_bw : 1; - uint8_t h_l_active : 1; - uint8_t not_used_01 : 1; - uint8_t st_en : 1; - uint8_t st_sign : 1; - uint8_t not_used_02 : 3; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_02 : 3; - uint8_t st_sign : 1; - uint8_t st_en : 1; - uint8_t not_used_01 : 1; - uint8_t h_l_active : 1; - uint8_t lpf_bw : 1; -#endif /* DRV_BYTE_ORDER */ -} l20g20is_ctrl3_ois_t; - -#define L20G20IS_CTRL4_OIS 0x0EU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t not_used_01 : 1; - uint8_t drdy_od : 1; - uint8_t temp_data_on_drdy : 1; - uint8_t not_used_02 : 1; - uint8_t drdy_en : 1; - uint8_t not_used_03 : 3; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_03 : 3; - uint8_t drdy_en : 1; - uint8_t not_used_02 : 1; - uint8_t temp_data_on_drdy : 1; - uint8_t drdy_od : 1; - uint8_t not_used_01 : 1; -#endif /* DRV_BYTE_ORDER */ -} l20g20is_ctrl4_ois_t; - -#define L20G20IS_OFF_X 0x0FU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t offx : 7; - uint8_t not_used_01 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 1; - uint8_t offx : 7; -#endif /* DRV_BYTE_ORDER */ -} l20g20is_off_x_t; - -#define L20G20IS_OFF_Y 0x10U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t offy : 7; - uint8_t not_used_01 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 1; - uint8_t offy : 7; -#endif /* DRV_BYTE_ORDER */ -} l20g20is_off_y_t; - -#define L20G20IS_OIS_CFG_REG 0x1FU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t hpf_bw : 2; - uint8_t not_used_01 : 1; - uint8_t fs_sel : 1; - uint8_t not_used_02 : 4; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_02 : 4; - uint8_t fs_sel : 1; - uint8_t not_used_01 : 1; - uint8_t hpf_bw : 2; -#endif /* DRV_BYTE_ORDER */ -} l20g20is_ois_cfg_reg_t; - -/** - * @defgroup L20G20IS_Register_Union - * @brief This union group all the registers having a bit-field - * description. - * This union is useful but it's not needed by the driver. - * - * REMOVING this union you are compliant with: - * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " - * - * @{ - * - */ - -typedef union -{ - l20g20is_data_status_ois_t data_status_ois; - l20g20is_ctrl1_ois_t ctrl1_ois; - l20g20is_ctrl2_ois_t ctrl2_ois; - l20g20is_ctrl3_ois_t ctrl3_ois; - l20g20is_ctrl4_ois_t ctrl4_ois; - l20g20is_off_x_t off_x; - l20g20is_off_y_t off_y; - l20g20is_ois_cfg_reg_t ois_cfg_reg; - bitwise_t bitwise; - uint8_t byte; -} l20g20is_reg_t; - -/** - * @} - * - */ - -#ifndef __weak -#define __weak __attribute__((weak)) -#endif /* __weak */ - -/* - * These are the basic platform dependent I/O routines to read - * and write device registers connected on a standard bus. - * The driver keeps offering a default implementation based on function - * pointers to read/write routines for backward compatibility. - * The __weak directive allows the final application to overwrite - * them with a custom implementation. - */ - -int32_t l20g20is_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len); -int32_t l20g20is_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len); - -float_t l20g20is_from_fs100dps_to_mdps(int16_t lsb); -float_t l20g20is_from_fs200dps_to_mdps(int16_t lsb); - -float_t l20g20is_from_lsb_to_celsius(int16_t lsb); - -int32_t l20g20is_gy_flag_data_ready_get(stmdev_ctx_t *ctx, - uint8_t *val); - -typedef enum -{ - L20G20IS_GY_OFF = 0, - L20G20IS_GY_SLEEP = 2, - L20G20IS_GY_9k33Hz = 3, -} l20g20is_gy_data_rate_t; -int32_t l20g20is_gy_data_rate_set(stmdev_ctx_t *ctx, - l20g20is_gy_data_rate_t val); -int32_t l20g20is_gy_data_rate_get(stmdev_ctx_t *ctx, - l20g20is_gy_data_rate_t *val); - -typedef struct -{ - uint8_t orient : 1; - uint8_t signy : 1; - uint8_t signx : 1; -} l20g20is_gy_orient_t; -int32_t l20g20is_gy_orient_set(stmdev_ctx_t *ctx, - l20g20is_gy_orient_t val); -int32_t l20g20is_gy_orient_get(stmdev_ctx_t *ctx, - l20g20is_gy_orient_t *val); - -int32_t l20g20is_block_data_update_set(stmdev_ctx_t *ctx, - uint8_t val); -int32_t l20g20is_block_data_update_get(stmdev_ctx_t *ctx, - uint8_t *val); - -typedef struct -{ - uint8_t offx : 7; - uint8_t offy : 7; -} l20g20is_off_t; -int32_t l20g20is_angular_rate_offset_set(stmdev_ctx_t *ctx, - l20g20is_off_t val); -int32_t l20g20is_angular_rate_offset_get(stmdev_ctx_t *ctx, - l20g20is_off_t *val); - -typedef enum -{ - L20G20IS_100dps = 0, - L20G20IS_200dps = 1, -} l20g20is_gy_fs_t; -int32_t l20g20is_gy_full_scale_set(stmdev_ctx_t *ctx, - l20g20is_gy_fs_t val); -int32_t l20g20is_gy_full_scale_get(stmdev_ctx_t *ctx, - l20g20is_gy_fs_t *val); - -int32_t l20g20is_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); - -int32_t l20g20is_angular_rate_raw_get(stmdev_ctx_t *ctx, - int16_t *val); - -int32_t l20g20is_dev_id_get(stmdev_ctx_t *ctx, uint8_t *buff); - -typedef struct -{ - uint8_t xyda_ois : 1; -} l20g20is_dev_status_t; -int32_t l20g20is_dev_status_get(stmdev_ctx_t *ctx, - l20g20is_dev_status_t *val); - -typedef enum -{ - L20G20IS_LSB_LOW_ADDRESS = 0, - L20G20IS_MSB_LOW_ADDRESS = 1, -} l20g20is_ble_t; -int32_t l20g20is_dev_data_format_set(stmdev_ctx_t *ctx, - l20g20is_ble_t val); -int32_t l20g20is_dev_data_format_get(stmdev_ctx_t *ctx, - l20g20is_ble_t *val); - -int32_t l20g20is_dev_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t l20g20is_dev_boot_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t l20g20is_dev_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t l20g20is_dev_reset_get(stmdev_ctx_t *ctx, uint8_t *val); - -typedef enum -{ - L20G20IS_HPF_BYPASS = 0x00, - L20G20IS_HPF_BW_23mHz = 0x80, - L20G20IS_HPF_BW_91mHz = 0x81, - L20G20IS_HPF_BW_324mHz = 0x82, - L20G20IS_HPF_BW_1Hz457 = 0x83, -} l20g20is_gy_hp_bw_t; -int32_t l20g20is_gy_filter_hp_bandwidth_set(stmdev_ctx_t *ctx, - l20g20is_gy_hp_bw_t val); -int32_t l20g20is_gy_filter_hp_bandwidth_get(stmdev_ctx_t *ctx, - l20g20is_gy_hp_bw_t *val); - -int32_t l20g20is_gy_filter_hp_reset_set(stmdev_ctx_t *ctx, - uint8_t val); -int32_t l20g20is_gy_filter_hp_reset_get(stmdev_ctx_t *ctx, - uint8_t *val); - -typedef enum -{ - L20G20IS_LPF_BW_290Hz = 0x00, - L20G20IS_LPF_BW_210Hz = 0x01, - L20G20IS_LPF_BW_160Hz = 0x02, - L20G20IS_LPF_BW_450Hz = 0x03, - L20G20IS_LPF_BW_1150Hz = 0x04, -} l20g20is_gy_lp_bw_t; -int32_t l20g20is_gy_filter_lp_bandwidth_set(stmdev_ctx_t *ctx, - l20g20is_gy_lp_bw_t val); -int32_t l20g20is_gy_filter_lp_bandwidth_get(stmdev_ctx_t *ctx, - l20g20is_gy_lp_bw_t *val); - -typedef enum -{ - L20G20IS_SPI_4_WIRE = 0, - L20G20IS_SPI_3_WIRE = 1, -} l20g20is_sim_t; -int32_t l20g20is_spi_mode_set(stmdev_ctx_t *ctx, l20g20is_sim_t val); -int32_t l20g20is_spi_mode_get(stmdev_ctx_t *ctx, l20g20is_sim_t *val); - -typedef enum -{ - L20G20IS_INT_PULSED = 1, - L20G20IS_INT_LATCHED = 0, -} l20g20is_lir_t; -int32_t l20g20is_pin_notification_set(stmdev_ctx_t *ctx, - l20g20is_lir_t val); -int32_t l20g20is_pin_notification_get(stmdev_ctx_t *ctx, - l20g20is_lir_t *val); - -typedef enum -{ - L20G20IS_ACTIVE_HIGH = 0, - L20G20IS_ACTIVE_LOW = 1, -} l20g20is_pin_pol_t; -int32_t l20g20is_pin_polarity_set(stmdev_ctx_t *ctx, - l20g20is_pin_pol_t val); -int32_t l20g20is_pin_polarity_get(stmdev_ctx_t *ctx, - l20g20is_pin_pol_t *val); - -typedef enum -{ - L20G20IS_PUSH_PULL = 0, - L20G20IS_OPEN_DRAIN = 1, -} l20g20is_pp_od_t; -int32_t l20g20is_pin_mode_set(stmdev_ctx_t *ctx, - l20g20is_pp_od_t val); -int32_t l20g20is_pin_mode_get(stmdev_ctx_t *ctx, - l20g20is_pp_od_t *val); - -typedef struct -{ - uint8_t temp_data_on_drdy : 1; - uint8_t drdy_en : 1; -} l20g20is_pin_drdy_route_t; -int32_t l20g20is_pin_drdy_route_set(stmdev_ctx_t *ctx, - l20g20is_pin_drdy_route_t val); -int32_t l20g20is_pin_drdy_route_get(stmdev_ctx_t *ctx, - l20g20is_pin_drdy_route_t *val); - -typedef enum -{ - L20G20IS_ST_DISABLE = 0x00, - L20G20IS_ST_POSITIVE = 0x02, - L20G20IS_ST_NEGATIVE = 0x03, -} l20g20is_gy_self_test_t; -int32_t l20g20is_gy_self_test_set(stmdev_ctx_t *ctx, - l20g20is_gy_self_test_t val); -int32_t l20g20is_gy_self_test_get(stmdev_ctx_t *ctx, - l20g20is_gy_self_test_t *val); - -/** - *@} - * - */ - -#ifdef __cplusplus -} -#endif - -#endif /* L20G20IS_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.c b/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.c index 9194d9b9..ed46a14e 100644 --- a/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.c +++ b/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.c @@ -46,11 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak l3gd20h_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak l3gd20h_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -66,11 +72,17 @@ int32_t __weak l3gd20h_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak l3gd20h_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak l3gd20h_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -127,7 +139,7 @@ float_t l3gd20h_from_lsb_to_celsius(int16_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_axis_set(stmdev_ctx_t *ctx, l3gd20h_gy_axis_t val) +int32_t l3gd20h_gy_axis_set(const stmdev_ctx_t *ctx, l3gd20h_gy_axis_t val) { l3gd20h_ctrl1_t ctrl1; int32_t ret; @@ -152,7 +164,7 @@ int32_t l3gd20h_gy_axis_set(stmdev_ctx_t *ctx, l3gd20h_gy_axis_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_axis_get(stmdev_ctx_t *ctx, l3gd20h_gy_axis_t *val) +int32_t l3gd20h_gy_axis_get(const stmdev_ctx_t *ctx, l3gd20h_gy_axis_t *val) { l3gd20h_ctrl1_t ctrl1; int32_t ret; @@ -172,7 +184,7 @@ int32_t l3gd20h_gy_axis_get(stmdev_ctx_t *ctx, l3gd20h_gy_axis_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_data_rate_set(const stmdev_ctx_t *ctx, l3gd20h_gy_data_rate_t val) { l3gd20h_low_odr_t low_odr; @@ -209,7 +221,7 @@ int32_t l3gd20h_gy_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_data_rate_get(const stmdev_ctx_t *ctx, l3gd20h_gy_data_rate_t *val) { l3gd20h_low_odr_t low_odr; @@ -272,7 +284,7 @@ int32_t l3gd20h_gy_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_full_scale_set(const stmdev_ctx_t *ctx, l3gd20h_gy_fs_t val) { l3gd20h_ctrl4_t ctrl4; @@ -296,7 +308,7 @@ int32_t l3gd20h_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_full_scale_get(const stmdev_ctx_t *ctx, l3gd20h_gy_fs_t *val) { l3gd20h_ctrl4_t ctrl4; @@ -328,7 +340,7 @@ int32_t l3gd20h_gy_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t l3gd20h_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { l3gd20h_ctrl4_t ctrl4; int32_t ret; @@ -351,7 +363,7 @@ int32_t l3gd20h_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t l3gd20h_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { l3gd20h_ctrl4_t ctrl4; int32_t ret; @@ -368,7 +380,7 @@ int32_t l3gd20h_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { l3gd20h_status_t status; @@ -400,7 +412,7 @@ int32_t l3gd20h_gy_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t l3gd20h_temperature_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_OUT_TEMP, buff, 1); @@ -417,7 +429,7 @@ int32_t l3gd20h_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t l3gd20h_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -452,7 +464,7 @@ int32_t l3gd20h_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_dev_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t l3gd20h_dev_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; ret = l3gd20h_read_reg(ctx, L3GD20H_WHO_AM_I, buff, 1); @@ -468,7 +480,7 @@ int32_t l3gd20h_dev_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_dev_data_format_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_dev_data_format_set(const stmdev_ctx_t *ctx, l3gd20h_ble_t val) { l3gd20h_ctrl4_t ctrl4; @@ -492,7 +504,7 @@ int32_t l3gd20h_dev_data_format_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_dev_data_format_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_dev_data_format_get(const stmdev_ctx_t *ctx, l3gd20h_ble_t *val) { l3gd20h_ctrl4_t ctrl4; @@ -525,7 +537,7 @@ int32_t l3gd20h_dev_data_format_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_dev_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t l3gd20h_dev_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { l3gd20h_ctrl5_t ctrl5; int32_t ret; @@ -548,7 +560,7 @@ int32_t l3gd20h_dev_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_dev_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t l3gd20h_dev_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { l3gd20h_ctrl5_t ctrl5; int32_t ret; @@ -565,7 +577,7 @@ int32_t l3gd20h_dev_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_dev_status_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_dev_status_get(const stmdev_ctx_t *ctx, l3gd20h_status_reg_t *val) { l3gd20h_status_t status; @@ -591,7 +603,7 @@ int32_t l3gd20h_dev_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_dev_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t l3gd20h_dev_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { l3gd20h_low_odr_t low_odr; int32_t ret; @@ -614,7 +626,7 @@ int32_t l3gd20h_dev_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_dev_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t l3gd20h_dev_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { l3gd20h_low_odr_t low_odr; int32_t ret; @@ -645,7 +657,7 @@ int32_t l3gd20h_dev_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_filter_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_filter_lp_bandwidth_set(const stmdev_ctx_t *ctx, l3gd20h_lpbw_t val) { l3gd20h_ctrl1_t ctrl1; @@ -669,7 +681,7 @@ int32_t l3gd20h_gy_filter_lp_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_filter_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_filter_lp_bandwidth_get(const stmdev_ctx_t *ctx, l3gd20h_lpbw_t *val) { l3gd20h_low_odr_t low_odr; @@ -748,7 +760,7 @@ int32_t l3gd20h_gy_filter_lp_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_filter_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_filter_hp_bandwidth_set(const stmdev_ctx_t *ctx, l3gd20h_gy_hp_bw_t val) { l3gd20h_ctrl2_t ctrl2; @@ -773,7 +785,7 @@ int32_t l3gd20h_gy_filter_hp_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_filter_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_filter_hp_bandwidth_get(const stmdev_ctx_t *ctx, l3gd20h_gy_hp_bw_t *val) { l3gd20h_ctrl2_t ctrl2; @@ -851,7 +863,7 @@ int32_t l3gd20h_gy_filter_hp_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_filter_out_path_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_filter_out_path_set(const stmdev_ctx_t *ctx, l3gd20h_gy_out_path_t val) { l3gd20h_ctrl5_t ctrl5; @@ -876,7 +888,7 @@ int32_t l3gd20h_gy_filter_out_path_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_filter_out_path_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_filter_out_path_get(const stmdev_ctx_t *ctx, l3gd20h_gy_out_path_t *val) { l3gd20h_ctrl5_t ctrl5; @@ -917,7 +929,7 @@ int32_t l3gd20h_gy_filter_out_path_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_filter_int_path_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_filter_int_path_set(const stmdev_ctx_t *ctx, l3gd20h_gy_int_path_t val) { l3gd20h_ctrl5_t ctrl5; @@ -942,7 +954,7 @@ int32_t l3gd20h_gy_filter_int_path_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_filter_int_path_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_filter_int_path_get(const stmdev_ctx_t *ctx, l3gd20h_gy_int_path_t *val) { l3gd20h_ctrl5_t ctrl5; @@ -984,7 +996,7 @@ int32_t l3gd20h_gy_filter_int_path_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_filter_reference_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_filter_reference_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1001,7 +1013,7 @@ int32_t l3gd20h_gy_filter_reference_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_filter_reference_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_filter_reference_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1031,7 +1043,7 @@ int32_t l3gd20h_gy_filter_reference_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_spi_mode_set(stmdev_ctx_t *ctx, l3gd20h_sim_t val) +int32_t l3gd20h_spi_mode_set(const stmdev_ctx_t *ctx, l3gd20h_sim_t val) { l3gd20h_ctrl4_t ctrl4; int32_t ret; @@ -1054,7 +1066,7 @@ int32_t l3gd20h_spi_mode_set(stmdev_ctx_t *ctx, l3gd20h_sim_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_spi_mode_get(stmdev_ctx_t *ctx, l3gd20h_sim_t *val) +int32_t l3gd20h_spi_mode_get(const stmdev_ctx_t *ctx, l3gd20h_sim_t *val) { l3gd20h_ctrl4_t ctrl4; int32_t ret; @@ -1086,7 +1098,7 @@ int32_t l3gd20h_spi_mode_get(stmdev_ctx_t *ctx, l3gd20h_sim_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_i2c_interface_set(const stmdev_ctx_t *ctx, l3gd20h_i2c_dis_t val) { l3gd20h_low_odr_t low_odr; @@ -1110,7 +1122,7 @@ int32_t l3gd20h_i2c_interface_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_i2c_interface_get(const stmdev_ctx_t *ctx, l3gd20h_i2c_dis_t *val) { l3gd20h_low_odr_t low_odr; @@ -1154,7 +1166,7 @@ int32_t l3gd20h_i2c_interface_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_pin_int2_route_set(const stmdev_ctx_t *ctx, l3gd20h_pin_int2_rt_t val) { l3gd20h_ctrl3_t ctrl3; @@ -1181,7 +1193,7 @@ int32_t l3gd20h_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_pin_int2_route_get(const stmdev_ctx_t *ctx, l3gd20h_pin_int2_rt_t *val) { l3gd20h_ctrl3_t ctrl3; @@ -1203,7 +1215,7 @@ int32_t l3gd20h_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_pin_mode_set(stmdev_ctx_t *ctx, l3gd20h_pp_od_t val) +int32_t l3gd20h_pin_mode_set(const stmdev_ctx_t *ctx, l3gd20h_pp_od_t val) { l3gd20h_ctrl3_t ctrl3; int32_t ret; @@ -1226,7 +1238,7 @@ int32_t l3gd20h_pin_mode_set(stmdev_ctx_t *ctx, l3gd20h_pp_od_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_pin_mode_get(stmdev_ctx_t *ctx, l3gd20h_pp_od_t *val) +int32_t l3gd20h_pin_mode_get(const stmdev_ctx_t *ctx, l3gd20h_pp_od_t *val) { l3gd20h_ctrl3_t ctrl3; int32_t ret; @@ -1258,7 +1270,7 @@ int32_t l3gd20h_pin_mode_get(stmdev_ctx_t *ctx, l3gd20h_pp_od_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_pin_polarity_set(const stmdev_ctx_t *ctx, l3gd20h_pin_pol_t val) { l3gd20h_low_odr_t low_odr; @@ -1294,7 +1306,7 @@ int32_t l3gd20h_pin_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_pin_polarity_get(const stmdev_ctx_t *ctx, l3gd20h_pin_pol_t *val) { l3gd20h_ctrl3_t ctrl3; @@ -1327,7 +1339,7 @@ int32_t l3gd20h_pin_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_pin_int1_route_set(const stmdev_ctx_t *ctx, l3gd20h_pin_int1_rt_t val) { l3gd20h_ctrl3_t ctrl3; @@ -1352,7 +1364,7 @@ int32_t l3gd20h_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_pin_int1_route_get(const stmdev_ctx_t *ctx, l3gd20h_pin_int1_rt_t *val) { l3gd20h_ctrl3_t ctrl3; @@ -1372,7 +1384,7 @@ int32_t l3gd20h_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_pin_notification_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_pin_notification_set(const stmdev_ctx_t *ctx, l3gd20h_lir_t val) { l3gd20h_ig_cfg_t ig_cfg; @@ -1396,7 +1408,7 @@ int32_t l3gd20h_pin_notification_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_pin_notification_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_pin_notification_get(const stmdev_ctx_t *ctx, l3gd20h_lir_t *val) { l3gd20h_ig_cfg_t ig_cfg; @@ -1430,7 +1442,7 @@ int32_t l3gd20h_pin_notification_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_pin_logic_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_pin_logic_set(const stmdev_ctx_t *ctx, l3gd20h_pin_logic_t val) { l3gd20h_ig_cfg_t ig_cfg; @@ -1454,7 +1466,7 @@ int32_t l3gd20h_pin_logic_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_pin_logic_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_pin_logic_get(const stmdev_ctx_t *ctx, l3gd20h_pin_logic_t *val) { l3gd20h_ig_cfg_t ig_cfg; @@ -1501,7 +1513,7 @@ int32_t l3gd20h_pin_logic_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_trshld_axis_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_trshld_axis_set(const stmdev_ctx_t *ctx, l3gd20h_gy_trshld_en_t val) { l3gd20h_ig_cfg_t ig_cfg; @@ -1531,7 +1543,7 @@ int32_t l3gd20h_gy_trshld_axis_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_trshld_axis_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_trshld_axis_get(const stmdev_ctx_t *ctx, l3gd20h_gy_trshld_en_t *val) { l3gd20h_ig_cfg_t ig_cfg; @@ -1556,7 +1568,7 @@ int32_t l3gd20h_gy_trshld_axis_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_trshld_src_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_trshld_src_get(const stmdev_ctx_t *ctx, l3gd20h_gy_trshld_src_t *val) { l3gd20h_ig_src_t ig_src; @@ -1581,7 +1593,7 @@ int32_t l3gd20h_gy_trshld_src_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_trshld_x_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t l3gd20h_gy_trshld_x_set(const stmdev_ctx_t *ctx, uint16_t val) { l3gd20h_ig_ths_xl_t ig_ths_xl; l3gd20h_ig_ths_xh_t ig_ths_xh; @@ -1616,7 +1628,7 @@ int32_t l3gd20h_gy_trshld_x_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_trshld_x_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t l3gd20h_gy_trshld_x_get(const stmdev_ctx_t *ctx, uint16_t *val) { l3gd20h_ig_ths_xl_t ig_ths_xl; l3gd20h_ig_ths_xh_t ig_ths_xh; @@ -1641,7 +1653,7 @@ int32_t l3gd20h_gy_trshld_x_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_trshld_mode_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_trshld_mode_set(const stmdev_ctx_t *ctx, l3gd20h_dcrm_g_t val) { l3gd20h_ig_ths_xh_t ig_ths_xh; @@ -1665,7 +1677,7 @@ int32_t l3gd20h_gy_trshld_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_trshld_mode_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_trshld_mode_get(const stmdev_ctx_t *ctx, l3gd20h_dcrm_g_t *val) { l3gd20h_ig_ths_xh_t ig_ths_xh; @@ -1698,7 +1710,7 @@ int32_t l3gd20h_gy_trshld_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_trshld_y_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t l3gd20h_gy_trshld_y_set(const stmdev_ctx_t *ctx, uint16_t val) { l3gd20h_ig_ths_yh_t ig_ths_yh; l3gd20h_ig_ths_yl_t ig_ths_yl; @@ -1733,7 +1745,7 @@ int32_t l3gd20h_gy_trshld_y_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_trshld_y_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t l3gd20h_gy_trshld_y_get(const stmdev_ctx_t *ctx, uint16_t *val) { l3gd20h_ig_ths_yh_t ig_ths_yh; l3gd20h_ig_ths_yl_t ig_ths_yl; @@ -1759,7 +1771,7 @@ int32_t l3gd20h_gy_trshld_y_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_trshld_z_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t l3gd20h_gy_trshld_z_set(const stmdev_ctx_t *ctx, uint16_t val) { l3gd20h_ig_ths_zh_t ig_ths_zh; l3gd20h_ig_ths_zl_t ig_ths_zl; @@ -1794,7 +1806,7 @@ int32_t l3gd20h_gy_trshld_z_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_trshld_z_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t l3gd20h_gy_trshld_z_get(const stmdev_ctx_t *ctx, uint16_t *val) { l3gd20h_ig_ths_zh_t ig_ths_zh; l3gd20h_ig_ths_zl_t ig_ths_zl; @@ -1820,7 +1832,7 @@ int32_t l3gd20h_gy_trshld_z_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_trshld_min_sample_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_trshld_min_sample_set(const stmdev_ctx_t *ctx, uint8_t val) { l3gd20h_ig_duration_t ig_duration; @@ -1857,7 +1869,7 @@ int32_t l3gd20h_gy_trshld_min_sample_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_trshld_min_sample_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_trshld_min_sample_get(const stmdev_ctx_t *ctx, uint8_t *val) { l3gd20h_ig_duration_t ig_duration; @@ -1889,7 +1901,7 @@ int32_t l3gd20h_gy_trshld_min_sample_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t l3gd20h_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) { l3gd20h_ctrl5_t ctrl5; int32_t ret; @@ -1912,7 +1924,7 @@ int32_t l3gd20h_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t l3gd20h_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) { l3gd20h_ctrl5_t ctrl5; int32_t ret; @@ -1929,7 +1941,7 @@ int32_t l3gd20h_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_fifo_mode_set(stmdev_ctx_t *ctx, l3gd20h_fifo_m_t val) +int32_t l3gd20h_fifo_mode_set(const stmdev_ctx_t *ctx, l3gd20h_fifo_m_t val) { l3gd20h_ctrl5_t ctrl5; l3gd20h_fifo_ctrl_t fifo_ctrl; @@ -1964,7 +1976,7 @@ int32_t l3gd20h_fifo_mode_set(stmdev_ctx_t *ctx, l3gd20h_fifo_m_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_fifo_mode_get(const stmdev_ctx_t *ctx, l3gd20h_fifo_m_t *val) { l3gd20h_ctrl5_t ctrl5; @@ -2018,7 +2030,7 @@ int32_t l3gd20h_fifo_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t l3gd20h_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { l3gd20h_fifo_ctrl_t fifo_ctrl; int32_t ret; @@ -2041,7 +2053,7 @@ int32_t l3gd20h_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t l3gd20h_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { l3gd20h_fifo_ctrl_t fifo_ctrl; int32_t ret; @@ -2059,7 +2071,7 @@ int32_t l3gd20h_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_fifo_src_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_fifo_src_get(const stmdev_ctx_t *ctx, l3gd20h_fifo_srs_t *val) { l3gd20h_fifo_src_t fifo_src; @@ -2081,7 +2093,7 @@ int32_t l3gd20h_fifo_src_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t l3gd20h_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) { l3gd20h_fifo_src_t fifo_src; int32_t ret; @@ -2099,7 +2111,7 @@ int32_t l3gd20h_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t l3gd20h_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { l3gd20h_fifo_src_t fifo_src; int32_t ret; @@ -2117,7 +2129,7 @@ int32_t l3gd20h_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t l3gd20h_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { l3gd20h_fifo_src_t fifo_src; int32_t ret; @@ -2147,7 +2159,7 @@ int32_t l3gd20h_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_den_mode_set(stmdev_ctx_t *ctx, l3gd20h_den_md_t val) +int32_t l3gd20h_den_mode_set(const stmdev_ctx_t *ctx, l3gd20h_den_md_t val) { l3gd20h_ctrl2_t ctrl2; l3gd20h_ctrl4_t ctrl4; @@ -2183,7 +2195,7 @@ int32_t l3gd20h_den_mode_set(stmdev_ctx_t *ctx, l3gd20h_den_md_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_den_mode_get(stmdev_ctx_t *ctx, l3gd20h_den_md_t *val) +int32_t l3gd20h_den_mode_get(const stmdev_ctx_t *ctx, l3gd20h_den_md_t *val) { l3gd20h_ctrl2_t ctrl2; l3gd20h_ctrl4_t ctrl4; @@ -2242,7 +2254,7 @@ int32_t l3gd20h_den_mode_get(stmdev_ctx_t *ctx, l3gd20h_den_md_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_self_test_set(stmdev_ctx_t *ctx, l3gd20h_st_t val) +int32_t l3gd20h_gy_self_test_set(const stmdev_ctx_t *ctx, l3gd20h_st_t val) { l3gd20h_ctrl4_t ctrl4; int32_t ret; @@ -2265,7 +2277,7 @@ int32_t l3gd20h_gy_self_test_set(stmdev_ctx_t *ctx, l3gd20h_st_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t l3gd20h_gy_self_test_get(stmdev_ctx_t *ctx, l3gd20h_st_t *val) +int32_t l3gd20h_gy_self_test_get(const stmdev_ctx_t *ctx, l3gd20h_st_t *val) { l3gd20h_ctrl4_t ctrl4; int32_t ret; diff --git a/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.h b/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.h index ce70da35..0d98c12c 100644 --- a/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.h +++ b/sensor/stmemsc/l3gd20h_STdC/driver/l3gd20h_reg.h @@ -531,10 +531,10 @@ typedef union * them with a custom implementation. */ -int32_t l3gd20h_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t l3gd20h_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t l3gd20h_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t l3gd20h_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -550,8 +550,8 @@ typedef struct uint8_t yen : 1; uint8_t zen : 1; } l3gd20h_gy_axis_t; -int32_t l3gd20h_gy_axis_set(stmdev_ctx_t *ctx, l3gd20h_gy_axis_t val); -int32_t l3gd20h_gy_axis_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_axis_set(const stmdev_ctx_t *ctx, l3gd20h_gy_axis_t val); +int32_t l3gd20h_gy_axis_get(const stmdev_ctx_t *ctx, l3gd20h_gy_axis_t *val); typedef enum @@ -565,9 +565,9 @@ typedef enum L3GD20H_400Hz = 0x82, L3GD20H_800Hz = 0x83, } l3gd20h_gy_data_rate_t; -int32_t l3gd20h_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_data_rate_set(const stmdev_ctx_t *ctx, l3gd20h_gy_data_rate_t val); -int32_t l3gd20h_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_data_rate_get(const stmdev_ctx_t *ctx, l3gd20h_gy_data_rate_t *val); @@ -577,36 +577,36 @@ typedef enum L3GD20H_500dps = 0x01, L3GD20H_2000dps = 0x02, } l3gd20h_gy_fs_t; -int32_t l3gd20h_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_full_scale_set(const stmdev_ctx_t *ctx, l3gd20h_gy_fs_t val); -int32_t l3gd20h_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_full_scale_get(const stmdev_ctx_t *ctx, l3gd20h_gy_fs_t *val); -int32_t l3gd20h_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t l3gd20h_block_data_update_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t l3gd20h_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t l3gd20h_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t l3gd20h_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t l3gd20h_temperature_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t l3gd20h_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t l3gd20h_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t l3gd20h_dev_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t l3gd20h_dev_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); typedef enum { L3GD20H_LSB_LOW_ADDRESS = 0, L3GD20H_MSB_LOW_ADDRESS = 1, } l3gd20h_ble_t; -int32_t l3gd20h_dev_data_format_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_dev_data_format_set(const stmdev_ctx_t *ctx, l3gd20h_ble_t val); -int32_t l3gd20h_dev_data_format_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_dev_data_format_get(const stmdev_ctx_t *ctx, l3gd20h_ble_t *val); -int32_t l3gd20h_dev_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t l3gd20h_dev_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t l3gd20h_dev_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t l3gd20h_dev_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -619,11 +619,11 @@ typedef struct uint8_t zor : 1; uint8_t zyxor : 1; } l3gd20h_status_reg_t; -int32_t l3gd20h_dev_status_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_dev_status_get(const stmdev_ctx_t *ctx, l3gd20h_status_reg_t *val); -int32_t l3gd20h_dev_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t l3gd20h_dev_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t l3gd20h_dev_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t l3gd20h_dev_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -640,9 +640,9 @@ typedef enum L3GD20H_35Hz_USE_ODR_800Hz = 0x31, L3GD20H_100Hz_USE_ODR_800Hz = 0x33, } l3gd20h_lpbw_t; -int32_t l3gd20h_gy_filter_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_filter_lp_bandwidth_set(const stmdev_ctx_t *ctx, l3gd20h_lpbw_t val); -int32_t l3gd20h_gy_filter_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_filter_lp_bandwidth_get(const stmdev_ctx_t *ctx, l3gd20h_lpbw_t *val); typedef enum @@ -660,9 +660,9 @@ typedef enum L3GD20H_AUTORESET_STRONG = 0x32, L3GD20H_AUTORESET_EXTREME = 0x33, } l3gd20h_gy_hp_bw_t; -int32_t l3gd20h_gy_filter_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_filter_hp_bandwidth_set(const stmdev_ctx_t *ctx, l3gd20h_gy_hp_bw_t val); -int32_t l3gd20h_gy_filter_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_filter_hp_bandwidth_get(const stmdev_ctx_t *ctx, l3gd20h_gy_hp_bw_t *val); typedef enum @@ -672,9 +672,9 @@ typedef enum L3GD20H_LPF1_LPF2_OUT = 0x02, L3GD20H_LPF1_HPF_LPF2_OUT = 0x12, } l3gd20h_gy_out_path_t; -int32_t l3gd20h_gy_filter_out_path_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_filter_out_path_set(const stmdev_ctx_t *ctx, l3gd20h_gy_out_path_t val); -int32_t l3gd20h_gy_filter_out_path_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_filter_out_path_get(const stmdev_ctx_t *ctx, l3gd20h_gy_out_path_t *val); typedef enum { @@ -683,14 +683,14 @@ typedef enum L3GD20H_LPF1_LPF2_INT = 0x02, L3GD20H_LPF1_HPF_LPF2_INT = 0x12, } l3gd20h_gy_int_path_t; -int32_t l3gd20h_gy_filter_int_path_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_filter_int_path_set(const stmdev_ctx_t *ctx, l3gd20h_gy_int_path_t val); -int32_t l3gd20h_gy_filter_int_path_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_filter_int_path_get(const stmdev_ctx_t *ctx, l3gd20h_gy_int_path_t *val); -int32_t l3gd20h_gy_filter_reference_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_filter_reference_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t l3gd20h_gy_filter_reference_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_filter_reference_get(const stmdev_ctx_t *ctx, uint8_t *buff); typedef enum @@ -698,17 +698,17 @@ typedef enum L3GD20H_SPI_4_WIRE = 0, L3GD20H_SPI_3_WIRE = 1, } l3gd20h_sim_t; -int32_t l3gd20h_spi_mode_set(stmdev_ctx_t *ctx, l3gd20h_sim_t val); -int32_t l3gd20h_spi_mode_get(stmdev_ctx_t *ctx, l3gd20h_sim_t *val); +int32_t l3gd20h_spi_mode_set(const stmdev_ctx_t *ctx, l3gd20h_sim_t val); +int32_t l3gd20h_spi_mode_get(const stmdev_ctx_t *ctx, l3gd20h_sim_t *val); typedef enum { L3GD20H_I2C_ENABLE = 0, L3GD20H_I2C_DISABLE = 1, } l3gd20h_i2c_dis_t; -int32_t l3gd20h_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_i2c_interface_set(const stmdev_ctx_t *ctx, l3gd20h_i2c_dis_t val); -int32_t l3gd20h_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_i2c_interface_get(const stmdev_ctx_t *ctx, l3gd20h_i2c_dis_t *val); typedef struct @@ -718,9 +718,9 @@ typedef struct uint8_t int2_fth : 1; uint8_t int2_drdy : 1; } l3gd20h_pin_int2_rt_t; -int32_t l3gd20h_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_pin_int2_route_set(const stmdev_ctx_t *ctx, l3gd20h_pin_int2_rt_t val); -int32_t l3gd20h_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_pin_int2_route_get(const stmdev_ctx_t *ctx, l3gd20h_pin_int2_rt_t *val); typedef enum @@ -728,17 +728,17 @@ typedef enum L3GD20H_PUSH_PULL = 0, L3GD20H_OPEN_DRAIN = 1, } l3gd20h_pp_od_t; -int32_t l3gd20h_pin_mode_set(stmdev_ctx_t *ctx, l3gd20h_pp_od_t val); -int32_t l3gd20h_pin_mode_get(stmdev_ctx_t *ctx, l3gd20h_pp_od_t *val); +int32_t l3gd20h_pin_mode_set(const stmdev_ctx_t *ctx, l3gd20h_pp_od_t val); +int32_t l3gd20h_pin_mode_get(const stmdev_ctx_t *ctx, l3gd20h_pp_od_t *val); typedef enum { L3GD20H_ACTIVE_HIGH = 0, L3GD20H_ACTIVE_LOW = 1, } l3gd20h_pin_pol_t; -int32_t l3gd20h_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_pin_polarity_set(const stmdev_ctx_t *ctx, l3gd20h_pin_pol_t val); -int32_t l3gd20h_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_pin_polarity_get(const stmdev_ctx_t *ctx, l3gd20h_pin_pol_t *val); typedef struct @@ -746,9 +746,9 @@ typedef struct uint8_t int1_boot : 1; uint8_t int1_ig : 1; } l3gd20h_pin_int1_rt_t; -int32_t l3gd20h_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_pin_int1_route_set(const stmdev_ctx_t *ctx, l3gd20h_pin_int1_rt_t val); -int32_t l3gd20h_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_pin_int1_route_get(const stmdev_ctx_t *ctx, l3gd20h_pin_int1_rt_t *val); typedef enum @@ -756,18 +756,18 @@ typedef enum L3GD20H_INT_PULSED = 0, L3GD20H_INT_LATCHED = 1, } l3gd20h_lir_t; -int32_t l3gd20h_pin_notification_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_pin_notification_set(const stmdev_ctx_t *ctx, l3gd20h_lir_t val); -int32_t l3gd20h_pin_notification_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_pin_notification_get(const stmdev_ctx_t *ctx, l3gd20h_lir_t *val); typedef enum { L3GD20H_LOGIC_OR = 0, L3GD20H_LOGIC_AND = 1, } l3gd20h_pin_logic_t; -int32_t l3gd20h_pin_logic_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_pin_logic_set(const stmdev_ctx_t *ctx, l3gd20h_pin_logic_t val); -int32_t l3gd20h_pin_logic_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_pin_logic_get(const stmdev_ctx_t *ctx, l3gd20h_pin_logic_t *val); typedef struct @@ -779,9 +779,9 @@ typedef struct uint8_t zlie : 1; uint8_t zhie : 1; } l3gd20h_gy_trshld_en_t; -int32_t l3gd20h_gy_trshld_axis_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_trshld_axis_set(const stmdev_ctx_t *ctx, l3gd20h_gy_trshld_en_t val); -int32_t l3gd20h_gy_trshld_axis_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_trshld_axis_get(const stmdev_ctx_t *ctx, l3gd20h_gy_trshld_en_t *val); typedef struct @@ -794,35 +794,35 @@ typedef struct uint8_t zh : 1; uint8_t ia : 1; } l3gd20h_gy_trshld_src_t; -int32_t l3gd20h_gy_trshld_src_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_trshld_src_get(const stmdev_ctx_t *ctx, l3gd20h_gy_trshld_src_t *val); -int32_t l3gd20h_gy_trshld_x_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t l3gd20h_gy_trshld_x_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t l3gd20h_gy_trshld_x_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t l3gd20h_gy_trshld_x_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum { L3GD20H_RESET_MODE = 0x00, L3GD20H_DECREMENT_MODE = 0x01, } l3gd20h_dcrm_g_t; -int32_t l3gd20h_gy_trshld_mode_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_trshld_mode_set(const stmdev_ctx_t *ctx, l3gd20h_dcrm_g_t val); -int32_t l3gd20h_gy_trshld_mode_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_trshld_mode_get(const stmdev_ctx_t *ctx, l3gd20h_dcrm_g_t *val); -int32_t l3gd20h_gy_trshld_y_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t l3gd20h_gy_trshld_y_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t l3gd20h_gy_trshld_y_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t l3gd20h_gy_trshld_y_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t l3gd20h_gy_trshld_z_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t l3gd20h_gy_trshld_z_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t l3gd20h_gy_trshld_z_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t l3gd20h_gy_trshld_z_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t l3gd20h_gy_trshld_min_sample_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_trshld_min_sample_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t l3gd20h_gy_trshld_min_sample_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_trshld_min_sample_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t l3gd20h_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t l3gd20h_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t l3gd20h_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t l3gd20h_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -834,13 +834,13 @@ typedef enum L3GD20H_DYNAMIC_STREAM_MODE = 0x16, L3GD20H_BYPASS_TO_FIFO_MODE = 0x17, } l3gd20h_fifo_m_t; -int32_t l3gd20h_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t l3gd20h_fifo_mode_set(const stmdev_ctx_t *ctx, l3gd20h_fifo_m_t val); -int32_t l3gd20h_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_fifo_mode_get(const stmdev_ctx_t *ctx, l3gd20h_fifo_m_t *val); -int32_t l3gd20h_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t l3gd20h_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t l3gd20h_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t l3gd20h_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -849,14 +849,14 @@ typedef struct uint8_t ovrn : 1; uint8_t fth : 1; } l3gd20h_fifo_srs_t; -int32_t l3gd20h_fifo_src_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_fifo_src_get(const stmdev_ctx_t *ctx, l3gd20h_fifo_srs_t *val); -int32_t l3gd20h_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t l3gd20h_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t l3gd20h_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t l3gd20h_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t l3gd20h_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t l3gd20h_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -865,8 +865,8 @@ typedef enum L3GD20H_DEN_ON_EDGE_TRIGGER = 0x02, L3GD20H_DEN_IMPULSE_TRIGGER = 0x05, } l3gd20h_den_md_t; -int32_t l3gd20h_den_mode_set(stmdev_ctx_t *ctx, l3gd20h_den_md_t val); -int32_t l3gd20h_den_mode_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_den_mode_set(const stmdev_ctx_t *ctx, l3gd20h_den_md_t val); +int32_t l3gd20h_den_mode_get(const stmdev_ctx_t *ctx, l3gd20h_den_md_t *val); typedef enum @@ -875,8 +875,8 @@ typedef enum L3GD20H_ST_POSITIVE = 0x01, L3GD20H_ST_NEGATIVE = 0x03, } l3gd20h_st_t; -int32_t l3gd20h_gy_self_test_set(stmdev_ctx_t *ctx, l3gd20h_st_t val); -int32_t l3gd20h_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t l3gd20h_gy_self_test_set(const stmdev_ctx_t *ctx, l3gd20h_st_t val); +int32_t l3gd20h_gy_self_test_get(const stmdev_ctx_t *ctx, l3gd20h_st_t *val); /** diff --git a/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.c b/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.c index 007f9399..4e996e4e 100644 --- a/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.c +++ b/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t __weak lis25ba_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lis25ba_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lis25ba_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t __weak lis25ba_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lis25ba_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -136,7 +146,7 @@ float_t lis25ba_from_raw_to_mg(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis25ba_id_get(stmdev_ctx_t *ctx, lis25ba_id_t *val) +int32_t lis25ba_id_get(const stmdev_ctx_t *ctx, lis25ba_id_t *val) { int32_t ret = 0; @@ -157,7 +167,7 @@ int32_t lis25ba_id_get(stmdev_ctx_t *ctx, lis25ba_id_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis25ba_bus_mode_set(stmdev_ctx_t *ctx, +int32_t lis25ba_bus_mode_set(const stmdev_ctx_t *ctx, lis25ba_bus_mode_t *val) { lis25ba_tdm_ctrl_reg_t tdm_ctrl_reg; @@ -207,7 +217,7 @@ int32_t lis25ba_bus_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis25ba_bus_mode_get(stmdev_ctx_t *ctx, +int32_t lis25ba_bus_mode_get(const stmdev_ctx_t *ctx, lis25ba_bus_mode_t *val) { lis25ba_tdm_ctrl_reg_t tdm_ctrl_reg; @@ -246,7 +256,7 @@ int32_t lis25ba_bus_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis25ba_mode_set(stmdev_ctx_t *ctx, lis25ba_md_t *val) +int32_t lis25ba_mode_set(const stmdev_ctx_t *ctx, lis25ba_md_t *val) { lis25ba_axes_ctrl_reg_t axes_ctrl_reg; lis25ba_tdm_ctrl_reg_t tdm_ctrl_reg; @@ -297,7 +307,7 @@ int32_t lis25ba_mode_set(stmdev_ctx_t *ctx, lis25ba_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis25ba_mode_get(stmdev_ctx_t *ctx, lis25ba_md_t *val) +int32_t lis25ba_mode_get(const stmdev_ctx_t *ctx, lis25ba_md_t *val) { lis25ba_axes_ctrl_reg_t axes_ctrl_reg; lis25ba_tdm_ctrl_reg_t tdm_ctrl_reg; @@ -394,7 +404,7 @@ int32_t lis25ba_data_get(uint16_t *tdm_stream, lis25ba_bus_mode_t *md, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis25ba_self_test_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis25ba_self_test_set(const stmdev_ctx_t *ctx, uint8_t val) { lis25ba_test_reg_t test_reg; int32_t ret; @@ -419,7 +429,7 @@ int32_t lis25ba_self_test_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis25ba_self_test_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis25ba_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis25ba_test_reg_t test_reg; int32_t ret; diff --git a/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.h b/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.h index c48a757e..fdffb764 100644 --- a/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.h +++ b/sensor/stmemsc/lis25ba_STdC/driver/lis25ba_reg.h @@ -310,10 +310,10 @@ typedef union * them with a custom implementation. */ -int32_t lis25ba_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lis25ba_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lis25ba_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lis25ba_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -323,7 +323,7 @@ typedef struct { uint8_t id; } lis25ba_id_t; -int32_t lis25ba_id_get(stmdev_ctx_t *ctx, lis25ba_id_t *val); +int32_t lis25ba_id_get(const stmdev_ctx_t *ctx, lis25ba_id_t *val); typedef struct { @@ -336,9 +336,9 @@ typedef struct uint16_t cmax : 1; /* BCLK in a WCLK (unused if odr=_XL_HW_SEL) */ } tdm; } lis25ba_bus_mode_t; -int32_t lis25ba_bus_mode_set(stmdev_ctx_t *ctx, +int32_t lis25ba_bus_mode_set(const stmdev_ctx_t *ctx, lis25ba_bus_mode_t *val); -int32_t lis25ba_bus_mode_get(stmdev_ctx_t *ctx, +int32_t lis25ba_bus_mode_get(const stmdev_ctx_t *ctx, lis25ba_bus_mode_t *val); typedef struct @@ -361,8 +361,8 @@ typedef struct } odr; } xl; } lis25ba_md_t; -int32_t lis25ba_mode_set(stmdev_ctx_t *ctx, lis25ba_md_t *val); -int32_t lis25ba_mode_get(stmdev_ctx_t *ctx, lis25ba_md_t *val); +int32_t lis25ba_mode_set(const stmdev_ctx_t *ctx, lis25ba_md_t *val); +int32_t lis25ba_mode_get(const stmdev_ctx_t *ctx, lis25ba_md_t *val); typedef struct { @@ -375,8 +375,8 @@ typedef struct int32_t lis25ba_data_get(uint16_t *tdm_stream, lis25ba_bus_mode_t *md, lis25ba_data_t *data); -int32_t lis25ba_self_test_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis25ba_self_test_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis25ba_self_test_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis25ba_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val); /** * @} diff --git a/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.c b/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.c index e40b907b..b8d62f7b 100644 --- a/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.c +++ b/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis2de12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lis2de12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lis2de12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis2de12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lis2de12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -135,7 +145,7 @@ float_t lis2de12_from_lsb_to_celsius(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis2de12_temp_status_reg_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -151,7 +161,7 @@ int32_t lis2de12_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2de12_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2de12_status_reg_aux_t status_reg_aux; int32_t ret; @@ -170,7 +180,7 @@ int32_t lis2de12_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2de12_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2de12_status_reg_aux_t status_reg_aux; int32_t ret; @@ -189,7 +199,7 @@ int32_t lis2de12_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lis2de12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -208,7 +218,7 @@ int32_t lis2de12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_temperature_meas_set(stmdev_ctx_t *ctx, +int32_t lis2de12_temperature_meas_set(const stmdev_ctx_t *ctx, lis2de12_temp_en_t val) { lis2de12_temp_cfg_reg_t temp_cfg_reg; @@ -235,7 +245,7 @@ int32_t lis2de12_temperature_meas_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_temperature_meas_get(stmdev_ctx_t *ctx, +int32_t lis2de12_temperature_meas_get(const stmdev_ctx_t *ctx, lis2de12_temp_en_t *val) { lis2de12_temp_cfg_reg_t temp_cfg_reg; @@ -270,7 +280,7 @@ int32_t lis2de12_temperature_meas_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_data_rate_set(stmdev_ctx_t *ctx, lis2de12_odr_t val) +int32_t lis2de12_data_rate_set(const stmdev_ctx_t *ctx, lis2de12_odr_t val) { lis2de12_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -297,7 +307,7 @@ int32_t lis2de12_data_rate_set(stmdev_ctx_t *ctx, lis2de12_odr_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_data_rate_get(stmdev_ctx_t *ctx, lis2de12_odr_t *val) +int32_t lis2de12_data_rate_get(const stmdev_ctx_t *ctx, lis2de12_odr_t *val) { lis2de12_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -364,7 +374,7 @@ int32_t lis2de12_data_rate_get(stmdev_ctx_t *ctx, lis2de12_odr_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_high_pass_on_outputs_set(stmdev_ctx_t *ctx, +int32_t lis2de12_high_pass_on_outputs_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2de12_ctrl_reg2_t ctrl_reg2; @@ -392,7 +402,7 @@ int32_t lis2de12_high_pass_on_outputs_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_high_pass_on_outputs_get(stmdev_ctx_t *ctx, +int32_t lis2de12_high_pass_on_outputs_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2de12_ctrl_reg2_t ctrl_reg2; @@ -419,7 +429,7 @@ int32_t lis2de12_high_pass_on_outputs_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_high_pass_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lis2de12_high_pass_bandwidth_set(const stmdev_ctx_t *ctx, lis2de12_hpcf_t val) { lis2de12_ctrl_reg2_t ctrl_reg2; @@ -452,7 +462,7 @@ int32_t lis2de12_high_pass_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_high_pass_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lis2de12_high_pass_bandwidth_get(const stmdev_ctx_t *ctx, lis2de12_hpcf_t *val) { lis2de12_ctrl_reg2_t ctrl_reg2; @@ -495,7 +505,7 @@ int32_t lis2de12_high_pass_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_high_pass_mode_set(stmdev_ctx_t *ctx, +int32_t lis2de12_high_pass_mode_set(const stmdev_ctx_t *ctx, lis2de12_hpm_t val) { lis2de12_ctrl_reg2_t ctrl_reg2; @@ -522,7 +532,7 @@ int32_t lis2de12_high_pass_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_high_pass_mode_get(stmdev_ctx_t *ctx, +int32_t lis2de12_high_pass_mode_get(const stmdev_ctx_t *ctx, lis2de12_hpm_t *val) { lis2de12_ctrl_reg2_t ctrl_reg2; @@ -565,7 +575,7 @@ int32_t lis2de12_high_pass_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_full_scale_set(stmdev_ctx_t *ctx, lis2de12_fs_t val) +int32_t lis2de12_full_scale_set(const stmdev_ctx_t *ctx, lis2de12_fs_t val) { lis2de12_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -591,7 +601,7 @@ int32_t lis2de12_full_scale_set(stmdev_ctx_t *ctx, lis2de12_fs_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_full_scale_get(stmdev_ctx_t *ctx, lis2de12_fs_t *val) +int32_t lis2de12_full_scale_get(const stmdev_ctx_t *ctx, lis2de12_fs_t *val) { lis2de12_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -633,7 +643,7 @@ int32_t lis2de12_full_scale_get(stmdev_ctx_t *ctx, lis2de12_fs_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2de12_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2de12_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -659,7 +669,7 @@ int32_t lis2de12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lis2de12_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2de12_ctrl_reg4_t ctrl_reg4; @@ -681,7 +691,7 @@ int32_t lis2de12_block_data_update_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_filter_reference_set(stmdev_ctx_t *ctx, +int32_t lis2de12_filter_reference_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -700,7 +710,7 @@ int32_t lis2de12_filter_reference_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_filter_reference_get(stmdev_ctx_t *ctx, +int32_t lis2de12_filter_reference_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -717,7 +727,7 @@ int32_t lis2de12_filter_reference_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2de12_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2de12_status_reg_t status_reg; int32_t ret; @@ -736,7 +746,7 @@ int32_t lis2de12_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2de12_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2de12_status_reg_t status_reg; int32_t ret; @@ -755,7 +765,7 @@ int32_t lis2de12_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lis2de12_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -790,7 +800,7 @@ int32_t lis2de12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis2de12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -806,7 +816,7 @@ int32_t lis2de12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_self_test_set(stmdev_ctx_t *ctx, lis2de12_st_t val) +int32_t lis2de12_self_test_set(const stmdev_ctx_t *ctx, lis2de12_st_t val) { lis2de12_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -832,7 +842,7 @@ int32_t lis2de12_self_test_set(stmdev_ctx_t *ctx, lis2de12_st_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_self_test_get(stmdev_ctx_t *ctx, lis2de12_st_t *val) +int32_t lis2de12_self_test_get(const stmdev_ctx_t *ctx, lis2de12_st_t *val) { lis2de12_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -870,7 +880,7 @@ int32_t lis2de12_self_test_get(stmdev_ctx_t *ctx, lis2de12_st_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2de12_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2de12_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -896,7 +906,7 @@ int32_t lis2de12_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2de12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2de12_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -916,7 +926,7 @@ int32_t lis2de12_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_status_get(stmdev_ctx_t *ctx, +int32_t lis2de12_status_get(const stmdev_ctx_t *ctx, lis2de12_status_reg_t *val) { int32_t ret; @@ -946,7 +956,7 @@ int32_t lis2de12_status_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_int1_gen_conf_set(stmdev_ctx_t *ctx, +int32_t lis2de12_int1_gen_conf_set(const stmdev_ctx_t *ctx, lis2de12_int1_cfg_t *val) { int32_t ret; @@ -964,7 +974,7 @@ int32_t lis2de12_int1_gen_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_int1_gen_conf_get(stmdev_ctx_t *ctx, +int32_t lis2de12_int1_gen_conf_get(const stmdev_ctx_t *ctx, lis2de12_int1_cfg_t *val) { int32_t ret; @@ -982,7 +992,7 @@ int32_t lis2de12_int1_gen_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_int1_gen_source_get(stmdev_ctx_t *ctx, +int32_t lis2de12_int1_gen_source_get(const stmdev_ctx_t *ctx, lis2de12_int1_src_t *val) { int32_t ret; @@ -1001,7 +1011,7 @@ int32_t lis2de12_int1_gen_source_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_int1_gen_threshold_set(stmdev_ctx_t *ctx, +int32_t lis2de12_int1_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2de12_int1_ths_t int1_ths; @@ -1028,7 +1038,7 @@ int32_t lis2de12_int1_gen_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_int1_gen_threshold_get(stmdev_ctx_t *ctx, +int32_t lis2de12_int1_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2de12_int1_ths_t int1_ths; @@ -1049,7 +1059,7 @@ int32_t lis2de12_int1_gen_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2de12_int1_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2de12_int1_duration_t int1_duration; int32_t ret; @@ -1076,7 +1086,7 @@ int32_t lis2de12_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_int1_gen_duration_get(stmdev_ctx_t *ctx, +int32_t lis2de12_int1_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2de12_int1_duration_t int1_duration; @@ -1110,7 +1120,7 @@ int32_t lis2de12_int1_gen_duration_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_int2_gen_conf_set(stmdev_ctx_t *ctx, +int32_t lis2de12_int2_gen_conf_set(const stmdev_ctx_t *ctx, lis2de12_int2_cfg_t *val) { int32_t ret; @@ -1128,7 +1138,7 @@ int32_t lis2de12_int2_gen_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_int2_gen_conf_get(stmdev_ctx_t *ctx, +int32_t lis2de12_int2_gen_conf_get(const stmdev_ctx_t *ctx, lis2de12_int2_cfg_t *val) { int32_t ret; @@ -1145,7 +1155,7 @@ int32_t lis2de12_int2_gen_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_int2_gen_source_get(stmdev_ctx_t *ctx, +int32_t lis2de12_int2_gen_source_get(const stmdev_ctx_t *ctx, lis2de12_int2_src_t *val) { int32_t ret; @@ -1164,7 +1174,7 @@ int32_t lis2de12_int2_gen_source_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_int2_gen_threshold_set(stmdev_ctx_t *ctx, +int32_t lis2de12_int2_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2de12_int2_ths_t int2_ths; @@ -1191,7 +1201,7 @@ int32_t lis2de12_int2_gen_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_int2_gen_threshold_get(stmdev_ctx_t *ctx, +int32_t lis2de12_int2_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2de12_int2_ths_t int2_ths; @@ -1212,7 +1222,7 @@ int32_t lis2de12_int2_gen_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2de12_int2_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2de12_int2_duration_t int2_duration; int32_t ret; @@ -1239,7 +1249,7 @@ int32_t lis2de12_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_int2_gen_duration_get(stmdev_ctx_t *ctx, +int32_t lis2de12_int2_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2de12_int2_duration_t int2_duration; @@ -1272,7 +1282,7 @@ int32_t lis2de12_int2_gen_duration_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_high_pass_int_conf_set(stmdev_ctx_t *ctx, +int32_t lis2de12_high_pass_int_conf_set(const stmdev_ctx_t *ctx, lis2de12_hp_t val) { lis2de12_ctrl_reg2_t ctrl_reg2; @@ -1299,7 +1309,7 @@ int32_t lis2de12_high_pass_int_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_high_pass_int_conf_get(stmdev_ctx_t *ctx, +int32_t lis2de12_high_pass_int_conf_get(const stmdev_ctx_t *ctx, lis2de12_hp_t *val) { lis2de12_ctrl_reg2_t ctrl_reg2; @@ -1358,7 +1368,7 @@ int32_t lis2de12_high_pass_int_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_pin_int1_config_set(stmdev_ctx_t *ctx, +int32_t lis2de12_pin_int1_config_set(const stmdev_ctx_t *ctx, lis2de12_ctrl_reg3_t *val) { int32_t ret; @@ -1376,7 +1386,7 @@ int32_t lis2de12_pin_int1_config_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_pin_int1_config_get(stmdev_ctx_t *ctx, +int32_t lis2de12_pin_int1_config_get(const stmdev_ctx_t *ctx, lis2de12_ctrl_reg3_t *val) { int32_t ret; @@ -1395,7 +1405,7 @@ int32_t lis2de12_pin_int1_config_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, +int32_t lis2de12_int2_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2de12_ctrl_reg5_t ctrl_reg5; @@ -1423,7 +1433,7 @@ int32_t lis2de12_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, +int32_t lis2de12_int2_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2de12_ctrl_reg5_t ctrl_reg5; @@ -1446,7 +1456,7 @@ int32_t lis2de12_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_int2_pin_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis2de12_int2_pin_notification_mode_set(const stmdev_ctx_t *ctx, lis2de12_lir_int2_t val) { lis2de12_ctrl_reg5_t ctrl_reg5; @@ -1475,7 +1485,7 @@ int32_t lis2de12_int2_pin_notification_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_int2_pin_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis2de12_int2_pin_notification_mode_get(const stmdev_ctx_t *ctx, lis2de12_lir_int2_t *val) { lis2de12_ctrl_reg5_t ctrl_reg5; @@ -1511,7 +1521,7 @@ int32_t lis2de12_int2_pin_notification_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, +int32_t lis2de12_int1_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2de12_ctrl_reg5_t ctrl_reg5; @@ -1539,7 +1549,7 @@ int32_t lis2de12_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, +int32_t lis2de12_int1_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2de12_ctrl_reg5_t ctrl_reg5; @@ -1561,7 +1571,7 @@ int32_t lis2de12_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_int1_pin_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis2de12_int1_pin_notification_mode_set(const stmdev_ctx_t *ctx, lis2de12_lir_int1_t val) { lis2de12_ctrl_reg5_t ctrl_reg5; @@ -1589,7 +1599,7 @@ int32_t lis2de12_int1_pin_notification_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_int1_pin_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis2de12_int1_pin_notification_mode_get(const stmdev_ctx_t *ctx, lis2de12_lir_int1_t *val) { lis2de12_ctrl_reg5_t ctrl_reg5; @@ -1624,7 +1634,7 @@ int32_t lis2de12_int1_pin_notification_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_pin_int2_config_set(stmdev_ctx_t *ctx, +int32_t lis2de12_pin_int2_config_set(const stmdev_ctx_t *ctx, lis2de12_ctrl_reg6_t *val) { int32_t ret; @@ -1642,7 +1652,7 @@ int32_t lis2de12_pin_int2_config_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_pin_int2_config_get(stmdev_ctx_t *ctx, +int32_t lis2de12_pin_int2_config_get(const stmdev_ctx_t *ctx, lis2de12_ctrl_reg6_t *val) { int32_t ret; @@ -1671,7 +1681,7 @@ int32_t lis2de12_pin_int2_config_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_fifo_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2de12_fifo_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2de12_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1697,7 +1707,7 @@ int32_t lis2de12_fifo_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_fifo_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2de12_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2de12_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1717,7 +1727,7 @@ int32_t lis2de12_fifo_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2de12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2de12_fifo_ctrl_reg_t fifo_ctrl_reg; int32_t ret; @@ -1743,7 +1753,7 @@ int32_t lis2de12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2de12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2de12_fifo_ctrl_reg_t fifo_ctrl_reg; int32_t ret; @@ -1763,7 +1773,7 @@ int32_t lis2de12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_fifo_trigger_event_set(stmdev_ctx_t *ctx, +int32_t lis2de12_fifo_trigger_event_set(const stmdev_ctx_t *ctx, lis2de12_tr_t val) { lis2de12_fifo_ctrl_reg_t fifo_ctrl_reg; @@ -1790,7 +1800,7 @@ int32_t lis2de12_fifo_trigger_event_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_fifo_trigger_event_get(stmdev_ctx_t *ctx, +int32_t lis2de12_fifo_trigger_event_get(const stmdev_ctx_t *ctx, lis2de12_tr_t *val) { lis2de12_fifo_ctrl_reg_t fifo_ctrl_reg; @@ -1825,7 +1835,7 @@ int32_t lis2de12_fifo_trigger_event_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_fifo_mode_set(stmdev_ctx_t *ctx, lis2de12_fm_t val) +int32_t lis2de12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2de12_fm_t val) { lis2de12_fifo_ctrl_reg_t fifo_ctrl_reg; int32_t ret; @@ -1851,7 +1861,7 @@ int32_t lis2de12_fifo_mode_set(stmdev_ctx_t *ctx, lis2de12_fm_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_fifo_mode_get(stmdev_ctx_t *ctx, lis2de12_fm_t *val) +int32_t lis2de12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2de12_fm_t *val) { lis2de12_fifo_ctrl_reg_t fifo_ctrl_reg; int32_t ret; @@ -1893,7 +1903,7 @@ int32_t lis2de12_fifo_mode_get(stmdev_ctx_t *ctx, lis2de12_fm_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lis2de12_fifo_status_get(const stmdev_ctx_t *ctx, lis2de12_fifo_src_reg_t *val) { int32_t ret; @@ -1910,7 +1920,7 @@ int32_t lis2de12_fifo_status_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2de12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2de12_fifo_src_reg_t fifo_src_reg; int32_t ret; @@ -1929,7 +1939,7 @@ int32_t lis2de12_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2de12_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2de12_fifo_src_reg_t fifo_src_reg; int32_t ret; @@ -1948,7 +1958,7 @@ int32_t lis2de12_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2de12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2de12_fifo_src_reg_t fifo_src_reg; int32_t ret; @@ -1967,7 +1977,7 @@ int32_t lis2de12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2de12_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2de12_fifo_src_reg_t fifo_src_reg; int32_t ret; @@ -1999,7 +2009,7 @@ int32_t lis2de12_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_tap_conf_set(stmdev_ctx_t *ctx, +int32_t lis2de12_tap_conf_set(const stmdev_ctx_t *ctx, lis2de12_click_cfg_t *val) { int32_t ret; @@ -2017,7 +2027,7 @@ int32_t lis2de12_tap_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_tap_conf_get(stmdev_ctx_t *ctx, +int32_t lis2de12_tap_conf_get(const stmdev_ctx_t *ctx, lis2de12_click_cfg_t *val) { int32_t ret; @@ -2034,7 +2044,7 @@ int32_t lis2de12_tap_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_tap_source_get(stmdev_ctx_t *ctx, +int32_t lis2de12_tap_source_get(const stmdev_ctx_t *ctx, lis2de12_click_src_t *val) { int32_t ret; @@ -2052,7 +2062,7 @@ int32_t lis2de12_tap_source_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2de12_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2de12_click_ths_t click_ths; int32_t ret; @@ -2079,7 +2089,7 @@ int32_t lis2de12_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2de12_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2de12_click_ths_t click_ths; int32_t ret; @@ -2102,7 +2112,7 @@ int32_t lis2de12_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_tap_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis2de12_tap_notification_mode_set(const stmdev_ctx_t *ctx, lis2de12_lir_click_t val) { lis2de12_click_ths_t click_ths; @@ -2132,7 +2142,7 @@ int32_t lis2de12_tap_notification_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_tap_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis2de12_tap_notification_mode_get(const stmdev_ctx_t *ctx, lis2de12_lir_click_t *val) { lis2de12_click_ths_t click_ths; @@ -2169,7 +2179,7 @@ int32_t lis2de12_tap_notification_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2de12_shock_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2de12_time_limit_t time_limit; int32_t ret; @@ -2197,7 +2207,7 @@ int32_t lis2de12_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2de12_shock_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2de12_time_limit_t time_limit; int32_t ret; @@ -2220,7 +2230,7 @@ int32_t lis2de12_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2de12_quiet_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2de12_time_latency_t time_latency; int32_t ret; @@ -2249,7 +2259,7 @@ int32_t lis2de12_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2de12_quiet_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2de12_time_latency_t time_latency; int32_t ret; @@ -2272,7 +2282,7 @@ int32_t lis2de12_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_double_tap_timeout_set(stmdev_ctx_t *ctx, +int32_t lis2de12_double_tap_timeout_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2de12_time_window_t time_window; @@ -2302,7 +2312,7 @@ int32_t lis2de12_double_tap_timeout_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_double_tap_timeout_get(stmdev_ctx_t *ctx, +int32_t lis2de12_double_tap_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2de12_time_window_t time_window; @@ -2338,7 +2348,7 @@ int32_t lis2de12_double_tap_timeout_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2de12_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2de12_act_ths_t act_ths; int32_t ret; @@ -2364,7 +2374,7 @@ int32_t lis2de12_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2de12_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2de12_act_ths_t act_ths; int32_t ret; @@ -2384,7 +2394,7 @@ int32_t lis2de12_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2de12_act_timeout_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2de12_act_dur_t act_dur; int32_t ret; @@ -2409,7 +2419,7 @@ int32_t lis2de12_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2de12_act_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2de12_act_dur_t act_dur; int32_t ret; @@ -2441,7 +2451,7 @@ int32_t lis2de12_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_pin_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t lis2de12_pin_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, lis2de12_sdo_pu_disc_t val) { lis2de12_ctrl_reg0_t ctrl_reg0; @@ -2468,7 +2478,7 @@ int32_t lis2de12_pin_sdo_sa0_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_pin_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t lis2de12_pin_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, lis2de12_sdo_pu_disc_t *val) { lis2de12_ctrl_reg0_t ctrl_reg0; @@ -2503,7 +2513,7 @@ int32_t lis2de12_pin_sdo_sa0_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_spi_mode_set(stmdev_ctx_t *ctx, lis2de12_sim_t val) +int32_t lis2de12_spi_mode_set(const stmdev_ctx_t *ctx, lis2de12_sim_t val) { lis2de12_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -2529,7 +2539,7 @@ int32_t lis2de12_spi_mode_set(stmdev_ctx_t *ctx, lis2de12_sim_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2de12_spi_mode_get(stmdev_ctx_t *ctx, lis2de12_sim_t *val) +int32_t lis2de12_spi_mode_get(const stmdev_ctx_t *ctx, lis2de12_sim_t *val) { lis2de12_ctrl_reg4_t ctrl_reg4; int32_t ret; diff --git a/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.h b/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.h index c6206d0b..02a3a0fe 100644 --- a/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.h +++ b/sensor/stmemsc/lis2de12_STdC/driver/lis2de12_reg.h @@ -717,10 +717,10 @@ typedef union * them with a custom implementation. */ -int32_t lis2de12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lis2de12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lis2de12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lis2de12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -731,22 +731,22 @@ float_t lis2de12_from_fs16_to_mg(int16_t lsb); float_t lis2de12_from_lsb_to_celsius(int16_t lsb); -int32_t lis2de12_temp_status_reg_get(stmdev_ctx_t *ctx, +int32_t lis2de12_temp_status_reg_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis2de12_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2de12_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2de12_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2de12_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2de12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lis2de12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); typedef enum { LIS2DE12_TEMP_DISABLE = 0, LIS2DE12_TEMP_ENABLE = 3, } lis2de12_temp_en_t; -int32_t lis2de12_temperature_meas_set(stmdev_ctx_t *ctx, +int32_t lis2de12_temperature_meas_set(const stmdev_ctx_t *ctx, lis2de12_temp_en_t val); -int32_t lis2de12_temperature_meas_get(stmdev_ctx_t *ctx, +int32_t lis2de12_temperature_meas_get(const stmdev_ctx_t *ctx, lis2de12_temp_en_t *val); typedef enum @@ -762,13 +762,13 @@ typedef enum LIS2DE12_ODR_1kHz620_LP = 0x08, LIS2DE12_ODR_5kHz376_LP_1kHz344_NM_HP = 0x09, } lis2de12_odr_t; -int32_t lis2de12_data_rate_set(stmdev_ctx_t *ctx, lis2de12_odr_t val); -int32_t lis2de12_data_rate_get(stmdev_ctx_t *ctx, +int32_t lis2de12_data_rate_set(const stmdev_ctx_t *ctx, lis2de12_odr_t val); +int32_t lis2de12_data_rate_get(const stmdev_ctx_t *ctx, lis2de12_odr_t *val); -int32_t lis2de12_high_pass_on_outputs_set(stmdev_ctx_t *ctx, +int32_t lis2de12_high_pass_on_outputs_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2de12_high_pass_on_outputs_get(stmdev_ctx_t *ctx, +int32_t lis2de12_high_pass_on_outputs_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -778,9 +778,9 @@ typedef enum LIS2DE12_MEDIUM = 2, LIS2DE12_LIGHT = 3, } lis2de12_hpcf_t; -int32_t lis2de12_high_pass_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lis2de12_high_pass_bandwidth_set(const stmdev_ctx_t *ctx, lis2de12_hpcf_t val); -int32_t lis2de12_high_pass_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lis2de12_high_pass_bandwidth_get(const stmdev_ctx_t *ctx, lis2de12_hpcf_t *val); typedef enum @@ -790,9 +790,9 @@ typedef enum LIS2DE12_NORMAL = 2, LIS2DE12_AUTORST_ON_INT = 3, } lis2de12_hpm_t; -int32_t lis2de12_high_pass_mode_set(stmdev_ctx_t *ctx, +int32_t lis2de12_high_pass_mode_set(const stmdev_ctx_t *ctx, lis2de12_hpm_t val); -int32_t lis2de12_high_pass_mode_get(stmdev_ctx_t *ctx, +int32_t lis2de12_high_pass_mode_get(const stmdev_ctx_t *ctx, lis2de12_hpm_t *val); typedef enum @@ -802,28 +802,28 @@ typedef enum LIS2DE12_8g = 2, LIS2DE12_16g = 3, } lis2de12_fs_t; -int32_t lis2de12_full_scale_set(stmdev_ctx_t *ctx, lis2de12_fs_t val); -int32_t lis2de12_full_scale_get(stmdev_ctx_t *ctx, +int32_t lis2de12_full_scale_set(const stmdev_ctx_t *ctx, lis2de12_fs_t val); +int32_t lis2de12_full_scale_get(const stmdev_ctx_t *ctx, lis2de12_fs_t *val); -int32_t lis2de12_block_data_update_set(stmdev_ctx_t *ctx, +int32_t lis2de12_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2de12_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lis2de12_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2de12_filter_reference_set(stmdev_ctx_t *ctx, +int32_t lis2de12_filter_reference_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis2de12_filter_reference_get(stmdev_ctx_t *ctx, +int32_t lis2de12_filter_reference_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis2de12_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2de12_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2de12_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2de12_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2de12_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t lis2de12_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lis2de12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis2de12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); typedef enum { @@ -831,49 +831,49 @@ typedef enum LIS2DE12_ST_POSITIVE = 1, LIS2DE12_ST_NEGATIVE = 2, } lis2de12_st_t; -int32_t lis2de12_self_test_set(stmdev_ctx_t *ctx, lis2de12_st_t val); -int32_t lis2de12_self_test_get(stmdev_ctx_t *ctx, lis2de12_st_t *val); +int32_t lis2de12_self_test_set(const stmdev_ctx_t *ctx, lis2de12_st_t val); +int32_t lis2de12_self_test_get(const stmdev_ctx_t *ctx, lis2de12_st_t *val); -int32_t lis2de12_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2de12_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2de12_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2de12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2de12_status_get(stmdev_ctx_t *ctx, +int32_t lis2de12_status_get(const stmdev_ctx_t *ctx, lis2de12_status_reg_t *val); -int32_t lis2de12_int1_gen_conf_set(stmdev_ctx_t *ctx, +int32_t lis2de12_int1_gen_conf_set(const stmdev_ctx_t *ctx, lis2de12_int1_cfg_t *val); -int32_t lis2de12_int1_gen_conf_get(stmdev_ctx_t *ctx, +int32_t lis2de12_int1_gen_conf_get(const stmdev_ctx_t *ctx, lis2de12_int1_cfg_t *val); -int32_t lis2de12_int1_gen_source_get(stmdev_ctx_t *ctx, +int32_t lis2de12_int1_gen_source_get(const stmdev_ctx_t *ctx, lis2de12_int1_src_t *val); -int32_t lis2de12_int1_gen_threshold_set(stmdev_ctx_t *ctx, +int32_t lis2de12_int1_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2de12_int1_gen_threshold_get(stmdev_ctx_t *ctx, +int32_t lis2de12_int1_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2de12_int1_gen_duration_set(stmdev_ctx_t *ctx, +int32_t lis2de12_int1_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2de12_int1_gen_duration_get(stmdev_ctx_t *ctx, +int32_t lis2de12_int1_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2de12_int2_gen_conf_set(stmdev_ctx_t *ctx, +int32_t lis2de12_int2_gen_conf_set(const stmdev_ctx_t *ctx, lis2de12_int2_cfg_t *val); -int32_t lis2de12_int2_gen_conf_get(stmdev_ctx_t *ctx, +int32_t lis2de12_int2_gen_conf_get(const stmdev_ctx_t *ctx, lis2de12_int2_cfg_t *val); -int32_t lis2de12_int2_gen_source_get(stmdev_ctx_t *ctx, +int32_t lis2de12_int2_gen_source_get(const stmdev_ctx_t *ctx, lis2de12_int2_src_t *val); -int32_t lis2de12_int2_gen_threshold_set(stmdev_ctx_t *ctx, +int32_t lis2de12_int2_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2de12_int2_gen_threshold_get(stmdev_ctx_t *ctx, +int32_t lis2de12_int2_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2de12_int2_gen_duration_set(stmdev_ctx_t *ctx, +int32_t lis2de12_int2_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2de12_int2_gen_duration_get(stmdev_ctx_t *ctx, +int32_t lis2de12_int2_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -887,19 +887,19 @@ typedef enum LIS2DE12_ON_INT2_TAP_GEN = 6, LIS2DE12_ON_INT1_INT2_TAP_GEN = 7, } lis2de12_hp_t; -int32_t lis2de12_high_pass_int_conf_set(stmdev_ctx_t *ctx, +int32_t lis2de12_high_pass_int_conf_set(const stmdev_ctx_t *ctx, lis2de12_hp_t val); -int32_t lis2de12_high_pass_int_conf_get(stmdev_ctx_t *ctx, +int32_t lis2de12_high_pass_int_conf_get(const stmdev_ctx_t *ctx, lis2de12_hp_t *val); -int32_t lis2de12_pin_int1_config_set(stmdev_ctx_t *ctx, +int32_t lis2de12_pin_int1_config_set(const stmdev_ctx_t *ctx, lis2de12_ctrl_reg3_t *val); -int32_t lis2de12_pin_int1_config_get(stmdev_ctx_t *ctx, +int32_t lis2de12_pin_int1_config_get(const stmdev_ctx_t *ctx, lis2de12_ctrl_reg3_t *val); -int32_t lis2de12_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, +int32_t lis2de12_int2_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2de12_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, +int32_t lis2de12_int2_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -907,14 +907,14 @@ typedef enum LIS2DE12_INT2_PULSED = 0, LIS2DE12_INT2_LATCHED = 1, } lis2de12_lir_int2_t; -int32_t lis2de12_int2_pin_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis2de12_int2_pin_notification_mode_set(const stmdev_ctx_t *ctx, lis2de12_lir_int2_t val); -int32_t lis2de12_int2_pin_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis2de12_int2_pin_notification_mode_get(const stmdev_ctx_t *ctx, lis2de12_lir_int2_t *val); -int32_t lis2de12_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, +int32_t lis2de12_int1_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2de12_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, +int32_t lis2de12_int1_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -922,30 +922,30 @@ typedef enum LIS2DE12_INT1_PULSED = 0, LIS2DE12_INT1_LATCHED = 1, } lis2de12_lir_int1_t; -int32_t lis2de12_int1_pin_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis2de12_int1_pin_notification_mode_set(const stmdev_ctx_t *ctx, lis2de12_lir_int1_t val); -int32_t lis2de12_int1_pin_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis2de12_int1_pin_notification_mode_get(const stmdev_ctx_t *ctx, lis2de12_lir_int1_t *val); -int32_t lis2de12_pin_int2_config_set(stmdev_ctx_t *ctx, +int32_t lis2de12_pin_int2_config_set(const stmdev_ctx_t *ctx, lis2de12_ctrl_reg6_t *val); -int32_t lis2de12_pin_int2_config_get(stmdev_ctx_t *ctx, +int32_t lis2de12_pin_int2_config_get(const stmdev_ctx_t *ctx, lis2de12_ctrl_reg6_t *val); -int32_t lis2de12_fifo_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2de12_fifo_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2de12_fifo_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2de12_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2de12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2de12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2de12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2de12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LIS2DE12_INT1_GEN = 0, LIS2DE12_INT2_GEN = 1, } lis2de12_tr_t; -int32_t lis2de12_fifo_trigger_event_set(stmdev_ctx_t *ctx, +int32_t lis2de12_fifo_trigger_event_set(const stmdev_ctx_t *ctx, lis2de12_tr_t val); -int32_t lis2de12_fifo_trigger_event_get(stmdev_ctx_t *ctx, +int32_t lis2de12_fifo_trigger_event_get(const stmdev_ctx_t *ctx, lis2de12_tr_t *val); typedef enum @@ -955,66 +955,66 @@ typedef enum LIS2DE12_DYNAMIC_STREAM_MODE = 2, LIS2DE12_STREAM_TO_FIFO_MODE = 3, } lis2de12_fm_t; -int32_t lis2de12_fifo_mode_set(stmdev_ctx_t *ctx, lis2de12_fm_t val); -int32_t lis2de12_fifo_mode_get(stmdev_ctx_t *ctx, lis2de12_fm_t *val); +int32_t lis2de12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2de12_fm_t val); +int32_t lis2de12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2de12_fm_t *val); -int32_t lis2de12_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lis2de12_fifo_status_get(const stmdev_ctx_t *ctx, lis2de12_fifo_src_reg_t *val); -int32_t lis2de12_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2de12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2de12_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2de12_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2de12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2de12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2de12_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2de12_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2de12_tap_conf_set(stmdev_ctx_t *ctx, +int32_t lis2de12_tap_conf_set(const stmdev_ctx_t *ctx, lis2de12_click_cfg_t *val); -int32_t lis2de12_tap_conf_get(stmdev_ctx_t *ctx, +int32_t lis2de12_tap_conf_get(const stmdev_ctx_t *ctx, lis2de12_click_cfg_t *val); -int32_t lis2de12_tap_source_get(stmdev_ctx_t *ctx, +int32_t lis2de12_tap_source_get(const stmdev_ctx_t *ctx, lis2de12_click_src_t *val); -int32_t lis2de12_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2de12_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2de12_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2de12_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LIS2DE12_TAP_PULSED = 0, LIS2DE12_TAP_LATCHED = 1, } lis2de12_lir_click_t; -int32_t lis2de12_tap_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis2de12_tap_notification_mode_set(const stmdev_ctx_t *ctx, lis2de12_lir_click_t val); -int32_t lis2de12_tap_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis2de12_tap_notification_mode_get(const stmdev_ctx_t *ctx, lis2de12_lir_click_t *val); -int32_t lis2de12_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2de12_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2de12_shock_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2de12_shock_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2de12_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2de12_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2de12_quiet_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2de12_quiet_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2de12_double_tap_timeout_set(stmdev_ctx_t *ctx, +int32_t lis2de12_double_tap_timeout_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2de12_double_tap_timeout_get(stmdev_ctx_t *ctx, +int32_t lis2de12_double_tap_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2de12_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2de12_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2de12_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2de12_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2de12_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2de12_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2de12_act_timeout_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2de12_act_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LIS2DE12_PULL_UP_DISCONNECT = 1, LIS2DE12_PULL_UP_CONNECT = 0, } lis2de12_sdo_pu_disc_t; -int32_t lis2de12_pin_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t lis2de12_pin_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, lis2de12_sdo_pu_disc_t val); -int32_t lis2de12_pin_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t lis2de12_pin_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, lis2de12_sdo_pu_disc_t *val); typedef enum @@ -1022,8 +1022,8 @@ typedef enum LIS2DE12_SPI_4_WIRE = 0, LIS2DE12_SPI_3_WIRE = 1, } lis2de12_sim_t; -int32_t lis2de12_spi_mode_set(stmdev_ctx_t *ctx, lis2de12_sim_t val); -int32_t lis2de12_spi_mode_get(stmdev_ctx_t *ctx, lis2de12_sim_t *val); +int32_t lis2de12_spi_mode_set(const stmdev_ctx_t *ctx, lis2de12_sim_t val); +int32_t lis2de12_spi_mode_get(const stmdev_ctx_t *ctx, lis2de12_sim_t *val); /** * @} diff --git a/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.c b/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.c index bd09a4b5..e56befd0 100644 --- a/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.c +++ b/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis2dh12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lis2dh12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lis2dh12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis2dh12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lis2dh12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -185,7 +195,7 @@ float_t lis2dh12_from_lsb_lp_to_celsius(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis2dh12_temp_status_reg_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -201,7 +211,7 @@ int32_t lis2dh12_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dh12_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dh12_status_reg_aux_t status_reg_aux; int32_t ret; @@ -220,7 +230,7 @@ int32_t lis2dh12_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dh12_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dh12_status_reg_aux_t status_reg_aux; int32_t ret; @@ -239,7 +249,7 @@ int32_t lis2dh12_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lis2dh12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -258,7 +268,7 @@ int32_t lis2dh12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_temperature_meas_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_temperature_meas_set(const stmdev_ctx_t *ctx, lis2dh12_temp_en_t val) { lis2dh12_temp_cfg_reg_t temp_cfg_reg; @@ -285,7 +295,7 @@ int32_t lis2dh12_temperature_meas_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_temperature_meas_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_temperature_meas_get(const stmdev_ctx_t *ctx, lis2dh12_temp_en_t *val) { lis2dh12_temp_cfg_reg_t temp_cfg_reg; @@ -321,7 +331,7 @@ int32_t lis2dh12_temperature_meas_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_operating_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_operating_mode_set(const stmdev_ctx_t *ctx, lis2dh12_op_md_t val) { lis2dh12_ctrl_reg1_t ctrl_reg1; @@ -378,7 +388,7 @@ int32_t lis2dh12_operating_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_operating_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_operating_mode_get(const stmdev_ctx_t *ctx, lis2dh12_op_md_t *val) { lis2dh12_ctrl_reg1_t ctrl_reg1; @@ -420,7 +430,7 @@ int32_t lis2dh12_operating_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_data_rate_set(stmdev_ctx_t *ctx, lis2dh12_odr_t val) +int32_t lis2dh12_data_rate_set(const stmdev_ctx_t *ctx, lis2dh12_odr_t val) { lis2dh12_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -446,7 +456,7 @@ int32_t lis2dh12_data_rate_set(stmdev_ctx_t *ctx, lis2dh12_odr_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_data_rate_get(stmdev_ctx_t *ctx, lis2dh12_odr_t *val) +int32_t lis2dh12_data_rate_get(const stmdev_ctx_t *ctx, lis2dh12_odr_t *val) { lis2dh12_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -513,7 +523,7 @@ int32_t lis2dh12_data_rate_get(stmdev_ctx_t *ctx, lis2dh12_odr_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_high_pass_on_outputs_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_high_pass_on_outputs_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dh12_ctrl_reg2_t ctrl_reg2; @@ -541,7 +551,7 @@ int32_t lis2dh12_high_pass_on_outputs_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_high_pass_on_outputs_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_high_pass_on_outputs_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dh12_ctrl_reg2_t ctrl_reg2; @@ -568,7 +578,7 @@ int32_t lis2dh12_high_pass_on_outputs_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_high_pass_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_high_pass_bandwidth_set(const stmdev_ctx_t *ctx, lis2dh12_hpcf_t val) { lis2dh12_ctrl_reg2_t ctrl_reg2; @@ -601,7 +611,7 @@ int32_t lis2dh12_high_pass_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_high_pass_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_high_pass_bandwidth_get(const stmdev_ctx_t *ctx, lis2dh12_hpcf_t *val) { lis2dh12_ctrl_reg2_t ctrl_reg2; @@ -644,7 +654,7 @@ int32_t lis2dh12_high_pass_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_high_pass_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_high_pass_mode_set(const stmdev_ctx_t *ctx, lis2dh12_hpm_t val) { lis2dh12_ctrl_reg2_t ctrl_reg2; @@ -671,7 +681,7 @@ int32_t lis2dh12_high_pass_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_high_pass_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_high_pass_mode_get(const stmdev_ctx_t *ctx, lis2dh12_hpm_t *val) { lis2dh12_ctrl_reg2_t ctrl_reg2; @@ -714,7 +724,7 @@ int32_t lis2dh12_high_pass_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_full_scale_set(stmdev_ctx_t *ctx, lis2dh12_fs_t val) +int32_t lis2dh12_full_scale_set(const stmdev_ctx_t *ctx, lis2dh12_fs_t val) { lis2dh12_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -740,7 +750,7 @@ int32_t lis2dh12_full_scale_set(stmdev_ctx_t *ctx, lis2dh12_fs_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_full_scale_get(stmdev_ctx_t *ctx, lis2dh12_fs_t *val) +int32_t lis2dh12_full_scale_get(const stmdev_ctx_t *ctx, lis2dh12_fs_t *val) { lis2dh12_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -782,7 +792,7 @@ int32_t lis2dh12_full_scale_get(stmdev_ctx_t *ctx, lis2dh12_fs_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dh12_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dh12_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -808,7 +818,7 @@ int32_t lis2dh12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dh12_ctrl_reg4_t ctrl_reg4; @@ -830,7 +840,7 @@ int32_t lis2dh12_block_data_update_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_filter_reference_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_filter_reference_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -849,7 +859,7 @@ int32_t lis2dh12_filter_reference_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_filter_reference_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_filter_reference_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -866,7 +876,7 @@ int32_t lis2dh12_filter_reference_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dh12_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dh12_status_reg_t status_reg; int32_t ret; @@ -885,7 +895,7 @@ int32_t lis2dh12_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dh12_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dh12_status_reg_t status_reg; int32_t ret; @@ -904,7 +914,7 @@ int32_t lis2dh12_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lis2dh12_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -939,7 +949,7 @@ int32_t lis2dh12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis2dh12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -955,7 +965,7 @@ int32_t lis2dh12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_self_test_set(stmdev_ctx_t *ctx, lis2dh12_st_t val) +int32_t lis2dh12_self_test_set(const stmdev_ctx_t *ctx, lis2dh12_st_t val) { lis2dh12_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -981,7 +991,7 @@ int32_t lis2dh12_self_test_set(stmdev_ctx_t *ctx, lis2dh12_st_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_self_test_get(stmdev_ctx_t *ctx, lis2dh12_st_t *val) +int32_t lis2dh12_self_test_get(const stmdev_ctx_t *ctx, lis2dh12_st_t *val) { lis2dh12_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -1019,7 +1029,7 @@ int32_t lis2dh12_self_test_get(stmdev_ctx_t *ctx, lis2dh12_st_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_data_format_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_data_format_set(const stmdev_ctx_t *ctx, lis2dh12_ble_t val) { lis2dh12_ctrl_reg4_t ctrl_reg4; @@ -1046,7 +1056,7 @@ int32_t lis2dh12_data_format_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_data_format_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_data_format_get(const stmdev_ctx_t *ctx, lis2dh12_ble_t *val) { lis2dh12_ctrl_reg4_t ctrl_reg4; @@ -1081,7 +1091,7 @@ int32_t lis2dh12_data_format_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dh12_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dh12_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1107,7 +1117,7 @@ int32_t lis2dh12_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dh12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dh12_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1127,7 +1137,7 @@ int32_t lis2dh12_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_status_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_status_get(const stmdev_ctx_t *ctx, lis2dh12_status_reg_t *val) { int32_t ret; @@ -1157,7 +1167,7 @@ int32_t lis2dh12_status_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_int1_gen_conf_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_int1_gen_conf_set(const stmdev_ctx_t *ctx, lis2dh12_int1_cfg_t *val) { int32_t ret; @@ -1175,7 +1185,7 @@ int32_t lis2dh12_int1_gen_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_int1_gen_conf_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_int1_gen_conf_get(const stmdev_ctx_t *ctx, lis2dh12_int1_cfg_t *val) { int32_t ret; @@ -1193,7 +1203,7 @@ int32_t lis2dh12_int1_gen_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_int1_gen_source_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_int1_gen_source_get(const stmdev_ctx_t *ctx, lis2dh12_int1_src_t *val) { int32_t ret; @@ -1212,7 +1222,7 @@ int32_t lis2dh12_int1_gen_source_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_int1_gen_threshold_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_int1_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dh12_int1_ths_t int1_ths; @@ -1239,7 +1249,7 @@ int32_t lis2dh12_int1_gen_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_int1_gen_threshold_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_int1_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dh12_int1_ths_t int1_ths; @@ -1260,7 +1270,7 @@ int32_t lis2dh12_int1_gen_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dh12_int1_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dh12_int1_duration_t int1_duration; int32_t ret; @@ -1287,7 +1297,7 @@ int32_t lis2dh12_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_int1_gen_duration_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_int1_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dh12_int1_duration_t int1_duration; @@ -1321,7 +1331,7 @@ int32_t lis2dh12_int1_gen_duration_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_int2_gen_conf_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_int2_gen_conf_set(const stmdev_ctx_t *ctx, lis2dh12_int2_cfg_t *val) { int32_t ret; @@ -1339,7 +1349,7 @@ int32_t lis2dh12_int2_gen_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_int2_gen_conf_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_int2_gen_conf_get(const stmdev_ctx_t *ctx, lis2dh12_int2_cfg_t *val) { int32_t ret; @@ -1356,7 +1366,7 @@ int32_t lis2dh12_int2_gen_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_int2_gen_source_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_int2_gen_source_get(const stmdev_ctx_t *ctx, lis2dh12_int2_src_t *val) { int32_t ret; @@ -1375,7 +1385,7 @@ int32_t lis2dh12_int2_gen_source_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_int2_gen_threshold_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_int2_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dh12_int2_ths_t int2_ths; @@ -1402,7 +1412,7 @@ int32_t lis2dh12_int2_gen_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_int2_gen_threshold_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_int2_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dh12_int2_ths_t int2_ths; @@ -1423,7 +1433,7 @@ int32_t lis2dh12_int2_gen_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dh12_int2_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dh12_int2_duration_t int2_duration; int32_t ret; @@ -1450,7 +1460,7 @@ int32_t lis2dh12_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_int2_gen_duration_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_int2_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dh12_int2_duration_t int2_duration; @@ -1483,7 +1493,7 @@ int32_t lis2dh12_int2_gen_duration_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_high_pass_int_conf_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_high_pass_int_conf_set(const stmdev_ctx_t *ctx, lis2dh12_hp_t val) { lis2dh12_ctrl_reg2_t ctrl_reg2; @@ -1510,7 +1520,7 @@ int32_t lis2dh12_high_pass_int_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_high_pass_int_conf_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_high_pass_int_conf_get(const stmdev_ctx_t *ctx, lis2dh12_hp_t *val) { lis2dh12_ctrl_reg2_t ctrl_reg2; @@ -1569,7 +1579,7 @@ int32_t lis2dh12_high_pass_int_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_pin_int1_config_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_pin_int1_config_set(const stmdev_ctx_t *ctx, lis2dh12_ctrl_reg3_t *val) { int32_t ret; @@ -1587,7 +1597,7 @@ int32_t lis2dh12_pin_int1_config_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_pin_int1_config_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_pin_int1_config_get(const stmdev_ctx_t *ctx, lis2dh12_ctrl_reg3_t *val) { int32_t ret; @@ -1606,7 +1616,7 @@ int32_t lis2dh12_pin_int1_config_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_int2_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dh12_ctrl_reg5_t ctrl_reg5; @@ -1634,7 +1644,7 @@ int32_t lis2dh12_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_int2_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dh12_ctrl_reg5_t ctrl_reg5; @@ -1657,7 +1667,7 @@ int32_t lis2dh12_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_int2_pin_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_int2_pin_notification_mode_set(const stmdev_ctx_t *ctx, lis2dh12_lir_int2_t val) { lis2dh12_ctrl_reg5_t ctrl_reg5; @@ -1686,7 +1696,7 @@ int32_t lis2dh12_int2_pin_notification_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_int2_pin_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_int2_pin_notification_mode_get(const stmdev_ctx_t *ctx, lis2dh12_lir_int2_t *val) { lis2dh12_ctrl_reg5_t ctrl_reg5; @@ -1722,7 +1732,7 @@ int32_t lis2dh12_int2_pin_notification_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_int1_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dh12_ctrl_reg5_t ctrl_reg5; @@ -1750,7 +1760,7 @@ int32_t lis2dh12_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_int1_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dh12_ctrl_reg5_t ctrl_reg5; @@ -1772,7 +1782,7 @@ int32_t lis2dh12_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_int1_pin_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_int1_pin_notification_mode_set(const stmdev_ctx_t *ctx, lis2dh12_lir_int1_t val) { lis2dh12_ctrl_reg5_t ctrl_reg5; @@ -1800,7 +1810,7 @@ int32_t lis2dh12_int1_pin_notification_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_int1_pin_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_int1_pin_notification_mode_get(const stmdev_ctx_t *ctx, lis2dh12_lir_int1_t *val) { lis2dh12_ctrl_reg5_t ctrl_reg5; @@ -1835,7 +1845,7 @@ int32_t lis2dh12_int1_pin_notification_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_pin_int2_config_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_pin_int2_config_set(const stmdev_ctx_t *ctx, lis2dh12_ctrl_reg6_t *val) { int32_t ret; @@ -1853,7 +1863,7 @@ int32_t lis2dh12_pin_int2_config_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_pin_int2_config_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_pin_int2_config_get(const stmdev_ctx_t *ctx, lis2dh12_ctrl_reg6_t *val) { int32_t ret; @@ -1882,7 +1892,7 @@ int32_t lis2dh12_pin_int2_config_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_fifo_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dh12_fifo_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dh12_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1908,7 +1918,7 @@ int32_t lis2dh12_fifo_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_fifo_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dh12_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dh12_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1928,7 +1938,7 @@ int32_t lis2dh12_fifo_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dh12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; int32_t ret; @@ -1954,7 +1964,7 @@ int32_t lis2dh12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dh12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; int32_t ret; @@ -1974,7 +1984,7 @@ int32_t lis2dh12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_fifo_trigger_event_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_fifo_trigger_event_set(const stmdev_ctx_t *ctx, lis2dh12_tr_t val) { lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; @@ -2001,7 +2011,7 @@ int32_t lis2dh12_fifo_trigger_event_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_fifo_trigger_event_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_fifo_trigger_event_get(const stmdev_ctx_t *ctx, lis2dh12_tr_t *val) { lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; @@ -2036,7 +2046,7 @@ int32_t lis2dh12_fifo_trigger_event_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_fifo_mode_set(stmdev_ctx_t *ctx, lis2dh12_fm_t val) +int32_t lis2dh12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2dh12_fm_t val) { lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; int32_t ret; @@ -2062,7 +2072,7 @@ int32_t lis2dh12_fifo_mode_set(stmdev_ctx_t *ctx, lis2dh12_fm_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_fifo_mode_get(stmdev_ctx_t *ctx, lis2dh12_fm_t *val) +int32_t lis2dh12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2dh12_fm_t *val) { lis2dh12_fifo_ctrl_reg_t fifo_ctrl_reg; int32_t ret; @@ -2104,7 +2114,7 @@ int32_t lis2dh12_fifo_mode_get(stmdev_ctx_t *ctx, lis2dh12_fm_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_fifo_status_get(const stmdev_ctx_t *ctx, lis2dh12_fifo_src_reg_t *val) { int32_t ret; @@ -2121,7 +2131,7 @@ int32_t lis2dh12_fifo_status_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dh12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dh12_fifo_src_reg_t fifo_src_reg; int32_t ret; @@ -2140,7 +2150,7 @@ int32_t lis2dh12_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dh12_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dh12_fifo_src_reg_t fifo_src_reg; int32_t ret; @@ -2159,7 +2169,7 @@ int32_t lis2dh12_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dh12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dh12_fifo_src_reg_t fifo_src_reg; int32_t ret; @@ -2178,7 +2188,7 @@ int32_t lis2dh12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dh12_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dh12_fifo_src_reg_t fifo_src_reg; int32_t ret; @@ -2210,7 +2220,7 @@ int32_t lis2dh12_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_tap_conf_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_tap_conf_set(const stmdev_ctx_t *ctx, lis2dh12_click_cfg_t *val) { int32_t ret; @@ -2228,7 +2238,7 @@ int32_t lis2dh12_tap_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_tap_conf_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_tap_conf_get(const stmdev_ctx_t *ctx, lis2dh12_click_cfg_t *val) { int32_t ret; @@ -2245,7 +2255,7 @@ int32_t lis2dh12_tap_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_tap_source_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_tap_source_get(const stmdev_ctx_t *ctx, lis2dh12_click_src_t *val) { int32_t ret; @@ -2263,7 +2273,7 @@ int32_t lis2dh12_tap_source_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dh12_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dh12_click_ths_t click_ths; int32_t ret; @@ -2290,7 +2300,7 @@ int32_t lis2dh12_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dh12_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dh12_click_ths_t click_ths; int32_t ret; @@ -2313,7 +2323,7 @@ int32_t lis2dh12_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_tap_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_tap_notification_mode_set(const stmdev_ctx_t *ctx, lis2dh12_lir_click_t val) { lis2dh12_click_ths_t click_ths; @@ -2343,7 +2353,7 @@ int32_t lis2dh12_tap_notification_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_tap_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_tap_notification_mode_get(const stmdev_ctx_t *ctx, lis2dh12_lir_click_t *val) { lis2dh12_click_ths_t click_ths; @@ -2380,7 +2390,7 @@ int32_t lis2dh12_tap_notification_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dh12_shock_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dh12_time_limit_t time_limit; int32_t ret; @@ -2408,7 +2418,7 @@ int32_t lis2dh12_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dh12_shock_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dh12_time_limit_t time_limit; int32_t ret; @@ -2431,7 +2441,7 @@ int32_t lis2dh12_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dh12_quiet_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dh12_time_latency_t time_latency; int32_t ret; @@ -2460,7 +2470,7 @@ int32_t lis2dh12_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dh12_quiet_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dh12_time_latency_t time_latency; int32_t ret; @@ -2483,7 +2493,7 @@ int32_t lis2dh12_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_double_tap_timeout_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_double_tap_timeout_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dh12_time_window_t time_window; @@ -2513,7 +2523,7 @@ int32_t lis2dh12_double_tap_timeout_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_double_tap_timeout_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_double_tap_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dh12_time_window_t time_window; @@ -2549,7 +2559,7 @@ int32_t lis2dh12_double_tap_timeout_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dh12_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dh12_act_ths_t act_ths; int32_t ret; @@ -2575,7 +2585,7 @@ int32_t lis2dh12_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dh12_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dh12_act_ths_t act_ths; int32_t ret; @@ -2595,7 +2605,7 @@ int32_t lis2dh12_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dh12_act_timeout_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dh12_act_dur_t act_dur; int32_t ret; @@ -2620,7 +2630,7 @@ int32_t lis2dh12_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dh12_act_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dh12_act_dur_t act_dur; int32_t ret; @@ -2652,7 +2662,7 @@ int32_t lis2dh12_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_pin_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_pin_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, lis2dh12_sdo_pu_disc_t val) { lis2dh12_ctrl_reg0_t ctrl_reg0; @@ -2679,7 +2689,7 @@ int32_t lis2dh12_pin_sdo_sa0_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_pin_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_pin_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, lis2dh12_sdo_pu_disc_t *val) { lis2dh12_ctrl_reg0_t ctrl_reg0; @@ -2714,7 +2724,7 @@ int32_t lis2dh12_pin_sdo_sa0_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_spi_mode_set(stmdev_ctx_t *ctx, lis2dh12_sim_t val) +int32_t lis2dh12_spi_mode_set(const stmdev_ctx_t *ctx, lis2dh12_sim_t val) { lis2dh12_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -2740,7 +2750,7 @@ int32_t lis2dh12_spi_mode_set(stmdev_ctx_t *ctx, lis2dh12_sim_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dh12_spi_mode_get(stmdev_ctx_t *ctx, lis2dh12_sim_t *val) +int32_t lis2dh12_spi_mode_get(const stmdev_ctx_t *ctx, lis2dh12_sim_t *val) { lis2dh12_ctrl_reg4_t ctrl_reg4; int32_t ret; diff --git a/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.h b/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.h index a32d5717..eb8d5ce8 100644 --- a/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.h +++ b/sensor/stmemsc/lis2dh12_STdC/driver/lis2dh12_reg.h @@ -718,10 +718,10 @@ typedef union * them with a custom implementation. */ -int32_t lis2dh12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lis2dh12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lis2dh12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lis2dh12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -743,22 +743,22 @@ float_t lis2dh12_from_fs8_lp_to_mg(int16_t lsb); float_t lis2dh12_from_fs16_lp_to_mg(int16_t lsb); float_t lis2dh12_from_lsb_lp_to_celsius(int16_t lsb); -int32_t lis2dh12_temp_status_reg_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_temp_status_reg_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis2dh12_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dh12_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dh12_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dh12_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dh12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lis2dh12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); typedef enum { LIS2DH12_TEMP_DISABLE = 0, LIS2DH12_TEMP_ENABLE = 3, } lis2dh12_temp_en_t; -int32_t lis2dh12_temperature_meas_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_temperature_meas_set(const stmdev_ctx_t *ctx, lis2dh12_temp_en_t val); -int32_t lis2dh12_temperature_meas_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_temperature_meas_get(const stmdev_ctx_t *ctx, lis2dh12_temp_en_t *val); typedef enum @@ -767,9 +767,9 @@ typedef enum LIS2DH12_NM_10bit = 1, LIS2DH12_LP_8bit = 2, } lis2dh12_op_md_t; -int32_t lis2dh12_operating_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_operating_mode_set(const stmdev_ctx_t *ctx, lis2dh12_op_md_t val); -int32_t lis2dh12_operating_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_operating_mode_get(const stmdev_ctx_t *ctx, lis2dh12_op_md_t *val); typedef enum @@ -785,13 +785,13 @@ typedef enum LIS2DH12_ODR_1kHz620_LP = 0x08, LIS2DH12_ODR_5kHz376_LP_1kHz344_NM_HP = 0x09, } lis2dh12_odr_t; -int32_t lis2dh12_data_rate_set(stmdev_ctx_t *ctx, lis2dh12_odr_t val); -int32_t lis2dh12_data_rate_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_data_rate_set(const stmdev_ctx_t *ctx, lis2dh12_odr_t val); +int32_t lis2dh12_data_rate_get(const stmdev_ctx_t *ctx, lis2dh12_odr_t *val); -int32_t lis2dh12_high_pass_on_outputs_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_high_pass_on_outputs_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dh12_high_pass_on_outputs_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_high_pass_on_outputs_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -801,9 +801,9 @@ typedef enum LIS2DH12_MEDIUM = 2, LIS2DH12_LIGHT = 3, } lis2dh12_hpcf_t; -int32_t lis2dh12_high_pass_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_high_pass_bandwidth_set(const stmdev_ctx_t *ctx, lis2dh12_hpcf_t val); -int32_t lis2dh12_high_pass_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_high_pass_bandwidth_get(const stmdev_ctx_t *ctx, lis2dh12_hpcf_t *val); typedef enum @@ -813,9 +813,9 @@ typedef enum LIS2DH12_NORMAL = 2, LIS2DH12_AUTORST_ON_INT = 3, } lis2dh12_hpm_t; -int32_t lis2dh12_high_pass_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_high_pass_mode_set(const stmdev_ctx_t *ctx, lis2dh12_hpm_t val); -int32_t lis2dh12_high_pass_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_high_pass_mode_get(const stmdev_ctx_t *ctx, lis2dh12_hpm_t *val); typedef enum @@ -825,28 +825,28 @@ typedef enum LIS2DH12_8g = 2, LIS2DH12_16g = 3, } lis2dh12_fs_t; -int32_t lis2dh12_full_scale_set(stmdev_ctx_t *ctx, lis2dh12_fs_t val); -int32_t lis2dh12_full_scale_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_full_scale_set(const stmdev_ctx_t *ctx, lis2dh12_fs_t val); +int32_t lis2dh12_full_scale_get(const stmdev_ctx_t *ctx, lis2dh12_fs_t *val); -int32_t lis2dh12_block_data_update_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dh12_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dh12_filter_reference_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_filter_reference_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis2dh12_filter_reference_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_filter_reference_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis2dh12_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dh12_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dh12_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dh12_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dh12_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lis2dh12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis2dh12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); typedef enum { @@ -854,59 +854,59 @@ typedef enum LIS2DH12_ST_POSITIVE = 1, LIS2DH12_ST_NEGATIVE = 2, } lis2dh12_st_t; -int32_t lis2dh12_self_test_set(stmdev_ctx_t *ctx, lis2dh12_st_t val); -int32_t lis2dh12_self_test_get(stmdev_ctx_t *ctx, lis2dh12_st_t *val); +int32_t lis2dh12_self_test_set(const stmdev_ctx_t *ctx, lis2dh12_st_t val); +int32_t lis2dh12_self_test_get(const stmdev_ctx_t *ctx, lis2dh12_st_t *val); typedef enum { LIS2DH12_LSB_AT_LOW_ADD = 0, LIS2DH12_MSB_AT_LOW_ADD = 1, } lis2dh12_ble_t; -int32_t lis2dh12_data_format_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_data_format_set(const stmdev_ctx_t *ctx, lis2dh12_ble_t val); -int32_t lis2dh12_data_format_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_data_format_get(const stmdev_ctx_t *ctx, lis2dh12_ble_t *val); -int32_t lis2dh12_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dh12_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dh12_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dh12_status_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_status_get(const stmdev_ctx_t *ctx, lis2dh12_status_reg_t *val); -int32_t lis2dh12_int1_gen_conf_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_int1_gen_conf_set(const stmdev_ctx_t *ctx, lis2dh12_int1_cfg_t *val); -int32_t lis2dh12_int1_gen_conf_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_int1_gen_conf_get(const stmdev_ctx_t *ctx, lis2dh12_int1_cfg_t *val); -int32_t lis2dh12_int1_gen_source_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_int1_gen_source_get(const stmdev_ctx_t *ctx, lis2dh12_int1_src_t *val); -int32_t lis2dh12_int1_gen_threshold_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_int1_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dh12_int1_gen_threshold_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_int1_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dh12_int1_gen_duration_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_int1_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dh12_int1_gen_duration_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_int1_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dh12_int2_gen_conf_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_int2_gen_conf_set(const stmdev_ctx_t *ctx, lis2dh12_int2_cfg_t *val); -int32_t lis2dh12_int2_gen_conf_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_int2_gen_conf_get(const stmdev_ctx_t *ctx, lis2dh12_int2_cfg_t *val); -int32_t lis2dh12_int2_gen_source_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_int2_gen_source_get(const stmdev_ctx_t *ctx, lis2dh12_int2_src_t *val); -int32_t lis2dh12_int2_gen_threshold_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_int2_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dh12_int2_gen_threshold_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_int2_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dh12_int2_gen_duration_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_int2_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dh12_int2_gen_duration_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_int2_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -920,19 +920,19 @@ typedef enum LIS2DH12_ON_INT2_TAP_GEN = 6, LIS2DH12_ON_INT1_INT2_TAP_GEN = 7, } lis2dh12_hp_t; -int32_t lis2dh12_high_pass_int_conf_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_high_pass_int_conf_set(const stmdev_ctx_t *ctx, lis2dh12_hp_t val); -int32_t lis2dh12_high_pass_int_conf_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_high_pass_int_conf_get(const stmdev_ctx_t *ctx, lis2dh12_hp_t *val); -int32_t lis2dh12_pin_int1_config_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_pin_int1_config_set(const stmdev_ctx_t *ctx, lis2dh12_ctrl_reg3_t *val); -int32_t lis2dh12_pin_int1_config_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_pin_int1_config_get(const stmdev_ctx_t *ctx, lis2dh12_ctrl_reg3_t *val); -int32_t lis2dh12_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_int2_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dh12_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_int2_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -940,14 +940,14 @@ typedef enum LIS2DH12_INT2_PULSED = 0, LIS2DH12_INT2_LATCHED = 1, } lis2dh12_lir_int2_t; -int32_t lis2dh12_int2_pin_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_int2_pin_notification_mode_set(const stmdev_ctx_t *ctx, lis2dh12_lir_int2_t val); -int32_t lis2dh12_int2_pin_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_int2_pin_notification_mode_get(const stmdev_ctx_t *ctx, lis2dh12_lir_int2_t *val); -int32_t lis2dh12_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_int1_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dh12_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_int1_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -955,30 +955,30 @@ typedef enum LIS2DH12_INT1_PULSED = 0, LIS2DH12_INT1_LATCHED = 1, } lis2dh12_lir_int1_t; -int32_t lis2dh12_int1_pin_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_int1_pin_notification_mode_set(const stmdev_ctx_t *ctx, lis2dh12_lir_int1_t val); -int32_t lis2dh12_int1_pin_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_int1_pin_notification_mode_get(const stmdev_ctx_t *ctx, lis2dh12_lir_int1_t *val); -int32_t lis2dh12_pin_int2_config_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_pin_int2_config_set(const stmdev_ctx_t *ctx, lis2dh12_ctrl_reg6_t *val); -int32_t lis2dh12_pin_int2_config_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_pin_int2_config_get(const stmdev_ctx_t *ctx, lis2dh12_ctrl_reg6_t *val); -int32_t lis2dh12_fifo_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dh12_fifo_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dh12_fifo_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dh12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dh12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dh12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LIS2DH12_INT1_GEN = 0, LIS2DH12_INT2_GEN = 1, } lis2dh12_tr_t; -int32_t lis2dh12_fifo_trigger_event_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_fifo_trigger_event_set(const stmdev_ctx_t *ctx, lis2dh12_tr_t val); -int32_t lis2dh12_fifo_trigger_event_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_fifo_trigger_event_get(const stmdev_ctx_t *ctx, lis2dh12_tr_t *val); typedef enum @@ -988,66 +988,66 @@ typedef enum LIS2DH12_DYNAMIC_STREAM_MODE = 2, LIS2DH12_STREAM_TO_FIFO_MODE = 3, } lis2dh12_fm_t; -int32_t lis2dh12_fifo_mode_set(stmdev_ctx_t *ctx, lis2dh12_fm_t val); -int32_t lis2dh12_fifo_mode_get(stmdev_ctx_t *ctx, lis2dh12_fm_t *val); +int32_t lis2dh12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2dh12_fm_t val); +int32_t lis2dh12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2dh12_fm_t *val); -int32_t lis2dh12_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_fifo_status_get(const stmdev_ctx_t *ctx, lis2dh12_fifo_src_reg_t *val); -int32_t lis2dh12_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dh12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dh12_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dh12_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dh12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dh12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dh12_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dh12_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dh12_tap_conf_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_tap_conf_set(const stmdev_ctx_t *ctx, lis2dh12_click_cfg_t *val); -int32_t lis2dh12_tap_conf_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_tap_conf_get(const stmdev_ctx_t *ctx, lis2dh12_click_cfg_t *val); -int32_t lis2dh12_tap_source_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_tap_source_get(const stmdev_ctx_t *ctx, lis2dh12_click_src_t *val); -int32_t lis2dh12_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dh12_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dh12_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LIS2DH12_TAP_PULSED = 0, LIS2DH12_TAP_LATCHED = 1, } lis2dh12_lir_click_t; -int32_t lis2dh12_tap_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_tap_notification_mode_set(const stmdev_ctx_t *ctx, lis2dh12_lir_click_t val); -int32_t lis2dh12_tap_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_tap_notification_mode_get(const stmdev_ctx_t *ctx, lis2dh12_lir_click_t *val); -int32_t lis2dh12_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dh12_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dh12_shock_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_shock_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dh12_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dh12_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dh12_quiet_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_quiet_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dh12_double_tap_timeout_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_double_tap_timeout_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dh12_double_tap_timeout_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_double_tap_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dh12_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dh12_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dh12_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dh12_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dh12_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dh12_act_timeout_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dh12_act_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { - LIS2DH12_PULL_UP_DISCONNECT = 0, - LIS2DH12_PULL_UP_CONNECT = 1, + LIS2DH12_PULL_UP_CONNECT = 0, + LIS2DH12_PULL_UP_DISCONNECT = 1, } lis2dh12_sdo_pu_disc_t; -int32_t lis2dh12_pin_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dh12_pin_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, lis2dh12_sdo_pu_disc_t val); -int32_t lis2dh12_pin_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dh12_pin_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, lis2dh12_sdo_pu_disc_t *val); typedef enum @@ -1055,8 +1055,8 @@ typedef enum LIS2DH12_SPI_4_WIRE = 0, LIS2DH12_SPI_3_WIRE = 1, } lis2dh12_sim_t; -int32_t lis2dh12_spi_mode_set(stmdev_ctx_t *ctx, lis2dh12_sim_t val); -int32_t lis2dh12_spi_mode_get(stmdev_ctx_t *ctx, lis2dh12_sim_t *val); +int32_t lis2dh12_spi_mode_set(const stmdev_ctx_t *ctx, lis2dh12_sim_t val); +int32_t lis2dh12_spi_mode_get(const stmdev_ctx_t *ctx, lis2dh12_sim_t *val); /** * @} diff --git a/sensor/stmemsc/lis2dh_STdC/driver/lis2dh_reg.c b/sensor/stmemsc/lis2dh_STdC/driver/lis2dh_reg.c deleted file mode 100644 index 507353a0..00000000 --- a/sensor/stmemsc/lis2dh_STdC/driver/lis2dh_reg.c +++ /dev/null @@ -1,2668 +0,0 @@ -/** - ****************************************************************************** - * @file lis2dh_reg.c - * @author Sensors Software Solution Team - * @brief LIS2DH driver file - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -#include "lis2dh_reg.h" - -/** - * @defgroup LIS2DH - * @brief This file provides a set of functions needed to drive the - * lis2dh enanced inertial module. - * @{ - * - */ - -/** - * @defgroup LIS2DH_Interfaces_Functions - * @brief This section provide a set of functions used to read and - * write a generic register of the device. - * MANDATORY: return 0 -> no Error. - * @{ - * - */ - -/** - * @brief Read generic device register - * - * @param ctx read / write interface definitions(ptr) - * @param reg register to read - * @param data pointer to buffer that store the data read(ptr) - * @param len number of consecutive register to read - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t __weak lis2dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) -{ - int32_t ret; - - ret = ctx->read_reg(ctx->handle, reg, data, len); - - return ret; -} - -/** - * @brief Write generic device register - * - * @param ctx read / write interface definitions(ptr) - * @param reg register to write - * @param data pointer to data to write in register reg(ptr) - * @param len number of consecutive register to write - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t __weak lis2dh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) -{ - int32_t ret; - - ret = ctx->write_reg(ctx->handle, reg, data, len); - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LIS2DH_Sensitivity - * @brief These functions convert raw-data into engineering units. - * @{ - * - */ - -float_t lis2dh_from_fs2_hr_to_mg(int16_t lsb) -{ - return ((float_t)lsb / 16.0f) * 1.0f; -} - -float_t lis2dh_from_fs4_hr_to_mg(int16_t lsb) -{ - return ((float_t)lsb / 16.0f) * 2.0f; -} - -float_t lis2dh_from_fs8_hr_to_mg(int16_t lsb) -{ - return ((float_t)lsb / 16.0f) * 4.0f; -} - -float_t lis2dh_from_fs16_hr_to_mg(int16_t lsb) -{ - return ((float_t)lsb / 16.0f) * 12.0f; -} - -float_t lis2dh_from_lsb_hr_to_celsius(int16_t lsb) -{ - return (((float_t)lsb / 64.0f) / 4.0f) + 25.0f; -} - -float_t lis2dh_from_fs2_nm_to_mg(int16_t lsb) -{ - return ((float_t)lsb / 64.0f) * 4.0f; -} - -float_t lis2dh_from_fs4_nm_to_mg(int16_t lsb) -{ - return ((float_t)lsb / 64.0f) * 8.0f; -} - -float_t lis2dh_from_fs8_nm_to_mg(int16_t lsb) -{ - return ((float_t)lsb / 64.0f) * 16.0f; -} - -float_t lis2dh_from_fs16_nm_to_mg(int16_t lsb) -{ - return ((float_t)lsb / 64.0f) * 48.0f; -} - -float_t lis2dh_from_lsb_nm_to_celsius(int16_t lsb) -{ - return (((float_t)lsb / 64.0f) / 4.0f) + 25.0f; -} - -float_t lis2dh_from_fs2_lp_to_mg(int16_t lsb) -{ - return ((float_t)lsb / 256.0f) * 16.0f; -} - -float_t lis2dh_from_fs4_lp_to_mg(int16_t lsb) -{ - return ((float_t)lsb / 256.0f) * 32.0f; -} - -float_t lis2dh_from_fs8_lp_to_mg(int16_t lsb) -{ - return ((float_t)lsb / 256.0f) * 64.0f; -} - -float_t lis2dh_from_fs16_lp_to_mg(int16_t lsb) -{ - return ((float_t)lsb / 256.0f) * 192.0f; -} - -float_t lis2dh_from_lsb_lp_to_celsius(int16_t lsb) -{ - return (((float_t)lsb / 256.0f) * 1.0f) + 25.0f; -} - -/** - * @} - * - */ - -/** - * @defgroup LIS2DH_Data_generation - * @brief This section group all the functions concerning data generation. - * @{ - * - */ - -/** - * @brief Interrupt event counter.[get] - * - * @param ctx read / write interface definitions - * @param val get the value of INT_COUNTER - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_int_count_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_INT_COUNTER, val, 1); - - return ret; -} - -/** - * @brief Temperature status register.[get] - * - * @param ctx read / write interface definitions - * @param buff buffer that stores data read - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff) -{ - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_STATUS_REG_AUX, buff, 1); - - return ret; -} -/** - * @brief Temperature data available.[get] - * - * @param ctx read / write interface definitions - * @param val change the values of tda in reg STATUS_REG_AUX - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lis2dh_status_reg_aux_t status_reg_aux; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_STATUS_REG_AUX, - (uint8_t *)&status_reg_aux, 1); - *val = status_reg_aux.tda; - - return ret; -} - -/** - * @brief Temperature data overrun.[get] - * - * @param ctx read / write interface definitions - * @param val change the values of tor in reg STATUS_REG_AUX - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lis2dh_status_reg_aux_t status_reg_aux; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_STATUS_REG_AUX, - (uint8_t *)&status_reg_aux, 1); - *val = status_reg_aux.tor; - - return ret; -} -/** - * @brief Temperature output value.[get] - * - * @param ctx read / write interface definitions - * @param buff buffer that stores data read - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) -{ - uint8_t buff[2]; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_OUT_TEMP_L, buff, 2); - *val = (int16_t)buff[1]; - *val = (*val * 256) + (int16_t)buff[0]; - - return ret; -} -/** - * @brief Temperature sensor enable.[set] - * - * @param ctx read / write interface definitions - * @param val change the values of temp_en in reg TEMP_CFG_REG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_temperature_meas_set(stmdev_ctx_t *ctx, - lis2dh_temp_en_t val) -{ - lis2dh_temp_cfg_reg_t temp_cfg_reg; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_TEMP_CFG_REG, - (uint8_t *)&temp_cfg_reg, 1); - - if (ret == 0) - { - temp_cfg_reg.temp_en = (uint8_t) val; - ret = lis2dh_write_reg(ctx, LIS2DH_TEMP_CFG_REG, - (uint8_t *)&temp_cfg_reg, 1); - } - - return ret; -} - -/** - * @brief Temperature sensor enable.[get] - * - * @param ctx read / write interface definitions - * @param val get the values of temp_en in reg TEMP_CFG_REG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_temperature_meas_get(stmdev_ctx_t *ctx, - lis2dh_temp_en_t *val) -{ - lis2dh_temp_cfg_reg_t temp_cfg_reg; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_TEMP_CFG_REG, - (uint8_t *)&temp_cfg_reg, 1); - - switch (temp_cfg_reg.temp_en) - { - case LIS2DH_TEMP_DISABLE: - *val = LIS2DH_TEMP_DISABLE; - break; - - case LIS2DH_TEMP_ENABLE: - *val = LIS2DH_TEMP_ENABLE; - break; - - default: - *val = LIS2DH_TEMP_DISABLE; - break; - } - - return ret; -} - -/** - * @brief Operating mode selection.[set] - * - * @param ctx read / write interface definitions - * @param val change the values of lpen in reg CTRL_REG1 - * and HR in reg CTRL_REG4 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_operating_mode_set(stmdev_ctx_t *ctx, - lis2dh_op_md_t val) -{ - lis2dh_ctrl_reg1_t ctrl_reg1; - lis2dh_ctrl_reg4_t ctrl_reg4; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG1, - (uint8_t *)&ctrl_reg1, 1); - - if (ret == 0) - { - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG4, - (uint8_t *)&ctrl_reg4, 1); - } - - if (ret == 0) - { - if (val == LIS2DH_HR_12bit) - { - ctrl_reg1.lpen = 0; - ctrl_reg4.hr = 1; - } - - if (val == LIS2DH_NM_10bit) - { - ctrl_reg1.lpen = 0; - ctrl_reg4.hr = 0; - } - - if (val == LIS2DH_LP_8bit) - { - ctrl_reg1.lpen = 1; - ctrl_reg4.hr = 0; - } - - ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG1, - (uint8_t *)&ctrl_reg1, 1); - } - - if (ret == 0) - { - ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG4, - (uint8_t *)&ctrl_reg4, 1); - } - - return ret; -} - -/** - * @brief Operating mode selection.[get] - * - * @param ctx read / write interface definitions - * @param val change the values of lpen in reg CTRL_REG1 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_operating_mode_get(stmdev_ctx_t *ctx, - lis2dh_op_md_t *val) -{ - lis2dh_ctrl_reg1_t ctrl_reg1; - lis2dh_ctrl_reg4_t ctrl_reg4; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG1, - (uint8_t *)&ctrl_reg1, 1); - - if (ret == 0) - { - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG4, - (uint8_t *)&ctrl_reg4, 1); - - if (ctrl_reg1.lpen == PROPERTY_ENABLE) - { - *val = LIS2DH_LP_8bit; - } - - else if (ctrl_reg4.hr == PROPERTY_ENABLE) - { - *val = LIS2DH_HR_12bit; - } - - else - { - *val = LIS2DH_NM_10bit; - } - } - - return ret; -} - -/** - * @brief Output data rate selection.[set] - * - * @param ctx read / write interface definitions - * @param val change the values of odr in reg CTRL_REG1 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_data_rate_set(stmdev_ctx_t *ctx, lis2dh_odr_t val) -{ - lis2dh_ctrl_reg1_t ctrl_reg1; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG1, - (uint8_t *)&ctrl_reg1, 1); - - if (ret == 0) - { - ctrl_reg1.odr = (uint8_t)val; - ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG1, - (uint8_t *)&ctrl_reg1, 1); - } - - return ret; -} - -/** - * @brief Output data rate selection.[get] - * - * @param ctx read / write interface definitions - * @param val get the values of odr in reg CTRL_REG1 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_data_rate_get(stmdev_ctx_t *ctx, lis2dh_odr_t *val) -{ - lis2dh_ctrl_reg1_t ctrl_reg1; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG1, - (uint8_t *)&ctrl_reg1, 1); - - switch (ctrl_reg1.odr) - { - case LIS2DH_POWER_DOWN: - *val = LIS2DH_POWER_DOWN; - break; - - case LIS2DH_ODR_1Hz: - *val = LIS2DH_ODR_1Hz; - break; - - case LIS2DH_ODR_10Hz: - *val = LIS2DH_ODR_10Hz; - break; - - case LIS2DH_ODR_25Hz: - *val = LIS2DH_ODR_25Hz; - break; - - case LIS2DH_ODR_50Hz: - *val = LIS2DH_ODR_50Hz; - break; - - case LIS2DH_ODR_100Hz: - *val = LIS2DH_ODR_100Hz; - break; - - case LIS2DH_ODR_200Hz: - *val = LIS2DH_ODR_200Hz; - break; - - case LIS2DH_ODR_400Hz: - *val = LIS2DH_ODR_400Hz; - break; - - case LIS2DH_ODR_1kHz620_LP: - *val = LIS2DH_ODR_1kHz620_LP; - break; - - case LIS2DH_ODR_5kHz376_LP_1kHz344_NM_HP: - *val = LIS2DH_ODR_5kHz376_LP_1kHz344_NM_HP; - break; - - default: - *val = LIS2DH_POWER_DOWN; - break; - } - - return ret; -} - -/** - * @brief High pass data from internal filter sent to output register - * and FIFO. - * - * @param ctx read / write interface definitions - * @param val change the values of fds in reg CTRL_REG2 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_high_pass_on_outputs_set(stmdev_ctx_t *ctx, - uint8_t val) -{ - lis2dh_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG2, - (uint8_t *)&ctrl_reg2, 1); - - if (ret == 0) - { - ctrl_reg2.fds = val; - ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG2, - (uint8_t *)&ctrl_reg2, 1); - } - - return ret; -} - -/** - * @brief High pass data from internal filter sent to output register - * and FIFO.[get] - * - * @param ctx read / write interface definitions - * @param val change the values of fds in reg CTRL_REG2 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_high_pass_on_outputs_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - lis2dh_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG2, - (uint8_t *)&ctrl_reg2, 1); - *val = (uint8_t)ctrl_reg2.fds; - - return ret; -} - -/** - * @brief High-pass filter cutoff frequency selection.[set] - * - * HPCF[2:1]\ft @1Hz @10Hz @25Hz @50Hz @100Hz @200Hz @400Hz @1kHz6 ft@5kHz - * AGGRESSIVE 0.02Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 8Hz 32Hz 100Hz - * STRONG 0.008Hz 0.08Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 16Hz 50Hz - * MEDIUM 0.004Hz 0.04Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 2Hz 8Hz 25Hz - * LIGHT 0.002Hz 0.02Hz 0.05Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 4Hz 12Hz - * - * @param ctx read / write interface definitions - * @param val change the values of hpcf in reg CTRL_REG2 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_high_pass_bandwidth_set(stmdev_ctx_t *ctx, - lis2dh_hpcf_t val) -{ - lis2dh_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG2, - (uint8_t *)&ctrl_reg2, 1); - - if (ret == 0) - { - ctrl_reg2.hpcf = (uint8_t)val; - ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG2, - (uint8_t *)&ctrl_reg2, 1); - } - - return ret; -} - -/** - * @brief High-pass filter cutoff frequency selection.[get] - * - * HPCF[2:1]\ft @1Hz @10Hz @25Hz @50Hz @100Hz @200Hz @400Hz @1kHz6 ft@5kHz - * AGGRESSIVE 0.02Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 8Hz 32Hz 100Hz - * STRONG 0.008Hz 0.08Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 16Hz 50Hz - * MEDIUM 0.004Hz 0.04Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 2Hz 8Hz 25Hz - * LIGHT 0.002Hz 0.02Hz 0.05Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 4Hz 12Hz - * - * @param ctx read / write interface definitions - * @param val get the values of hpcf in reg CTRL_REG2 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_high_pass_bandwidth_get(stmdev_ctx_t *ctx, - lis2dh_hpcf_t *val) -{ - lis2dh_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG2, - (uint8_t *)&ctrl_reg2, 1); - - switch (ctrl_reg2.hpcf) - { - case LIS2DH_AGGRESSIVE: - *val = LIS2DH_AGGRESSIVE; - break; - - case LIS2DH_STRONG: - *val = LIS2DH_STRONG; - break; - - case LIS2DH_MEDIUM: - *val = LIS2DH_MEDIUM; - break; - - case LIS2DH_LIGHT: - *val = LIS2DH_LIGHT; - break; - - default: - *val = LIS2DH_LIGHT; - break; - } - - return ret; -} - -/** - * @brief High-pass filter mode selection.[set] - * - * @param ctx read / write interface definitions - * @param val change the values of hpm in reg CTRL_REG2 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_high_pass_mode_set(stmdev_ctx_t *ctx, - lis2dh_hpm_t val) -{ - lis2dh_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG2, - (uint8_t *)&ctrl_reg2, 1); - - if (ret == 0) - { - ctrl_reg2.hpm = (uint8_t)val; - ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG2, - (uint8_t *)&ctrl_reg2, 1); - } - - return ret; -} - -/** - * @brief High-pass filter mode selection.[get] - * - * @param ctx read / write interface definitions - * @param val get the values of hpm in reg CTRL_REG2 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_high_pass_mode_get(stmdev_ctx_t *ctx, - lis2dh_hpm_t *val) -{ - lis2dh_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG2, - (uint8_t *)&ctrl_reg2, 1); - - switch (ctrl_reg2.hpm) - { - case LIS2DH_NORMAL_WITH_RST: - *val = LIS2DH_NORMAL_WITH_RST; - break; - - case LIS2DH_REFERENCE_MODE: - *val = LIS2DH_REFERENCE_MODE; - break; - - case LIS2DH_NORMAL: - *val = LIS2DH_NORMAL; - break; - - case LIS2DH_AUTORST_ON_INT: - *val = LIS2DH_AUTORST_ON_INT; - break; - - default: - *val = LIS2DH_NORMAL_WITH_RST; - break; - } - - return ret; -} - -/** - * @brief Full-scale configuration.[set] - * - * @param ctx read / write interface definitions - * @param val change the values of fs in reg CTRL_REG4 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_full_scale_set(stmdev_ctx_t *ctx, lis2dh_fs_t val) -{ - lis2dh_ctrl_reg4_t ctrl_reg4; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG4, - (uint8_t *)&ctrl_reg4, 1); - - if (ret == 0) - { - ctrl_reg4.fs = (uint8_t)val; - ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG4, - (uint8_t *)&ctrl_reg4, 1); - } - - return ret; -} - -/** - * @brief Full-scale configuration.[get] - * - * @param ctx read / write interface definitions - * @param val get the values of fs in reg CTRL_REG4 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_full_scale_get(stmdev_ctx_t *ctx, lis2dh_fs_t *val) -{ - lis2dh_ctrl_reg4_t ctrl_reg4; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG4, - (uint8_t *)&ctrl_reg4, 1); - - switch (ctrl_reg4.fs) - { - case LIS2DH_2g: - *val = LIS2DH_2g; - break; - - case LIS2DH_4g: - *val = LIS2DH_4g; - break; - - case LIS2DH_8g: - *val = LIS2DH_8g; - break; - - case LIS2DH_16g: - *val = LIS2DH_16g; - break; - - default: - *val = LIS2DH_2g; - break; - } - - return ret; -} - -/** - * @brief Block Data Update.[set] - * - * @param ctx read / write interface definitions - * @param val change the values of bdu in reg CTRL_REG4 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lis2dh_ctrl_reg4_t ctrl_reg4; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG4, - (uint8_t *)&ctrl_reg4, 1); - - if (ret == 0) - { - ctrl_reg4.bdu = val; - ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG4, - (uint8_t *)&ctrl_reg4, 1); - } - - return ret; -} - -/** - * @brief Block Data Update.[get] - * - * @param ctx read / write interface definitions - * @param val change the values of bdu in reg CTRL_REG4 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_block_data_update_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - lis2dh_ctrl_reg4_t ctrl_reg4; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG4, - (uint8_t *)&ctrl_reg4, 1); - *val = (uint8_t)ctrl_reg4.bdu; - - return ret; -} - -/** - * @brief Reference value for interrupt generation.[set] - * LSB = ~16@2g / ~31@4g / ~63@8g / ~127@16g - * - * @param ctx read / write interface definitions - * @param buff buffer that contains data to write - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_filter_reference_set(stmdev_ctx_t *ctx, - uint8_t *buff) -{ - int32_t ret; - - ret = lis2dh_write_reg(ctx, LIS2DH_REFERENCE, buff, 1); - - return ret; -} - -/** - * @brief Reference value for interrupt generation.[get] - * LSB = ~16@2g / ~31@4g / ~63@8g / ~127@16g - * - * @param ctx read / write interface definitions - * @param buff buffer that stores data read - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_filter_reference_get(stmdev_ctx_t *ctx, - uint8_t *buff) -{ - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_REFERENCE, buff, 1); - - return ret; -} -/** - * @brief Acceleration set of data available.[get] - * - * @param ctx read / write interface definitions - * @param val change the values of zyxda in reg STATUS_REG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lis2dh_status_reg_t status_reg; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_STATUS_REG, - (uint8_t *)&status_reg, 1); - *val = status_reg.zyxda; - - return ret; -} -/** - * @brief Acceleration set of data overrun.[get] - * - * @param ctx read / write interface definitions - * @param val change the values of zyxor in reg STATUS_REG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lis2dh_status_reg_t status_reg; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_STATUS_REG, - (uint8_t *)&status_reg, 1); - *val = status_reg.zyxor; - - return ret; -} -/** - * @brief Acceleration output value.[get] - * - * @param ctx read / write interface definitions - * @param buff buffer that stores data read - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) -{ - uint8_t buff[6]; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_OUT_X_L, buff, 6); - val[0] = (int16_t)buff[1]; - val[0] = (val[0] * 256) + (int16_t)buff[0]; - val[1] = (int16_t)buff[3]; - val[1] = (val[1] * 256) + (int16_t)buff[2]; - val[2] = (int16_t)buff[5]; - val[2] = (val[2] * 256) + (int16_t)buff[4]; - - return ret; -} -/** - * @} - * - */ - -/** - * @defgroup LIS2DH_Common - * @brief This section group common useful functions - * @{ - * - */ - -/** - * @brief DeviceWhoamI .[get] - * - * @param ctx read / write interface definitions - * @param buff buffer that stores data read - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) -{ - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_WHO_AM_I, buff, 1); - - return ret; -} -/** - * @brief Self Test.[set] - * - * @param ctx read / write interface definitions - * @param val change the values of st in reg CTRL_REG4 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_self_test_set(stmdev_ctx_t *ctx, lis2dh_st_t val) -{ - lis2dh_ctrl_reg4_t ctrl_reg4; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG4, - (uint8_t *)&ctrl_reg4, 1); - - if (ret == 0) - { - ctrl_reg4.st = (uint8_t)val; - ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG4, - (uint8_t *)&ctrl_reg4, 1); - } - - return ret; -} - -/** - * @brief Self Test.[get] - * - * @param ctx read / write interface definitions - * @param val Get the values of st in reg CTRL_REG4 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_self_test_get(stmdev_ctx_t *ctx, lis2dh_st_t *val) -{ - lis2dh_ctrl_reg4_t ctrl_reg4; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG4, - (uint8_t *)&ctrl_reg4, 1); - - switch (ctrl_reg4.st) - { - case LIS2DH_ST_DISABLE: - *val = LIS2DH_ST_DISABLE; - break; - - case LIS2DH_ST_POSITIVE: - *val = LIS2DH_ST_POSITIVE; - break; - - case LIS2DH_ST_NEGATIVE: - *val = LIS2DH_ST_NEGATIVE; - break; - - default: - *val = LIS2DH_ST_DISABLE; - break; - } - - return ret; -} - -/** - * @brief Big/Little Endian data selection.[set] - * - * @param ctx read / write interface definitions - * @param val change the values of ble in reg CTRL_REG4 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_data_format_set(stmdev_ctx_t *ctx, - lis2dh_ble_t val) -{ - lis2dh_ctrl_reg4_t ctrl_reg4; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG4, - (uint8_t *)&ctrl_reg4, 1); - - if (ret == 0) - { - ctrl_reg4.ble = (uint8_t)val; - ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG4, - (uint8_t *)&ctrl_reg4, 1); - } - - return ret; -} - -/** - * @brief Big/Little Endian data selection.[get] - * - * @param ctx read / write interface definitions - * @param val get the values of ble in reg CTRL_REG4 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_data_format_get(stmdev_ctx_t *ctx, - lis2dh_ble_t *val) -{ - lis2dh_ctrl_reg4_t ctrl_reg4; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG4, - (uint8_t *)&ctrl_reg4, 1); - - switch (ctrl_reg4.ble) - { - case LIS2DH_LSB_AT_LOW_ADD: - *val = LIS2DH_LSB_AT_LOW_ADD; - break; - - case LIS2DH_MSB_AT_LOW_ADD: - *val = LIS2DH_MSB_AT_LOW_ADD; - break; - - default: - *val = LIS2DH_LSB_AT_LOW_ADD; - break; - } - - return ret; -} - -/** - * @brief Reboot memory content. Reload the calibration parameters.[set] - * - * @param ctx read / write interface definitions - * @param val change the values of boot in reg CTRL_REG5 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_boot_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lis2dh_ctrl_reg5_t ctrl_reg5; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG5, - (uint8_t *)&ctrl_reg5, 1); - - if (ret == 0) - { - ctrl_reg5.boot = val; - ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG5, - (uint8_t *)&ctrl_reg5, 1); - } - - return ret; -} - -/** - * @brief Reboot memory content. Reload the calibration parameters.[get] - * - * @param ctx read / write interface definitions - * @param val change the values of boot in reg CTRL_REG5 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_boot_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lis2dh_ctrl_reg5_t ctrl_reg5; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG5, - (uint8_t *)&ctrl_reg5, 1); - *val = (uint8_t)ctrl_reg5.boot; - - return ret; -} - -/** - * @brief Info about device status.[get] - * - * @param ctx read / write interface definitions - * @param val register STATUS_REG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_status_get(stmdev_ctx_t *ctx, - lis2dh_status_reg_t *val) -{ - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_STATUS_REG, (uint8_t *) val, 1); - - return ret; -} -/** - * @} - * - */ - -/** - * @defgroup LIS2DH_Interrupts_generator_1 - * @brief This section group all the functions that manage the first - * interrupts generator - * @{ - * - */ - -/** - * @brief Interrupt generator 1 configuration register.[set] - * - * @param ctx read / write interface definitions - * @param val register INT1_CFG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_int1_gen_conf_set(stmdev_ctx_t *ctx, - lis2dh_int1_cfg_t *val) -{ - int32_t ret; - - ret = lis2dh_write_reg(ctx, LIS2DH_INT1_CFG, (uint8_t *) val, 1); - - return ret; -} - -/** - * @brief Interrupt generator 1 configuration register.[get] - * - * @param ctx read / write interface definitions - * @param val register INT1_CFG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_int1_gen_conf_get(stmdev_ctx_t *ctx, - lis2dh_int1_cfg_t *val) -{ - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_INT1_CFG, (uint8_t *) val, 1); - - return ret; -} - -/** - * @brief Interrupt generator 1 source register.[get] - * - * @param ctx read / write interface definitions - * @param val Registers INT1_SRC - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_int1_gen_source_get(stmdev_ctx_t *ctx, - lis2dh_int1_src_t *val) -{ - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_INT1_SRC, (uint8_t *) val, 1); - - return ret; -} -/** - * @brief User-defined threshold value for xl interrupt event on - * generator 1.[set] - * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g - * - * @param ctx read / write interface definitions - * @param val change the values of ths in reg INT1_THS - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_int1_gen_threshold_set(stmdev_ctx_t *ctx, - uint8_t val) -{ - lis2dh_int1_ths_t int1_ths; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_INT1_THS, (uint8_t *)&int1_ths, 1); - - if (ret == 0) - { - int1_ths.ths = val; - ret = lis2dh_write_reg(ctx, LIS2DH_INT1_THS, (uint8_t *)&int1_ths, 1); - } - - return ret; -} - -/** - * @brief User-defined threshold value for xl interrupt event on - * generator 1.[get] - * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g - * - * @param ctx read / write interface definitions - * @param val change the values of ths in reg INT1_THS - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_int1_gen_threshold_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - lis2dh_int1_ths_t int1_ths; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_INT1_THS, (uint8_t *)&int1_ths, 1); - *val = (uint8_t)int1_ths.ths; - - return ret; -} - -/** - * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be - * recognized.[set] - * - * @param ctx read / write interface definitions - * @param val change the values of d in reg INT1_DURATION - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lis2dh_int1_duration_t int1_duration; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_INT1_DURATION, - (uint8_t *)&int1_duration, 1); - - if (ret == 0) - { - int1_duration.d = val; - ret = lis2dh_write_reg(ctx, LIS2DH_INT1_DURATION, - (uint8_t *)&int1_duration, 1); - } - - return ret; -} - -/** - * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be - * recognized.[get] - * - * @param ctx read / write interface definitions - * @param val change the values of d in reg INT1_DURATION - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_int1_gen_duration_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - lis2dh_int1_duration_t int1_duration; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_INT1_DURATION, - (uint8_t *)&int1_duration, 1); - *val = (uint8_t)int1_duration.d; - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LIS2DH_Interrupts_generator_2 - * @brief This section group all the functions that manage the second - * interrupts generator - * @{ - * - */ - -/** - * @brief Interrupt generator 2 configuration register.[set] - * - * @param ctx read / write interface definitions - * @param val registers INT2_CFG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_int2_gen_conf_set(stmdev_ctx_t *ctx, - lis2dh_int2_cfg_t *val) -{ - int32_t ret; - - ret = lis2dh_write_reg(ctx, LIS2DH_INT2_CFG, (uint8_t *) val, 1); - - return ret; -} - -/** - * @brief Interrupt generator 2 configuration register.[get] - * - * @param ctx read / write interface definitions - * @param val registers INT2_CFG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_int2_gen_conf_get(stmdev_ctx_t *ctx, - lis2dh_int2_cfg_t *val) -{ - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_INT2_CFG, (uint8_t *) val, 1); - - return ret; -} -/** - * @brief Interrupt generator 2 source register.[get] - * - * @param ctx read / write interface definitions - * @param val registers INT2_SRC - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_int2_gen_source_get(stmdev_ctx_t *ctx, - lis2dh_int2_src_t *val) -{ - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_INT2_SRC, (uint8_t *) val, 1); - - return ret; -} -/** - * @brief User-defined threshold value for xl interrupt event on - * generator 2.[set] - * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g - * - * @param ctx read / write interface definitions - * @param val change the values of ths in reg INT2_THS - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_int2_gen_threshold_set(stmdev_ctx_t *ctx, - uint8_t val) -{ - lis2dh_int2_ths_t int2_ths; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_INT2_THS, (uint8_t *)&int2_ths, 1); - - if (ret == 0) - { - int2_ths.ths = val; - ret = lis2dh_write_reg(ctx, LIS2DH_INT2_THS, (uint8_t *)&int2_ths, 1); - } - - return ret; -} - -/** - * @brief User-defined threshold value for xl interrupt event on - * generator 2.[get] - * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g - * - * @param ctx read / write interface definitions - * @param val change the values of ths in reg INT2_THS - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_int2_gen_threshold_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - lis2dh_int2_ths_t int2_ths; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_INT2_THS, (uint8_t *)&int2_ths, 1); - *val = (uint8_t)int2_ths.ths; - - return ret; -} - -/** - * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be - * recognized .[set] - * - * @param ctx read / write interface definitions - * @param val change the values of d in reg INT2_DURATION - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lis2dh_int2_duration_t int2_duration; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_INT2_DURATION, - (uint8_t *)&int2_duration, 1); - - if (ret == 0) - { - int2_duration.d = val; - ret = lis2dh_write_reg(ctx, LIS2DH_INT2_DURATION, - (uint8_t *)&int2_duration, 1); - } - - return ret; -} - -/** - * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be - * recognized.[get] - * - * @param ctx read / write interface definitions - * @param val change the values of d in reg INT2_DURATION - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_int2_gen_duration_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - lis2dh_int2_duration_t int2_duration; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_INT2_DURATION, - (uint8_t *)&int2_duration, 1); - *val = (uint8_t)int2_duration.d; - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LIS2DH_Interrupt_pins - * @brief This section group all the functions that manage interrupt pins - * @{ - * - */ - -/** - * @brief High-pass filter on interrupts/tap generator.[set] - * - * @param ctx read / write interface definitions - * @param val change the values of hp in reg CTRL_REG2 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_high_pass_int_conf_set(stmdev_ctx_t *ctx, - lis2dh_hp_t val) -{ - lis2dh_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG2, - (uint8_t *)&ctrl_reg2, 1); - - if (ret == 0) - { - ctrl_reg2.hp = (uint8_t)val; - ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG2, - (uint8_t *)&ctrl_reg2, 1); - } - - return ret; -} - -/** - * @brief High-pass filter on interrupts/tap generator.[get] - * - * @param ctx read / write interface definitions - * @param val Get the values of hp in reg CTRL_REG2 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_high_pass_int_conf_get(stmdev_ctx_t *ctx, - lis2dh_hp_t *val) -{ - lis2dh_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG2, - (uint8_t *)&ctrl_reg2, 1); - - switch (ctrl_reg2.hp) - { - case LIS2DH_DISC_FROM_INT_GENERATOR: - *val = LIS2DH_DISC_FROM_INT_GENERATOR; - break; - - case LIS2DH_ON_INT1_GEN: - *val = LIS2DH_ON_INT1_GEN; - break; - - case LIS2DH_ON_INT2_GEN: - *val = LIS2DH_ON_INT2_GEN; - break; - - case LIS2DH_ON_TAP_GEN: - *val = LIS2DH_ON_TAP_GEN; - break; - - case LIS2DH_ON_INT1_INT2_GEN: - *val = LIS2DH_ON_INT1_INT2_GEN; - break; - - case LIS2DH_ON_INT1_TAP_GEN: - *val = LIS2DH_ON_INT1_TAP_GEN; - break; - - case LIS2DH_ON_INT2_TAP_GEN: - *val = LIS2DH_ON_INT2_TAP_GEN; - break; - - case LIS2DH_ON_INT1_INT2_TAP_GEN: - *val = LIS2DH_ON_INT1_INT2_TAP_GEN; - break; - - default: - *val = LIS2DH_DISC_FROM_INT_GENERATOR; - break; - } - - return ret; -} - -/** - * @brief Int1 pin routing configuration register.[set] - * - * @param ctx read / write interface definitions - * @param val registers CTRL_REG3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_pin_int1_config_set(stmdev_ctx_t *ctx, - lis2dh_ctrl_reg3_t *val) -{ - int32_t ret; - - ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG3, (uint8_t *) val, 1); - - return ret; -} - -/** - * @brief Int1 pin routing configuration register.[get] - * - * @param ctx read / write interface definitions - * @param val registers CTRL_REG3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_pin_int1_config_get(stmdev_ctx_t *ctx, - lis2dh_ctrl_reg3_t *val) -{ - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG3, (uint8_t *) val, 1); - - return ret; -} -/** - * @brief int2_pin_detect_4d: [set] 4D enable: 4D detection is enabled - * on INT2 pin when 6D bit on - * INT2_CFG (34h) is set to 1. - * - * @param ctx read / write interface definitions - * @param val change the values of d4d_int2 in reg CTRL_REG5 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, - uint8_t val) -{ - lis2dh_ctrl_reg5_t ctrl_reg5; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG5, - (uint8_t *)&ctrl_reg5, 1); - - if (ret == 0) - { - ctrl_reg5.d4d_int2 = val; - ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG5, - (uint8_t *)&ctrl_reg5, 1); - } - - return ret; -} - -/** - * @brief 4D enable: 4D detection is enabled on INT2 pin when 6D bit on - * INT2_CFG (34h) is set to 1.[get] - * - * @param ctx read / write interface definitions - * @param val change the values of d4d_int2 in reg CTRL_REG5 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - lis2dh_ctrl_reg5_t ctrl_reg5; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG5, - (uint8_t *)&ctrl_reg5, 1); - *val = (uint8_t)ctrl_reg5.d4d_int2; - - return ret; -} - -/** - * @brief Latch interrupt request on INT2_SRC (35h) register, with - * INT2_SRC (35h) register cleared by reading INT2_SRC(35h) - * itself.[set] - * - * @param ctx read / write interface definitions - * @param val change the values of lir_int2 in reg CTRL_REG5 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_int2_pin_notification_mode_set(stmdev_ctx_t *ctx, - lis2dh_lir_int2_t val) -{ - lis2dh_ctrl_reg5_t ctrl_reg5; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG5, - (uint8_t *)&ctrl_reg5, 1); - - if (ret == 0) - { - ctrl_reg5.lir_int2 = (uint8_t)val; - ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG5, - (uint8_t *)&ctrl_reg5, 1); - } - - return ret; -} - -/** - * @brief Latch interrupt request on INT2_SRC (35h) register, with - * INT2_SRC (35h) register cleared by reading INT2_SRC(35h) - * itself.[get] - * - * @param ctx read / write interface definitions - * @param val Get the values of lir_int2 in reg CTRL_REG5 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_int2_pin_notification_mode_get(stmdev_ctx_t *ctx, - lis2dh_lir_int2_t *val) -{ - lis2dh_ctrl_reg5_t ctrl_reg5; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG5, - (uint8_t *)&ctrl_reg5, 1); - - switch (ctrl_reg5.lir_int2) - { - case LIS2DH_INT2_PULSED: - *val = LIS2DH_INT2_PULSED; - break; - - case LIS2DH_INT2_LATCHED: - *val = LIS2DH_INT2_LATCHED; - break; - - default: - *val = LIS2DH_INT2_PULSED; - break; - } - - return ret; -} - -/** - * @brief 4D enable: 4D detection is enabled on INT1 pin when 6D bit - * on INT1_CFG(30h) is set to 1.[set] - * - * @param ctx read / write interface definitions - * @param val change the values of d4d_int1 in reg CTRL_REG5 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, - uint8_t val) -{ - lis2dh_ctrl_reg5_t ctrl_reg5; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG5, - (uint8_t *)&ctrl_reg5, 1); - - if (ret == 0) - { - ctrl_reg5.d4d_int1 = val; - ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG5, - (uint8_t *)&ctrl_reg5, 1); - } - - return ret; -} - -/** - * @brief 4D enable: 4D detection is enabled on INT1 pin when 6D bit on - * INT1_CFG(30h) is set to 1.[get] - * - * @param ctx read / write interface definitions - * @param val change the values of d4d_int1 in reg CTRL_REG5 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - lis2dh_ctrl_reg5_t ctrl_reg5; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG5, - (uint8_t *)&ctrl_reg5, 1); - *val = (uint8_t)ctrl_reg5.d4d_int1; - - return ret; -} - -/** - * @brief Latch interrupt request on INT1_SRC (31h), with INT1_SRC(31h) - * register cleared by reading INT1_SRC (31h) itself.[set] - * - * @param ctx read / write interface definitions - * @param val change the values of lir_int1 in reg CTRL_REG5 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_int1_pin_notification_mode_set(stmdev_ctx_t *ctx, - lis2dh_lir_int1_t val) -{ - lis2dh_ctrl_reg5_t ctrl_reg5; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG5, - (uint8_t *)&ctrl_reg5, 1); - - if (ret == 0) - { - ctrl_reg5.lir_int1 = (uint8_t)val; - ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG5, - (uint8_t *)&ctrl_reg5, 1); - } - - return ret; -} - -/** - * @brief Latch interrupt request on INT1_SRC (31h), with INT1_SRC(31h) - * register cleared by reading INT1_SRC (31h) itself.[get] - * - * @param ctx read / write interface definitions - * @param val Get the values of lir_int1 in reg CTRL_REG5 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_int1_pin_notification_mode_get(stmdev_ctx_t *ctx, - lis2dh_lir_int1_t *val) -{ - lis2dh_ctrl_reg5_t ctrl_reg5; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG5, - (uint8_t *)&ctrl_reg5, 1); - - switch (ctrl_reg5.lir_int1) - { - case LIS2DH_INT1_PULSED: - *val = LIS2DH_INT1_PULSED; - break; - - case LIS2DH_INT1_LATCHED: - *val = LIS2DH_INT1_LATCHED; - break; - - default: - *val = LIS2DH_INT1_PULSED; - break; - } - - return ret; -} - -/** - * @brief Int2 pin routing configuration register.[set] - * - * @param ctx read / write interface definitions - * @param val registers CTRL_REG6 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_pin_int2_config_set(stmdev_ctx_t *ctx, - lis2dh_ctrl_reg6_t *val) -{ - int32_t ret; - - ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG6, (uint8_t *) val, 1); - - return ret; -} - -/** - * @brief Int2 pin routing configuration register.[get] - * - * @param ctx read / write interface definitions - * @param val registers CTRL_REG6 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_pin_int2_config_get(stmdev_ctx_t *ctx, - lis2dh_ctrl_reg6_t *val) -{ - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG6, (uint8_t *) val, 1); - - return ret; -} -/** - * @} - * - */ - -/** - * @defgroup LIS2DH_Fifo - * @brief This section group all the functions concerning the fifo usage - * @{ - * - */ - -/** - * @brief FIFO enable.[set] - * - * @param ctx read / write interface definitions - * @param val change the values of fifo_en in reg CTRL_REG5 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_fifo_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lis2dh_ctrl_reg5_t ctrl_reg5; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG5, - (uint8_t *)&ctrl_reg5, 1); - - if (ret == 0) - { - ctrl_reg5.fifo_en = val; - ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG5, - (uint8_t *)&ctrl_reg5, 1); - } - - return ret; -} - -/** - * @brief FIFO enable.[get] - * - * @param ctx read / write interface definitions - * @param val change the values of fifo_en in reg CTRL_REG5 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_fifo_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lis2dh_ctrl_reg5_t ctrl_reg5; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG5, - (uint8_t *)&ctrl_reg5, 1); - *val = (uint8_t)ctrl_reg5.fifo_en; - - return ret; -} - -/** - * @brief FIFO watermark level selection.[set] - * - * @param ctx read / write interface definitions - * @param val change the values of fth in reg FIFO_CTRL_REG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lis2dh_fifo_ctrl_reg_t fifo_ctrl_reg; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_FIFO_CTRL_REG, - (uint8_t *)&fifo_ctrl_reg, 1); - - if (ret == 0) - { - fifo_ctrl_reg.fth = val; - ret = lis2dh_write_reg(ctx, LIS2DH_FIFO_CTRL_REG, - (uint8_t *)&fifo_ctrl_reg, 1); - } - - return ret; -} - -/** - * @brief FIFO watermark level selection.[get] - * - * @param ctx read / write interface definitions - * @param val change the values of fth in reg FIFO_CTRL_REG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lis2dh_fifo_ctrl_reg_t fifo_ctrl_reg; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_FIFO_CTRL_REG, - (uint8_t *)&fifo_ctrl_reg, 1); - *val = (uint8_t)fifo_ctrl_reg.fth; - - return ret; -} - -/** - * @brief Trigger FIFO selection.[set] - * - * @param ctx read / write interface definitions - * @param val change the values of tr in reg FIFO_CTRL_REG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_fifo_trigger_event_set(stmdev_ctx_t *ctx, - lis2dh_tr_t val) -{ - lis2dh_fifo_ctrl_reg_t fifo_ctrl_reg; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_FIFO_CTRL_REG, - (uint8_t *)&fifo_ctrl_reg, 1); - - if (ret == 0) - { - fifo_ctrl_reg.tr = (uint8_t)val; - ret = lis2dh_write_reg(ctx, LIS2DH_FIFO_CTRL_REG, - (uint8_t *)&fifo_ctrl_reg, 1); - } - - return ret; -} - -/** - * @brief Trigger FIFO selection.[get] - * - * @param ctx read / write interface definitions - * @param val Get the values of tr in reg FIFO_CTRL_REG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_fifo_trigger_event_get(stmdev_ctx_t *ctx, - lis2dh_tr_t *val) -{ - lis2dh_fifo_ctrl_reg_t fifo_ctrl_reg; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_FIFO_CTRL_REG, - (uint8_t *)&fifo_ctrl_reg, 1); - - switch (fifo_ctrl_reg.tr) - { - case LIS2DH_INT1_GEN: - *val = LIS2DH_INT1_GEN; - break; - - case LIS2DH_INT2_GEN: - *val = LIS2DH_INT2_GEN; - break; - - default: - *val = LIS2DH_INT1_GEN; - break; - } - - return ret; -} - -/** - * @brief FIFO mode selection.[set] - * - * @param ctx read / write interface definitions - * @param val change the values of fm in reg FIFO_CTRL_REG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_fifo_mode_set(stmdev_ctx_t *ctx, lis2dh_fm_t val) -{ - lis2dh_fifo_ctrl_reg_t fifo_ctrl_reg; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_FIFO_CTRL_REG, - (uint8_t *)&fifo_ctrl_reg, 1); - - if (ret == 0) - { - fifo_ctrl_reg.fm = (uint8_t)val; - ret = lis2dh_write_reg(ctx, LIS2DH_FIFO_CTRL_REG, - (uint8_t *)&fifo_ctrl_reg, 1); - } - - return ret; -} - -/** - * @brief FIFO mode selection.[get] - * - * @param ctx read / write interface definitions - * @param val Get the values of fm in reg FIFO_CTRL_REG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_fifo_mode_get(stmdev_ctx_t *ctx, lis2dh_fm_t *val) -{ - lis2dh_fifo_ctrl_reg_t fifo_ctrl_reg; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_FIFO_CTRL_REG, - (uint8_t *)&fifo_ctrl_reg, 1); - - switch (fifo_ctrl_reg.fm) - { - case LIS2DH_BYPASS_MODE: - *val = LIS2DH_BYPASS_MODE; - break; - - case LIS2DH_FIFO_MODE: - *val = LIS2DH_FIFO_MODE; - break; - - case LIS2DH_DYNAMIC_STREAM_MODE: - *val = LIS2DH_DYNAMIC_STREAM_MODE; - break; - - case LIS2DH_STREAM_TO_FIFO_MODE: - *val = LIS2DH_STREAM_TO_FIFO_MODE; - break; - - default: - *val = LIS2DH_BYPASS_MODE; - break; - } - - return ret; -} - -/** - * @brief FIFO status register.[get] - * - * @param ctx read / write interface definitions - * @param val registers FIFO_SRC_REG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_fifo_status_get(stmdev_ctx_t *ctx, - lis2dh_fifo_src_reg_t *val) -{ - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_FIFO_SRC_REG, (uint8_t *) val, 1); - - return ret; -} -/** - * @brief FIFO stored data level.[get] - * - * @param ctx read / write interface definitions - * @param val change the values of fss in reg FIFO_SRC_REG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lis2dh_fifo_src_reg_t fifo_src_reg; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_FIFO_SRC_REG, - (uint8_t *)&fifo_src_reg, 1); - *val = (uint8_t)fifo_src_reg.fss; - - return ret; -} -/** - * @brief Empty FIFO status flag.[get] - * - * @param ctx read / write interface definitions - * @param val change the values of empty in reg FIFO_SRC_REG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lis2dh_fifo_src_reg_t fifo_src_reg; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_FIFO_SRC_REG, - (uint8_t *)&fifo_src_reg, 1); - *val = (uint8_t)fifo_src_reg.empty; - - return ret; -} -/** - * @brief FIFO overrun status flag.[get] - * - * @param ctx read / write interface definitions - * @param val change the values of ovrn_fifo in reg FIFO_SRC_REG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lis2dh_fifo_src_reg_t fifo_src_reg; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_FIFO_SRC_REG, - (uint8_t *)&fifo_src_reg, 1); - *val = (uint8_t)fifo_src_reg.ovrn_fifo; - - return ret; -} -/** - * @brief FIFO watermark status.[get] - * - * @param ctx read / write interface definitions - * @param val change the values of wtm in reg FIFO_SRC_REG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lis2dh_fifo_src_reg_t fifo_src_reg; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_FIFO_SRC_REG, - (uint8_t *)&fifo_src_reg, 1); - *val = (uint8_t)fifo_src_reg.wtm; - - return ret; -} -/** - * @} - * - */ - -/** - * @defgroup LIS2DH_Tap_generator - * @brief This section group all the functions that manage the tap and - * double tap event generation - * @{ - * - */ - -/** - * @brief Tap/Double Tap generator configuration register.[set] - * - * @param ctx read / write interface definitions - * @param val registers CLICK_CFG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_tap_conf_set(stmdev_ctx_t *ctx, - lis2dh_click_cfg_t *val) -{ - int32_t ret; - - ret = lis2dh_write_reg(ctx, LIS2DH_CLICK_CFG, (uint8_t *) val, 1); - - return ret; -} - -/** - * @brief Tap/Double Tap generator configuration register.[get] - * - * @param ctx read / write interface definitions - * @param val registers CLICK_CFG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_tap_conf_get(stmdev_ctx_t *ctx, - lis2dh_click_cfg_t *val) -{ - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CLICK_CFG, (uint8_t *) val, 1); - - return ret; -} -/** - * @brief Tap/Double Tap generator source register.[get] - * - * @param ctx read / write interface definitions - * @param val registers CLICK_SRC - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_tap_source_get(stmdev_ctx_t *ctx, - lis2dh_click_src_t *val) -{ - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CLICK_SRC, (uint8_t *) val, 1); - - return ret; -} -/** - * @brief User-defined threshold value for Tap/Double Tap event.[set] - * 1 LSB = full scale/128 - * - * @param ctx read / write interface definitions - * @param val change the values of ths in reg CLICK_THS - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lis2dh_click_ths_t click_ths; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CLICK_THS, - (uint8_t *)&click_ths, 1); - - if (ret == 0) - { - click_ths.ths = val; - ret = lis2dh_write_reg(ctx, LIS2DH_CLICK_THS, - (uint8_t *)&click_ths, 1); - } - - return ret; -} - -/** - * @brief User-defined threshold value for Tap/Double Tap event.[get] - * 1 LSB = full scale/128 - * - * @param ctx read / write interface definitions - * @param val change the values of ths in reg CLICK_THS - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lis2dh_click_ths_t click_ths; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CLICK_THS, - (uint8_t *)&click_ths, 1); - *val = (uint8_t)click_ths.ths; - - return ret; -} - -/** - * @brief The maximum time (1 LSB = 1/ODR) interval that can elapse - * between the start of the click-detection procedure and when the - * acceleration falls back below the threshold.[set] - * - * @param ctx read / write interface definitions - * @param val change the values of tli in reg TIME_LIMIT - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lis2dh_time_limit_t time_limit; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_TIME_LIMIT, - (uint8_t *)&time_limit, 1); - - if (ret == 0) - { - time_limit.tli = val; - ret = lis2dh_write_reg(ctx, LIS2DH_TIME_LIMIT, - (uint8_t *)&time_limit, 1); - } - - return ret; -} - -/** - * @brief The maximum time (1 LSB = 1/ODR) interval that can elapse between - * the start of the click-detection procedure and when the - * acceleration falls back below the threshold.[get] - * - * @param ctx read / write interface definitions - * @param val change the values of tli in reg TIME_LIMIT - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lis2dh_time_limit_t time_limit; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_TIME_LIMIT, - (uint8_t *)&time_limit, 1); - *val = (uint8_t)time_limit.tli; - - return ret; -} - -/** - * @brief The time (1 LSB = 1/ODR) interval that starts after the first - * click detection where the click-detection procedure is - * disabled, in cases where the device is configured for - * double-click detection.[set] - * - * @param ctx read / write interface definitions - * @param val change the values of tla in reg TIME_LATENCY - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lis2dh_time_latency_t time_latency; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_TIME_LATENCY, - (uint8_t *)&time_latency, 1); - - if (ret == 0) - { - time_latency.tla = val; - ret = lis2dh_write_reg(ctx, LIS2DH_TIME_LATENCY, - (uint8_t *)&time_latency, 1); - } - - return ret; -} - -/** - * @brief The time (1 LSB = 1/ODR) interval that starts after the first - * click detection where the click-detection procedure is - * disabled, in cases where the device is configured for - * double-click detection.[get] - * - * @param ctx read / write interface definitions - * @param val change the values of tla in reg TIME_LATENCY - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lis2dh_time_latency_t time_latency; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_TIME_LATENCY, - (uint8_t *)&time_latency, 1); - *val = (uint8_t)time_latency.tla; - - return ret; -} - -/** - * @brief The maximum interval of time (1 LSB = 1/ODR) that can elapse - * after the end of the latency interval in which the click-detection - * procedure can start, in cases where the device is configured - * for double-click detection.[set] - * - * @param ctx read / write interface definitions - * @param val change the values of tw in reg TIME_WINDOW - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_double_tap_timeout_set(stmdev_ctx_t *ctx, - uint8_t val) -{ - lis2dh_time_window_t time_window; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_TIME_WINDOW, - (uint8_t *)&time_window, 1); - - if (ret == 0) - { - time_window.tw = val; - ret = lis2dh_write_reg(ctx, LIS2DH_TIME_WINDOW, - (uint8_t *)&time_window, 1); - } - - return ret; -} - -/** - * @brief The maximum interval of time (1 LSB = 1/ODR) that can elapse - * after the end of the latency interval in which the - * click-detection procedure can start, in cases where the device - * is configured for double-click detection.[get] - * - * @param ctx read / write interface definitions - * @param val change the values of tw in reg TIME_WINDOW - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_double_tap_timeout_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - lis2dh_time_window_t time_window; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_TIME_WINDOW, - (uint8_t *)&time_window, 1); - *val = (uint8_t)time_window.tw; - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LIS2DH_Activity_inactivity - * @brief This section group all the functions concerning activity - * inactivity functionality - * @{ - * - */ - -/** - * @brief Sleep-to-wake, return-to-sleep activation threshold in - * low-power mode.[set] - * 1 LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g - * - * @param ctx read / write interface definitions - * @param val change the values of acth in reg ACT_THS - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lis2dh_act_ths_t act_ths; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_ACT_THS, (uint8_t *)&act_ths, 1); - - if (ret == 0) - { - act_ths.acth = val; - ret = lis2dh_write_reg(ctx, LIS2DH_ACT_THS, (uint8_t *)&act_ths, 1); - } - - return ret; -} - -/** - * @brief Sleep-to-wake, return-to-sleep activation threshold in low-power - * mode.[get] - * 1 LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g - * - * @param ctx read / write interface definitions - * @param val change the values of acth in reg ACT_THS - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lis2dh_act_ths_t act_ths; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_ACT_THS, (uint8_t *)&act_ths, 1); - *val = (uint8_t)act_ths.acth; - - return ret; -} - -/** - * @brief Sleep-to-wake, return-to-sleep.[set] - * duration = (8*1[LSb]+1)/ODR - * - * @param ctx read / write interface definitions - * @param val change the values of actd in reg ACT_DUR - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lis2dh_act_dur_t act_dur; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_ACT_DUR, (uint8_t *)&act_dur, 1); - - if (ret == 0) - { - act_dur.actd = val; - ret = lis2dh_write_reg(ctx, LIS2DH_ACT_DUR, (uint8_t *)&act_dur, 1); - } - - return ret; -} - -/** - * @brief Sleep-to-wake, return-to-sleep.[get] - * duration = (8*1[LSb]+1)/ODR - * - * @param ctx read / write interface definitions - * @param val change the values of actd in reg ACT_DUR - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lis2dh_act_dur_t act_dur; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_ACT_DUR, (uint8_t *)&act_dur, 1); - *val = (uint8_t)act_dur.actd; - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LIS2DH_Serial_interface - * @brief This section group all the functions concerning serial - * interface management - * @{ - * - */ - -/** - * @brief SPI Serial Interface Mode selection.[set] - * - * @param ctx read / write interface definitions - * @param val change the values of sim in reg CTRL_REG4 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_spi_mode_set(stmdev_ctx_t *ctx, lis2dh_sim_t val) -{ - lis2dh_ctrl_reg4_t ctrl_reg4; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG4, - (uint8_t *)&ctrl_reg4, 1); - - if (ret == 0) - { - ctrl_reg4.sim = (uint8_t)val; - ret = lis2dh_write_reg(ctx, LIS2DH_CTRL_REG4, - (uint8_t *)&ctrl_reg4, 1); - } - - return ret; -} - -/** - * @brief SPI Serial Interface Mode selection.[get] - * - * @param ctx read / write interface definitions - * @param val Get the values of sim in reg CTRL_REG4 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis2dh_spi_mode_get(stmdev_ctx_t *ctx, lis2dh_sim_t *val) -{ - lis2dh_ctrl_reg4_t ctrl_reg4; - int32_t ret; - - ret = lis2dh_read_reg(ctx, LIS2DH_CTRL_REG4, - (uint8_t *)&ctrl_reg4, 1); - - switch (ctrl_reg4.sim) - { - case LIS2DH_SPI_4_WIRE: - *val = LIS2DH_SPI_4_WIRE; - break; - - case LIS2DH_SPI_3_WIRE: - *val = LIS2DH_SPI_3_WIRE; - break; - - default: - *val = LIS2DH_SPI_4_WIRE; - break; - } - - return ret; -} - -/** - * @} - * - */ - -/** - * @} - * - */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2dh_STdC/driver/lis2dh_reg.h b/sensor/stmemsc/lis2dh_STdC/driver/lis2dh_reg.h deleted file mode 100644 index ead648cd..00000000 --- a/sensor/stmemsc/lis2dh_STdC/driver/lis2dh_reg.h +++ /dev/null @@ -1,1042 +0,0 @@ -/** - ****************************************************************************** - * @file lis2dh_reg.h - * @author Sensors Software Solution Team - * @brief This file contains all the functions prototypes for the - * lis2dh_reg.c driver. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef LIS2DH_REGS_H -#define LIS2DH_REGS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include -#include -#include - -/** @addtogroup LIS2DH - * @{ - * - */ - -/** @defgroup Endianness definitions - * @{ - * - */ - -#ifndef DRV_BYTE_ORDER -#ifndef __BYTE_ORDER__ - -#define DRV_LITTLE_ENDIAN 1234 -#define DRV_BIG_ENDIAN 4321 - -/** if _BYTE_ORDER is not defined, choose the endianness of your architecture - * by uncommenting the define which fits your platform endianness - */ -//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN -#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN - -#else /* defined __BYTE_ORDER__ */ - -#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ -#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ -#define DRV_BYTE_ORDER __BYTE_ORDER__ - -#endif /* __BYTE_ORDER__*/ -#endif /* DRV_BYTE_ORDER */ - -/** - * @} - * - */ - -/** @defgroup STMicroelectronics sensors common types - * @{ - * - */ - -#ifndef MEMS_SHARED_TYPES -#define MEMS_SHARED_TYPES - -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t bit0 : 1; - uint8_t bit1 : 1; - uint8_t bit2 : 1; - uint8_t bit3 : 1; - uint8_t bit4 : 1; - uint8_t bit5 : 1; - uint8_t bit6 : 1; - uint8_t bit7 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t bit7 : 1; - uint8_t bit6 : 1; - uint8_t bit5 : 1; - uint8_t bit4 : 1; - uint8_t bit3 : 1; - uint8_t bit2 : 1; - uint8_t bit1 : 1; - uint8_t bit0 : 1; -#endif /* DRV_BYTE_ORDER */ -} bitwise_t; - -#define PROPERTY_DISABLE (0U) -#define PROPERTY_ENABLE (1U) - -/** @addtogroup Interfaces_Functions - * @brief This section provide a set of functions used to read and - * write a generic register of the device. - * MANDATORY: return 0 -> no Error. - * @{ - * - */ - -typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); -typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); -typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); - -typedef struct -{ - /** Component mandatory fields **/ - stmdev_write_ptr write_reg; - stmdev_read_ptr read_reg; - /** Component optional fields **/ - stmdev_mdelay_ptr mdelay; - /** Customizable optional pointer **/ - void *handle; -} stmdev_ctx_t; - -/** - * @} - * - */ - -#endif /* MEMS_SHARED_TYPES */ - -#ifndef MEMS_UCF_SHARED_TYPES -#define MEMS_UCF_SHARED_TYPES - -/** @defgroup Generic address-data structure definition - * @brief This structure is useful to load a predefined configuration - * of a sensor. - * You can create a sensor configuration by your own or using - * Unico / Unicleo tools available on STMicroelectronics - * web site. - * - * @{ - * - */ - -typedef struct -{ - uint8_t address; - uint8_t data; -} ucf_line_t; - -/** - * @} - * - */ - -#endif /* MEMS_UCF_SHARED_TYPES */ - -/** - * @} - * - */ - -/** @defgroup LIS2DH_Infos - * @{ - * - */ - -/** I2C Device Address 8 bit format if SA0=0 -> 31 if SA0=1 -> 33 **/ -#define LIS2DH_I2C_ADD_L 0x31U -#define LIS2DH_I2C_ADD_H 0x33U - -/** Device Identification (Who am I) **/ -#define LIS2DH_ID 0x33U - -/** - * @} - * - */ - -#define LIS2DH_STATUS_REG_AUX 0x07U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t not_used_01 : 2; - uint8_t tda : 1; - uint8_t not_used_02 : 3; - uint8_t tor : 1; - uint8_t not_used_03 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_03 : 1; - uint8_t tor : 1; - uint8_t not_used_02 : 3; - uint8_t tda : 1; - uint8_t not_used_01 : 2; -#endif /* DRV_BYTE_ORDER */ -} lis2dh_status_reg_aux_t; - -#define LIS2DH_OUT_TEMP_L 0x0CU -#define LIS2DH_OUT_TEMP_H 0x0DU -#define LIS2DH_INT_COUNTER 0x0EU -#define LIS2DH_WHO_AM_I 0x0FU -#define LIS2DH_TEMP_CFG_REG 0x1FU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t not_used_01 : 6; - uint8_t temp_en : 2; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t temp_en : 2; - uint8_t not_used_01 : 6; -#endif /* DRV_BYTE_ORDER */ -} lis2dh_temp_cfg_reg_t; - -#define LIS2DH_CTRL_REG1 0x20U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t xen : 1; - uint8_t yen : 1; - uint8_t zen : 1; - uint8_t lpen : 1; - uint8_t odr : 4; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t odr : 4; - uint8_t lpen : 1; - uint8_t zen : 1; - uint8_t yen : 1; - uint8_t xen : 1; -#endif /* DRV_BYTE_ORDER */ -} lis2dh_ctrl_reg1_t; - -#define LIS2DH_CTRL_REG2 0x21U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t hp : 3; /* HPCLICK + HPIS[1:2] -> HP */ - uint8_t fds : 1; - uint8_t hpcf : 2; - uint8_t hpm : 2; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t hpm : 2; - uint8_t hpcf : 2; - uint8_t fds : 1; - uint8_t hp : 3; /* HPCLICK + HPIS[1:2] -> HP */ -#endif /* DRV_BYTE_ORDER */ -} lis2dh_ctrl_reg2_t; - -#define LIS2DH_CTRL_REG3 0x22U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t not_used_01 : 1; - uint8_t i1_overrun : 1; - uint8_t i1_wtm : 1; - uint8_t i1_drdy2 : 1; - uint8_t i1_drdy1 : 1; - uint8_t i1_aoi2 : 1; - uint8_t i1_aoi1 : 1; - uint8_t i1_click : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t i1_click : 1; - uint8_t i1_aoi1 : 1; - uint8_t i1_aoi2 : 1; - uint8_t i1_drdy1 : 1; - uint8_t i1_drdy2 : 1; - uint8_t i1_wtm : 1; - uint8_t i1_overrun : 1; - uint8_t not_used_01 : 1; -#endif /* DRV_BYTE_ORDER */ -} lis2dh_ctrl_reg3_t; - -#define LIS2DH_CTRL_REG4 0x23U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t sim : 1; - uint8_t st : 2; - uint8_t hr : 1; - uint8_t fs : 2; - uint8_t ble : 1; - uint8_t bdu : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t bdu : 1; - uint8_t ble : 1; - uint8_t fs : 2; - uint8_t hr : 1; - uint8_t st : 2; - uint8_t sim : 1; -#endif /* DRV_BYTE_ORDER */ -} lis2dh_ctrl_reg4_t; - -#define LIS2DH_CTRL_REG5 0x24U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t d4d_int2 : 1; - uint8_t lir_int2 : 1; - uint8_t d4d_int1 : 1; - uint8_t lir_int1 : 1; - uint8_t not_used_01 : 2; - uint8_t fifo_en : 1; - uint8_t boot : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t boot : 1; - uint8_t fifo_en : 1; - uint8_t not_used_01 : 2; - uint8_t lir_int1 : 1; - uint8_t d4d_int1 : 1; - uint8_t lir_int2 : 1; - uint8_t d4d_int2 : 1; -#endif /* DRV_BYTE_ORDER */ -} lis2dh_ctrl_reg5_t; - -#define LIS2DH_CTRL_REG6 0x25U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t not_used_01 : 1; - uint8_t h_lactive : 1; - uint8_t not_used_02 : 1; - uint8_t p2_act : 1; - uint8_t boot_i2 : 1; - uint8_t i2_int2 : 1; - uint8_t i2_int1 : 1; - uint8_t i2_clicken : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t i2_clicken : 1; - uint8_t i2_int1 : 1; - uint8_t i2_int2 : 1; - uint8_t boot_i2 : 1; - uint8_t p2_act : 1; - uint8_t not_used_02 : 1; - uint8_t h_lactive : 1; - uint8_t not_used_01 : 1; -#endif /* DRV_BYTE_ORDER */ -} lis2dh_ctrl_reg6_t; - -#define LIS2DH_REFERENCE 0x26U -#define LIS2DH_STATUS_REG 0x27U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t xda : 1; - uint8_t yda : 1; - uint8_t zda : 1; - uint8_t zyxda : 1; - uint8_t _xor : 1; - uint8_t yor : 1; - uint8_t zor : 1; - uint8_t zyxor : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t zyxor : 1; - uint8_t zor : 1; - uint8_t yor : 1; - uint8_t _xor : 1; - uint8_t zyxda : 1; - uint8_t zda : 1; - uint8_t yda : 1; - uint8_t xda : 1; -#endif /* DRV_BYTE_ORDER */ -} lis2dh_status_reg_t; - -#define LIS2DH_OUT_X_L 0x28U -#define LIS2DH_OUT_X_H 0x29U -#define LIS2DH_OUT_Y_L 0x2AU -#define LIS2DH_OUT_Y_H 0x2BU -#define LIS2DH_OUT_Z_L 0x2CU -#define LIS2DH_OUT_Z_H 0x2DU -#define LIS2DH_FIFO_CTRL_REG 0x2EU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t fth : 5; - uint8_t tr : 1; - uint8_t fm : 2; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t fm : 2; - uint8_t tr : 1; - uint8_t fth : 5; -#endif /* DRV_BYTE_ORDER */ -} lis2dh_fifo_ctrl_reg_t; - -#define LIS2DH_FIFO_SRC_REG 0x2FU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t fss : 5; - uint8_t empty : 1; - uint8_t ovrn_fifo : 1; - uint8_t wtm : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t wtm : 1; - uint8_t ovrn_fifo : 1; - uint8_t empty : 1; - uint8_t fss : 5; -#endif /* DRV_BYTE_ORDER */ -} lis2dh_fifo_src_reg_t; - -#define LIS2DH_INT1_CFG 0x30U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t xlie : 1; - uint8_t xhie : 1; - uint8_t ylie : 1; - uint8_t yhie : 1; - uint8_t zlie : 1; - uint8_t zhie : 1; - uint8_t _6d : 1; - uint8_t aoi : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t aoi : 1; - uint8_t _6d : 1; - uint8_t zhie : 1; - uint8_t zlie : 1; - uint8_t yhie : 1; - uint8_t ylie : 1; - uint8_t xhie : 1; - uint8_t xlie : 1; -#endif /* DRV_BYTE_ORDER */ -} lis2dh_int1_cfg_t; - -#define LIS2DH_INT1_SRC 0x31U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t xl : 1; - uint8_t xh : 1; - uint8_t yl : 1; - uint8_t yh : 1; - uint8_t zl : 1; - uint8_t zh : 1; - uint8_t ia : 1; - uint8_t not_used_01 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 1; - uint8_t ia : 1; - uint8_t zh : 1; - uint8_t zl : 1; - uint8_t yh : 1; - uint8_t yl : 1; - uint8_t xh : 1; - uint8_t xl : 1; -#endif /* DRV_BYTE_ORDER */ -} lis2dh_int1_src_t; - -#define LIS2DH_INT1_THS 0x32U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t ths : 7; - uint8_t not_used_01 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 1; - uint8_t ths : 7; -#endif /* DRV_BYTE_ORDER */ -} lis2dh_int1_ths_t; - -#define LIS2DH_INT1_DURATION 0x33U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t d : 7; - uint8_t not_used_01 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 1; - uint8_t d : 7; -#endif /* DRV_BYTE_ORDER */ -} lis2dh_int1_duration_t; - -#define LIS2DH_INT2_CFG 0x34U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t xlie : 1; - uint8_t xhie : 1; - uint8_t ylie : 1; - uint8_t yhie : 1; - uint8_t zlie : 1; - uint8_t zhie : 1; - uint8_t _6d : 1; - uint8_t aoi : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t aoi : 1; - uint8_t _6d : 1; - uint8_t zhie : 1; - uint8_t zlie : 1; - uint8_t yhie : 1; - uint8_t ylie : 1; - uint8_t xhie : 1; - uint8_t xlie : 1; -#endif /* DRV_BYTE_ORDER */ -} lis2dh_int2_cfg_t; - -#define LIS2DH_INT2_SRC 0x35U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t xl : 1; - uint8_t xh : 1; - uint8_t yl : 1; - uint8_t yh : 1; - uint8_t zl : 1; - uint8_t zh : 1; - uint8_t ia : 1; - uint8_t not_used_01 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 1; - uint8_t ia : 1; - uint8_t zh : 1; - uint8_t zl : 1; - uint8_t yh : 1; - uint8_t yl : 1; - uint8_t xh : 1; - uint8_t xl : 1; -#endif /* DRV_BYTE_ORDER */ -} lis2dh_int2_src_t; - -#define LIS2DH_INT2_THS 0x36U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t ths : 7; - uint8_t not_used_01 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 1; - uint8_t ths : 7; -#endif /* DRV_BYTE_ORDER */ -} lis2dh_int2_ths_t; - -#define LIS2DH_INT2_DURATION 0x37U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t d : 7; - uint8_t not_used_01 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 1; - uint8_t d : 7; -#endif /* DRV_BYTE_ORDER */ -} lis2dh_int2_duration_t; - -#define LIS2DH_CLICK_CFG 0x38U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t xs : 1; - uint8_t xd : 1; - uint8_t ys : 1; - uint8_t yd : 1; - uint8_t zs : 1; - uint8_t zd : 1; - uint8_t not_used_01 : 2; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 2; - uint8_t zd : 1; - uint8_t zs : 1; - uint8_t yd : 1; - uint8_t ys : 1; - uint8_t xd : 1; - uint8_t xs : 1; -#endif /* DRV_BYTE_ORDER */ -} lis2dh_click_cfg_t; - -#define LIS2DH_CLICK_SRC 0x39U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t x : 1; - uint8_t y : 1; - uint8_t z : 1; - uint8_t sign : 1; - uint8_t sclick : 1; - uint8_t dclick : 1; - uint8_t ia : 1; - uint8_t not_used_01 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 1; - uint8_t ia : 1; - uint8_t dclick : 1; - uint8_t sclick : 1; - uint8_t sign : 1; - uint8_t z : 1; - uint8_t y : 1; - uint8_t x : 1; -#endif /* DRV_BYTE_ORDER */ -} lis2dh_click_src_t; - -#define LIS2DH_CLICK_THS 0x3AU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t ths : 7; - uint8_t not_used_01 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 1; - uint8_t ths : 7; -#endif /* DRV_BYTE_ORDER */ -} lis2dh_click_ths_t; - -#define LIS2DH_TIME_LIMIT 0x3BU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t tli : 7; - uint8_t not_used_01 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 1; - uint8_t tli : 7; -#endif /* DRV_BYTE_ORDER */ -} lis2dh_time_limit_t; - -#define LIS2DH_TIME_LATENCY 0x3CU -typedef struct -{ - uint8_t tla : 8; -} lis2dh_time_latency_t; - -#define LIS2DH_TIME_WINDOW 0x3DU -typedef struct -{ - uint8_t tw : 8; -} lis2dh_time_window_t; - -#define LIS2DH_ACT_THS 0x3EU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t acth : 7; - uint8_t not_used_01 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 1; - uint8_t acth : 7; -#endif /* DRV_BYTE_ORDER */ -} lis2dh_act_ths_t; - -#define LIS2DH_ACT_DUR 0x3FU -typedef struct -{ - uint8_t actd : 8; -} lis2dh_act_dur_t; - -/** - * @defgroup LIS2DH_Register_Union - * @brief This union group all the registers having a bit-field - * description. - * This union is useful but it's not needed by the driver. - * - * REMOVING this union you are compliant with: - * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " - * - * @{ - * - */ -typedef union -{ - lis2dh_status_reg_aux_t status_reg_aux; - lis2dh_temp_cfg_reg_t temp_cfg_reg; - lis2dh_ctrl_reg1_t ctrl_reg1; - lis2dh_ctrl_reg2_t ctrl_reg2; - lis2dh_ctrl_reg3_t ctrl_reg3; - lis2dh_ctrl_reg4_t ctrl_reg4; - lis2dh_ctrl_reg5_t ctrl_reg5; - lis2dh_ctrl_reg6_t ctrl_reg6; - lis2dh_status_reg_t status_reg; - lis2dh_fifo_ctrl_reg_t fifo_ctrl_reg; - lis2dh_fifo_src_reg_t fifo_src_reg; - lis2dh_int1_cfg_t int1_cfg; - lis2dh_int1_src_t int1_src; - lis2dh_int1_ths_t int1_ths; - lis2dh_int1_duration_t int1_duration; - lis2dh_int2_cfg_t int2_cfg; - lis2dh_int2_src_t int2_src; - lis2dh_int2_ths_t int2_ths; - lis2dh_int2_duration_t int2_duration; - lis2dh_click_cfg_t click_cfg; - lis2dh_click_src_t click_src; - lis2dh_click_ths_t click_ths; - lis2dh_time_limit_t time_limit; - lis2dh_time_latency_t time_latency; - lis2dh_time_window_t time_window; - lis2dh_act_ths_t act_ths; - lis2dh_act_dur_t act_dur; - bitwise_t bitwise; - uint8_t byte; -} lis2dh_reg_t; - -/** - * @} - * - */ - -#ifndef __weak -#define __weak __attribute__((weak)) -#endif /* __weak */ - -/* - * These are the basic platform dependent I/O routines to read - * and write device registers connected on a standard bus. - * The driver keeps offering a default implementation based on function - * pointers to read/write routines for backward compatibility. - * The __weak directive allows the final application to overwrite - * them with a custom implementation. - */ - -int32_t lis2dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len); -int32_t lis2dh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len); - -float_t lis2dh_from_fs2_hr_to_mg(int16_t lsb); -float_t lis2dh_from_fs4_hr_to_mg(int16_t lsb); -float_t lis2dh_from_fs8_hr_to_mg(int16_t lsb); -float_t lis2dh_from_fs16_hr_to_mg(int16_t lsb); -float_t lis2dh_from_lsb_hr_to_celsius(int16_t lsb); - -float_t lis2dh_from_fs2_nm_to_mg(int16_t lsb); -float_t lis2dh_from_fs4_nm_to_mg(int16_t lsb); -float_t lis2dh_from_fs8_nm_to_mg(int16_t lsb); -float_t lis2dh_from_fs16_nm_to_mg(int16_t lsb); -float_t lis2dh_from_lsb_nm_to_celsius(int16_t lsb); - -float_t lis2dh_from_fs2_lp_to_mg(int16_t lsb); -float_t lis2dh_from_fs4_lp_to_mg(int16_t lsb); -float_t lis2dh_from_fs8_lp_to_mg(int16_t lsb); -float_t lis2dh_from_fs16_lp_to_mg(int16_t lsb); -float_t lis2dh_from_lsb_lp_to_celsius(int16_t lsb); - -int32_t lis2dh_int_count_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lis2dh_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff); - -int32_t lis2dh_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lis2dh_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lis2dh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); - -typedef enum -{ - LIS2DH_TEMP_DISABLE = 0, - LIS2DH_TEMP_ENABLE = 3, -} lis2dh_temp_en_t; -int32_t lis2dh_temperature_meas_set(stmdev_ctx_t *ctx, - lis2dh_temp_en_t val); -int32_t lis2dh_temperature_meas_get(stmdev_ctx_t *ctx, - lis2dh_temp_en_t *val); - -typedef enum -{ - LIS2DH_HR_12bit = 0, - LIS2DH_NM_10bit = 1, - LIS2DH_LP_8bit = 2, -} lis2dh_op_md_t; -int32_t lis2dh_operating_mode_set(stmdev_ctx_t *ctx, - lis2dh_op_md_t val); -int32_t lis2dh_operating_mode_get(stmdev_ctx_t *ctx, - lis2dh_op_md_t *val); - -typedef enum -{ - LIS2DH_POWER_DOWN = 0x00, - LIS2DH_ODR_1Hz = 0x01, - LIS2DH_ODR_10Hz = 0x02, - LIS2DH_ODR_25Hz = 0x03, - LIS2DH_ODR_50Hz = 0x04, - LIS2DH_ODR_100Hz = 0x05, - LIS2DH_ODR_200Hz = 0x06, - LIS2DH_ODR_400Hz = 0x07, - LIS2DH_ODR_1kHz620_LP = 0x08, - LIS2DH_ODR_5kHz376_LP_1kHz344_NM_HP = 0x09, -} lis2dh_odr_t; -int32_t lis2dh_data_rate_set(stmdev_ctx_t *ctx, lis2dh_odr_t val); -int32_t lis2dh_data_rate_get(stmdev_ctx_t *ctx, - lis2dh_odr_t *val); - -int32_t lis2dh_high_pass_on_outputs_set(stmdev_ctx_t *ctx, - uint8_t val); -int32_t lis2dh_high_pass_on_outputs_get(stmdev_ctx_t *ctx, - uint8_t *val); - -typedef enum -{ - LIS2DH_AGGRESSIVE = 0, - LIS2DH_STRONG = 1, - LIS2DH_MEDIUM = 2, - LIS2DH_LIGHT = 3, -} lis2dh_hpcf_t; -int32_t lis2dh_high_pass_bandwidth_set(stmdev_ctx_t *ctx, - lis2dh_hpcf_t val); -int32_t lis2dh_high_pass_bandwidth_get(stmdev_ctx_t *ctx, - lis2dh_hpcf_t *val); - -typedef enum -{ - LIS2DH_NORMAL_WITH_RST = 0, - LIS2DH_REFERENCE_MODE = 1, - LIS2DH_NORMAL = 2, - LIS2DH_AUTORST_ON_INT = 3, -} lis2dh_hpm_t; -int32_t lis2dh_high_pass_mode_set(stmdev_ctx_t *ctx, - lis2dh_hpm_t val); -int32_t lis2dh_high_pass_mode_get(stmdev_ctx_t *ctx, - lis2dh_hpm_t *val); - -typedef enum -{ - LIS2DH_2g = 0, - LIS2DH_4g = 1, - LIS2DH_8g = 2, - LIS2DH_16g = 3, -} lis2dh_fs_t; -int32_t lis2dh_full_scale_set(stmdev_ctx_t *ctx, lis2dh_fs_t val); -int32_t lis2dh_full_scale_get(stmdev_ctx_t *ctx, - lis2dh_fs_t *val); - -int32_t lis2dh_block_data_update_set(stmdev_ctx_t *ctx, - uint8_t val); -int32_t lis2dh_block_data_update_get(stmdev_ctx_t *ctx, - uint8_t *val); - -int32_t lis2dh_filter_reference_set(stmdev_ctx_t *ctx, - uint8_t *buff); -int32_t lis2dh_filter_reference_get(stmdev_ctx_t *ctx, - uint8_t *buff); - -int32_t lis2dh_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lis2dh_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lis2dh_acceleration_raw_get(stmdev_ctx_t *ctx, - int16_t *val); - -int32_t lis2dh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); - -typedef enum -{ - LIS2DH_ST_DISABLE = 0, - LIS2DH_ST_POSITIVE = 1, - LIS2DH_ST_NEGATIVE = 2, -} lis2dh_st_t; -int32_t lis2dh_self_test_set(stmdev_ctx_t *ctx, lis2dh_st_t val); -int32_t lis2dh_self_test_get(stmdev_ctx_t *ctx, lis2dh_st_t *val); - -typedef enum -{ - LIS2DH_LSB_AT_LOW_ADD = 0, - LIS2DH_MSB_AT_LOW_ADD = 1, -} lis2dh_ble_t; -int32_t lis2dh_data_format_set(stmdev_ctx_t *ctx, - lis2dh_ble_t val); -int32_t lis2dh_data_format_get(stmdev_ctx_t *ctx, - lis2dh_ble_t *val); - -int32_t lis2dh_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dh_boot_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lis2dh_status_get(stmdev_ctx_t *ctx, - lis2dh_status_reg_t *val); - -int32_t lis2dh_int1_gen_conf_set(stmdev_ctx_t *ctx, - lis2dh_int1_cfg_t *val); -int32_t lis2dh_int1_gen_conf_get(stmdev_ctx_t *ctx, - lis2dh_int1_cfg_t *val); - -int32_t lis2dh_int1_gen_source_get(stmdev_ctx_t *ctx, - lis2dh_int1_src_t *val); - -int32_t lis2dh_int1_gen_threshold_set(stmdev_ctx_t *ctx, - uint8_t val); -int32_t lis2dh_int1_gen_threshold_get(stmdev_ctx_t *ctx, - uint8_t *val); - -int32_t lis2dh_int1_gen_duration_set(stmdev_ctx_t *ctx, - uint8_t val); -int32_t lis2dh_int1_gen_duration_get(stmdev_ctx_t *ctx, - uint8_t *val); - -int32_t lis2dh_int2_gen_conf_set(stmdev_ctx_t *ctx, - lis2dh_int2_cfg_t *val); -int32_t lis2dh_int2_gen_conf_get(stmdev_ctx_t *ctx, - lis2dh_int2_cfg_t *val); - -int32_t lis2dh_int2_gen_source_get(stmdev_ctx_t *ctx, - lis2dh_int2_src_t *val); - -int32_t lis2dh_int2_gen_threshold_set(stmdev_ctx_t *ctx, - uint8_t val); -int32_t lis2dh_int2_gen_threshold_get(stmdev_ctx_t *ctx, - uint8_t *val); - -int32_t lis2dh_int2_gen_duration_set(stmdev_ctx_t *ctx, - uint8_t val); -int32_t lis2dh_int2_gen_duration_get(stmdev_ctx_t *ctx, - uint8_t *val); - -typedef enum -{ - LIS2DH_DISC_FROM_INT_GENERATOR = 0, - LIS2DH_ON_INT1_GEN = 1, - LIS2DH_ON_INT2_GEN = 2, - LIS2DH_ON_TAP_GEN = 4, - LIS2DH_ON_INT1_INT2_GEN = 3, - LIS2DH_ON_INT1_TAP_GEN = 5, - LIS2DH_ON_INT2_TAP_GEN = 6, - LIS2DH_ON_INT1_INT2_TAP_GEN = 7, -} lis2dh_hp_t; -int32_t lis2dh_high_pass_int_conf_set(stmdev_ctx_t *ctx, - lis2dh_hp_t val); -int32_t lis2dh_high_pass_int_conf_get(stmdev_ctx_t *ctx, - lis2dh_hp_t *val); - -int32_t lis2dh_pin_int1_config_set(stmdev_ctx_t *ctx, - lis2dh_ctrl_reg3_t *val); -int32_t lis2dh_pin_int1_config_get(stmdev_ctx_t *ctx, - lis2dh_ctrl_reg3_t *val); - -int32_t lis2dh_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, - uint8_t val); -int32_t lis2dh_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, - uint8_t *val); - -typedef enum -{ - LIS2DH_INT2_PULSED = 0, - LIS2DH_INT2_LATCHED = 1, -} lis2dh_lir_int2_t; -int32_t lis2dh_int2_pin_notification_mode_set(stmdev_ctx_t *ctx, - lis2dh_lir_int2_t val); -int32_t lis2dh_int2_pin_notification_mode_get(stmdev_ctx_t *ctx, - lis2dh_lir_int2_t *val); - -int32_t lis2dh_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, - uint8_t val); -int32_t lis2dh_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, - uint8_t *val); - -typedef enum -{ - LIS2DH_INT1_PULSED = 0, - LIS2DH_INT1_LATCHED = 1, -} lis2dh_lir_int1_t; -int32_t lis2dh_int1_pin_notification_mode_set(stmdev_ctx_t *ctx, - lis2dh_lir_int1_t val); -int32_t lis2dh_int1_pin_notification_mode_get(stmdev_ctx_t *ctx, - lis2dh_lir_int1_t *val); - -int32_t lis2dh_pin_int2_config_set(stmdev_ctx_t *ctx, - lis2dh_ctrl_reg6_t *val); -int32_t lis2dh_pin_int2_config_get(stmdev_ctx_t *ctx, - lis2dh_ctrl_reg6_t *val); - -int32_t lis2dh_fifo_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dh_fifo_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lis2dh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); - -typedef enum -{ - LIS2DH_INT1_GEN = 0, - LIS2DH_INT2_GEN = 1, -} lis2dh_tr_t; -int32_t lis2dh_fifo_trigger_event_set(stmdev_ctx_t *ctx, - lis2dh_tr_t val); -int32_t lis2dh_fifo_trigger_event_get(stmdev_ctx_t *ctx, - lis2dh_tr_t *val); - -typedef enum -{ - LIS2DH_BYPASS_MODE = 0, - LIS2DH_FIFO_MODE = 1, - LIS2DH_DYNAMIC_STREAM_MODE = 2, - LIS2DH_STREAM_TO_FIFO_MODE = 3, -} lis2dh_fm_t; -int32_t lis2dh_fifo_mode_set(stmdev_ctx_t *ctx, lis2dh_fm_t val); -int32_t lis2dh_fifo_mode_get(stmdev_ctx_t *ctx, lis2dh_fm_t *val); - -int32_t lis2dh_fifo_status_get(stmdev_ctx_t *ctx, - lis2dh_fifo_src_reg_t *val); - -int32_t lis2dh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lis2dh_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lis2dh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lis2dh_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lis2dh_tap_conf_set(stmdev_ctx_t *ctx, - lis2dh_click_cfg_t *val); -int32_t lis2dh_tap_conf_get(stmdev_ctx_t *ctx, - lis2dh_click_cfg_t *val); - -int32_t lis2dh_tap_source_get(stmdev_ctx_t *ctx, - lis2dh_click_src_t *val); - -int32_t lis2dh_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dh_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lis2dh_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dh_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lis2dh_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dh_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lis2dh_double_tap_timeout_set(stmdev_ctx_t *ctx, - uint8_t val); -int32_t lis2dh_double_tap_timeout_get(stmdev_ctx_t *ctx, - uint8_t *val); - -int32_t lis2dh_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dh_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lis2dh_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dh_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val); - -typedef enum -{ - LIS2DH_SPI_4_WIRE = 0, - LIS2DH_SPI_3_WIRE = 1, -} lis2dh_sim_t; -int32_t lis2dh_spi_mode_set(stmdev_ctx_t *ctx, lis2dh_sim_t val); -int32_t lis2dh_spi_mode_get(stmdev_ctx_t *ctx, lis2dh_sim_t *val); - -/** - * @} - * - */ - -#ifdef __cplusplus -} -#endif - -#endif /* LIS2DH_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.c b/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.c index a985af74..96a8552d 100644 --- a/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.c +++ b/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis2ds12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lis2ds12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lis2ds12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis2ds12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lis2ds12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -136,7 +146,7 @@ float_t lis2ds12_from_lsb_to_celsius(int16_t lsb) * 6D_SRC, FUNC_CK_GATE, FUNC_SRC.(ptr) * */ -int32_t lis2ds12_all_sources_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_all_sources_get(const stmdev_ctx_t *ctx, lis2ds12_all_sources_t *val) { int32_t ret; @@ -191,7 +201,7 @@ int32_t lis2ds12_all_sources_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2ds12_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_ctrl1_t ctrl1; int32_t ret; @@ -215,7 +225,7 @@ int32_t lis2ds12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_ctrl1_t ctrl1; @@ -235,7 +245,7 @@ int32_t lis2ds12_block_data_update_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_xl_full_scale_set(const stmdev_ctx_t *ctx, lis2ds12_fs_t val) { lis2ds12_ctrl1_t ctrl1; @@ -260,7 +270,7 @@ int32_t lis2ds12_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_xl_full_scale_get(const stmdev_ctx_t *ctx, lis2ds12_fs_t *val) { lis2ds12_ctrl1_t ctrl1; @@ -302,7 +312,7 @@ int32_t lis2ds12_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_xl_data_rate_set(const stmdev_ctx_t *ctx, lis2ds12_odr_t val) { lis2ds12_ctrl1_t ctrl1; @@ -328,7 +338,7 @@ int32_t lis2ds12_xl_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_xl_data_rate_get(const stmdev_ctx_t *ctx, lis2ds12_odr_t *val) { lis2ds12_ctrl1_t ctrl1; @@ -430,7 +440,7 @@ int32_t lis2ds12_xl_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_status_reg_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_status_reg_get(const stmdev_ctx_t *ctx, lis2ds12_status_t *val) { int32_t ret; @@ -448,7 +458,7 @@ int32_t lis2ds12_status_reg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_status_t status; @@ -480,7 +490,7 @@ int32_t lis2ds12_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_acceleration_module_raw_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_acceleration_module_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -499,7 +509,7 @@ int32_t lis2ds12_acceleration_module_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis2ds12_temperature_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -517,7 +527,7 @@ int32_t lis2ds12_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lis2ds12_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -541,7 +551,7 @@ int32_t lis2ds12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_number_of_steps_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lis2ds12_number_of_steps_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -573,7 +583,7 @@ int32_t lis2ds12_number_of_steps_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis2ds12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -591,7 +601,7 @@ int32_t lis2ds12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2ds12_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_ctrl2_t ctrl2; int32_t ret; @@ -616,7 +626,7 @@ int32_t lis2ds12_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_ctrl2_t ctrl2; int32_t ret; @@ -636,7 +646,7 @@ int32_t lis2ds12_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_mem_bank_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_mem_bank_set(const stmdev_ctx_t *ctx, lis2ds12_func_cfg_en_t val) { lis2ds12_ctrl2_t ctrl2; @@ -680,7 +690,7 @@ int32_t lis2ds12_mem_bank_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2ds12_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_ctrl2_t ctrl2; int32_t ret; @@ -705,7 +715,7 @@ int32_t lis2ds12_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_ctrl2_t ctrl2; int32_t ret; @@ -724,7 +734,7 @@ int32_t lis2ds12_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2ds12_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_ctrl2_t ctrl2; int32_t ret; @@ -748,7 +758,7 @@ int32_t lis2ds12_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_ctrl2_t ctrl2; int32_t ret; @@ -767,7 +777,7 @@ int32_t lis2ds12_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_xl_self_test_set(const stmdev_ctx_t *ctx, lis2ds12_st_t val) { lis2ds12_ctrl3_t ctrl3; @@ -792,7 +802,7 @@ int32_t lis2ds12_xl_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_xl_self_test_get(const stmdev_ctx_t *ctx, lis2ds12_st_t *val) { lis2ds12_ctrl3_t ctrl3; @@ -830,7 +840,7 @@ int32_t lis2ds12_xl_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_data_ready_mode_set(const stmdev_ctx_t *ctx, lis2ds12_drdy_pulsed_t val) { lis2ds12_ctrl5_t ctrl5; @@ -855,7 +865,7 @@ int32_t lis2ds12_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_data_ready_mode_get(const stmdev_ctx_t *ctx, lis2ds12_drdy_pulsed_t *val) { lis2ds12_ctrl5_t ctrl5; @@ -902,7 +912,7 @@ int32_t lis2ds12_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_xl_hp_path_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_xl_hp_path_set(const stmdev_ctx_t *ctx, lis2ds12_fds_slope_t val) { lis2ds12_ctrl2_t ctrl2; @@ -927,7 +937,7 @@ int32_t lis2ds12_xl_hp_path_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_xl_hp_path_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_xl_hp_path_get(const stmdev_ctx_t *ctx, lis2ds12_fds_slope_t *val) { lis2ds12_ctrl2_t ctrl2; @@ -974,7 +984,7 @@ int32_t lis2ds12_xl_hp_path_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_spi_mode_set(stmdev_ctx_t *ctx, lis2ds12_sim_t val) +int32_t lis2ds12_spi_mode_set(const stmdev_ctx_t *ctx, lis2ds12_sim_t val) { lis2ds12_ctrl2_t ctrl2; int32_t ret; @@ -998,7 +1008,7 @@ int32_t lis2ds12_spi_mode_set(stmdev_ctx_t *ctx, lis2ds12_sim_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_spi_mode_get(stmdev_ctx_t *ctx, lis2ds12_sim_t *val) +int32_t lis2ds12_spi_mode_get(const stmdev_ctx_t *ctx, lis2ds12_sim_t *val) { lis2ds12_ctrl2_t ctrl2; int32_t ret; @@ -1031,7 +1041,7 @@ int32_t lis2ds12_spi_mode_get(stmdev_ctx_t *ctx, lis2ds12_sim_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_i2c_interface_set(const stmdev_ctx_t *ctx, lis2ds12_i2c_disable_t val) { lis2ds12_ctrl2_t ctrl2; @@ -1056,7 +1066,7 @@ int32_t lis2ds12_i2c_interface_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_i2c_interface_get(const stmdev_ctx_t *ctx, lis2ds12_i2c_disable_t *val) { lis2ds12_ctrl2_t ctrl2; @@ -1090,7 +1100,7 @@ int32_t lis2ds12_i2c_interface_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_cs_mode_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_cs_mode_set(const stmdev_ctx_t *ctx, lis2ds12_if_cs_pu_dis_t val) { lis2ds12_fifo_ctrl_t fifo_ctrl; @@ -1117,7 +1127,7 @@ int32_t lis2ds12_cs_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_cs_mode_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_cs_mode_get(const stmdev_ctx_t *ctx, lis2ds12_if_cs_pu_dis_t *val) { lis2ds12_fifo_ctrl_t fifo_ctrl; @@ -1165,7 +1175,7 @@ int32_t lis2ds12_cs_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_pin_mode_set(stmdev_ctx_t *ctx, lis2ds12_pp_od_t val) +int32_t lis2ds12_pin_mode_set(const stmdev_ctx_t *ctx, lis2ds12_pp_od_t val) { lis2ds12_ctrl3_t ctrl3; int32_t ret; @@ -1189,7 +1199,7 @@ int32_t lis2ds12_pin_mode_set(stmdev_ctx_t *ctx, lis2ds12_pp_od_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_pin_mode_get(const stmdev_ctx_t *ctx, lis2ds12_pp_od_t *val) { lis2ds12_ctrl3_t ctrl3; @@ -1223,7 +1233,7 @@ int32_t lis2ds12_pin_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_pin_polarity_set(const stmdev_ctx_t *ctx, lis2ds12_h_lactive_t val) { lis2ds12_ctrl3_t ctrl3; @@ -1248,7 +1258,7 @@ int32_t lis2ds12_pin_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_pin_polarity_get(const stmdev_ctx_t *ctx, lis2ds12_h_lactive_t *val) { lis2ds12_ctrl3_t ctrl3; @@ -1282,7 +1292,7 @@ int32_t lis2ds12_pin_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_int_notification_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_int_notification_set(const stmdev_ctx_t *ctx, lis2ds12_lir_t val) { lis2ds12_ctrl3_t ctrl3; @@ -1307,7 +1317,7 @@ int32_t lis2ds12_int_notification_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_int_notification_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_int_notification_get(const stmdev_ctx_t *ctx, lis2ds12_lir_t *val) { lis2ds12_ctrl3_t ctrl3; @@ -1341,7 +1351,7 @@ int32_t lis2ds12_int_notification_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_pin_int1_route_set(const stmdev_ctx_t *ctx, lis2ds12_pin_int1_route_t val) { lis2ds12_wake_up_dur_t wake_up_dur; @@ -1387,7 +1397,7 @@ int32_t lis2ds12_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_pin_int1_route_get(const stmdev_ctx_t *ctx, lis2ds12_pin_int1_route_t *val) { lis2ds12_wake_up_dur_t wake_up_dur; @@ -1422,7 +1432,7 @@ int32_t lis2ds12_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_pin_int2_route_set(const stmdev_ctx_t *ctx, lis2ds12_pin_int2_route_t val) { lis2ds12_ctrl5_t ctrl5; @@ -1452,7 +1462,7 @@ int32_t lis2ds12_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_pin_int2_route_get(const stmdev_ctx_t *ctx, lis2ds12_pin_int2_route_t *val) { lis2ds12_ctrl5_t ctrl5; @@ -1477,7 +1487,7 @@ int32_t lis2ds12_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2ds12_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_ctrl5_t ctrl5; int32_t ret; @@ -1501,7 +1511,7 @@ int32_t lis2ds12_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_ctrl5_t ctrl5; int32_t ret; @@ -1532,7 +1542,7 @@ int32_t lis2ds12_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_sh_pin_mode_set(const stmdev_ctx_t *ctx, lis2ds12_tud_en_t val) { lis2ds12_func_ctrl_t func_ctrl; @@ -1559,7 +1569,7 @@ int32_t lis2ds12_sh_pin_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_sh_pin_mode_get(const stmdev_ctx_t *ctx, lis2ds12_tud_en_t *val) { lis2ds12_func_ctrl_t func_ctrl; @@ -1607,7 +1617,7 @@ int32_t lis2ds12_sh_pin_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2ds12_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_wake_up_ths_t wake_up_ths; int32_t ret; @@ -1633,7 +1643,7 @@ int32_t lis2ds12_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_wake_up_ths_t wake_up_ths; int32_t ret; @@ -1653,7 +1663,7 @@ int32_t lis2ds12_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2ds12_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_wake_up_dur_t wake_up_dur; int32_t ret; @@ -1679,7 +1689,7 @@ int32_t lis2ds12_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_wake_up_dur_t wake_up_dur; int32_t ret; @@ -1712,7 +1722,7 @@ int32_t lis2ds12_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2ds12_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_wake_up_ths_t wake_up_ths; int32_t ret; @@ -1738,7 +1748,7 @@ int32_t lis2ds12_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_wake_up_ths_t wake_up_ths; int32_t ret; @@ -1758,7 +1768,7 @@ int32_t lis2ds12_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2ds12_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_wake_up_dur_t wake_up_dur; int32_t ret; @@ -1784,7 +1794,7 @@ int32_t lis2ds12_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_wake_up_dur_t wake_up_dur; int32_t ret; @@ -1817,7 +1827,7 @@ int32_t lis2ds12_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_ctrl3_t ctrl3; @@ -1842,7 +1852,7 @@ int32_t lis2ds12_tap_detection_on_z_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_ctrl3_t ctrl3; @@ -1862,7 +1872,7 @@ int32_t lis2ds12_tap_detection_on_z_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_ctrl3_t ctrl3; @@ -1887,7 +1897,7 @@ int32_t lis2ds12_tap_detection_on_y_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_ctrl3_t ctrl3; @@ -1907,7 +1917,7 @@ int32_t lis2ds12_tap_detection_on_y_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_ctrl3_t ctrl3; @@ -1932,7 +1942,7 @@ int32_t lis2ds12_tap_detection_on_x_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_ctrl3_t ctrl3; @@ -1952,7 +1962,7 @@ int32_t lis2ds12_tap_detection_on_x_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2ds12_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_tap_6d_ths_t tap_6d_ths; int32_t ret; @@ -1978,7 +1988,7 @@ int32_t lis2ds12_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_tap_6d_ths_t tap_6d_ths; int32_t ret; @@ -2002,7 +2012,7 @@ int32_t lis2ds12_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2ds12_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_int_dur_t int_dur; int32_t ret; @@ -2030,7 +2040,7 @@ int32_t lis2ds12_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_int_dur_t int_dur; int32_t ret; @@ -2053,7 +2063,7 @@ int32_t lis2ds12_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2ds12_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_int_dur_t int_dur; int32_t ret; @@ -2081,7 +2091,7 @@ int32_t lis2ds12_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_int_dur_t int_dur; int32_t ret; @@ -2104,7 +2114,7 @@ int32_t lis2ds12_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2ds12_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_int_dur_t int_dur; int32_t ret; @@ -2132,7 +2142,7 @@ int32_t lis2ds12_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_int_dur_t int_dur; int32_t ret; @@ -2151,7 +2161,7 @@ int32_t lis2ds12_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_tap_mode_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_tap_mode_set(const stmdev_ctx_t *ctx, lis2ds12_single_double_tap_t val) { lis2ds12_wake_up_ths_t wake_up_ths; @@ -2178,7 +2188,7 @@ int32_t lis2ds12_tap_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_tap_mode_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_tap_mode_get(const stmdev_ctx_t *ctx, lis2ds12_single_double_tap_t *val) { lis2ds12_wake_up_ths_t wake_up_ths; @@ -2213,7 +2223,7 @@ int32_t lis2ds12_tap_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_tap_src_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_tap_src_get(const stmdev_ctx_t *ctx, lis2ds12_tap_src_t *val) { int32_t ret; @@ -2244,7 +2254,7 @@ int32_t lis2ds12_tap_src_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_6d_threshold_set(const stmdev_ctx_t *ctx, lis2ds12_6d_ths_t val) { lis2ds12_tap_6d_ths_t tap_6d_ths; @@ -2271,7 +2281,7 @@ int32_t lis2ds12_6d_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_6d_threshold_get(const stmdev_ctx_t *ctx, lis2ds12_6d_ths_t *val) { lis2ds12_tap_6d_ths_t tap_6d_ths; @@ -2314,7 +2324,7 @@ int32_t lis2ds12_6d_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2ds12_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_tap_6d_ths_t tap_6d_ths; int32_t ret; @@ -2340,7 +2350,7 @@ int32_t lis2ds12_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_tap_6d_ths_t tap_6d_ths; int32_t ret; @@ -2360,7 +2370,7 @@ int32_t lis2ds12_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_6d_src_get(stmdev_ctx_t *ctx, lis2ds12_6d_src_t *val) +int32_t lis2ds12_6d_src_get(const stmdev_ctx_t *ctx, lis2ds12_6d_src_t *val) { int32_t ret; @@ -2390,7 +2400,7 @@ int32_t lis2ds12_6d_src_get(stmdev_ctx_t *ctx, lis2ds12_6d_src_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2ds12_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_free_fall_t free_fall; lis2ds12_wake_up_dur_t wake_up_dur; @@ -2430,7 +2440,7 @@ int32_t lis2ds12_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_free_fall_t free_fall; lis2ds12_wake_up_dur_t wake_up_dur; @@ -2457,7 +2467,7 @@ int32_t lis2ds12_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_ff_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2ds12_ff_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_free_fall_t free_fall; int32_t ret; @@ -2483,7 +2493,7 @@ int32_t lis2ds12_ff_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_ff_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_ff_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_free_fall_t free_fall; int32_t ret; @@ -2516,7 +2526,7 @@ int32_t lis2ds12_ff_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_fifo_xl_module_batch_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_fifo_xl_module_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_fifo_ctrl_t fifo_ctrl; @@ -2544,7 +2554,7 @@ int32_t lis2ds12_fifo_xl_module_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_fifo_xl_module_batch_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_fifo_xl_module_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_fifo_ctrl_t fifo_ctrl; @@ -2565,7 +2575,7 @@ int32_t lis2ds12_fifo_xl_module_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2ds12_fmode_t val) { lis2ds12_fifo_ctrl_t fifo_ctrl; @@ -2592,7 +2602,7 @@ int32_t lis2ds12_fifo_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2ds12_fmode_t *val) { lis2ds12_fifo_ctrl_t fifo_ctrl; @@ -2639,7 +2649,7 @@ int32_t lis2ds12_fifo_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2ds12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; @@ -2656,7 +2666,7 @@ int32_t lis2ds12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -2673,7 +2683,7 @@ int32_t lis2ds12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_fifo_src_t fifo_src; int32_t ret; @@ -2692,7 +2702,7 @@ int32_t lis2ds12_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_fifo_src_t fifo_src; int32_t ret; @@ -2711,7 +2721,7 @@ int32_t lis2ds12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_fifo_src_t fifo_src; int32_t ret; @@ -2730,7 +2740,7 @@ int32_t lis2ds12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lis2ds12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) { lis2ds12_fifo_ths_t fifo_ths; lis2ds12_fifo_src_t fifo_src; @@ -2756,7 +2766,7 @@ int32_t lis2ds12_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_fifo_src_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_fifo_src_get(const stmdev_ctx_t *ctx, lis2ds12_fifo_src_t *val) { int32_t ret; @@ -2786,7 +2796,7 @@ int32_t lis2ds12_fifo_src_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2ds12_pedo_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_step_counter_minths_t step_counter_minths; int32_t ret; @@ -2812,7 +2822,7 @@ int32_t lis2ds12_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_pedo_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_step_counter_minths_t step_counter_minths; int32_t ret; @@ -2832,7 +2842,7 @@ int32_t lis2ds12_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_pedo_full_scale_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_pedo_full_scale_set(const stmdev_ctx_t *ctx, lis2ds12_pedo4g_t val) { lis2ds12_step_counter_minths_t step_counter_minths; @@ -2859,7 +2869,7 @@ int32_t lis2ds12_pedo_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_pedo_full_scale_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_pedo_full_scale_get(const stmdev_ctx_t *ctx, lis2ds12_pedo4g_t *val) { lis2ds12_step_counter_minths_t step_counter_minths; @@ -2894,7 +2904,7 @@ int32_t lis2ds12_pedo_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2ds12_pedo_step_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_step_counter_minths_t step_counter_minths; int32_t ret; @@ -2920,7 +2930,7 @@ int32_t lis2ds12_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_pedo_step_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_step_counter_minths_t step_counter_minths; int32_t ret; @@ -2940,7 +2950,7 @@ int32_t lis2ds12_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_pedo_step_detect_flag_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_pedo_step_detect_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_func_ck_gate_t func_ck_gate; @@ -2961,7 +2971,7 @@ int32_t lis2ds12_pedo_step_detect_flag_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2ds12_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_func_ctrl_t func_ctrl; int32_t ret; @@ -2987,7 +2997,7 @@ int32_t lis2ds12_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_func_ctrl_t func_ctrl; int32_t ret; @@ -3007,7 +3017,7 @@ int32_t lis2ds12_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_pedo_debounce_steps_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_pedo_deb_reg_t pedo_deb_reg; @@ -3044,7 +3054,7 @@ int32_t lis2ds12_pedo_debounce_steps_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_pedo_debounce_steps_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_pedo_deb_reg_t pedo_deb_reg; @@ -3077,7 +3087,7 @@ int32_t lis2ds12_pedo_debounce_steps_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2ds12_pedo_timeout_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_pedo_deb_reg_t pedo_deb_reg; int32_t ret; @@ -3115,7 +3125,7 @@ int32_t lis2ds12_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_pedo_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_pedo_deb_reg_t pedo_deb_reg; int32_t ret; @@ -3146,7 +3156,7 @@ int32_t lis2ds12_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_pedo_steps_period_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_pedo_steps_period_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -3175,7 +3185,7 @@ int32_t lis2ds12_pedo_steps_period_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_pedo_steps_period_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_pedo_steps_period_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -3216,7 +3226,7 @@ int32_t lis2ds12_pedo_steps_period_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_motion_data_ready_flag_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_motion_data_ready_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_func_ck_gate_t func_ck_gate; @@ -3237,7 +3247,7 @@ int32_t lis2ds12_motion_data_ready_flag_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2ds12_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_func_ctrl_t func_ctrl; int32_t ret; @@ -3263,7 +3273,7 @@ int32_t lis2ds12_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_func_ctrl_t func_ctrl; int32_t ret; @@ -3287,7 +3297,7 @@ int32_t lis2ds12_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2ds12_motion_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_sm_ths_t sm_ths; int32_t ret; @@ -3325,7 +3335,7 @@ int32_t lis2ds12_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_motion_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_sm_ths_t sm_ths; int32_t ret; @@ -3367,7 +3377,7 @@ int32_t lis2ds12_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_tilt_data_ready_flag_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_tilt_data_ready_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_func_ck_gate_t func_ck_gate; @@ -3388,7 +3398,7 @@ int32_t lis2ds12_tilt_data_ready_flag_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2ds12_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_func_ctrl_t func_ctrl; int32_t ret; @@ -3414,7 +3424,7 @@ int32_t lis2ds12_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_func_ctrl_t func_ctrl; int32_t ret; @@ -3447,7 +3457,7 @@ int32_t lis2ds12_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_module_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2ds12_module_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_func_ctrl_t func_ctrl; int32_t ret; @@ -3473,7 +3483,7 @@ int32_t lis2ds12_module_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_module_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_module_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_func_ctrl_t func_ctrl; int32_t ret; @@ -3506,7 +3516,7 @@ int32_t lis2ds12_module_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_sh_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_sh_read_data_raw_get(const stmdev_ctx_t *ctx, lis2ds12_sh_read_data_raw_t *val) { int32_t ret; @@ -3525,7 +3535,7 @@ int32_t lis2ds12_sh_read_data_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2ds12_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2ds12_func_ctrl_t func_ctrl; int32_t ret; @@ -3551,7 +3561,7 @@ int32_t lis2ds12_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_func_ctrl_t func_ctrl; int32_t ret; @@ -3574,7 +3584,7 @@ int32_t lis2ds12_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t lis2ds12_sh_cfg_write(const stmdev_ctx_t *ctx, lis2ds12_sh_cfg_write_t *val) { lis2ds12_slv0_add_t slv0_add; @@ -3621,7 +3631,7 @@ int32_t lis2ds12_sh_cfg_write(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_sh_slv_cfg_read(stmdev_ctx_t *ctx, +int32_t lis2ds12_sh_slv_cfg_read(const stmdev_ctx_t *ctx, lis2ds12_sh_cfg_read_t *val) { lis2ds12_slv0_add_t slv0_add; @@ -3673,7 +3683,7 @@ int32_t lis2ds12_sh_slv_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2ds12_sh_end_op_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2ds12_sh_end_op_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2ds12_func_src_t func_src; int32_t ret; diff --git a/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.h b/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.h index a28e55b2..312c0c33 100644 --- a/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.h +++ b/sensor/stmemsc/lis2ds12_STdC/driver/lis2ds12_reg.h @@ -906,10 +906,10 @@ typedef union * them with a custom implementation. */ -int32_t lis2ds12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lis2ds12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lis2ds12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lis2ds12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -930,12 +930,12 @@ typedef struct lis2ds12_func_ck_gate_t func_ck_gate; lis2ds12_func_src_t func_src; } lis2ds12_all_sources_t; -int32_t lis2ds12_all_sources_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_all_sources_get(const stmdev_ctx_t *ctx, lis2ds12_all_sources_t *val); -int32_t lis2ds12_block_data_update_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -945,9 +945,9 @@ typedef enum LIS2DS12_4g = 2, LIS2DS12_8g = 3, } lis2ds12_fs_t; -int32_t lis2ds12_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_xl_full_scale_set(const stmdev_ctx_t *ctx, lis2ds12_fs_t val); -int32_t lis2ds12_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_xl_full_scale_get(const stmdev_ctx_t *ctx, lis2ds12_fs_t *val); typedef enum @@ -972,46 +972,46 @@ typedef enum LIS2DS12_XL_ODR_3k2Hz_HF = 0x16, LIS2DS12_XL_ODR_6k4Hz_HF = 0x17, } lis2ds12_odr_t; -int32_t lis2ds12_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_xl_data_rate_set(const stmdev_ctx_t *ctx, lis2ds12_odr_t val); -int32_t lis2ds12_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_xl_data_rate_get(const stmdev_ctx_t *ctx, lis2ds12_odr_t *val); -int32_t lis2ds12_status_reg_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_status_reg_get(const stmdev_ctx_t *ctx, lis2ds12_status_t *val); -int32_t lis2ds12_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_acceleration_module_raw_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_acceleration_module_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis2ds12_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_temperature_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis2ds12_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lis2ds12_number_of_steps_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lis2ds12_number_of_steps_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lis2ds12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis2ds12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis2ds12_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2ds12_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LIS2DS12_USER_BANK = 0, LIS2DS12_ADV_BANK = 1, } lis2ds12_func_cfg_en_t; -int32_t lis2ds12_mem_bank_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_mem_bank_set(const stmdev_ctx_t *ctx, lis2ds12_func_cfg_en_t val); -int32_t lis2ds12_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2ds12_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2ds12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -1019,9 +1019,9 @@ typedef enum LIS2DS12_XL_ST_POSITIVE = 1, LIS2DS12_XL_ST_NEGATIVE = 2, } lis2ds12_st_t; -int32_t lis2ds12_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_xl_self_test_set(const stmdev_ctx_t *ctx, lis2ds12_st_t val); -int32_t lis2ds12_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_xl_self_test_get(const stmdev_ctx_t *ctx, lis2ds12_st_t *val); typedef enum @@ -1029,9 +1029,9 @@ typedef enum LIS2DS12_DRDY_LATCHED = 0, LIS2DS12_DRDY_PULSED = 1, } lis2ds12_drdy_pulsed_t; -int32_t lis2ds12_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_data_ready_mode_set(const stmdev_ctx_t *ctx, lis2ds12_drdy_pulsed_t val); -int32_t lis2ds12_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_data_ready_mode_get(const stmdev_ctx_t *ctx, lis2ds12_drdy_pulsed_t *val); typedef enum @@ -1039,9 +1039,9 @@ typedef enum LIS2DS12_HP_INTERNAL_ONLY = 0, LIS2DS12_HP_ON_OUTPUTS = 1, } lis2ds12_fds_slope_t; -int32_t lis2ds12_xl_hp_path_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_xl_hp_path_set(const stmdev_ctx_t *ctx, lis2ds12_fds_slope_t val); -int32_t lis2ds12_xl_hp_path_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_xl_hp_path_get(const stmdev_ctx_t *ctx, lis2ds12_fds_slope_t *val); typedef enum @@ -1049,17 +1049,17 @@ typedef enum LIS2DS12_SPI_4_WIRE = 0, LIS2DS12_SPI_3_WIRE = 1, } lis2ds12_sim_t; -int32_t lis2ds12_spi_mode_set(stmdev_ctx_t *ctx, lis2ds12_sim_t val); -int32_t lis2ds12_spi_mode_get(stmdev_ctx_t *ctx, lis2ds12_sim_t *val); +int32_t lis2ds12_spi_mode_set(const stmdev_ctx_t *ctx, lis2ds12_sim_t val); +int32_t lis2ds12_spi_mode_get(const stmdev_ctx_t *ctx, lis2ds12_sim_t *val); typedef enum { LIS2DS12_I2C_ENABLE = 0, LIS2DS12_I2C_DISABLE = 1, } lis2ds12_i2c_disable_t; -int32_t lis2ds12_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_i2c_interface_set(const stmdev_ctx_t *ctx, lis2ds12_i2c_disable_t val); -int32_t lis2ds12_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_i2c_interface_get(const stmdev_ctx_t *ctx, lis2ds12_i2c_disable_t *val); typedef enum @@ -1067,9 +1067,9 @@ typedef enum LIS2DS12_PULL_UP_CONNECTED = 0, LIS2DS12_PULL_UP_DISCONNECTED = 1, } lis2ds12_if_cs_pu_dis_t; -int32_t lis2ds12_cs_mode_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_cs_mode_set(const stmdev_ctx_t *ctx, lis2ds12_if_cs_pu_dis_t val); -int32_t lis2ds12_cs_mode_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_cs_mode_get(const stmdev_ctx_t *ctx, lis2ds12_if_cs_pu_dis_t *val); typedef enum @@ -1077,9 +1077,9 @@ typedef enum LIS2DS12_PUSH_PULL = 0, LIS2DS12_OPEN_DRAIN = 1, } lis2ds12_pp_od_t; -int32_t lis2ds12_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_pin_mode_set(const stmdev_ctx_t *ctx, lis2ds12_pp_od_t val); -int32_t lis2ds12_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_pin_mode_get(const stmdev_ctx_t *ctx, lis2ds12_pp_od_t *val); typedef enum @@ -1087,9 +1087,9 @@ typedef enum LIS2DS12_ACTIVE_HIGH = 0, LIS2DS12_ACTIVE_LOW = 1, } lis2ds12_h_lactive_t; -int32_t lis2ds12_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_pin_polarity_set(const stmdev_ctx_t *ctx, lis2ds12_h_lactive_t val); -int32_t lis2ds12_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_pin_polarity_get(const stmdev_ctx_t *ctx, lis2ds12_h_lactive_t *val); typedef enum @@ -1097,9 +1097,9 @@ typedef enum LIS2DS12_INT_PULSED = 0, LIS2DS12_INT_LATCHED = 1, } lis2ds12_lir_t; -int32_t lis2ds12_int_notification_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_int_notification_set(const stmdev_ctx_t *ctx, lis2ds12_lir_t val); -int32_t lis2ds12_int_notification_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_int_notification_get(const stmdev_ctx_t *ctx, lis2ds12_lir_t *val); typedef struct @@ -1114,9 +1114,9 @@ typedef struct uint8_t int1_master_drdy : 1; uint8_t int1_fss7 : 1; } lis2ds12_pin_int1_route_t; -int32_t lis2ds12_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_pin_int1_route_set(const stmdev_ctx_t *ctx, lis2ds12_pin_int1_route_t val); -int32_t lis2ds12_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_pin_int1_route_get(const stmdev_ctx_t *ctx, lis2ds12_pin_int1_route_t *val); typedef struct @@ -1128,64 +1128,64 @@ typedef struct uint8_t int2_fth : 1; uint8_t int2_drdy : 1; } lis2ds12_pin_int2_route_t; -int32_t lis2ds12_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_pin_int2_route_set(const stmdev_ctx_t *ctx, lis2ds12_pin_int2_route_t val); -int32_t lis2ds12_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_pin_int2_route_get(const stmdev_ctx_t *ctx, lis2ds12_pin_int2_route_t *val); -int32_t lis2ds12_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2ds12_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2ds12_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2ds12_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2ds12_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2ds12_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2ds12_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2ds12_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2ds12_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2ds12_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LIS2DS12_ONLY_SINGLE = 0, LIS2DS12_ONLY_DOUBLE = 1, } lis2ds12_single_double_tap_t; -int32_t lis2ds12_tap_mode_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_tap_mode_set(const stmdev_ctx_t *ctx, lis2ds12_single_double_tap_t val); -int32_t lis2ds12_tap_mode_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_tap_mode_get(const stmdev_ctx_t *ctx, lis2ds12_single_double_tap_t *val); -int32_t lis2ds12_tap_src_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_tap_src_get(const stmdev_ctx_t *ctx, lis2ds12_tap_src_t *val); typedef enum @@ -1195,26 +1195,26 @@ typedef enum LIS2DS12_DEG_60 = 2, LIS2DS12_DEG_50 = 3, } lis2ds12_6d_ths_t; -int32_t lis2ds12_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_6d_threshold_set(const stmdev_ctx_t *ctx, lis2ds12_6d_ths_t val); -int32_t lis2ds12_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_6d_threshold_get(const stmdev_ctx_t *ctx, lis2ds12_6d_ths_t *val); -int32_t lis2ds12_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2ds12_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_6d_src_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_6d_src_get(const stmdev_ctx_t *ctx, lis2ds12_6d_src_t *val); -int32_t lis2ds12_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2ds12_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_ff_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_ff_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_ff_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2ds12_ff_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_fifo_xl_module_batch_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_fifo_xl_module_batch_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_fifo_xl_module_batch_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_fifo_xl_module_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -1225,78 +1225,78 @@ typedef enum LIS2DS12_BYPASS_TO_STREAM_MODE = 4, LIS2DS12_STREAM_MODE = 6, } lis2ds12_fmode_t; -int32_t lis2ds12_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2ds12_fmode_t val); -int32_t lis2ds12_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2ds12_fmode_t *val); -int32_t lis2ds12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2ds12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_fifo_data_level_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lis2ds12_fifo_src_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_fifo_src_get(const stmdev_ctx_t *ctx, lis2ds12_fifo_src_t *val); -int32_t lis2ds12_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_pedo_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2ds12_pedo_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LIS2DS12_PEDO_AT_2g = 0, LIS2DS12_PEDO_AT_4g = 1, } lis2ds12_pedo4g_t; -int32_t lis2ds12_pedo_full_scale_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_pedo_full_scale_set(const stmdev_ctx_t *ctx, lis2ds12_pedo4g_t val); -int32_t lis2ds12_pedo_full_scale_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_pedo_full_scale_get(const stmdev_ctx_t *ctx, lis2ds12_pedo4g_t *val); -int32_t lis2ds12_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_pedo_step_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2ds12_pedo_step_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_pedo_step_detect_flag_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_pedo_step_detect_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2ds12_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_pedo_debounce_steps_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_pedo_debounce_steps_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_pedo_timeout_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2ds12_pedo_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_pedo_steps_period_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_pedo_steps_period_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis2ds12_pedo_steps_period_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_pedo_steps_period_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis2ds12_motion_data_ready_flag_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_motion_data_ready_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2ds12_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_motion_threshold_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_motion_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2ds12_motion_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_tilt_data_ready_flag_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_tilt_data_ready_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2ds12_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_module_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_module_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_module_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2ds12_module_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -1307,20 +1307,20 @@ typedef struct lis2ds12_sensorhub5_reg_t sensorhub5_reg; lis2ds12_sensorhub6_reg_t sensorhub6_reg; } lis2ds12_sh_read_data_raw_t; -int32_t lis2ds12_sh_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_sh_read_data_raw_get(const stmdev_ctx_t *ctx, lis2ds12_sh_read_data_raw_t *val); -int32_t lis2ds12_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2ds12_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LIS2DS12_EXT_PULL_UP = 0, LIS2DS12_INTERNAL_PULL_UP = 1, } lis2ds12_tud_en_t; -int32_t lis2ds12_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lis2ds12_sh_pin_mode_set(const stmdev_ctx_t *ctx, lis2ds12_tud_en_t val); -int32_t lis2ds12_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_sh_pin_mode_get(const stmdev_ctx_t *ctx, lis2ds12_tud_en_t *val); typedef struct @@ -1329,7 +1329,7 @@ typedef struct uint8_t slv_subadd; uint8_t slv_data; } lis2ds12_sh_cfg_write_t; -int32_t lis2ds12_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t lis2ds12_sh_cfg_write(const stmdev_ctx_t *ctx, lis2ds12_sh_cfg_write_t *val); typedef struct @@ -1338,14 +1338,14 @@ typedef struct uint8_t slv_subadd; uint8_t slv_len; } lis2ds12_sh_cfg_read_t; -int32_t lis2ds12_sh_slv_cfg_read(stmdev_ctx_t *ctx, +int32_t lis2ds12_sh_slv_cfg_read(const stmdev_ctx_t *ctx, lis2ds12_sh_cfg_read_t *val); -int32_t lis2ds12_sh_slv0_cfg_read_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2ds12_sh_slv0_cfg_read_get(stmdev_ctx_t *ctx, +int32_t lis2ds12_sh_slv0_cfg_read_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2ds12_sh_slv0_cfg_read_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2ds12_sh_end_op_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2ds12_sh_end_op_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); /** * @} diff --git a/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.c b/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.c index f89f3031..64a0e1a2 100644 --- a/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.c +++ b/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis2dtw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lis2dtw12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lis2dtw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis2dtw12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lis2dtw12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -157,7 +167,7 @@ float_t lis2dtw12_from_lsb_to_celsius(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_power_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_power_mode_set(const stmdev_ctx_t *ctx, lis2dtw12_mode_t val) { lis2dtw12_ctrl1_t ctrl1; @@ -196,7 +206,7 @@ int32_t lis2dtw12_power_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_power_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_power_mode_get(const stmdev_ctx_t *ctx, lis2dtw12_mode_t *val) { lis2dtw12_ctrl1_t ctrl1; @@ -301,7 +311,7 @@ int32_t lis2dtw12_power_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_data_rate_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_data_rate_set(const stmdev_ctx_t *ctx, lis2dtw12_odr_t val) { lis2dtw12_ctrl1_t ctrl1; @@ -338,7 +348,7 @@ int32_t lis2dtw12_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_data_rate_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_data_rate_get(const stmdev_ctx_t *ctx, lis2dtw12_odr_t *val) { lis2dtw12_ctrl1_t ctrl1; @@ -418,7 +428,7 @@ int32_t lis2dtw12_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_block_data_update_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dtw12_ctrl2_t reg; @@ -443,7 +453,7 @@ int32_t lis2dtw12_block_data_update_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dtw12_ctrl2_t reg; @@ -463,7 +473,7 @@ int32_t lis2dtw12_block_data_update_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_full_scale_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_full_scale_set(const stmdev_ctx_t *ctx, lis2dtw12_fs_t val) { lis2dtw12_ctrl6_t reg; @@ -488,7 +498,7 @@ int32_t lis2dtw12_full_scale_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_full_scale_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_full_scale_get(const stmdev_ctx_t *ctx, lis2dtw12_fs_t *val) { lis2dtw12_ctrl6_t reg; @@ -530,7 +540,7 @@ int32_t lis2dtw12_full_scale_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_status_reg_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_status_reg_get(const stmdev_ctx_t *ctx, lis2dtw12_status_t *val) { int32_t ret; @@ -548,7 +558,7 @@ int32_t lis2dtw12_status_reg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dtw12_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dtw12_status_t reg; int32_t ret; @@ -567,7 +577,7 @@ int32_t lis2dtw12_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_all_sources_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_all_sources_get(const stmdev_ctx_t *ctx, lis2dtw12_all_sources_t *val) { int32_t ret; @@ -588,7 +598,7 @@ int32_t lis2dtw12_all_sources_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis2dtw12_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -607,7 +617,7 @@ int32_t lis2dtw12_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis2dtw12_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -626,7 +636,7 @@ int32_t lis2dtw12_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis2dtw12_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -645,7 +655,7 @@ int32_t lis2dtw12_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis2dtw12_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -664,7 +674,7 @@ int32_t lis2dtw12_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis2dtw12_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -683,7 +693,7 @@ int32_t lis2dtw12_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis2dtw12_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -702,7 +712,7 @@ int32_t lis2dtw12_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_offset_weight_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_offset_weight_set(const stmdev_ctx_t *ctx, lis2dtw12_usr_off_w_t val) { lis2dtw12_ctrl_reg7_t reg; @@ -728,7 +738,7 @@ int32_t lis2dtw12_offset_weight_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_offset_weight_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_offset_weight_get(const stmdev_ctx_t *ctx, lis2dtw12_usr_off_w_t *val) { lis2dtw12_ctrl_reg7_t reg; @@ -775,7 +785,7 @@ int32_t lis2dtw12_offset_weight_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lis2dtw12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -796,7 +806,7 @@ int32_t lis2dtw12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -833,7 +843,7 @@ int32_t lis2dtw12_acceleration_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis2dtw12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -851,7 +861,7 @@ int32_t lis2dtw12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dtw12_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dtw12_ctrl2_t reg; int32_t ret; @@ -876,7 +886,7 @@ int32_t lis2dtw12_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dtw12_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dtw12_ctrl2_t reg; int32_t ret; @@ -895,7 +905,7 @@ int32_t lis2dtw12_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dtw12_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dtw12_ctrl2_t reg; int32_t ret; @@ -919,7 +929,7 @@ int32_t lis2dtw12_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dtw12_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dtw12_ctrl2_t reg; int32_t ret; @@ -938,7 +948,7 @@ int32_t lis2dtw12_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dtw12_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dtw12_ctrl2_t reg; int32_t ret; @@ -962,7 +972,7 @@ int32_t lis2dtw12_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dtw12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dtw12_ctrl2_t reg; int32_t ret; @@ -981,7 +991,7 @@ int32_t lis2dtw12_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_self_test_set(stmdev_ctx_t *ctx, lis2dtw12_st_t val) +int32_t lis2dtw12_self_test_set(const stmdev_ctx_t *ctx, lis2dtw12_st_t val) { lis2dtw12_ctrl3_t reg; int32_t ret; @@ -1005,7 +1015,7 @@ int32_t lis2dtw12_self_test_set(stmdev_ctx_t *ctx, lis2dtw12_st_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_self_test_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_self_test_get(const stmdev_ctx_t *ctx, lis2dtw12_st_t *val) { lis2dtw12_ctrl3_t reg; @@ -1043,7 +1053,7 @@ int32_t lis2dtw12_self_test_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_data_ready_mode_set(const stmdev_ctx_t *ctx, lis2dtw12_drdy_pulsed_t val) { lis2dtw12_ctrl_reg7_t reg; @@ -1068,7 +1078,7 @@ int32_t lis2dtw12_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_data_ready_mode_get(const stmdev_ctx_t *ctx, lis2dtw12_drdy_pulsed_t *val) { lis2dtw12_ctrl_reg7_t reg; @@ -1115,7 +1125,7 @@ int32_t lis2dtw12_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_filter_path_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_filter_path_set(const stmdev_ctx_t *ctx, lis2dtw12_fds_t val) { lis2dtw12_ctrl6_t ctrl6; @@ -1154,7 +1164,7 @@ int32_t lis2dtw12_filter_path_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_filter_path_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_filter_path_get(const stmdev_ctx_t *ctx, lis2dtw12_fds_t *val) { lis2dtw12_ctrl6_t ctrl6; @@ -1200,7 +1210,7 @@ int32_t lis2dtw12_filter_path_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_filter_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_filter_bandwidth_set(const stmdev_ctx_t *ctx, lis2dtw12_bw_filt_t val) { lis2dtw12_ctrl6_t reg; @@ -1226,7 +1236,7 @@ int32_t lis2dtw12_filter_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_filter_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_filter_bandwidth_get(const stmdev_ctx_t *ctx, lis2dtw12_bw_filt_t *val) { lis2dtw12_ctrl6_t reg; @@ -1268,7 +1278,7 @@ int32_t lis2dtw12_filter_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dtw12_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dtw12_ctrl_reg7_t reg; int32_t ret; @@ -1292,7 +1302,7 @@ int32_t lis2dtw12_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dtw12_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dtw12_ctrl_reg7_t reg; int32_t ret; @@ -1324,7 +1334,7 @@ int32_t lis2dtw12_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_spi_mode_set(stmdev_ctx_t *ctx, lis2dtw12_sim_t val) +int32_t lis2dtw12_spi_mode_set(const stmdev_ctx_t *ctx, lis2dtw12_sim_t val) { lis2dtw12_ctrl2_t reg; int32_t ret; @@ -1348,7 +1358,7 @@ int32_t lis2dtw12_spi_mode_set(stmdev_ctx_t *ctx, lis2dtw12_sim_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_spi_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_spi_mode_get(const stmdev_ctx_t *ctx, lis2dtw12_sim_t *val) { lis2dtw12_ctrl2_t reg; @@ -1383,7 +1393,7 @@ int32_t lis2dtw12_spi_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_i2c_interface_set(const stmdev_ctx_t *ctx, lis2dtw12_i2c_disable_t val) { lis2dtw12_ctrl2_t reg; @@ -1408,7 +1418,7 @@ int32_t lis2dtw12_i2c_interface_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_i2c_interface_get(const stmdev_ctx_t *ctx, lis2dtw12_i2c_disable_t *val) { lis2dtw12_ctrl2_t reg; @@ -1442,7 +1452,7 @@ int32_t lis2dtw12_i2c_interface_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_cs_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_cs_mode_set(const stmdev_ctx_t *ctx, lis2dtw12_cs_pu_disc_t val) { lis2dtw12_ctrl2_t reg; @@ -1467,7 +1477,7 @@ int32_t lis2dtw12_cs_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_cs_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_cs_mode_get(const stmdev_ctx_t *ctx, lis2dtw12_cs_pu_disc_t *val) { lis2dtw12_ctrl2_t reg; @@ -1513,7 +1523,7 @@ int32_t lis2dtw12_cs_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_pin_polarity_set(const stmdev_ctx_t *ctx, lis2dtw12_h_lactive_t val) { lis2dtw12_ctrl3_t reg; @@ -1538,7 +1548,7 @@ int32_t lis2dtw12_pin_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_pin_polarity_get(const stmdev_ctx_t *ctx, lis2dtw12_h_lactive_t *val) { lis2dtw12_ctrl3_t reg; @@ -1572,7 +1582,7 @@ int32_t lis2dtw12_pin_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_int_notification_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_int_notification_set(const stmdev_ctx_t *ctx, lis2dtw12_lir_t val) { lis2dtw12_ctrl3_t reg; @@ -1597,7 +1607,7 @@ int32_t lis2dtw12_int_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_int_notification_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_int_notification_get(const stmdev_ctx_t *ctx, lis2dtw12_lir_t *val) { lis2dtw12_ctrl3_t reg; @@ -1631,7 +1641,7 @@ int32_t lis2dtw12_int_notification_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_pin_mode_set(const stmdev_ctx_t *ctx, lis2dtw12_pp_od_t val) { lis2dtw12_ctrl3_t reg; @@ -1656,7 +1666,7 @@ int32_t lis2dtw12_pin_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_pin_mode_get(const stmdev_ctx_t *ctx, lis2dtw12_pp_od_t *val) { lis2dtw12_ctrl3_t reg; @@ -1690,7 +1700,7 @@ int32_t lis2dtw12_pin_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_pin_int1_route_set(const stmdev_ctx_t *ctx, lis2dtw12_ctrl4_int1_pad_ctrl_t *val) { lis2dtw12_ctrl_reg7_t reg; @@ -1732,7 +1742,7 @@ int32_t lis2dtw12_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_pin_int1_route_get(const stmdev_ctx_t *ctx, lis2dtw12_ctrl4_int1_pad_ctrl_t *val) { int32_t ret; @@ -1751,7 +1761,7 @@ int32_t lis2dtw12_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_pin_int2_route_set(const stmdev_ctx_t *ctx, lis2dtw12_ctrl5_int2_pad_ctrl_t *val) { lis2dtw12_ctrl_reg7_t reg; @@ -1792,7 +1802,7 @@ int32_t lis2dtw12_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_pin_int2_route_get(const stmdev_ctx_t *ctx, lis2dtw12_ctrl5_int2_pad_ctrl_t *val) { int32_t ret; @@ -1810,7 +1820,7 @@ int32_t lis2dtw12_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dtw12_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dtw12_ctrl_reg7_t reg; int32_t ret; @@ -1834,7 +1844,7 @@ int32_t lis2dtw12_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dtw12_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dtw12_ctrl_reg7_t reg; int32_t ret; @@ -1866,7 +1876,7 @@ int32_t lis2dtw12_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dtw12_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dtw12_wake_up_ths_t reg; int32_t ret; @@ -1891,7 +1901,7 @@ int32_t lis2dtw12_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dtw12_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dtw12_wake_up_ths_t reg; int32_t ret; @@ -1910,7 +1920,7 @@ int32_t lis2dtw12_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dtw12_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dtw12_wake_up_dur_t reg; int32_t ret; @@ -1935,7 +1945,7 @@ int32_t lis2dtw12_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dtw12_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dtw12_wake_up_dur_t reg; int32_t ret; @@ -1954,7 +1964,7 @@ int32_t lis2dtw12_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_wkup_feed_data_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_wkup_feed_data_set(const stmdev_ctx_t *ctx, lis2dtw12_usr_off_on_wu_t val) { lis2dtw12_ctrl_reg7_t reg; @@ -1979,7 +1989,7 @@ int32_t lis2dtw12_wkup_feed_data_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_wkup_feed_data_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_wkup_feed_data_get(const stmdev_ctx_t *ctx, lis2dtw12_usr_off_on_wu_t *val) { lis2dtw12_ctrl_reg7_t reg; @@ -2028,7 +2038,7 @@ int32_t lis2dtw12_wkup_feed_data_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_act_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_act_mode_set(const stmdev_ctx_t *ctx, lis2dtw12_sleep_on_t val) { lis2dtw12_wake_up_ths_t wake_up_ths; @@ -2070,7 +2080,7 @@ int32_t lis2dtw12_act_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_act_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_act_mode_get(const stmdev_ctx_t *ctx, lis2dtw12_sleep_on_t *val) { lis2dtw12_wake_up_ths_t wake_up_ths; @@ -2116,7 +2126,7 @@ int32_t lis2dtw12_act_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dtw12_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dtw12_wake_up_dur_t reg; int32_t ret; @@ -2141,7 +2151,7 @@ int32_t lis2dtw12_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dtw12_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dtw12_wake_up_dur_t reg; int32_t ret; @@ -2173,7 +2183,7 @@ int32_t lis2dtw12_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dtw12_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dtw12_tap_ths_x_t reg; int32_t ret; @@ -2197,7 +2207,7 @@ int32_t lis2dtw12_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dtw12_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dtw12_tap_ths_x_t reg; int32_t ret; @@ -2216,7 +2226,7 @@ int32_t lis2dtw12_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dtw12_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dtw12_tap_ths_y_t reg; int32_t ret; @@ -2240,7 +2250,7 @@ int32_t lis2dtw12_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dtw12_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dtw12_tap_ths_y_t reg; int32_t ret; @@ -2259,7 +2269,7 @@ int32_t lis2dtw12_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_tap_axis_priority_set(const stmdev_ctx_t *ctx, lis2dtw12_tap_prior_t val) { lis2dtw12_tap_ths_y_t reg; @@ -2284,7 +2294,7 @@ int32_t lis2dtw12_tap_axis_priority_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_tap_axis_priority_get(const stmdev_ctx_t *ctx, lis2dtw12_tap_prior_t *val) { lis2dtw12_tap_ths_y_t reg; @@ -2334,7 +2344,7 @@ int32_t lis2dtw12_tap_axis_priority_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dtw12_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dtw12_tap_ths_z_t reg; int32_t ret; @@ -2358,7 +2368,7 @@ int32_t lis2dtw12_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dtw12_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dtw12_tap_ths_z_t reg; int32_t ret; @@ -2377,7 +2387,7 @@ int32_t lis2dtw12_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dtw12_tap_ths_z_t reg; @@ -2402,7 +2412,7 @@ int32_t lis2dtw12_tap_detection_on_z_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dtw12_tap_ths_z_t reg; @@ -2422,7 +2432,7 @@ int32_t lis2dtw12_tap_detection_on_z_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dtw12_tap_ths_z_t reg; @@ -2447,7 +2457,7 @@ int32_t lis2dtw12_tap_detection_on_y_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dtw12_tap_ths_z_t reg; @@ -2467,7 +2477,7 @@ int32_t lis2dtw12_tap_detection_on_y_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dtw12_tap_ths_z_t reg; @@ -2492,7 +2502,7 @@ int32_t lis2dtw12_tap_detection_on_x_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dtw12_tap_ths_z_t reg; @@ -2516,7 +2526,7 @@ int32_t lis2dtw12_tap_detection_on_x_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dtw12_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dtw12_int_dur_t reg; int32_t ret; @@ -2544,7 +2554,7 @@ int32_t lis2dtw12_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dtw12_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dtw12_int_dur_t reg; int32_t ret; @@ -2567,7 +2577,7 @@ int32_t lis2dtw12_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dtw12_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dtw12_int_dur_t reg; int32_t ret; @@ -2595,7 +2605,7 @@ int32_t lis2dtw12_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dtw12_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dtw12_int_dur_t reg; int32_t ret; @@ -2619,7 +2629,7 @@ int32_t lis2dtw12_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dtw12_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dtw12_int_dur_t reg; int32_t ret; @@ -2648,7 +2658,7 @@ int32_t lis2dtw12_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dtw12_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dtw12_int_dur_t reg; int32_t ret; @@ -2667,7 +2677,7 @@ int32_t lis2dtw12_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_tap_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_tap_mode_set(const stmdev_ctx_t *ctx, lis2dtw12_single_double_tap_t val) { lis2dtw12_wake_up_ths_t reg; @@ -2693,7 +2703,7 @@ int32_t lis2dtw12_tap_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_tap_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_tap_mode_get(const stmdev_ctx_t *ctx, lis2dtw12_single_double_tap_t *val) { lis2dtw12_wake_up_ths_t reg; @@ -2727,7 +2737,7 @@ int32_t lis2dtw12_tap_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_tap_src_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_tap_src_get(const stmdev_ctx_t *ctx, lis2dtw12_tap_src_t *val) { int32_t ret; @@ -2758,7 +2768,7 @@ int32_t lis2dtw12_tap_src_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dtw12_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dtw12_tap_ths_x_t reg; int32_t ret; @@ -2782,7 +2792,7 @@ int32_t lis2dtw12_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dtw12_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dtw12_tap_ths_x_t reg; int32_t ret; @@ -2801,7 +2811,7 @@ int32_t lis2dtw12_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dtw12_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dtw12_tap_ths_x_t reg; int32_t ret; @@ -2825,7 +2835,7 @@ int32_t lis2dtw12_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dtw12_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dtw12_tap_ths_x_t reg; int32_t ret; @@ -2844,7 +2854,7 @@ int32_t lis2dtw12_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_6d_src_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_6d_src_get(const stmdev_ctx_t *ctx, lis2dtw12_sixd_src_t *val) { int32_t ret; @@ -2861,7 +2871,7 @@ int32_t lis2dtw12_6d_src_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_6d_feed_data_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_6d_feed_data_set(const stmdev_ctx_t *ctx, lis2dtw12_lpass_on6d_t val) { lis2dtw12_ctrl_reg7_t reg; @@ -2886,7 +2896,7 @@ int32_t lis2dtw12_6d_feed_data_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_6d_feed_data_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_6d_feed_data_get(const stmdev_ctx_t *ctx, lis2dtw12_lpass_on6d_t *val) { lis2dtw12_ctrl_reg7_t reg; @@ -2934,7 +2944,7 @@ int32_t lis2dtw12_6d_feed_data_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dtw12_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dtw12_wake_up_dur_t wake_up_dur; lis2dtw12_free_fall_t free_fall; @@ -2975,7 +2985,7 @@ int32_t lis2dtw12_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dtw12_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dtw12_wake_up_dur_t wake_up_dur; lis2dtw12_free_fall_t free_fall; @@ -3002,7 +3012,7 @@ int32_t lis2dtw12_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_ff_threshold_set(const stmdev_ctx_t *ctx, lis2dtw12_ff_ths_t val) { lis2dtw12_free_fall_t reg; @@ -3027,7 +3037,7 @@ int32_t lis2dtw12_ff_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_ff_threshold_get(const stmdev_ctx_t *ctx, lis2dtw12_ff_ths_t *val) { lis2dtw12_free_fall_t reg; @@ -3097,7 +3107,7 @@ int32_t lis2dtw12_ff_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dtw12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dtw12_fifo_ctrl_t reg; int32_t ret; @@ -3121,7 +3131,7 @@ int32_t lis2dtw12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dtw12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dtw12_fifo_ctrl_t reg; int32_t ret; @@ -3140,7 +3150,7 @@ int32_t lis2dtw12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2dtw12_fmode_t val) { lis2dtw12_fifo_ctrl_t reg; @@ -3165,7 +3175,7 @@ int32_t lis2dtw12_fifo_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2dtw12_fmode_t *val) { lis2dtw12_fifo_ctrl_t reg; @@ -3211,7 +3221,7 @@ int32_t lis2dtw12_fifo_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dtw12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dtw12_fifo_samples_t reg; int32_t ret; @@ -3230,7 +3240,7 @@ int32_t lis2dtw12_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dtw12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dtw12_fifo_samples_t reg; int32_t ret; @@ -3249,7 +3259,7 @@ int32_t lis2dtw12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dtw12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dtw12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dtw12_fifo_samples_t reg; int32_t ret; diff --git a/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.h b/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.h index 5a51e7a6..e66da51e 100644 --- a/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.h +++ b/sensor/stmemsc/lis2dtw12_STdC/driver/lis2dtw12_reg.h @@ -225,8 +225,7 @@ typedef struct typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN -uint8_t slp_mode : - 2; /* slp_mode_sel + slp_mode_1 */ + uint8_t slp_mode : 2; /* slp_mode_sel + slp_mode_1 */ uint8_t not_used_01 : 1; uint8_t h_lactive : 1; uint8_t lir : 1; @@ -238,8 +237,7 @@ uint8_t slp_mode : uint8_t lir : 1; uint8_t h_lactive : 1; uint8_t not_used_01 : 1; -uint8_t slp_mode : - 2; /* slp_mode_sel + slp_mode_1 */ + uint8_t slp_mode : 2; /* slp_mode_sel + slp_mode_1 */ #endif /* DRV_BYTE_ORDER */ } lis2dtw12_ctrl3_t; @@ -667,10 +665,10 @@ typedef union * them with a custom implementation. */ -int32_t lis2dtw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lis2dtw12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lis2dtw12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lis2dtw12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -707,9 +705,9 @@ typedef enum LIS2DTW12_SINGLE_LOW_PWR_LOW_NOISE_2 = 0x19, LIS2DTW12_SINGLE_LOW_LOW_NOISE_PWR_12bit = 0x18, } lis2dtw12_mode_t; -int32_t lis2dtw12_power_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_power_mode_set(const stmdev_ctx_t *ctx, lis2dtw12_mode_t val); -int32_t lis2dtw12_power_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_power_mode_get(const stmdev_ctx_t *ctx, lis2dtw12_mode_t *val); typedef enum @@ -727,14 +725,14 @@ typedef enum LIS2DTW12_XL_SET_SW_TRIG = 0x12, /* Use this only in SINGLE mode */ LIS2DTW12_XL_SET_PIN_TRIG = 0x22, /* Use this only in SINGLE mode */ } lis2dtw12_odr_t; -int32_t lis2dtw12_data_rate_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_data_rate_set(const stmdev_ctx_t *ctx, lis2dtw12_odr_t val); -int32_t lis2dtw12_data_rate_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_data_rate_get(const stmdev_ctx_t *ctx, lis2dtw12_odr_t *val); -int32_t lis2dtw12_block_data_update_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dtw12_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -744,15 +742,15 @@ typedef enum LIS2DTW12_8g = 2, LIS2DTW12_16g = 3, } lis2dtw12_fs_t; -int32_t lis2dtw12_full_scale_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_full_scale_set(const stmdev_ctx_t *ctx, lis2dtw12_fs_t val); -int32_t lis2dtw12_full_scale_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_full_scale_get(const stmdev_ctx_t *ctx, lis2dtw12_fs_t *val); -int32_t lis2dtw12_status_reg_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_status_reg_get(const stmdev_ctx_t *ctx, lis2dtw12_status_t *val); -int32_t lis2dtw12_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct @@ -763,44 +761,44 @@ typedef struct lis2dtw12_sixd_src_t sixd_src; lis2dtw12_all_int_src_t all_int_src; } lis2dtw12_all_sources_t; -int32_t lis2dtw12_all_sources_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_all_sources_get(const stmdev_ctx_t *ctx, lis2dtw12_all_sources_t *val); -int32_t lis2dtw12_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis2dtw12_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis2dtw12_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis2dtw12_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis2dtw12_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis2dtw12_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis2dtw12_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis2dtw12_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis2dtw12_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis2dtw12_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis2dtw12_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis2dtw12_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff); typedef enum { LIS2DTW12_LSb_977ug = 0, LIS2DTW12_LSb_15mg6 = 1, } lis2dtw12_usr_off_w_t; -int32_t lis2dtw12_offset_weight_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_offset_weight_set(const stmdev_ctx_t *ctx, lis2dtw12_usr_off_w_t val); -int32_t lis2dtw12_offset_weight_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_offset_weight_get(const stmdev_ctx_t *ctx, lis2dtw12_usr_off_w_t *val); -int32_t lis2dtw12_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lis2dtw12_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lis2dtw12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis2dtw12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis2dtw12_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dtw12_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dtw12_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dtw12_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dtw12_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dtw12_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dtw12_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dtw12_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dtw12_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dtw12_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dtw12_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dtw12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -808,9 +806,9 @@ typedef enum LIS2DTW12_XL_ST_POSITIVE = 1, LIS2DTW12_XL_ST_NEGATIVE = 2, } lis2dtw12_st_t; -int32_t lis2dtw12_self_test_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_self_test_set(const stmdev_ctx_t *ctx, lis2dtw12_st_t val); -int32_t lis2dtw12_self_test_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_self_test_get(const stmdev_ctx_t *ctx, lis2dtw12_st_t *val); typedef enum @@ -818,9 +816,9 @@ typedef enum LIS2DTW12_DRDY_LATCHED = 0, LIS2DTW12_DRDY_PULSED = 1, } lis2dtw12_drdy_pulsed_t; -int32_t lis2dtw12_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_data_ready_mode_set(const stmdev_ctx_t *ctx, lis2dtw12_drdy_pulsed_t val); -int32_t lis2dtw12_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_data_ready_mode_get(const stmdev_ctx_t *ctx, lis2dtw12_drdy_pulsed_t *val); typedef enum @@ -829,9 +827,9 @@ typedef enum LIS2DTW12_USER_OFFSET_ON_OUT = 0x01, LIS2DTW12_HIGH_PASS_ON_OUT = 0x10, } lis2dtw12_fds_t; -int32_t lis2dtw12_filter_path_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_filter_path_set(const stmdev_ctx_t *ctx, lis2dtw12_fds_t val); -int32_t lis2dtw12_filter_path_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_filter_path_get(const stmdev_ctx_t *ctx, lis2dtw12_fds_t *val); typedef enum @@ -841,22 +839,22 @@ typedef enum LIS2DTW12_ODR_DIV_10 = 2, LIS2DTW12_ODR_DIV_20 = 3, } lis2dtw12_bw_filt_t; -int32_t lis2dtw12_filter_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_filter_bandwidth_set(const stmdev_ctx_t *ctx, lis2dtw12_bw_filt_t val); -int32_t lis2dtw12_filter_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_filter_bandwidth_get(const stmdev_ctx_t *ctx, lis2dtw12_bw_filt_t *val); -int32_t lis2dtw12_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dtw12_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dtw12_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dtw12_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LIS2DTW12_SPI_4_WIRE = 0, LIS2DTW12_SPI_3_WIRE = 1, } lis2dtw12_sim_t; -int32_t lis2dtw12_spi_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_spi_mode_set(const stmdev_ctx_t *ctx, lis2dtw12_sim_t val); -int32_t lis2dtw12_spi_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_spi_mode_get(const stmdev_ctx_t *ctx, lis2dtw12_sim_t *val); typedef enum @@ -864,9 +862,9 @@ typedef enum LIS2DTW12_I2C_ENABLE = 0, LIS2DTW12_I2C_DISABLE = 1, } lis2dtw12_i2c_disable_t; -int32_t lis2dtw12_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_i2c_interface_set(const stmdev_ctx_t *ctx, lis2dtw12_i2c_disable_t val); -int32_t lis2dtw12_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_i2c_interface_get(const stmdev_ctx_t *ctx, lis2dtw12_i2c_disable_t *val); typedef enum @@ -874,9 +872,9 @@ typedef enum LIS2DTW12_PULL_UP_CONNECT = 0, LIS2DTW12_PULL_UP_DISCONNECT = 1, } lis2dtw12_cs_pu_disc_t; -int32_t lis2dtw12_cs_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_cs_mode_set(const stmdev_ctx_t *ctx, lis2dtw12_cs_pu_disc_t val); -int32_t lis2dtw12_cs_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_cs_mode_get(const stmdev_ctx_t *ctx, lis2dtw12_cs_pu_disc_t *val); typedef enum @@ -884,9 +882,9 @@ typedef enum LIS2DTW12_ACTIVE_HIGH = 0, LIS2DTW12_ACTIVE_LOW = 1, } lis2dtw12_h_lactive_t; -int32_t lis2dtw12_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_pin_polarity_set(const stmdev_ctx_t *ctx, lis2dtw12_h_lactive_t val); -int32_t lis2dtw12_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_pin_polarity_get(const stmdev_ctx_t *ctx, lis2dtw12_h_lactive_t *val); typedef enum @@ -894,9 +892,9 @@ typedef enum LIS2DTW12_INT_PULSED = 0, LIS2DTW12_INT_LATCHED = 1, } lis2dtw12_lir_t; -int32_t lis2dtw12_int_notification_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_int_notification_set(const stmdev_ctx_t *ctx, lis2dtw12_lir_t val); -int32_t lis2dtw12_int_notification_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_int_notification_get(const stmdev_ctx_t *ctx, lis2dtw12_lir_t *val); typedef enum @@ -904,38 +902,38 @@ typedef enum LIS2DTW12_PUSH_PULL = 0, LIS2DTW12_OPEN_DRAIN = 1, } lis2dtw12_pp_od_t; -int32_t lis2dtw12_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_pin_mode_set(const stmdev_ctx_t *ctx, lis2dtw12_pp_od_t val); -int32_t lis2dtw12_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_pin_mode_get(const stmdev_ctx_t *ctx, lis2dtw12_pp_od_t *val); -int32_t lis2dtw12_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_pin_int1_route_set(const stmdev_ctx_t *ctx, lis2dtw12_ctrl4_int1_pad_ctrl_t *val); -int32_t lis2dtw12_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_pin_int1_route_get(const stmdev_ctx_t *ctx, lis2dtw12_ctrl4_int1_pad_ctrl_t *val); -int32_t lis2dtw12_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_pin_int2_route_set(const stmdev_ctx_t *ctx, lis2dtw12_ctrl5_int2_pad_ctrl_t *val); -int32_t lis2dtw12_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_pin_int2_route_get(const stmdev_ctx_t *ctx, lis2dtw12_ctrl5_int2_pad_ctrl_t *val); -int32_t lis2dtw12_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dtw12_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dtw12_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dtw12_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dtw12_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dtw12_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dtw12_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dtw12_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dtw12_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dtw12_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dtw12_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dtw12_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LIS2DTW12_HP_FEED = 0, LIS2DTW12_USER_OFFSET_FEED = 1, } lis2dtw12_usr_off_on_wu_t; -int32_t lis2dtw12_wkup_feed_data_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_wkup_feed_data_set(const stmdev_ctx_t *ctx, lis2dtw12_usr_off_on_wu_t val); -int32_t lis2dtw12_wkup_feed_data_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_wkup_feed_data_get(const stmdev_ctx_t *ctx, lis2dtw12_usr_off_on_wu_t *val); typedef enum @@ -944,20 +942,20 @@ typedef enum LIS2DTW12_DETECT_ACT_INACT = 1, LIS2DTW12_DETECT_STAT_MOTION = 3, } lis2dtw12_sleep_on_t; -int32_t lis2dtw12_act_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_act_mode_set(const stmdev_ctx_t *ctx, lis2dtw12_sleep_on_t val); -int32_t lis2dtw12_act_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_act_mode_get(const stmdev_ctx_t *ctx, lis2dtw12_sleep_on_t *val); -int32_t lis2dtw12_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dtw12_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dtw12_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dtw12_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dtw12_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dtw12_tap_threshold_x_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dtw12_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dtw12_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dtw12_tap_threshold_y_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dtw12_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -969,59 +967,59 @@ typedef enum LIS2DTW12_YZX = 5, LIS2DTW12_ZXY = 6, } lis2dtw12_tap_prior_t; -int32_t lis2dtw12_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_tap_axis_priority_set(const stmdev_ctx_t *ctx, lis2dtw12_tap_prior_t val); -int32_t lis2dtw12_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_tap_axis_priority_get(const stmdev_ctx_t *ctx, lis2dtw12_tap_prior_t *val); -int32_t lis2dtw12_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dtw12_tap_threshold_z_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dtw12_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dtw12_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dtw12_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dtw12_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dtw12_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dtw12_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dtw12_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dtw12_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dtw12_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dtw12_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dtw12_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dtw12_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dtw12_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dtw12_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dtw12_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dtw12_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dtw12_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dtw12_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dtw12_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LIS2DTW12_ONLY_SINGLE = 0, LIS2DTW12_BOTH_SINGLE_DOUBLE = 1, } lis2dtw12_single_double_tap_t; -int32_t lis2dtw12_tap_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_tap_mode_set(const stmdev_ctx_t *ctx, lis2dtw12_single_double_tap_t val); -int32_t lis2dtw12_tap_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_tap_mode_get(const stmdev_ctx_t *ctx, lis2dtw12_single_double_tap_t *val); -int32_t lis2dtw12_tap_src_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_tap_src_get(const stmdev_ctx_t *ctx, lis2dtw12_tap_src_t *val); -int32_t lis2dtw12_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dtw12_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dtw12_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dtw12_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dtw12_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dtw12_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dtw12_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dtw12_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dtw12_6d_src_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_6d_src_get(const stmdev_ctx_t *ctx, lis2dtw12_sixd_src_t *val); typedef enum @@ -1029,13 +1027,13 @@ typedef enum LIS2DTW12_ODR_DIV_2_FEED = 0, LIS2DTW12_LPF2_FEED = 1, } lis2dtw12_lpass_on6d_t; -int32_t lis2dtw12_6d_feed_data_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_6d_feed_data_set(const stmdev_ctx_t *ctx, lis2dtw12_lpass_on6d_t val); -int32_t lis2dtw12_6d_feed_data_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_6d_feed_data_get(const stmdev_ctx_t *ctx, lis2dtw12_lpass_on6d_t *val); -int32_t lis2dtw12_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dtw12_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dtw12_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dtw12_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -1048,13 +1046,13 @@ typedef enum LIS2DTW12_FF_TSH_15LSb_FS2g = 6, LIS2DTW12_FF_TSH_16LSb_FS2g = 7, } lis2dtw12_ff_ths_t; -int32_t lis2dtw12_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_ff_threshold_set(const stmdev_ctx_t *ctx, lis2dtw12_ff_ths_t val); -int32_t lis2dtw12_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_ff_threshold_get(const stmdev_ctx_t *ctx, lis2dtw12_ff_ths_t *val); -int32_t lis2dtw12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dtw12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dtw12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dtw12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -1064,17 +1062,17 @@ typedef enum LIS2DTW12_BYPASS_TO_STREAM_MODE = 4, LIS2DTW12_STREAM_MODE = 6, } lis2dtw12_fmode_t; -int32_t lis2dtw12_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dtw12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2dtw12_fmode_t val); -int32_t lis2dtw12_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2dtw12_fmode_t *val); -int32_t lis2dtw12_fifo_data_level_get(stmdev_ctx_t *ctx, +int32_t lis2dtw12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dtw12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dtw12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dtw12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dtw12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); /** * @} diff --git a/sensor/stmemsc/lis2du12_STdC/driver/lis2du12_reg.c b/sensor/stmemsc/lis2du12_STdC/driver/lis2du12_reg.c index 89e298b0..5062b5eb 100644 --- a/sensor/stmemsc/lis2du12_STdC/driver/lis2du12_reg.c +++ b/sensor/stmemsc/lis2du12_STdC/driver/lis2du12_reg.c @@ -46,11 +46,18 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis2du12_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data, +int32_t __weak lis2du12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); + return ret; } @@ -64,11 +71,18 @@ int32_t __weak lis2du12_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis2du12_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data, +int32_t __weak lis2du12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); + return ret; } @@ -86,7 +100,8 @@ int32_t __weak lis2du12_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data, static void bytecpy(uint8_t *target, uint8_t *source) { - if ( (target != NULL) && (source != NULL) ) { + if ((target != NULL) && (source != NULL)) + { *target = *source; } } @@ -149,12 +164,12 @@ float_t lis2du12_from_lsb_to_celsius(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_id_get(stmdev_ctx_t *ctx, lis2du12_id_t *val) +int32_t lis2du12_id_get(const stmdev_ctx_t *ctx, lis2du12_id_t *val) { uint8_t reg; int32_t ret; - ret = lis2du12_read_reg(ctx, LIS2DU12_WHO_AM_I,®, 1); + ret = lis2du12_read_reg(ctx, LIS2DU12_WHO_AM_I, ®, 1); val->whoami = reg; return ret; @@ -168,24 +183,27 @@ int32_t lis2du12_id_get(stmdev_ctx_t *ctx, lis2du12_id_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_bus_mode_set(stmdev_ctx_t *ctx, lis2du12_bus_mode_t val) +int32_t lis2du12_bus_mode_set(const stmdev_ctx_t *ctx, lis2du12_bus_mode_t val) { lis2du12_if_ctrl_t if_ctrl; lis2du12_ctrl1_t ctrl1; int32_t ret; - ret = lis2du12_read_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t*)&if_ctrl, 1); - if (ret == 0) { + ret = lis2du12_read_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t *)&if_ctrl, 1); + if (ret == 0) + { if_ctrl.i3c_disable = (uint8_t)val & 0x01U; if_ctrl.i2c_disable = ((uint8_t)val & 0x02U) >> 1; - ret = lis2du12_write_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t*)&if_ctrl, 1); + ret = lis2du12_write_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t *)&if_ctrl, 1); } - if (ret == 0) { - ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + if (ret == 0) + { + ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); } - if (ret == 0) { + if (ret == 0) + { ctrl1.sim = ((uint8_t)val & 0x04U) >> 2; - ret = lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + ret = lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); } return ret; @@ -200,18 +218,20 @@ int32_t lis2du12_bus_mode_set(stmdev_ctx_t *ctx, lis2du12_bus_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_bus_mode_get(stmdev_ctx_t *ctx, lis2du12_bus_mode_t *val) +int32_t lis2du12_bus_mode_get(const stmdev_ctx_t *ctx, lis2du12_bus_mode_t *val) { lis2du12_if_ctrl_t if_ctrl; lis2du12_ctrl1_t ctrl1; int32_t ret; - ret = lis2du12_read_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t*)&if_ctrl, 1); - if (ret == 0) { - ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + ret = lis2du12_read_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t *)&if_ctrl, 1); + if (ret == 0) + { + ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); } - switch ( (ctrl1.sim << 2) | (if_ctrl.i2c_disable) << 1 | - (if_ctrl.i3c_disable) ) { + switch ((ctrl1.sim << 2) | (if_ctrl.i2c_disable) << 1 | + (if_ctrl.i3c_disable)) + { case LIS2DU12_SEL_BY_HW: *val = LIS2DU12_SEL_BY_HW; break; @@ -234,33 +254,34 @@ int32_t lis2du12_bus_mode_get(stmdev_ctx_t *ctx, lis2du12_bus_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_init_set(stmdev_ctx_t *ctx, lis2du12_init_t val) +int32_t lis2du12_init_set(const stmdev_ctx_t *ctx, lis2du12_init_t val) { lis2du12_ctrl1_t ctrl1; lis2du12_ctrl4_t ctrl4; int32_t ret; - ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); - ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL4, (uint8_t*)&ctrl4, 1); - switch ( val ) { + ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1); + switch (val) + { case LIS2DU12_BOOT: ctrl4.boot = PROPERTY_ENABLE; - ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL4, (uint8_t*)&ctrl4, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1); break; case LIS2DU12_RESET: ctrl1.sw_reset = PROPERTY_ENABLE; - ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); break; case LIS2DU12_DRV_RDY: ctrl4.bdu = PROPERTY_ENABLE; ctrl1.if_add_inc = PROPERTY_ENABLE; - ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL4, (uint8_t*)&ctrl4, 1); - ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); break; default: ctrl1.sw_reset = PROPERTY_ENABLE; - ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); break; } @@ -275,7 +296,7 @@ int32_t lis2du12_init_set(stmdev_ctx_t *ctx, lis2du12_init_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_status_get(stmdev_ctx_t *ctx, lis2du12_status_t *val) +int32_t lis2du12_status_get(const stmdev_ctx_t *ctx, lis2du12_status_t *val) { lis2du12_status_register_t status_register; lis2du12_ctrl1_t ctrl1; @@ -283,12 +304,14 @@ int32_t lis2du12_status_get(stmdev_ctx_t *ctx, lis2du12_status_t *val) int32_t ret; ret = lis2du12_read_reg(ctx, LIS2DU12_STATUS, - (uint8_t*)&status_register, 1); - if (ret == 0) { - ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + (uint8_t *)&status_register, 1); + if (ret == 0) + { + ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); } - if (ret == 0) { - ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL4, (uint8_t*)&ctrl4, 1); + if (ret == 0) + { + ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1); } val->sw_reset = ctrl1.sw_reset; @@ -307,7 +330,7 @@ int32_t lis2du12_status_get(stmdev_ctx_t *ctx, lis2du12_status_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_pin_conf_set(stmdev_ctx_t *ctx, lis2du12_pin_conf_t *val) +int32_t lis2du12_pin_conf_set(const stmdev_ctx_t *ctx, lis2du12_pin_conf_t *val) { lis2du12_if_pu_ctrl_t if_pu_ctrl; lis2du12_md2_cfg_t md2_cfg; @@ -315,34 +338,41 @@ int32_t lis2du12_pin_conf_set(stmdev_ctx_t *ctx, lis2du12_pin_conf_t *val) lis2du12_ctrl1_t ctrl1; int32_t ret; - ret = lis2du12_read_reg(ctx, LIS2DU12_IF_PU_CTRL, (uint8_t*)&if_pu_ctrl, 1); - if (ret == 0) { - ret = lis2du12_read_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t*)&if_ctrl, 1); + ret = lis2du12_read_reg(ctx, LIS2DU12_IF_PU_CTRL, (uint8_t *)&if_pu_ctrl, 1); + if (ret == 0) + { + ret = lis2du12_read_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t *)&if_ctrl, 1); } - if (ret == 0) { - ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + if (ret == 0) + { + ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); } - if (ret == 0) { - ret = lis2du12_read_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t*)&md2_cfg, 1); + if (ret == 0) + { + ret = lis2du12_read_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t *)&md2_cfg, 1); } - if (ret == 0) { + if (ret == 0) + { if_pu_ctrl.sdo_pu_disc = ~val->sdo_pull_up; if_pu_ctrl.sda_pu_en = val->sda_pull_up; if_pu_ctrl.cs_pu_disc = ~val->cs_pull_up; - ret = lis2du12_write_reg(ctx, LIS2DU12_IF_PU_CTRL, (uint8_t*)&if_pu_ctrl, 1); + ret = lis2du12_write_reg(ctx, LIS2DU12_IF_PU_CTRL, (uint8_t *)&if_pu_ctrl, 1); } - if (ret == 0) { + if (ret == 0) + { if_ctrl.pd_dis_int1 = val->int1_pull_down; - ret = lis2du12_write_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t*)&if_ctrl, 1); + ret = lis2du12_write_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t *)&if_ctrl, 1); } - if (ret == 0) { + if (ret == 0) + { ctrl1.pp_od = val->int1_int2_push_pull; - ret = lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + ret = lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); } - if (ret == 0) { + if (ret == 0) + { md2_cfg.pd_dis_int2 = val->int2_pull_down; - ret = lis2du12_write_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t*)&md2_cfg, 1); + ret = lis2du12_write_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t *)&md2_cfg, 1); } return ret; @@ -356,7 +386,7 @@ int32_t lis2du12_pin_conf_set(stmdev_ctx_t *ctx, lis2du12_pin_conf_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_pin_conf_get(stmdev_ctx_t *ctx, lis2du12_pin_conf_t *val) +int32_t lis2du12_pin_conf_get(const stmdev_ctx_t *ctx, lis2du12_pin_conf_t *val) { lis2du12_if_pu_ctrl_t if_pu_ctrl; lis2du12_md2_cfg_t md2_cfg; @@ -364,15 +394,18 @@ int32_t lis2du12_pin_conf_get(stmdev_ctx_t *ctx, lis2du12_pin_conf_t *val) lis2du12_ctrl1_t ctrl1; int32_t ret; - ret = lis2du12_read_reg(ctx, LIS2DU12_IF_PU_CTRL, (uint8_t*)&if_pu_ctrl, 1); - if (ret == 0) { - ret = lis2du12_read_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t*)&if_ctrl, 1); + ret = lis2du12_read_reg(ctx, LIS2DU12_IF_PU_CTRL, (uint8_t *)&if_pu_ctrl, 1); + if (ret == 0) + { + ret = lis2du12_read_reg(ctx, LIS2DU12_IF_CTRL, (uint8_t *)&if_ctrl, 1); } - if (ret == 0) { - ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + if (ret == 0) + { + ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); } - if (ret == 0) { - ret = lis2du12_read_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t*)&md2_cfg, 1); + if (ret == 0) + { + ret = lis2du12_read_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t *)&md2_cfg, 1); } val->sdo_pull_up = ~if_pu_ctrl.sdo_pu_disc; val->sda_pull_up = if_pu_ctrl.sda_pu_en; @@ -392,13 +425,13 @@ int32_t lis2du12_pin_conf_get(stmdev_ctx_t *ctx, lis2du12_pin_conf_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_all_sources_get(stmdev_ctx_t *ctx, +int32_t lis2du12_all_sources_get(const stmdev_ctx_t *ctx, lis2du12_all_sources_t *val) { lis2du12_all_int_src_t all_int_src; int32_t ret; - ret = lis2du12_read_reg(ctx, LIS2DU12_ALL_INT_SRC, (uint8_t*)&all_int_src, 1); + ret = lis2du12_read_reg(ctx, LIS2DU12_ALL_INT_SRC, (uint8_t *)&all_int_src, 1); if (ret == 0 && all_int_src.int_global == 1U) { val->free_fall = all_int_src.ff_ia_all; @@ -412,7 +445,7 @@ int32_t lis2du12_all_sources_get(stmdev_ctx_t *ctx, { lis2du12_sixd_src_t sixd_src; - ret = lis2du12_read_reg(ctx, LIS2DU12_SIXD_SRC, (uint8_t*)&sixd_src, 1); + ret = lis2du12_read_reg(ctx, LIS2DU12_SIXD_SRC, (uint8_t *)&sixd_src, 1); val->six_d_xl = sixd_src.xl; val->six_d_xh = sixd_src.xh; @@ -426,7 +459,7 @@ int32_t lis2du12_all_sources_get(stmdev_ctx_t *ctx, { lis2du12_wake_up_src_t wu_src; - ret = lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_SRC, (uint8_t*)&wu_src, 1); + ret = lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_SRC, (uint8_t *)&wu_src, 1); val->wake_up_z = wu_src.z_wu; val->wake_up_y = wu_src.y_wu; @@ -438,7 +471,7 @@ int32_t lis2du12_all_sources_get(stmdev_ctx_t *ctx, { lis2du12_tap_src_t tap_src; - ret = lis2du12_read_reg(ctx, LIS2DU12_TAP_SRC, (uint8_t*)&tap_src, 1); + ret = lis2du12_read_reg(ctx, LIS2DU12_TAP_SRC, (uint8_t *)&tap_src, 1); val->tap_z = tap_src.z_tap; val->tap_y = tap_src.y_tap; @@ -458,18 +491,18 @@ int32_t lis2du12_all_sources_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_mode_set(stmdev_ctx_t *ctx, lis2du12_md_t *val) +int32_t lis2du12_mode_set(const stmdev_ctx_t *ctx, lis2du12_md_t *val) { lis2du12_ctrl5_t ctrl5; int32_t ret; - ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL5, (uint8_t*)&ctrl5, 1); + ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL5, (uint8_t *)&ctrl5, 1); ctrl5.odr = (uint8_t)val->odr; ctrl5.fs = (uint8_t)val->fs; ctrl5.bw = (uint8_t)val->bw; - ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL5, (uint8_t*)&ctrl5, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL5, (uint8_t *)&ctrl5, 1); return ret; } @@ -482,14 +515,15 @@ int32_t lis2du12_mode_set(stmdev_ctx_t *ctx, lis2du12_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_mode_get(stmdev_ctx_t *ctx, lis2du12_md_t *val) +int32_t lis2du12_mode_get(const stmdev_ctx_t *ctx, lis2du12_md_t *val) { lis2du12_ctrl5_t ctrl5; int32_t ret; - ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL5, (uint8_t*)&ctrl5, 1); + ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL5, (uint8_t *)&ctrl5, 1); - switch (ctrl5.odr) { + switch (ctrl5.odr) + { case LIS2DU12_OFF: val->odr = LIS2DU12_OFF; break; @@ -537,7 +571,8 @@ int32_t lis2du12_mode_get(stmdev_ctx_t *ctx, lis2du12_md_t *val) break; } - switch (ctrl5.fs) { + switch (ctrl5.fs) + { case LIS2DU12_2g: val->fs = LIS2DU12_2g; break; @@ -555,7 +590,8 @@ int32_t lis2du12_mode_get(stmdev_ctx_t *ctx, lis2du12_md_t *val) break; } - switch (ctrl5.bw) { + switch (ctrl5.bw) + { case LIS2DU12_ODR_div_2: val->bw = LIS2DU12_ODR_div_2; break; @@ -584,15 +620,16 @@ int32_t lis2du12_mode_get(stmdev_ctx_t *ctx, lis2du12_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_trigger_sw(stmdev_ctx_t *ctx, lis2du12_md_t *md) +int32_t lis2du12_trigger_sw(const stmdev_ctx_t *ctx, lis2du12_md_t *md) { lis2du12_ctrl4_t ctrl4; int32_t ret = 0; - if ( md->odr == LIS2DU12_TRIG_SW ) { - ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL4, (uint8_t*)&ctrl4, 1); + if (md->odr == LIS2DU12_TRIG_SW) + { + ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1); ctrl4.soc = PROPERTY_ENABLE; - ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL4, (uint8_t*)&ctrl4, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1); } return ret; } @@ -606,7 +643,7 @@ int32_t lis2du12_trigger_sw(stmdev_ctx_t *ctx, lis2du12_md_t *md) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_data_get(stmdev_ctx_t *ctx, lis2du12_md_t *md, +int32_t lis2du12_data_get(const stmdev_ctx_t *ctx, lis2du12_md_t *md, lis2du12_data_t *data) { uint8_t buff[8]; @@ -614,26 +651,28 @@ int32_t lis2du12_data_get(stmdev_ctx_t *ctx, lis2du12_md_t *md, uint8_t i; uint8_t j; - ret = lis2du12_read_reg(ctx, LIS2DU12_OUTX_L, (uint8_t*)&buff, 8); + ret = lis2du12_read_reg(ctx, LIS2DU12_OUTX_L, (uint8_t *)&buff, 8); /* acceleration conversion */ j = 0U; - for (i = 0U; i < 3U; i++) { - data->xl.raw[i] = (int16_t)buff[j+1U]; + for (i = 0U; i < 3U; i++) + { + data->xl.raw[i] = (int16_t)buff[j + 1U]; data->xl.raw[i] = (data->xl.raw[i] * 256) + (int16_t) buff[j]; - j+=2U; - switch ( md->fs ) { + j += 2U; + switch (md->fs) + { case LIS2DU12_2g: - data->xl.mg[i] =lis2du12_from_fs2g_to_mg(data->xl.raw[i]); + data->xl.mg[i] = lis2du12_from_fs2g_to_mg(data->xl.raw[i]); break; case LIS2DU12_4g: - data->xl.mg[i] =lis2du12_from_fs4g_to_mg(data->xl.raw[i]); + data->xl.mg[i] = lis2du12_from_fs4g_to_mg(data->xl.raw[i]); break; case LIS2DU12_8g: - data->xl.mg[i] =lis2du12_from_fs8g_to_mg(data->xl.raw[i]); + data->xl.mg[i] = lis2du12_from_fs8g_to_mg(data->xl.raw[i]); break; case LIS2DU12_16g: - data->xl.mg[i] =lis2du12_from_fs16g_to_mg(data->xl.raw[i]); + data->xl.mg[i] = lis2du12_from_fs16g_to_mg(data->xl.raw[i]); break; default: data->xl.mg[i] = 0.0f; @@ -641,7 +680,7 @@ int32_t lis2du12_data_get(stmdev_ctx_t *ctx, lis2du12_md_t *md, } } - data->heat.raw = (int16_t)buff[j+1U]; + data->heat.raw = (int16_t)buff[j + 1U]; data->heat.raw = (data->heat.raw * 256) + (int16_t) buff[j]; /* temperature conversion */ data->heat.deg_c = lis2du12_from_lsb_to_celsius(data->heat.raw); @@ -657,15 +696,16 @@ int32_t lis2du12_data_get(stmdev_ctx_t *ctx, lis2du12_md_t *md, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_self_test_sign_set(stmdev_ctx_t *ctx, lis2du12_st_t val) +int32_t lis2du12_self_test_sign_set(const stmdev_ctx_t *ctx, lis2du12_st_t val) { lis2du12_st_sign_t st_sign; int32_t ret; - ret = lis2du12_read_reg(ctx, LIS2DU12_ST_SIGN, (uint8_t*)&st_sign, 1); - if (ret == 0) { + ret = lis2du12_read_reg(ctx, LIS2DU12_ST_SIGN, (uint8_t *)&st_sign, 1); + if (ret == 0) + { st_sign.stsign = (uint8_t) val; - ret = lis2du12_write_reg(ctx, LIS2DU12_ST_SIGN, (uint8_t*)&st_sign, 1); + ret = lis2du12_write_reg(ctx, LIS2DU12_ST_SIGN, (uint8_t *)&st_sign, 1); } return ret; } @@ -678,18 +718,19 @@ int32_t lis2du12_self_test_sign_set(stmdev_ctx_t *ctx, lis2du12_st_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_self_test_start(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2du12_self_test_start(const stmdev_ctx_t *ctx, uint8_t val) { lis2du12_ctrl3_t ctrl3; int32_t ret; - if (val != 1U && val != 2U) { + if (val != 1U && val != 2U) + { return -1; } - ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL3, (uint8_t*)&ctrl3, 1); + ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL3, (uint8_t *)&ctrl3, 1); ctrl3.st = (uint8_t) val; - ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL3, (uint8_t*)&ctrl3, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL3, (uint8_t *)&ctrl3, 1); return ret; } @@ -702,14 +743,14 @@ int32_t lis2du12_self_test_start(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_self_test_stop(stmdev_ctx_t *ctx) +int32_t lis2du12_self_test_stop(const stmdev_ctx_t *ctx) { lis2du12_ctrl3_t ctrl3; int32_t ret; - ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL3, (uint8_t*)&ctrl3, 1); + ret = lis2du12_read_reg(ctx, LIS2DU12_CTRL3, (uint8_t *)&ctrl3, 1); ctrl3.st = 0; - ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL3, (uint8_t*)&ctrl3, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL3, (uint8_t *)&ctrl3, 1); return ret; } @@ -735,7 +776,7 @@ int32_t lis2du12_self_test_stop(stmdev_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_fifo_mode_set(stmdev_ctx_t *ctx, lis2du12_fifo_md_t *val) +int32_t lis2du12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2du12_fifo_md_t *val) { lis2du12_fifo_ctrl_t fifo_ctrl; lis2du12_fifo_wtm_t fifo_wtm; @@ -744,23 +785,25 @@ int32_t lis2du12_fifo_mode_set(stmdev_ctx_t *ctx, lis2du12_fifo_md_t *val) ret = lis2du12_read_reg(ctx, LIS2DU12_FIFO_CTRL, reg, 2); - bytecpy(( uint8_t*)&fifo_ctrl, ®[0]); - bytecpy(( uint8_t*)&fifo_wtm, ®[1]); + bytecpy((uint8_t *)&fifo_ctrl, ®[0]); + bytecpy((uint8_t *)&fifo_wtm, ®[1]); fifo_ctrl.f_mode = (uint8_t) val->operation; fifo_ctrl.fifo_depth = (uint8_t) val->store; - if (val->watermark != 0x00U) { + if (val->watermark != 0x00U) + { fifo_ctrl.stop_on_fth = PROPERTY_ENABLE; } - else { + else + { fifo_ctrl.stop_on_fth = PROPERTY_DISABLE; } fifo_wtm.fth = val->watermark; - bytecpy(®[0], ( uint8_t*)&fifo_ctrl); - bytecpy(®[1], ( uint8_t*)&fifo_wtm); + bytecpy(®[0], (uint8_t *)&fifo_ctrl); + bytecpy(®[1], (uint8_t *)&fifo_wtm); ret += lis2du12_write_reg(ctx, LIS2DU12_FIFO_CTRL, reg, 2); @@ -775,7 +818,7 @@ int32_t lis2du12_fifo_mode_set(stmdev_ctx_t *ctx, lis2du12_fifo_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_fifo_mode_get(stmdev_ctx_t *ctx, lis2du12_fifo_md_t *val) +int32_t lis2du12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2du12_fifo_md_t *val) { lis2du12_fifo_ctrl_t fifo_ctrl; lis2du12_fifo_wtm_t fifo_wtm; @@ -784,8 +827,8 @@ int32_t lis2du12_fifo_mode_get(stmdev_ctx_t *ctx, lis2du12_fifo_md_t *val) ret = lis2du12_read_reg(ctx, LIS2DU12_FIFO_CTRL, reg, 2); - bytecpy(( uint8_t*)&fifo_ctrl, ®[0]); - bytecpy(( uint8_t*)&fifo_wtm, ®[1]); + bytecpy((uint8_t *)&fifo_ctrl, ®[0]); + bytecpy((uint8_t *)&fifo_wtm, ®[1]); switch (fifo_ctrl.f_mode) { @@ -830,7 +873,7 @@ int32_t lis2du12_fifo_mode_get(stmdev_ctx_t *ctx, lis2du12_fifo_md_t *val) return ret; } -int32_t lis2du12_fifo_status_get(stmdev_ctx_t *ctx, lis2du12_fifo_status_t *val) +int32_t lis2du12_fifo_status_get(const stmdev_ctx_t *ctx, lis2du12_fifo_status_t *val) { lis2du12_fifo_status1_t fifo_status1; int32_t ret; @@ -852,14 +895,14 @@ int32_t lis2du12_fifo_status_get(stmdev_ctx_t *ctx, lis2du12_fifo_status_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_fifo_level_get(stmdev_ctx_t *ctx, lis2du12_fifo_md_t *md, +int32_t lis2du12_fifo_level_get(const stmdev_ctx_t *ctx, lis2du12_fifo_md_t *md, uint8_t *val) { lis2du12_fifo_status2_t fifo_status2; int32_t ret; ret = lis2du12_read_reg(ctx, LIS2DU12_FIFO_STATUS2, - (uint8_t*)&fifo_status2, 1); + (uint8_t *)&fifo_status2, 1); *val = fifo_status2.fss; @@ -876,7 +919,7 @@ int32_t lis2du12_fifo_level_get(stmdev_ctx_t *ctx, lis2du12_fifo_md_t *md, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_fifo_data_get(stmdev_ctx_t *ctx, lis2du12_md_t *md, +int32_t lis2du12_fifo_data_get(const stmdev_ctx_t *ctx, lis2du12_md_t *md, lis2du12_fifo_md_t *fmd, lis2du12_fifo_data_t *data) { @@ -886,40 +929,47 @@ int32_t lis2du12_fifo_data_get(stmdev_ctx_t *ctx, lis2du12_md_t *md, ret = lis2du12_read_reg(ctx, LIS2DU12_OUTX_L, fifo_data, 8); - if (fmd->store == LIS2DU12_8_BIT) { - for (i = 0; i < 3; i++) { - data->xl[0].raw[i] = (int16_t)fifo_data[2*i + 1]; - data->xl[0].raw[i] = data->xl[0].raw[i] * 256 + (int16_t)fifo_data[2*i]; + if (fmd->store == LIS2DU12_8_BIT) + { + for (i = 0; i < 3; i++) + { + data->xl[0].raw[i] = (int16_t)fifo_data[2 * i + 1]; + data->xl[0].raw[i] = data->xl[0].raw[i] * 256 + (int16_t)fifo_data[2 * i]; } data->heat.raw = (int16_t)fifo_data[7U]; data->heat.raw = (data->heat.raw * 256) + (int16_t) fifo_data[6U]; /* temperature conversion */ data->heat.deg_c = lis2du12_from_lsb_to_celsius(data->heat.raw); - } else { - for (i = 0; i < 3; i++) { + } + else + { + for (i = 0; i < 3; i++) + { data->xl[0].raw[i] = (int16_t)fifo_data[i] * 256; data->xl[1].raw[i] = (int16_t)fifo_data[3 + i] * 256; } } - for (i = 0; i < 3; i++) { - switch ( md->fs ) { + for (i = 0; i < 3; i++) + { + switch (md->fs) + { case LIS2DU12_2g: - data->xl[0].mg[i] =lis2du12_from_fs2g_to_mg(data->xl[0].raw[i]); - data->xl[1].mg[i] =lis2du12_from_fs2g_to_mg(data->xl[1].raw[i]); + data->xl[0].mg[i] = lis2du12_from_fs2g_to_mg(data->xl[0].raw[i]); + data->xl[1].mg[i] = lis2du12_from_fs2g_to_mg(data->xl[1].raw[i]); break; case LIS2DU12_4g: - data->xl[0].mg[i] =lis2du12_from_fs4g_to_mg(data->xl[0].raw[i]); - data->xl[1].mg[i] =lis2du12_from_fs4g_to_mg(data->xl[1].raw[i]); + data->xl[0].mg[i] = lis2du12_from_fs4g_to_mg(data->xl[0].raw[i]); + data->xl[1].mg[i] = lis2du12_from_fs4g_to_mg(data->xl[1].raw[i]); break; case LIS2DU12_8g: - data->xl[0].mg[i] =lis2du12_from_fs8g_to_mg(data->xl[0].raw[i]); - data->xl[1].mg[i] =lis2du12_from_fs8g_to_mg(data->xl[1].raw[i]); + data->xl[0].mg[i] = lis2du12_from_fs8g_to_mg(data->xl[0].raw[i]); + data->xl[1].mg[i] = lis2du12_from_fs8g_to_mg(data->xl[1].raw[i]); break; case LIS2DU12_16g: - data->xl[0].mg[i] =lis2du12_from_fs16g_to_mg(data->xl[0].raw[i]); - data->xl[1].mg[i] =lis2du12_from_fs16g_to_mg(data->xl[1].raw[i]); + data->xl[0].mg[i] = lis2du12_from_fs16g_to_mg(data->xl[0].raw[i]); + data->xl[1].mg[i] = lis2du12_from_fs16g_to_mg(data->xl[1].raw[i]); break; default: data->xl[0].mg[i] = 0.0f; @@ -952,7 +1002,7 @@ int32_t lis2du12_fifo_data_get(stmdev_ctx_t *ctx, lis2du12_md_t *md, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_interrupt_mode_set(stmdev_ctx_t *ctx, +int32_t lis2du12_interrupt_mode_set(const stmdev_ctx_t *ctx, lis2du12_int_mode_t *val) { lis2du12_interrupt_cfg_t interrupt_cfg; @@ -960,8 +1010,8 @@ int32_t lis2du12_interrupt_mode_set(stmdev_ctx_t *ctx, int32_t ret; ret = lis2du12_read_reg(ctx, LIS2DU12_INTERRUPT_CFG, - (uint8_t*)&interrupt_cfg, 1); - ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + (uint8_t *)&interrupt_cfg, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); interrupt_cfg.int_short_en = (uint8_t)val->base_sig & 0x01U; interrupt_cfg.lir = ((uint8_t)val->base_sig & 0x02U) >> 1 ; @@ -972,8 +1022,8 @@ int32_t lis2du12_interrupt_mode_set(stmdev_ctx_t *ctx, interrupt_cfg.interrupts_enable = val->enable; ret += lis2du12_write_reg(ctx, LIS2DU12_INTERRUPT_CFG, - (uint8_t*)&interrupt_cfg, 1); - ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + (uint8_t *)&interrupt_cfg, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); return ret; } @@ -986,7 +1036,7 @@ int32_t lis2du12_interrupt_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_interrupt_mode_get(stmdev_ctx_t *ctx, +int32_t lis2du12_interrupt_mode_get(const stmdev_ctx_t *ctx, lis2du12_int_mode_t *val) { lis2du12_interrupt_cfg_t interrupt_cfg; @@ -994,14 +1044,15 @@ int32_t lis2du12_interrupt_mode_get(stmdev_ctx_t *ctx, int32_t ret; ret = lis2du12_read_reg(ctx, LIS2DU12_INTERRUPT_CFG, - (uint8_t*)&interrupt_cfg, 1); - ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + (uint8_t *)&interrupt_cfg, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); val->active_low = interrupt_cfg.h_lactive; val->drdy_latched = ~ctrl1.drdy_pulsed; val->enable = interrupt_cfg.interrupts_enable; - switch ( (interrupt_cfg.lir << 1) | interrupt_cfg.int_short_en ) { + switch ((interrupt_cfg.lir << 1) | interrupt_cfg.int_short_en) + { case LIS2DU12_INT_LEVEL: val->base_sig = LIS2DU12_INT_LEVEL; break; @@ -1023,7 +1074,7 @@ int32_t lis2du12_interrupt_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lis2du12_pin_int1_route_set(const stmdev_ctx_t *ctx, lis2du12_pin_int_route_t *val) { lis2du12_interrupt_cfg_t interrupt_cfg; @@ -1032,9 +1083,9 @@ int32_t lis2du12_pin_int1_route_set(stmdev_ctx_t *ctx, int32_t ret; ret = lis2du12_read_reg(ctx, LIS2DU12_INTERRUPT_CFG, - (uint8_t*)&interrupt_cfg, 1); - ret += lis2du12_read_reg(ctx, LIS2DU12_MD1_CFG, (uint8_t*)&md1_cfg, 1); - ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL2, (uint8_t*)&ctrl2, 1); + (uint8_t *)&interrupt_cfg, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_MD1_CFG, (uint8_t *)&md1_cfg, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL2, (uint8_t *)&ctrl2, 1); ctrl2.int1_boot = val->boot; ctrl2.int1_drdy = val->drdy_xl; @@ -1048,19 +1099,21 @@ int32_t lis2du12_pin_int1_route_set(stmdev_ctx_t *ctx, md1_cfg.int1_ff = val->free_fall; md1_cfg.int1_single_tap = val->single_tap; - if ( val->sleep_state == 1U) { + if (val->sleep_state == 1U) + { interrupt_cfg.sleep_status_on_int = PROPERTY_ENABLE; md1_cfg.int1_sleep_change = PROPERTY_ENABLE; } - if ( val->sleep_change == 1U) { + if (val->sleep_change == 1U) + { interrupt_cfg.sleep_status_on_int = PROPERTY_DISABLE; md1_cfg.int1_sleep_change = PROPERTY_ENABLE; } ret += lis2du12_write_reg(ctx, LIS2DU12_INTERRUPT_CFG, - (uint8_t*)&interrupt_cfg, 1); - ret += lis2du12_write_reg(ctx, LIS2DU12_MD1_CFG, (uint8_t*)&md1_cfg, 1); - ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL2, (uint8_t*)&ctrl2, 1); + (uint8_t *)&interrupt_cfg, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_MD1_CFG, (uint8_t *)&md1_cfg, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL2, (uint8_t *)&ctrl2, 1); return ret; } @@ -1073,7 +1126,7 @@ int32_t lis2du12_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lis2du12_pin_int1_route_get(const stmdev_ctx_t *ctx, lis2du12_pin_int_route_t *val) { lis2du12_interrupt_cfg_t interrupt_cfg; @@ -1082,9 +1135,9 @@ int32_t lis2du12_pin_int1_route_get(stmdev_ctx_t *ctx, int32_t ret; ret = lis2du12_read_reg(ctx, LIS2DU12_INTERRUPT_CFG, - (uint8_t*)&interrupt_cfg, 1); - ret += lis2du12_read_reg(ctx, LIS2DU12_MD1_CFG, (uint8_t*)&md1_cfg, 1); - ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL2, (uint8_t*)&ctrl2, 1); + (uint8_t *)&interrupt_cfg, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_MD1_CFG, (uint8_t *)&md1_cfg, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL2, (uint8_t *)&ctrl2, 1); val->boot = ctrl2.int1_boot; val->drdy_xl = ctrl2.int1_drdy; @@ -1100,10 +1153,12 @@ int32_t lis2du12_pin_int1_route_get(stmdev_ctx_t *ctx, val->sleep_state = interrupt_cfg.sleep_status_on_int; - if (val->sleep_state == PROPERTY_DISABLE) { + if (val->sleep_state == PROPERTY_DISABLE) + { val->sleep_change = md1_cfg.int1_sleep_change; } - else { + else + { val->sleep_change = PROPERTY_DISABLE; } @@ -1118,7 +1173,7 @@ int32_t lis2du12_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lis2du12_pin_int2_route_set(const stmdev_ctx_t *ctx, lis2du12_pin_int_route_t *val) { lis2du12_interrupt_cfg_t interrupt_cfg; @@ -1127,9 +1182,9 @@ int32_t lis2du12_pin_int2_route_set(stmdev_ctx_t *ctx, int32_t ret; ret = lis2du12_read_reg(ctx, LIS2DU12_INTERRUPT_CFG, - (uint8_t*)&interrupt_cfg, 1); - ret += lis2du12_read_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t*)&md2_cfg, 1); - ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL3, (uint8_t*)&ctrl3, 1); + (uint8_t *)&interrupt_cfg, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t *)&md2_cfg, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL3, (uint8_t *)&ctrl3, 1); ctrl3.int2_boot = val->boot; ctrl3.int2_drdy = val->drdy_xl; @@ -1143,19 +1198,21 @@ int32_t lis2du12_pin_int2_route_set(stmdev_ctx_t *ctx, md2_cfg.int2_ff = val->free_fall; md2_cfg.int2_single_tap = val->single_tap; - if ( val->sleep_state == 1U) { + if (val->sleep_state == 1U) + { interrupt_cfg.sleep_status_on_int = PROPERTY_ENABLE; md2_cfg.int2_sleep_change = PROPERTY_ENABLE; } - if ( val->sleep_change == 1U) { + if (val->sleep_change == 1U) + { interrupt_cfg.sleep_status_on_int = PROPERTY_DISABLE; md2_cfg.int2_sleep_change = PROPERTY_ENABLE; } ret += lis2du12_write_reg(ctx, LIS2DU12_INTERRUPT_CFG, - (uint8_t*)&interrupt_cfg, 1); - ret += lis2du12_write_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t*)&md2_cfg, 1); - ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL3, (uint8_t*)&ctrl3, 1); + (uint8_t *)&interrupt_cfg, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t *)&md2_cfg, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL3, (uint8_t *)&ctrl3, 1); return ret; } @@ -1168,7 +1225,7 @@ int32_t lis2du12_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lis2du12_pin_int2_route_get(const stmdev_ctx_t *ctx, lis2du12_pin_int_route_t *val) { lis2du12_interrupt_cfg_t interrupt_cfg; @@ -1177,9 +1234,9 @@ int32_t lis2du12_pin_int2_route_get(stmdev_ctx_t *ctx, int32_t ret; ret = lis2du12_read_reg(ctx, LIS2DU12_INTERRUPT_CFG, - (uint8_t*)&interrupt_cfg, 1); - ret += lis2du12_read_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t*)&md2_cfg, 1); - ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL3, (uint8_t*)&ctrl3, 1); + (uint8_t *)&interrupt_cfg, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_MD2_CFG, (uint8_t *)&md2_cfg, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL3, (uint8_t *)&ctrl3, 1); val->boot = ctrl3.int2_boot; val->drdy_xl = ctrl3.int2_drdy; @@ -1195,10 +1252,12 @@ int32_t lis2du12_pin_int2_route_get(stmdev_ctx_t *ctx, val->sleep_state = interrupt_cfg.sleep_status_on_int; - if (val->sleep_state == PROPERTY_DISABLE) { + if (val->sleep_state == PROPERTY_DISABLE) + { val->sleep_change = md2_cfg.int2_sleep_change; } - else { + else + { val->sleep_change = PROPERTY_DISABLE; } @@ -1226,7 +1285,7 @@ int32_t lis2du12_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_wake_up_mode_set(stmdev_ctx_t *ctx, lis2du12_wkup_md_t *val) +int32_t lis2du12_wake_up_mode_set(const stmdev_ctx_t *ctx, lis2du12_wkup_md_t *val) { lis2du12_interrupt_cfg_t interrupt_cfg; lis2du12_wake_up_ths_t wake_up_ths; @@ -1237,33 +1296,37 @@ int32_t lis2du12_wake_up_mode_set(stmdev_ctx_t *ctx, lis2du12_wkup_md_t *val) int32_t ret; ret = lis2du12_read_reg(ctx, LIS2DU12_INTERRUPT_CFG, - (uint8_t*)&interrupt_cfg, 1); + (uint8_t *)&interrupt_cfg, 1); ret += lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_THS, - (uint8_t*)&wake_up_ths, 1); + (uint8_t *)&wake_up_ths, 1); ret += lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_DUR, - (uint8_t*)&wake_up_dur, 1); - ret += lis2du12_read_reg(ctx, LIS2DU12_MD1_CFG, (uint8_t*)&md1_cfg, 1); - ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); - ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL4, (uint8_t*)&ctrl4, 1); + (uint8_t *)&wake_up_dur, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_MD1_CFG, (uint8_t *)&md1_cfg, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1); ctrl1.wu_z_en = val->z_en; ctrl1.wu_y_en = val->y_en; ctrl1.wu_x_en = val->x_en; - if (val->threshold > 63U) { + if (val->threshold > 63U) + { interrupt_cfg.wake_ths_w = PROPERTY_ENABLE; wake_up_ths.wk_ths = val->threshold / 4U; } - else { + else + { interrupt_cfg.wake_ths_w = PROPERTY_DISABLE; wake_up_ths.wk_ths = val->threshold; } - if (val->duration > 3U) { + if (val->duration > 3U) + { md1_cfg.wu_dur_x4 = PROPERTY_ENABLE; wake_up_dur.wake_dur = val->duration / 4U; } - else { + else + { md1_cfg.wu_dur_x4 = PROPERTY_DISABLE; wake_up_dur.wake_dur = val->duration; } @@ -1273,13 +1336,13 @@ int32_t lis2du12_wake_up_mode_set(stmdev_ctx_t *ctx, lis2du12_wkup_md_t *val) wake_up_dur.sleep_dur = val->sleep.duration; ret += lis2du12_write_reg(ctx, LIS2DU12_INTERRUPT_CFG, - (uint8_t*)&interrupt_cfg, 1); + (uint8_t *)&interrupt_cfg, 1); ret += lis2du12_write_reg(ctx, LIS2DU12_WAKE_UP_THS, - (uint8_t*)&wake_up_ths, 1); + (uint8_t *)&wake_up_ths, 1); ret += lis2du12_write_reg(ctx, LIS2DU12_WAKE_UP_DUR, - (uint8_t*)&wake_up_dur, 1); - ret += lis2du12_write_reg(ctx, LIS2DU12_MD1_CFG, (uint8_t*)&md1_cfg, 1); - ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); + (uint8_t *)&wake_up_dur, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_MD1_CFG, (uint8_t *)&md1_cfg, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); ret += lis2du12_write_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1); return ret; @@ -1293,7 +1356,7 @@ int32_t lis2du12_wake_up_mode_set(stmdev_ctx_t *ctx, lis2du12_wkup_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_wake_up_mode_get(stmdev_ctx_t *ctx, lis2du12_wkup_md_t *val) +int32_t lis2du12_wake_up_mode_get(const stmdev_ctx_t *ctx, lis2du12_wkup_md_t *val) { lis2du12_interrupt_cfg_t interrupt_cfg; lis2du12_wake_up_ths_t wake_up_ths; @@ -1304,37 +1367,42 @@ int32_t lis2du12_wake_up_mode_get(stmdev_ctx_t *ctx, lis2du12_wkup_md_t *val) int32_t ret; ret = lis2du12_read_reg(ctx, LIS2DU12_INTERRUPT_CFG, - (uint8_t*)&interrupt_cfg, 1); + (uint8_t *)&interrupt_cfg, 1); ret += lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_THS, - (uint8_t*)&wake_up_ths, 1); + (uint8_t *)&wake_up_ths, 1); ret += lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_DUR, - (uint8_t*)&wake_up_dur, 1); - ret += lis2du12_read_reg(ctx, LIS2DU12_MD1_CFG, (uint8_t*)&md1_cfg, 1); - ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t*)&ctrl1, 1); - ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL4, (uint8_t*)&ctrl4, 1); + (uint8_t *)&wake_up_dur, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_MD1_CFG, (uint8_t *)&md1_cfg, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL1, (uint8_t *)&ctrl1, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_CTRL4, (uint8_t *)&ctrl4, 1); val->z_en = ctrl1.wu_z_en; val->y_en = ctrl1.wu_y_en; val->x_en = ctrl1.wu_x_en; - if (interrupt_cfg.wake_ths_w == PROPERTY_ENABLE) { + if (interrupt_cfg.wake_ths_w == PROPERTY_ENABLE) + { val->threshold = wake_up_ths.wk_ths * 4U; } - else { + else + { val->threshold = wake_up_ths.wk_ths; } - if (md1_cfg.wu_dur_x4 == PROPERTY_ENABLE) { + if (md1_cfg.wu_dur_x4 == PROPERTY_ENABLE) + { val->duration = wake_up_dur.wake_dur * 4U; } - else { + else + { val->duration = wake_up_dur.wake_dur; } val->sleep.en = wake_up_ths.sleep_on; val->sleep.duration = wake_up_dur.sleep_dur; - switch ( ctrl4.inact_odr ) { + switch (ctrl4.inact_odr) + { case LIS2DU12_DO_NOT_CHANGE: val->sleep.odr = LIS2DU12_DO_NOT_CHANGE; break; @@ -1375,7 +1443,7 @@ int32_t lis2du12_wake_up_mode_get(stmdev_ctx_t *ctx, lis2du12_wkup_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_tap_mode_set(stmdev_ctx_t *ctx, lis2du12_tap_md_t *val) +int32_t lis2du12_tap_mode_set(const stmdev_ctx_t *ctx, lis2du12_tap_md_t *val) { lis2du12_wake_up_ths_t wake_up_ths; lis2du12_tap_ths_x_t tap_ths_x; @@ -1385,12 +1453,12 @@ int32_t lis2du12_tap_mode_set(stmdev_ctx_t *ctx, lis2du12_tap_md_t *val) int32_t ret; ret = lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_THS, - (uint8_t*)&wake_up_ths, 1); + (uint8_t *)&wake_up_ths, 1); ret += lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_X, - (uint8_t*)&tap_ths_x, 1); - ret += lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_Y, (uint8_t*)&tap_ths_y, 1); - ret += lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_Z, (uint8_t*)&tap_ths_z, 1); - ret += lis2du12_read_reg(ctx, LIS2DU12_INT_DUR, (uint8_t*)&int_dur, 1); + (uint8_t *)&tap_ths_x, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_Y, (uint8_t *)&tap_ths_y, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_Z, (uint8_t *)&tap_ths_z, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_INT_DUR, (uint8_t *)&int_dur, 1); tap_ths_z.tap_z_en = val->z_en; tap_ths_z.tap_y_en = val->y_en; @@ -1409,11 +1477,11 @@ int32_t lis2du12_tap_mode_set(stmdev_ctx_t *ctx, lis2du12_tap_md_t *val) int_dur.latency = val->tap_double.latency; ret += lis2du12_write_reg(ctx, LIS2DU12_WAKE_UP_THS, - (uint8_t*)&wake_up_ths, 1); - ret += lis2du12_write_reg(ctx, LIS2DU12_TAP_THS_X, (uint8_t*)&tap_ths_x, 1); - ret += lis2du12_write_reg(ctx, LIS2DU12_TAP_THS_Y, (uint8_t*)&tap_ths_y, 1); - ret += lis2du12_write_reg(ctx, LIS2DU12_TAP_THS_Z, (uint8_t*)&tap_ths_z, 1); - ret += lis2du12_write_reg(ctx, LIS2DU12_INT_DUR, (uint8_t*)&int_dur, 1); + (uint8_t *)&wake_up_ths, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_TAP_THS_X, (uint8_t *)&tap_ths_x, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_TAP_THS_Y, (uint8_t *)&tap_ths_y, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_TAP_THS_Z, (uint8_t *)&tap_ths_z, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_INT_DUR, (uint8_t *)&int_dur, 1); return ret; } @@ -1426,7 +1494,7 @@ int32_t lis2du12_tap_mode_set(stmdev_ctx_t *ctx, lis2du12_tap_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_tap_mode_get(stmdev_ctx_t *ctx, lis2du12_tap_md_t *val) +int32_t lis2du12_tap_mode_get(const stmdev_ctx_t *ctx, lis2du12_tap_md_t *val) { lis2du12_wake_up_ths_t wake_up_ths; lis2du12_tap_ths_x_t tap_ths_x; @@ -1436,11 +1504,11 @@ int32_t lis2du12_tap_mode_get(stmdev_ctx_t *ctx, lis2du12_tap_md_t *val) int32_t ret; ret = lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_THS, - (uint8_t*)&wake_up_ths, 1); - ret += lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_X, (uint8_t*)&tap_ths_x, 1); - ret += lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_Y, (uint8_t*)&tap_ths_y, 1); - ret += lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_Z, (uint8_t*)&tap_ths_z, 1); - ret += lis2du12_read_reg(ctx, LIS2DU12_INT_DUR, (uint8_t*)&int_dur, 1); + (uint8_t *)&wake_up_ths, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_X, (uint8_t *)&tap_ths_x, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_Y, (uint8_t *)&tap_ths_y, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_Z, (uint8_t *)&tap_ths_z, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_INT_DUR, (uint8_t *)&int_dur, 1); val->z_en = tap_ths_z.tap_z_en; val->y_en = tap_ths_z.tap_y_en; @@ -1453,7 +1521,8 @@ int32_t lis2du12_tap_mode_get(stmdev_ctx_t *ctx, lis2du12_tap_md_t *val) val->shock = int_dur.shock; val->quiet = int_dur.quiet; - switch ( tap_ths_y.tap_priority ) { + switch (tap_ths_y.tap_priority) + { case LIS2DU12_XYZ: val->priority = LIS2DU12_XYZ; break; @@ -1504,15 +1573,15 @@ int32_t lis2du12_tap_mode_get(stmdev_ctx_t *ctx, lis2du12_tap_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_free_fall_mode_set(stmdev_ctx_t *ctx, lis2du12_ff_md_t *val) +int32_t lis2du12_free_fall_mode_set(const stmdev_ctx_t *ctx, lis2du12_ff_md_t *val) { lis2du12_wake_up_dur_t wake_up_dur; lis2du12_free_fall_t free_fall; int32_t ret; ret = lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_DUR, - (uint8_t*)&wake_up_dur, 1); - ret += lis2du12_read_reg(ctx, LIS2DU12_FREE_FALL, (uint8_t*)&free_fall, 1); + (uint8_t *)&wake_up_dur, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_FREE_FALL, (uint8_t *)&free_fall, 1); wake_up_dur.ff_dur = val->duration & 0x1FU; free_fall.ff_dur = (val->duration) & 0x20U >> 5; @@ -1520,8 +1589,8 @@ int32_t lis2du12_free_fall_mode_set(stmdev_ctx_t *ctx, lis2du12_ff_md_t *val) free_fall.ff_ths = (uint8_t)val->threshold; ret += lis2du12_write_reg(ctx, LIS2DU12_WAKE_UP_DUR, - (uint8_t*)&wake_up_dur, 1); - ret += lis2du12_write_reg(ctx, LIS2DU12_FREE_FALL, (uint8_t*)&free_fall, 1); + (uint8_t *)&wake_up_dur, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_FREE_FALL, (uint8_t *)&free_fall, 1); return ret; } @@ -1534,19 +1603,20 @@ int32_t lis2du12_free_fall_mode_set(stmdev_ctx_t *ctx, lis2du12_ff_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_free_fall_mode_get(stmdev_ctx_t *ctx, lis2du12_ff_md_t *val) +int32_t lis2du12_free_fall_mode_get(const stmdev_ctx_t *ctx, lis2du12_ff_md_t *val) { lis2du12_wake_up_dur_t wake_up_dur; lis2du12_free_fall_t free_fall; int32_t ret; ret = lis2du12_read_reg(ctx, LIS2DU12_WAKE_UP_DUR, - (uint8_t*)&wake_up_dur, 1); - ret += lis2du12_read_reg(ctx, LIS2DU12_FREE_FALL, (uint8_t*)&free_fall, 1); + (uint8_t *)&wake_up_dur, 1); + ret += lis2du12_read_reg(ctx, LIS2DU12_FREE_FALL, (uint8_t *)&free_fall, 1); val->duration = (free_fall.ff_dur * 32U) + wake_up_dur.ff_dur; - switch ( free_fall.ff_ths ) { + switch (free_fall.ff_ths) + { case LIS2DU12_156mg: val->threshold = LIS2DU12_156mg; break; @@ -1600,18 +1670,18 @@ int32_t lis2du12_free_fall_mode_get(stmdev_ctx_t *ctx, lis2du12_ff_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_orientation_mode_set(stmdev_ctx_t *ctx, +int32_t lis2du12_orientation_mode_set(const stmdev_ctx_t *ctx, lis2du12_orient_md_t *val) { lis2du12_tap_ths_x_t tap_ths_x; int32_t ret; - ret = lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_X, (uint8_t*)&tap_ths_x, 1); + ret = lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_X, (uint8_t *)&tap_ths_x, 1); tap_ths_x.d6d_ths = (uint8_t)val->threshold; tap_ths_x.d4d_en = (uint8_t)val->deg_of_freedom; - ret += lis2du12_write_reg(ctx, LIS2DU12_TAP_THS_X, (uint8_t*)&tap_ths_x, 1); + ret += lis2du12_write_reg(ctx, LIS2DU12_TAP_THS_X, (uint8_t *)&tap_ths_x, 1); return ret; } @@ -1624,15 +1694,16 @@ int32_t lis2du12_orientation_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2du12_orientation_mode_get(stmdev_ctx_t *ctx, +int32_t lis2du12_orientation_mode_get(const stmdev_ctx_t *ctx, lis2du12_orient_md_t *val) { lis2du12_tap_ths_x_t tap_ths_x; int32_t ret; - ret = lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_X, (uint8_t*)&tap_ths_x, 1); + ret = lis2du12_read_reg(ctx, LIS2DU12_TAP_THS_X, (uint8_t *)&tap_ths_x, 1); - switch ( tap_ths_x.d6d_ths ) { + switch (tap_ths_x.d6d_ths) + { case LIS2DU12_DEG_80: val->threshold = LIS2DU12_DEG_80; break; @@ -1650,7 +1721,8 @@ int32_t lis2du12_orientation_mode_get(stmdev_ctx_t *ctx, break; } - switch ( tap_ths_x.d4d_en ) { + switch (tap_ths_x.d4d_en) + { case LIS2DU12_SIX: val->deg_of_freedom = LIS2DU12_SIX; break; diff --git a/sensor/stmemsc/lis2du12_STdC/driver/lis2du12_reg.h b/sensor/stmemsc/lis2du12_STdC/driver/lis2du12_reg.h index 901a3288..885a8917 100644 --- a/sensor/stmemsc/lis2du12_STdC/driver/lis2du12_reg.h +++ b/sensor/stmemsc/lis2du12_STdC/driver/lis2du12_reg.h @@ -23,7 +23,7 @@ #define LIS2DU12_REGS_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -75,7 +75,8 @@ #ifndef MEMS_SHARED_TYPES #define MEMS_SHARED_TYPES -typedef struct{ +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t bit0 : 1; uint8_t bit1 : 1; @@ -144,7 +145,8 @@ typedef struct * */ -typedef struct { +typedef struct +{ uint8_t address; uint8_t data; } ucf_line_t; @@ -179,7 +181,8 @@ typedef struct { */ #define LIS2DU12_IF_PU_CTRL 0x0CU -typedef struct { +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t not_used_01 : 2; uint8_t cs_pu_disc : 1; @@ -196,7 +199,8 @@ typedef struct { } lis2du12_if_pu_ctrl_t; #define LIS2DU12_IF_CTRL 0x0EU -typedef struct { +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t i2c_disable : 1; uint8_t i3c_disable : 1; @@ -211,7 +215,8 @@ typedef struct { } lis2du12_if_ctrl_t; #define LIS2DU12_CTRL1 0x10U -typedef struct { +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t wu_z_en : 1; uint8_t wu_y_en : 1; @@ -234,7 +239,8 @@ typedef struct { } lis2du12_ctrl1_t; #define LIS2DU12_CTRL2 0x11U -typedef struct { +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t not_used_01 : 3; uint8_t int1_drdy : 1; @@ -253,7 +259,8 @@ typedef struct { } lis2du12_ctrl2_t; #define LIS2DU12_CTRL3 0x12U -typedef struct { +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t st : 2; uint8_t not_used_01 : 1; @@ -274,7 +281,8 @@ typedef struct { } lis2du12_ctrl3_t; #define LIS2DU12_CTRL4 0x13U -typedef struct { +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t boot : 1; uint8_t soc : 1; @@ -291,7 +299,8 @@ typedef struct { } lis2du12_ctrl4_t; #define LIS2DU12_CTRL5 0x14U -typedef struct { +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t fs : 2; uint8_t bw : 2; @@ -304,7 +313,8 @@ typedef struct { } lis2du12_ctrl5_t; #define LIS2DU12_FIFO_CTRL 0x15U -typedef struct { +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t f_mode : 3; uint8_t stop_on_fth : 1; @@ -321,7 +331,8 @@ typedef struct { } lis2du12_fifo_ctrl_t; #define LIS2DU12_FIFO_WTM 0x16U -typedef struct { +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t fth : 7; uint8_t not_used_01 : 1; @@ -332,7 +343,8 @@ typedef struct { } lis2du12_fifo_wtm_t; #define LIS2DU12_INTERRUPT_CFG 0x17U -typedef struct { +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t interrupts_enable : 1; uint8_t lir : 1; @@ -355,7 +367,8 @@ typedef struct { } lis2du12_interrupt_cfg_t; #define LIS2DU12_TAP_THS_X 0x18U -typedef struct { +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t tap_ths_x : 5; uint8_t d6d_ths : 2; @@ -368,7 +381,8 @@ typedef struct { } lis2du12_tap_ths_x_t; #define LIS2DU12_TAP_THS_Y 0x19U -typedef struct { +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t tap_ths_y : 5; uint8_t tap_priority : 3; @@ -379,7 +393,8 @@ typedef struct { } lis2du12_tap_ths_y_t; #define LIS2DU12_TAP_THS_Z 0x1AU -typedef struct { +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t tap_ths_z : 5; uint8_t tap_z_en : 1; @@ -394,7 +409,8 @@ typedef struct { } lis2du12_tap_ths_z_t; #define LIS2DU12_INT_DUR 0x1BU -typedef struct { +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t shock : 2; uint8_t quiet : 2; @@ -407,7 +423,8 @@ typedef struct { } lis2du12_int_dur_t; #define LIS2DU12_WAKE_UP_THS 0x1CU -typedef struct { +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t wk_ths : 6; uint8_t sleep_on : 1; @@ -420,7 +437,8 @@ typedef struct { } lis2du12_wake_up_ths_t; #define LIS2DU12_WAKE_UP_DUR 0x1DU -typedef struct { +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t sleep_dur : 4; uint8_t not_used_01 : 1; @@ -435,7 +453,8 @@ typedef struct { } lis2du12_wake_up_dur_t; #define LIS2DU12_FREE_FALL 0x1EU -typedef struct { +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t ff_ths : 3; uint8_t ff_dur : 5; @@ -446,7 +465,8 @@ typedef struct { } lis2du12_free_fall_t; #define LIS2DU12_MD1_CFG 0x1FU -typedef struct { +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t not_used_01 : 1; uint8_t wu_dur_x4 : 1; @@ -469,7 +489,8 @@ typedef struct { } lis2du12_md1_cfg_t; #define LIS2DU12_MD2_CFG 0x20U -typedef struct { +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t not_used_01 : 1; uint8_t pd_dis_int2 : 1; @@ -492,7 +513,8 @@ typedef struct { } lis2du12_md2_cfg_t; #define LIS2DU12_WAKE_UP_SRC 0x21U -typedef struct { +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t z_wu : 1; uint8_t y_wu : 1; @@ -515,7 +537,8 @@ typedef struct { } lis2du12_wake_up_src_t; #define LIS2DU12_TAP_SRC 0x22U -typedef struct { +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t z_tap : 1; uint8_t y_tap : 1; @@ -538,7 +561,8 @@ typedef struct { } lis2du12_tap_src_t; #define LIS2DU12_SIXD_SRC 0x23U -typedef struct { +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t xl : 1; uint8_t xh : 1; @@ -561,7 +585,8 @@ typedef struct { } lis2du12_sixd_src_t; #define LIS2DU12_ALL_INT_SRC 0x24U -typedef struct { +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t ff_ia_all : 1; uint8_t wu_ia_all : 1; @@ -584,7 +609,8 @@ typedef struct { } lis2du12_all_int_src_t; #define LIS2DU12_STATUS 0x25U -typedef struct { +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t drdy : 1; uint8_t pd_status : 1; @@ -597,7 +623,8 @@ typedef struct { } lis2du12_status_register_t; #define LIS2DU12_FIFO_STATUS1 0x26U -typedef struct { +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t not_used_01 : 6; uint8_t fifo_ovr : 1; @@ -610,7 +637,8 @@ typedef struct { } lis2du12_fifo_status1_t; #define LIS2DU12_FIFO_STATUS2 0x27U -typedef struct { +typedef struct +{ uint8_t fss : 8; } lis2du12_fifo_status2_t; @@ -627,7 +655,8 @@ typedef struct { #define LIS2DU12_WHO_AM_I 0x43U #define LIS2DU12_ST_SIGN 0x58U -typedef struct { +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t not_used_01 : 5; uint8_t stsign : 3; @@ -650,7 +679,8 @@ typedef struct { * */ -typedef union{ +typedef union +{ lis2du12_if_pu_ctrl_t if_pu_ctrl; lis2du12_if_ctrl_t if_ctrl; lis2du12_ctrl1_t ctrl1; @@ -699,9 +729,9 @@ typedef union{ * them with a custom implementation. */ -int32_t lis2du12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data, +int32_t lis2du12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lis2du12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data, +int32_t lis2du12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); float_t lis2du12_from_fs2g_to_mg(int16_t lsb); @@ -710,36 +740,41 @@ float_t lis2du12_from_fs8g_to_mg(int16_t lsb); float_t lis2du12_from_fs16g_to_mg(int16_t lsb); float_t lis2du12_from_lsb_to_celsius(int16_t lsb); -typedef struct { +typedef struct +{ uint8_t whoami; } lis2du12_id_t; -int32_t lis2du12_id_get(stmdev_ctx_t *ctx, lis2du12_id_t *val); +int32_t lis2du12_id_get(const stmdev_ctx_t *ctx, lis2du12_id_t *val); -typedef enum { - LIS2DU12_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */ - LIS2DU12_SPI_4W = 0x03, /* Only SPI: SDO / SDI separated pins */ - LIS2DU12_SPI_3W = 0x07, /* Only SPI: SDO / SDI share the same pin */ - LIS2DU12_I3C_DISABLE = 0x01, /* Select by HW (SPI 3W and I3C disable) */ +typedef enum +{ + LIS2DU12_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */ + LIS2DU12_SPI_4W = 0x03, /* Only SPI: SDO / SDI separated pins */ + LIS2DU12_SPI_3W = 0x07, /* Only SPI: SDO / SDI share the same pin */ + LIS2DU12_I3C_DISABLE = 0x01, /* Select by HW (SPI 3W and I3C disable) */ } lis2du12_bus_mode_t; -int32_t lis2du12_bus_mode_set(stmdev_ctx_t *ctx, lis2du12_bus_mode_t val); -int32_t lis2du12_bus_mode_get(stmdev_ctx_t *ctx, lis2du12_bus_mode_t *val); +int32_t lis2du12_bus_mode_set(const stmdev_ctx_t *ctx, lis2du12_bus_mode_t val); +int32_t lis2du12_bus_mode_get(const stmdev_ctx_t *ctx, lis2du12_bus_mode_t *val); -typedef enum { +typedef enum +{ LIS2DU12_DRV_RDY = 0x00, /* Initialize the device for driver usage */ LIS2DU12_BOOT = 0x01, /* Restore calib. param. ( it takes 10ms ) */ LIS2DU12_RESET = 0x02, /* Reset configuration registers */ } lis2du12_init_t; -int32_t lis2du12_init_set(stmdev_ctx_t *ctx, lis2du12_init_t val); +int32_t lis2du12_init_set(const stmdev_ctx_t *ctx, lis2du12_init_t val); -typedef struct { +typedef struct +{ uint8_t sw_reset : 1; /* Restoring configuration registers */ uint8_t boot : 1; /* Restoring calibration parameters */ uint8_t drdy_xl : 1; /* Accelerometer data ready */ uint8_t power_down : 1; /* Monitors power-down. */ } lis2du12_status_t; -int32_t lis2du12_status_get(stmdev_ctx_t *ctx, lis2du12_status_t *val); +int32_t lis2du12_status_get(const stmdev_ctx_t *ctx, lis2du12_status_t *val); -typedef struct { +typedef struct +{ uint8_t sdo_pull_up : 1; /* 1 = pull up enable */ uint8_t sda_pull_up : 1; /* 1 = pull up enable */ uint8_t cs_pull_up : 1; /* 1 = pull up enable */ @@ -747,10 +782,11 @@ typedef struct { uint8_t int1_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */ uint8_t int2_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */ } lis2du12_pin_conf_t; -int32_t lis2du12_pin_conf_set(stmdev_ctx_t *ctx, lis2du12_pin_conf_t *val); -int32_t lis2du12_pin_conf_get(stmdev_ctx_t *ctx, lis2du12_pin_conf_t *val); +int32_t lis2du12_pin_conf_set(const stmdev_ctx_t *ctx, lis2du12_pin_conf_t *val); +int32_t lis2du12_pin_conf_get(const stmdev_ctx_t *ctx, lis2du12_pin_conf_t *val); -typedef struct { +typedef struct +{ uint8_t free_fall : 1; /* free fall event */ uint8_t wake_up : 1; /* wake up event */ uint8_t wake_up_z : 1; /* wake up on Z axis event */ @@ -772,122 +808,152 @@ typedef struct { uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ uint8_t sleep_state : 1; /* Act/Inact status flag (0-Act / 1-Inact) */ } lis2du12_all_sources_t; -int32_t lis2du12_all_sources_get(stmdev_ctx_t *ctx, +int32_t lis2du12_all_sources_get(const stmdev_ctx_t *ctx, lis2du12_all_sources_t *val); -typedef struct { - enum { - LIS2DU12_OFF = 0x00, /* in power down */ - LIS2DU12_1Hz6_ULP = 0x01, /* @1Hz6(ultralow power) */ - LIS2DU12_3Hz_ULP = 0x02, /* @3Hz (ultralow power) */ - LIS2DU12_6Hz_ULP = 0x03, /* @6Hz (ultralow power) */ - LIS2DU12_6Hz = 0x04, /* @6Hz (normal) */ - LIS2DU12_12Hz5 = 0x05, /* @12Hz5 (normal) */ - LIS2DU12_25Hz = 0x06, /* @25Hz (normal) */ - LIS2DU12_50Hz = 0x07, /* @50Hz (normal) */ - LIS2DU12_100Hz = 0x08, /* @100Hz (normal) */ - LIS2DU12_200Hz = 0x09, /* @200Hz (normal) */ - LIS2DU12_400Hz = 0x0A, /* @400Hz (normal) */ - LIS2DU12_800Hz = 0x0B, /* @800Hz (normal) */ - LIS2DU12_TRIG_PIN = 0x0E, /* Single-shot high latency by INT2 */ - LIS2DU12_TRIG_SW = 0x0F, /* Single-shot high latency by IF */ - } odr; - enum { - LIS2DU12_2g = 0, - LIS2DU12_4g = 1, - LIS2DU12_8g = 2, - LIS2DU12_16g = 3, - } fs; - enum { - LIS2DU12_ODR_div_2 = 0, - LIS2DU12_ODR_div_4 = 1, - LIS2DU12_ODR_div_8 = 2, - LIS2DU12_ODR_div_16 = 3, - } bw; +typedef enum +{ + LIS2DU12_OFF = 0x00, /* in power down */ + LIS2DU12_1Hz6_ULP = 0x01, /* @1Hz6(ultralow power) */ + LIS2DU12_3Hz_ULP = 0x02, /* @3Hz (ultralow power) */ + LIS2DU12_6Hz_ULP = 0x03, /* @6Hz (ultralow power) */ + LIS2DU12_6Hz = 0x04, /* @6Hz (normal) */ + LIS2DU12_12Hz5 = 0x05, /* @12Hz5 (normal) */ + LIS2DU12_25Hz = 0x06, /* @25Hz (normal) */ + LIS2DU12_50Hz = 0x07, /* @50Hz (normal) */ + LIS2DU12_100Hz = 0x08, /* @100Hz (normal) */ + LIS2DU12_200Hz = 0x09, /* @200Hz (normal) */ + LIS2DU12_400Hz = 0x0A, /* @400Hz (normal) */ + LIS2DU12_800Hz = 0x0B, /* @800Hz (normal) */ + LIS2DU12_TRIG_PIN = 0x0E, /* Single-shot high latency by INT2 */ + LIS2DU12_TRIG_SW = 0x0F, /* Single-shot high latency by IF */ +} lis2du12_odr_t; + +typedef enum +{ + LIS2DU12_2g = 0, + LIS2DU12_4g = 1, + LIS2DU12_8g = 2, + LIS2DU12_16g = 3, +} lis2du12_fs_t; + +typedef enum +{ + LIS2DU12_ODR_div_2 = 0, + LIS2DU12_ODR_div_4 = 1, + LIS2DU12_ODR_div_8 = 2, + LIS2DU12_ODR_div_16 = 3, +} lis2du12_bw_t; + +typedef struct +{ + lis2du12_odr_t odr; + lis2du12_fs_t fs; + lis2du12_bw_t bw; } lis2du12_md_t; -int32_t lis2du12_mode_set(stmdev_ctx_t *ctx, lis2du12_md_t *val); -int32_t lis2du12_mode_get(stmdev_ctx_t *ctx, lis2du12_md_t *val); +int32_t lis2du12_mode_set(const stmdev_ctx_t *ctx, lis2du12_md_t *val); +int32_t lis2du12_mode_get(const stmdev_ctx_t *ctx, lis2du12_md_t *val); -int32_t lis2du12_trigger_sw(stmdev_ctx_t *ctx, lis2du12_md_t *val); +int32_t lis2du12_trigger_sw(const stmdev_ctx_t *ctx, lis2du12_md_t *val); -typedef struct { - struct { +typedef struct +{ + struct + { float_t mg[3]; int16_t raw[3]; - }xl; - struct { + } xl; + struct + { float_t deg_c; int16_t raw; - }heat; + } heat; } lis2du12_data_t; -int32_t lis2du12_data_get(stmdev_ctx_t *ctx, lis2du12_md_t *md, +int32_t lis2du12_data_get(const stmdev_ctx_t *ctx, lis2du12_md_t *md, lis2du12_data_t *data); -typedef enum { +typedef enum +{ LIS2DU12_ST_DISABLE = 0, LIS2DU12_ST_POSITIVE = 6, LIS2DU12_ST_NEGATIVE = 1, } lis2du12_st_t; -int32_t lis2du12_self_test_sign_set(stmdev_ctx_t *ctx, lis2du12_st_t val); -int32_t lis2du12_self_test_start(stmdev_ctx_t *ctx, uint8_t val); /* valid values: 1 or 2 */ -int32_t lis2du12_self_test_stop(stmdev_ctx_t *ctx); - -typedef struct { - enum { - LIS2DU12_BYPASS = 0, - LIS2DU12_FIFO = 1, - LIS2DU12_STREAM = 6, - LIS2DU12_STREAM_TO_FIFO = 3, /* Dynamic-Stream, FIFO on Trigger */ - LIS2DU12_BYPASS_TO_STREAM = 4, /* Bypass, Dynamic-Stream on Trigger */ - LIS2DU12_BYPASS_TO_FIFO = 7, /* Bypass, FIFO on Trigger */ - } operation; - enum { - LIS2DU12_8_BIT = 0, - LIS2DU12_16_BIT = 1, - } store; +int32_t lis2du12_self_test_sign_set(const stmdev_ctx_t *ctx, lis2du12_st_t val); +int32_t lis2du12_self_test_start(const stmdev_ctx_t *ctx, uint8_t val); /* valid values: 1 or 2 */ +int32_t lis2du12_self_test_stop(const stmdev_ctx_t *ctx); + +typedef enum +{ + LIS2DU12_BYPASS = 0, + LIS2DU12_FIFO = 1, + LIS2DU12_STREAM = 6, + LIS2DU12_STREAM_TO_FIFO = 3, /* Dynamic-Stream, FIFO on Trigger */ + LIS2DU12_BYPASS_TO_STREAM = 4, /* Bypass, Dynamic-Stream on Trigger */ + LIS2DU12_BYPASS_TO_FIFO = 7, /* Bypass, FIFO on Trigger */ +} lis2du12_fifo_operation_t; + +typedef enum +{ + LIS2DU12_8_BIT = 0, + LIS2DU12_16_BIT = 1, +} lis2du12_fifo_store_t; + +typedef struct +{ + lis2du12_fifo_operation_t operation; + lis2du12_fifo_store_t store; uint8_t watermark; /* (0 disable) max 127 @16bit, even and max 256 @8bit.*/ } lis2du12_fifo_md_t; -int32_t lis2du12_fifo_mode_set(stmdev_ctx_t *ctx, lis2du12_fifo_md_t *val); -int32_t lis2du12_fifo_mode_get(stmdev_ctx_t *ctx, lis2du12_fifo_md_t *val); +int32_t lis2du12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2du12_fifo_md_t *val); +int32_t lis2du12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2du12_fifo_md_t *val); -typedef struct { +typedef struct +{ uint8_t fifo_fth : 1; /* 1 = fifo threshold event */ uint8_t fifo_ovr : 1; /* 1 = fifo overrun event */ } lis2du12_fifo_status_t; -int32_t lis2du12_fifo_status_get(stmdev_ctx_t *ctx, lis2du12_fifo_status_t *val); +int32_t lis2du12_fifo_status_get(const stmdev_ctx_t *ctx, lis2du12_fifo_status_t *val); -int32_t lis2du12_fifo_level_get(stmdev_ctx_t *ctx, lis2du12_fifo_md_t *md, +int32_t lis2du12_fifo_level_get(const stmdev_ctx_t *ctx, lis2du12_fifo_md_t *md, uint8_t *val); -typedef struct { - struct { +typedef struct +{ + struct + { float_t mg[3]; int16_t raw[3]; - }xl[2]; - struct { + } xl[2]; + struct + { float_t deg_c; int16_t raw; - }heat; + } heat; } lis2du12_fifo_data_t; -int32_t lis2du12_fifo_data_get(stmdev_ctx_t *ctx, lis2du12_md_t *md, +int32_t lis2du12_fifo_data_get(const stmdev_ctx_t *ctx, lis2du12_md_t *md, lis2du12_fifo_md_t *fmd, lis2du12_fifo_data_t *data); -typedef struct { +typedef enum +{ + LIS2DU12_INT_LEVEL = 0, /* active till event condition persist */ + LIS2DU12_INT_LATCHED = 3, /* read ALL_INT_SRC for reset (API all_sources)*/ +} lis2du12_base_sig_t; /* base functions are: FF, WU(W2S), 4/6D, Tap */ + +typedef struct +{ uint8_t enable : 1; /* 1 = enabled / 0 = disabled */ uint8_t active_low : 1; /* 1 = active low / 0 = active high */ uint8_t drdy_latched : 1; /* drdy returns to 0 after reading data */ - enum { - LIS2DU12_INT_LEVEL = 0, /* active till event condition persist */ - LIS2DU12_INT_LATCHED = 3, /* read ALL_INT_SRC for reset (API all_sources)*/ -} base_sig; /* base functions are: FF, WU(W2S), 4/6D, Tap */ + lis2du12_base_sig_t base_sig; } lis2du12_int_mode_t; -int32_t lis2du12_interrupt_mode_set(stmdev_ctx_t *ctx, +int32_t lis2du12_interrupt_mode_set(const stmdev_ctx_t *ctx, lis2du12_int_mode_t *val); -int32_t lis2du12_interrupt_mode_get(stmdev_ctx_t *ctx, +int32_t lis2du12_interrupt_mode_get(const stmdev_ctx_t *ctx, lis2du12_int_mode_t *val); -typedef struct { +typedef struct +{ uint8_t drdy_xl : 1; /* Accelerometer data ready */ uint8_t boot : 1; /* Restoring calibration parameters */ uint8_t fifo_th : 1; /* FIFO threshold reached */ @@ -901,94 +967,116 @@ typedef struct { uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ uint8_t sleep_state : 1; /* Act/Inact status flag */ } lis2du12_pin_int_route_t; -int32_t lis2du12_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lis2du12_pin_int1_route_set(const stmdev_ctx_t *ctx, lis2du12_pin_int_route_t *val); -int32_t lis2du12_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lis2du12_pin_int1_route_get(const stmdev_ctx_t *ctx, lis2du12_pin_int_route_t *val); -int32_t lis2du12_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lis2du12_pin_int2_route_set(const stmdev_ctx_t *ctx, lis2du12_pin_int_route_t *val); -int32_t lis2du12_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lis2du12_pin_int2_route_get(const stmdev_ctx_t *ctx, lis2du12_pin_int_route_t *val); -typedef struct { +typedef enum +{ + LIS2DU12_DO_NOT_CHANGE = 0, + LIS2DU12_SLEEP_AT_6Hz = 1, + LIS2DU12_SLEEP_AT_3Hz = 2, + LIS2DU12_SLEEP_AT_1Hz6 = 3, +} lis2du12_sleep_odr_t; + +typedef struct +{ uint8_t x_en : 1; /* Detection on X-axis */ uint8_t y_en : 1; /* Detection on Y-axis */ uint8_t z_en : 1; /* Detection on Z-axis */ uint8_t threshold; /* full scale dependent */ uint8_t duration; /* 1 LSb: 1 ODR_time */ - struct { + struct + { uint8_t en : 1; /* Enable sleep detection */ uint8_t duration; /* 0 is 16 ODR_time, 1 LSB: 512 ODR_time. */ - enum { - LIS2DU12_DO_NOT_CHANGE = 0, - LIS2DU12_SLEEP_AT_6Hz = 1, - LIS2DU12_SLEEP_AT_3Hz = 2, - LIS2DU12_SLEEP_AT_1Hz6 = 3, - } odr; + lis2du12_sleep_odr_t odr; } sleep; } lis2du12_wkup_md_t; -int32_t lis2du12_wake_up_mode_set(stmdev_ctx_t *ctx, lis2du12_wkup_md_t *val); -int32_t lis2du12_wake_up_mode_get(stmdev_ctx_t *ctx, lis2du12_wkup_md_t *val); +int32_t lis2du12_wake_up_mode_set(const stmdev_ctx_t *ctx, lis2du12_wkup_md_t *val); +int32_t lis2du12_wake_up_mode_get(const stmdev_ctx_t *ctx, lis2du12_wkup_md_t *val); -typedef struct { +typedef enum +{ + LIS2DU12_XYZ = 0, + LIS2DU12_YXZ = 1, + LIS2DU12_XZY = 2, + LIS2DU12_ZYX = 3, + LIS2DU12_YZX = 5, + LIS2DU12_ZXY = 6, +} lis2du12_priority_t; + +typedef struct +{ uint8_t x_en : 1; /* Detection on X-axis */ uint8_t y_en : 1; /* Detection on Y-axis */ uint8_t z_en : 1; /* Detection on Z-axis */ - struct { + struct + { uint8_t x; uint8_t y; uint8_t z; } threshold; uint8_t shock; /* max shock time. 0 is 4 ODR_time, 1 LSb : 8 ODR_time. */ uint8_t quiet; /* Time after a tap. 0 is 2 ODR_time, 1 LSB : 4 ODR_time.*/ - enum { - LIS2DU12_XYZ = 0, - LIS2DU12_YXZ = 1, - LIS2DU12_XZY = 2, - LIS2DU12_ZYX = 3, - LIS2DU12_YZX = 5, - LIS2DU12_ZXY = 6, - } priority; - struct { + lis2du12_priority_t priority; + struct + { uint8_t en : 1; /* Double tap detection */ uint8_t latency; /* Max time gap. 0 is 16 ODR_time, 1 LSB : 32 ODR_time. */ } tap_double; } lis2du12_tap_md_t; -int32_t lis2du12_tap_mode_set(stmdev_ctx_t *ctx, lis2du12_tap_md_t *val); -int32_t lis2du12_tap_mode_get(stmdev_ctx_t *ctx, lis2du12_tap_md_t *val); - -typedef struct { - enum { - LIS2DU12_156mg = 0, - LIS2DU12_219mg = 1, - LIS2DU12_250mg = 2, - LIS2DU12_312mg = 3, - LIS2DU12_344mg = 4, - LIS2DU12_406mg = 5, - LIS2DU12_469mg = 6, - LIS2DU12_500mg = 7, - } threshold; +int32_t lis2du12_tap_mode_set(const stmdev_ctx_t *ctx, lis2du12_tap_md_t *val); +int32_t lis2du12_tap_mode_get(const stmdev_ctx_t *ctx, lis2du12_tap_md_t *val); + +typedef enum +{ + LIS2DU12_156mg = 0, + LIS2DU12_219mg = 1, + LIS2DU12_250mg = 2, + LIS2DU12_312mg = 3, + LIS2DU12_344mg = 4, + LIS2DU12_406mg = 5, + LIS2DU12_469mg = 6, + LIS2DU12_500mg = 7, +} lis2du12_threshold_t; + +typedef struct +{ + lis2du12_threshold_t threshold; uint8_t duration; /* 1 LSb: 1 ODR_time */ } lis2du12_ff_md_t; -int32_t lis2du12_free_fall_mode_set(stmdev_ctx_t *ctx, lis2du12_ff_md_t *val); -int32_t lis2du12_free_fall_mode_get(stmdev_ctx_t *ctx, lis2du12_ff_md_t *val); - -typedef struct { - enum { - LIS2DU12_DEG_80 = 0, - LIS2DU12_DEG_70 = 1, - LIS2DU12_DEG_60 = 2, - LIS2DU12_DEG_50 = 3, - } threshold; - enum { - LIS2DU12_SIX = 0, - LIS2DU12_FOUR = 1, - } deg_of_freedom; +int32_t lis2du12_free_fall_mode_set(const stmdev_ctx_t *ctx, lis2du12_ff_md_t *val); +int32_t lis2du12_free_fall_mode_get(const stmdev_ctx_t *ctx, lis2du12_ff_md_t *val); + +typedef enum +{ + LIS2DU12_DEG_80 = 0, + LIS2DU12_DEG_70 = 1, + LIS2DU12_DEG_60 = 2, + LIS2DU12_DEG_50 = 3, +} lis2du12_orient_trshld_t; + +typedef enum +{ + LIS2DU12_SIX = 0, + LIS2DU12_FOUR = 1, +} lis2du12_deg_of_freedom_t; + +typedef struct +{ + lis2du12_orient_trshld_t threshold; + lis2du12_deg_of_freedom_t deg_of_freedom; } lis2du12_orient_md_t; -int32_t lis2du12_orientation_mode_set(stmdev_ctx_t *ctx, +int32_t lis2du12_orientation_mode_set(const stmdev_ctx_t *ctx, lis2du12_orient_md_t *val); -int32_t lis2du12_orientation_mode_get(stmdev_ctx_t *ctx, +int32_t lis2du12_orientation_mode_get(const stmdev_ctx_t *ctx, lis2du12_orient_md_t *val); /** diff --git a/sensor/stmemsc/lis2dux12_STdC/driver/lis2dux12_reg.c b/sensor/stmemsc/lis2dux12_STdC/driver/lis2dux12_reg.c index 2da763de..f1b94b1c 100644 --- a/sensor/stmemsc/lis2dux12_STdC/driver/lis2dux12_reg.c +++ b/sensor/stmemsc/lis2dux12_STdC/driver/lis2dux12_reg.c @@ -46,12 +46,15 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis2dux12_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data, +int32_t __weak lis2dux12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { - int32_t ret; - ret = ctx->read_reg(ctx->handle, reg, data, len); - return ret; + if (ctx == NULL) + { + return -1; + } + + return ctx->read_reg(ctx->handle, reg, data, len); } /** @@ -64,12 +67,15 @@ int32_t __weak lis2dux12_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis2dux12_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data, +int32_t __weak lis2dux12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { - int32_t ret; - ret = ctx->write_reg(ctx->handle, reg, data, len); - return ret; + if (ctx == NULL) + { + return -1; + } + + return ctx->write_reg(ctx->handle, reg, data, len); } /** @@ -128,7 +134,7 @@ float_t lis2dux12_from_lsb_to_celsius(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_device_id_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dux12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -145,43 +151,103 @@ int32_t lis2dux12_device_id_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_init_set(stmdev_ctx_t *ctx, lis2dux12_init_t val) +int32_t lis2dux12_init_set(const stmdev_ctx_t *ctx, lis2dux12_init_t val) { lis2dux12_ctrl1_t ctrl1; lis2dux12_ctrl4_t ctrl4; + lis2dux12_status_t status; + uint8_t cnt = 0; int32_t ret = 0; - ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL1, (uint8_t*)&ctrl1, 1); - ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL4, (uint8_t*)&ctrl4, 1); - switch (val) { + ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1); + switch (val) + { case LIS2DUX12_BOOT: ctrl4.boot = PROPERTY_ENABLE; - ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL4, (uint8_t*)&ctrl4, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + break; + } + + do + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + break; + } + + /* boot procedue ended correctly */ + if (ctrl4.boot == 0U) + { + break; + } + + if (ctx->mdelay != NULL) + { + ctx->mdelay(25); /* 25 ms of boot time */ + } + } while (cnt++ < 5U); + + if (cnt >= 5U) + { + ret = -1; /* boot procedure failed */ + } break; case LIS2DUX12_RESET: - ctrl1.sw_reset = PROPERTY_ENABLE; - ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL1, (uint8_t*)&ctrl1, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) + { + break; + } + + do + { + ret = lis2dux12_status_get(ctx, &status); + if (ret != 0) + { + break; + } + + /* sw-reset procedue ended correctly */ + if (status.sw_reset == 0U) + { + break; + } + + if (ctx->mdelay != NULL) + { + ctx->mdelay(1); /* should be 50 us */ + } + } while (cnt++ < 5U); + + if (cnt >= 5U) + { + ret = -1; /* sw-reset procedure failed */ + } break; case LIS2DUX12_SENSOR_ONLY_ON: /* no embedded funcs are used */ ctrl4.emb_func_en = PROPERTY_DISABLE; ctrl4.bdu = PROPERTY_ENABLE; ctrl1.if_add_inc = PROPERTY_ENABLE; - ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL4, (uint8_t*)&ctrl4, 1); - ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL1, (uint8_t*)&ctrl1, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1); break; case LIS2DUX12_SENSOR_EMB_FUNC_ON: /* complete configuration is used */ ctrl4.emb_func_en = PROPERTY_ENABLE; ctrl4.bdu = PROPERTY_ENABLE; ctrl1.if_add_inc = PROPERTY_ENABLE; - ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL4, (uint8_t*)&ctrl4, 1); - ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL1, (uint8_t*)&ctrl1, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1); break; default: ctrl1.sw_reset = PROPERTY_ENABLE; - ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL1, (uint8_t*)&ctrl1, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1); break; } return ret; @@ -195,7 +261,7 @@ int32_t lis2dux12_init_set(stmdev_ctx_t *ctx, lis2dux12_init_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_status_get(stmdev_ctx_t *ctx, lis2dux12_status_t *val) +int32_t lis2dux12_status_get(const stmdev_ctx_t *ctx, lis2dux12_status_t *val) { lis2dux12_status_register_t status_register; lis2dux12_ctrl1_t ctrl1; @@ -203,13 +269,9 @@ int32_t lis2dux12_status_get(stmdev_ctx_t *ctx, lis2dux12_status_t *val) int32_t ret; ret = lis2dux12_read_reg(ctx, LIS2DUX12_STATUS, - (uint8_t*)&status_register, 1); - if (ret == 0) { - ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL1, (uint8_t*)&ctrl1, 1); - } - if (ret == 0) { - ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL4, (uint8_t*)&ctrl4, 1); - } + (uint8_t *)&status_register, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL1, (uint8_t *)&ctrl1, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1); val->sw_reset = ctrl1.sw_reset; val->boot = ctrl4.boot; @@ -226,13 +288,13 @@ int32_t lis2dux12_status_get(stmdev_ctx_t *ctx, lis2dux12_status_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_embedded_status_get(stmdev_ctx_t *ctx, lis2dux12_embedded_status_t *val) +int32_t lis2dux12_embedded_status_get(const stmdev_ctx_t *ctx, lis2dux12_embedded_status_t *val) { lis2dux12_emb_func_status_t status; int32_t ret; ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); - ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_STATUS, (uint8_t*)&status, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_STATUS, (uint8_t *)&status, 1); ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); val->is_step_det = status.is_step_det; @@ -250,7 +312,7 @@ int32_t lis2dux12_embedded_status_get(stmdev_ctx_t *ctx, lis2dux12_embedded_stat * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_data_ready_mode_set(stmdev_ctx_t *ctx, lis2dux12_data_ready_mode_t val) +int32_t lis2dux12_data_ready_mode_set(const stmdev_ctx_t *ctx, lis2dux12_data_ready_mode_t val) { lis2dux12_ctrl1_t ctrl1; int32_t ret; @@ -274,7 +336,7 @@ int32_t lis2dux12_data_ready_mode_set(stmdev_ctx_t *ctx, lis2dux12_data_ready_mo * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_data_ready_mode_get(stmdev_ctx_t *ctx, lis2dux12_data_ready_mode_t *val) +int32_t lis2dux12_data_ready_mode_get(const stmdev_ctx_t *ctx, lis2dux12_data_ready_mode_t *val) { lis2dux12_ctrl1_t ctrl1; int32_t ret; @@ -283,11 +345,11 @@ int32_t lis2dux12_data_ready_mode_get(stmdev_ctx_t *ctx, lis2dux12_data_ready_mo switch ((ctrl1.drdy_pulsed)) { - case LIS2DUX12_DRDY_LATCHED: + case 0x0: *val = LIS2DUX12_DRDY_LATCHED; break; - case LIS2DUX12_DRDY_PULSED: + case 0x1: *val = LIS2DUX12_DRDY_PULSED; break; @@ -306,19 +368,20 @@ int32_t lis2dux12_data_ready_mode_get(stmdev_ctx_t *ctx, lis2dux12_data_ready_mo * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_mode_set(stmdev_ctx_t *ctx, lis2dux12_md_t *val) +int32_t lis2dux12_mode_set(const stmdev_ctx_t *ctx, const lis2dux12_md_t *val) { lis2dux12_ctrl3_t ctrl3; lis2dux12_ctrl5_t ctrl5; int32_t ret; - ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL5, (uint8_t*)&ctrl5, 1); + ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL5, (uint8_t *)&ctrl5, 1); ctrl5.odr = (uint8_t)val->odr & 0xFU; ctrl5.fs = (uint8_t)val->fs; /* set the bandwidth */ - switch (val->odr) { + switch (val->odr) + { /* no anti-aliasing filter present */ case LIS2DUX12_OFF: case LIS2DUX12_1Hz6_ULP: @@ -329,21 +392,29 @@ int32_t lis2dux12_mode_set(stmdev_ctx_t *ctx, lis2dux12_md_t *val) /* low-power mode with ODR < 50 Hz */ case LIS2DUX12_6Hz_LP: - switch(val->bw) { + switch (val->bw) + { + default: case LIS2DUX12_ODR_div_4: case LIS2DUX12_ODR_div_8: case LIS2DUX12_ODR_div_16: - return -1; + /* value not allowed */ + ret = -1; + break; case LIS2DUX12_ODR_div_2: ctrl5.bw = 0x3; break; } break; case LIS2DUX12_12Hz5_LP: - switch(val->bw) { + switch (val->bw) + { + default: case LIS2DUX12_ODR_div_8: case LIS2DUX12_ODR_div_16: - return -1; + /* value not allowed */ + ret = -1; + break; case LIS2DUX12_ODR_div_2: ctrl5.bw = 0x2; break; @@ -353,9 +424,13 @@ int32_t lis2dux12_mode_set(stmdev_ctx_t *ctx, lis2dux12_md_t *val) } break; case LIS2DUX12_25Hz_LP: - switch(val->bw) { + switch (val->bw) + { + default: case LIS2DUX12_ODR_div_16: - return -1; + /* value not allowed */ + ret = -1; + break; case LIS2DUX12_ODR_div_2: ctrl5.bw = 0x1; break; @@ -384,17 +459,24 @@ int32_t lis2dux12_mode_set(stmdev_ctx_t *ctx, lis2dux12_md_t *val) case LIS2DUX12_200Hz_HP: case LIS2DUX12_400Hz_HP: case LIS2DUX12_800Hz_HP: + default: ctrl5.bw = (uint8_t)val->bw; break; } - ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL3, (uint8_t*)&ctrl3, 1); + if (ret != 0) + { + return ret; + } + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL3, (uint8_t *)&ctrl3, 1); ctrl3.hp_en = (((uint8_t)val->odr & 0x30U) == 0x10U) ? 1U : 0U; - if (ret == 0) { - ret = lis2dux12_write_reg(ctx, LIS2DUX12_CTRL5, (uint8_t*)&ctrl5, 1); - ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL3, (uint8_t*)&ctrl3, 1); + if (ret == 0) + { + ret = lis2dux12_write_reg(ctx, LIS2DUX12_CTRL5, (uint8_t *)&ctrl5, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL3, (uint8_t *)&ctrl3, 1); } return ret; @@ -408,56 +490,57 @@ int32_t lis2dux12_mode_set(stmdev_ctx_t *ctx, lis2dux12_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_mode_get(stmdev_ctx_t *ctx, lis2dux12_md_t *val) +int32_t lis2dux12_mode_get(const stmdev_ctx_t *ctx, lis2dux12_md_t *val) { lis2dux12_ctrl3_t ctrl3; lis2dux12_ctrl5_t ctrl5; int32_t ret; - ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL5, (uint8_t*)&ctrl5, 1); - ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL3, (uint8_t*)&ctrl3, 1); + ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL5, (uint8_t *)&ctrl5, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_CTRL3, (uint8_t *)&ctrl3, 1); - switch (ctrl5.odr) { - case LIS2DUX12_OFF: + switch (ctrl5.odr) + { + case 0x00: val->odr = LIS2DUX12_OFF; break; - case LIS2DUX12_1Hz6_ULP: + case 0x01: val->odr = LIS2DUX12_1Hz6_ULP; break; - case LIS2DUX12_3Hz_ULP: + case 0x02: val->odr = LIS2DUX12_3Hz_ULP; break; - case LIS2DUX12_25Hz_ULP: + case 0x03: val->odr = LIS2DUX12_25Hz_ULP; break; - case LIS2DUX12_6Hz_LP: + case 0x04: val->odr = LIS2DUX12_6Hz_LP; break; - case LIS2DUX12_12Hz5_LP: + case 0x05: val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUX12_12Hz5_HP : LIS2DUX12_12Hz5_LP; break; - case LIS2DUX12_25Hz_LP: + case 0x06: val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUX12_25Hz_HP : LIS2DUX12_25Hz_LP; break; - case LIS2DUX12_50Hz_LP: + case 0x07: val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUX12_50Hz_HP : LIS2DUX12_50Hz_LP; break; - case LIS2DUX12_100Hz_LP: + case 0x08: val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUX12_100Hz_HP : LIS2DUX12_100Hz_LP; break; - case LIS2DUX12_200Hz_LP: + case 0x09: val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUX12_200Hz_HP : LIS2DUX12_200Hz_LP; break; - case LIS2DUX12_400Hz_LP: + case 0x0A: val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUX12_400Hz_HP : LIS2DUX12_400Hz_LP; break; - case LIS2DUX12_800Hz_LP: + case 0x0B: val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUX12_800Hz_HP : LIS2DUX12_800Hz_LP; break; - case LIS2DUX12_TRIG_PIN: + case 0xe: val->odr = LIS2DUX12_TRIG_PIN; break; - case LIS2DUX12_TRIG_SW: + case 0xf: val->odr = LIS2DUX12_TRIG_SW; break; default: @@ -465,17 +548,18 @@ int32_t lis2dux12_mode_get(stmdev_ctx_t *ctx, lis2dux12_md_t *val) break; } - switch (ctrl5.fs) { - case LIS2DUX12_2g: + switch (ctrl5.fs) + { + case 0: val->fs = LIS2DUX12_2g; break; - case LIS2DUX12_4g: + case 1: val->fs = LIS2DUX12_4g; break; - case LIS2DUX12_8g: + case 2: val->fs = LIS2DUX12_8g; break; - case LIS2DUX12_16g: + case 3: val->fs = LIS2DUX12_16g; break; default: @@ -483,17 +567,18 @@ int32_t lis2dux12_mode_get(stmdev_ctx_t *ctx, lis2dux12_md_t *val) break; } - switch (ctrl5.bw) { - case LIS2DUX12_ODR_div_2: + switch (ctrl5.bw) + { + case 0: val->bw = LIS2DUX12_ODR_div_2; break; - case LIS2DUX12_ODR_div_4: + case 1: val->bw = LIS2DUX12_ODR_div_4; break; - case LIS2DUX12_ODR_div_8: + case 2: val->bw = LIS2DUX12_ODR_div_8; break; - case LIS2DUX12_ODR_div_16: + case 3: val->bw = LIS2DUX12_ODR_div_16; break; default: @@ -504,6 +589,49 @@ int32_t lis2dux12_mode_get(stmdev_ctx_t *ctx, lis2dux12_md_t *val) return ret; } +/** + * @brief Disable/Enable temperature sensor acquisition[set] + * + * @param ctx read / write interface definitions + * @param val 1: disable temp acquisition - 0: enable temp acquisition + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_temp_disable_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lis2dux12_self_test_t temp; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_SELF_TEST, (uint8_t *)&temp, 1); + + if (ret == 0) + { + temp.t_dis = val; + ret = lis2dux12_write_reg(ctx, LIS2DUX12_SELF_TEST, (uint8_t *)&temp, 1); + } + + return ret; +} + +/** + * @brief Disable/Enable temperature sensor acquisition[get] + * + * @param ctx read / write interface definitions + * @param val 1: disable temp acquisition - 0: enable temp acquisition + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_temp_disable_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lis2dux12_self_test_t temp; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_SELF_TEST, (uint8_t *)&temp, 1); + *val = temp.t_dis; + + return ret; +} + /** * @brief Enter deep power down[set] * @@ -512,7 +640,7 @@ int32_t lis2dux12_mode_get(stmdev_ctx_t *ctx, lis2dux12_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_enter_deep_power_down(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dux12_enter_deep_power_down(const stmdev_ctx_t *ctx, uint8_t val) { lis2dux12_sleep_t sleep; int32_t ret; @@ -536,13 +664,18 @@ int32_t lis2dux12_enter_deep_power_down(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_exit_deep_power_down(stmdev_ctx_t *ctx) +int32_t lis2dux12_exit_deep_power_down(const stmdev_ctx_t *ctx) { - lis2dux12_if_wake_up_t if_wake_up = {0}; + lis2dux12_en_device_config_t en_device_config = {0}; int32_t ret; - if_wake_up.soft_pd = PROPERTY_ENABLE; - ret = lis2dux12_write_reg(ctx, LIS2DUX12_IF_WAKE_UP, (uint8_t *)&if_wake_up, 1); + en_device_config.soft_pd = PROPERTY_ENABLE; + ret = lis2dux12_write_reg(ctx, LIS2DUX12_EN_DEVICE_CONFIG, (uint8_t *)&en_device_config, 1); + + if (ctx->mdelay != NULL) + { + ctx->mdelay(25); /* See AN5909 - paragraphs 3.1.1.1 and 3.1.1.2 */ + } return ret; } @@ -555,27 +688,29 @@ int32_t lis2dux12_exit_deep_power_down(stmdev_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_trigger_sw(stmdev_ctx_t *ctx, lis2dux12_md_t *md) +int32_t lis2dux12_trigger_sw(const stmdev_ctx_t *ctx, const lis2dux12_md_t *md) { lis2dux12_ctrl4_t ctrl4; int32_t ret = 0; - if ( md->odr == LIS2DUX12_TRIG_SW ) { - ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL4, (uint8_t*)&ctrl4, 1); + if (md->odr == LIS2DUX12_TRIG_SW) + { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1); ctrl4.soc = PROPERTY_ENABLE; - if (ret == 0) { - ret = lis2dux12_write_reg(ctx, LIS2DUX12_CTRL4, (uint8_t*)&ctrl4, 1); + if (ret == 0) + { + ret = lis2dux12_write_reg(ctx, LIS2DUX12_CTRL4, (uint8_t *)&ctrl4, 1); } } return ret; } -int32_t lis2dux12_all_sources_get(stmdev_ctx_t *ctx, lis2dux12_all_sources_t *val) +int32_t lis2dux12_all_sources_get(const stmdev_ctx_t *ctx, lis2dux12_all_sources_t *val) { lis2dux12_status_register_t status; int32_t ret; - ret = lis2dux12_read_reg(ctx, LIS2DUX12_STATUS, (uint8_t*)&status, 1); + ret = lis2dux12_read_reg(ctx, LIS2DUX12_STATUS, (uint8_t *)&status, 1); val->drdy = status.drdy; if (ret == 0 && status.int_global == 0x1U) @@ -584,9 +719,9 @@ int32_t lis2dux12_all_sources_get(stmdev_ctx_t *ctx, lis2dux12_all_sources_t *va lis2dux12_tap_src_t tap_src; lis2dux12_sixd_src_t sixd_src; - ret = lis2dux12_read_reg(ctx, LIS2DUX12_SIXD_SRC, (uint8_t*)&sixd_src, 1); - ret += lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_SRC, (uint8_t*)&wu_src, 1); - ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_SRC, (uint8_t*)&tap_src, 1); + ret = lis2dux12_read_reg(ctx, LIS2DUX12_SIXD_SRC, (uint8_t *)&sixd_src, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_SRC, (uint8_t *)&wu_src, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_TAP_SRC, (uint8_t *)&tap_src, 1); val->six_d = sixd_src.d6d_ia; val->six_d_xl = sixd_src.xl; @@ -621,8 +756,8 @@ int32_t lis2dux12_all_sources_get(stmdev_ctx_t *ctx, lis2dux12_all_sources_t *va * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_xl_data_get(stmdev_ctx_t *ctx, lis2dux12_md_t *md, - lis2dux12_xl_data_t *data) +int32_t lis2dux12_xl_data_get(const stmdev_ctx_t *ctx, const lis2dux12_md_t *md, + lis2dux12_xl_data_t *data) { uint8_t buff[6]; int32_t ret; @@ -633,22 +768,24 @@ int32_t lis2dux12_xl_data_get(stmdev_ctx_t *ctx, lis2dux12_md_t *md, /* acceleration conversion */ j = 0U; - for (i = 0U; i < 3U; i++) { - data->raw[i] = (int16_t)buff[j+1U]; + for (i = 0U; i < 3U; i++) + { + data->raw[i] = (int16_t)buff[j + 1U]; data->raw[i] = (data->raw[i] * 256) + (int16_t) buff[j]; - j+=2U; - switch ( md->fs ) { + j += 2U; + switch (md->fs) + { case LIS2DUX12_2g: - data->mg[i] =lis2dux12_from_fs2g_to_mg(data->raw[i]); + data->mg[i] = lis2dux12_from_fs2g_to_mg(data->raw[i]); break; case LIS2DUX12_4g: - data->mg[i] =lis2dux12_from_fs4g_to_mg(data->raw[i]); + data->mg[i] = lis2dux12_from_fs4g_to_mg(data->raw[i]); break; case LIS2DUX12_8g: - data->mg[i] =lis2dux12_from_fs8g_to_mg(data->raw[i]); + data->mg[i] = lis2dux12_from_fs8g_to_mg(data->raw[i]); break; case LIS2DUX12_16g: - data->mg[i] =lis2dux12_from_fs16g_to_mg(data->raw[i]); + data->mg[i] = lis2dux12_from_fs16g_to_mg(data->raw[i]); break; default: data->mg[i] = 0.0f; @@ -668,8 +805,8 @@ int32_t lis2dux12_xl_data_get(stmdev_ctx_t *ctx, lis2dux12_md_t *md, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_outt_data_get(stmdev_ctx_t *ctx, lis2dux12_md_t *md, - lis2dux12_outt_data_t *data) +int32_t lis2dux12_outt_data_get(const stmdev_ctx_t *ctx, + lis2dux12_outt_data_t *data) { uint8_t buff[2]; int32_t ret; @@ -692,37 +829,38 @@ int32_t lis2dux12_outt_data_get(stmdev_ctx_t *ctx, lis2dux12_md_t *md, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_self_test_sign_set(stmdev_ctx_t *ctx, lis2dux12_xl_self_test_t val) +int32_t lis2dux12_self_test_sign_set(const stmdev_ctx_t *ctx, lis2dux12_xl_self_test_t val) { lis2dux12_ctrl3_t ctrl3; lis2dux12_wake_up_dur_t wkup_dur; int32_t ret; - ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL3, (uint8_t*)&ctrl3, 1); - ret += lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_DUR, (uint8_t*)&wkup_dur, 1); + ret = lis2dux12_read_reg(ctx, LIS2DUX12_CTRL3, (uint8_t *)&ctrl3, 1); + ret += lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_DUR, (uint8_t *)&wkup_dur, 1); - switch (val) { - case LIS2DUX12_XL_ST_POSITIVE: - ctrl3.st_sign_x = 1; - ctrl3.st_sign_y = 1; - wkup_dur.st_sign_z = 0; - break; + switch (val) + { + case LIS2DUX12_XL_ST_POSITIVE: + ctrl3.st_sign_x = 1; + ctrl3.st_sign_y = 1; + wkup_dur.st_sign_z = 0; + break; - case LIS2DUX12_XL_ST_NEGATIVE: - ctrl3.st_sign_x = 0; - ctrl3.st_sign_y = 0; - wkup_dur.st_sign_z = 1; - break; + case LIS2DUX12_XL_ST_NEGATIVE: + ctrl3.st_sign_x = 0; + ctrl3.st_sign_y = 0; + wkup_dur.st_sign_z = 1; + break; - case LIS2DUX12_XL_ST_DISABLE: - default: - ret = -1; - break; + case LIS2DUX12_XL_ST_DISABLE: + default: + ret = -1; + break; } - ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL3, (uint8_t*)&ctrl3, 1); - ret += lis2dux12_write_reg(ctx, LIS2DUX12_WAKE_UP_DUR, (uint8_t*)&wkup_dur, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_CTRL3, (uint8_t *)&ctrl3, 1); + ret += lis2dux12_write_reg(ctx, LIS2DUX12_WAKE_UP_DUR, (uint8_t *)&wkup_dur, 1); return ret; } @@ -735,19 +873,21 @@ int32_t lis2dux12_self_test_sign_set(stmdev_ctx_t *ctx, lis2dux12_xl_self_test_t * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_self_test_start(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dux12_self_test_start(const stmdev_ctx_t *ctx, uint8_t val) { lis2dux12_self_test_t self_test; int32_t ret; - if (val != 1U && val != 2U) { + if (val != 1U && val != 2U) + { return -1; } - ret = lis2dux12_read_reg(ctx, LIS2DUX12_SELF_TEST, (uint8_t*)&self_test, 1); - if (ret == 0) { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_SELF_TEST, (uint8_t *)&self_test, 1); + if (ret == 0) + { self_test.st = (uint8_t) val; - ret = lis2dux12_write_reg(ctx, LIS2DUX12_SELF_TEST, (uint8_t*)&self_test, 1); + ret = lis2dux12_write_reg(ctx, LIS2DUX12_SELF_TEST, (uint8_t *)&self_test, 1); } return ret; } @@ -759,15 +899,16 @@ int32_t lis2dux12_self_test_start(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_self_test_stop(stmdev_ctx_t *ctx) +int32_t lis2dux12_self_test_stop(const stmdev_ctx_t *ctx) { lis2dux12_self_test_t self_test; int32_t ret; - ret = lis2dux12_read_reg(ctx, LIS2DUX12_SELF_TEST, (uint8_t*)&self_test, 1); - if (ret == 0) { + ret = lis2dux12_read_reg(ctx, LIS2DUX12_SELF_TEST, (uint8_t *)&self_test, 1); + if (ret == 0) + { self_test.st = 0; - ret = lis2dux12_write_reg(ctx, LIS2DUX12_SELF_TEST, (uint8_t*)&self_test, 1); + ret = lis2dux12_write_reg(ctx, LIS2DUX12_SELF_TEST, (uint8_t *)&self_test, 1); } return ret; } @@ -780,7 +921,7 @@ int32_t lis2dux12_self_test_stop(stmdev_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_i3c_configure_set(stmdev_ctx_t *ctx, lis2dux12_i3c_cfg_t *val) +int32_t lis2dux12_i3c_configure_set(const stmdev_ctx_t *ctx, const lis2dux12_i3c_cfg_t *val) { lis2dux12_i3c_if_ctrl_t i3c_cfg; int32_t ret; @@ -805,7 +946,7 @@ int32_t lis2dux12_i3c_configure_set(stmdev_ctx_t *ctx, lis2dux12_i3c_cfg_t *val) * @param val configuration params * @retval interface status (MANDATORY: return 0 -> no Error) * - */int32_t lis2dux12_i3c_configure_get(stmdev_ctx_t *ctx, lis2dux12_i3c_cfg_t *val) + */int32_t lis2dux12_i3c_configure_get(const stmdev_ctx_t *ctx, lis2dux12_i3c_cfg_t *val) { lis2dux12_i3c_if_ctrl_t i3c_cfg; int32_t ret; @@ -815,26 +956,27 @@ int32_t lis2dux12_i3c_configure_set(stmdev_ctx_t *ctx, lis2dux12_i3c_cfg_t *val) val->drstdaa_en = i3c_cfg.dis_drstdaa; val->asf_on = i3c_cfg.asf_on; - switch (val->bus_act_sel) { + switch (val->bus_act_sel) + { case LIS2DUX12_I3C_BUS_AVAIL_TIME_20US: - val->bus_act_sel = LIS2DUX12_I3C_BUS_AVAIL_TIME_20US; - break; + val->bus_act_sel = LIS2DUX12_I3C_BUS_AVAIL_TIME_20US; + break; case LIS2DUX12_I3C_BUS_AVAIL_TIME_50US: - val->bus_act_sel = LIS2DUX12_I3C_BUS_AVAIL_TIME_50US; - break; + val->bus_act_sel = LIS2DUX12_I3C_BUS_AVAIL_TIME_50US; + break; case LIS2DUX12_I3C_BUS_AVAIL_TIME_1MS: - val->bus_act_sel = LIS2DUX12_I3C_BUS_AVAIL_TIME_1MS; - break; + val->bus_act_sel = LIS2DUX12_I3C_BUS_AVAIL_TIME_1MS; + break; case LIS2DUX12_I3C_BUS_AVAIL_TIME_25MS: default: - val->bus_act_sel = LIS2DUX12_I3C_BUS_AVAIL_TIME_25MS; - break; + val->bus_act_sel = LIS2DUX12_I3C_BUS_AVAIL_TIME_25MS; + break; } - return ret; + return ret; } /** @@ -845,7 +987,7 @@ int32_t lis2dux12_i3c_configure_set(stmdev_ctx_t *ctx, lis2dux12_i3c_cfg_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_mem_bank_set(stmdev_ctx_t *ctx, lis2dux12_mem_bank_t val) +int32_t lis2dux12_mem_bank_set(const stmdev_ctx_t *ctx, lis2dux12_mem_bank_t val) { lis2dux12_func_cfg_access_t func_cfg_access; int32_t ret; @@ -869,7 +1011,7 @@ int32_t lis2dux12_mem_bank_set(stmdev_ctx_t *ctx, lis2dux12_mem_bank_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_mem_bank_get(stmdev_ctx_t *ctx, lis2dux12_mem_bank_t *val) +int32_t lis2dux12_mem_bank_get(const stmdev_ctx_t *ctx, lis2dux12_mem_bank_t *val) { lis2dux12_func_cfg_access_t func_cfg_access; int32_t ret; @@ -878,11 +1020,11 @@ int32_t lis2dux12_mem_bank_get(stmdev_ctx_t *ctx, lis2dux12_mem_bank_t *val) switch ((func_cfg_access.emb_func_reg_access)) { - case LIS2DUX12_MAIN_MEM_BANK: + case 0x0: *val = LIS2DUX12_MAIN_MEM_BANK; break; - case LIS2DUX12_EMBED_FUNC_MEM_BANK: + case 0x1: *val = LIS2DUX12_EMBED_FUNC_MEM_BANK; break; @@ -904,7 +1046,7 @@ int32_t lis2dux12_mem_bank_get(stmdev_ctx_t *ctx, lis2dux12_mem_bank_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len) +int32_t lis2dux12_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len) { lis2dux12_page_address_t page_address; lis2dux12_page_sel_t page_sel; @@ -934,7 +1076,7 @@ int32_t lis2dux12_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, page_address.page_addr = lsb; ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_ADDRESS, (uint8_t *)&page_address, 1); - for (i = 0; ((i < len) && (ret == 0)); i++) + for (i = 0; i < len; i++) { ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_VALUE, &buf[i], 1); lsb++; @@ -948,6 +1090,11 @@ int32_t lis2dux12_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, page_sel.not_used0 = 1; // Default value ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1); } + + if (ret != 0) + { + break; + } } page_sel.page_sel = 0; @@ -976,7 +1123,7 @@ int32_t lis2dux12_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len) +int32_t lis2dux12_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len) { lis2dux12_page_address_t page_address; lis2dux12_page_sel_t page_sel; @@ -1006,7 +1153,7 @@ int32_t lis2dux12_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, page_address.page_addr = lsb; ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_ADDRESS, (uint8_t *)&page_address, 1); - for (i = 0; ((i < len) && (ret == 0)); i++) + for (i = 0; i < len; i++) { ret += lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_VALUE, &buf[i], 1); lsb++; @@ -1020,6 +1167,11 @@ int32_t lis2dux12_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, page_sel.not_used0 = 1; // Default value ret += lis2dux12_write_reg(ctx, LIS2DUX12_PAGE_SEL, (uint8_t *)&page_sel, 1); } + + if (ret != 0) + { + break; + } } page_sel.page_sel = 0; @@ -1049,6 +1201,45 @@ int32_t lis2dux12_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, * */ +/** + * @brief External Clock Enable/Disable on INT pin.[set] + * + * @param ctx read / write interface definitions + * @param val 0: disable ext_clk - 1: enable ext_clk + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_ext_clk_en_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lis2dux12_ext_clk_cfg_t clk; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_EXT_CLK_CFG, (uint8_t *)&clk, 1); + clk.ext_clk_en = val; + ret += lis2dux12_write_reg(ctx, LIS2DUX12_EXT_CLK_CFG, (uint8_t *)&clk, 1); + + return ret; +} + +/** + * @brief External Clock Enable/Disable on INT pin.[get] + * + * @param ctx read / write interface definitions + * @param val 0: disable ext_clk - 1: enable ext_clk + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2dux12_ext_clk_en_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lis2dux12_ext_clk_cfg_t clk; + int32_t ret; + + ret = lis2dux12_read_reg(ctx, LIS2DUX12_EXT_CLK_CFG, (uint8_t *)&clk, 1); + *val = clk.ext_clk_en; + + return ret; +} + /** * @brief Electrical pin configuration.[set] * @@ -1057,7 +1248,7 @@ int32_t lis2dux12_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_pin_conf_set(stmdev_ctx_t *ctx, lis2dux12_pin_conf_t *val) +int32_t lis2dux12_pin_conf_set(const stmdev_ctx_t *ctx, const lis2dux12_pin_conf_t *val) { lis2dux12_pin_ctrl_t pin_ctrl; int32_t ret; @@ -1087,7 +1278,7 @@ int32_t lis2dux12_pin_conf_set(stmdev_ctx_t *ctx, lis2dux12_pin_conf_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_pin_conf_get(stmdev_ctx_t *ctx, lis2dux12_pin_conf_t *val) +int32_t lis2dux12_pin_conf_get(const stmdev_ctx_t *ctx, lis2dux12_pin_conf_t *val) { lis2dux12_pin_ctrl_t pin_ctrl; int32_t ret; @@ -1112,7 +1303,7 @@ int32_t lis2dux12_pin_conf_get(stmdev_ctx_t *ctx, lis2dux12_pin_conf_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_int_pin_polarity_set(stmdev_ctx_t *ctx, lis2dux12_int_pin_polarity_t val) +int32_t lis2dux12_int_pin_polarity_set(const stmdev_ctx_t *ctx, lis2dux12_int_pin_polarity_t val) { lis2dux12_pin_ctrl_t pin_ctrl; int32_t ret; @@ -1136,7 +1327,7 @@ int32_t lis2dux12_int_pin_polarity_set(stmdev_ctx_t *ctx, lis2dux12_int_pin_pola * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_int_pin_polarity_get(stmdev_ctx_t *ctx, lis2dux12_int_pin_polarity_t *val) +int32_t lis2dux12_int_pin_polarity_get(const stmdev_ctx_t *ctx, lis2dux12_int_pin_polarity_t *val) { lis2dux12_pin_ctrl_t pin_ctrl; int32_t ret; @@ -1145,11 +1336,11 @@ int32_t lis2dux12_int_pin_polarity_get(stmdev_ctx_t *ctx, lis2dux12_int_pin_pola switch ((pin_ctrl.h_lactive)) { - case LIS2DUX12_ACTIVE_HIGH: + case 0x0: *val = LIS2DUX12_ACTIVE_HIGH; break; - case LIS2DUX12_ACTIVE_LOW: + case 0x1: *val = LIS2DUX12_ACTIVE_LOW; break; @@ -1168,7 +1359,7 @@ int32_t lis2dux12_int_pin_polarity_get(stmdev_ctx_t *ctx, lis2dux12_int_pin_pola * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_spi_mode_set(stmdev_ctx_t *ctx, lis2dux12_spi_mode val) +int32_t lis2dux12_spi_mode_set(const stmdev_ctx_t *ctx, lis2dux12_spi_mode val) { lis2dux12_pin_ctrl_t pin_ctrl; int32_t ret; @@ -1192,7 +1383,7 @@ int32_t lis2dux12_spi_mode_set(stmdev_ctx_t *ctx, lis2dux12_spi_mode val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_spi_mode_get(stmdev_ctx_t *ctx, lis2dux12_spi_mode *val) +int32_t lis2dux12_spi_mode_get(const stmdev_ctx_t *ctx, lis2dux12_spi_mode *val) { lis2dux12_pin_ctrl_t pin_ctrl; int32_t ret; @@ -1201,11 +1392,11 @@ int32_t lis2dux12_spi_mode_get(stmdev_ctx_t *ctx, lis2dux12_spi_mode *val) switch ((pin_ctrl.h_lactive)) { - case LIS2DUX12_SPI_4_WIRE: + case 0x0: *val = LIS2DUX12_SPI_4_WIRE; break; - case LIS2DUX12_SPI_3_WIRE: + case 0x1: *val = LIS2DUX12_SPI_3_WIRE; break; @@ -1224,7 +1415,7 @@ int32_t lis2dux12_spi_mode_get(stmdev_ctx_t *ctx, lis2dux12_spi_mode *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_pin_int1_route_set(stmdev_ctx_t *ctx, lis2dux12_pin_int_route_t *val) +int32_t lis2dux12_pin_int1_route_set(const stmdev_ctx_t *ctx, const lis2dux12_pin_int_route_t *val) { lis2dux12_ctrl1_t ctrl1; lis2dux12_ctrl2_t ctrl2; @@ -1285,7 +1476,7 @@ int32_t lis2dux12_pin_int1_route_set(stmdev_ctx_t *ctx, lis2dux12_pin_int_route_ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_pin_int1_route_get(stmdev_ctx_t *ctx, lis2dux12_pin_int_route_t *val) +int32_t lis2dux12_pin_int1_route_get(const stmdev_ctx_t *ctx, lis2dux12_pin_int_route_t *val) { lis2dux12_ctrl1_t ctrl1; lis2dux12_ctrl2_t ctrl2; @@ -1324,8 +1515,8 @@ int32_t lis2dux12_pin_int1_route_get(stmdev_ctx_t *ctx, lis2dux12_pin_int_route_ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_emb_pin_int1_route_set(stmdev_ctx_t *ctx, - lis2dux12_emb_pin_int_route_t *val) +int32_t lis2dux12_emb_pin_int1_route_set(const stmdev_ctx_t *ctx, + const lis2dux12_emb_pin_int_route_t *val) { lis2dux12_emb_func_int1_t emb_func_int1; lis2dux12_md1_cfg_t md1_cfg; @@ -1366,8 +1557,8 @@ int32_t lis2dux12_emb_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_emb_pin_int1_route_get(stmdev_ctx_t *ctx, - lis2dux12_emb_pin_int_route_t *val) +int32_t lis2dux12_emb_pin_int1_route_get(const stmdev_ctx_t *ctx, + lis2dux12_emb_pin_int_route_t *val) { lis2dux12_emb_func_int1_t emb_func_int1; int32_t ret; @@ -1398,7 +1589,7 @@ int32_t lis2dux12_emb_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_pin_int2_route_set(stmdev_ctx_t *ctx, lis2dux12_pin_int_route_t *val) +int32_t lis2dux12_pin_int2_route_set(const stmdev_ctx_t *ctx, const lis2dux12_pin_int_route_t *val) { lis2dux12_ctrl3_t ctrl3; lis2dux12_md2_cfg_t md2_cfg; @@ -1446,7 +1637,7 @@ int32_t lis2dux12_pin_int2_route_set(stmdev_ctx_t *ctx, lis2dux12_pin_int_route_ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_pin_int2_route_get(stmdev_ctx_t *ctx, lis2dux12_pin_int_route_t *val) +int32_t lis2dux12_pin_int2_route_get(const stmdev_ctx_t *ctx, lis2dux12_pin_int_route_t *val) { lis2dux12_ctrl3_t ctrl3; lis2dux12_md2_cfg_t md2_cfg; @@ -1482,8 +1673,8 @@ int32_t lis2dux12_pin_int2_route_get(stmdev_ctx_t *ctx, lis2dux12_pin_int_route_ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_emb_pin_int2_route_set(stmdev_ctx_t *ctx, - lis2dux12_emb_pin_int_route_t *val) +int32_t lis2dux12_emb_pin_int2_route_set(const stmdev_ctx_t *ctx, + const lis2dux12_emb_pin_int_route_t *val) { lis2dux12_emb_func_int2_t emb_func_int2; lis2dux12_md2_cfg_t md2_cfg; @@ -1524,8 +1715,8 @@ int32_t lis2dux12_emb_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_emb_pin_int2_route_get(stmdev_ctx_t *ctx, - lis2dux12_emb_pin_int_route_t *val) +int32_t lis2dux12_emb_pin_int2_route_get(const stmdev_ctx_t *ctx, + lis2dux12_emb_pin_int_route_t *val) { lis2dux12_emb_func_int2_t emb_func_int2; int32_t ret; @@ -1556,7 +1747,7 @@ int32_t lis2dux12_emb_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_int_config_set(stmdev_ctx_t *ctx, lis2dux12_int_config_t *val) +int32_t lis2dux12_int_config_set(const stmdev_ctx_t *ctx, const lis2dux12_int_config_t *val) { lis2dux12_interrupt_cfg_t interrupt_cfg; int32_t ret; @@ -1600,7 +1791,7 @@ int32_t lis2dux12_int_config_set(stmdev_ctx_t *ctx, lis2dux12_int_config_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_int_config_get(stmdev_ctx_t *ctx, lis2dux12_int_config_t *val) +int32_t lis2dux12_int_config_get(const stmdev_ctx_t *ctx, lis2dux12_int_config_t *val) { lis2dux12_interrupt_cfg_t interrupt_cfg; int32_t ret; @@ -1637,7 +1828,7 @@ int32_t lis2dux12_int_config_get(stmdev_ctx_t *ctx, lis2dux12_int_config_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_embedded_int_config_set(stmdev_ctx_t *ctx, lis2dux12_embedded_int_config_t val) +int32_t lis2dux12_embedded_int_cfg_set(const stmdev_ctx_t *ctx, lis2dux12_embedded_int_config_t val) { lis2dux12_page_rw_t page_rw; int32_t ret; @@ -1675,7 +1866,8 @@ int32_t lis2dux12_embedded_int_config_set(stmdev_ctx_t *ctx, lis2dux12_embedded_ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_embedded_int_config_get(stmdev_ctx_t *ctx, lis2dux12_embedded_int_config_t *val) +int32_t lis2dux12_embedded_int_cfg_get(const stmdev_ctx_t *ctx, + lis2dux12_embedded_int_config_t *val) { lis2dux12_page_rw_t page_rw; int32_t ret; @@ -1685,9 +1877,12 @@ int32_t lis2dux12_embedded_int_config_get(stmdev_ctx_t *ctx, lis2dux12_embedded_ { ret = lis2dux12_read_reg(ctx, LIS2DUX12_PAGE_RW, (uint8_t *)&page_rw, 1); - if (page_rw.emb_func_lir == 0U) { + if (page_rw.emb_func_lir == 0U) + { *val = LIS2DUX12_EMBEDDED_INT_LEVEL; - } else { + } + else + { *val = LIS2DUX12_EMBEDDED_INT_LATCHED; } } @@ -1717,7 +1912,7 @@ int32_t lis2dux12_embedded_int_config_get(stmdev_ctx_t *ctx, lis2dux12_embedded_ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_fifo_mode_set(stmdev_ctx_t *ctx, lis2dux12_fifo_mode_t val) +int32_t lis2dux12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2dux12_fifo_mode_t val) { lis2dux12_ctrl4_t ctrl4; lis2dux12_fifo_ctrl_t fifo_ctrl; @@ -1738,7 +1933,8 @@ int32_t lis2dux12_fifo_mode_set(stmdev_ctx_t *ctx, lis2dux12_fifo_mode_t val) ctrl4.fifo_en = 1; fifo_ctrl.fifo_mode = ((uint8_t)val.operation & 0x7U); } - else { + else + { ctrl4.fifo_en = 0; } @@ -1758,7 +1954,8 @@ int32_t lis2dux12_fifo_mode_set(stmdev_ctx_t *ctx, lis2dux12_fifo_mode_t val) fifo_ctrl.cfg_chg_en = val.cfg_change_in_fifo; /* set watermark */ - if (val.watermark > 0U) { + if (val.watermark > 0U) + { fifo_ctrl.stop_on_fth = 1; fifo_wtm.fth = val.watermark; } @@ -1780,7 +1977,7 @@ int32_t lis2dux12_fifo_mode_set(stmdev_ctx_t *ctx, lis2dux12_fifo_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_fifo_mode_get(stmdev_ctx_t *ctx, lis2dux12_fifo_mode_t *val) +int32_t lis2dux12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2dux12_fifo_mode_t *val) { lis2dux12_ctrl4_t ctrl4; lis2dux12_fifo_ctrl_t fifo_ctrl; @@ -1796,10 +1993,12 @@ int32_t lis2dux12_fifo_mode_get(stmdev_ctx_t *ctx, lis2dux12_fifo_mode_t *val) if (ret == 0) { /* get FIFO mode */ - if (ctrl4.fifo_en == 0U) { + if (ctrl4.fifo_en == 0U) + { val->operation = LIS2DUX12_FIFO_OFF; } - else { + else + { val->operation = (lis2dux12_operation_t)fifo_ctrl.fifo_mode; } val->cfg_change_in_fifo = fifo_ctrl.cfg_chg_en; @@ -1829,7 +2028,7 @@ int32_t lis2dux12_fifo_mode_get(stmdev_ctx_t *ctx, lis2dux12_fifo_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lis2dux12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff; int32_t ret; @@ -1841,7 +2040,7 @@ int32_t lis2dux12_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) return ret; } -int32_t lis2dux12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dux12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dux12_fifo_status1_t fifo_status1; int32_t ret; @@ -1853,7 +2052,7 @@ int32_t lis2dux12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) return ret; } -int32_t lis2dux12_fifo_sensor_tag_get(stmdev_ctx_t *ctx, lis2dux12_fifo_sensor_tag_t *val) +int32_t lis2dux12_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, lis2dux12_fifo_sensor_tag_t *val) { lis2dux12_fifo_data_out_tag_t fifo_tag; int32_t ret; @@ -1865,7 +2064,7 @@ int32_t lis2dux12_fifo_sensor_tag_get(stmdev_ctx_t *ctx, lis2dux12_fifo_sensor_t return ret; } -int32_t lis2dux12_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis2dux12_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1874,9 +2073,9 @@ int32_t lis2dux12_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) return ret; } -int32_t lis2dux12_fifo_data_get(stmdev_ctx_t *ctx, lis2dux12_md_t *md, - lis2dux12_fifo_mode_t *fmd, - lis2dux12_fifo_data_t *data) +int32_t lis2dux12_fifo_data_get(const stmdev_ctx_t *ctx, const lis2dux12_md_t *md, + const lis2dux12_fifo_mode_t *fmd, + lis2dux12_fifo_data_t *data) { lis2dux12_fifo_data_out_tag_t fifo_tag; uint8_t fifo_raw[6]; @@ -1885,18 +2084,21 @@ int32_t lis2dux12_fifo_data_get(stmdev_ctx_t *ctx, lis2dux12_md_t *md, ret = lis2dux12_read_reg(ctx, LIS2DUX12_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_tag, 1); data->tag = fifo_tag.tag_sensor; - switch (fifo_tag.tag_sensor) { - case LIS2DUX12_XL_ONLY_2X_TAG: + switch (fifo_tag.tag_sensor) + { + case 0x3: /* A FIFO sample consists of 2X 8-bits 3-axis XL at ODR/2 */ ret = lis2dux12_fifo_out_raw_get(ctx, fifo_raw); - for (i = 0; i < 3; i++) { + for (i = 0; i < 3; i++) + { data->xl[0].raw[i] = (int16_t)fifo_raw[i] * 256; data->xl[1].raw[i] = (int16_t)fifo_raw[3 + i] * 256; } break; - case LIS2DUX12_XL_TEMP_TAG: + case 0x2: ret = lis2dux12_fifo_out_raw_get(ctx, fifo_raw); - if (fmd->xl_only == 0x0U) { + if (fmd->xl_only == 0x0U) + { /* A FIFO sample consists of 12-bits 3-axis XL + T at ODR*/ data->xl[0].raw[0] = (int16_t)fifo_raw[0]; data->xl[0].raw[0] = (data->xl[0].raw[0] + (int16_t)fifo_raw[1] * 256) * 16; @@ -1907,65 +2109,70 @@ int32_t lis2dux12_fifo_data_get(stmdev_ctx_t *ctx, lis2dux12_md_t *md, data->heat.raw = (int16_t)fifo_raw[4] / 16; data->heat.raw = (data->heat.raw + ((int16_t)fifo_raw[5] * 16)) * 16; data->heat.deg_c = lis2dux12_from_lsb_to_celsius(data->heat.raw); - } else { + } + else + { /* A FIFO sample consists of 16-bits 3-axis XL at ODR */ data->xl[0].raw[0] = (int16_t)fifo_raw[0] + (int16_t)fifo_raw[1] * 256; data->xl[0].raw[1] = (int16_t)fifo_raw[1] + (int16_t)fifo_raw[3] * 256; data->xl[0].raw[2] = (int16_t)fifo_raw[2] + (int16_t)fifo_raw[5] * 256; } break; - case LIS2DUX12_TIMESTAMP_TAG: - ret = lis2dux12_fifo_out_raw_get(ctx, fifo_raw); + case 0x4: + ret = lis2dux12_fifo_out_raw_get(ctx, fifo_raw); - data->cfg_chg.cfg_change = fifo_raw[0] >> 7; - data->cfg_chg.odr = (fifo_raw[0] >> 3) & 0xFU; - data->cfg_chg.bw = (fifo_raw[0] >> 1) & 0x3U; - data->cfg_chg.lp_hp = fifo_raw[0] & 0x1U; - data->cfg_chg.fs = (fifo_raw[1] >> 5) & 0x3U; - data->cfg_chg.dec_ts = (fifo_raw[1] >> 3) & 0x3U; - data->cfg_chg.odr_xl_batch = fifo_raw[1] & 0x7U; + data->cfg_chg.cfg_change = fifo_raw[0] >> 7; + data->cfg_chg.odr = (fifo_raw[0] >> 3) & 0xFU; + data->cfg_chg.bw = (fifo_raw[0] >> 1) & 0x3U; + data->cfg_chg.lp_hp = fifo_raw[0] & 0x1U; + data->cfg_chg.fs = (fifo_raw[1] >> 5) & 0x3U; + data->cfg_chg.dec_ts = (fifo_raw[1] >> 3) & 0x3U; + data->cfg_chg.odr_xl_batch = fifo_raw[1] & 0x7U; - data->cfg_chg.timestamp = fifo_raw[5]; - data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[4]; - data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[3]; - data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[2]; - break; + data->cfg_chg.timestamp = fifo_raw[5]; + data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[4]; + data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[3]; + data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[2]; + break; - case LIS2DUX12_STEP_COUNTER_TAG: - ret = lis2dux12_fifo_out_raw_get(ctx, fifo_raw); + case 0x12: + ret = lis2dux12_fifo_out_raw_get(ctx, fifo_raw); - data->pedo.steps = fifo_raw[1]; - data->pedo.steps = (data->pedo.steps * 256U) + fifo_raw[0]; + data->pedo.steps = fifo_raw[1]; + data->pedo.steps = (data->pedo.steps * 256U) + fifo_raw[0]; - data->pedo.timestamp = fifo_raw[5]; - data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[4]; - data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[3]; - data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[2]; + data->pedo.timestamp = fifo_raw[5]; + data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[4]; + data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[3]; + data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[2]; - break; + break; - case LIS2DUX12_FIFO_EMPTY: - default: - break; + case 0x0: + default: + /* do nothing */ + break; } - for (i = 0; i < 3; i++) { - switch ( md->fs ) { + for (i = 0; i < 3; i++) + { + switch (md->fs) + { case LIS2DUX12_2g: - data->xl[0].mg[i] =lis2dux12_from_fs2g_to_mg(data->xl[0].raw[i]); - data->xl[1].mg[i] =lis2dux12_from_fs2g_to_mg(data->xl[1].raw[i]); + data->xl[0].mg[i] = lis2dux12_from_fs2g_to_mg(data->xl[0].raw[i]); + data->xl[1].mg[i] = lis2dux12_from_fs2g_to_mg(data->xl[1].raw[i]); break; case LIS2DUX12_4g: - data->xl[0].mg[i] =lis2dux12_from_fs4g_to_mg(data->xl[0].raw[i]); - data->xl[1].mg[i] =lis2dux12_from_fs4g_to_mg(data->xl[1].raw[i]); + data->xl[0].mg[i] = lis2dux12_from_fs4g_to_mg(data->xl[0].raw[i]); + data->xl[1].mg[i] = lis2dux12_from_fs4g_to_mg(data->xl[1].raw[i]); break; case LIS2DUX12_8g: - data->xl[0].mg[i] =lis2dux12_from_fs8g_to_mg(data->xl[0].raw[i]); - data->xl[1].mg[i] =lis2dux12_from_fs8g_to_mg(data->xl[1].raw[i]); + data->xl[0].mg[i] = lis2dux12_from_fs8g_to_mg(data->xl[0].raw[i]); + data->xl[1].mg[i] = lis2dux12_from_fs8g_to_mg(data->xl[1].raw[i]); break; case LIS2DUX12_16g: - data->xl[0].mg[i] =lis2dux12_from_fs16g_to_mg(data->xl[0].raw[i]); - data->xl[1].mg[i] =lis2dux12_from_fs16g_to_mg(data->xl[1].raw[i]); + data->xl[0].mg[i] = lis2dux12_from_fs16g_to_mg(data->xl[0].raw[i]); + data->xl[1].mg[i] = lis2dux12_from_fs16g_to_mg(data->xl[1].raw[i]); break; default: data->xl[0].mg[i] = 0.0f; @@ -1991,7 +2198,7 @@ int32_t lis2dux12_fifo_data_get(stmdev_ctx_t *ctx, lis2dux12_md_t *md, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_stpcnt_mode_set(stmdev_ctx_t *ctx, lis2dux12_stpcnt_mode_t val) +int32_t lis2dux12_stpcnt_mode_set(const stmdev_ctx_t *ctx, lis2dux12_stpcnt_mode_t val) { lis2dux12_emb_func_en_a_t emb_func_en_a; lis2dux12_emb_func_en_b_t emb_func_en_b; @@ -2004,7 +2211,8 @@ int32_t lis2dux12_stpcnt_mode_set(stmdev_ctx_t *ctx, lis2dux12_stpcnt_mode_t val ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_FIFO_EN, (uint8_t *)&emb_func_fifo_en, 1); - if ((val.false_step_rej == PROPERTY_ENABLE) && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) == PROPERTY_DISABLE)) + if ((val.false_step_rej == PROPERTY_ENABLE) + && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) == PROPERTY_DISABLE)) { emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE; } @@ -2016,12 +2224,14 @@ int32_t lis2dux12_stpcnt_mode_set(stmdev_ctx_t *ctx, lis2dux12_stpcnt_mode_t val ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); - ret += lis2dux12_ln_pg_read(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + ret += lis2dux12_ln_pg_read(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_CMD_REG, + (uint8_t *)&pedo_cmd_reg, 1); if (ret == 0) { pedo_cmd_reg.fp_rejection_en = val.false_step_rej; - ret += lis2dux12_ln_pg_write(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + ret += lis2dux12_ln_pg_write(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_CMD_REG, + (uint8_t *)&pedo_cmd_reg, 1); } return ret; @@ -2035,7 +2245,7 @@ int32_t lis2dux12_stpcnt_mode_set(stmdev_ctx_t *ctx, lis2dux12_stpcnt_mode_t val * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_stpcnt_mode_get(stmdev_ctx_t *ctx, lis2dux12_stpcnt_mode_t *val) +int32_t lis2dux12_stpcnt_mode_get(const stmdev_ctx_t *ctx, lis2dux12_stpcnt_mode_t *val) { lis2dux12_emb_func_en_a_t emb_func_en_a; lis2dux12_pedo_cmd_reg_t pedo_cmd_reg; @@ -2045,7 +2255,8 @@ int32_t lis2dux12_stpcnt_mode_get(stmdev_ctx_t *ctx, lis2dux12_stpcnt_mode_t *va ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); - ret += lis2dux12_ln_pg_read(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + ret += lis2dux12_ln_pg_read(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_CMD_REG, + (uint8_t *)&pedo_cmd_reg, 1); val->false_step_rej = pedo_cmd_reg.fp_rejection_en; val->step_counter_enable = emb_func_en_a.pedo_en; @@ -2060,7 +2271,7 @@ int32_t lis2dux12_stpcnt_mode_get(stmdev_ctx_t *ctx, lis2dux12_stpcnt_mode_t *va * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lis2dux12_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -2083,7 +2294,7 @@ int32_t lis2dux12_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_stpcnt_rst_step_set(stmdev_ctx_t *ctx) +int32_t lis2dux12_stpcnt_rst_step_set(const stmdev_ctx_t *ctx) { lis2dux12_emb_func_src_t emb_func_src; int32_t ret; @@ -2109,13 +2320,14 @@ int32_t lis2dux12_stpcnt_rst_step_set(stmdev_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dux12_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dux12_pedo_deb_steps_conf_t pedo_deb_steps_conf; int32_t ret; pedo_deb_steps_conf.deb_step = val; - ret = lis2dux12_ln_pg_write(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + ret = lis2dux12_ln_pg_write(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_DEB_STEPS_CONF, + (uint8_t *)&pedo_deb_steps_conf, 1); return ret; } @@ -2128,12 +2340,13 @@ int32_t lis2dux12_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dux12_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dux12_pedo_deb_steps_conf_t pedo_deb_steps_conf; int32_t ret; - ret = lis2dux12_ln_pg_read(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + ret = lis2dux12_ln_pg_read(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_DEB_STEPS_CONF, + (uint8_t *)&pedo_deb_steps_conf, 1); *val = pedo_deb_steps_conf.deb_step; return ret; @@ -2147,7 +2360,7 @@ int32_t lis2dux12_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lis2dux12_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -2155,7 +2368,8 @@ int32_t lis2dux12_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val) buff[1] = (uint8_t)(val / 256U); buff[0] = (uint8_t)(val - (buff[1] * 256U)); - ret = lis2dux12_ln_pg_write(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_SC_DELTAT_L, (uint8_t *)buff, 2); + ret = lis2dux12_ln_pg_write(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_SC_DELTAT_L, + (uint8_t *)buff, 2); return ret; } @@ -2168,12 +2382,13 @@ int32_t lis2dux12_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lis2dux12_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; - ret = lis2dux12_ln_pg_read(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_SC_DELTAT_L, (uint8_t *)buff, 2); + ret = lis2dux12_ln_pg_read(ctx, LIS2DUX12_EMB_ADV_PG_0 + LIS2DUX12_PEDO_SC_DELTAT_L, + (uint8_t *)buff, 2); *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -2199,7 +2414,7 @@ int32_t lis2dux12_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dux12_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dux12_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -2225,7 +2440,7 @@ int32_t lis2dux12_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dux12_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dux12_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -2261,7 +2476,7 @@ int32_t lis2dux12_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dux12_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dux12_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -2287,7 +2502,7 @@ int32_t lis2dux12_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dux12_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dux12_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -2324,7 +2539,7 @@ int32_t lis2dux12_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_ff_duration_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dux12_ff_duration_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dux12_wake_up_dur_t wake_up_dur; lis2dux12_free_fall_t free_fall; @@ -2356,18 +2571,14 @@ int32_t lis2dux12_ff_duration_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_ff_duration_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dux12_ff_duration_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dux12_wake_up_dur_t wake_up_dur; lis2dux12_free_fall_t free_fall; int32_t ret; ret = lis2dux12_read_reg(ctx, LIS2DUX12_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); - - if (ret == 0) - { - ret = lis2dux12_read_reg(ctx, LIS2DUX12_FREE_FALL, (uint8_t *)&free_fall, 1); - } + ret += lis2dux12_read_reg(ctx, LIS2DUX12_FREE_FALL, (uint8_t *)&free_fall, 1); *val = (wake_up_dur.ff_dur << 5) | free_fall.ff_dur; @@ -2382,7 +2593,7 @@ int32_t lis2dux12_ff_duration_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_ff_thresholds_set(stmdev_ctx_t *ctx, lis2dux12_ff_thresholds_t val) +int32_t lis2dux12_ff_thresholds_set(const stmdev_ctx_t *ctx, lis2dux12_ff_thresholds_t val) { lis2dux12_free_fall_t free_fall; int32_t ret; @@ -2402,7 +2613,7 @@ int32_t lis2dux12_ff_thresholds_set(stmdev_ctx_t *ctx, lis2dux12_ff_thresholds_t * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_ff_thresholds_get(stmdev_ctx_t *ctx, lis2dux12_ff_thresholds_t *val) +int32_t lis2dux12_ff_thresholds_get(const stmdev_ctx_t *ctx, lis2dux12_ff_thresholds_t *val) { lis2dux12_free_fall_t free_fall; int32_t ret; @@ -2411,35 +2622,35 @@ int32_t lis2dux12_ff_thresholds_get(stmdev_ctx_t *ctx, lis2dux12_ff_thresholds_t switch (free_fall.ff_ths) { - case LIS2DUX12_156_mg: + case 0x0: *val = LIS2DUX12_156_mg; break; - case LIS2DUX12_219_mg: + case 0x1: *val = LIS2DUX12_219_mg; break; - case LIS2DUX12_250_mg: + case 0x2: *val = LIS2DUX12_250_mg; break; - case LIS2DUX12_312_mg: + case 0x3: *val = LIS2DUX12_312_mg; break; - case LIS2DUX12_344_mg: + case 0x4: *val = LIS2DUX12_344_mg; break; - case LIS2DUX12_406_mg: + case 0x5: *val = LIS2DUX12_406_mg; break; - case LIS2DUX12_469_mg: + case 0x6: *val = LIS2DUX12_469_mg; break; - case LIS2DUX12_500_mg: + case 0x7: *val = LIS2DUX12_500_mg; break; @@ -2470,7 +2681,7 @@ int32_t lis2dux12_ff_thresholds_get(stmdev_ctx_t *ctx, lis2dux12_ff_thresholds_t * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_sixd_config_set(stmdev_ctx_t *ctx, lis2dux12_sixd_config_t val) +int32_t lis2dux12_sixd_config_set(const stmdev_ctx_t *ctx, lis2dux12_sixd_config_t val) { lis2dux12_sixd_t sixd; int32_t ret; @@ -2479,7 +2690,7 @@ int32_t lis2dux12_sixd_config_set(stmdev_ctx_t *ctx, lis2dux12_sixd_config_t val if (ret == 0) { - sixd.d4d_en = ((uint8_t)val.mode); + sixd.d4d_en = ((uint8_t)val.mode); sixd.d6d_ths = ((uint8_t)val.threshold); ret = lis2dux12_write_reg(ctx, LIS2DUX12_SIXD, (uint8_t *)&sixd, 1); } @@ -2495,7 +2706,7 @@ int32_t lis2dux12_sixd_config_set(stmdev_ctx_t *ctx, lis2dux12_sixd_config_t val * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_sixd_config_get(stmdev_ctx_t *ctx, lis2dux12_sixd_config_t *val) +int32_t lis2dux12_sixd_config_get(const stmdev_ctx_t *ctx, lis2dux12_sixd_config_t *val) { lis2dux12_sixd_t sixd; int32_t ret; @@ -2506,19 +2717,19 @@ int32_t lis2dux12_sixd_config_get(stmdev_ctx_t *ctx, lis2dux12_sixd_config_t *va switch ((sixd.d6d_ths)) { - case LIS2DUX12_DEG_80: + case 0x0: val->threshold = LIS2DUX12_DEG_80; break; - case LIS2DUX12_DEG_70: + case 0x1: val->threshold = LIS2DUX12_DEG_70; break; - case LIS2DUX12_DEG_60: + case 0x2: val->threshold = LIS2DUX12_DEG_60; break; - case LIS2DUX12_DEG_50: + case 0x3: val->threshold = LIS2DUX12_DEG_50; break; @@ -2550,7 +2761,7 @@ int32_t lis2dux12_sixd_config_get(stmdev_ctx_t *ctx, lis2dux12_sixd_config_t *va * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_wakeup_config_set(stmdev_ctx_t *ctx, lis2dux12_wakeup_config_t val) +int32_t lis2dux12_wakeup_config_set(const stmdev_ctx_t *ctx, lis2dux12_wakeup_config_t val) { lis2dux12_wake_up_ths_t wup_ths; lis2dux12_wake_up_dur_t wup_dur; @@ -2578,11 +2789,14 @@ int32_t lis2dux12_wakeup_config_set(stmdev_ctx_t *ctx, lis2dux12_wakeup_config_t wup_ths.sleep_on = (uint8_t)val.wake_enable; ctrl4.inact_odr = (uint8_t)val.inact_odr; - if (val.wake_enable == LIS2DUX12_SLEEP_ON) { + if (val.wake_enable == LIS2DUX12_SLEEP_ON) + { ctrl1.wu_x_en = 1; ctrl1.wu_y_en = 1; ctrl1.wu_z_en = 1; - } else { + } + else + { ctrl1.wu_x_en = 0; ctrl1.wu_y_en = 0; ctrl1.wu_z_en = 0; @@ -2607,7 +2821,7 @@ int32_t lis2dux12_wakeup_config_set(stmdev_ctx_t *ctx, lis2dux12_wakeup_config_t * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dux12_wakeup_config_get(stmdev_ctx_t *ctx, lis2dux12_wakeup_config_t *val) +int32_t lis2dux12_wakeup_config_get(const stmdev_ctx_t *ctx, lis2dux12_wakeup_config_t *val) { lis2dux12_wake_up_ths_t wup_ths; lis2dux12_wake_up_dur_t wup_dur; @@ -2624,26 +2838,27 @@ int32_t lis2dux12_wakeup_config_get(stmdev_ctx_t *ctx, lis2dux12_wakeup_config_t if (ret == 0) { - switch(wup_dur.wake_dur) { - case 0x0: - val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ? - LIS2DUX12_3_ODR : LIS2DUX12_0_ODR; - break; + switch (wup_dur.wake_dur) + { + case 0x0: + val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ? + LIS2DUX12_3_ODR : LIS2DUX12_0_ODR; + break; - case 0x1: - val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ? - LIS2DUX12_7_ODR : LIS2DUX12_1_ODR; - break; + case 0x1: + val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ? + LIS2DUX12_7_ODR : LIS2DUX12_1_ODR; + break; - case 0x2: - val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ? - LIS2DUX12_11_ODR : LIS2DUX12_2_ODR; - break; + case 0x2: + val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ? + LIS2DUX12_11_ODR : LIS2DUX12_2_ODR; + break; - case 0x3: - default: - val->wake_dur = LIS2DUX12_15_ODR; - break; + case 0x3: + default: + val->wake_dur = LIS2DUX12_15_ODR; + break; } val->sleep_dur = wup_dur.sleep_dur; @@ -2662,7 +2877,7 @@ int32_t lis2dux12_wakeup_config_get(stmdev_ctx_t *ctx, lis2dux12_wakeup_config_t * */ -int32_t lis2dux12_tap_config_set(stmdev_ctx_t *ctx, lis2dux12_tap_config_t val) +int32_t lis2dux12_tap_config_set(const stmdev_ctx_t *ctx, lis2dux12_tap_config_t val) { lis2dux12_tap_cfg0_t tap_cfg0; lis2dux12_tap_cfg1_t tap_cfg1; @@ -2712,7 +2927,7 @@ int32_t lis2dux12_tap_config_set(stmdev_ctx_t *ctx, lis2dux12_tap_config_t val) return ret; } -int32_t lis2dux12_tap_config_get(stmdev_ctx_t *ctx, lis2dux12_tap_config_t *val) +int32_t lis2dux12_tap_config_get(const stmdev_ctx_t *ctx, lis2dux12_tap_config_t *val) { lis2dux12_tap_cfg0_t tap_cfg0; lis2dux12_tap_cfg1_t tap_cfg1; @@ -2774,7 +2989,7 @@ int32_t lis2dux12_tap_config_get(stmdev_ctx_t *ctx, lis2dux12_tap_config_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2dux12_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dux12_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dux12_interrupt_cfg_t int_cfg; int32_t ret; @@ -2798,7 +3013,7 @@ int32_t lis2dux12_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2dux12_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dux12_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dux12_interrupt_cfg_t int_cfg; int32_t ret; @@ -2819,7 +3034,7 @@ int32_t lis2dux12_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2dux12_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t lis2dux12_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; @@ -2855,8 +3070,8 @@ int32_t lis2dux12_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2dux12_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, - uint8_t *val) +int32_t lis2dux12_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, + uint8_t *val) { lis2dux12_emb_func_status_t emb_func_status; int32_t ret; @@ -2866,7 +3081,7 @@ int32_t lis2dux12_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, if (ret == 0) { ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_STATUS, - (uint8_t *)&emb_func_status, 1); + (uint8_t *)&emb_func_status, 1); *val = emb_func_status.is_fsm_lc; } @@ -2884,7 +3099,7 @@ int32_t lis2dux12_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2dux12_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dux12_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; @@ -2894,7 +3109,7 @@ int32_t lis2dux12_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val) if (ret == 0) { ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); + (uint8_t *)&emb_func_en_b, 1); emb_func_en_b.fsm_en = (uint8_t)val; @@ -2915,7 +3130,7 @@ int32_t lis2dux12_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2dux12_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dux12_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -2925,12 +3140,12 @@ int32_t lis2dux12_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); + (uint8_t *)&emb_func_en_b, 1); *val = emb_func_en_b.fsm_en; ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); + (uint8_t *)&emb_func_en_b, 1); } ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); @@ -2946,8 +3161,8 @@ int32_t lis2dux12_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2dux12_fsm_enable_set(stmdev_ctx_t *ctx, - lis2dux12_emb_fsm_enable_t *val) +int32_t lis2dux12_fsm_enable_set(const stmdev_ctx_t *ctx, + lis2dux12_emb_fsm_enable_t *val) { lis2dux12_emb_func_en_b_t emb_func_en_b; int32_t ret; @@ -2957,13 +3172,13 @@ int32_t lis2dux12_fsm_enable_set(stmdev_ctx_t *ctx, if (ret == 0) { ret = lis2dux12_write_reg(ctx, LIS2DUX12_FSM_ENABLE, - (uint8_t *)&val->fsm_enable, 1); + (uint8_t *)&val->fsm_enable, 1); } if (ret == 0) { ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); + (uint8_t *)&emb_func_en_b, 1); if ((val->fsm_enable.fsm1_en | val->fsm_enable.fsm2_en | @@ -2982,7 +3197,7 @@ int32_t lis2dux12_fsm_enable_set(stmdev_ctx_t *ctx, } ret += lis2dux12_write_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); + (uint8_t *)&emb_func_en_b, 1); } ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); @@ -2998,8 +3213,8 @@ int32_t lis2dux12_fsm_enable_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2dux12_fsm_enable_get(stmdev_ctx_t *ctx, - lis2dux12_emb_fsm_enable_t *val) +int32_t lis2dux12_fsm_enable_get(const stmdev_ctx_t *ctx, + lis2dux12_emb_fsm_enable_t *val) { int32_t ret; @@ -3008,7 +3223,7 @@ int32_t lis2dux12_fsm_enable_get(stmdev_ctx_t *ctx, if (ret == 0) { ret = lis2dux12_read_reg(ctx, LIS2DUX12_FSM_ENABLE, - (uint8_t *)&val->fsm_enable, 1); + (uint8_t *)&val->fsm_enable, 1); } ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); @@ -3025,7 +3240,7 @@ int32_t lis2dux12_fsm_enable_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2dux12_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lis2dux12_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -3053,7 +3268,7 @@ int32_t lis2dux12_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2dux12_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lis2dux12_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -3079,8 +3294,8 @@ int32_t lis2dux12_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) * @param val register FSM_STATUS_MAINPAGE * */ -int32_t lis2dux12_fsm_status_get(stmdev_ctx_t *ctx, - lis2dux12_fsm_status_mainpage_t *val) +int32_t lis2dux12_fsm_status_get(const stmdev_ctx_t *ctx, + lis2dux12_fsm_status_mainpage_t *val) { return lis2dux12_read_reg(ctx, LIS2DUX12_FSM_STATUS_MAINPAGE, (uint8_t *) val, 1); @@ -3094,7 +3309,7 @@ int32_t lis2dux12_fsm_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2dux12_fsm_out_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dux12_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -3118,8 +3333,8 @@ int32_t lis2dux12_fsm_out_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2dux12_fsm_data_rate_set(stmdev_ctx_t *ctx, - lis2dux12_fsm_val_odr_t val) +int32_t lis2dux12_fsm_data_rate_set(const stmdev_ctx_t *ctx, + lis2dux12_fsm_val_odr_t val) { lis2dux12_fsm_odr_t fsm_odr_reg; int32_t ret; @@ -3129,11 +3344,11 @@ int32_t lis2dux12_fsm_data_rate_set(stmdev_ctx_t *ctx, if (ret == 0) { ret = lis2dux12_read_reg(ctx, LIS2DUX12_FSM_ODR, - (uint8_t *)&fsm_odr_reg, 1); + (uint8_t *)&fsm_odr_reg, 1); fsm_odr_reg.fsm_odr = (uint8_t)val; ret += lis2dux12_write_reg(ctx, LIS2DUX12_FSM_ODR, - (uint8_t *)&fsm_odr_reg, 1); + (uint8_t *)&fsm_odr_reg, 1); } ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); @@ -3149,49 +3364,43 @@ int32_t lis2dux12_fsm_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2dux12_fsm_data_rate_get(stmdev_ctx_t *ctx, - lis2dux12_fsm_val_odr_t *val) +int32_t lis2dux12_fsm_data_rate_get(const stmdev_ctx_t *ctx, + lis2dux12_fsm_val_odr_t *val) { lis2dux12_fsm_odr_t fsm_odr_reg; int32_t ret; ret = lis2dux12_mem_bank_set(ctx, LIS2DUX12_EMBED_FUNC_MEM_BANK); - - if (ret == 0) - { - ret = lis2dux12_read_reg(ctx, LIS2DUX12_FSM_ODR, - (uint8_t *)&fsm_odr_reg, 1); - } - + ret += lis2dux12_read_reg(ctx, LIS2DUX12_FSM_ODR, (uint8_t *)&fsm_odr_reg, 1); ret += lis2dux12_mem_bank_set(ctx, LIS2DUX12_MAIN_MEM_BANK); switch (fsm_odr_reg.fsm_odr) { - case LIS2DUX12_ODR_FSM_12Hz5: + case 0: *val = LIS2DUX12_ODR_FSM_12Hz5; break; - case LIS2DUX12_ODR_FSM_25Hz: + case 1: *val = LIS2DUX12_ODR_FSM_25Hz; break; - case LIS2DUX12_ODR_FSM_50Hz: + case 2: *val = LIS2DUX12_ODR_FSM_50Hz; break; - case LIS2DUX12_ODR_FSM_100Hz: + case 3: *val = LIS2DUX12_ODR_FSM_100Hz; break; - case LIS2DUX12_ODR_FSM_200Hz: + case 4: *val = LIS2DUX12_ODR_FSM_200Hz; break; - case LIS2DUX12_ODR_FSM_400Hz: + case 5: *val = LIS2DUX12_ODR_FSM_400Hz; break; - case LIS2DUX12_ODR_FSM_800Hz: + case 6: *val = LIS2DUX12_ODR_FSM_800Hz; break; @@ -3211,7 +3420,7 @@ int32_t lis2dux12_fsm_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2dux12_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dux12_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dux12_emb_func_init_b_t emb_func_init_b; int32_t ret; @@ -3221,7 +3430,7 @@ int32_t lis2dux12_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) if (ret == 0) { ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_INIT_B, - (uint8_t *)&emb_func_init_b, 1); + (uint8_t *)&emb_func_init_b, 1); emb_func_init_b.fsm_init = (uint8_t)val; @@ -3242,7 +3451,7 @@ int32_t lis2dux12_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2dux12_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dux12_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dux12_emb_func_init_b_t emb_func_init_b; int32_t ret; @@ -3252,7 +3461,7 @@ int32_t lis2dux12_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) if (ret == 0) { ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_INIT_B, - (uint8_t *)&emb_func_init_b, 1); + (uint8_t *)&emb_func_init_b, 1); *val = emb_func_init_b.fsm_init; } @@ -3270,7 +3479,7 @@ int32_t lis2dux12_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2dux12_fsm_fifo_en_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dux12_fsm_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dux12_emb_func_fifo_en_t fifo_reg; int32_t ret; @@ -3297,7 +3506,7 @@ int32_t lis2dux12_fsm_fifo_en_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2dux12_fsm_fifo_en_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dux12_fsm_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dux12_emb_func_fifo_en_t fifo_reg; int32_t ret; @@ -3326,8 +3535,8 @@ int32_t lis2dux12_fsm_fifo_en_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2dux12_long_cnt_int_value_set(stmdev_ctx_t *ctx, - uint16_t val) +int32_t lis2dux12_long_cnt_int_value_set(const stmdev_ctx_t *ctx, + uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -3350,8 +3559,8 @@ int32_t lis2dux12_long_cnt_int_value_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2dux12_long_cnt_int_value_get(stmdev_ctx_t *ctx, - uint16_t *val) +int32_t lis2dux12_long_cnt_int_value_get(const stmdev_ctx_t *ctx, + uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -3367,16 +3576,15 @@ int32_t lis2dux12_long_cnt_int_value_get(stmdev_ctx_t *ctx, * @brief FSM number of programs register.[set] * * @param ctx Read / write interface definitions.(ptr) - * @param buff Buffer that contains data to write + * @param val Buffer that contains data to write * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2dux12_fsm_number_of_programs_set(stmdev_ctx_t *ctx, - uint8_t *buff) +int32_t lis2dux12_fsm_programs_num_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; - ret = lis2dux12_ln_pg_write(ctx, LIS2DUX12_FSM_PROGRAMS, buff, 2); + ret = lis2dux12_ln_pg_write(ctx, LIS2DUX12_FSM_PROGRAMS, &val, 1); return ret; } @@ -3385,16 +3593,15 @@ int32_t lis2dux12_fsm_number_of_programs_set(stmdev_ctx_t *ctx, * @brief FSM number of programs register.[get] * * @param ctx Read / write interface definitions.(ptr) - * @param buff Buffer that stores data read + * @param val Buffer that stores data read * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2dux12_fsm_number_of_programs_get(stmdev_ctx_t *ctx, - uint8_t *buff) +int32_t lis2dux12_fsm_programs_num_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; - ret = lis2dux12_ln_pg_read(ctx, LIS2DUX12_FSM_PROGRAMS, buff, 2); + ret = lis2dux12_ln_pg_read(ctx, LIS2DUX12_FSM_PROGRAMS, val, 1); return ret; } @@ -3408,8 +3615,8 @@ int32_t lis2dux12_fsm_number_of_programs_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2dux12_fsm_start_address_set(stmdev_ctx_t *ctx, - uint16_t val) +int32_t lis2dux12_fsm_start_address_set(const stmdev_ctx_t *ctx, + uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -3430,8 +3637,8 @@ int32_t lis2dux12_fsm_start_address_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2dux12_fsm_start_address_get(stmdev_ctx_t *ctx, - uint16_t *val) +int32_t lis2dux12_fsm_start_address_get(const stmdev_ctx_t *ctx, + uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -3465,7 +3672,7 @@ int32_t lis2dux12_fsm_start_address_get(stmdev_ctx_t *ctx, * in EMB_FUNC_INIT_A * */ -int32_t lis2dux12_mlc_set(stmdev_ctx_t *ctx, lis2dux12_mlc_mode_t val) +int32_t lis2dux12_mlc_set(const stmdev_ctx_t *ctx, lis2dux12_mlc_mode_t val) { lis2dux12_emb_func_en_a_t emb_en_a; lis2dux12_emb_func_en_b_t emb_en_b; @@ -3478,7 +3685,7 @@ int32_t lis2dux12_mlc_set(stmdev_ctx_t *ctx, lis2dux12_mlc_mode_t val) ret = lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); ret += lis2dux12_read_reg(ctx, LIS2DUX12_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); - switch(val) + switch (val) { case LIS2DUX12_MLC_OFF: emb_en_a.mlc_before_fsm_en = 0; @@ -3493,6 +3700,7 @@ int32_t lis2dux12_mlc_set(stmdev_ctx_t *ctx, lis2dux12_mlc_mode_t val) emb_en_b.mlc_en = 0; break; default: + /* do nothing */ break; } @@ -3514,7 +3722,7 @@ int32_t lis2dux12_mlc_set(stmdev_ctx_t *ctx, lis2dux12_mlc_mode_t val) * in EMB_FUNC_INIT_A * */ -int32_t lis2dux12_mlc_get(stmdev_ctx_t *ctx, lis2dux12_mlc_mode_t *val) +int32_t lis2dux12_mlc_get(const stmdev_ctx_t *ctx, lis2dux12_mlc_mode_t *val) { lis2dux12_emb_func_en_a_t emb_en_a; lis2dux12_emb_func_en_b_t emb_en_b; @@ -3557,11 +3765,11 @@ int32_t lis2dux12_mlc_get(stmdev_ctx_t *ctx, lis2dux12_mlc_mode_t *val) * @param val register MLC_STATUS_MAINPAGE * */ -int32_t lis2dux12_mlc_status_get(stmdev_ctx_t *ctx, - lis2dux12_mlc_status_mainpage_t *val) +int32_t lis2dux12_mlc_status_get(const stmdev_ctx_t *ctx, + lis2dux12_mlc_status_mainpage_t *val) { return lis2dux12_read_reg(ctx, LIS2DUX12_MLC_STATUS_MAINPAGE, - (uint8_t *) val, 1); + (uint8_t *) val, 1); } /** @@ -3571,7 +3779,7 @@ int32_t lis2dux12_mlc_status_get(stmdev_ctx_t *ctx, * @param uint8_t * : buffer that stores data read * */ -int32_t lis2dux12_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis2dux12_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -3595,8 +3803,8 @@ int32_t lis2dux12_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff) * reg EMB_FUNC_ODR_CFG_C * */ -int32_t lis2dux12_mlc_data_rate_set(stmdev_ctx_t *ctx, - lis2dux12_mlc_odr_val_t val) +int32_t lis2dux12_mlc_data_rate_set(const stmdev_ctx_t *ctx, + lis2dux12_mlc_odr_val_t val) { lis2dux12_mlc_odr_t reg; int32_t ret; @@ -3626,8 +3834,8 @@ int32_t lis2dux12_mlc_data_rate_set(stmdev_ctx_t *ctx, * reg EMB_FUNC_ODR_CFG_C * */ -int32_t lis2dux12_mlc_data_rate_get(stmdev_ctx_t *ctx, - lis2dux12_mlc_odr_val_t *val) +int32_t lis2dux12_mlc_data_rate_get(const stmdev_ctx_t *ctx, + lis2dux12_mlc_odr_val_t *val) { lis2dux12_mlc_odr_t reg; int32_t ret; @@ -3640,23 +3848,23 @@ int32_t lis2dux12_mlc_data_rate_get(stmdev_ctx_t *ctx, switch (reg.mlc_odr) { - case LIS2DUX12_ODR_PRGS_12Hz5: + case 0: *val = LIS2DUX12_ODR_PRGS_12Hz5; break; - case LIS2DUX12_ODR_PRGS_25Hz: + case 1: *val = LIS2DUX12_ODR_PRGS_25Hz; break; - case LIS2DUX12_ODR_PRGS_50Hz: + case 2: *val = LIS2DUX12_ODR_PRGS_50Hz; break; - case LIS2DUX12_ODR_PRGS_100Hz: + case 3: *val = LIS2DUX12_ODR_PRGS_100Hz; break; - case LIS2DUX12_ODR_PRGS_200Hz: + case 4: *val = LIS2DUX12_ODR_PRGS_200Hz; break; @@ -3679,7 +3887,7 @@ int32_t lis2dux12_mlc_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2dux12_mlc_fifo_en_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dux12_mlc_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dux12_emb_func_fifo_en_t fifo_reg; int32_t ret; @@ -3706,7 +3914,7 @@ int32_t lis2dux12_mlc_fifo_en_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2dux12_mlc_fifo_en_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dux12_mlc_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dux12_emb_func_fifo_en_t fifo_reg; int32_t ret; diff --git a/sensor/stmemsc/lis2dux12_STdC/driver/lis2dux12_reg.h b/sensor/stmemsc/lis2dux12_STdC/driver/lis2dux12_reg.h index 3a5a72e7..4458d964 100644 --- a/sensor/stmemsc/lis2dux12_STdC/driver/lis2dux12_reg.h +++ b/sensor/stmemsc/lis2dux12_STdC/driver/lis2dux12_reg.h @@ -23,7 +23,7 @@ #define LIS2DUX12_REGS_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -75,7 +75,8 @@ #ifndef MEMS_SHARED_TYPES #define MEMS_SHARED_TYPES -typedef struct{ +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t bit0 : 1; uint8_t bit1 : 1; @@ -108,8 +109,8 @@ typedef struct{ * */ -typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); -typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef int32_t (*stmdev_write_ptr)(void *ctx, uint8_t reg, const uint8_t *data, uint16_t len); +typedef int32_t (*stmdev_read_ptr)(void *ctx, uint8_t reg, uint8_t *data, uint16_t len); typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct @@ -144,7 +145,8 @@ typedef struct * */ -typedef struct { +typedef struct +{ uint8_t address; uint8_t data; } ucf_line_t; @@ -178,6 +180,18 @@ typedef struct { * */ +#define LIS2DUX12_EXT_CLK_CFG 0x08U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 7; + uint8_t ext_clk_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ext_clk_en : 1; + uint8_t not_used0 : 7; +#endif /* DRV_BYTE_ORDER */ +} lis2dux12_ext_clk_cfg_t; + #define LIS2DUX12_PIN_CTRL 0x0CU typedef struct { @@ -702,13 +716,15 @@ typedef struct typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t not_used0 : 4; + uint8_t t_dis : 1; + uint8_t not_used0 : 3; uint8_t st : 2; uint8_t not_used1 : 2; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN uint8_t not_used1 : 2; uint8_t st : 2; - uint8_t not_used0 : 4; + uint8_t not_used0 : 3; + uint8_t t_dis : 1; #endif /* DRV_BYTE_ORDER */ } lis2dux12_self_test_t; @@ -804,7 +820,7 @@ typedef struct #endif /* DRV_BYTE_ORDER */ } lis2dux12_sleep_t; -#define LIS2DUX12_IF_WAKE_UP 0x3EU +#define LIS2DUX12_EN_DEVICE_CONFIG 0x3EU typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN @@ -814,7 +830,7 @@ typedef struct uint8_t not_used0 : 7; uint8_t soft_pd : 1; #endif /* DRV_BYTE_ORDER */ -} lis2dux12_if_wake_up_t; +} lis2dux12_en_device_config_t; #define LIS2DUX12_FUNC_CFG_ACCESS 0x3FU typedef struct @@ -1938,7 +1954,7 @@ typedef union lis2dux12_fsm_status_mainpage_t fsm_status_mainpage; lis2dux12_mlc_status_mainpage_t mlc_status_mainpage; lis2dux12_sleep_t sleep; - lis2dux12_if_wake_up_t if_wake_up; + lis2dux12_en_device_config_t en_device_config; lis2dux12_func_cfg_access_t func_cfg_access; lis2dux12_fifo_data_out_tag_t fifo_data_out_tag; lis2dux12_fifo_data_out_x_l_t fifo_data_out_x_l; @@ -2032,12 +2048,12 @@ typedef union * them with a custom implementation. */ -int32_t lis2dux12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len); -int32_t lis2dux12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lis2dux12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); +int32_t lis2dux12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); float_t lis2dux12_from_fs2g_to_mg(int16_t lsb); float_t lis2dux12_from_fs4g_to_mg(int16_t lsb); @@ -2045,41 +2061,45 @@ float_t lis2dux12_from_fs8g_to_mg(int16_t lsb); float_t lis2dux12_from_fs16g_to_mg(int16_t lsb); float_t lis2dux12_from_lsb_to_celsius(int16_t lsb); -int32_t lis2dux12_device_id_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dux12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val); -typedef enum { +typedef enum +{ LIS2DUX12_SENSOR_ONLY_ON = 0x00, /* Initialize the driver for sensor usage */ LIS2DUX12_BOOT = 0x01, /* Restore calib. param. (it takes 10ms) */ LIS2DUX12_RESET = 0x02, /* Reset configuration registers */ LIS2DUX12_SENSOR_EMB_FUNC_ON = 0x03, /* Initialize the driver for sensor and/or embedded functions usage (it takes 10ms) */ } lis2dux12_init_t; -int32_t lis2dux12_init_set(stmdev_ctx_t *ctx, lis2dux12_init_t val); +int32_t lis2dux12_init_set(const stmdev_ctx_t *ctx, lis2dux12_init_t val); -typedef struct { +typedef struct +{ uint8_t sw_reset : 1; /* Restoring configuration registers */ uint8_t boot : 1; /* Restoring calibration parameters */ uint8_t drdy : 1; /* Accelerometer data ready */ uint8_t power_down : 1; /* Monitors power-down. */ } lis2dux12_status_t; -int32_t lis2dux12_status_get(stmdev_ctx_t *ctx, lis2dux12_status_t *val); +int32_t lis2dux12_status_get(const stmdev_ctx_t *ctx, lis2dux12_status_t *val); -typedef struct { +typedef struct +{ uint8_t is_step_det : 1; /* Step detected */ uint8_t is_tilt : 1; /* Tilt detected */ uint8_t is_sigmot : 1; /* Significant motion detected */ } lis2dux12_embedded_status_t; -int32_t lis2dux12_embedded_status_get(stmdev_ctx_t *ctx, lis2dux12_embedded_status_t *val); +int32_t lis2dux12_embedded_status_get(const stmdev_ctx_t *ctx, lis2dux12_embedded_status_t *val); typedef enum { LIS2DUX12_DRDY_LATCHED = 0x0, LIS2DUX12_DRDY_PULSED = 0x1, } lis2dux12_data_ready_mode_t; -int32_t lis2dux12_data_ready_mode_set(stmdev_ctx_t *ctx, lis2dux12_data_ready_mode_t val); -int32_t lis2dux12_data_ready_mode_get(stmdev_ctx_t *ctx, lis2dux12_data_ready_mode_t *val); +int32_t lis2dux12_data_ready_mode_set(const stmdev_ctx_t *ctx, lis2dux12_data_ready_mode_t val); +int32_t lis2dux12_data_ready_mode_get(const stmdev_ctx_t *ctx, lis2dux12_data_ready_mode_t *val); -typedef enum { +typedef enum +{ LIS2DUX12_OFF = 0x00, /* in power down */ LIS2DUX12_1Hz6_ULP = 0x01, /* @1Hz6 (ultra low power) */ LIS2DUX12_3Hz_ULP = 0x02, /* @3Hz (ultra low power) */ @@ -2104,29 +2124,35 @@ typedef enum { LIS2DUX12_TRIG_SW = 0x2F, /* Single-shot high latency by IF */ } lis2dux12_odr_t; -typedef enum { +typedef enum +{ LIS2DUX12_2g = 0, LIS2DUX12_4g = 1, LIS2DUX12_8g = 2, LIS2DUX12_16g = 3, } lis2dux12_fs_t; -typedef enum { +typedef enum +{ LIS2DUX12_ODR_div_2 = 0, LIS2DUX12_ODR_div_4 = 1, LIS2DUX12_ODR_div_8 = 2, LIS2DUX12_ODR_div_16 = 3, } lis2dux12_bw_t; -typedef struct { +typedef struct +{ lis2dux12_odr_t odr; lis2dux12_fs_t fs; lis2dux12_bw_t bw; } lis2dux12_md_t; -int32_t lis2dux12_mode_set(stmdev_ctx_t *ctx, lis2dux12_md_t *val); -int32_t lis2dux12_mode_get(stmdev_ctx_t *ctx, lis2dux12_md_t *val); +int32_t lis2dux12_mode_set(const stmdev_ctx_t *ctx, const lis2dux12_md_t *val); +int32_t lis2dux12_mode_get(const stmdev_ctx_t *ctx, lis2dux12_md_t *val); -int32_t lis2dux12_trigger_sw(stmdev_ctx_t *ctx, lis2dux12_md_t *md); +int32_t lis2dux12_temp_disable_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dux12_temp_disable_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lis2dux12_trigger_sw(const stmdev_ctx_t *ctx, const lis2dux12_md_t *md); typedef struct { @@ -2155,23 +2181,26 @@ typedef struct uint8_t fifo_ovr : 1; uint8_t fifo_th : 1; } lis2dux12_all_sources_t; -int32_t lis2dux12_all_sources_get(stmdev_ctx_t *ctx, lis2dux12_all_sources_t *val); +int32_t lis2dux12_all_sources_get(const stmdev_ctx_t *ctx, lis2dux12_all_sources_t *val); -typedef struct { +typedef struct +{ float_t mg[3]; int16_t raw[3]; } lis2dux12_xl_data_t; -int32_t lis2dux12_xl_data_get(stmdev_ctx_t *ctx, lis2dux12_md_t *md, - lis2dux12_xl_data_t *data); +int32_t lis2dux12_xl_data_get(const stmdev_ctx_t *ctx, const lis2dux12_md_t *md, + lis2dux12_xl_data_t *data); -typedef struct { - struct { +typedef struct +{ + struct + { float_t deg_c; int16_t raw; - }heat; + } heat; } lis2dux12_outt_data_t; -int32_t lis2dux12_outt_data_get(stmdev_ctx_t *ctx, lis2dux12_md_t *md, - lis2dux12_outt_data_t *data); +int32_t lis2dux12_outt_data_get(const stmdev_ctx_t *ctx, + lis2dux12_outt_data_t *data); typedef enum { @@ -2179,40 +2208,46 @@ typedef enum LIS2DUX12_XL_ST_POSITIVE = 0x1, LIS2DUX12_XL_ST_NEGATIVE = 0x2, } lis2dux12_xl_self_test_t; -int32_t lis2dux12_self_test_sign_set(stmdev_ctx_t *ctx, lis2dux12_xl_self_test_t val); -int32_t lis2dux12_self_test_start(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dux12_self_test_stop(stmdev_ctx_t *ctx); +int32_t lis2dux12_self_test_sign_set(const stmdev_ctx_t *ctx, lis2dux12_xl_self_test_t val); +int32_t lis2dux12_self_test_start(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dux12_self_test_stop(const stmdev_ctx_t *ctx); -int32_t lis2dux12_enter_deep_power_down(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dux12_exit_deep_power_down(stmdev_ctx_t *ctx); +int32_t lis2dux12_enter_deep_power_down(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dux12_exit_deep_power_down(const stmdev_ctx_t *ctx); -typedef enum { +typedef enum +{ LIS2DUX12_I3C_BUS_AVAIL_TIME_20US = 0x0, LIS2DUX12_I3C_BUS_AVAIL_TIME_50US = 0x1, LIS2DUX12_I3C_BUS_AVAIL_TIME_1MS = 0x2, LIS2DUX12_I3C_BUS_AVAIL_TIME_25MS = 0x3, } lis2dux12_bus_act_sel_t; -typedef struct { +typedef struct +{ lis2dux12_bus_act_sel_t bus_act_sel; uint8_t asf_on : 1; uint8_t drstdaa_en : 1; } lis2dux12_i3c_cfg_t; -int32_t lis2dux12_i3c_configure_set(stmdev_ctx_t *ctx, lis2dux12_i3c_cfg_t *val); -int32_t lis2dux12_i3c_configure_get(stmdev_ctx_t *ctx, lis2dux12_i3c_cfg_t *val); +int32_t lis2dux12_i3c_configure_set(const stmdev_ctx_t *ctx, const lis2dux12_i3c_cfg_t *val); +int32_t lis2dux12_i3c_configure_get(const stmdev_ctx_t *ctx, lis2dux12_i3c_cfg_t *val); typedef enum { LIS2DUX12_MAIN_MEM_BANK = 0x0, LIS2DUX12_EMBED_FUNC_MEM_BANK = 0x1, } lis2dux12_mem_bank_t; -int32_t lis2dux12_mem_bank_set(stmdev_ctx_t *ctx, lis2dux12_mem_bank_t val); -int32_t lis2dux12_mem_bank_get(stmdev_ctx_t *ctx, lis2dux12_mem_bank_t *val); +int32_t lis2dux12_mem_bank_set(const stmdev_ctx_t *ctx, lis2dux12_mem_bank_t val); +int32_t lis2dux12_mem_bank_get(const stmdev_ctx_t *ctx, lis2dux12_mem_bank_t *val); + +int32_t lis2dux12_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); +int32_t lis2dux12_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); -int32_t lis2dux12_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); -int32_t lis2dux12_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); +int32_t lis2dux12_ext_clk_en_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dux12_ext_clk_en_get(const stmdev_ctx_t *ctx, uint8_t *val); -typedef struct { +typedef struct +{ uint8_t sdo_pull_up : 1; /* 1 = pull up enable */ uint8_t sda_pull_up : 1; /* 1 = pull up enable */ uint8_t cs_pull_up : 1; /* 1 = pull up enable */ @@ -2220,26 +2255,27 @@ typedef struct { uint8_t int1_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */ uint8_t int2_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */ } lis2dux12_pin_conf_t; -int32_t lis2dux12_pin_conf_set(stmdev_ctx_t *ctx, lis2dux12_pin_conf_t *val); -int32_t lis2dux12_pin_conf_get(stmdev_ctx_t *ctx, lis2dux12_pin_conf_t *val); +int32_t lis2dux12_pin_conf_set(const stmdev_ctx_t *ctx, const lis2dux12_pin_conf_t *val); +int32_t lis2dux12_pin_conf_get(const stmdev_ctx_t *ctx, lis2dux12_pin_conf_t *val); typedef enum { LIS2DUX12_ACTIVE_HIGH = 0x0, LIS2DUX12_ACTIVE_LOW = 0x1, } lis2dux12_int_pin_polarity_t; -int32_t lis2dux12_int_pin_polarity_set(stmdev_ctx_t *ctx, lis2dux12_int_pin_polarity_t val); -int32_t lis2dux12_int_pin_polarity_get(stmdev_ctx_t *ctx, lis2dux12_int_pin_polarity_t *val); +int32_t lis2dux12_int_pin_polarity_set(const stmdev_ctx_t *ctx, lis2dux12_int_pin_polarity_t val); +int32_t lis2dux12_int_pin_polarity_get(const stmdev_ctx_t *ctx, lis2dux12_int_pin_polarity_t *val); typedef enum { LIS2DUX12_SPI_4_WIRE = 0x0, /* SPI 4 wires */ LIS2DUX12_SPI_3_WIRE = 0x1, /* SPI 3 wires */ } lis2dux12_spi_mode; -int32_t lis2dux12_spi_mode_set(stmdev_ctx_t *ctx, lis2dux12_spi_mode val); -int32_t lis2dux12_spi_mode_get(stmdev_ctx_t *ctx, lis2dux12_spi_mode *val); +int32_t lis2dux12_spi_mode_set(const stmdev_ctx_t *ctx, lis2dux12_spi_mode val); +int32_t lis2dux12_spi_mode_get(const stmdev_ctx_t *ctx, lis2dux12_spi_mode *val); -typedef struct { +typedef struct +{ uint8_t int_on_res : 1; /* Interrupt on RES pin */ uint8_t drdy : 1; /* Accelerometer data ready */ uint8_t boot : 1; /* Restoring calibration parameters */ @@ -2254,29 +2290,30 @@ typedef struct { uint8_t emb_function : 1; /* Embedded Function */ uint8_t timestamp : 1; /* Timestamp */ } lis2dux12_pin_int_route_t; -int32_t lis2dux12_pin_int1_route_set(stmdev_ctx_t *ctx, - lis2dux12_pin_int_route_t *val); -int32_t lis2dux12_pin_int1_route_get(stmdev_ctx_t *ctx, - lis2dux12_pin_int_route_t *val); -int32_t lis2dux12_pin_int2_route_set(stmdev_ctx_t *ctx, - lis2dux12_pin_int_route_t *val); -int32_t lis2dux12_pin_int2_route_get(stmdev_ctx_t *ctx, - lis2dux12_pin_int_route_t *val); - -typedef struct { +int32_t lis2dux12_pin_int1_route_set(const stmdev_ctx_t *ctx, + const lis2dux12_pin_int_route_t *val); +int32_t lis2dux12_pin_int1_route_get(const stmdev_ctx_t *ctx, + lis2dux12_pin_int_route_t *val); +int32_t lis2dux12_pin_int2_route_set(const stmdev_ctx_t *ctx, + const lis2dux12_pin_int_route_t *val); +int32_t lis2dux12_pin_int2_route_get(const stmdev_ctx_t *ctx, + lis2dux12_pin_int_route_t *val); + +typedef struct +{ uint8_t step_det : 1; /* route step detection event on INT pad */ uint8_t tilt : 1; /* route tilt event on INT pad */ uint8_t sig_mot : 1; /* route significant motion event on INT pad */ uint8_t fsm_lc : 1; /* route FSM long counter event on INT pad */ } lis2dux12_emb_pin_int_route_t; -int32_t lis2dux12_emb_pin_int1_route_set(stmdev_ctx_t *ctx, - lis2dux12_emb_pin_int_route_t *val); -int32_t lis2dux12_emb_pin_int1_route_get(stmdev_ctx_t *ctx, - lis2dux12_emb_pin_int_route_t *val); -int32_t lis2dux12_emb_pin_int2_route_set(stmdev_ctx_t *ctx, - lis2dux12_emb_pin_int_route_t *val); -int32_t lis2dux12_emb_pin_int2_route_get(stmdev_ctx_t *ctx, - lis2dux12_emb_pin_int_route_t *val); +int32_t lis2dux12_emb_pin_int1_route_set(const stmdev_ctx_t *ctx, + const lis2dux12_emb_pin_int_route_t *val); +int32_t lis2dux12_emb_pin_int1_route_get(const stmdev_ctx_t *ctx, + lis2dux12_emb_pin_int_route_t *val); +int32_t lis2dux12_emb_pin_int2_route_set(const stmdev_ctx_t *ctx, + const lis2dux12_emb_pin_int_route_t *val); +int32_t lis2dux12_emb_pin_int2_route_get(const stmdev_ctx_t *ctx, + lis2dux12_emb_pin_int_route_t *val); typedef enum { @@ -2285,21 +2322,24 @@ typedef enum LIS2DUX12_INT_LATCHED = 0x2, } lis2dux12_int_cfg_t; -typedef struct { +typedef struct +{ lis2dux12_int_cfg_t int_cfg; uint8_t sleep_status_on_int : 1; /* route sleep_status on interrupt */ uint8_t dis_rst_lir_all_int : 1; /* disable LIR reset when reading ALL_INT_SRC */ } lis2dux12_int_config_t; -int32_t lis2dux12_int_config_set(stmdev_ctx_t *ctx, lis2dux12_int_config_t *val); -int32_t lis2dux12_int_config_get(stmdev_ctx_t *ctx, lis2dux12_int_config_t *val); +int32_t lis2dux12_int_config_set(const stmdev_ctx_t *ctx, const lis2dux12_int_config_t *val); +int32_t lis2dux12_int_config_get(const stmdev_ctx_t *ctx, lis2dux12_int_config_t *val); typedef enum { LIS2DUX12_EMBEDDED_INT_LEVEL = 0x0, LIS2DUX12_EMBEDDED_INT_LATCHED = 0x1, } lis2dux12_embedded_int_config_t; -int32_t lis2dux12_embedded_int_config_set(stmdev_ctx_t *ctx, lis2dux12_embedded_int_config_t val); -int32_t lis2dux12_embedded_int_config_get(stmdev_ctx_t *ctx, lis2dux12_embedded_int_config_t *val); +int32_t lis2dux12_embedded_int_cfg_set(const stmdev_ctx_t *ctx, + lis2dux12_embedded_int_config_t val); +int32_t lis2dux12_embedded_int_cfg_get(const stmdev_ctx_t *ctx, + lis2dux12_embedded_int_config_t *val); typedef enum { @@ -2312,7 +2352,8 @@ typedef enum LIS2DUX12_FIFO_OFF = 0x8, } lis2dux12_operation_t; -typedef enum { +typedef enum +{ LIS2DUX12_FIFO_1X = 0, LIS2DUX12_FIFO_2X = 1, } lis2dux12_store_t; @@ -2337,22 +2378,24 @@ typedef enum LIS2DUX12_BDR_XL_ODR_OFF = 0x7, } lis2dux12_bdr_xl_t; -typedef struct { +typedef struct +{ lis2dux12_operation_t operation; lis2dux12_store_t store; - uint8_t xl_only : 1; /* when set to 1, only XL samples (16-bit) are stored in FIFO */ + uint8_t xl_only : 1; /* only XL samples (16-bit) are stored in FIFO */ uint8_t watermark : 7; /* (0 disable) max 127 @16bit, even and max 256 @8bit.*/ uint8_t cfg_change_in_fifo : 1; - struct { + struct + { lis2dux12_dec_ts_t dec_ts; /* decimation for timestamp batching*/ lis2dux12_bdr_xl_t bdr_xl; /* accelerometer batch data rate*/ } batch; } lis2dux12_fifo_mode_t; -int32_t lis2dux12_fifo_mode_set(stmdev_ctx_t *ctx, lis2dux12_fifo_mode_t val); -int32_t lis2dux12_fifo_mode_get(stmdev_ctx_t *ctx, lis2dux12_fifo_mode_t *val); +int32_t lis2dux12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2dux12_fifo_mode_t val); +int32_t lis2dux12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2dux12_fifo_mode_t *val); -int32_t lis2dux12_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val); -int32_t lis2dux12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dux12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); +int32_t lis2dux12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2366,40 +2409,44 @@ typedef enum LIS2DUX12_MLC_FEATURE = 0x1C, LIS2DUX12_FSM_RESULT_TAG = 0x1D, } lis2dux12_fifo_sensor_tag_t; -int32_t lis2dux12_fifo_sensor_tag_get(stmdev_ctx_t *ctx, - lis2dux12_fifo_sensor_tag_t *val); +int32_t lis2dux12_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, + lis2dux12_fifo_sensor_tag_t *val); -int32_t lis2dux12_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis2dux12_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); -typedef struct { +typedef struct +{ uint8_t tag; - struct { + struct + { float_t mg[3]; int16_t raw[3]; - }xl[2]; - struct lis2dux12_heat { + } xl[2]; + struct + { float_t deg_c; int16_t raw; } heat; - struct lis2dux12_pedo { + struct + { uint32_t steps; uint32_t timestamp; } pedo; - struct lis2dux12_cfg_chg { + struct + { uint8_t cfg_change : 1; /* 1 if ODR/BDR configuration is changed */ uint8_t odr : 4; /* ODR */ uint8_t bw : 2; /* BW */ - uint8_t lp_hp : 1; /* Power (LP == 0/HP == 1) */ + uint8_t lp_hp : 1; /* Power: 0 for LP, 1 for HP */ uint8_t fs : 2; /* FS */ uint8_t dec_ts : 2; /* Timestamp decimator value */ uint8_t odr_xl_batch : 1; /* Accelerometer ODR is batched */ uint32_t timestamp; } cfg_chg; } lis2dux12_fifo_data_t; -int32_t lis2dux12_fifo_data_get(stmdev_ctx_t *ctx, lis2dux12_md_t *md, - lis2dux12_fifo_mode_t *fmd, - lis2dux12_fifo_data_t *data); - +int32_t lis2dux12_fifo_data_get(const stmdev_ctx_t *ctx, const lis2dux12_md_t *md, + const lis2dux12_fifo_mode_t *fmd, + lis2dux12_fifo_data_t *data); typedef struct { @@ -2407,27 +2454,27 @@ typedef struct uint8_t step_counter_enable : 1; uint8_t step_counter_in_fifo : 1; } lis2dux12_stpcnt_mode_t; -int32_t lis2dux12_stpcnt_mode_set(stmdev_ctx_t *ctx, lis2dux12_stpcnt_mode_t val); -int32_t lis2dux12_stpcnt_mode_get(stmdev_ctx_t *ctx, lis2dux12_stpcnt_mode_t *val); +int32_t lis2dux12_stpcnt_mode_set(const stmdev_ctx_t *ctx, lis2dux12_stpcnt_mode_t val); +int32_t lis2dux12_stpcnt_mode_get(const stmdev_ctx_t *ctx, lis2dux12_stpcnt_mode_t *val); -int32_t lis2dux12_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lis2dux12_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lis2dux12_stpcnt_rst_step_set(stmdev_ctx_t *ctx); +int32_t lis2dux12_stpcnt_rst_step_set(const stmdev_ctx_t *ctx); -int32_t lis2dux12_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dux12_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dux12_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dux12_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dux12_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lis2dux12_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lis2dux12_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lis2dux12_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lis2dux12_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dux12_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dux12_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dux12_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dux12_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dux12_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dux12_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dux12_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dux12_ff_duration_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dux12_ff_duration_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dux12_ff_duration_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dux12_ff_duration_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2440,8 +2487,8 @@ typedef enum LIS2DUX12_469_mg = 0x6, LIS2DUX12_500_mg = 0x7, } lis2dux12_ff_thresholds_t; -int32_t lis2dux12_ff_thresholds_set(stmdev_ctx_t *ctx, lis2dux12_ff_thresholds_t val); -int32_t lis2dux12_ff_thresholds_get(stmdev_ctx_t *ctx, lis2dux12_ff_thresholds_t *val); +int32_t lis2dux12_ff_thresholds_set(const stmdev_ctx_t *ctx, lis2dux12_ff_thresholds_t val); +int32_t lis2dux12_ff_thresholds_get(const stmdev_ctx_t *ctx, lis2dux12_ff_thresholds_t *val); typedef enum { @@ -2457,13 +2504,14 @@ typedef enum LIS2DUX12_4D = 0x1, } lis2dux12_mode_t; -typedef struct { +typedef struct +{ lis2dux12_threshold_t threshold; lis2dux12_mode_t mode; } lis2dux12_sixd_config_t; -int32_t lis2dux12_sixd_config_set(stmdev_ctx_t *ctx, lis2dux12_sixd_config_t val); -int32_t lis2dux12_sixd_config_get(stmdev_ctx_t *ctx, lis2dux12_sixd_config_t *val); +int32_t lis2dux12_sixd_config_set(const stmdev_ctx_t *ctx, lis2dux12_sixd_config_t val); +int32_t lis2dux12_sixd_config_get(const stmdev_ctx_t *ctx, lis2dux12_sixd_config_t *val); typedef enum { @@ -2490,7 +2538,8 @@ typedef enum LIS2DUX12_ODR_25_HZ = 1, /* set odr to 25Hz during inactivity state */ } lis2dux12_inact_odr_t; -typedef struct { +typedef struct +{ lis2dux12_wake_dur_t wake_dur; uint8_t sleep_dur : 4; /* 1 LSB == 512 ODR time */ uint8_t wake_ths : 7; /* wakeup threshold */ @@ -2499,8 +2548,8 @@ typedef struct { lis2dux12_inact_odr_t inact_odr; } lis2dux12_wakeup_config_t; -int32_t lis2dux12_wakeup_config_set(stmdev_ctx_t *ctx, lis2dux12_wakeup_config_t val); -int32_t lis2dux12_wakeup_config_get(stmdev_ctx_t *ctx, lis2dux12_wakeup_config_t *val); +int32_t lis2dux12_wakeup_config_set(const stmdev_ctx_t *ctx, lis2dux12_wakeup_config_t val); +int32_t lis2dux12_wakeup_config_get(const stmdev_ctx_t *ctx, lis2dux12_wakeup_config_t *val); typedef enum { @@ -2510,7 +2559,8 @@ typedef enum LIS2DUX12_TAP_ON_Z = 0x3, /* Detect tap on Z axis */ } lis2dux12_axis_t; -typedef struct { +typedef struct +{ lis2dux12_axis_t axis; uint8_t inverted_peak_time : 5; /* 1 LSB == 1 sample */ uint8_t pre_still_ths : 4; /* 1 LSB == 62.5 mg */ @@ -2528,35 +2578,35 @@ typedef struct { uint8_t triple_tap_on : 1; /* enable triple tap */ } lis2dux12_tap_config_t; -int32_t lis2dux12_tap_config_set(stmdev_ctx_t *ctx, lis2dux12_tap_config_t val); -int32_t lis2dux12_tap_config_get(stmdev_ctx_t *ctx, lis2dux12_tap_config_t *val); +int32_t lis2dux12_tap_config_set(const stmdev_ctx_t *ctx, lis2dux12_tap_config_t val); +int32_t lis2dux12_tap_config_get(const stmdev_ctx_t *ctx, lis2dux12_tap_config_t *val); -int32_t lis2dux12_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dux12_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dux12_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dux12_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dux12_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); +int32_t lis2dux12_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); -int32_t lis2dux12_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, - uint8_t *val); +int32_t lis2dux12_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, + uint8_t *val); -int32_t lis2dux12_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dux12_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dux12_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dux12_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { lis2dux12_fsm_enable_t fsm_enable; } lis2dux12_emb_fsm_enable_t; -int32_t lis2dux12_fsm_enable_set(stmdev_ctx_t *ctx, - lis2dux12_emb_fsm_enable_t *val); -int32_t lis2dux12_fsm_enable_get(stmdev_ctx_t *ctx, - lis2dux12_emb_fsm_enable_t *val); +int32_t lis2dux12_fsm_enable_set(const stmdev_ctx_t *ctx, + lis2dux12_emb_fsm_enable_t *val); +int32_t lis2dux12_fsm_enable_get(const stmdev_ctx_t *ctx, + lis2dux12_emb_fsm_enable_t *val); -int32_t lis2dux12_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lis2dux12_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lis2dux12_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lis2dux12_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lis2dux12_fsm_status_get(stmdev_ctx_t *ctx, - lis2dux12_fsm_status_mainpage_t *val); -int32_t lis2dux12_fsm_out_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dux12_fsm_status_get(const stmdev_ctx_t *ctx, + lis2dux12_fsm_status_mainpage_t *val); +int32_t lis2dux12_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2568,45 +2618,43 @@ typedef enum LIS2DUX12_ODR_FSM_400Hz = 5, LIS2DUX12_ODR_FSM_800Hz = 6, } lis2dux12_fsm_val_odr_t; -int32_t lis2dux12_fsm_data_rate_set(stmdev_ctx_t *ctx, - lis2dux12_fsm_val_odr_t val); -int32_t lis2dux12_fsm_data_rate_get(stmdev_ctx_t *ctx, - lis2dux12_fsm_val_odr_t *val); +int32_t lis2dux12_fsm_data_rate_set(const stmdev_ctx_t *ctx, + lis2dux12_fsm_val_odr_t val); +int32_t lis2dux12_fsm_data_rate_get(const stmdev_ctx_t *ctx, + lis2dux12_fsm_val_odr_t *val); -int32_t lis2dux12_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dux12_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dux12_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dux12_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dux12_fsm_fifo_en_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dux12_fsm_fifo_en_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dux12_fsm_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dux12_fsm_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dux12_long_cnt_int_value_set(stmdev_ctx_t *ctx, - uint16_t val); -int32_t lis2dux12_long_cnt_int_value_get(stmdev_ctx_t *ctx, - uint16_t *val); - -int32_t lis2dux12_fsm_number_of_programs_set(stmdev_ctx_t *ctx, - uint8_t *buff); -int32_t lis2dux12_fsm_number_of_programs_get(stmdev_ctx_t *ctx, - uint8_t *buff); - -int32_t lis2dux12_fsm_start_address_set(stmdev_ctx_t *ctx, +int32_t lis2dux12_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lis2dux12_fsm_start_address_get(stmdev_ctx_t *ctx, +int32_t lis2dux12_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val); +int32_t lis2dux12_fsm_programs_num_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dux12_fsm_programs_num_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lis2dux12_fsm_start_address_set(const stmdev_ctx_t *ctx, + uint16_t val); +int32_t lis2dux12_fsm_start_address_get(const stmdev_ctx_t *ctx, + uint16_t *val); + typedef enum { LIS2DUX12_MLC_OFF = 0, LIS2DUX12_MLC_ON = 1, LIS2DUX12_MLC_ON_BEFORE_FSM = 2, } lis2dux12_mlc_mode_t; -int32_t lis2dux12_mlc_set(stmdev_ctx_t *ctx, lis2dux12_mlc_mode_t val); -int32_t lis2dux12_mlc_get(stmdev_ctx_t *ctx, lis2dux12_mlc_mode_t *val); +int32_t lis2dux12_mlc_set(const stmdev_ctx_t *ctx, lis2dux12_mlc_mode_t val); +int32_t lis2dux12_mlc_get(const stmdev_ctx_t *ctx, lis2dux12_mlc_mode_t *val); -int32_t lis2dux12_mlc_status_get(stmdev_ctx_t *ctx, - lis2dux12_mlc_status_mainpage_t *val); +int32_t lis2dux12_mlc_status_get(const stmdev_ctx_t *ctx, + lis2dux12_mlc_status_mainpage_t *val); -int32_t lis2dux12_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis2dux12_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); typedef enum { @@ -2616,13 +2664,13 @@ typedef enum LIS2DUX12_ODR_PRGS_100Hz = 3, LIS2DUX12_ODR_PRGS_200Hz = 4, } lis2dux12_mlc_odr_val_t; -int32_t lis2dux12_mlc_data_rate_set(stmdev_ctx_t *ctx, - lis2dux12_mlc_odr_val_t val); -int32_t lis2dux12_mlc_data_rate_get(stmdev_ctx_t *ctx, - lis2dux12_mlc_odr_val_t *val); +int32_t lis2dux12_mlc_data_rate_set(const stmdev_ctx_t *ctx, + lis2dux12_mlc_odr_val_t val); +int32_t lis2dux12_mlc_data_rate_get(const stmdev_ctx_t *ctx, + lis2dux12_mlc_odr_val_t *val); -int32_t lis2dux12_mlc_fifo_en_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dux12_mlc_fifo_en_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dux12_mlc_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dux12_mlc_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val); #ifdef __cplusplus } diff --git a/sensor/stmemsc/lis2duxs12_STdC/driver/lis2duxs12_reg.c b/sensor/stmemsc/lis2duxs12_STdC/driver/lis2duxs12_reg.c index bc988655..1393f830 100644 --- a/sensor/stmemsc/lis2duxs12_STdC/driver/lis2duxs12_reg.c +++ b/sensor/stmemsc/lis2duxs12_STdC/driver/lis2duxs12_reg.c @@ -46,12 +46,15 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis2duxs12_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data, +int32_t __weak lis2duxs12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { - int32_t ret; - ret = ctx->read_reg(ctx->handle, reg, data, len); - return ret; + if (ctx == NULL) + { + return -1; + } + + return ctx->read_reg(ctx->handle, reg, data, len); } /** @@ -64,12 +67,15 @@ int32_t __weak lis2duxs12_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis2duxs12_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data, +int32_t __weak lis2duxs12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { - int32_t ret; - ret = ctx->write_reg(ctx->handle, reg, data, len); - return ret; + if (ctx == NULL) + { + return -1; + } + + return ctx->write_reg(ctx->handle, reg, data, len); } /** @@ -133,7 +139,7 @@ float_t lis2duxs12_from_lsb_to_mv(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_device_id_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2duxs12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -150,43 +156,103 @@ int32_t lis2duxs12_device_id_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_init_set(stmdev_ctx_t *ctx, lis2duxs12_init_t val) +int32_t lis2duxs12_init_set(const stmdev_ctx_t *ctx, lis2duxs12_init_t val) { lis2duxs12_ctrl1_t ctrl1; lis2duxs12_ctrl4_t ctrl4; + lis2duxs12_status_t status; + uint8_t cnt = 0; int32_t ret = 0; - ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t*)&ctrl1, 1); - ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t*)&ctrl4, 1); - switch (val) { + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1); + switch (val) + { case LIS2DUXS12_BOOT: ctrl4.boot = PROPERTY_ENABLE; - ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t*)&ctrl4, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + break; + } + + do + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + break; + } + + /* boot procedue ended correctly */ + if (ctrl4.boot == 0U) + { + break; + } + + if (ctx->mdelay != NULL) + { + ctx->mdelay(25); /* 25 ms of boot time */ + } + } while (cnt++ < 5U); + + if (cnt >= 5U) + { + ret = -1; /* boot procedure failed */ + } break; case LIS2DUXS12_RESET: - ctrl1.sw_reset = PROPERTY_ENABLE; - ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t*)&ctrl1, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) + { + break; + } + + do + { + ret = lis2duxs12_status_get(ctx, &status); + if (ret != 0) + { + break; + } + + /* sw-reset procedue ended correctly */ + if (status.sw_reset == 0U) + { + break; + } + + if (ctx->mdelay != NULL) + { + ctx->mdelay(1); /* should be 50 us */ + } + } while (cnt++ < 5U); + + if (cnt >= 5U) + { + ret = -1; /* sw-reset procedure failed */ + } break; case LIS2DUXS12_SENSOR_ONLY_ON: /* no embedded funcs are used */ ctrl4.emb_func_en = PROPERTY_DISABLE; ctrl4.bdu = PROPERTY_ENABLE; ctrl1.if_add_inc = PROPERTY_ENABLE; - ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t*)&ctrl4, 1); - ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t*)&ctrl1, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1); break; case LIS2DUXS12_SENSOR_EMB_FUNC_ON: /* complete configuration is used */ ctrl4.emb_func_en = PROPERTY_ENABLE; ctrl4.bdu = PROPERTY_ENABLE; ctrl1.if_add_inc = PROPERTY_ENABLE; - ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t*)&ctrl4, 1); - ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t*)&ctrl1, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1); break; default: ctrl1.sw_reset = PROPERTY_ENABLE; - ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t*)&ctrl1, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1); break; } return ret; @@ -200,7 +266,7 @@ int32_t lis2duxs12_init_set(stmdev_ctx_t *ctx, lis2duxs12_init_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_status_get(stmdev_ctx_t *ctx, lis2duxs12_status_t *val) +int32_t lis2duxs12_status_get(const stmdev_ctx_t *ctx, lis2duxs12_status_t *val) { lis2duxs12_status_register_t status_register; lis2duxs12_ctrl1_t ctrl1; @@ -208,13 +274,9 @@ int32_t lis2duxs12_status_get(stmdev_ctx_t *ctx, lis2duxs12_status_t *val) int32_t ret; ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_STATUS, - (uint8_t*)&status_register, 1); - if (ret == 0) { - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t*)&ctrl1, 1); - } - if (ret == 0) { - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t*)&ctrl4, 1); - } + (uint8_t *)&status_register, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL1, (uint8_t *)&ctrl1, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1); val->sw_reset = ctrl1.sw_reset; val->boot = ctrl4.boot; @@ -231,13 +293,13 @@ int32_t lis2duxs12_status_get(stmdev_ctx_t *ctx, lis2duxs12_status_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_embedded_status_get(stmdev_ctx_t *ctx, lis2duxs12_embedded_status_t *val) +int32_t lis2duxs12_embedded_status_get(const stmdev_ctx_t *ctx, lis2duxs12_embedded_status_t *val) { lis2duxs12_emb_func_status_t status; int32_t ret; ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); - ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_STATUS, (uint8_t*)&status, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_STATUS, (uint8_t *)&status, 1); ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); val->is_step_det = status.is_step_det; @@ -255,7 +317,7 @@ int32_t lis2duxs12_embedded_status_get(stmdev_ctx_t *ctx, lis2duxs12_embedded_st * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_data_ready_mode_set(stmdev_ctx_t *ctx, lis2duxs12_data_ready_mode_t val) +int32_t lis2duxs12_data_ready_mode_set(const stmdev_ctx_t *ctx, lis2duxs12_data_ready_mode_t val) { lis2duxs12_ctrl1_t ctrl1; int32_t ret; @@ -279,7 +341,7 @@ int32_t lis2duxs12_data_ready_mode_set(stmdev_ctx_t *ctx, lis2duxs12_data_ready_ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_data_ready_mode_get(stmdev_ctx_t *ctx, lis2duxs12_data_ready_mode_t *val) +int32_t lis2duxs12_data_ready_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_data_ready_mode_t *val) { lis2duxs12_ctrl1_t ctrl1; int32_t ret; @@ -288,11 +350,11 @@ int32_t lis2duxs12_data_ready_mode_get(stmdev_ctx_t *ctx, lis2duxs12_data_ready_ switch ((ctrl1.drdy_pulsed)) { - case LIS2DUXS12_DRDY_LATCHED: + case 0x0: *val = LIS2DUXS12_DRDY_LATCHED; break; - case LIS2DUXS12_DRDY_PULSED: + case 0x1: *val = LIS2DUXS12_DRDY_PULSED; break; @@ -311,19 +373,20 @@ int32_t lis2duxs12_data_ready_mode_get(stmdev_ctx_t *ctx, lis2duxs12_data_ready_ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_mode_set(stmdev_ctx_t *ctx, lis2duxs12_md_t *val) +int32_t lis2duxs12_mode_set(const stmdev_ctx_t *ctx, const lis2duxs12_md_t *val) { lis2duxs12_ctrl3_t ctrl3; lis2duxs12_ctrl5_t ctrl5; int32_t ret; - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL5, (uint8_t*)&ctrl5, 1); + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL5, (uint8_t *)&ctrl5, 1); ctrl5.odr = (uint8_t)val->odr & 0xFU; ctrl5.fs = (uint8_t)val->fs; /* set the bandwidth */ - switch (val->odr) { + switch (val->odr) + { /* no anti-aliasing filter present */ case LIS2DUXS12_OFF: case LIS2DUXS12_1Hz6_ULP: @@ -334,21 +397,29 @@ int32_t lis2duxs12_mode_set(stmdev_ctx_t *ctx, lis2duxs12_md_t *val) /* low-power mode with ODR < 50 Hz */ case LIS2DUXS12_6Hz_LP: - switch(val->bw) { + switch (val->bw) + { + default: case LIS2DUXS12_ODR_div_4: case LIS2DUXS12_ODR_div_8: case LIS2DUXS12_ODR_div_16: - return -1; + /* value not allowed */ + ret = -1; + break; case LIS2DUXS12_ODR_div_2: ctrl5.bw = 0x3; break; } break; case LIS2DUXS12_12Hz5_LP: - switch(val->bw) { + switch (val->bw) + { + default: case LIS2DUXS12_ODR_div_8: case LIS2DUXS12_ODR_div_16: - return -1; + /* value not allowed */ + ret = -1; + break; case LIS2DUXS12_ODR_div_2: ctrl5.bw = 0x2; break; @@ -358,9 +429,13 @@ int32_t lis2duxs12_mode_set(stmdev_ctx_t *ctx, lis2duxs12_md_t *val) } break; case LIS2DUXS12_25Hz_LP: - switch(val->bw) { + switch (val->bw) + { + default: case LIS2DUXS12_ODR_div_16: - return -1; + /* value not allowed */ + ret = -1; + break; case LIS2DUXS12_ODR_div_2: ctrl5.bw = 0x1; break; @@ -389,17 +464,24 @@ int32_t lis2duxs12_mode_set(stmdev_ctx_t *ctx, lis2duxs12_md_t *val) case LIS2DUXS12_200Hz_HP: case LIS2DUXS12_400Hz_HP: case LIS2DUXS12_800Hz_HP: + default: ctrl5.bw = (uint8_t)val->bw; break; } - ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t*)&ctrl3, 1); + if (ret != 0) + { + return ret; + } + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t *)&ctrl3, 1); ctrl3.hp_en = (((uint8_t)val->odr & 0x30U) == 0x10U) ? 1U : 0U; - if (ret == 0) { - ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL5, (uint8_t*)&ctrl5, 1); - ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t*)&ctrl3, 1); + if (ret == 0) + { + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL5, (uint8_t *)&ctrl5, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t *)&ctrl3, 1); } return ret; @@ -413,56 +495,57 @@ int32_t lis2duxs12_mode_set(stmdev_ctx_t *ctx, lis2duxs12_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_mode_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *val) +int32_t lis2duxs12_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_md_t *val) { lis2duxs12_ctrl3_t ctrl3; lis2duxs12_ctrl5_t ctrl5; int32_t ret; - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL5, (uint8_t*)&ctrl5, 1); - ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t*)&ctrl3, 1); + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL5, (uint8_t *)&ctrl5, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t *)&ctrl3, 1); - switch (ctrl5.odr) { - case LIS2DUXS12_OFF: + switch (ctrl5.odr) + { + case 0x00: val->odr = LIS2DUXS12_OFF; break; - case LIS2DUXS12_1Hz6_ULP: + case 0x01: val->odr = LIS2DUXS12_1Hz6_ULP; break; - case LIS2DUXS12_3Hz_ULP: + case 0x02: val->odr = LIS2DUXS12_3Hz_ULP; break; - case LIS2DUXS12_25Hz_ULP: + case 0x03: val->odr = LIS2DUXS12_25Hz_ULP; break; - case LIS2DUXS12_6Hz_LP: + case 0x04: val->odr = LIS2DUXS12_6Hz_LP; break; - case LIS2DUXS12_12Hz5_LP: + case 0x05: val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_12Hz5_HP : LIS2DUXS12_12Hz5_LP; break; - case LIS2DUXS12_25Hz_LP: + case 0x06: val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_25Hz_HP : LIS2DUXS12_25Hz_LP; break; - case LIS2DUXS12_50Hz_LP: + case 0x07: val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_50Hz_HP : LIS2DUXS12_50Hz_LP; break; - case LIS2DUXS12_100Hz_LP: + case 0x08: val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_100Hz_HP : LIS2DUXS12_100Hz_LP; break; - case LIS2DUXS12_200Hz_LP: + case 0x09: val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_200Hz_HP : LIS2DUXS12_200Hz_LP; break; - case LIS2DUXS12_400Hz_LP: + case 0x0A: val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_400Hz_HP : LIS2DUXS12_400Hz_LP; break; - case LIS2DUXS12_800Hz_LP: + case 0x0B: val->odr = (ctrl3.hp_en == 0x1U) ? LIS2DUXS12_800Hz_HP : LIS2DUXS12_800Hz_LP; break; - case LIS2DUXS12_TRIG_PIN: + case 0xe: val->odr = LIS2DUXS12_TRIG_PIN; break; - case LIS2DUXS12_TRIG_SW: + case 0xf: val->odr = LIS2DUXS12_TRIG_SW; break; default: @@ -470,17 +553,18 @@ int32_t lis2duxs12_mode_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *val) break; } - switch (ctrl5.fs) { - case LIS2DUXS12_2g: + switch (ctrl5.fs) + { + case 0: val->fs = LIS2DUXS12_2g; break; - case LIS2DUXS12_4g: + case 1: val->fs = LIS2DUXS12_4g; break; - case LIS2DUXS12_8g: + case 2: val->fs = LIS2DUXS12_8g; break; - case LIS2DUXS12_16g: + case 3: val->fs = LIS2DUXS12_16g; break; default: @@ -488,17 +572,18 @@ int32_t lis2duxs12_mode_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *val) break; } - switch (ctrl5.bw) { - case LIS2DUXS12_ODR_div_2: + switch (ctrl5.bw) + { + case 0: val->bw = LIS2DUXS12_ODR_div_2; break; - case LIS2DUXS12_ODR_div_4: + case 1: val->bw = LIS2DUXS12_ODR_div_4; break; - case LIS2DUXS12_ODR_div_8: + case 2: val->bw = LIS2DUXS12_ODR_div_8; break; - case LIS2DUXS12_ODR_div_16: + case 3: val->bw = LIS2DUXS12_ODR_div_16; break; default: @@ -509,6 +594,49 @@ int32_t lis2duxs12_mode_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *val) return ret; } +/** + * @brief Disable/Enable temperature (or AH_QVAR) sensor acquisition[set] + * + * @param ctx read / write interface definitions + * @param val 1: disable temp acquisition - 0: enable temp acquisition + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_t_ah_qvar_dis_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lis2duxs12_self_test_t temp; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t *)&temp, 1); + + if (ret == 0) + { + temp.t_ah_qvar_dis = val; + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t *)&temp, 1); + } + + return ret; +} + +/** + * @brief Disable/Enable temperature (or AH_QVAR) sensor acquisition[get] + * + * @param ctx read / write interface definitions + * @param val 1: disable temp acquisition - 0: enable temp acquisition + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_t_ah_qvar_dis_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lis2duxs12_self_test_t temp; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t *)&temp, 1); + *val = temp.t_ah_qvar_dis; + + return ret; +} + /** * @brief Enter deep power down[set] * @@ -517,7 +645,7 @@ int32_t lis2duxs12_mode_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_enter_deep_power_down(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2duxs12_enter_deep_power_down(const stmdev_ctx_t *ctx, uint8_t val) { lis2duxs12_sleep_t sleep; int32_t ret; @@ -541,13 +669,18 @@ int32_t lis2duxs12_enter_deep_power_down(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_exit_deep_power_down(stmdev_ctx_t *ctx) +int32_t lis2duxs12_exit_deep_power_down(const stmdev_ctx_t *ctx) { - lis2duxs12_if_wake_up_t if_wake_up = {0}; + lis2duxs12_en_device_config_t en_device_config = {0}; int32_t ret; - if_wake_up.soft_pd = PROPERTY_ENABLE; - ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_IF_WAKE_UP, (uint8_t *)&if_wake_up, 1); + en_device_config.soft_pd = PROPERTY_ENABLE; + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_EN_DEVICE_CONFIG, (uint8_t *)&en_device_config, 1); + + if (ctx->mdelay != NULL) + { + ctx->mdelay(25); /* See AN5812 - paragraphs 3.1.1.1 and 3.1.1.2 */ + } return ret; } @@ -560,27 +693,29 @@ int32_t lis2duxs12_exit_deep_power_down(stmdev_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_trigger_sw(stmdev_ctx_t *ctx, lis2duxs12_md_t *md) +int32_t lis2duxs12_trigger_sw(const stmdev_ctx_t *ctx, const lis2duxs12_md_t *md) { lis2duxs12_ctrl4_t ctrl4; int32_t ret = 0; - if ( md->odr == LIS2DUXS12_TRIG_SW ) { - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t*)&ctrl4, 1); + if (md->odr == LIS2DUXS12_TRIG_SW) + { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1); ctrl4.soc = PROPERTY_ENABLE; - if (ret == 0) { - ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t*)&ctrl4, 1); + if (ret == 0) + { + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL4, (uint8_t *)&ctrl4, 1); } } return ret; } -int32_t lis2duxs12_all_sources_get(stmdev_ctx_t *ctx, lis2duxs12_all_sources_t *val) +int32_t lis2duxs12_all_sources_get(const stmdev_ctx_t *ctx, lis2duxs12_all_sources_t *val) { lis2duxs12_status_register_t status; int32_t ret; - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_STATUS, (uint8_t*)&status, 1); + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_STATUS, (uint8_t *)&status, 1); val->drdy = status.drdy; if (ret == 0 && status.int_global == 0x1U) @@ -589,9 +724,9 @@ int32_t lis2duxs12_all_sources_get(stmdev_ctx_t *ctx, lis2duxs12_all_sources_t * lis2duxs12_tap_src_t tap_src; lis2duxs12_sixd_src_t sixd_src; - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SIXD_SRC, (uint8_t*)&sixd_src, 1); - ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_SRC, (uint8_t*)&wu_src, 1); - ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_SRC, (uint8_t*)&tap_src, 1); + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SIXD_SRC, (uint8_t *)&sixd_src, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_SRC, (uint8_t *)&wu_src, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_TAP_SRC, (uint8_t *)&tap_src, 1); val->six_d = sixd_src.d6d_ia; val->six_d_xl = sixd_src.xl; @@ -626,8 +761,8 @@ int32_t lis2duxs12_all_sources_get(stmdev_ctx_t *ctx, lis2duxs12_all_sources_t * * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_xl_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md, - lis2duxs12_xl_data_t *data) +int32_t lis2duxs12_xl_data_get(const stmdev_ctx_t *ctx, const lis2duxs12_md_t *md, + lis2duxs12_xl_data_t *data) { uint8_t buff[6]; int32_t ret; @@ -638,22 +773,24 @@ int32_t lis2duxs12_xl_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md, /* acceleration conversion */ j = 0U; - for (i = 0U; i < 3U; i++) { - data->raw[i] = (int16_t)buff[j+1U]; + for (i = 0U; i < 3U; i++) + { + data->raw[i] = (int16_t)buff[j + 1U]; data->raw[i] = (data->raw[i] * 256) + (int16_t) buff[j]; - j+=2U; - switch ( md->fs ) { + j += 2U; + switch (md->fs) + { case LIS2DUXS12_2g: - data->mg[i] =lis2duxs12_from_fs2g_to_mg(data->raw[i]); + data->mg[i] = lis2duxs12_from_fs2g_to_mg(data->raw[i]); break; case LIS2DUXS12_4g: - data->mg[i] =lis2duxs12_from_fs4g_to_mg(data->raw[i]); + data->mg[i] = lis2duxs12_from_fs4g_to_mg(data->raw[i]); break; case LIS2DUXS12_8g: - data->mg[i] =lis2duxs12_from_fs8g_to_mg(data->raw[i]); + data->mg[i] = lis2duxs12_from_fs8g_to_mg(data->raw[i]); break; case LIS2DUXS12_16g: - data->mg[i] =lis2duxs12_from_fs16g_to_mg(data->raw[i]); + data->mg[i] = lis2duxs12_from_fs16g_to_mg(data->raw[i]); break; default: data->mg[i] = 0.0f; @@ -673,8 +810,8 @@ int32_t lis2duxs12_xl_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_outt_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md, - lis2duxs12_outt_data_t *data) +int32_t lis2duxs12_outt_data_get(const stmdev_ctx_t *ctx, + lis2duxs12_outt_data_t *data) { uint8_t buff[2]; int32_t ret; @@ -698,8 +835,8 @@ int32_t lis2duxs12_outt_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_ah_qvar_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md, - lis2duxs12_ah_qvar_data_t *data) +int32_t lis2duxs12_ah_qvar_data_get(const stmdev_ctx_t *ctx, + lis2duxs12_ah_qvar_data_t *data) { uint8_t buff[2]; int32_t ret; @@ -721,37 +858,38 @@ int32_t lis2duxs12_ah_qvar_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_self_test_sign_set(stmdev_ctx_t *ctx, lis2duxs12_xl_self_test_t val) +int32_t lis2duxs12_self_test_sign_set(const stmdev_ctx_t *ctx, lis2duxs12_xl_self_test_t val) { lis2duxs12_ctrl3_t ctrl3; lis2duxs12_wake_up_dur_t wkup_dur; int32_t ret; - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t*)&ctrl3, 1); - ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t*)&wkup_dur, 1); + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t *)&ctrl3, 1); + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wkup_dur, 1); - switch (val) { - case LIS2DUXS12_XL_ST_POSITIVE: - ctrl3.st_sign_x = 1; - ctrl3.st_sign_y = 1; - wkup_dur.st_sign_z = 0; - break; + switch (val) + { + case LIS2DUXS12_XL_ST_POSITIVE: + ctrl3.st_sign_x = 1; + ctrl3.st_sign_y = 1; + wkup_dur.st_sign_z = 0; + break; - case LIS2DUXS12_XL_ST_NEGATIVE: - ctrl3.st_sign_x = 0; - ctrl3.st_sign_y = 0; - wkup_dur.st_sign_z = 1; - break; + case LIS2DUXS12_XL_ST_NEGATIVE: + ctrl3.st_sign_x = 0; + ctrl3.st_sign_y = 0; + wkup_dur.st_sign_z = 1; + break; - case LIS2DUXS12_XL_ST_DISABLE: - default: - ret = -1; - break; + case LIS2DUXS12_XL_ST_DISABLE: + default: + ret = -1; + break; } - ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t*)&ctrl3, 1); - ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t*)&wkup_dur, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_CTRL3, (uint8_t *)&ctrl3, 1); + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wkup_dur, 1); return ret; } @@ -764,19 +902,21 @@ int32_t lis2duxs12_self_test_sign_set(stmdev_ctx_t *ctx, lis2duxs12_xl_self_test * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_self_test_start(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2duxs12_self_test_start(const stmdev_ctx_t *ctx, uint8_t val) { lis2duxs12_self_test_t self_test; int32_t ret; - if (val != 1U && val != 2U) { + if (val != 1U && val != 2U) + { return -1; } - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t*)&self_test, 1); - if (ret == 0) { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t *)&self_test, 1); + if (ret == 0) + { self_test.st = (uint8_t) val; - ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t*)&self_test, 1); + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t *)&self_test, 1); } return ret; } @@ -788,15 +928,16 @@ int32_t lis2duxs12_self_test_start(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_self_test_stop(stmdev_ctx_t *ctx) +int32_t lis2duxs12_self_test_stop(const stmdev_ctx_t *ctx) { lis2duxs12_self_test_t self_test; int32_t ret; - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t*)&self_test, 1); - if (ret == 0) { + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t *)&self_test, 1); + if (ret == 0) + { self_test.st = 0; - ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t*)&self_test, 1); + ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_SELF_TEST, (uint8_t *)&self_test, 1); } return ret; } @@ -809,7 +950,7 @@ int32_t lis2duxs12_self_test_stop(stmdev_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_i3c_configure_set(stmdev_ctx_t *ctx, lis2duxs12_i3c_cfg_t *val) +int32_t lis2duxs12_i3c_configure_set(const stmdev_ctx_t *ctx, const lis2duxs12_i3c_cfg_t *val) { lis2duxs12_i3c_if_ctrl_t i3c_cfg; int32_t ret; @@ -834,7 +975,7 @@ int32_t lis2duxs12_i3c_configure_set(stmdev_ctx_t *ctx, lis2duxs12_i3c_cfg_t *va * @param val configuration params * @retval interface status (MANDATORY: return 0 -> no Error) * - */int32_t lis2duxs12_i3c_configure_get(stmdev_ctx_t *ctx, lis2duxs12_i3c_cfg_t *val) + */int32_t lis2duxs12_i3c_configure_get(const stmdev_ctx_t *ctx, lis2duxs12_i3c_cfg_t *val) { lis2duxs12_i3c_if_ctrl_t i3c_cfg; int32_t ret; @@ -844,26 +985,27 @@ int32_t lis2duxs12_i3c_configure_set(stmdev_ctx_t *ctx, lis2duxs12_i3c_cfg_t *va val->drstdaa_en = i3c_cfg.dis_drstdaa; val->asf_on = i3c_cfg.asf_on; - switch (val->bus_act_sel) { + switch (val->bus_act_sel) + { case LIS2DUXS12_I3C_BUS_AVAIL_TIME_20US: - val->bus_act_sel = LIS2DUXS12_I3C_BUS_AVAIL_TIME_20US; - break; + val->bus_act_sel = LIS2DUXS12_I3C_BUS_AVAIL_TIME_20US; + break; case LIS2DUXS12_I3C_BUS_AVAIL_TIME_50US: - val->bus_act_sel = LIS2DUXS12_I3C_BUS_AVAIL_TIME_50US; - break; + val->bus_act_sel = LIS2DUXS12_I3C_BUS_AVAIL_TIME_50US; + break; case LIS2DUXS12_I3C_BUS_AVAIL_TIME_1MS: - val->bus_act_sel = LIS2DUXS12_I3C_BUS_AVAIL_TIME_1MS; - break; + val->bus_act_sel = LIS2DUXS12_I3C_BUS_AVAIL_TIME_1MS; + break; case LIS2DUXS12_I3C_BUS_AVAIL_TIME_25MS: default: - val->bus_act_sel = LIS2DUXS12_I3C_BUS_AVAIL_TIME_25MS; - break; + val->bus_act_sel = LIS2DUXS12_I3C_BUS_AVAIL_TIME_25MS; + break; } - return ret; + return ret; } /** @@ -874,7 +1016,7 @@ int32_t lis2duxs12_i3c_configure_set(stmdev_ctx_t *ctx, lis2duxs12_i3c_cfg_t *va * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_mem_bank_set(stmdev_ctx_t *ctx, lis2duxs12_mem_bank_t val) +int32_t lis2duxs12_mem_bank_set(const stmdev_ctx_t *ctx, lis2duxs12_mem_bank_t val) { lis2duxs12_func_cfg_access_t func_cfg_access; int32_t ret; @@ -898,7 +1040,7 @@ int32_t lis2duxs12_mem_bank_set(stmdev_ctx_t *ctx, lis2duxs12_mem_bank_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_mem_bank_get(stmdev_ctx_t *ctx, lis2duxs12_mem_bank_t *val) +int32_t lis2duxs12_mem_bank_get(const stmdev_ctx_t *ctx, lis2duxs12_mem_bank_t *val) { lis2duxs12_func_cfg_access_t func_cfg_access; int32_t ret; @@ -907,11 +1049,11 @@ int32_t lis2duxs12_mem_bank_get(stmdev_ctx_t *ctx, lis2duxs12_mem_bank_t *val) switch ((func_cfg_access.emb_func_reg_access)) { - case LIS2DUXS12_MAIN_MEM_BANK: + case 0x0: *val = LIS2DUXS12_MAIN_MEM_BANK; break; - case LIS2DUXS12_EMBED_FUNC_MEM_BANK: + case 0x1: *val = LIS2DUXS12_EMBED_FUNC_MEM_BANK; break; @@ -933,7 +1075,7 @@ int32_t lis2duxs12_mem_bank_get(stmdev_ctx_t *ctx, lis2duxs12_mem_bank_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len) +int32_t lis2duxs12_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len) { lis2duxs12_page_address_t page_address; lis2duxs12_page_sel_t page_sel; @@ -963,7 +1105,7 @@ int32_t lis2duxs12_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf page_address.page_addr = lsb; ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_ADDRESS, (uint8_t *)&page_address, 1); - for (i = 0; ((i < len) && (ret == 0)); i++) + for (i = 0; i < len; i++) { ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_VALUE, &buf[i], 1); lsb++; @@ -977,6 +1119,11 @@ int32_t lis2duxs12_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf page_sel.not_used0 = 1; // Default value ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1); } + + if (ret != 0) + { + break; + } } page_sel.page_sel = 0; @@ -1005,7 +1152,7 @@ int32_t lis2duxs12_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len) +int32_t lis2duxs12_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len) { lis2duxs12_page_address_t page_address; lis2duxs12_page_sel_t page_sel; @@ -1035,7 +1182,7 @@ int32_t lis2duxs12_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, page_address.page_addr = lsb; ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_ADDRESS, (uint8_t *)&page_address, 1); - for (i = 0; ((i < len) && (ret == 0)); i++) + for (i = 0; i < len; i++) { ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_VALUE, &buf[i], 1); lsb++; @@ -1049,6 +1196,11 @@ int32_t lis2duxs12_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, page_sel.not_used0 = 1; // Default value ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_PAGE_SEL, (uint8_t *)&page_sel, 1); } + + if (ret != 0) + { + break; + } } page_sel.page_sel = 0; @@ -1078,6 +1230,45 @@ int32_t lis2duxs12_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, * */ +/** + * @brief External Clock Enable/Disable on INT pin.[set] + * + * @param ctx read / write interface definitions + * @param val 0: disable ext_clk - 1: enable ext_clk + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_ext_clk_en_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lis2duxs12_ext_clk_cfg_t clk; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EXT_CLK_CFG, (uint8_t *)&clk, 1); + clk.ext_clk_en = val; + ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EXT_CLK_CFG, (uint8_t *)&clk, 1); + + return ret; +} + +/** + * @brief External Clock Enable/Disable on INT pin.[get] + * + * @param ctx read / write interface definitions + * @param val 0: disable ext_clk - 1: enable ext_clk + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lis2duxs12_ext_clk_en_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lis2duxs12_ext_clk_cfg_t clk; + int32_t ret; + + ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EXT_CLK_CFG, (uint8_t *)&clk, 1); + *val = clk.ext_clk_en; + + return ret; +} + /** * @brief Electrical pin configuration.[set] * @@ -1086,7 +1277,7 @@ int32_t lis2duxs12_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_pin_conf_set(stmdev_ctx_t *ctx, lis2duxs12_pin_conf_t *val) +int32_t lis2duxs12_pin_conf_set(const stmdev_ctx_t *ctx, const lis2duxs12_pin_conf_t *val) { lis2duxs12_pin_ctrl_t pin_ctrl; int32_t ret; @@ -1116,7 +1307,7 @@ int32_t lis2duxs12_pin_conf_set(stmdev_ctx_t *ctx, lis2duxs12_pin_conf_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_pin_conf_get(stmdev_ctx_t *ctx, lis2duxs12_pin_conf_t *val) +int32_t lis2duxs12_pin_conf_get(const stmdev_ctx_t *ctx, lis2duxs12_pin_conf_t *val) { lis2duxs12_pin_ctrl_t pin_ctrl; int32_t ret; @@ -1141,7 +1332,7 @@ int32_t lis2duxs12_pin_conf_get(stmdev_ctx_t *ctx, lis2duxs12_pin_conf_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_int_pin_polarity_set(stmdev_ctx_t *ctx, lis2duxs12_int_pin_polarity_t val) +int32_t lis2duxs12_int_pin_polarity_set(const stmdev_ctx_t *ctx, lis2duxs12_int_pin_polarity_t val) { lis2duxs12_pin_ctrl_t pin_ctrl; int32_t ret; @@ -1165,7 +1356,7 @@ int32_t lis2duxs12_int_pin_polarity_set(stmdev_ctx_t *ctx, lis2duxs12_int_pin_po * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_int_pin_polarity_get(stmdev_ctx_t *ctx, lis2duxs12_int_pin_polarity_t *val) +int32_t lis2duxs12_int_pin_polarity_get(const stmdev_ctx_t *ctx, lis2duxs12_int_pin_polarity_t *val) { lis2duxs12_pin_ctrl_t pin_ctrl; int32_t ret; @@ -1174,11 +1365,11 @@ int32_t lis2duxs12_int_pin_polarity_get(stmdev_ctx_t *ctx, lis2duxs12_int_pin_po switch ((pin_ctrl.h_lactive)) { - case LIS2DUXS12_ACTIVE_HIGH: + case 0x0: *val = LIS2DUXS12_ACTIVE_HIGH; break; - case LIS2DUXS12_ACTIVE_LOW: + case 0x1: *val = LIS2DUXS12_ACTIVE_LOW; break; @@ -1197,7 +1388,7 @@ int32_t lis2duxs12_int_pin_polarity_get(stmdev_ctx_t *ctx, lis2duxs12_int_pin_po * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_spi_mode_set(stmdev_ctx_t *ctx, lis2duxs12_spi_mode val) +int32_t lis2duxs12_spi_mode_set(const stmdev_ctx_t *ctx, lis2duxs12_spi_mode val) { lis2duxs12_pin_ctrl_t pin_ctrl; int32_t ret; @@ -1221,7 +1412,7 @@ int32_t lis2duxs12_spi_mode_set(stmdev_ctx_t *ctx, lis2duxs12_spi_mode val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_spi_mode_get(stmdev_ctx_t *ctx, lis2duxs12_spi_mode *val) +int32_t lis2duxs12_spi_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_spi_mode *val) { lis2duxs12_pin_ctrl_t pin_ctrl; int32_t ret; @@ -1230,11 +1421,11 @@ int32_t lis2duxs12_spi_mode_get(stmdev_ctx_t *ctx, lis2duxs12_spi_mode *val) switch ((pin_ctrl.h_lactive)) { - case LIS2DUXS12_SPI_4_WIRE: + case 0x0: *val = LIS2DUXS12_SPI_4_WIRE; break; - case LIS2DUXS12_SPI_3_WIRE: + case 0x1: *val = LIS2DUXS12_SPI_3_WIRE; break; @@ -1253,7 +1444,8 @@ int32_t lis2duxs12_spi_mode_get(stmdev_ctx_t *ctx, lis2duxs12_spi_mode *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_pin_int1_route_set(stmdev_ctx_t *ctx, lis2duxs12_pin_int_route_t *val) +int32_t lis2duxs12_pin_int1_route_set(const stmdev_ctx_t *ctx, + const lis2duxs12_pin_int_route_t *val) { lis2duxs12_ctrl1_t ctrl1; lis2duxs12_ctrl2_t ctrl2; @@ -1314,7 +1506,7 @@ int32_t lis2duxs12_pin_int1_route_set(stmdev_ctx_t *ctx, lis2duxs12_pin_int_rout * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_pin_int1_route_get(stmdev_ctx_t *ctx, lis2duxs12_pin_int_route_t *val) +int32_t lis2duxs12_pin_int1_route_get(const stmdev_ctx_t *ctx, lis2duxs12_pin_int_route_t *val) { lis2duxs12_ctrl1_t ctrl1; lis2duxs12_ctrl2_t ctrl2; @@ -1353,8 +1545,8 @@ int32_t lis2duxs12_pin_int1_route_get(stmdev_ctx_t *ctx, lis2duxs12_pin_int_rout * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_emb_pin_int1_route_set(stmdev_ctx_t *ctx, - lis2duxs12_emb_pin_int_route_t *val) +int32_t lis2duxs12_emb_pin_int1_route_set(const stmdev_ctx_t *ctx, + const lis2duxs12_emb_pin_int_route_t *val) { lis2duxs12_emb_func_int1_t emb_func_int1; lis2duxs12_md1_cfg_t md1_cfg; @@ -1395,7 +1587,7 @@ int32_t lis2duxs12_emb_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_emb_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lis2duxs12_emb_pin_int1_route_get(const stmdev_ctx_t *ctx, lis2duxs12_emb_pin_int_route_t *val) { lis2duxs12_emb_func_int1_t emb_func_int1; @@ -1427,7 +1619,8 @@ int32_t lis2duxs12_emb_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_pin_int2_route_set(stmdev_ctx_t *ctx, lis2duxs12_pin_int_route_t *val) +int32_t lis2duxs12_pin_int2_route_set(const stmdev_ctx_t *ctx, + const lis2duxs12_pin_int_route_t *val) { lis2duxs12_ctrl3_t ctrl3; lis2duxs12_md2_cfg_t md2_cfg; @@ -1475,7 +1668,7 @@ int32_t lis2duxs12_pin_int2_route_set(stmdev_ctx_t *ctx, lis2duxs12_pin_int_rout * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_pin_int2_route_get(stmdev_ctx_t *ctx, lis2duxs12_pin_int_route_t *val) +int32_t lis2duxs12_pin_int2_route_get(const stmdev_ctx_t *ctx, lis2duxs12_pin_int_route_t *val) { lis2duxs12_ctrl3_t ctrl3; lis2duxs12_md2_cfg_t md2_cfg; @@ -1511,8 +1704,8 @@ int32_t lis2duxs12_pin_int2_route_get(stmdev_ctx_t *ctx, lis2duxs12_pin_int_rout * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_emb_pin_int2_route_set(stmdev_ctx_t *ctx, - lis2duxs12_emb_pin_int_route_t *val) +int32_t lis2duxs12_emb_pin_int2_route_set(const stmdev_ctx_t *ctx, + const lis2duxs12_emb_pin_int_route_t *val) { lis2duxs12_emb_func_int2_t emb_func_int2; lis2duxs12_md2_cfg_t md2_cfg; @@ -1553,7 +1746,7 @@ int32_t lis2duxs12_emb_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_emb_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lis2duxs12_emb_pin_int2_route_get(const stmdev_ctx_t *ctx, lis2duxs12_emb_pin_int_route_t *val) { lis2duxs12_emb_func_int2_t emb_func_int2; @@ -1585,7 +1778,7 @@ int32_t lis2duxs12_emb_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_int_config_set(stmdev_ctx_t *ctx, lis2duxs12_int_config_t *val) +int32_t lis2duxs12_int_config_set(const stmdev_ctx_t *ctx, const lis2duxs12_int_config_t *val) { lis2duxs12_interrupt_cfg_t interrupt_cfg; int32_t ret; @@ -1629,7 +1822,7 @@ int32_t lis2duxs12_int_config_set(stmdev_ctx_t *ctx, lis2duxs12_int_config_t *va * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_int_config_get(stmdev_ctx_t *ctx, lis2duxs12_int_config_t *val) +int32_t lis2duxs12_int_config_get(const stmdev_ctx_t *ctx, lis2duxs12_int_config_t *val) { lis2duxs12_interrupt_cfg_t interrupt_cfg; int32_t ret; @@ -1666,7 +1859,8 @@ int32_t lis2duxs12_int_config_get(stmdev_ctx_t *ctx, lis2duxs12_int_config_t *va * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_embedded_int_config_set(stmdev_ctx_t *ctx, lis2duxs12_embedded_int_config_t val) +int32_t lis2duxs12_embedded_int_cfg_set(const stmdev_ctx_t *ctx, + lis2duxs12_embedded_int_config_t val) { lis2duxs12_page_rw_t page_rw; int32_t ret; @@ -1704,7 +1898,8 @@ int32_t lis2duxs12_embedded_int_config_set(stmdev_ctx_t *ctx, lis2duxs12_embedde * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_embedded_int_config_get(stmdev_ctx_t *ctx, lis2duxs12_embedded_int_config_t *val) +int32_t lis2duxs12_embedded_int_cfg_get(const stmdev_ctx_t *ctx, + lis2duxs12_embedded_int_config_t *val) { lis2duxs12_page_rw_t page_rw; int32_t ret; @@ -1714,9 +1909,12 @@ int32_t lis2duxs12_embedded_int_config_get(stmdev_ctx_t *ctx, lis2duxs12_embedde { ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_PAGE_RW, (uint8_t *)&page_rw, 1); - if (page_rw.emb_func_lir == 0U) { + if (page_rw.emb_func_lir == 0U) + { *val = LIS2DUXS12_EMBEDDED_INT_LEVEL; - } else { + } + else + { *val = LIS2DUXS12_EMBEDDED_INT_LATCHED; } } @@ -1746,7 +1944,7 @@ int32_t lis2duxs12_embedded_int_config_get(stmdev_ctx_t *ctx, lis2duxs12_embedde * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_fifo_mode_set(stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t val) +int32_t lis2duxs12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t val) { lis2duxs12_ctrl4_t ctrl4; lis2duxs12_fifo_ctrl_t fifo_ctrl; @@ -1767,7 +1965,8 @@ int32_t lis2duxs12_fifo_mode_set(stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t val) ctrl4.fifo_en = 1; fifo_ctrl.fifo_mode = ((uint8_t)val.operation & 0x7U); } - else { + else + { ctrl4.fifo_en = 0; } @@ -1787,7 +1986,8 @@ int32_t lis2duxs12_fifo_mode_set(stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t val) fifo_ctrl.cfg_chg_en = val.cfg_change_in_fifo; /* set watermark */ - if (val.watermark > 0U) { + if (val.watermark > 0U) + { fifo_ctrl.stop_on_fth = 1; fifo_wtm.fth = val.watermark; } @@ -1809,7 +2009,7 @@ int32_t lis2duxs12_fifo_mode_set(stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_fifo_mode_get(stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t *val) +int32_t lis2duxs12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t *val) { lis2duxs12_ctrl4_t ctrl4; lis2duxs12_fifo_ctrl_t fifo_ctrl; @@ -1825,10 +2025,12 @@ int32_t lis2duxs12_fifo_mode_get(stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t *val) if (ret == 0) { /* get FIFO mode */ - if (ctrl4.fifo_en == 0U) { + if (ctrl4.fifo_en == 0U) + { val->operation = LIS2DUXS12_FIFO_OFF; } - else { + else + { val->operation = (lis2duxs12_operation_t)fifo_ctrl.fifo_mode; } val->cfg_change_in_fifo = fifo_ctrl.cfg_chg_en; @@ -1858,7 +2060,7 @@ int32_t lis2duxs12_fifo_mode_get(stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lis2duxs12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff; int32_t ret; @@ -1870,7 +2072,7 @@ int32_t lis2duxs12_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) return ret; } -int32_t lis2duxs12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2duxs12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2duxs12_fifo_status1_t fifo_status1; int32_t ret; @@ -1882,7 +2084,7 @@ int32_t lis2duxs12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) return ret; } -int32_t lis2duxs12_fifo_sensor_tag_get(stmdev_ctx_t *ctx, lis2duxs12_fifo_sensor_tag_t *val) +int32_t lis2duxs12_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, lis2duxs12_fifo_sensor_tag_t *val) { lis2duxs12_fifo_data_out_tag_t fifo_tag; int32_t ret; @@ -1894,7 +2096,7 @@ int32_t lis2duxs12_fifo_sensor_tag_get(stmdev_ctx_t *ctx, lis2duxs12_fifo_sensor return ret; } -int32_t lis2duxs12_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis2duxs12_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1903,8 +2105,8 @@ int32_t lis2duxs12_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) return ret; } -int32_t lis2duxs12_fifo_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md, - lis2duxs12_fifo_mode_t *fmd, +int32_t lis2duxs12_fifo_data_get(const stmdev_ctx_t *ctx, const lis2duxs12_md_t *md, + const lis2duxs12_fifo_mode_t *fmd, lis2duxs12_fifo_data_t *data) { lis2duxs12_fifo_data_out_tag_t fifo_tag; @@ -1914,20 +2116,23 @@ int32_t lis2duxs12_fifo_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md, ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FIFO_DATA_OUT_TAG, (uint8_t *)&fifo_tag, 1); data->tag = fifo_tag.tag_sensor; - switch (fifo_tag.tag_sensor) { - case LIS2DUXS12_XL_ONLY_2X_TAG: - case LIS2DUXS12_XL_ONLY_2X_TAG_2ND: + switch (fifo_tag.tag_sensor) + { + case 0x3: + case 0x1E: /* A FIFO sample consists of 2X 8-bits 3-axis XL at ODR/2 */ ret = lis2duxs12_fifo_out_raw_get(ctx, fifo_raw); - for (i = 0; i < 3; i++) { + for (i = 0; i < 3; i++) + { data->xl[0].raw[i] = (int16_t)fifo_raw[i] * 256; data->xl[1].raw[i] = (int16_t)fifo_raw[3 + i] * 256; } break; - case LIS2DUXS12_XL_AND_QVAR: - case LIS2DUXS12_XL_TEMP_TAG: + case 0x1F: + case 0x2: ret = lis2duxs12_fifo_out_raw_get(ctx, fifo_raw); - if (fmd->xl_only == 0x0U) { + if (fmd->xl_only == 0x0U) + { /* A FIFO sample consists of 12-bits 3-axis XL + T at ODR*/ data->xl[0].raw[0] = (int16_t)fifo_raw[0]; data->xl[0].raw[0] = (data->xl[0].raw[0] + (int16_t)fifo_raw[1] * 256) * 16; @@ -1937,72 +2142,80 @@ int32_t lis2duxs12_fifo_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md, data->xl[0].raw[2] = data->xl[0].raw[2] + ((int16_t)fifo_raw[4] * 256) * 16; data->heat.raw = (int16_t)fifo_raw[4] / 16; data->heat.raw = (data->heat.raw + ((int16_t)fifo_raw[5] * 16)) * 16; - if (fifo_tag.tag_sensor == (uint8_t)LIS2DUXS12_XL_TEMP_TAG) { - data->heat.deg_c = lis2duxs12_from_lsb_to_celsius(data->heat.raw); - } else { - data->ah_qvar.raw = data->heat.raw; - data->ah_qvar.mv = lis2duxs12_from_lsb_to_mv(data->ah_qvar.raw); - } - } else { + if (fifo_tag.tag_sensor == (uint8_t)LIS2DUXS12_XL_TEMP_TAG) + { + data->heat.deg_c = lis2duxs12_from_lsb_to_celsius(data->heat.raw); + } + else + { + data->ah_qvar.raw = data->heat.raw; + data->ah_qvar.mv = lis2duxs12_from_lsb_to_mv(data->ah_qvar.raw); + } + } + else + { /* A FIFO sample consists of 16-bits 3-axis XL at ODR */ data->xl[0].raw[0] = (int16_t)fifo_raw[0] + (int16_t)fifo_raw[1] * 256; data->xl[0].raw[1] = (int16_t)fifo_raw[1] + (int16_t)fifo_raw[3] * 256; data->xl[0].raw[2] = (int16_t)fifo_raw[2] + (int16_t)fifo_raw[5] * 256; } break; - case LIS2DUXS12_TIMESTAMP_TAG: - ret = lis2duxs12_fifo_out_raw_get(ctx, fifo_raw); + case 0x4: + ret = lis2duxs12_fifo_out_raw_get(ctx, fifo_raw); - data->cfg_chg.cfg_change = fifo_raw[0] >> 7; - data->cfg_chg.odr = (fifo_raw[0] >> 3) & 0xFU; - data->cfg_chg.bw = (fifo_raw[0] >> 1) & 0x3U; - data->cfg_chg.lp_hp = fifo_raw[0] & 0x1U; - data->cfg_chg.qvar_en = fifo_raw[1] >> 7; - data->cfg_chg.fs = (fifo_raw[1] >> 5) & 0x3U; - data->cfg_chg.dec_ts = (fifo_raw[1] >> 3) & 0x3U; - data->cfg_chg.odr_xl_batch = fifo_raw[1] & 0x7U; + data->cfg_chg.cfg_change = fifo_raw[0] >> 7; + data->cfg_chg.odr = (fifo_raw[0] >> 3) & 0xFU; + data->cfg_chg.bw = (fifo_raw[0] >> 1) & 0x3U; + data->cfg_chg.lp_hp = fifo_raw[0] & 0x1U; + data->cfg_chg.qvar_en = fifo_raw[1] >> 7; + data->cfg_chg.fs = (fifo_raw[1] >> 5) & 0x3U; + data->cfg_chg.dec_ts = (fifo_raw[1] >> 3) & 0x3U; + data->cfg_chg.odr_xl_batch = fifo_raw[1] & 0x7U; - data->cfg_chg.timestamp = fifo_raw[5]; - data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[4]; - data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[3]; - data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[2]; - break; + data->cfg_chg.timestamp = fifo_raw[5]; + data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[4]; + data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[3]; + data->cfg_chg.timestamp = (data->cfg_chg.timestamp * 256U) + fifo_raw[2]; + break; - case LIS2DUXS12_STEP_COUNTER_TAG: - ret = lis2duxs12_fifo_out_raw_get(ctx, fifo_raw); + case 0x12: + ret = lis2duxs12_fifo_out_raw_get(ctx, fifo_raw); - data->pedo.steps = fifo_raw[1]; - data->pedo.steps = (data->pedo.steps * 256U) + fifo_raw[0]; + data->pedo.steps = fifo_raw[1]; + data->pedo.steps = (data->pedo.steps * 256U) + fifo_raw[0]; - data->pedo.timestamp = fifo_raw[5]; - data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[4]; - data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[3]; - data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[2]; + data->pedo.timestamp = fifo_raw[5]; + data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[4]; + data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[3]; + data->pedo.timestamp = (data->pedo.timestamp * 256U) + fifo_raw[2]; - break; + break; - case LIS2DUXS12_FIFO_EMPTY: - default: - break; + case 0x0: + default: + /* do nothing */ + break; } - for (i = 0; i < 3; i++) { - switch ( md->fs ) { + for (i = 0; i < 3; i++) + { + switch (md->fs) + { case LIS2DUXS12_2g: - data->xl[0].mg[i] =lis2duxs12_from_fs2g_to_mg(data->xl[0].raw[i]); - data->xl[1].mg[i] =lis2duxs12_from_fs2g_to_mg(data->xl[1].raw[i]); + data->xl[0].mg[i] = lis2duxs12_from_fs2g_to_mg(data->xl[0].raw[i]); + data->xl[1].mg[i] = lis2duxs12_from_fs2g_to_mg(data->xl[1].raw[i]); break; case LIS2DUXS12_4g: - data->xl[0].mg[i] =lis2duxs12_from_fs4g_to_mg(data->xl[0].raw[i]); - data->xl[1].mg[i] =lis2duxs12_from_fs4g_to_mg(data->xl[1].raw[i]); + data->xl[0].mg[i] = lis2duxs12_from_fs4g_to_mg(data->xl[0].raw[i]); + data->xl[1].mg[i] = lis2duxs12_from_fs4g_to_mg(data->xl[1].raw[i]); break; case LIS2DUXS12_8g: - data->xl[0].mg[i] =lis2duxs12_from_fs8g_to_mg(data->xl[0].raw[i]); - data->xl[1].mg[i] =lis2duxs12_from_fs8g_to_mg(data->xl[1].raw[i]); + data->xl[0].mg[i] = lis2duxs12_from_fs8g_to_mg(data->xl[0].raw[i]); + data->xl[1].mg[i] = lis2duxs12_from_fs8g_to_mg(data->xl[1].raw[i]); break; case LIS2DUXS12_16g: - data->xl[0].mg[i] =lis2duxs12_from_fs16g_to_mg(data->xl[0].raw[i]); - data->xl[1].mg[i] =lis2duxs12_from_fs16g_to_mg(data->xl[1].raw[i]); + data->xl[0].mg[i] = lis2duxs12_from_fs16g_to_mg(data->xl[0].raw[i]); + data->xl[1].mg[i] = lis2duxs12_from_fs16g_to_mg(data->xl[1].raw[i]); break; default: data->xl[0].mg[i] = 0.0f; @@ -2022,7 +2235,7 @@ int32_t lis2duxs12_fifo_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_ah_qvar_mode_set(stmdev_ctx_t *ctx, +int32_t lis2duxs12_ah_qvar_mode_set(const stmdev_ctx_t *ctx, lis2duxs12_ah_qvar_mode_t val) { lis2duxs12_ah_qvar_cfg_t ah_qvar_cfg; @@ -2050,7 +2263,7 @@ int32_t lis2duxs12_ah_qvar_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_ah_qvar_mode_get(stmdev_ctx_t *ctx, +int32_t lis2duxs12_ah_qvar_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_ah_qvar_mode_t *val) { lis2duxs12_ah_qvar_cfg_t ah_qvar_cfg; @@ -2060,19 +2273,19 @@ int32_t lis2duxs12_ah_qvar_mode_get(stmdev_ctx_t *ctx, switch (ah_qvar_cfg.ah_qvar_gain) { - case LIS2DUXS12_GAIN_0_5: + case 0x0: val->ah_qvar_gain = LIS2DUXS12_GAIN_0_5; break; - case LIS2DUXS12_GAIN_1: + case 0x1: val->ah_qvar_gain = LIS2DUXS12_GAIN_1; break; - case LIS2DUXS12_GAIN_2: + case 0x2: val->ah_qvar_gain = LIS2DUXS12_GAIN_2; break; - case LIS2DUXS12_GAIN_4: + case 0x3: default: val->ah_qvar_gain = LIS2DUXS12_GAIN_4; break; @@ -2080,19 +2293,19 @@ int32_t lis2duxs12_ah_qvar_mode_get(stmdev_ctx_t *ctx, switch (ah_qvar_cfg.ah_qvar_c_zin) { - case LIS2DUXS12_520MOhm: + case 0x0: val->ah_qvar_zin = LIS2DUXS12_520MOhm; break; - case LIS2DUXS12_175MOhm: + case 0x1: val->ah_qvar_zin = LIS2DUXS12_175MOhm; break; - case LIS2DUXS12_310MOhm: + case 0x2: val->ah_qvar_zin = LIS2DUXS12_310MOhm; break; - case LIS2DUXS12_75MOhm: + case 0x3: default: val->ah_qvar_zin = LIS2DUXS12_75MOhm; break; @@ -2100,11 +2313,11 @@ int32_t lis2duxs12_ah_qvar_mode_get(stmdev_ctx_t *ctx, switch (ah_qvar_cfg.ah_qvar_notch_cutoff) { - case LIS2DUXS12_NOTCH_50HZ: + case 0x0: val->ah_qvar_notch = LIS2DUXS12_NOTCH_50HZ; break; - case LIS2DUXS12_NOTCH_60HZ: + case 0x1: default: val->ah_qvar_notch = LIS2DUXS12_NOTCH_60HZ; break; @@ -2130,7 +2343,7 @@ int32_t lis2duxs12_ah_qvar_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_stpcnt_mode_set(stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mode_t val) +int32_t lis2duxs12_stpcnt_mode_set(const stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mode_t val) { lis2duxs12_emb_func_en_a_t emb_func_en_a; lis2duxs12_emb_func_en_b_t emb_func_en_b; @@ -2143,7 +2356,8 @@ int32_t lis2duxs12_stpcnt_mode_set(stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mode_t v ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_FIFO_EN, (uint8_t *)&emb_func_fifo_en, 1); - if ((val.false_step_rej == PROPERTY_ENABLE) && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) == PROPERTY_DISABLE)) + if ((val.false_step_rej == PROPERTY_ENABLE) + && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) == PROPERTY_DISABLE)) { emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE; } @@ -2155,12 +2369,14 @@ int32_t lis2duxs12_stpcnt_mode_set(stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mode_t v ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); - ret += lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + ret += lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_CMD_REG, + (uint8_t *)&pedo_cmd_reg, 1); if (ret == 0) { pedo_cmd_reg.fp_rejection_en = val.false_step_rej; - ret += lis2duxs12_ln_pg_write(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + ret += lis2duxs12_ln_pg_write(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_CMD_REG, + (uint8_t *)&pedo_cmd_reg, 1); } return ret; @@ -2174,7 +2390,7 @@ int32_t lis2duxs12_stpcnt_mode_set(stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mode_t v * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_stpcnt_mode_get(stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mode_t *val) +int32_t lis2duxs12_stpcnt_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mode_t *val) { lis2duxs12_emb_func_en_a_t emb_func_en_a; lis2duxs12_pedo_cmd_reg_t pedo_cmd_reg; @@ -2184,7 +2400,8 @@ int32_t lis2duxs12_stpcnt_mode_get(stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mode_t * ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); - ret += lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + ret += lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_CMD_REG, + (uint8_t *)&pedo_cmd_reg, 1); val->false_step_rej = pedo_cmd_reg.fp_rejection_en; val->step_counter_enable = emb_func_en_a.pedo_en; @@ -2199,7 +2416,7 @@ int32_t lis2duxs12_stpcnt_mode_get(stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mode_t * * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lis2duxs12_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -2222,7 +2439,7 @@ int32_t lis2duxs12_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_stpcnt_rst_step_set(stmdev_ctx_t *ctx) +int32_t lis2duxs12_stpcnt_rst_step_set(const stmdev_ctx_t *ctx) { lis2duxs12_emb_func_src_t emb_func_src; int32_t ret; @@ -2248,13 +2465,14 @@ int32_t lis2duxs12_stpcnt_rst_step_set(stmdev_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2duxs12_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2duxs12_pedo_deb_steps_conf_t pedo_deb_steps_conf; int32_t ret; pedo_deb_steps_conf.deb_step = val; - ret = lis2duxs12_ln_pg_write(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + ret = lis2duxs12_ln_pg_write(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_DEB_STEPS_CONF, + (uint8_t *)&pedo_deb_steps_conf, 1); return ret; } @@ -2267,12 +2485,13 @@ int32_t lis2duxs12_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2duxs12_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2duxs12_pedo_deb_steps_conf_t pedo_deb_steps_conf; int32_t ret; - ret = lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + ret = lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_DEB_STEPS_CONF, + (uint8_t *)&pedo_deb_steps_conf, 1); *val = pedo_deb_steps_conf.deb_step; return ret; @@ -2286,7 +2505,7 @@ int32_t lis2duxs12_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lis2duxs12_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -2294,7 +2513,8 @@ int32_t lis2duxs12_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val) buff[1] = (uint8_t)(val / 256U); buff[0] = (uint8_t)(val - (buff[1] * 256U)); - ret = lis2duxs12_ln_pg_write(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_SC_DELTAT_L, (uint8_t *)buff, 2); + ret = lis2duxs12_ln_pg_write(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_SC_DELTAT_L, + (uint8_t *)buff, 2); return ret; } @@ -2307,12 +2527,13 @@ int32_t lis2duxs12_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lis2duxs12_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; - ret = lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_SC_DELTAT_L, (uint8_t *)buff, 2); + ret = lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_EMB_ADV_PG_0 + LIS2DUXS12_PEDO_SC_DELTAT_L, + (uint8_t *)buff, 2); *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -2338,7 +2559,7 @@ int32_t lis2duxs12_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2duxs12_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2duxs12_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -2364,7 +2585,7 @@ int32_t lis2duxs12_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2duxs12_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2duxs12_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -2400,7 +2621,7 @@ int32_t lis2duxs12_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2duxs12_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2duxs12_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -2426,7 +2647,7 @@ int32_t lis2duxs12_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2duxs12_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2duxs12_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -2463,7 +2684,7 @@ int32_t lis2duxs12_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_ff_duration_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2duxs12_ff_duration_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2duxs12_wake_up_dur_t wake_up_dur; lis2duxs12_free_fall_t free_fall; @@ -2495,18 +2716,14 @@ int32_t lis2duxs12_ff_duration_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_ff_duration_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2duxs12_ff_duration_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2duxs12_wake_up_dur_t wake_up_dur; lis2duxs12_free_fall_t free_fall; int32_t ret; ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); - - if (ret == 0) - { - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1); - } + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FREE_FALL, (uint8_t *)&free_fall, 1); *val = (wake_up_dur.ff_dur << 5) | free_fall.ff_dur; @@ -2521,7 +2738,7 @@ int32_t lis2duxs12_ff_duration_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_ff_thresholds_set(stmdev_ctx_t *ctx, lis2duxs12_ff_thresholds_t val) +int32_t lis2duxs12_ff_thresholds_set(const stmdev_ctx_t *ctx, lis2duxs12_ff_thresholds_t val) { lis2duxs12_free_fall_t free_fall; int32_t ret; @@ -2541,7 +2758,7 @@ int32_t lis2duxs12_ff_thresholds_set(stmdev_ctx_t *ctx, lis2duxs12_ff_thresholds * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_ff_thresholds_get(stmdev_ctx_t *ctx, lis2duxs12_ff_thresholds_t *val) +int32_t lis2duxs12_ff_thresholds_get(const stmdev_ctx_t *ctx, lis2duxs12_ff_thresholds_t *val) { lis2duxs12_free_fall_t free_fall; int32_t ret; @@ -2550,35 +2767,35 @@ int32_t lis2duxs12_ff_thresholds_get(stmdev_ctx_t *ctx, lis2duxs12_ff_thresholds switch (free_fall.ff_ths) { - case LIS2DUXS12_156_mg: + case 0x0: *val = LIS2DUXS12_156_mg; break; - case LIS2DUXS12_219_mg: + case 0x1: *val = LIS2DUXS12_219_mg; break; - case LIS2DUXS12_250_mg: + case 0x2: *val = LIS2DUXS12_250_mg; break; - case LIS2DUXS12_312_mg: + case 0x3: *val = LIS2DUXS12_312_mg; break; - case LIS2DUXS12_344_mg: + case 0x4: *val = LIS2DUXS12_344_mg; break; - case LIS2DUXS12_406_mg: + case 0x5: *val = LIS2DUXS12_406_mg; break; - case LIS2DUXS12_469_mg: + case 0x6: *val = LIS2DUXS12_469_mg; break; - case LIS2DUXS12_500_mg: + case 0x7: *val = LIS2DUXS12_500_mg; break; @@ -2609,7 +2826,7 @@ int32_t lis2duxs12_ff_thresholds_get(stmdev_ctx_t *ctx, lis2duxs12_ff_thresholds * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_sixd_config_set(stmdev_ctx_t *ctx, lis2duxs12_sixd_config_t val) +int32_t lis2duxs12_sixd_config_set(const stmdev_ctx_t *ctx, lis2duxs12_sixd_config_t val) { lis2duxs12_sixd_t sixd; int32_t ret; @@ -2618,7 +2835,7 @@ int32_t lis2duxs12_sixd_config_set(stmdev_ctx_t *ctx, lis2duxs12_sixd_config_t v if (ret == 0) { - sixd.d4d_en = ((uint8_t)val.mode); + sixd.d4d_en = ((uint8_t)val.mode); sixd.d6d_ths = ((uint8_t)val.threshold); ret = lis2duxs12_write_reg(ctx, LIS2DUXS12_SIXD, (uint8_t *)&sixd, 1); } @@ -2634,7 +2851,7 @@ int32_t lis2duxs12_sixd_config_set(stmdev_ctx_t *ctx, lis2duxs12_sixd_config_t v * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_sixd_config_get(stmdev_ctx_t *ctx, lis2duxs12_sixd_config_t *val) +int32_t lis2duxs12_sixd_config_get(const stmdev_ctx_t *ctx, lis2duxs12_sixd_config_t *val) { lis2duxs12_sixd_t sixd; int32_t ret; @@ -2645,19 +2862,19 @@ int32_t lis2duxs12_sixd_config_get(stmdev_ctx_t *ctx, lis2duxs12_sixd_config_t * switch ((sixd.d6d_ths)) { - case LIS2DUXS12_DEG_80: + case 0x0: val->threshold = LIS2DUXS12_DEG_80; break; - case LIS2DUXS12_DEG_70: + case 0x1: val->threshold = LIS2DUXS12_DEG_70; break; - case LIS2DUXS12_DEG_60: + case 0x2: val->threshold = LIS2DUXS12_DEG_60; break; - case LIS2DUXS12_DEG_50: + case 0x3: val->threshold = LIS2DUXS12_DEG_50; break; @@ -2689,7 +2906,7 @@ int32_t lis2duxs12_sixd_config_get(stmdev_ctx_t *ctx, lis2duxs12_sixd_config_t * * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_wakeup_config_set(stmdev_ctx_t *ctx, lis2duxs12_wakeup_config_t val) +int32_t lis2duxs12_wakeup_config_set(const stmdev_ctx_t *ctx, lis2duxs12_wakeup_config_t val) { lis2duxs12_wake_up_ths_t wup_ths; lis2duxs12_wake_up_dur_t wup_dur; @@ -2717,11 +2934,14 @@ int32_t lis2duxs12_wakeup_config_set(stmdev_ctx_t *ctx, lis2duxs12_wakeup_config wup_ths.sleep_on = (uint8_t)val.wake_enable; ctrl4.inact_odr = (uint8_t)val.inact_odr; - if (val.wake_enable == LIS2DUXS12_SLEEP_ON) { + if (val.wake_enable == LIS2DUXS12_SLEEP_ON) + { ctrl1.wu_x_en = 1; ctrl1.wu_y_en = 1; ctrl1.wu_z_en = 1; - } else { + } + else + { ctrl1.wu_x_en = 0; ctrl1.wu_y_en = 0; ctrl1.wu_z_en = 0; @@ -2746,7 +2966,7 @@ int32_t lis2duxs12_wakeup_config_set(stmdev_ctx_t *ctx, lis2duxs12_wakeup_config * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2duxs12_wakeup_config_get(stmdev_ctx_t *ctx, lis2duxs12_wakeup_config_t *val) +int32_t lis2duxs12_wakeup_config_get(const stmdev_ctx_t *ctx, lis2duxs12_wakeup_config_t *val) { lis2duxs12_wake_up_ths_t wup_ths; lis2duxs12_wake_up_dur_t wup_dur; @@ -2763,26 +2983,27 @@ int32_t lis2duxs12_wakeup_config_get(stmdev_ctx_t *ctx, lis2duxs12_wakeup_config if (ret == 0) { - switch(wup_dur.wake_dur) { - case 0x0: - val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ? - LIS2DUXS12_3_ODR : LIS2DUXS12_0_ODR; - break; + switch (wup_dur.wake_dur) + { + case 0x0: + val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ? + LIS2DUXS12_3_ODR : LIS2DUXS12_0_ODR; + break; - case 0x1: - val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ? - LIS2DUXS12_7_ODR : LIS2DUXS12_1_ODR; - break; + case 0x1: + val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ? + LIS2DUXS12_7_ODR : LIS2DUXS12_1_ODR; + break; - case 0x2: - val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ? - LIS2DUXS12_11_ODR : LIS2DUXS12_2_ODR; - break; + case 0x2: + val->wake_dur = (wup_dur_ext.wu_dur_extended == 1U) ? + LIS2DUXS12_11_ODR : LIS2DUXS12_2_ODR; + break; - case 0x3: - default: - val->wake_dur = LIS2DUXS12_15_ODR; - break; + case 0x3: + default: + val->wake_dur = LIS2DUXS12_15_ODR; + break; } val->sleep_dur = wup_dur.sleep_dur; @@ -2801,7 +3022,7 @@ int32_t lis2duxs12_wakeup_config_get(stmdev_ctx_t *ctx, lis2duxs12_wakeup_config * */ -int32_t lis2duxs12_tap_config_set(stmdev_ctx_t *ctx, lis2duxs12_tap_config_t val) +int32_t lis2duxs12_tap_config_set(const stmdev_ctx_t *ctx, lis2duxs12_tap_config_t val) { lis2duxs12_tap_cfg0_t tap_cfg0; lis2duxs12_tap_cfg1_t tap_cfg1; @@ -2851,7 +3072,7 @@ int32_t lis2duxs12_tap_config_set(stmdev_ctx_t *ctx, lis2duxs12_tap_config_t val return ret; } -int32_t lis2duxs12_tap_config_get(stmdev_ctx_t *ctx, lis2duxs12_tap_config_t *val) +int32_t lis2duxs12_tap_config_get(const stmdev_ctx_t *ctx, lis2duxs12_tap_config_t *val) { lis2duxs12_tap_cfg0_t tap_cfg0; lis2duxs12_tap_cfg1_t tap_cfg1; @@ -2913,7 +3134,7 @@ int32_t lis2duxs12_tap_config_get(stmdev_ctx_t *ctx, lis2duxs12_tap_config_t *va * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2duxs12_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2duxs12_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2duxs12_interrupt_cfg_t int_cfg; int32_t ret; @@ -2937,7 +3158,7 @@ int32_t lis2duxs12_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2duxs12_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2duxs12_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2duxs12_interrupt_cfg_t int_cfg; int32_t ret; @@ -2958,7 +3179,7 @@ int32_t lis2duxs12_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2duxs12_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t lis2duxs12_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; @@ -2994,8 +3215,8 @@ int32_t lis2duxs12_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2duxs12_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, - uint8_t *val) +int32_t lis2duxs12_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, + uint8_t *val) { lis2duxs12_emb_func_status_t emb_func_status; int32_t ret; @@ -3023,7 +3244,7 @@ int32_t lis2duxs12_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2duxs12_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2duxs12_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; @@ -3038,7 +3259,7 @@ int32_t lis2duxs12_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val) emb_func_en_b.fsm_en = (uint8_t)val; ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, - (uint8_t *)&emb_func_en_b, 1); + (uint8_t *)&emb_func_en_b, 1); } ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); @@ -3054,7 +3275,7 @@ int32_t lis2duxs12_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2duxs12_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2duxs12_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -3085,7 +3306,7 @@ int32_t lis2duxs12_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2duxs12_fsm_enable_set(stmdev_ctx_t *ctx, +int32_t lis2duxs12_fsm_enable_set(const stmdev_ctx_t *ctx, lis2duxs12_emb_fsm_enable_t *val) { lis2duxs12_emb_func_en_b_t emb_func_en_b; @@ -3137,7 +3358,7 @@ int32_t lis2duxs12_fsm_enable_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2duxs12_fsm_enable_get(stmdev_ctx_t *ctx, +int32_t lis2duxs12_fsm_enable_get(const stmdev_ctx_t *ctx, lis2duxs12_emb_fsm_enable_t *val) { int32_t ret; @@ -3164,7 +3385,7 @@ int32_t lis2duxs12_fsm_enable_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2duxs12_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lis2duxs12_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -3192,7 +3413,7 @@ int32_t lis2duxs12_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2duxs12_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lis2duxs12_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -3218,7 +3439,7 @@ int32_t lis2duxs12_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) * @param val register FSM_STATUS_MAINPAGE * */ -int32_t lis2duxs12_fsm_status_get(stmdev_ctx_t *ctx, +int32_t lis2duxs12_fsm_status_get(const stmdev_ctx_t *ctx, lis2duxs12_fsm_status_mainpage_t *val) { return lis2duxs12_read_reg(ctx, LIS2DUXS12_FSM_STATUS_MAINPAGE, @@ -3233,7 +3454,7 @@ int32_t lis2duxs12_fsm_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2duxs12_fsm_out_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2duxs12_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -3257,8 +3478,8 @@ int32_t lis2duxs12_fsm_out_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2duxs12_fsm_data_rate_set(stmdev_ctx_t *ctx, - lis2duxs12_fsm_val_odr_t val) +int32_t lis2duxs12_fsm_data_rate_set(const stmdev_ctx_t *ctx, + lis2duxs12_fsm_val_odr_t val) { lis2duxs12_fsm_odr_t fsm_odr_reg; int32_t ret; @@ -3288,49 +3509,43 @@ int32_t lis2duxs12_fsm_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2duxs12_fsm_data_rate_get(stmdev_ctx_t *ctx, - lis2duxs12_fsm_val_odr_t *val) +int32_t lis2duxs12_fsm_data_rate_get(const stmdev_ctx_t *ctx, + lis2duxs12_fsm_val_odr_t *val) { lis2duxs12_fsm_odr_t fsm_odr_reg; int32_t ret; ret = lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_EMBED_FUNC_MEM_BANK); - - if (ret == 0) - { - ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_FSM_ODR, - (uint8_t *)&fsm_odr_reg, 1); - } - + ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_FSM_ODR, (uint8_t *)&fsm_odr_reg, 1); ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); switch (fsm_odr_reg.fsm_odr) { - case LIS2DUXS12_ODR_FSM_12Hz5: + case 0: *val = LIS2DUXS12_ODR_FSM_12Hz5; break; - case LIS2DUXS12_ODR_FSM_25Hz: + case 1: *val = LIS2DUXS12_ODR_FSM_25Hz; break; - case LIS2DUXS12_ODR_FSM_50Hz: + case 2: *val = LIS2DUXS12_ODR_FSM_50Hz; break; - case LIS2DUXS12_ODR_FSM_100Hz: + case 3: *val = LIS2DUXS12_ODR_FSM_100Hz; break; - case LIS2DUXS12_ODR_FSM_200Hz: + case 4: *val = LIS2DUXS12_ODR_FSM_200Hz; break; - case LIS2DUXS12_ODR_FSM_400Hz: + case 5: *val = LIS2DUXS12_ODR_FSM_400Hz; break; - case LIS2DUXS12_ODR_FSM_800Hz: + case 6: *val = LIS2DUXS12_ODR_FSM_800Hz; break; @@ -3350,7 +3565,7 @@ int32_t lis2duxs12_fsm_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2duxs12_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2duxs12_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2duxs12_emb_func_init_b_t emb_func_init_b; int32_t ret; @@ -3365,7 +3580,7 @@ int32_t lis2duxs12_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) emb_func_init_b.fsm_init = (uint8_t)val; ret += lis2duxs12_write_reg(ctx, LIS2DUXS12_EMB_FUNC_INIT_B, - (uint8_t *)&emb_func_init_b, 1); + (uint8_t *)&emb_func_init_b, 1); } ret += lis2duxs12_mem_bank_set(ctx, LIS2DUXS12_MAIN_MEM_BANK); @@ -3381,7 +3596,7 @@ int32_t lis2duxs12_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2duxs12_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2duxs12_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2duxs12_emb_func_init_b_t emb_func_init_b; int32_t ret; @@ -3409,7 +3624,7 @@ int32_t lis2duxs12_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2duxs12_fsm_fifo_en_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2duxs12_fsm_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2duxs12_emb_func_fifo_en_t fifo_reg; int32_t ret; @@ -3436,7 +3651,7 @@ int32_t lis2duxs12_fsm_fifo_en_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2duxs12_fsm_fifo_en_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2duxs12_fsm_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2duxs12_emb_func_fifo_en_t fifo_reg; int32_t ret; @@ -3465,7 +3680,7 @@ int32_t lis2duxs12_fsm_fifo_en_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2duxs12_long_cnt_int_value_set(stmdev_ctx_t *ctx, +int32_t lis2duxs12_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; @@ -3489,8 +3704,8 @@ int32_t lis2duxs12_long_cnt_int_value_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2duxs12_long_cnt_int_value_get(stmdev_ctx_t *ctx, - uint16_t *val) +int32_t lis2duxs12_long_cnt_int_value_get(const stmdev_ctx_t *ctx, + uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -3506,16 +3721,15 @@ int32_t lis2duxs12_long_cnt_int_value_get(stmdev_ctx_t *ctx, * @brief FSM number of programs register.[set] * * @param ctx Read / write interface definitions.(ptr) - * @param buff Buffer that contains data to write + * @param val Buffer that contains data to write * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2duxs12_fsm_number_of_programs_set(stmdev_ctx_t *ctx, - uint8_t *buff) +int32_t lis2duxs12_fsm_programs_num_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; - ret = lis2duxs12_ln_pg_write(ctx, LIS2DUXS12_FSM_PROGRAMS, buff, 2); + ret = lis2duxs12_ln_pg_write(ctx, LIS2DUXS12_FSM_PROGRAMS, &val, 1); return ret; } @@ -3524,16 +3738,15 @@ int32_t lis2duxs12_fsm_number_of_programs_set(stmdev_ctx_t *ctx, * @brief FSM number of programs register.[get] * * @param ctx Read / write interface definitions.(ptr) - * @param buff Buffer that stores data read + * @param val Buffer that stores data read * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2duxs12_fsm_number_of_programs_get(stmdev_ctx_t *ctx, - uint8_t *buff) +int32_t lis2duxs12_fsm_programs_num_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; - ret = lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_FSM_PROGRAMS, buff, 2); + ret = lis2duxs12_ln_pg_read(ctx, LIS2DUXS12_FSM_PROGRAMS, val, 1); return ret; } @@ -3547,8 +3760,8 @@ int32_t lis2duxs12_fsm_number_of_programs_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2duxs12_fsm_start_address_set(stmdev_ctx_t *ctx, - uint16_t val) +int32_t lis2duxs12_fsm_start_address_set(const stmdev_ctx_t *ctx, + uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -3569,8 +3782,8 @@ int32_t lis2duxs12_fsm_start_address_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2duxs12_fsm_start_address_get(stmdev_ctx_t *ctx, - uint16_t *val) +int32_t lis2duxs12_fsm_start_address_get(const stmdev_ctx_t *ctx, + uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -3604,7 +3817,7 @@ int32_t lis2duxs12_fsm_start_address_get(stmdev_ctx_t *ctx, * in EMB_FUNC_INIT_A * */ -int32_t lis2duxs12_mlc_set(stmdev_ctx_t *ctx, lis2duxs12_mlc_mode_t val) +int32_t lis2duxs12_mlc_set(const stmdev_ctx_t *ctx, lis2duxs12_mlc_mode_t val) { lis2duxs12_emb_func_en_a_t emb_en_a; lis2duxs12_emb_func_en_b_t emb_en_b; @@ -3617,7 +3830,7 @@ int32_t lis2duxs12_mlc_set(stmdev_ctx_t *ctx, lis2duxs12_mlc_mode_t val) ret = lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); ret += lis2duxs12_read_reg(ctx, LIS2DUXS12_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); - switch(val) + switch (val) { case LIS2DUXS12_MLC_OFF: emb_en_a.mlc_before_fsm_en = 0; @@ -3632,6 +3845,7 @@ int32_t lis2duxs12_mlc_set(stmdev_ctx_t *ctx, lis2duxs12_mlc_mode_t val) emb_en_b.mlc_en = 0; break; default: + /* do nothing */ break; } @@ -3653,7 +3867,7 @@ int32_t lis2duxs12_mlc_set(stmdev_ctx_t *ctx, lis2duxs12_mlc_mode_t val) * in EMB_FUNC_INIT_A * */ -int32_t lis2duxs12_mlc_get(stmdev_ctx_t *ctx, lis2duxs12_mlc_mode_t *val) +int32_t lis2duxs12_mlc_get(const stmdev_ctx_t *ctx, lis2duxs12_mlc_mode_t *val) { lis2duxs12_emb_func_en_a_t emb_en_a; lis2duxs12_emb_func_en_b_t emb_en_b; @@ -3696,7 +3910,7 @@ int32_t lis2duxs12_mlc_get(stmdev_ctx_t *ctx, lis2duxs12_mlc_mode_t *val) * @param val register MLC_STATUS_MAINPAGE * */ -int32_t lis2duxs12_mlc_status_get(stmdev_ctx_t *ctx, +int32_t lis2duxs12_mlc_status_get(const stmdev_ctx_t *ctx, lis2duxs12_mlc_status_mainpage_t *val) { return lis2duxs12_read_reg(ctx, LIS2DUXS12_MLC_STATUS_MAINPAGE, @@ -3710,7 +3924,7 @@ int32_t lis2duxs12_mlc_status_get(stmdev_ctx_t *ctx, * @param uint8_t * : buffer that stores data read * */ -int32_t lis2duxs12_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis2duxs12_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -3734,7 +3948,7 @@ int32_t lis2duxs12_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff) * reg EMB_FUNC_ODR_CFG_C * */ -int32_t lis2duxs12_mlc_data_rate_set(stmdev_ctx_t *ctx, +int32_t lis2duxs12_mlc_data_rate_set(const stmdev_ctx_t *ctx, lis2duxs12_mlc_odr_val_t val) { lis2duxs12_mlc_odr_t reg; @@ -3765,7 +3979,7 @@ int32_t lis2duxs12_mlc_data_rate_set(stmdev_ctx_t *ctx, * reg EMB_FUNC_ODR_CFG_C * */ -int32_t lis2duxs12_mlc_data_rate_get(stmdev_ctx_t *ctx, +int32_t lis2duxs12_mlc_data_rate_get(const stmdev_ctx_t *ctx, lis2duxs12_mlc_odr_val_t *val) { lis2duxs12_mlc_odr_t reg; @@ -3779,23 +3993,23 @@ int32_t lis2duxs12_mlc_data_rate_get(stmdev_ctx_t *ctx, switch (reg.mlc_odr) { - case LIS2DUXS12_ODR_PRGS_12Hz5: + case 0: *val = LIS2DUXS12_ODR_PRGS_12Hz5; break; - case LIS2DUXS12_ODR_PRGS_25Hz: + case 1: *val = LIS2DUXS12_ODR_PRGS_25Hz; break; - case LIS2DUXS12_ODR_PRGS_50Hz: + case 2: *val = LIS2DUXS12_ODR_PRGS_50Hz; break; - case LIS2DUXS12_ODR_PRGS_100Hz: + case 3: *val = LIS2DUXS12_ODR_PRGS_100Hz; break; - case LIS2DUXS12_ODR_PRGS_200Hz: + case 4: *val = LIS2DUXS12_ODR_PRGS_200Hz; break; @@ -3818,7 +4032,7 @@ int32_t lis2duxs12_mlc_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2duxs12_mlc_fifo_en_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2duxs12_mlc_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2duxs12_emb_func_fifo_en_t fifo_reg; int32_t ret; @@ -3845,7 +4059,7 @@ int32_t lis2duxs12_mlc_fifo_en_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2duxs12_mlc_fifo_en_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2duxs12_mlc_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2duxs12_emb_func_fifo_en_t fifo_reg; int32_t ret; diff --git a/sensor/stmemsc/lis2duxs12_STdC/driver/lis2duxs12_reg.h b/sensor/stmemsc/lis2duxs12_STdC/driver/lis2duxs12_reg.h index daf81b79..5312110e 100644 --- a/sensor/stmemsc/lis2duxs12_STdC/driver/lis2duxs12_reg.h +++ b/sensor/stmemsc/lis2duxs12_STdC/driver/lis2duxs12_reg.h @@ -23,7 +23,7 @@ #define LIS2DUXS12_REGS_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -75,7 +75,8 @@ #ifndef MEMS_SHARED_TYPES #define MEMS_SHARED_TYPES -typedef struct{ +typedef struct +{ #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t bit0 : 1; uint8_t bit1 : 1; @@ -108,8 +109,8 @@ typedef struct{ * */ -typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); -typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef int32_t (*stmdev_write_ptr)(void *ctx, uint8_t reg, const uint8_t *data, uint16_t len); +typedef int32_t (*stmdev_read_ptr)(void *ctx, uint8_t reg, uint8_t *data, uint16_t len); typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); typedef struct @@ -144,7 +145,8 @@ typedef struct * */ -typedef struct { +typedef struct +{ uint8_t address; uint8_t data; } ucf_line_t; @@ -178,6 +180,18 @@ typedef struct { * */ +#define LIS2DUXS12_EXT_CLK_CFG 0x08U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 7; + uint8_t ext_clk_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ext_clk_en : 1; + uint8_t not_used0 : 7; +#endif /* DRV_BYTE_ORDER */ +} lis2duxs12_ext_clk_cfg_t; + #define LIS2DUXS12_PIN_CTRL 0x0CU typedef struct { @@ -722,13 +736,15 @@ typedef struct typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t not_used0 : 4; + uint8_t t_ah_qvar_dis : 1; + uint8_t not_used0 : 3; uint8_t st : 2; uint8_t not_used1 : 2; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN uint8_t not_used1 : 2; uint8_t st : 2; - uint8_t not_used0 : 4; + uint8_t not_used0 : 3; + uint8_t t_ah_qvar_dis : 1; #endif /* DRV_BYTE_ORDER */ } lis2duxs12_self_test_t; @@ -824,7 +840,7 @@ typedef struct #endif /* DRV_BYTE_ORDER */ } lis2duxs12_sleep_t; -#define LIS2DUXS12_IF_WAKE_UP 0x3EU +#define LIS2DUXS12_EN_DEVICE_CONFIG 0x3EU typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN @@ -834,7 +850,7 @@ typedef struct uint8_t not_used0 : 7; uint8_t soft_pd : 1; #endif /* DRV_BYTE_ORDER */ -} lis2duxs12_if_wake_up_t; +} lis2duxs12_en_device_config_t; #define LIS2DUXS12_FUNC_CFG_ACCESS 0x3FU typedef struct @@ -1959,7 +1975,7 @@ typedef union lis2duxs12_fsm_status_mainpage_t fsm_status_mainpage; lis2duxs12_mlc_status_mainpage_t mlc_status_mainpage; lis2duxs12_sleep_t sleep; - lis2duxs12_if_wake_up_t if_wake_up; + lis2duxs12_en_device_config_t en_device_config; lis2duxs12_func_cfg_access_t func_cfg_access; lis2duxs12_fifo_data_out_tag_t fifo_data_out_tag; lis2duxs12_fifo_data_out_x_l_t fifo_data_out_x_l; @@ -2053,12 +2069,12 @@ typedef union * them with a custom implementation. */ -int32_t lis2duxs12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len); -int32_t lis2duxs12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len); +int32_t lis2duxs12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); +int32_t lis2duxs12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); float_t lis2duxs12_from_fs2g_to_mg(int16_t lsb); float_t lis2duxs12_from_fs4g_to_mg(int16_t lsb); @@ -2067,41 +2083,45 @@ float_t lis2duxs12_from_fs16g_to_mg(int16_t lsb); float_t lis2duxs12_from_lsb_to_celsius(int16_t lsb); float_t lis2duxs12_from_lsb_to_mv(int16_t lsb); -int32_t lis2duxs12_device_id_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2duxs12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val); -typedef enum { +typedef enum +{ LIS2DUXS12_SENSOR_ONLY_ON = 0x00, /* Initialize the driver for sensor usage */ LIS2DUXS12_BOOT = 0x01, /* Restore calib. param. (it takes 10ms) */ LIS2DUXS12_RESET = 0x02, /* Reset configuration registers */ LIS2DUXS12_SENSOR_EMB_FUNC_ON = 0x03, /* Initialize the driver for sensor and/or embedded functions usage (it takes 10ms) */ } lis2duxs12_init_t; -int32_t lis2duxs12_init_set(stmdev_ctx_t *ctx, lis2duxs12_init_t val); +int32_t lis2duxs12_init_set(const stmdev_ctx_t *ctx, lis2duxs12_init_t val); -typedef struct { +typedef struct +{ uint8_t sw_reset : 1; /* Restoring configuration registers */ uint8_t boot : 1; /* Restoring calibration parameters */ uint8_t drdy : 1; /* Accelerometer data ready */ uint8_t power_down : 1; /* Monitors power-down. */ } lis2duxs12_status_t; -int32_t lis2duxs12_status_get(stmdev_ctx_t *ctx, lis2duxs12_status_t *val); +int32_t lis2duxs12_status_get(const stmdev_ctx_t *ctx, lis2duxs12_status_t *val); -typedef struct { +typedef struct +{ uint8_t is_step_det : 1; /* Step detected */ uint8_t is_tilt : 1; /* Tilt detected */ uint8_t is_sigmot : 1; /* Significant motion detected */ } lis2duxs12_embedded_status_t; -int32_t lis2duxs12_embedded_status_get(stmdev_ctx_t *ctx, lis2duxs12_embedded_status_t *val); +int32_t lis2duxs12_embedded_status_get(const stmdev_ctx_t *ctx, lis2duxs12_embedded_status_t *val); typedef enum { LIS2DUXS12_DRDY_LATCHED = 0x0, LIS2DUXS12_DRDY_PULSED = 0x1, } lis2duxs12_data_ready_mode_t; -int32_t lis2duxs12_data_ready_mode_set(stmdev_ctx_t *ctx, lis2duxs12_data_ready_mode_t val); -int32_t lis2duxs12_data_ready_mode_get(stmdev_ctx_t *ctx, lis2duxs12_data_ready_mode_t *val); +int32_t lis2duxs12_data_ready_mode_set(const stmdev_ctx_t *ctx, lis2duxs12_data_ready_mode_t val); +int32_t lis2duxs12_data_ready_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_data_ready_mode_t *val); -typedef enum { +typedef enum +{ LIS2DUXS12_OFF = 0x00, /* in power down */ LIS2DUXS12_1Hz6_ULP = 0x01, /* @1Hz6 (ultra low power) */ LIS2DUXS12_3Hz_ULP = 0x02, /* @3Hz (ultra low power) */ @@ -2126,29 +2146,35 @@ typedef enum { LIS2DUXS12_TRIG_SW = 0x2F, /* Single-shot high latency by IF */ } lis2duxs12_odr_t; -typedef enum { +typedef enum +{ LIS2DUXS12_2g = 0, LIS2DUXS12_4g = 1, LIS2DUXS12_8g = 2, LIS2DUXS12_16g = 3, } lis2duxs12_fs_t; -typedef enum { +typedef enum +{ LIS2DUXS12_ODR_div_2 = 0, LIS2DUXS12_ODR_div_4 = 1, LIS2DUXS12_ODR_div_8 = 2, LIS2DUXS12_ODR_div_16 = 3, } lis2duxs12_bw_t; -typedef struct { +typedef struct +{ lis2duxs12_odr_t odr; lis2duxs12_fs_t fs; lis2duxs12_bw_t bw; } lis2duxs12_md_t; -int32_t lis2duxs12_mode_set(stmdev_ctx_t *ctx, lis2duxs12_md_t *val); -int32_t lis2duxs12_mode_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *val); +int32_t lis2duxs12_mode_set(const stmdev_ctx_t *ctx, const lis2duxs12_md_t *val); +int32_t lis2duxs12_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_md_t *val); -int32_t lis2duxs12_trigger_sw(stmdev_ctx_t *ctx, lis2duxs12_md_t *md); +int32_t lis2duxs12_t_ah_qvar_dis_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2duxs12_t_ah_qvar_dis_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lis2duxs12_trigger_sw(const stmdev_ctx_t *ctx, const lis2duxs12_md_t *md); typedef struct { @@ -2177,30 +2203,34 @@ typedef struct uint8_t fifo_ovr : 1; uint8_t fifo_th : 1; } lis2duxs12_all_sources_t; -int32_t lis2duxs12_all_sources_get(stmdev_ctx_t *ctx, lis2duxs12_all_sources_t *val); +int32_t lis2duxs12_all_sources_get(const stmdev_ctx_t *ctx, lis2duxs12_all_sources_t *val); -typedef struct { +typedef struct +{ float_t mg[3]; int16_t raw[3]; } lis2duxs12_xl_data_t; -int32_t lis2duxs12_xl_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md, +int32_t lis2duxs12_xl_data_get(const stmdev_ctx_t *ctx, const lis2duxs12_md_t *md, lis2duxs12_xl_data_t *data); -typedef struct { - struct { +typedef struct +{ + struct + { float_t deg_c; int16_t raw; - }heat; + } heat; } lis2duxs12_outt_data_t; -int32_t lis2duxs12_outt_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md, - lis2duxs12_outt_data_t *data); +int32_t lis2duxs12_outt_data_get(const stmdev_ctx_t *ctx, + lis2duxs12_outt_data_t *data); -typedef struct { +typedef struct +{ float_t mv; int16_t raw; } lis2duxs12_ah_qvar_data_t; -int32_t lis2duxs12_ah_qvar_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md, - lis2duxs12_ah_qvar_data_t *data); +int32_t lis2duxs12_ah_qvar_data_get(const stmdev_ctx_t *ctx, + lis2duxs12_ah_qvar_data_t *data); typedef enum { @@ -2208,40 +2238,47 @@ typedef enum LIS2DUXS12_XL_ST_POSITIVE = 0x1, LIS2DUXS12_XL_ST_NEGATIVE = 0x2, } lis2duxs12_xl_self_test_t; -int32_t lis2duxs12_self_test_sign_set(stmdev_ctx_t *ctx, lis2duxs12_xl_self_test_t val); -int32_t lis2duxs12_self_test_start(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2duxs12_self_test_stop(stmdev_ctx_t *ctx); +int32_t lis2duxs12_self_test_sign_set(const stmdev_ctx_t *ctx, lis2duxs12_xl_self_test_t val); +int32_t lis2duxs12_self_test_start(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2duxs12_self_test_stop(const stmdev_ctx_t *ctx); -int32_t lis2duxs12_enter_deep_power_down(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2duxs12_exit_deep_power_down(stmdev_ctx_t *ctx); +int32_t lis2duxs12_enter_deep_power_down(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2duxs12_exit_deep_power_down(const stmdev_ctx_t *ctx); -typedef enum { +typedef enum +{ LIS2DUXS12_I3C_BUS_AVAIL_TIME_20US = 0x0, LIS2DUXS12_I3C_BUS_AVAIL_TIME_50US = 0x1, LIS2DUXS12_I3C_BUS_AVAIL_TIME_1MS = 0x2, LIS2DUXS12_I3C_BUS_AVAIL_TIME_25MS = 0x3, } lis2duxs12_bus_act_sel_t; -typedef struct { +typedef struct +{ lis2duxs12_bus_act_sel_t bus_act_sel; uint8_t asf_on : 1; uint8_t drstdaa_en : 1; } lis2duxs12_i3c_cfg_t; -int32_t lis2duxs12_i3c_configure_set(stmdev_ctx_t *ctx, lis2duxs12_i3c_cfg_t *val); -int32_t lis2duxs12_i3c_configure_get(stmdev_ctx_t *ctx, lis2duxs12_i3c_cfg_t *val); +int32_t lis2duxs12_i3c_configure_set(const stmdev_ctx_t *ctx, const lis2duxs12_i3c_cfg_t *val); +int32_t lis2duxs12_i3c_configure_get(const stmdev_ctx_t *ctx, lis2duxs12_i3c_cfg_t *val); typedef enum { LIS2DUXS12_MAIN_MEM_BANK = 0x0, LIS2DUXS12_EMBED_FUNC_MEM_BANK = 0x1, } lis2duxs12_mem_bank_t; -int32_t lis2duxs12_mem_bank_set(stmdev_ctx_t *ctx, lis2duxs12_mem_bank_t val); -int32_t lis2duxs12_mem_bank_get(stmdev_ctx_t *ctx, lis2duxs12_mem_bank_t *val); +int32_t lis2duxs12_mem_bank_set(const stmdev_ctx_t *ctx, lis2duxs12_mem_bank_t val); +int32_t lis2duxs12_mem_bank_get(const stmdev_ctx_t *ctx, lis2duxs12_mem_bank_t *val); -int32_t lis2duxs12_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); -int32_t lis2duxs12_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); +int32_t lis2duxs12_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, + uint8_t len); +int32_t lis2duxs12_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); -typedef struct { +int32_t lis2duxs12_ext_clk_en_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2duxs12_ext_clk_en_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ uint8_t sdo_pull_up : 1; /* 1 = pull up enable */ uint8_t sda_pull_up : 1; /* 1 = pull up enable */ uint8_t cs_pull_up : 1; /* 1 = pull up enable */ @@ -2249,26 +2286,28 @@ typedef struct { uint8_t int1_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */ uint8_t int2_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */ } lis2duxs12_pin_conf_t; -int32_t lis2duxs12_pin_conf_set(stmdev_ctx_t *ctx, lis2duxs12_pin_conf_t *val); -int32_t lis2duxs12_pin_conf_get(stmdev_ctx_t *ctx, lis2duxs12_pin_conf_t *val); +int32_t lis2duxs12_pin_conf_set(const stmdev_ctx_t *ctx, const lis2duxs12_pin_conf_t *val); +int32_t lis2duxs12_pin_conf_get(const stmdev_ctx_t *ctx, lis2duxs12_pin_conf_t *val); typedef enum { LIS2DUXS12_ACTIVE_HIGH = 0x0, LIS2DUXS12_ACTIVE_LOW = 0x1, } lis2duxs12_int_pin_polarity_t; -int32_t lis2duxs12_int_pin_polarity_set(stmdev_ctx_t *ctx, lis2duxs12_int_pin_polarity_t val); -int32_t lis2duxs12_int_pin_polarity_get(stmdev_ctx_t *ctx, lis2duxs12_int_pin_polarity_t *val); +int32_t lis2duxs12_int_pin_polarity_set(const stmdev_ctx_t *ctx, lis2duxs12_int_pin_polarity_t val); +int32_t lis2duxs12_int_pin_polarity_get(const stmdev_ctx_t *ctx, + lis2duxs12_int_pin_polarity_t *val); typedef enum { LIS2DUXS12_SPI_4_WIRE = 0x0, /* SPI 4 wires */ LIS2DUXS12_SPI_3_WIRE = 0x1, /* SPI 3 wires */ } lis2duxs12_spi_mode; -int32_t lis2duxs12_spi_mode_set(stmdev_ctx_t *ctx, lis2duxs12_spi_mode val); -int32_t lis2duxs12_spi_mode_get(stmdev_ctx_t *ctx, lis2duxs12_spi_mode *val); +int32_t lis2duxs12_spi_mode_set(const stmdev_ctx_t *ctx, lis2duxs12_spi_mode val); +int32_t lis2duxs12_spi_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_spi_mode *val); -typedef struct { +typedef struct +{ uint8_t int_on_res : 1; /* Interrupt on RES pin */ uint8_t drdy : 1; /* Accelerometer data ready */ uint8_t boot : 1; /* Restoring calibration parameters */ @@ -2283,28 +2322,29 @@ typedef struct { uint8_t emb_function : 1; /* Embedded Function */ uint8_t timestamp : 1; /* Timestamp */ } lis2duxs12_pin_int_route_t; -int32_t lis2duxs12_pin_int1_route_set(stmdev_ctx_t *ctx, - lis2duxs12_pin_int_route_t *val); -int32_t lis2duxs12_pin_int1_route_get(stmdev_ctx_t *ctx, - lis2duxs12_pin_int_route_t *val); -int32_t lis2duxs12_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lis2duxs12_pin_int1_route_set(const stmdev_ctx_t *ctx, + const lis2duxs12_pin_int_route_t *val); +int32_t lis2duxs12_pin_int1_route_get(const stmdev_ctx_t *ctx, lis2duxs12_pin_int_route_t *val); -int32_t lis2duxs12_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lis2duxs12_pin_int2_route_set(const stmdev_ctx_t *ctx, + const lis2duxs12_pin_int_route_t *val); +int32_t lis2duxs12_pin_int2_route_get(const stmdev_ctx_t *ctx, lis2duxs12_pin_int_route_t *val); -typedef struct { +typedef struct +{ uint8_t step_det : 1; /* route step detection event on INT pad */ uint8_t tilt : 1; /* route tilt event on INT pad */ uint8_t sig_mot : 1; /* route significant motion event on INT pad */ uint8_t fsm_lc : 1; /* route FSM long counter event on INT pad */ } lis2duxs12_emb_pin_int_route_t; -int32_t lis2duxs12_emb_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lis2duxs12_emb_pin_int1_route_set(const stmdev_ctx_t *ctx, + const lis2duxs12_emb_pin_int_route_t *val); +int32_t lis2duxs12_emb_pin_int1_route_get(const stmdev_ctx_t *ctx, lis2duxs12_emb_pin_int_route_t *val); -int32_t lis2duxs12_emb_pin_int1_route_get(stmdev_ctx_t *ctx, - lis2duxs12_emb_pin_int_route_t *val); -int32_t lis2duxs12_emb_pin_int2_route_set(stmdev_ctx_t *ctx, - lis2duxs12_emb_pin_int_route_t *val); -int32_t lis2duxs12_emb_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lis2duxs12_emb_pin_int2_route_set(const stmdev_ctx_t *ctx, + const lis2duxs12_emb_pin_int_route_t *val); +int32_t lis2duxs12_emb_pin_int2_route_get(const stmdev_ctx_t *ctx, lis2duxs12_emb_pin_int_route_t *val); typedef enum @@ -2314,21 +2354,24 @@ typedef enum LIS2DUXS12_INT_LATCHED = 0x2, } lis2duxs12_int_cfg_t; -typedef struct { +typedef struct +{ lis2duxs12_int_cfg_t int_cfg; uint8_t sleep_status_on_int : 1; /* route sleep_status on interrupt */ uint8_t dis_rst_lir_all_int : 1; /* disable LIR reset when reading ALL_INT_SRC */ } lis2duxs12_int_config_t; -int32_t lis2duxs12_int_config_set(stmdev_ctx_t *ctx, lis2duxs12_int_config_t *val); -int32_t lis2duxs12_int_config_get(stmdev_ctx_t *ctx, lis2duxs12_int_config_t *val); +int32_t lis2duxs12_int_config_set(const stmdev_ctx_t *ctx, const lis2duxs12_int_config_t *val); +int32_t lis2duxs12_int_config_get(const stmdev_ctx_t *ctx, lis2duxs12_int_config_t *val); typedef enum { LIS2DUXS12_EMBEDDED_INT_LEVEL = 0x0, LIS2DUXS12_EMBEDDED_INT_LATCHED = 0x1, } lis2duxs12_embedded_int_config_t; -int32_t lis2duxs12_embedded_int_config_set(stmdev_ctx_t *ctx, lis2duxs12_embedded_int_config_t val); -int32_t lis2duxs12_embedded_int_config_get(stmdev_ctx_t *ctx, lis2duxs12_embedded_int_config_t *val); +int32_t lis2duxs12_embedded_int_cfg_set(const stmdev_ctx_t *ctx, + lis2duxs12_embedded_int_config_t val); +int32_t lis2duxs12_embedded_int_cfg_get(const stmdev_ctx_t *ctx, + lis2duxs12_embedded_int_config_t *val); typedef enum { @@ -2341,7 +2384,8 @@ typedef enum LIS2DUXS12_FIFO_OFF = 0x8, } lis2duxs12_operation_t; -typedef enum { +typedef enum +{ LIS2DUXS12_FIFO_1X = 0, LIS2DUXS12_FIFO_2X = 1, } lis2duxs12_store_t; @@ -2366,22 +2410,24 @@ typedef enum LIS2DUXS12_BDR_XL_ODR_OFF = 0x7, } lis2duxs12_bdr_xl_t; -typedef struct { +typedef struct +{ lis2duxs12_operation_t operation; lis2duxs12_store_t store; - uint8_t xl_only : 1; /* when set to 1, only XL samples (16-bit) are stored in FIFO */ + uint8_t xl_only : 1; /* only XL samples (16-bit) are stored in FIFO */ uint8_t watermark : 7; /* (0 disable) max 127 @16bit, even and max 256 @8bit.*/ uint8_t cfg_change_in_fifo : 1; - struct { + struct + { lis2duxs12_dec_ts_t dec_ts; /* decimation for timestamp batching*/ lis2duxs12_bdr_xl_t bdr_xl; /* accelerometer batch data rate*/ } batch; } lis2duxs12_fifo_mode_t; -int32_t lis2duxs12_fifo_mode_set(stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t val); -int32_t lis2duxs12_fifo_mode_get(stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t *val); +int32_t lis2duxs12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t val); +int32_t lis2duxs12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_fifo_mode_t *val); -int32_t lis2duxs12_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val); -int32_t lis2duxs12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2duxs12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); +int32_t lis2duxs12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2397,34 +2443,40 @@ typedef enum LIS2DUXS12_XL_ONLY_2X_TAG_2ND = 0x1E, LIS2DUXS12_XL_AND_QVAR = 0x1F, } lis2duxs12_fifo_sensor_tag_t; -int32_t lis2duxs12_fifo_sensor_tag_get(stmdev_ctx_t *ctx, +int32_t lis2duxs12_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, lis2duxs12_fifo_sensor_tag_t *val); -int32_t lis2duxs12_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis2duxs12_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); -typedef struct { +typedef struct +{ uint8_t tag; - struct { + struct + { float_t mg[3]; int16_t raw[3]; - }xl[2]; - struct { + } xl[2]; + struct + { float_t mv; int16_t raw; } ah_qvar; - struct { + struct + { float_t deg_c; int16_t raw; - }heat; - struct lis2duxs12_pedo { + } heat; + struct + { uint32_t steps; uint32_t timestamp; } pedo; - struct lis2duxs12_cfg_chg { + struct + { uint8_t cfg_change : 1; /* 1 if ODR/BDR configuration is changed */ uint8_t odr : 4; /* ODR */ uint8_t bw : 2; /* BW */ - uint8_t lp_hp : 1; /* Power (LP == 0/HP == 1) */ + uint8_t lp_hp : 1; /* Power: 0 for LP, 1 for HP */ uint8_t qvar_en : 1; /* QVAR is enabled */ uint8_t fs : 2; /* FS */ uint8_t dec_ts : 2; /* Timestamp decimator value */ @@ -2432,23 +2484,26 @@ typedef struct { uint32_t timestamp; } cfg_chg; } lis2duxs12_fifo_data_t; -int32_t lis2duxs12_fifo_data_get(stmdev_ctx_t *ctx, lis2duxs12_md_t *md, - lis2duxs12_fifo_mode_t *fmd, +int32_t lis2duxs12_fifo_data_get(const stmdev_ctx_t *ctx, const lis2duxs12_md_t *md, + const lis2duxs12_fifo_mode_t *fmd, lis2duxs12_fifo_data_t *data); -typedef enum { +typedef enum +{ LIS2DUXS12_NOTCH_50HZ = 0x0, LIS2DUXS12_NOTCH_60HZ = 0x1, } lis2duxs12_ah_qvar_notch_t; -typedef enum { +typedef enum +{ LIS2DUXS12_520MOhm = 0x0, LIS2DUXS12_175MOhm = 0x1, LIS2DUXS12_310MOhm = 0x2, LIS2DUXS12_75MOhm = 0x3, } lis2duxs12_ah_qvar_zin_t; -typedef enum { +typedef enum +{ LIS2DUXS12_GAIN_0_5 = 0x0, LIS2DUXS12_GAIN_1 = 0x1, LIS2DUXS12_GAIN_2 = 0x2, @@ -2463,9 +2518,9 @@ typedef struct lis2duxs12_ah_qvar_zin_t ah_qvar_zin; lis2duxs12_ah_qvar_gain_t ah_qvar_gain; } lis2duxs12_ah_qvar_mode_t; -int32_t lis2duxs12_ah_qvar_mode_set(stmdev_ctx_t *ctx, +int32_t lis2duxs12_ah_qvar_mode_set(const stmdev_ctx_t *ctx, lis2duxs12_ah_qvar_mode_t val); -int32_t lis2duxs12_ah_qvar_mode_get(stmdev_ctx_t *ctx, +int32_t lis2duxs12_ah_qvar_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_ah_qvar_mode_t *val); typedef struct @@ -2474,27 +2529,27 @@ typedef struct uint8_t step_counter_enable : 1; uint8_t step_counter_in_fifo : 1; } lis2duxs12_stpcnt_mode_t; -int32_t lis2duxs12_stpcnt_mode_set(stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mode_t val); -int32_t lis2duxs12_stpcnt_mode_get(stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mode_t *val); +int32_t lis2duxs12_stpcnt_mode_set(const stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mode_t val); +int32_t lis2duxs12_stpcnt_mode_get(const stmdev_ctx_t *ctx, lis2duxs12_stpcnt_mode_t *val); -int32_t lis2duxs12_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lis2duxs12_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lis2duxs12_stpcnt_rst_step_set(stmdev_ctx_t *ctx); +int32_t lis2duxs12_stpcnt_rst_step_set(const stmdev_ctx_t *ctx); -int32_t lis2duxs12_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2duxs12_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2duxs12_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2duxs12_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2duxs12_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lis2duxs12_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lis2duxs12_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lis2duxs12_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lis2duxs12_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2duxs12_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2duxs12_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2duxs12_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2duxs12_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2duxs12_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2duxs12_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2duxs12_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2duxs12_ff_duration_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2duxs12_ff_duration_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2duxs12_ff_duration_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2duxs12_ff_duration_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2507,8 +2562,8 @@ typedef enum LIS2DUXS12_469_mg = 0x6, LIS2DUXS12_500_mg = 0x7, } lis2duxs12_ff_thresholds_t; -int32_t lis2duxs12_ff_thresholds_set(stmdev_ctx_t *ctx, lis2duxs12_ff_thresholds_t val); -int32_t lis2duxs12_ff_thresholds_get(stmdev_ctx_t *ctx, lis2duxs12_ff_thresholds_t *val); +int32_t lis2duxs12_ff_thresholds_set(const stmdev_ctx_t *ctx, lis2duxs12_ff_thresholds_t val); +int32_t lis2duxs12_ff_thresholds_get(const stmdev_ctx_t *ctx, lis2duxs12_ff_thresholds_t *val); typedef enum { @@ -2524,13 +2579,14 @@ typedef enum LIS2DUXS12_4D = 0x1, } lis2duxs12_mode_t; -typedef struct { +typedef struct +{ lis2duxs12_threshold_t threshold; lis2duxs12_mode_t mode; } lis2duxs12_sixd_config_t; -int32_t lis2duxs12_sixd_config_set(stmdev_ctx_t *ctx, lis2duxs12_sixd_config_t val); -int32_t lis2duxs12_sixd_config_get(stmdev_ctx_t *ctx, lis2duxs12_sixd_config_t *val); +int32_t lis2duxs12_sixd_config_set(const stmdev_ctx_t *ctx, lis2duxs12_sixd_config_t val); +int32_t lis2duxs12_sixd_config_get(const stmdev_ctx_t *ctx, lis2duxs12_sixd_config_t *val); typedef enum { @@ -2557,7 +2613,8 @@ typedef enum LIS2DUXS12_ODR_25_HZ = 1, /* set odr to 25Hz during inactivity state */ } lis2duxs12_inact_odr_t; -typedef struct { +typedef struct +{ lis2duxs12_wake_dur_t wake_dur; uint8_t sleep_dur : 4; /* 1 LSB == 512 ODR time */ uint8_t wake_ths : 7; /* wakeup threshold */ @@ -2566,8 +2623,8 @@ typedef struct { lis2duxs12_inact_odr_t inact_odr; } lis2duxs12_wakeup_config_t; -int32_t lis2duxs12_wakeup_config_set(stmdev_ctx_t *ctx, lis2duxs12_wakeup_config_t val); -int32_t lis2duxs12_wakeup_config_get(stmdev_ctx_t *ctx, lis2duxs12_wakeup_config_t *val); +int32_t lis2duxs12_wakeup_config_set(const stmdev_ctx_t *ctx, lis2duxs12_wakeup_config_t val); +int32_t lis2duxs12_wakeup_config_get(const stmdev_ctx_t *ctx, lis2duxs12_wakeup_config_t *val); typedef enum { @@ -2577,7 +2634,8 @@ typedef enum LIS2DUXS12_TAP_ON_Z = 0x3, /* Detect tap on Z axis */ } lis2duxs12_axis_t; -typedef struct { +typedef struct +{ lis2duxs12_axis_t axis; uint8_t inverted_peak_time : 5; /* 1 LSB == 1 sample */ uint8_t pre_still_ths : 4; /* 1 LSB == 62.5 mg */ @@ -2595,35 +2653,35 @@ typedef struct { uint8_t triple_tap_on : 1; /* enable triple tap */ } lis2duxs12_tap_config_t; -int32_t lis2duxs12_tap_config_set(stmdev_ctx_t *ctx, lis2duxs12_tap_config_t val); -int32_t lis2duxs12_tap_config_get(stmdev_ctx_t *ctx, lis2duxs12_tap_config_t *val); +int32_t lis2duxs12_tap_config_set(const stmdev_ctx_t *ctx, lis2duxs12_tap_config_t val); +int32_t lis2duxs12_tap_config_get(const stmdev_ctx_t *ctx, lis2duxs12_tap_config_t *val); -int32_t lis2duxs12_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2duxs12_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2duxs12_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2duxs12_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2duxs12_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); +int32_t lis2duxs12_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); -int32_t lis2duxs12_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lis2duxs12_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2duxs12_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2duxs12_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2duxs12_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2duxs12_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { lis2duxs12_fsm_enable_t fsm_enable; } lis2duxs12_emb_fsm_enable_t; -int32_t lis2duxs12_fsm_enable_set(stmdev_ctx_t *ctx, +int32_t lis2duxs12_fsm_enable_set(const stmdev_ctx_t *ctx, lis2duxs12_emb_fsm_enable_t *val); -int32_t lis2duxs12_fsm_enable_get(stmdev_ctx_t *ctx, +int32_t lis2duxs12_fsm_enable_get(const stmdev_ctx_t *ctx, lis2duxs12_emb_fsm_enable_t *val); -int32_t lis2duxs12_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lis2duxs12_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lis2duxs12_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lis2duxs12_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lis2duxs12_fsm_status_get(stmdev_ctx_t *ctx, +int32_t lis2duxs12_fsm_status_get(const stmdev_ctx_t *ctx, lis2duxs12_fsm_status_mainpage_t *val); -int32_t lis2duxs12_fsm_out_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2duxs12_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2635,30 +2693,28 @@ typedef enum LIS2DUXS12_ODR_FSM_400Hz = 5, LIS2DUXS12_ODR_FSM_800Hz = 6, } lis2duxs12_fsm_val_odr_t; -int32_t lis2duxs12_fsm_data_rate_set(stmdev_ctx_t *ctx, +int32_t lis2duxs12_fsm_data_rate_set(const stmdev_ctx_t *ctx, lis2duxs12_fsm_val_odr_t val); -int32_t lis2duxs12_fsm_data_rate_get(stmdev_ctx_t *ctx, +int32_t lis2duxs12_fsm_data_rate_get(const stmdev_ctx_t *ctx, lis2duxs12_fsm_val_odr_t *val); -int32_t lis2duxs12_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2duxs12_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2duxs12_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2duxs12_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2duxs12_fsm_fifo_en_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2duxs12_fsm_fifo_en_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2duxs12_fsm_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2duxs12_fsm_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2duxs12_long_cnt_int_value_set(stmdev_ctx_t *ctx, +int32_t lis2duxs12_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lis2duxs12_long_cnt_int_value_get(stmdev_ctx_t *ctx, +int32_t lis2duxs12_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lis2duxs12_fsm_number_of_programs_set(stmdev_ctx_t *ctx, - uint8_t *buff); -int32_t lis2duxs12_fsm_number_of_programs_get(stmdev_ctx_t *ctx, - uint8_t *buff); +int32_t lis2duxs12_fsm_programs_num_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2duxs12_fsm_programs_num_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2duxs12_fsm_start_address_set(stmdev_ctx_t *ctx, +int32_t lis2duxs12_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lis2duxs12_fsm_start_address_get(stmdev_ctx_t *ctx, +int32_t lis2duxs12_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum @@ -2667,13 +2723,13 @@ typedef enum LIS2DUXS12_MLC_ON = 1, LIS2DUXS12_MLC_ON_BEFORE_FSM = 2, } lis2duxs12_mlc_mode_t; -int32_t lis2duxs12_mlc_set(stmdev_ctx_t *ctx, lis2duxs12_mlc_mode_t val); -int32_t lis2duxs12_mlc_get(stmdev_ctx_t *ctx, lis2duxs12_mlc_mode_t *val); +int32_t lis2duxs12_mlc_set(const stmdev_ctx_t *ctx, lis2duxs12_mlc_mode_t val); +int32_t lis2duxs12_mlc_get(const stmdev_ctx_t *ctx, lis2duxs12_mlc_mode_t *val); -int32_t lis2duxs12_mlc_status_get(stmdev_ctx_t *ctx, +int32_t lis2duxs12_mlc_status_get(const stmdev_ctx_t *ctx, lis2duxs12_mlc_status_mainpage_t *val); -int32_t lis2duxs12_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis2duxs12_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); typedef enum { @@ -2683,13 +2739,13 @@ typedef enum LIS2DUXS12_ODR_PRGS_100Hz = 3, LIS2DUXS12_ODR_PRGS_200Hz = 4, } lis2duxs12_mlc_odr_val_t; -int32_t lis2duxs12_mlc_data_rate_set(stmdev_ctx_t *ctx, +int32_t lis2duxs12_mlc_data_rate_set(const stmdev_ctx_t *ctx, lis2duxs12_mlc_odr_val_t val); -int32_t lis2duxs12_mlc_data_rate_get(stmdev_ctx_t *ctx, +int32_t lis2duxs12_mlc_data_rate_get(const stmdev_ctx_t *ctx, lis2duxs12_mlc_odr_val_t *val); -int32_t lis2duxs12_mlc_fifo_en_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2duxs12_mlc_fifo_en_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2duxs12_mlc_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2duxs12_mlc_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val); #ifdef __cplusplus } diff --git a/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.c b/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.c index 52d89e1a..ed65bf00 100644 --- a/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.c +++ b/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis2dw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lis2dw12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lis2dw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis2dw12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lis2dw12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -157,7 +167,7 @@ float_t lis2dw12_from_lsb_to_celsius(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_power_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_power_mode_set(const stmdev_ctx_t *ctx, lis2dw12_mode_t val) { lis2dw12_ctrl1_t ctrl1; @@ -196,7 +206,7 @@ int32_t lis2dw12_power_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_power_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_power_mode_get(const stmdev_ctx_t *ctx, lis2dw12_mode_t *val) { lis2dw12_ctrl1_t ctrl1; @@ -301,7 +311,7 @@ int32_t lis2dw12_power_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_data_rate_set(stmdev_ctx_t *ctx, lis2dw12_odr_t val) +int32_t lis2dw12_data_rate_set(const stmdev_ctx_t *ctx, lis2dw12_odr_t val) { lis2dw12_ctrl1_t ctrl1; lis2dw12_ctrl3_t ctrl3; @@ -337,7 +347,7 @@ int32_t lis2dw12_data_rate_set(stmdev_ctx_t *ctx, lis2dw12_odr_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_data_rate_get(stmdev_ctx_t *ctx, lis2dw12_odr_t *val) +int32_t lis2dw12_data_rate_get(const stmdev_ctx_t *ctx, lis2dw12_odr_t *val) { lis2dw12_ctrl1_t ctrl1; lis2dw12_ctrl3_t ctrl3; @@ -416,7 +426,7 @@ int32_t lis2dw12_data_rate_get(stmdev_ctx_t *ctx, lis2dw12_odr_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dw12_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dw12_ctrl2_t reg; int32_t ret; @@ -440,7 +450,7 @@ int32_t lis2dw12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dw12_ctrl2_t reg; @@ -460,7 +470,7 @@ int32_t lis2dw12_block_data_update_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_full_scale_set(stmdev_ctx_t *ctx, lis2dw12_fs_t val) +int32_t lis2dw12_full_scale_set(const stmdev_ctx_t *ctx, lis2dw12_fs_t val) { lis2dw12_ctrl6_t reg; int32_t ret; @@ -484,7 +494,7 @@ int32_t lis2dw12_full_scale_set(stmdev_ctx_t *ctx, lis2dw12_fs_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_full_scale_get(stmdev_ctx_t *ctx, lis2dw12_fs_t *val) +int32_t lis2dw12_full_scale_get(const stmdev_ctx_t *ctx, lis2dw12_fs_t *val) { lis2dw12_ctrl6_t reg; int32_t ret; @@ -525,7 +535,7 @@ int32_t lis2dw12_full_scale_get(stmdev_ctx_t *ctx, lis2dw12_fs_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_status_reg_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_status_reg_get(const stmdev_ctx_t *ctx, lis2dw12_status_t *val) { int32_t ret; @@ -543,7 +553,7 @@ int32_t lis2dw12_status_reg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dw12_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dw12_status_t reg; int32_t ret; @@ -562,7 +572,7 @@ int32_t lis2dw12_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_all_sources_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_all_sources_get(const stmdev_ctx_t *ctx, lis2dw12_all_sources_t *val) { int32_t ret; @@ -582,7 +592,7 @@ int32_t lis2dw12_all_sources_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis2dw12_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -601,7 +611,7 @@ int32_t lis2dw12_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis2dw12_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -620,7 +630,7 @@ int32_t lis2dw12_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis2dw12_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -639,7 +649,7 @@ int32_t lis2dw12_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis2dw12_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -658,7 +668,7 @@ int32_t lis2dw12_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis2dw12_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -677,7 +687,7 @@ int32_t lis2dw12_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis2dw12_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -696,7 +706,7 @@ int32_t lis2dw12_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_offset_weight_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_offset_weight_set(const stmdev_ctx_t *ctx, lis2dw12_usr_off_w_t val) { lis2dw12_ctrl_reg7_t reg; @@ -722,7 +732,7 @@ int32_t lis2dw12_offset_weight_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_offset_weight_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_offset_weight_get(const stmdev_ctx_t *ctx, lis2dw12_usr_off_w_t *val) { lis2dw12_ctrl_reg7_t reg; @@ -769,7 +779,7 @@ int32_t lis2dw12_offset_weight_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lis2dw12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -790,7 +800,7 @@ int32_t lis2dw12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lis2dw12_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -826,7 +836,7 @@ int32_t lis2dw12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis2dw12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -844,7 +854,7 @@ int32_t lis2dw12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dw12_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dw12_ctrl2_t reg; int32_t ret; @@ -869,7 +879,7 @@ int32_t lis2dw12_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dw12_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dw12_ctrl2_t reg; int32_t ret; @@ -888,7 +898,7 @@ int32_t lis2dw12_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dw12_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dw12_ctrl2_t reg; int32_t ret; @@ -912,7 +922,7 @@ int32_t lis2dw12_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dw12_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dw12_ctrl2_t reg; int32_t ret; @@ -931,7 +941,7 @@ int32_t lis2dw12_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dw12_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dw12_ctrl2_t reg; int32_t ret; @@ -955,7 +965,7 @@ int32_t lis2dw12_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dw12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dw12_ctrl2_t reg; int32_t ret; @@ -974,7 +984,7 @@ int32_t lis2dw12_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_self_test_set(stmdev_ctx_t *ctx, lis2dw12_st_t val) +int32_t lis2dw12_self_test_set(const stmdev_ctx_t *ctx, lis2dw12_st_t val) { lis2dw12_ctrl3_t reg; int32_t ret; @@ -998,7 +1008,7 @@ int32_t lis2dw12_self_test_set(stmdev_ctx_t *ctx, lis2dw12_st_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_self_test_get(stmdev_ctx_t *ctx, lis2dw12_st_t *val) +int32_t lis2dw12_self_test_get(const stmdev_ctx_t *ctx, lis2dw12_st_t *val) { lis2dw12_ctrl3_t reg; int32_t ret; @@ -1035,7 +1045,7 @@ int32_t lis2dw12_self_test_get(stmdev_ctx_t *ctx, lis2dw12_st_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_data_ready_mode_set(const stmdev_ctx_t *ctx, lis2dw12_drdy_pulsed_t val) { lis2dw12_ctrl_reg7_t reg; @@ -1060,7 +1070,7 @@ int32_t lis2dw12_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_data_ready_mode_get(const stmdev_ctx_t *ctx, lis2dw12_drdy_pulsed_t *val) { lis2dw12_ctrl_reg7_t reg; @@ -1107,7 +1117,7 @@ int32_t lis2dw12_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_filter_path_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_filter_path_set(const stmdev_ctx_t *ctx, lis2dw12_fds_t val) { lis2dw12_ctrl6_t ctrl6; @@ -1146,7 +1156,7 @@ int32_t lis2dw12_filter_path_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_filter_path_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_filter_path_get(const stmdev_ctx_t *ctx, lis2dw12_fds_t *val) { lis2dw12_ctrl6_t ctrl6; @@ -1192,7 +1202,7 @@ int32_t lis2dw12_filter_path_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_filter_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_filter_bandwidth_set(const stmdev_ctx_t *ctx, lis2dw12_bw_filt_t val) { lis2dw12_ctrl6_t reg; @@ -1218,7 +1228,7 @@ int32_t lis2dw12_filter_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_filter_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_filter_bandwidth_get(const stmdev_ctx_t *ctx, lis2dw12_bw_filt_t *val) { lis2dw12_ctrl6_t reg; @@ -1260,7 +1270,7 @@ int32_t lis2dw12_filter_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dw12_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dw12_ctrl_reg7_t reg; int32_t ret; @@ -1284,7 +1294,7 @@ int32_t lis2dw12_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dw12_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dw12_ctrl_reg7_t reg; int32_t ret; @@ -1316,7 +1326,7 @@ int32_t lis2dw12_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_spi_mode_set(stmdev_ctx_t *ctx, lis2dw12_sim_t val) +int32_t lis2dw12_spi_mode_set(const stmdev_ctx_t *ctx, lis2dw12_sim_t val) { lis2dw12_ctrl2_t reg; int32_t ret; @@ -1340,7 +1350,7 @@ int32_t lis2dw12_spi_mode_set(stmdev_ctx_t *ctx, lis2dw12_sim_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_spi_mode_get(stmdev_ctx_t *ctx, lis2dw12_sim_t *val) +int32_t lis2dw12_spi_mode_get(const stmdev_ctx_t *ctx, lis2dw12_sim_t *val) { lis2dw12_ctrl2_t reg; int32_t ret; @@ -1374,7 +1384,7 @@ int32_t lis2dw12_spi_mode_get(stmdev_ctx_t *ctx, lis2dw12_sim_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_i2c_interface_set(const stmdev_ctx_t *ctx, lis2dw12_i2c_disable_t val) { lis2dw12_ctrl2_t reg; @@ -1399,7 +1409,7 @@ int32_t lis2dw12_i2c_interface_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_i2c_interface_get(const stmdev_ctx_t *ctx, lis2dw12_i2c_disable_t *val) { lis2dw12_ctrl2_t reg; @@ -1433,7 +1443,7 @@ int32_t lis2dw12_i2c_interface_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_cs_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_cs_mode_set(const stmdev_ctx_t *ctx, lis2dw12_cs_pu_disc_t val) { lis2dw12_ctrl2_t reg; @@ -1458,7 +1468,7 @@ int32_t lis2dw12_cs_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_cs_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_cs_mode_get(const stmdev_ctx_t *ctx, lis2dw12_cs_pu_disc_t *val) { lis2dw12_ctrl2_t reg; @@ -1504,7 +1514,7 @@ int32_t lis2dw12_cs_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_pin_polarity_set(const stmdev_ctx_t *ctx, lis2dw12_h_lactive_t val) { lis2dw12_ctrl3_t reg; @@ -1529,7 +1539,7 @@ int32_t lis2dw12_pin_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_pin_polarity_get(const stmdev_ctx_t *ctx, lis2dw12_h_lactive_t *val) { lis2dw12_ctrl3_t reg; @@ -1563,7 +1573,7 @@ int32_t lis2dw12_pin_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_int_notification_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_int_notification_set(const stmdev_ctx_t *ctx, lis2dw12_lir_t val) { lis2dw12_ctrl3_t reg; @@ -1588,7 +1598,7 @@ int32_t lis2dw12_int_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_int_notification_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_int_notification_get(const stmdev_ctx_t *ctx, lis2dw12_lir_t *val) { lis2dw12_ctrl3_t reg; @@ -1622,7 +1632,7 @@ int32_t lis2dw12_int_notification_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_pin_mode_set(stmdev_ctx_t *ctx, lis2dw12_pp_od_t val) +int32_t lis2dw12_pin_mode_set(const stmdev_ctx_t *ctx, lis2dw12_pp_od_t val) { lis2dw12_ctrl3_t reg; int32_t ret; @@ -1646,7 +1656,7 @@ int32_t lis2dw12_pin_mode_set(stmdev_ctx_t *ctx, lis2dw12_pp_od_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_pin_mode_get(const stmdev_ctx_t *ctx, lis2dw12_pp_od_t *val) { lis2dw12_ctrl3_t reg; @@ -1680,7 +1690,7 @@ int32_t lis2dw12_pin_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_pin_int1_route_set(const stmdev_ctx_t *ctx, lis2dw12_ctrl4_int1_pad_ctrl_t *val) { lis2dw12_ctrl5_int2_pad_ctrl_t ctrl5_int2_pad_ctrl; @@ -1733,7 +1743,7 @@ int32_t lis2dw12_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_pin_int1_route_get(const stmdev_ctx_t *ctx, lis2dw12_ctrl4_int1_pad_ctrl_t *val) { int32_t ret; @@ -1752,7 +1762,7 @@ int32_t lis2dw12_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_pin_int2_route_set(const stmdev_ctx_t *ctx, lis2dw12_ctrl5_int2_pad_ctrl_t *val) { lis2dw12_ctrl4_int1_pad_ctrl_t ctrl4_int1_pad_ctrl; @@ -1804,7 +1814,7 @@ int32_t lis2dw12_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_pin_int2_route_get(const stmdev_ctx_t *ctx, lis2dw12_ctrl5_int2_pad_ctrl_t *val) { int32_t ret; @@ -1822,7 +1832,7 @@ int32_t lis2dw12_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dw12_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dw12_ctrl_reg7_t reg; int32_t ret; @@ -1846,7 +1856,7 @@ int32_t lis2dw12_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dw12_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dw12_ctrl_reg7_t reg; int32_t ret; @@ -1878,7 +1888,7 @@ int32_t lis2dw12_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dw12_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dw12_wake_up_ths_t reg; int32_t ret; @@ -1902,7 +1912,7 @@ int32_t lis2dw12_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dw12_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dw12_wake_up_ths_t reg; int32_t ret; @@ -1921,7 +1931,7 @@ int32_t lis2dw12_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dw12_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dw12_wake_up_dur_t reg; int32_t ret; @@ -1945,7 +1955,7 @@ int32_t lis2dw12_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dw12_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dw12_wake_up_dur_t reg; int32_t ret; @@ -1964,7 +1974,7 @@ int32_t lis2dw12_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_wkup_feed_data_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_wkup_feed_data_set(const stmdev_ctx_t *ctx, lis2dw12_usr_off_on_wu_t val) { lis2dw12_ctrl_reg7_t reg; @@ -1989,7 +1999,7 @@ int32_t lis2dw12_wkup_feed_data_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_wkup_feed_data_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_wkup_feed_data_get(const stmdev_ctx_t *ctx, lis2dw12_usr_off_on_wu_t *val) { lis2dw12_ctrl_reg7_t reg; @@ -2038,7 +2048,7 @@ int32_t lis2dw12_wkup_feed_data_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_act_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_act_mode_set(const stmdev_ctx_t *ctx, lis2dw12_sleep_on_t val) { lis2dw12_wake_up_ths_t wake_up_ths; @@ -2080,7 +2090,7 @@ int32_t lis2dw12_act_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_act_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_act_mode_get(const stmdev_ctx_t *ctx, lis2dw12_sleep_on_t *val) { lis2dw12_wake_up_ths_t wake_up_ths; @@ -2126,7 +2136,7 @@ int32_t lis2dw12_act_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dw12_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dw12_wake_up_dur_t reg; int32_t ret; @@ -2150,7 +2160,7 @@ int32_t lis2dw12_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dw12_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dw12_wake_up_dur_t reg; int32_t ret; @@ -2182,7 +2192,7 @@ int32_t lis2dw12_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dw12_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dw12_tap_ths_x_t reg; int32_t ret; @@ -2206,7 +2216,7 @@ int32_t lis2dw12_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dw12_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dw12_tap_ths_x_t reg; int32_t ret; @@ -2225,7 +2235,7 @@ int32_t lis2dw12_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dw12_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dw12_tap_ths_y_t reg; int32_t ret; @@ -2249,7 +2259,7 @@ int32_t lis2dw12_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dw12_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dw12_tap_ths_y_t reg; int32_t ret; @@ -2268,7 +2278,7 @@ int32_t lis2dw12_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_tap_axis_priority_set(const stmdev_ctx_t *ctx, lis2dw12_tap_prior_t val) { lis2dw12_tap_ths_y_t reg; @@ -2293,7 +2303,7 @@ int32_t lis2dw12_tap_axis_priority_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_tap_axis_priority_get(const stmdev_ctx_t *ctx, lis2dw12_tap_prior_t *val) { lis2dw12_tap_ths_y_t reg; @@ -2343,7 +2353,7 @@ int32_t lis2dw12_tap_axis_priority_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dw12_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dw12_tap_ths_z_t reg; int32_t ret; @@ -2367,7 +2377,7 @@ int32_t lis2dw12_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dw12_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dw12_tap_ths_z_t reg; int32_t ret; @@ -2386,7 +2396,7 @@ int32_t lis2dw12_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dw12_tap_ths_z_t reg; @@ -2411,7 +2421,7 @@ int32_t lis2dw12_tap_detection_on_z_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dw12_tap_ths_z_t reg; @@ -2431,7 +2441,7 @@ int32_t lis2dw12_tap_detection_on_z_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dw12_tap_ths_z_t reg; @@ -2456,7 +2466,7 @@ int32_t lis2dw12_tap_detection_on_y_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dw12_tap_ths_z_t reg; @@ -2476,7 +2486,7 @@ int32_t lis2dw12_tap_detection_on_y_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dw12_tap_ths_z_t reg; @@ -2501,7 +2511,7 @@ int32_t lis2dw12_tap_detection_on_x_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dw12_tap_ths_z_t reg; @@ -2525,7 +2535,7 @@ int32_t lis2dw12_tap_detection_on_x_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dw12_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dw12_int_dur_t reg; int32_t ret; @@ -2553,7 +2563,7 @@ int32_t lis2dw12_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dw12_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dw12_int_dur_t reg; int32_t ret; @@ -2576,7 +2586,7 @@ int32_t lis2dw12_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dw12_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dw12_int_dur_t reg; int32_t ret; @@ -2604,7 +2614,7 @@ int32_t lis2dw12_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dw12_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dw12_int_dur_t reg; int32_t ret; @@ -2628,7 +2638,7 @@ int32_t lis2dw12_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dw12_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dw12_int_dur_t reg; int32_t ret; @@ -2657,7 +2667,7 @@ int32_t lis2dw12_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dw12_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dw12_int_dur_t reg; int32_t ret; @@ -2676,7 +2686,7 @@ int32_t lis2dw12_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_tap_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_tap_mode_set(const stmdev_ctx_t *ctx, lis2dw12_single_double_tap_t val) { lis2dw12_wake_up_ths_t reg; @@ -2701,7 +2711,7 @@ int32_t lis2dw12_tap_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_tap_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_tap_mode_get(const stmdev_ctx_t *ctx, lis2dw12_single_double_tap_t *val) { lis2dw12_wake_up_ths_t reg; @@ -2735,7 +2745,7 @@ int32_t lis2dw12_tap_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_tap_src_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_tap_src_get(const stmdev_ctx_t *ctx, lis2dw12_tap_src_t *val) { int32_t ret; @@ -2766,7 +2776,7 @@ int32_t lis2dw12_tap_src_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dw12_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dw12_tap_ths_x_t reg; int32_t ret; @@ -2790,7 +2800,7 @@ int32_t lis2dw12_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dw12_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dw12_tap_ths_x_t reg; int32_t ret; @@ -2809,7 +2819,7 @@ int32_t lis2dw12_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dw12_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dw12_tap_ths_x_t reg; int32_t ret; @@ -2833,7 +2843,7 @@ int32_t lis2dw12_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dw12_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dw12_tap_ths_x_t reg; int32_t ret; @@ -2852,7 +2862,7 @@ int32_t lis2dw12_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_6d_src_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_6d_src_get(const stmdev_ctx_t *ctx, lis2dw12_sixd_src_t *val) { int32_t ret; @@ -2869,7 +2879,7 @@ int32_t lis2dw12_6d_src_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_6d_feed_data_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_6d_feed_data_set(const stmdev_ctx_t *ctx, lis2dw12_lpass_on6d_t val) { lis2dw12_ctrl_reg7_t reg; @@ -2894,7 +2904,7 @@ int32_t lis2dw12_6d_feed_data_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_6d_feed_data_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_6d_feed_data_get(const stmdev_ctx_t *ctx, lis2dw12_lpass_on6d_t *val) { lis2dw12_ctrl_reg7_t reg; @@ -2942,7 +2952,7 @@ int32_t lis2dw12_6d_feed_data_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dw12_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dw12_wake_up_dur_t wake_up_dur; lis2dw12_free_fall_t free_fall; @@ -2983,7 +2993,7 @@ int32_t lis2dw12_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dw12_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dw12_wake_up_dur_t wake_up_dur; lis2dw12_free_fall_t free_fall; @@ -3010,7 +3020,7 @@ int32_t lis2dw12_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_ff_threshold_set(const stmdev_ctx_t *ctx, lis2dw12_ff_ths_t val) { lis2dw12_free_fall_t reg; @@ -3035,7 +3045,7 @@ int32_t lis2dw12_ff_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_ff_threshold_get(const stmdev_ctx_t *ctx, lis2dw12_ff_ths_t *val) { lis2dw12_free_fall_t reg; @@ -3105,7 +3115,7 @@ int32_t lis2dw12_ff_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2dw12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2dw12_fifo_ctrl_t reg; int32_t ret; @@ -3129,7 +3139,7 @@ int32_t lis2dw12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dw12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dw12_fifo_ctrl_t reg; int32_t ret; @@ -3148,7 +3158,7 @@ int32_t lis2dw12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2dw12_fmode_t val) { lis2dw12_fifo_ctrl_t reg; @@ -3173,7 +3183,7 @@ int32_t lis2dw12_fifo_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2dw12_fmode_t *val) { lis2dw12_fifo_ctrl_t reg; @@ -3219,7 +3229,7 @@ int32_t lis2dw12_fifo_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dw12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dw12_fifo_samples_t reg; int32_t ret; @@ -3237,7 +3247,7 @@ int32_t lis2dw12_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dw12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dw12_fifo_samples_t reg; int32_t ret; @@ -3255,7 +3265,7 @@ int32_t lis2dw12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2dw12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2dw12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2dw12_fifo_samples_t reg; int32_t ret; diff --git a/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.h b/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.h index ef1d637c..7aea50d9 100644 --- a/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.h +++ b/sensor/stmemsc/lis2dw12_STdC/driver/lis2dw12_reg.h @@ -227,8 +227,7 @@ typedef struct typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN -uint8_t slp_mode : - 2; /* slp_mode_sel + slp_mode_1 */ + uint8_t slp_mode : 2; /* slp_mode_sel + slp_mode_1 */ uint8_t not_used_01 : 1; uint8_t h_lactive : 1; uint8_t lir : 1; @@ -240,8 +239,7 @@ uint8_t slp_mode : uint8_t lir : 1; uint8_t h_lactive : 1; uint8_t not_used_01 : 1; -uint8_t slp_mode : - 2; /* slp_mode_sel + slp_mode_1 */ + uint8_t slp_mode : 2; /* slp_mode_sel + slp_mode_1 */ #endif /* DRV_BYTE_ORDER */ } lis2dw12_ctrl3_t; @@ -669,10 +667,10 @@ typedef union * them with a custom implementation. */ -int32_t lis2dw12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lis2dw12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lis2dw12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lis2dw12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -709,9 +707,9 @@ typedef enum LIS2DW12_SINGLE_LOW_PWR_LOW_NOISE_2 = 0x19, LIS2DW12_SINGLE_LOW_LOW_NOISE_PWR_12bit = 0x18, } lis2dw12_mode_t; -int32_t lis2dw12_power_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_power_mode_set(const stmdev_ctx_t *ctx, lis2dw12_mode_t val); -int32_t lis2dw12_power_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_power_mode_get(const stmdev_ctx_t *ctx, lis2dw12_mode_t *val); typedef enum @@ -729,13 +727,13 @@ typedef enum LIS2DW12_XL_SET_SW_TRIG = 0x32, /* Use this only in SINGLE mode */ LIS2DW12_XL_SET_PIN_TRIG = 0x12, /* Use this only in SINGLE mode */ } lis2dw12_odr_t; -int32_t lis2dw12_data_rate_set(stmdev_ctx_t *ctx, lis2dw12_odr_t val); -int32_t lis2dw12_data_rate_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_data_rate_set(const stmdev_ctx_t *ctx, lis2dw12_odr_t val); +int32_t lis2dw12_data_rate_get(const stmdev_ctx_t *ctx, lis2dw12_odr_t *val); -int32_t lis2dw12_block_data_update_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dw12_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -745,14 +743,14 @@ typedef enum LIS2DW12_8g = 2, LIS2DW12_16g = 3, } lis2dw12_fs_t; -int32_t lis2dw12_full_scale_set(stmdev_ctx_t *ctx, lis2dw12_fs_t val); -int32_t lis2dw12_full_scale_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_full_scale_set(const stmdev_ctx_t *ctx, lis2dw12_fs_t val); +int32_t lis2dw12_full_scale_get(const stmdev_ctx_t *ctx, lis2dw12_fs_t *val); -int32_t lis2dw12_status_reg_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_status_reg_get(const stmdev_ctx_t *ctx, lis2dw12_status_t *val); -int32_t lis2dw12_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dw12_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -762,43 +760,43 @@ typedef struct lis2dw12_sixd_src_t sixd_src; lis2dw12_all_int_src_t all_int_src; } lis2dw12_all_sources_t; -int32_t lis2dw12_all_sources_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_all_sources_get(const stmdev_ctx_t *ctx, lis2dw12_all_sources_t *val); -int32_t lis2dw12_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis2dw12_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis2dw12_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis2dw12_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis2dw12_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis2dw12_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis2dw12_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis2dw12_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis2dw12_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis2dw12_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis2dw12_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis2dw12_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff); typedef enum { LIS2DW12_LSb_977ug = 0, LIS2DW12_LSb_15mg6 = 1, } lis2dw12_usr_off_w_t; -int32_t lis2dw12_offset_weight_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_offset_weight_set(const stmdev_ctx_t *ctx, lis2dw12_usr_off_w_t val); -int32_t lis2dw12_offset_weight_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_offset_weight_get(const stmdev_ctx_t *ctx, lis2dw12_usr_off_w_t *val); -int32_t lis2dw12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lis2dw12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lis2dw12_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lis2dw12_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis2dw12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis2dw12_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dw12_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dw12_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dw12_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dw12_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dw12_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dw12_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dw12_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dw12_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dw12_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dw12_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dw12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -806,17 +804,17 @@ typedef enum LIS2DW12_XL_ST_POSITIVE = 1, LIS2DW12_XL_ST_NEGATIVE = 2, } lis2dw12_st_t; -int32_t lis2dw12_self_test_set(stmdev_ctx_t *ctx, lis2dw12_st_t val); -int32_t lis2dw12_self_test_get(stmdev_ctx_t *ctx, lis2dw12_st_t *val); +int32_t lis2dw12_self_test_set(const stmdev_ctx_t *ctx, lis2dw12_st_t val); +int32_t lis2dw12_self_test_get(const stmdev_ctx_t *ctx, lis2dw12_st_t *val); typedef enum { LIS2DW12_DRDY_LATCHED = 0, LIS2DW12_DRDY_PULSED = 1, } lis2dw12_drdy_pulsed_t; -int32_t lis2dw12_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_data_ready_mode_set(const stmdev_ctx_t *ctx, lis2dw12_drdy_pulsed_t val); -int32_t lis2dw12_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_data_ready_mode_get(const stmdev_ctx_t *ctx, lis2dw12_drdy_pulsed_t *val); typedef enum @@ -825,9 +823,9 @@ typedef enum LIS2DW12_USER_OFFSET_ON_OUT = 0x01, LIS2DW12_HIGH_PASS_ON_OUT = 0x10, } lis2dw12_fds_t; -int32_t lis2dw12_filter_path_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_filter_path_set(const stmdev_ctx_t *ctx, lis2dw12_fds_t val); -int32_t lis2dw12_filter_path_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_filter_path_get(const stmdev_ctx_t *ctx, lis2dw12_fds_t *val); typedef enum @@ -837,30 +835,30 @@ typedef enum LIS2DW12_ODR_DIV_10 = 2, LIS2DW12_ODR_DIV_20 = 3, } lis2dw12_bw_filt_t; -int32_t lis2dw12_filter_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_filter_bandwidth_set(const stmdev_ctx_t *ctx, lis2dw12_bw_filt_t val); -int32_t lis2dw12_filter_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_filter_bandwidth_get(const stmdev_ctx_t *ctx, lis2dw12_bw_filt_t *val); -int32_t lis2dw12_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dw12_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dw12_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dw12_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LIS2DW12_SPI_4_WIRE = 0, LIS2DW12_SPI_3_WIRE = 1, } lis2dw12_sim_t; -int32_t lis2dw12_spi_mode_set(stmdev_ctx_t *ctx, lis2dw12_sim_t val); -int32_t lis2dw12_spi_mode_get(stmdev_ctx_t *ctx, lis2dw12_sim_t *val); +int32_t lis2dw12_spi_mode_set(const stmdev_ctx_t *ctx, lis2dw12_sim_t val); +int32_t lis2dw12_spi_mode_get(const stmdev_ctx_t *ctx, lis2dw12_sim_t *val); typedef enum { LIS2DW12_I2C_ENABLE = 0, LIS2DW12_I2C_DISABLE = 1, } lis2dw12_i2c_disable_t; -int32_t lis2dw12_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_i2c_interface_set(const stmdev_ctx_t *ctx, lis2dw12_i2c_disable_t val); -int32_t lis2dw12_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_i2c_interface_get(const stmdev_ctx_t *ctx, lis2dw12_i2c_disable_t *val); typedef enum @@ -868,9 +866,9 @@ typedef enum LIS2DW12_PULL_UP_CONNECT = 0, LIS2DW12_PULL_UP_DISCONNECT = 1, } lis2dw12_cs_pu_disc_t; -int32_t lis2dw12_cs_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_cs_mode_set(const stmdev_ctx_t *ctx, lis2dw12_cs_pu_disc_t val); -int32_t lis2dw12_cs_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_cs_mode_get(const stmdev_ctx_t *ctx, lis2dw12_cs_pu_disc_t *val); typedef enum @@ -878,9 +876,9 @@ typedef enum LIS2DW12_ACTIVE_HIGH = 0, LIS2DW12_ACTIVE_LOW = 1, } lis2dw12_h_lactive_t; -int32_t lis2dw12_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_pin_polarity_set(const stmdev_ctx_t *ctx, lis2dw12_h_lactive_t val); -int32_t lis2dw12_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_pin_polarity_get(const stmdev_ctx_t *ctx, lis2dw12_h_lactive_t *val); typedef enum @@ -888,9 +886,9 @@ typedef enum LIS2DW12_INT_PULSED = 0, LIS2DW12_INT_LATCHED = 1, } lis2dw12_lir_t; -int32_t lis2dw12_int_notification_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_int_notification_set(const stmdev_ctx_t *ctx, lis2dw12_lir_t val); -int32_t lis2dw12_int_notification_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_int_notification_get(const stmdev_ctx_t *ctx, lis2dw12_lir_t *val); typedef enum @@ -898,38 +896,38 @@ typedef enum LIS2DW12_PUSH_PULL = 0, LIS2DW12_OPEN_DRAIN = 1, } lis2dw12_pp_od_t; -int32_t lis2dw12_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_pin_mode_set(const stmdev_ctx_t *ctx, lis2dw12_pp_od_t val); -int32_t lis2dw12_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_pin_mode_get(const stmdev_ctx_t *ctx, lis2dw12_pp_od_t *val); -int32_t lis2dw12_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_pin_int1_route_set(const stmdev_ctx_t *ctx, lis2dw12_ctrl4_int1_pad_ctrl_t *val); -int32_t lis2dw12_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_pin_int1_route_get(const stmdev_ctx_t *ctx, lis2dw12_ctrl4_int1_pad_ctrl_t *val); -int32_t lis2dw12_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_pin_int2_route_set(const stmdev_ctx_t *ctx, lis2dw12_ctrl5_int2_pad_ctrl_t *val); -int32_t lis2dw12_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_pin_int2_route_get(const stmdev_ctx_t *ctx, lis2dw12_ctrl5_int2_pad_ctrl_t *val); -int32_t lis2dw12_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dw12_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dw12_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dw12_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dw12_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dw12_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dw12_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dw12_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dw12_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dw12_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dw12_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dw12_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LIS2DW12_HP_FEED = 0, LIS2DW12_USER_OFFSET_FEED = 1, } lis2dw12_usr_off_on_wu_t; -int32_t lis2dw12_wkup_feed_data_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_wkup_feed_data_set(const stmdev_ctx_t *ctx, lis2dw12_usr_off_on_wu_t val); -int32_t lis2dw12_wkup_feed_data_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_wkup_feed_data_get(const stmdev_ctx_t *ctx, lis2dw12_usr_off_on_wu_t *val); typedef enum @@ -938,19 +936,19 @@ typedef enum LIS2DW12_DETECT_ACT_INACT = 1, LIS2DW12_DETECT_STAT_MOTION = 3, } lis2dw12_sleep_on_t; -int32_t lis2dw12_act_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_act_mode_set(const stmdev_ctx_t *ctx, lis2dw12_sleep_on_t val); -int32_t lis2dw12_act_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_act_mode_get(const stmdev_ctx_t *ctx, lis2dw12_sleep_on_t *val); -int32_t lis2dw12_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dw12_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dw12_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dw12_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dw12_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dw12_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dw12_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dw12_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dw12_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dw12_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dw12_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dw12_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -961,58 +959,58 @@ typedef enum LIS2DW12_YZX = 5, LIS2DW12_ZXY = 6, } lis2dw12_tap_prior_t; -int32_t lis2dw12_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_tap_axis_priority_set(const stmdev_ctx_t *ctx, lis2dw12_tap_prior_t val); -int32_t lis2dw12_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_tap_axis_priority_get(const stmdev_ctx_t *ctx, lis2dw12_tap_prior_t *val); -int32_t lis2dw12_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dw12_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dw12_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dw12_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dw12_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dw12_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dw12_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dw12_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dw12_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dw12_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dw12_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dw12_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dw12_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dw12_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dw12_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dw12_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dw12_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dw12_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dw12_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dw12_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dw12_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dw12_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LIS2DW12_ONLY_SINGLE = 0, LIS2DW12_BOTH_SINGLE_DOUBLE = 1, } lis2dw12_single_double_tap_t; -int32_t lis2dw12_tap_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_tap_mode_set(const stmdev_ctx_t *ctx, lis2dw12_single_double_tap_t val); -int32_t lis2dw12_tap_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_tap_mode_get(const stmdev_ctx_t *ctx, lis2dw12_single_double_tap_t *val); -int32_t lis2dw12_tap_src_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_tap_src_get(const stmdev_ctx_t *ctx, lis2dw12_tap_src_t *val); -int32_t lis2dw12_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dw12_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dw12_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dw12_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dw12_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dw12_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dw12_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dw12_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dw12_6d_src_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_6d_src_get(const stmdev_ctx_t *ctx, lis2dw12_sixd_src_t *val); typedef enum @@ -1020,13 +1018,13 @@ typedef enum LIS2DW12_ODR_DIV_2_FEED = 0, LIS2DW12_LPF2_FEED = 1, } lis2dw12_lpass_on6d_t; -int32_t lis2dw12_6d_feed_data_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_6d_feed_data_set(const stmdev_ctx_t *ctx, lis2dw12_lpass_on6d_t val); -int32_t lis2dw12_6d_feed_data_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_6d_feed_data_get(const stmdev_ctx_t *ctx, lis2dw12_lpass_on6d_t *val); -int32_t lis2dw12_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dw12_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dw12_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dw12_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -1039,13 +1037,13 @@ typedef enum LIS2DW12_FF_TSH_15LSb_FS2g = 6, LIS2DW12_FF_TSH_16LSb_FS2g = 7, } lis2dw12_ff_ths_t; -int32_t lis2dw12_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_ff_threshold_set(const stmdev_ctx_t *ctx, lis2dw12_ff_ths_t val); -int32_t lis2dw12_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_ff_threshold_get(const stmdev_ctx_t *ctx, lis2dw12_ff_ths_t *val); -int32_t lis2dw12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2dw12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dw12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2dw12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -1055,16 +1053,16 @@ typedef enum LIS2DW12_BYPASS_TO_STREAM_MODE = 4, LIS2DW12_STREAM_MODE = 6, } lis2dw12_fmode_t; -int32_t lis2dw12_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lis2dw12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2dw12_fmode_t val); -int32_t lis2dw12_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lis2dw12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2dw12_fmode_t *val); -int32_t lis2dw12_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dw12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dw12_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dw12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2dw12_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2dw12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); /** * @} diff --git a/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.c b/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.c index 4d04ce50..a880de50 100644 --- a/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.c +++ b/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.c @@ -45,12 +45,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis2hh12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lis2hh12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -66,12 +71,17 @@ int32_t __weak lis2hh12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis2hh12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lis2hh12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -106,7 +116,8 @@ float_t lis2hh12_from_fs8g_to_mg(int16_t lsb) float_t lis2hh12_from_lsb_to_celsius(int16_t lsb) { - return (((float_t)lsb / 8.0f) + 25.0f); + /* 8 LSB/C - 11bit resolution */ + return ((((float_t)lsb / 32.0f) / 8.0f) + 25.0f); } /** @@ -130,7 +141,7 @@ float_t lis2hh12_from_lsb_to_celsius(int16_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_axis_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_axis_set(const stmdev_ctx_t *ctx, lis2hh12_xl_axis_t val) { lis2hh12_ctrl1_t ctrl1; @@ -157,7 +168,7 @@ int32_t lis2hh12_xl_axis_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_axis_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_axis_get(const stmdev_ctx_t *ctx, lis2hh12_xl_axis_t *val) { lis2hh12_ctrl1_t ctrl1; @@ -179,7 +190,7 @@ int32_t lis2hh12_xl_axis_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2hh12_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2hh12_ctrl1_t ctrl1; int32_t ret; @@ -203,7 +214,7 @@ int32_t lis2hh12_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2hh12_ctrl1_t ctrl1; @@ -223,7 +234,7 @@ int32_t lis2hh12_block_data_update_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_data_rate_set(const stmdev_ctx_t *ctx, lis2hh12_xl_data_rate_t val) { lis2hh12_ctrl1_t ctrl1; @@ -248,7 +259,7 @@ int32_t lis2hh12_xl_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_data_rate_get(const stmdev_ctx_t *ctx, lis2hh12_xl_data_rate_t *val) { lis2hh12_ctrl1_t ctrl1; @@ -302,7 +313,7 @@ int32_t lis2hh12_xl_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_full_scale_set(const stmdev_ctx_t *ctx, lis2hh12_xl_fs_t val) { lis2hh12_ctrl4_t ctrl4; @@ -327,7 +338,7 @@ int32_t lis2hh12_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_full_scale_get(const stmdev_ctx_t *ctx, lis2hh12_xl_fs_t *val) { lis2hh12_ctrl4_t ctrl4; @@ -365,7 +376,7 @@ int32_t lis2hh12_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_decimation_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_decimation_set(const stmdev_ctx_t *ctx, lis2hh12_dec_t val) { lis2hh12_ctrl5_t ctrl5; @@ -390,7 +401,7 @@ int32_t lis2hh12_xl_decimation_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_decimation_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_decimation_get(const stmdev_ctx_t *ctx, lis2hh12_dec_t *val) { lis2hh12_ctrl5_t ctrl5; @@ -432,7 +443,7 @@ int32_t lis2hh12_xl_decimation_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2hh12_status_t status; @@ -465,7 +476,7 @@ int32_t lis2hh12_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lis2hh12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -486,7 +497,7 @@ int32_t lis2hh12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lis2hh12_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -522,7 +533,7 @@ int32_t lis2hh12_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_dev_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis2hh12_dev_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -540,7 +551,7 @@ int32_t lis2hh12_dev_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_dev_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2hh12_dev_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2hh12_ctrl5_t ctrl5; int32_t ret; @@ -565,7 +576,7 @@ int32_t lis2hh12_dev_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_dev_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2hh12_dev_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2hh12_ctrl5_t ctrl5; int32_t ret; @@ -584,7 +595,7 @@ int32_t lis2hh12_dev_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_dev_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2hh12_dev_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2hh12_ctrl6_t ctrl6; int32_t ret; @@ -608,7 +619,7 @@ int32_t lis2hh12_dev_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_dev_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2hh12_dev_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2hh12_ctrl6_t ctrl6; int32_t ret; @@ -627,7 +638,7 @@ int32_t lis2hh12_dev_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_dev_status_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_dev_status_get(const stmdev_ctx_t *ctx, lis2hh12_status_reg_t *val) { lis2hh12_status_t status; @@ -667,7 +678,7 @@ int32_t lis2hh12_dev_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_filter_int_path_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_filter_int_path_set(const stmdev_ctx_t *ctx, lis2hh12_xl_hp_path_t val) { lis2hh12_ctrl2_t ctrl2; @@ -692,7 +703,7 @@ int32_t lis2hh12_xl_filter_int_path_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_filter_int_path_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_filter_int_path_get(const stmdev_ctx_t *ctx, lis2hh12_xl_hp_path_t *val) { lis2hh12_ctrl2_t ctrl2; @@ -730,7 +741,7 @@ int32_t lis2hh12_xl_filter_int_path_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_filter_out_path_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_filter_out_path_set(const stmdev_ctx_t *ctx, lis2hh12_xl_out_path_t val) { lis2hh12_ctrl1_t ctrl1; @@ -767,7 +778,7 @@ int32_t lis2hh12_xl_filter_out_path_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_filter_out_path_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_filter_out_path_get(const stmdev_ctx_t *ctx, lis2hh12_xl_out_path_t *val) { lis2hh12_ctrl1_t ctrl1; @@ -812,7 +823,7 @@ int32_t lis2hh12_xl_filter_out_path_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_filter_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_filter_hp_bandwidth_set(const stmdev_ctx_t *ctx, lis2hh12_xl_hp_bw_t val) { lis2hh12_ctrl2_t ctrl2; @@ -839,7 +850,7 @@ int32_t lis2hh12_xl_filter_hp_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_filter_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_filter_hp_bandwidth_get(const stmdev_ctx_t *ctx, lis2hh12_xl_hp_bw_t *val) { lis2hh12_ctrl2_t ctrl2; @@ -898,7 +909,7 @@ int32_t lis2hh12_xl_filter_hp_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_filter_low_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_filter_low_bandwidth_set(const stmdev_ctx_t *ctx, lis2hh12_xl_lp_bw_t val) { lis2hh12_ctrl2_t ctrl2; @@ -924,7 +935,7 @@ int32_t lis2hh12_xl_filter_low_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_filter_low_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_filter_low_bandwidth_get(const stmdev_ctx_t *ctx, lis2hh12_xl_lp_bw_t *val) { lis2hh12_ctrl2_t ctrl2; @@ -966,7 +977,7 @@ int32_t lis2hh12_xl_filter_low_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_filter_aalias_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_filter_aalias_bandwidth_set(const stmdev_ctx_t *ctx, lis2hh12_xl_filt_aa_bw_t val) { lis2hh12_ctrl4_t ctrl4; @@ -992,7 +1003,7 @@ int32_t lis2hh12_xl_filter_aalias_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_filter_aalias_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_filter_aalias_bandwidth_get(const stmdev_ctx_t *ctx, lis2hh12_xl_filt_aa_bw_t *val) { lis2hh12_ctrl4_t ctrl4; @@ -1038,7 +1049,7 @@ int32_t lis2hh12_xl_filter_aalias_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_filter_reference_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_filter_reference_set(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -1063,7 +1074,7 @@ int32_t lis2hh12_xl_filter_reference_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_filter_reference_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_filter_reference_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -1101,7 +1112,7 @@ int32_t lis2hh12_xl_filter_reference_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_spi_mode_set(stmdev_ctx_t *ctx, lis2hh12_sim_t val) +int32_t lis2hh12_spi_mode_set(const stmdev_ctx_t *ctx, lis2hh12_sim_t val) { lis2hh12_ctrl4_t ctrl4; int32_t ret; @@ -1125,7 +1136,7 @@ int32_t lis2hh12_spi_mode_set(stmdev_ctx_t *ctx, lis2hh12_sim_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_spi_mode_get(stmdev_ctx_t *ctx, lis2hh12_sim_t *val) +int32_t lis2hh12_spi_mode_get(const stmdev_ctx_t *ctx, lis2hh12_sim_t *val) { lis2hh12_ctrl4_t ctrl4; int32_t ret; @@ -1158,7 +1169,7 @@ int32_t lis2hh12_spi_mode_get(stmdev_ctx_t *ctx, lis2hh12_sim_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_i2c_interface_set(const stmdev_ctx_t *ctx, lis2hh12_i2c_dis_t val) { lis2hh12_ctrl4_t ctrl4; @@ -1183,7 +1194,7 @@ int32_t lis2hh12_i2c_interface_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_i2c_interface_get(const stmdev_ctx_t *ctx, lis2hh12_i2c_dis_t *val) { lis2hh12_ctrl4_t ctrl4; @@ -1218,7 +1229,7 @@ int32_t lis2hh12_i2c_interface_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_auto_increment_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_auto_increment_set(const stmdev_ctx_t *ctx, lis2hh12_auto_inc_t val) { lis2hh12_ctrl4_t ctrl4; @@ -1244,7 +1255,7 @@ int32_t lis2hh12_auto_increment_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_auto_increment_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_auto_increment_get(const stmdev_ctx_t *ctx, lis2hh12_auto_inc_t *val) { lis2hh12_ctrl4_t ctrl4; @@ -1291,7 +1302,7 @@ int32_t lis2hh12_auto_increment_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_pin_int1_route_set(const stmdev_ctx_t *ctx, lis2hh12_pin_int1_route_t val) { lis2hh12_ctrl3_t ctrl3; @@ -1321,7 +1332,7 @@ int32_t lis2hh12_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_pin_int1_route_get(const stmdev_ctx_t *ctx, lis2hh12_pin_int1_route_t *val) { lis2hh12_ctrl3_t ctrl3; @@ -1346,7 +1357,7 @@ int32_t lis2hh12_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_pin_mode_set(stmdev_ctx_t *ctx, lis2hh12_pp_od_t val) +int32_t lis2hh12_pin_mode_set(const stmdev_ctx_t *ctx, lis2hh12_pp_od_t val) { lis2hh12_ctrl5_t ctrl5; int32_t ret; @@ -1370,7 +1381,7 @@ int32_t lis2hh12_pin_mode_set(stmdev_ctx_t *ctx, lis2hh12_pp_od_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_pin_mode_get(const stmdev_ctx_t *ctx, lis2hh12_pp_od_t *val) { lis2hh12_ctrl5_t ctrl5; @@ -1404,7 +1415,7 @@ int32_t lis2hh12_pin_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_pin_polarity_set(const stmdev_ctx_t *ctx, lis2hh12_pin_pol_t val) { lis2hh12_ctrl5_t ctrl5; @@ -1429,7 +1440,7 @@ int32_t lis2hh12_pin_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_pin_polarity_get(const stmdev_ctx_t *ctx, lis2hh12_pin_pol_t *val) { lis2hh12_ctrl5_t ctrl5; @@ -1463,7 +1474,7 @@ int32_t lis2hh12_pin_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_pin_int2_route_set(const stmdev_ctx_t *ctx, lis2hh12_pin_int2_route_t val) { lis2hh12_ctrl6_t ctrl6; @@ -1493,7 +1504,7 @@ int32_t lis2hh12_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_pin_int2_route_get(const stmdev_ctx_t *ctx, lis2hh12_pin_int2_route_t *val) { lis2hh12_ctrl6_t ctrl6; @@ -1518,7 +1529,7 @@ int32_t lis2hh12_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_pin_notification_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_pin_notification_set(const stmdev_ctx_t *ctx, lis2hh12_lir_t val) { lis2hh12_ctrl7_t ctrl7; @@ -1543,7 +1554,7 @@ int32_t lis2hh12_pin_notification_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_pin_notification_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_pin_notification_get(const stmdev_ctx_t *ctx, lis2hh12_lir_t *val) { lis2hh12_ctrl7_t ctrl7; @@ -1577,7 +1588,7 @@ int32_t lis2hh12_pin_notification_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_pin_logic_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_pin_logic_set(const stmdev_ctx_t *ctx, lis2hh12_pin_logic_t val) { lis2hh12_ig_cfg1_t ig_cfg1; @@ -1614,7 +1625,7 @@ int32_t lis2hh12_pin_logic_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_pin_logic_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_pin_logic_get(const stmdev_ctx_t *ctx, lis2hh12_pin_logic_t *val) { lis2hh12_ig_cfg1_t ig_cfg1; @@ -1675,7 +1686,7 @@ int32_t lis2hh12_pin_logic_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_trshld_mode_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_trshld_mode_set(const stmdev_ctx_t *ctx, lis2hh12_dcrm_t val) { lis2hh12_ctrl7_t ctrl7; @@ -1700,7 +1711,7 @@ int32_t lis2hh12_xl_trshld_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_trshld_mode_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_trshld_mode_get(const stmdev_ctx_t *ctx, lis2hh12_dcrm_t *val) { lis2hh12_ctrl7_t ctrl7; @@ -1735,7 +1746,7 @@ int32_t lis2hh12_xl_trshld_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_trshld_axis_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_trshld_axis_set(const stmdev_ctx_t *ctx, lis2hh12_xl_trshld_en_t val) { lis2hh12_ig_cfg1_t ig_cfg1; @@ -1783,7 +1794,7 @@ int32_t lis2hh12_xl_trshld_axis_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_trshld_axis_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_trshld_axis_get(const stmdev_ctx_t *ctx, lis2hh12_xl_trshld_en_t *val) { lis2hh12_ig_cfg1_t ig_cfg1; @@ -1821,7 +1832,7 @@ int32_t lis2hh12_xl_trshld_axis_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_trshld_src_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_trshld_src_get(const stmdev_ctx_t *ctx, lis2hh12_xl_trshld_src_t *val) { lis2hh12_ig_src1_t ig_src1; @@ -1861,7 +1872,7 @@ int32_t lis2hh12_xl_trshld_src_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_trshld_set(stmdev_ctx_t *ctx, uint8_t ig1_x, +int32_t lis2hh12_xl_trshld_set(const stmdev_ctx_t *ctx, uint8_t ig1_x, uint8_t ig1_y, uint8_t ig1_z, uint8_t ig2_xyz) { @@ -1895,7 +1906,7 @@ int32_t lis2hh12_xl_trshld_set(stmdev_ctx_t *ctx, uint8_t ig1_x, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_trshld_get(stmdev_ctx_t *ctx, uint8_t *ig1_x, +int32_t lis2hh12_xl_trshld_get(const stmdev_ctx_t *ctx, uint8_t *ig1_x, uint8_t *ig1_y, uint8_t *ig1_z, uint8_t *ig2_xyz) { @@ -1929,7 +1940,7 @@ int32_t lis2hh12_xl_trshld_get(stmdev_ctx_t *ctx, uint8_t *ig1_x, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_trshld_min_sample_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_trshld_min_sample_set(const stmdev_ctx_t *ctx, uint8_t ig1_sam, uint8_t ig2_sam) { lis2hh12_ig_dur1_t ig_dur1; @@ -1986,7 +1997,7 @@ int32_t lis2hh12_xl_trshld_min_sample_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_trshld_min_sample_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_trshld_min_sample_get(const stmdev_ctx_t *ctx, uint8_t *ig1_sam, uint8_t *ig2_sam) { lis2hh12_ig_dur1_t ig_dur1; @@ -2026,7 +2037,7 @@ int32_t lis2hh12_xl_trshld_min_sample_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2hh12_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2hh12_act_ths_t act_ths; int32_t ret; @@ -2050,7 +2061,7 @@ int32_t lis2hh12_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2hh12_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2hh12_act_ths_t act_ths; int32_t ret; @@ -2069,7 +2080,7 @@ int32_t lis2hh12_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_act_duration_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2hh12_act_duration_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2hh12_act_dur_t act_dur; int32_t ret; @@ -2093,7 +2104,7 @@ int32_t lis2hh12_act_duration_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_act_duration_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2hh12_act_duration_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2hh12_act_dur_t act_dur; int32_t ret; @@ -2125,7 +2136,7 @@ int32_t lis2hh12_act_duration_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_6d_mode_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_6d_mode_set(const stmdev_ctx_t *ctx, lis2hh12_6d_mode_t val) { lis2hh12_ig_cfg1_t ig_cfg1; @@ -2174,7 +2185,7 @@ int32_t lis2hh12_6d_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_6d_mode_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_6d_mode_get(const stmdev_ctx_t *ctx, lis2hh12_6d_mode_t *val) { lis2hh12_ig_cfg1_t ig_cfg1; @@ -2245,7 +2256,7 @@ int32_t lis2hh12_6d_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2hh12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2hh12_fifo_ctrl_t fifo_ctrl; lis2hh12_ctrl3_t ctrl3; @@ -2292,7 +2303,7 @@ int32_t lis2hh12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2hh12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2hh12_fifo_ctrl_t fifo_ctrl; int32_t ret; @@ -2312,7 +2323,7 @@ int32_t lis2hh12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2hh12_fifo_md_t val) { lis2hh12_fifo_ctrl_t fifo_ctrl; @@ -2351,7 +2362,7 @@ int32_t lis2hh12_fifo_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2hh12_fifo_md_t *val) { lis2hh12_fifo_ctrl_t fifo_ctrl; @@ -2412,7 +2423,7 @@ int32_t lis2hh12_fifo_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_fifo_status_get(const stmdev_ctx_t *ctx, lis2hh12_fifo_stat_t *val) { lis2hh12_fifo_src_t fifo_src; @@ -2448,7 +2459,7 @@ int32_t lis2hh12_fifo_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_self_test_set(const stmdev_ctx_t *ctx, lis2hh12_xl_st_t val) { lis2hh12_ctrl5_t ctrl5; @@ -2473,7 +2484,7 @@ int32_t lis2hh12_xl_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis2hh12_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_self_test_get(const stmdev_ctx_t *ctx, lis2hh12_xl_st_t *val) { lis2hh12_ctrl5_t ctrl5; diff --git a/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.h b/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.h index 9b35afcf..46ed50f9 100644 --- a/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.h +++ b/sensor/stmemsc/lis2hh12_STdC/driver/lis2hh12_reg.h @@ -585,10 +585,10 @@ typedef union * them with a custom implementation. */ -int32_t lis2hh12_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lis2hh12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lis2hh12_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lis2hh12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -604,14 +604,14 @@ typedef struct uint8_t yen : 1; uint8_t zen : 1; } lis2hh12_xl_axis_t; -int32_t lis2hh12_xl_axis_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_axis_set(const stmdev_ctx_t *ctx, lis2hh12_xl_axis_t val); -int32_t lis2hh12_xl_axis_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_axis_get(const stmdev_ctx_t *ctx, lis2hh12_xl_axis_t *val); -int32_t lis2hh12_block_data_update_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2hh12_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -624,9 +624,9 @@ typedef enum LIS2HH12_XL_ODR_400Hz = 0x05, LIS2HH12_XL_ODR_800Hz = 0x06, } lis2hh12_xl_data_rate_t; -int32_t lis2hh12_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_data_rate_set(const stmdev_ctx_t *ctx, lis2hh12_xl_data_rate_t val); -int32_t lis2hh12_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_data_rate_get(const stmdev_ctx_t *ctx, lis2hh12_xl_data_rate_t *val); typedef enum @@ -636,9 +636,9 @@ typedef enum LIS2HH12_4g = 0x02, LIS2HH12_8g = 0x03, } lis2hh12_xl_fs_t; -int32_t lis2hh12_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_full_scale_set(const stmdev_ctx_t *ctx, lis2hh12_xl_fs_t val); -int32_t lis2hh12_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_full_scale_get(const stmdev_ctx_t *ctx, lis2hh12_xl_fs_t *val); typedef enum @@ -648,26 +648,26 @@ typedef enum LIS2HH12_EVERY_4_SAMPLES = 0x02, LIS2HH12_EVERY_8_SAMPLES = 0x03, } lis2hh12_dec_t; -int32_t lis2hh12_xl_decimation_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_decimation_set(const stmdev_ctx_t *ctx, lis2hh12_dec_t val); -int32_t lis2hh12_xl_decimation_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_decimation_get(const stmdev_ctx_t *ctx, lis2hh12_dec_t *val); -int32_t lis2hh12_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2hh12_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lis2hh12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lis2hh12_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lis2hh12_dev_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis2hh12_dev_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis2hh12_dev_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2hh12_dev_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2hh12_dev_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2hh12_dev_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2hh12_dev_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2hh12_dev_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2hh12_dev_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2hh12_dev_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -680,7 +680,7 @@ typedef struct uint8_t zor : 1; uint8_t zyxor : 1; } lis2hh12_status_reg_t; -int32_t lis2hh12_dev_status_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_dev_status_get(const stmdev_ctx_t *ctx, lis2hh12_status_reg_t *val); typedef enum @@ -690,9 +690,9 @@ typedef enum LIS2HH12_HP_ON_INT_GEN_2 = 0x01, LIS2HH12_HP_ON_BOTH_GEN = 0x03, } lis2hh12_xl_hp_path_t; -int32_t lis2hh12_xl_filter_int_path_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_filter_int_path_set(const stmdev_ctx_t *ctx, lis2hh12_xl_hp_path_t val); -int32_t lis2hh12_xl_filter_int_path_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_filter_int_path_get(const stmdev_ctx_t *ctx, lis2hh12_xl_hp_path_t *val); typedef enum @@ -701,9 +701,9 @@ typedef enum LIS2HH12_FILT_HP = 0x02, LIS2HH12_FILT_LP = 0x01, } lis2hh12_xl_out_path_t; -int32_t lis2hh12_xl_filter_out_path_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_filter_out_path_set(const stmdev_ctx_t *ctx, lis2hh12_xl_out_path_t val); -int32_t lis2hh12_xl_filter_out_path_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_filter_out_path_get(const stmdev_ctx_t *ctx, lis2hh12_xl_out_path_t *val); typedef enum @@ -717,9 +717,9 @@ typedef enum LIS2HH12_HP_ODR_DIV_9_REF_MD = 0x21, LIS2HH12_HP_ODR_DIV_400_REF_MD = 0x31, } lis2hh12_xl_hp_bw_t; -int32_t lis2hh12_xl_filter_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_filter_hp_bandwidth_set(const stmdev_ctx_t *ctx, lis2hh12_xl_hp_bw_t val); -int32_t lis2hh12_xl_filter_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_filter_hp_bandwidth_get(const stmdev_ctx_t *ctx, lis2hh12_xl_hp_bw_t *val); typedef enum @@ -729,9 +729,9 @@ typedef enum LIS2HH12_LP_ODR_DIV_9 = 2, LIS2HH12_LP_ODR_DIV_400 = 3, } lis2hh12_xl_lp_bw_t; -int32_t lis2hh12_xl_filter_low_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_filter_low_bandwidth_set(const stmdev_ctx_t *ctx, lis2hh12_xl_lp_bw_t val); -int32_t lis2hh12_xl_filter_low_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_filter_low_bandwidth_get(const stmdev_ctx_t *ctx, lis2hh12_xl_lp_bw_t *val); typedef enum @@ -742,14 +742,14 @@ typedef enum LIS2HH12_105Hz = 0x12, LIS2HH12_50Hz = 0x13, } lis2hh12_xl_filt_aa_bw_t; -int32_t lis2hh12_xl_filter_aalias_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_filter_aalias_bandwidth_set(const stmdev_ctx_t *ctx, lis2hh12_xl_filt_aa_bw_t val); -int32_t lis2hh12_xl_filter_aalias_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_filter_aalias_bandwidth_get(const stmdev_ctx_t *ctx, lis2hh12_xl_filt_aa_bw_t *val); -int32_t lis2hh12_xl_filter_reference_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_filter_reference_set(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lis2hh12_xl_filter_reference_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_filter_reference_get(const stmdev_ctx_t *ctx, int16_t *val); typedef enum @@ -757,17 +757,17 @@ typedef enum LIS2HH12_SPI_4_WIRE = 0x00, LIS2HH12_SPI_3_WIRE = 0x01, } lis2hh12_sim_t; -int32_t lis2hh12_spi_mode_set(stmdev_ctx_t *ctx, lis2hh12_sim_t val); -int32_t lis2hh12_spi_mode_get(stmdev_ctx_t *ctx, lis2hh12_sim_t *val); +int32_t lis2hh12_spi_mode_set(const stmdev_ctx_t *ctx, lis2hh12_sim_t val); +int32_t lis2hh12_spi_mode_get(const stmdev_ctx_t *ctx, lis2hh12_sim_t *val); typedef enum { LIS2HH12_I2C_ENABLE = 0x00, LIS2HH12_I2C_DISABLE = 0x01, } lis2hh12_i2c_dis_t; -int32_t lis2hh12_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_i2c_interface_set(const stmdev_ctx_t *ctx, lis2hh12_i2c_dis_t val); -int32_t lis2hh12_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_i2c_interface_get(const stmdev_ctx_t *ctx, lis2hh12_i2c_dis_t *val); typedef enum @@ -775,9 +775,9 @@ typedef enum LIS2HH12_DISABLE = 0x00, LIS2HH12_ENABLE = 0x01, } lis2hh12_auto_inc_t; -int32_t lis2hh12_auto_increment_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_auto_increment_set(const stmdev_ctx_t *ctx, lis2hh12_auto_inc_t val); -int32_t lis2hh12_auto_increment_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_auto_increment_get(const stmdev_ctx_t *ctx, lis2hh12_auto_inc_t *val); typedef struct @@ -789,9 +789,9 @@ typedef struct uint8_t int1_ig2 : 1; uint8_t int1_inact : 1; } lis2hh12_pin_int1_route_t; -int32_t lis2hh12_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_pin_int1_route_set(const stmdev_ctx_t *ctx, lis2hh12_pin_int1_route_t val); -int32_t lis2hh12_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_pin_int1_route_get(const stmdev_ctx_t *ctx, lis2hh12_pin_int1_route_t *val); typedef enum @@ -799,9 +799,9 @@ typedef enum LIS2HH12_PUSH_PULL = 0x00, LIS2HH12_OPEN_DRAIN = 0x01, } lis2hh12_pp_od_t; -int32_t lis2hh12_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_pin_mode_set(const stmdev_ctx_t *ctx, lis2hh12_pp_od_t val); -int32_t lis2hh12_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_pin_mode_get(const stmdev_ctx_t *ctx, lis2hh12_pp_od_t *val); typedef enum @@ -809,9 +809,9 @@ typedef enum LIS2HH12_ACTIVE_HIGH = 0x00, LIS2HH12_ACTIVE_LOW = 0x01, } lis2hh12_pin_pol_t; -int32_t lis2hh12_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_pin_polarity_set(const stmdev_ctx_t *ctx, lis2hh12_pin_pol_t val); -int32_t lis2hh12_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_pin_polarity_get(const stmdev_ctx_t *ctx, lis2hh12_pin_pol_t *val); typedef struct @@ -823,9 +823,9 @@ typedef struct uint8_t int2_ig2 : 1; uint8_t int2_boot : 1; } lis2hh12_pin_int2_route_t; -int32_t lis2hh12_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_pin_int2_route_set(const stmdev_ctx_t *ctx, lis2hh12_pin_int2_route_t val); -int32_t lis2hh12_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_pin_int2_route_get(const stmdev_ctx_t *ctx, lis2hh12_pin_int2_route_t *val); typedef enum @@ -833,9 +833,9 @@ typedef enum LIS2HH12_INT_PULSED = 0x00, LIS2HH12_INT_LATCHED = 0x01, } lis2hh12_lir_t; -int32_t lis2hh12_pin_notification_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_pin_notification_set(const stmdev_ctx_t *ctx, lis2hh12_lir_t val); -int32_t lis2hh12_pin_notification_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_pin_notification_get(const stmdev_ctx_t *ctx, lis2hh12_lir_t *val); typedef enum { @@ -844,9 +844,9 @@ typedef enum LIS2HH12_IG1_OR_IG2_AND = 0x10, LIS2HH12_IG1_AND_IG2_AND = 0x11, } lis2hh12_pin_logic_t; -int32_t lis2hh12_pin_logic_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_pin_logic_set(const stmdev_ctx_t *ctx, lis2hh12_pin_logic_t val); -int32_t lis2hh12_pin_logic_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_pin_logic_get(const stmdev_ctx_t *ctx, lis2hh12_pin_logic_t *val); typedef enum @@ -854,9 +854,9 @@ typedef enum LIS2HH12_RESET_MODE = 0x00, LIS2HH12_DECREMENT_MODE = 0x01, } lis2hh12_dcrm_t; -int32_t lis2hh12_xl_trshld_mode_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_trshld_mode_set(const stmdev_ctx_t *ctx, lis2hh12_dcrm_t val); -int32_t lis2hh12_xl_trshld_mode_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_trshld_mode_get(const stmdev_ctx_t *ctx, lis2hh12_dcrm_t *val); typedef struct @@ -874,9 +874,9 @@ typedef struct uint16_t ig2_zlie : 1; uint16_t ig2_zhie : 1; } lis2hh12_xl_trshld_en_t; -int32_t lis2hh12_xl_trshld_axis_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_trshld_axis_set(const stmdev_ctx_t *ctx, lis2hh12_xl_trshld_en_t val); -int32_t lis2hh12_xl_trshld_axis_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_trshld_axis_get(const stmdev_ctx_t *ctx, lis2hh12_xl_trshld_en_t *val); typedef struct @@ -896,26 +896,26 @@ typedef struct uint16_t ig2_zh : 1; uint16_t ig2_ia : 1; } lis2hh12_xl_trshld_src_t; -int32_t lis2hh12_xl_trshld_src_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_trshld_src_get(const stmdev_ctx_t *ctx, lis2hh12_xl_trshld_src_t *val); -int32_t lis2hh12_xl_trshld_set(stmdev_ctx_t *ctx, uint8_t ig1_x, +int32_t lis2hh12_xl_trshld_set(const stmdev_ctx_t *ctx, uint8_t ig1_x, uint8_t ig1_y, uint8_t ig1_z, uint8_t ig2_xyz); -int32_t lis2hh12_xl_trshld_get(stmdev_ctx_t *ctx, uint8_t *ig1_x, +int32_t lis2hh12_xl_trshld_get(const stmdev_ctx_t *ctx, uint8_t *ig1_x, uint8_t *ig1_y, uint8_t *ig1_z, uint8_t *ig2_xyz); -int32_t lis2hh12_xl_trshld_min_sample_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_trshld_min_sample_set(const stmdev_ctx_t *ctx, uint8_t ig1_sam, uint8_t ig2_sam); -int32_t lis2hh12_xl_trshld_min_sample_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_trshld_min_sample_get(const stmdev_ctx_t *ctx, uint8_t *ig1_sam, uint8_t *ig2_sam); -int32_t lis2hh12_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2hh12_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2hh12_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2hh12_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2hh12_act_duration_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2hh12_act_duration_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2hh12_act_duration_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2hh12_act_duration_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -925,13 +925,13 @@ typedef enum LIS2HH12_ENABLE_ON_IG1_4D = 0x11, LIS2HH12_ENABLE_ON_IG2_4D = 0x12, } lis2hh12_6d_mode_t; -int32_t lis2hh12_6d_mode_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_6d_mode_set(const stmdev_ctx_t *ctx, lis2hh12_6d_mode_t val); -int32_t lis2hh12_6d_mode_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_6d_mode_get(const stmdev_ctx_t *ctx, lis2hh12_6d_mode_t *val); -int32_t lis2hh12_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2hh12_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2hh12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2hh12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -943,9 +943,9 @@ typedef enum LIS2HH12_BYPASS_TO_STREAM_MODE = 0x14, LIS2HH12_BYPASS_TO_FIFO_MODE = 0x17, } lis2hh12_fifo_md_t; -int32_t lis2hh12_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_fifo_mode_set(const stmdev_ctx_t *ctx, lis2hh12_fifo_md_t val); -int32_t lis2hh12_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_fifo_mode_get(const stmdev_ctx_t *ctx, lis2hh12_fifo_md_t *val); typedef struct @@ -955,7 +955,7 @@ typedef struct uint8_t ovr : 1; uint8_t fth : 1; } lis2hh12_fifo_stat_t; -int32_t lis2hh12_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_fifo_status_get(const stmdev_ctx_t *ctx, lis2hh12_fifo_stat_t *val); typedef enum @@ -964,9 +964,9 @@ typedef enum LIS2HH12_ST_POSITIVE = 0x01, LIS2HH12_ST_NEGATIVE = 0x02, } lis2hh12_xl_st_t; -int32_t lis2hh12_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_self_test_set(const stmdev_ctx_t *ctx, lis2hh12_xl_st_t val); -int32_t lis2hh12_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lis2hh12_xl_self_test_get(const stmdev_ctx_t *ctx, lis2hh12_xl_st_t *val); /** diff --git a/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.c b/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.c index 6fcd19ef..42cd92e4 100644 --- a/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.c +++ b/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis2mdl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lis2mdl_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lis2mdl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis2mdl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lis2mdl_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -124,7 +134,7 @@ float_t lis2mdl_from_lsb_to_celsius(int16_t lsb) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_mag_user_offset_set(stmdev_ctx_t *ctx, int16_t *val) +int32_t lis2mdl_mag_user_offset_set(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -152,7 +162,7 @@ int32_t lis2mdl_mag_user_offset_set(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_mag_user_offset_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lis2mdl_mag_user_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -176,7 +186,7 @@ int32_t lis2mdl_mag_user_offset_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_operating_mode_set(stmdev_ctx_t *ctx, +int32_t lis2mdl_operating_mode_set(const stmdev_ctx_t *ctx, lis2mdl_md_t val) { lis2mdl_cfg_reg_a_t reg; @@ -201,7 +211,7 @@ int32_t lis2mdl_operating_mode_set(stmdev_ctx_t *ctx, * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_operating_mode_get(stmdev_ctx_t *ctx, +int32_t lis2mdl_operating_mode_get(const stmdev_ctx_t *ctx, lis2mdl_md_t *val) { lis2mdl_cfg_reg_a_t reg; @@ -239,7 +249,7 @@ int32_t lis2mdl_operating_mode_get(stmdev_ctx_t *ctx, * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_data_rate_set(stmdev_ctx_t *ctx, lis2mdl_odr_t val) +int32_t lis2mdl_data_rate_set(const stmdev_ctx_t *ctx, lis2mdl_odr_t val) { lis2mdl_cfg_reg_a_t reg; int32_t ret; @@ -263,7 +273,7 @@ int32_t lis2mdl_data_rate_set(stmdev_ctx_t *ctx, lis2mdl_odr_t val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_data_rate_get(stmdev_ctx_t *ctx, lis2mdl_odr_t *val) +int32_t lis2mdl_data_rate_get(const stmdev_ctx_t *ctx, lis2mdl_odr_t *val) { lis2mdl_cfg_reg_a_t reg; int32_t ret; @@ -304,7 +314,7 @@ int32_t lis2mdl_data_rate_get(stmdev_ctx_t *ctx, lis2mdl_odr_t *val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_power_mode_set(stmdev_ctx_t *ctx, lis2mdl_lp_t val) +int32_t lis2mdl_power_mode_set(const stmdev_ctx_t *ctx, lis2mdl_lp_t val) { lis2mdl_cfg_reg_a_t reg; int32_t ret; @@ -328,7 +338,7 @@ int32_t lis2mdl_power_mode_set(stmdev_ctx_t *ctx, lis2mdl_lp_t val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_power_mode_get(stmdev_ctx_t *ctx, lis2mdl_lp_t *val) +int32_t lis2mdl_power_mode_get(const stmdev_ctx_t *ctx, lis2mdl_lp_t *val) { lis2mdl_cfg_reg_a_t reg; int32_t ret; @@ -361,7 +371,7 @@ int32_t lis2mdl_power_mode_get(stmdev_ctx_t *ctx, lis2mdl_lp_t *val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_offset_temp_comp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2mdl_offset_temp_comp_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2mdl_cfg_reg_a_t reg; int32_t ret; @@ -385,7 +395,7 @@ int32_t lis2mdl_offset_temp_comp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_offset_temp_comp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2mdl_offset_temp_comp_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2mdl_cfg_reg_a_t reg; int32_t ret; @@ -404,7 +414,7 @@ int32_t lis2mdl_offset_temp_comp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_low_pass_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lis2mdl_low_pass_bandwidth_set(const stmdev_ctx_t *ctx, lis2mdl_lpf_t val) { lis2mdl_cfg_reg_b_t reg; @@ -429,7 +439,7 @@ int32_t lis2mdl_low_pass_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_low_pass_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lis2mdl_low_pass_bandwidth_get(const stmdev_ctx_t *ctx, lis2mdl_lpf_t *val) { lis2mdl_cfg_reg_b_t reg; @@ -463,7 +473,7 @@ int32_t lis2mdl_low_pass_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_set_rst_mode_set(stmdev_ctx_t *ctx, +int32_t lis2mdl_set_rst_mode_set(const stmdev_ctx_t *ctx, lis2mdl_set_rst_t val) { lis2mdl_cfg_reg_b_t reg; @@ -488,7 +498,7 @@ int32_t lis2mdl_set_rst_mode_set(stmdev_ctx_t *ctx, * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_set_rst_mode_get(stmdev_ctx_t *ctx, +int32_t lis2mdl_set_rst_mode_get(const stmdev_ctx_t *ctx, lis2mdl_set_rst_t *val) { lis2mdl_cfg_reg_b_t reg; @@ -530,7 +540,7 @@ int32_t lis2mdl_set_rst_mode_get(stmdev_ctx_t *ctx, * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_set_rst_sensor_single_set(stmdev_ctx_t *ctx, +int32_t lis2mdl_set_rst_sensor_single_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2mdl_cfg_reg_b_t reg; @@ -559,7 +569,7 @@ int32_t lis2mdl_set_rst_sensor_single_set(stmdev_ctx_t *ctx, * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_set_rst_sensor_single_get(stmdev_ctx_t *ctx, +int32_t lis2mdl_set_rst_sensor_single_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2mdl_cfg_reg_b_t reg; @@ -579,7 +589,7 @@ int32_t lis2mdl_set_rst_sensor_single_get(stmdev_ctx_t *ctx, * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2mdl_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2mdl_cfg_reg_c_t reg; int32_t ret; @@ -603,7 +613,7 @@ int32_t lis2mdl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2mdl_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2mdl_cfg_reg_c_t reg; int32_t ret; @@ -622,7 +632,7 @@ int32_t lis2mdl_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_mag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2mdl_mag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2mdl_status_reg_t reg; int32_t ret; @@ -641,7 +651,7 @@ int32_t lis2mdl_mag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_mag_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2mdl_mag_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2mdl_status_reg_t reg; int32_t ret; @@ -660,7 +670,7 @@ int32_t lis2mdl_mag_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lis2mdl_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -684,7 +694,7 @@ int32_t lis2mdl_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lis2mdl_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -716,7 +726,7 @@ int32_t lis2mdl_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis2mdl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -733,7 +743,7 @@ int32_t lis2mdl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2mdl_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2mdl_cfg_reg_a_t reg; int32_t ret; @@ -757,7 +767,7 @@ int32_t lis2mdl_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2mdl_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2mdl_cfg_reg_a_t reg; int32_t ret; @@ -776,7 +786,7 @@ int32_t lis2mdl_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2mdl_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2mdl_cfg_reg_a_t reg; int32_t ret; @@ -800,7 +810,7 @@ int32_t lis2mdl_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2mdl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2mdl_cfg_reg_a_t reg; int32_t ret; @@ -819,7 +829,7 @@ int32_t lis2mdl_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_self_test_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2mdl_self_test_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2mdl_cfg_reg_c_t reg; int32_t ret; @@ -843,7 +853,7 @@ int32_t lis2mdl_self_test_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_self_test_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2mdl_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2mdl_cfg_reg_c_t reg; int32_t ret; @@ -862,7 +872,7 @@ int32_t lis2mdl_self_test_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_data_format_set(stmdev_ctx_t *ctx, lis2mdl_ble_t val) +int32_t lis2mdl_data_format_set(const stmdev_ctx_t *ctx, lis2mdl_ble_t val) { lis2mdl_cfg_reg_c_t reg; int32_t ret; @@ -886,7 +896,7 @@ int32_t lis2mdl_data_format_set(stmdev_ctx_t *ctx, lis2mdl_ble_t val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_data_format_get(stmdev_ctx_t *ctx, lis2mdl_ble_t *val) +int32_t lis2mdl_data_format_get(const stmdev_ctx_t *ctx, lis2mdl_ble_t *val) { lis2mdl_cfg_reg_c_t reg; int32_t ret; @@ -919,7 +929,7 @@ int32_t lis2mdl_data_format_get(stmdev_ctx_t *ctx, lis2mdl_ble_t *val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_status_get(stmdev_ctx_t *ctx, +int32_t lis2mdl_status_get(const stmdev_ctx_t *ctx, lis2mdl_status_reg_t *val) { int32_t ret; @@ -950,7 +960,7 @@ int32_t lis2mdl_status_get(stmdev_ctx_t *ctx, * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_offset_int_conf_set(stmdev_ctx_t *ctx, +int32_t lis2mdl_offset_int_conf_set(const stmdev_ctx_t *ctx, lis2mdl_int_on_dataoff_t val) { lis2mdl_cfg_reg_b_t reg; @@ -976,7 +986,7 @@ int32_t lis2mdl_offset_int_conf_set(stmdev_ctx_t *ctx, * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_offset_int_conf_get(stmdev_ctx_t *ctx, +int32_t lis2mdl_offset_int_conf_get(const stmdev_ctx_t *ctx, lis2mdl_int_on_dataoff_t *val) { lis2mdl_cfg_reg_b_t reg; @@ -1010,7 +1020,7 @@ int32_t lis2mdl_offset_int_conf_get(stmdev_ctx_t *ctx, * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_drdy_on_pin_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2mdl_drdy_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2mdl_cfg_reg_c_t reg; int32_t ret; @@ -1034,7 +1044,7 @@ int32_t lis2mdl_drdy_on_pin_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_drdy_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2mdl_drdy_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2mdl_cfg_reg_c_t reg; int32_t ret; @@ -1053,7 +1063,7 @@ int32_t lis2mdl_drdy_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_int_on_pin_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis2mdl_int_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val) { lis2mdl_cfg_reg_c_t reg; int32_t ret; @@ -1077,7 +1087,7 @@ int32_t lis2mdl_int_on_pin_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_int_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis2mdl_int_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis2mdl_cfg_reg_c_t reg; int32_t ret; @@ -1096,7 +1106,7 @@ int32_t lis2mdl_int_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_int_gen_conf_set(stmdev_ctx_t *ctx, +int32_t lis2mdl_int_gen_conf_set(const stmdev_ctx_t *ctx, lis2mdl_int_crtl_reg_t *val) { int32_t ret; @@ -1114,7 +1124,7 @@ int32_t lis2mdl_int_gen_conf_set(stmdev_ctx_t *ctx, * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_int_gen_conf_get(stmdev_ctx_t *ctx, +int32_t lis2mdl_int_gen_conf_get(const stmdev_ctx_t *ctx, lis2mdl_int_crtl_reg_t *val) { int32_t ret; @@ -1132,7 +1142,7 @@ int32_t lis2mdl_int_gen_conf_get(stmdev_ctx_t *ctx, * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_int_gen_source_get(stmdev_ctx_t *ctx, +int32_t lis2mdl_int_gen_source_get(const stmdev_ctx_t *ctx, lis2mdl_int_source_reg_t *val) { int32_t ret; @@ -1152,7 +1162,7 @@ int32_t lis2mdl_int_gen_source_get(stmdev_ctx_t *ctx, * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_int_gen_treshold_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lis2mdl_int_gen_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -1174,7 +1184,7 @@ int32_t lis2mdl_int_gen_treshold_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_int_gen_treshold_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lis2mdl_int_gen_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1207,7 +1217,7 @@ int32_t lis2mdl_int_gen_treshold_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_spi_mode_set(stmdev_ctx_t *ctx, lis2mdl_sim_t val) +int32_t lis2mdl_spi_mode_set(const stmdev_ctx_t *ctx, lis2mdl_sim_t val) { lis2mdl_cfg_reg_c_t reg; int32_t ret; @@ -1231,7 +1241,7 @@ int32_t lis2mdl_spi_mode_set(stmdev_ctx_t *ctx, lis2mdl_sim_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_spi_mode_get(stmdev_ctx_t *ctx, lis2mdl_sim_t *val) +int32_t lis2mdl_spi_mode_get(const stmdev_ctx_t *ctx, lis2mdl_sim_t *val) { lis2mdl_cfg_reg_c_t reg; int32_t ret; @@ -1264,7 +1274,7 @@ int32_t lis2mdl_spi_mode_get(stmdev_ctx_t *ctx, lis2mdl_sim_t *val) * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lis2mdl_i2c_interface_set(const stmdev_ctx_t *ctx, lis2mdl_i2c_dis_t val) { lis2mdl_cfg_reg_c_t reg; @@ -1289,7 +1299,7 @@ int32_t lis2mdl_i2c_interface_set(stmdev_ctx_t *ctx, * @retval interface status.(MANDATORY: return 0 -> no Error) * */ -int32_t lis2mdl_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lis2mdl_i2c_interface_get(const stmdev_ctx_t *ctx, lis2mdl_i2c_dis_t *val) { lis2mdl_cfg_reg_c_t reg; diff --git a/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.h b/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.h index 2d298fae..985a98e4 100644 --- a/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.h +++ b/sensor/stmemsc/lis2mdl_STdC/driver/lis2mdl_reg.h @@ -371,10 +371,10 @@ typedef union * them with a custom implementation. */ -int32_t lis2mdl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lis2mdl_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lis2mdl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lis2mdl_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -382,8 +382,8 @@ float_t lis2mdl_from_lsb_to_mgauss(int16_t lsb); float_t lis2mdl_from_lsb_to_celsius(int16_t lsb); -int32_t lis2mdl_mag_user_offset_set(stmdev_ctx_t *ctx, int16_t *val); -int32_t lis2mdl_mag_user_offset_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lis2mdl_mag_user_offset_set(const stmdev_ctx_t *ctx, int16_t *val); +int32_t lis2mdl_mag_user_offset_get(const stmdev_ctx_t *ctx, int16_t *val); typedef enum { @@ -391,9 +391,9 @@ typedef enum LIS2MDL_SINGLE_TRIGGER = 1, LIS2MDL_POWER_DOWN = 2, } lis2mdl_md_t; -int32_t lis2mdl_operating_mode_set(stmdev_ctx_t *ctx, +int32_t lis2mdl_operating_mode_set(const stmdev_ctx_t *ctx, lis2mdl_md_t val); -int32_t lis2mdl_operating_mode_get(stmdev_ctx_t *ctx, +int32_t lis2mdl_operating_mode_get(const stmdev_ctx_t *ctx, lis2mdl_md_t *val); typedef enum @@ -403,28 +403,28 @@ typedef enum LIS2MDL_ODR_50Hz = 2, LIS2MDL_ODR_100Hz = 3, } lis2mdl_odr_t; -int32_t lis2mdl_data_rate_set(stmdev_ctx_t *ctx, lis2mdl_odr_t val); -int32_t lis2mdl_data_rate_get(stmdev_ctx_t *ctx, lis2mdl_odr_t *val); +int32_t lis2mdl_data_rate_set(const stmdev_ctx_t *ctx, lis2mdl_odr_t val); +int32_t lis2mdl_data_rate_get(const stmdev_ctx_t *ctx, lis2mdl_odr_t *val); typedef enum { LIS2MDL_HIGH_RESOLUTION = 0, LIS2MDL_LOW_POWER = 1, } lis2mdl_lp_t; -int32_t lis2mdl_power_mode_set(stmdev_ctx_t *ctx, lis2mdl_lp_t val); -int32_t lis2mdl_power_mode_get(stmdev_ctx_t *ctx, lis2mdl_lp_t *val); +int32_t lis2mdl_power_mode_set(const stmdev_ctx_t *ctx, lis2mdl_lp_t val); +int32_t lis2mdl_power_mode_get(const stmdev_ctx_t *ctx, lis2mdl_lp_t *val); -int32_t lis2mdl_offset_temp_comp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2mdl_offset_temp_comp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2mdl_offset_temp_comp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2mdl_offset_temp_comp_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LIS2MDL_ODR_DIV_2 = 0, LIS2MDL_ODR_DIV_4 = 1, } lis2mdl_lpf_t; -int32_t lis2mdl_low_pass_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lis2mdl_low_pass_bandwidth_set(const stmdev_ctx_t *ctx, lis2mdl_lpf_t val); -int32_t lis2mdl_low_pass_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lis2mdl_low_pass_bandwidth_get(const stmdev_ctx_t *ctx, lis2mdl_lpf_t *val); typedef enum @@ -433,49 +433,49 @@ typedef enum LIS2MDL_SENS_OFF_CANC_EVERY_ODR = 1, LIS2MDL_SET_SENS_ONLY_AT_POWER_ON = 2, } lis2mdl_set_rst_t; -int32_t lis2mdl_set_rst_mode_set(stmdev_ctx_t *ctx, +int32_t lis2mdl_set_rst_mode_set(const stmdev_ctx_t *ctx, lis2mdl_set_rst_t val); -int32_t lis2mdl_set_rst_mode_get(stmdev_ctx_t *ctx, +int32_t lis2mdl_set_rst_mode_get(const stmdev_ctx_t *ctx, lis2mdl_set_rst_t *val); -int32_t lis2mdl_set_rst_sensor_single_set(stmdev_ctx_t *ctx, +int32_t lis2mdl_set_rst_sensor_single_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2mdl_set_rst_sensor_single_get(stmdev_ctx_t *ctx, +int32_t lis2mdl_set_rst_sensor_single_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2mdl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2mdl_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lis2mdl_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2mdl_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2mdl_mag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2mdl_mag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2mdl_mag_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2mdl_mag_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2mdl_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lis2mdl_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lis2mdl_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lis2mdl_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lis2mdl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis2mdl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis2mdl_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2mdl_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2mdl_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2mdl_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2mdl_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2mdl_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2mdl_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2mdl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2mdl_self_test_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2mdl_self_test_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2mdl_self_test_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2mdl_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LIS2MDL_LSB_AT_LOW_ADD = 0, LIS2MDL_MSB_AT_LOW_ADD = 1, } lis2mdl_ble_t; -int32_t lis2mdl_data_format_set(stmdev_ctx_t *ctx, lis2mdl_ble_t val); -int32_t lis2mdl_data_format_get(stmdev_ctx_t *ctx, +int32_t lis2mdl_data_format_set(const stmdev_ctx_t *ctx, lis2mdl_ble_t val); +int32_t lis2mdl_data_format_get(const stmdev_ctx_t *ctx, lis2mdl_ble_t *val); -int32_t lis2mdl_status_get(stmdev_ctx_t *ctx, +int32_t lis2mdl_status_get(const stmdev_ctx_t *ctx, lis2mdl_status_reg_t *val); typedef enum @@ -483,45 +483,45 @@ typedef enum LIS2MDL_CHECK_BEFORE = 0, LIS2MDL_CHECK_AFTER = 1, } lis2mdl_int_on_dataoff_t; -int32_t lis2mdl_offset_int_conf_set(stmdev_ctx_t *ctx, +int32_t lis2mdl_offset_int_conf_set(const stmdev_ctx_t *ctx, lis2mdl_int_on_dataoff_t val); -int32_t lis2mdl_offset_int_conf_get(stmdev_ctx_t *ctx, +int32_t lis2mdl_offset_int_conf_get(const stmdev_ctx_t *ctx, lis2mdl_int_on_dataoff_t *val); -int32_t lis2mdl_drdy_on_pin_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2mdl_drdy_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2mdl_drdy_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2mdl_drdy_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2mdl_int_on_pin_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis2mdl_int_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis2mdl_int_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis2mdl_int_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis2mdl_int_gen_conf_set(stmdev_ctx_t *ctx, +int32_t lis2mdl_int_gen_conf_set(const stmdev_ctx_t *ctx, lis2mdl_int_crtl_reg_t *val); -int32_t lis2mdl_int_gen_conf_get(stmdev_ctx_t *ctx, +int32_t lis2mdl_int_gen_conf_get(const stmdev_ctx_t *ctx, lis2mdl_int_crtl_reg_t *val); -int32_t lis2mdl_int_gen_source_get(stmdev_ctx_t *ctx, +int32_t lis2mdl_int_gen_source_get(const stmdev_ctx_t *ctx, lis2mdl_int_source_reg_t *val); -int32_t lis2mdl_int_gen_treshold_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lis2mdl_int_gen_treshold_get(stmdev_ctx_t *ctx, - uint16_t *val); +int32_t lis2mdl_int_gen_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lis2mdl_int_gen_threshold_get(const stmdev_ctx_t *ctx, + uint16_t *val); typedef enum { LIS2MDL_SPI_4_WIRE = 1, LIS2MDL_SPI_3_WIRE = 0, } lis2mdl_sim_t; -int32_t lis2mdl_spi_mode_set(stmdev_ctx_t *ctx, lis2mdl_sim_t val); -int32_t lis2mdl_spi_mode_get(stmdev_ctx_t *ctx, lis2mdl_sim_t *val); +int32_t lis2mdl_spi_mode_set(const stmdev_ctx_t *ctx, lis2mdl_sim_t val); +int32_t lis2mdl_spi_mode_get(const stmdev_ctx_t *ctx, lis2mdl_sim_t *val); typedef enum { LIS2MDL_I2C_ENABLE = 0, LIS2MDL_I2C_DISABLE = 1, } lis2mdl_i2c_dis_t; -int32_t lis2mdl_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lis2mdl_i2c_interface_set(const stmdev_ctx_t *ctx, lis2mdl_i2c_dis_t val); -int32_t lis2mdl_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lis2mdl_i2c_interface_get(const stmdev_ctx_t *ctx, lis2mdl_i2c_dis_t *val); /** diff --git a/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.c b/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.c index e0f791cc..1ccc1ee8 100644 --- a/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.c +++ b/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis331dlh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lis331dlh_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lis331dlh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis331dlh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lis331dlh_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -126,7 +136,7 @@ float_t lis331dlh_from_fs8_to_mg(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis331dlh_axis_x_data_set(const stmdev_ctx_t *ctx, uint8_t val) { lis331dlh_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -152,7 +162,7 @@ int32_t lis331dlh_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis331dlh_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis331dlh_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -172,7 +182,7 @@ int32_t lis331dlh_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis331dlh_axis_y_data_set(const stmdev_ctx_t *ctx, uint8_t val) { lis331dlh_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -198,7 +208,7 @@ int32_t lis331dlh_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis331dlh_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis331dlh_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -218,7 +228,7 @@ int32_t lis331dlh_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis331dlh_axis_z_data_set(const stmdev_ctx_t *ctx, uint8_t val) { lis331dlh_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -244,7 +254,7 @@ int32_t lis331dlh_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis331dlh_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis331dlh_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -264,7 +274,7 @@ int32_t lis331dlh_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_data_rate_set(stmdev_ctx_t *ctx, lis331dlh_dr_t val) +int32_t lis331dlh_data_rate_set(const stmdev_ctx_t *ctx, lis331dlh_dr_t val) { lis331dlh_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -291,7 +301,7 @@ int32_t lis331dlh_data_rate_set(stmdev_ctx_t *ctx, lis331dlh_dr_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_data_rate_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_data_rate_get(const stmdev_ctx_t *ctx, lis331dlh_dr_t *val) { lis331dlh_ctrl_reg1_t ctrl_reg1; @@ -358,7 +368,7 @@ int32_t lis331dlh_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_reference_mode_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_reference_mode_set(const stmdev_ctx_t *ctx, lis331dlh_hpm_t val) { lis331dlh_ctrl_reg2_t ctrl_reg2; @@ -385,7 +395,7 @@ int32_t lis331dlh_reference_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_reference_mode_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_reference_mode_get(const stmdev_ctx_t *ctx, lis331dlh_hpm_t *val) { lis331dlh_ctrl_reg2_t ctrl_reg2; @@ -420,7 +430,7 @@ int32_t lis331dlh_reference_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_full_scale_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_full_scale_set(const stmdev_ctx_t *ctx, lis331dlh_fs_t val) { lis331dlh_ctrl_reg4_t ctrl_reg4; @@ -447,7 +457,7 @@ int32_t lis331dlh_full_scale_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_full_scale_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_full_scale_get(const stmdev_ctx_t *ctx, lis331dlh_fs_t *val) { lis331dlh_ctrl_reg4_t ctrl_reg4; @@ -486,7 +496,7 @@ int32_t lis331dlh_full_scale_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_block_data_update_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lis331dlh_ctrl_reg4_t ctrl_reg4; @@ -513,7 +523,7 @@ int32_t lis331dlh_block_data_update_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis331dlh_ctrl_reg4_t ctrl_reg4; @@ -534,7 +544,7 @@ int32_t lis331dlh_block_data_update_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_status_reg_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_status_reg_get(const stmdev_ctx_t *ctx, lis331dlh_status_reg_t *val) { int32_t ret; @@ -552,7 +562,7 @@ int32_t lis331dlh_status_reg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis331dlh_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis331dlh_status_reg_t status_reg; int32_t ret; @@ -585,7 +595,7 @@ int32_t lis331dlh_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -622,7 +632,7 @@ int32_t lis331dlh_acceleration_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis331dlh_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -639,7 +649,7 @@ int32_t lis331dlh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis331dlh_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lis331dlh_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -665,7 +675,7 @@ int32_t lis331dlh_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis331dlh_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis331dlh_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -685,7 +695,7 @@ int32_t lis331dlh_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_self_test_set(stmdev_ctx_t *ctx, lis331dlh_st_t val) +int32_t lis331dlh_self_test_set(const stmdev_ctx_t *ctx, lis331dlh_st_t val) { lis331dlh_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -711,7 +721,7 @@ int32_t lis331dlh_self_test_set(stmdev_ctx_t *ctx, lis331dlh_st_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_self_test_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_self_test_get(const stmdev_ctx_t *ctx, lis331dlh_st_t *val) { lis331dlh_ctrl_reg4_t ctrl_reg4; @@ -750,7 +760,7 @@ int32_t lis331dlh_self_test_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_data_format_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_data_format_set(const stmdev_ctx_t *ctx, lis331dlh_ble_t val) { lis331dlh_ctrl_reg4_t ctrl_reg4; @@ -777,7 +787,7 @@ int32_t lis331dlh_data_format_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_data_format_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_data_format_get(const stmdev_ctx_t *ctx, lis331dlh_ble_t *val) { lis331dlh_ctrl_reg4_t ctrl_reg4; @@ -825,7 +835,7 @@ int32_t lis331dlh_data_format_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_hp_bandwidth_set(const stmdev_ctx_t *ctx, lis331dlh_hpcf_t val) { lis331dlh_ctrl_reg2_t ctrl_reg2; @@ -852,7 +862,7 @@ int32_t lis331dlh_hp_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_hp_bandwidth_get(const stmdev_ctx_t *ctx, lis331dlh_hpcf_t *val) { lis331dlh_ctrl_reg2_t ctrl_reg2; @@ -895,7 +905,7 @@ int32_t lis331dlh_hp_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_hp_path_set(stmdev_ctx_t *ctx, lis331dlh_hpen_t val) +int32_t lis331dlh_hp_path_set(const stmdev_ctx_t *ctx, lis331dlh_hpen_t val) { lis331dlh_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -922,7 +932,7 @@ int32_t lis331dlh_hp_path_set(stmdev_ctx_t *ctx, lis331dlh_hpen_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_hp_path_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_hp_path_get(const stmdev_ctx_t *ctx, lis331dlh_hpen_t *val) { lis331dlh_ctrl_reg2_t ctrl_reg2; @@ -985,7 +995,7 @@ int32_t lis331dlh_hp_path_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_hp_reset_get(stmdev_ctx_t *ctx) +int32_t lis331dlh_hp_reset_get(const stmdev_ctx_t *ctx) { uint8_t dummy; int32_t ret; @@ -1004,7 +1014,7 @@ int32_t lis331dlh_hp_reset_get(stmdev_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_hp_reference_value_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_hp_reference_value_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; @@ -1022,7 +1032,7 @@ int32_t lis331dlh_hp_reference_value_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_hp_reference_value_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_hp_reference_value_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -1053,7 +1063,7 @@ int32_t lis331dlh_hp_reference_value_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_spi_mode_set(stmdev_ctx_t *ctx, lis331dlh_sim_t val) +int32_t lis331dlh_spi_mode_set(const stmdev_ctx_t *ctx, lis331dlh_sim_t val) { lis331dlh_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -1079,7 +1089,7 @@ int32_t lis331dlh_spi_mode_set(stmdev_ctx_t *ctx, lis331dlh_sim_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_spi_mode_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_spi_mode_get(const stmdev_ctx_t *ctx, lis331dlh_sim_t *val) { lis331dlh_ctrl_reg4_t ctrl_reg4; @@ -1127,7 +1137,7 @@ int32_t lis331dlh_spi_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_pin_int1_route_set(const stmdev_ctx_t *ctx, lis331dlh_i1_cfg_t val) { lis331dlh_ctrl_reg3_t ctrl_reg3; @@ -1154,7 +1164,7 @@ int32_t lis331dlh_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_pin_int1_route_get(const stmdev_ctx_t *ctx, lis331dlh_i1_cfg_t *val) { lis331dlh_ctrl_reg3_t ctrl_reg3; @@ -1198,7 +1208,7 @@ int32_t lis331dlh_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int1_notification_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_int1_notification_set(const stmdev_ctx_t *ctx, lis331dlh_lir1_t val) { lis331dlh_ctrl_reg3_t ctrl_reg3; @@ -1226,7 +1236,7 @@ int32_t lis331dlh_int1_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int1_notification_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_int1_notification_get(const stmdev_ctx_t *ctx, lis331dlh_lir1_t *val) { lis331dlh_ctrl_reg3_t ctrl_reg3; @@ -1261,7 +1271,7 @@ int32_t lis331dlh_int1_notification_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_pin_int2_route_set(const stmdev_ctx_t *ctx, lis331dlh_i2_cfg_t val) { lis331dlh_ctrl_reg3_t ctrl_reg3; @@ -1288,7 +1298,7 @@ int32_t lis331dlh_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_pin_int2_route_get(const stmdev_ctx_t *ctx, lis331dlh_i2_cfg_t *val) { lis331dlh_ctrl_reg3_t ctrl_reg3; @@ -1332,7 +1342,7 @@ int32_t lis331dlh_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int2_notification_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_int2_notification_set(const stmdev_ctx_t *ctx, lis331dlh_lir2_t val) { lis331dlh_ctrl_reg3_t ctrl_reg3; @@ -1360,7 +1370,7 @@ int32_t lis331dlh_int2_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int2_notification_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_int2_notification_get(const stmdev_ctx_t *ctx, lis331dlh_lir2_t *val) { lis331dlh_ctrl_reg3_t ctrl_reg3; @@ -1395,7 +1405,7 @@ int32_t lis331dlh_int2_notification_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_pin_mode_set(const stmdev_ctx_t *ctx, lis331dlh_pp_od_t val) { lis331dlh_ctrl_reg3_t ctrl_reg3; @@ -1422,7 +1432,7 @@ int32_t lis331dlh_pin_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_pin_mode_get(const stmdev_ctx_t *ctx, lis331dlh_pp_od_t *val) { lis331dlh_ctrl_reg3_t ctrl_reg3; @@ -1457,7 +1467,7 @@ int32_t lis331dlh_pin_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_pin_polarity_set(const stmdev_ctx_t *ctx, lis331dlh_ihl_t val) { lis331dlh_ctrl_reg3_t ctrl_reg3; @@ -1484,7 +1494,7 @@ int32_t lis331dlh_pin_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_pin_polarity_get(const stmdev_ctx_t *ctx, lis331dlh_ihl_t *val) { lis331dlh_ctrl_reg3_t ctrl_reg3; @@ -1532,7 +1542,7 @@ int32_t lis331dlh_pin_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int1_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_int1_on_threshold_conf_set(const stmdev_ctx_t *ctx, int1_on_th_conf_t val) { lis331dlh_int1_cfg_t int1_cfg; @@ -1564,7 +1574,7 @@ int32_t lis331dlh_int1_on_threshold_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int1_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_int1_on_threshold_conf_get(const stmdev_ctx_t *ctx, int1_on_th_conf_t *val) { lis331dlh_int1_cfg_t int1_cfg; @@ -1590,7 +1600,7 @@ int32_t lis331dlh_int1_on_threshold_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int1_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_int1_on_threshold_mode_set(const stmdev_ctx_t *ctx, lis331dlh_int1_aoi_t val) { lis331dlh_int1_cfg_t int1_cfg; @@ -1617,7 +1627,7 @@ int32_t lis331dlh_int1_on_threshold_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int1_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_int1_on_threshold_mode_get(const stmdev_ctx_t *ctx, lis331dlh_int1_aoi_t *val) { lis331dlh_int1_cfg_t int1_cfg; @@ -1652,7 +1662,7 @@ int32_t lis331dlh_int1_on_threshold_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int1_src_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_int1_src_get(const stmdev_ctx_t *ctx, lis331dlh_int1_src_t *val) { int32_t ret; @@ -1670,7 +1680,7 @@ int32_t lis331dlh_int1_src_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis331dlh_int1_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis331dlh_int1_ths_t int1_ths; int32_t ret; @@ -1696,7 +1706,7 @@ int32_t lis331dlh_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis331dlh_int1_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis331dlh_int1_ths_t int1_ths; int32_t ret; @@ -1716,7 +1726,7 @@ int32_t lis331dlh_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis331dlh_int1_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lis331dlh_int1_duration_t int1_duration; int32_t ret; @@ -1742,7 +1752,7 @@ int32_t lis331dlh_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis331dlh_int1_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis331dlh_int1_duration_t int1_duration; int32_t ret; @@ -1762,7 +1772,7 @@ int32_t lis331dlh_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int2_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_int2_on_threshold_conf_set(const stmdev_ctx_t *ctx, int2_on_th_conf_t val) { lis331dlh_int2_cfg_t int2_cfg; @@ -1794,7 +1804,7 @@ int32_t lis331dlh_int2_on_threshold_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int2_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_int2_on_threshold_conf_get(const stmdev_ctx_t *ctx, int2_on_th_conf_t *val) { lis331dlh_int2_cfg_t int2_cfg; @@ -1820,7 +1830,7 @@ int32_t lis331dlh_int2_on_threshold_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int2_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_int2_on_threshold_mode_set(const stmdev_ctx_t *ctx, lis331dlh_int2_aoi_t val) { lis331dlh_int2_cfg_t int2_cfg; @@ -1847,7 +1857,7 @@ int32_t lis331dlh_int2_on_threshold_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int2_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_int2_on_threshold_mode_get(const stmdev_ctx_t *ctx, lis331dlh_int2_aoi_t *val) { lis331dlh_int2_cfg_t int2_cfg; @@ -1882,7 +1892,7 @@ int32_t lis331dlh_int2_on_threshold_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int2_src_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_int2_src_get(const stmdev_ctx_t *ctx, lis331dlh_int2_src_t *val) { int32_t ret; @@ -1900,7 +1910,7 @@ int32_t lis331dlh_int2_src_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis331dlh_int2_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis331dlh_int2_ths_t int2_ths; int32_t ret; @@ -1926,7 +1936,7 @@ int32_t lis331dlh_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis331dlh_int2_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis331dlh_int2_ths_t int2_ths; int32_t ret; @@ -1946,7 +1956,7 @@ int32_t lis331dlh_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis331dlh_int2_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lis331dlh_int2_duration_t int2_duration; int32_t ret; @@ -1972,7 +1982,7 @@ int32_t lis331dlh_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis331dlh_int2_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis331dlh_int2_duration_t int2_duration; int32_t ret; @@ -2005,7 +2015,7 @@ int32_t lis331dlh_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis331dlh_wkup_to_sleep_set(const stmdev_ctx_t *ctx, uint8_t val) { lis331dlh_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -2031,7 +2041,7 @@ int32_t lis331dlh_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis331dlh_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis331dlh_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -2064,7 +2074,7 @@ int32_t lis331dlh_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int1_6d_mode_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_int1_6d_mode_set(const stmdev_ctx_t *ctx, lis331dlh_int1_6d_t val) { lis331dlh_int1_cfg_t int1_cfg; @@ -2092,7 +2102,7 @@ int32_t lis331dlh_int1_6d_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int1_6d_mode_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_int1_6d_mode_get(const stmdev_ctx_t *ctx, lis331dlh_int1_6d_t *val) { lis331dlh_int1_cfg_t int1_cfg; @@ -2131,7 +2141,7 @@ int32_t lis331dlh_int1_6d_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int1_6d_src_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_int1_6d_src_get(const stmdev_ctx_t *ctx, lis331dlh_int1_src_t *val) { int32_t ret; @@ -2149,7 +2159,7 @@ int32_t lis331dlh_int1_6d_src_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int1_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis331dlh_int1_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis331dlh_int1_ths_t int1_ths; int32_t ret; @@ -2175,8 +2185,8 @@ int32_t lis331dlh_int1_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int1_6d_treshold_get(stmdev_ctx_t *ctx, - uint8_t *val) +int32_t lis331dlh_int1_6d_threshold_get(const stmdev_ctx_t *ctx, + uint8_t *val) { lis331dlh_int1_ths_t int1_ths; int32_t ret; @@ -2196,7 +2206,7 @@ int32_t lis331dlh_int1_6d_treshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int2_6d_mode_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_int2_6d_mode_set(const stmdev_ctx_t *ctx, lis331dlh_int2_6d_t val) { lis331dlh_int2_cfg_t int2_cfg; @@ -2224,7 +2234,7 @@ int32_t lis331dlh_int2_6d_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int2_6d_mode_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_int2_6d_mode_get(const stmdev_ctx_t *ctx, lis331dlh_int2_6d_t *val) { lis331dlh_int2_cfg_t int2_cfg; @@ -2263,7 +2273,7 @@ int32_t lis331dlh_int2_6d_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int2_6d_src_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_int2_6d_src_get(const stmdev_ctx_t *ctx, lis331dlh_int2_src_t *val) { int32_t ret; @@ -2281,7 +2291,7 @@ int32_t lis331dlh_int2_6d_src_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int2_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis331dlh_int2_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis331dlh_int2_ths_t int2_ths; int32_t ret; @@ -2307,8 +2317,8 @@ int32_t lis331dlh_int2_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis331dlh_int2_6d_treshold_get(stmdev_ctx_t *ctx, - uint8_t *val) +int32_t lis331dlh_int2_6d_threshold_get(const stmdev_ctx_t *ctx, + uint8_t *val) { lis331dlh_int2_ths_t int2_ths; int32_t ret; diff --git a/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.h b/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.h index ed1fab2d..963ebb34 100644 --- a/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.h +++ b/sensor/stmemsc/lis331dlh_STdC/driver/lis331dlh_reg.h @@ -497,10 +497,10 @@ typedef union * them with a custom implementation. */ -int32_t lis331dlh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lis331dlh_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lis331dlh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lis331dlh_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -508,14 +508,14 @@ float_t lis331dlh_from_fs2_to_mg(int16_t lsb); float_t lis331dlh_from_fs4_to_mg(int16_t lsb); float_t lis331dlh_from_fs8_to_mg(int16_t lsb); -int32_t lis331dlh_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis331dlh_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis331dlh_axis_x_data_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis331dlh_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis331dlh_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis331dlh_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis331dlh_axis_y_data_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis331dlh_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis331dlh_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis331dlh_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis331dlh_axis_z_data_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis331dlh_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -530,9 +530,9 @@ typedef enum LIS331DLH_ODR_400Hz = 0x21, LIS331DLH_ODR_1kHz = 0x31, } lis331dlh_dr_t; -int32_t lis331dlh_data_rate_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_data_rate_set(const stmdev_ctx_t *ctx, lis331dlh_dr_t val); -int32_t lis331dlh_data_rate_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_data_rate_get(const stmdev_ctx_t *ctx, lis331dlh_dr_t *val); typedef enum @@ -540,9 +540,9 @@ typedef enum LIS331DLH_NORMAL_MODE = 0, LIS331DLH_REF_MODE_ENABLE = 1, } lis331dlh_hpm_t; -int32_t lis331dlh_reference_mode_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_reference_mode_set(const stmdev_ctx_t *ctx, lis331dlh_hpm_t val); -int32_t lis331dlh_reference_mode_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_reference_mode_get(const stmdev_ctx_t *ctx, lis331dlh_hpm_t *val); typedef enum @@ -551,29 +551,29 @@ typedef enum LIS331DLH_4g = 1, LIS331DLH_8g = 3, } lis331dlh_fs_t; -int32_t lis331dlh_full_scale_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_full_scale_set(const stmdev_ctx_t *ctx, lis331dlh_fs_t val); -int32_t lis331dlh_full_scale_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_full_scale_get(const stmdev_ctx_t *ctx, lis331dlh_fs_t *val); -int32_t lis331dlh_block_data_update_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis331dlh_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis331dlh_status_reg_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_status_reg_get(const stmdev_ctx_t *ctx, lis331dlh_status_reg_t *val); -int32_t lis331dlh_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis331dlh_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lis331dlh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis331dlh_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis331dlh_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis331dlh_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis331dlh_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis331dlh_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -581,9 +581,9 @@ typedef enum LIS331DLH_ST_POSITIVE = 1, LIS331DLH_ST_NEGATIVE = 5, } lis331dlh_st_t; -int32_t lis331dlh_self_test_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_self_test_set(const stmdev_ctx_t *ctx, lis331dlh_st_t val); -int32_t lis331dlh_self_test_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_self_test_get(const stmdev_ctx_t *ctx, lis331dlh_st_t *val); typedef enum @@ -591,9 +591,9 @@ typedef enum LIS331DLH_LSB_AT_LOW_ADD = 0, LIS331DLH_MSB_AT_LOW_ADD = 1, } lis331dlh_ble_t; -int32_t lis331dlh_data_format_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_data_format_set(const stmdev_ctx_t *ctx, lis331dlh_ble_t val); -int32_t lis331dlh_data_format_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_data_format_get(const stmdev_ctx_t *ctx, lis331dlh_ble_t *val); typedef enum @@ -603,9 +603,9 @@ typedef enum LIS331DLH_CUT_OFF_32Hz = 2, LIS331DLH_CUT_OFF_64Hz = 3, } lis331dlh_hpcf_t; -int32_t lis331dlh_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_hp_bandwidth_set(const stmdev_ctx_t *ctx, lis331dlh_hpcf_t val); -int32_t lis331dlh_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_hp_bandwidth_get(const stmdev_ctx_t *ctx, lis331dlh_hpcf_t *val); typedef enum @@ -619,16 +619,16 @@ typedef enum LIS331DLH_HP_ON_INT2_OUT = 6, LIS331DLH_HP_ON_INT1_OUT = 5, } lis331dlh_hpen_t; -int32_t lis331dlh_hp_path_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_hp_path_set(const stmdev_ctx_t *ctx, lis331dlh_hpen_t val); -int32_t lis331dlh_hp_path_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_hp_path_get(const stmdev_ctx_t *ctx, lis331dlh_hpen_t *val); -int32_t lis331dlh_hp_reset_get(stmdev_ctx_t *ctx); +int32_t lis331dlh_hp_reset_get(const stmdev_ctx_t *ctx); -int32_t lis331dlh_hp_reference_value_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_hp_reference_value_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis331dlh_hp_reference_value_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_hp_reference_value_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -636,9 +636,9 @@ typedef enum LIS331DLH_SPI_4_WIRE = 0, LIS331DLH_SPI_3_WIRE = 1, } lis331dlh_sim_t; -int32_t lis331dlh_spi_mode_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_spi_mode_set(const stmdev_ctx_t *ctx, lis331dlh_sim_t val); -int32_t lis331dlh_spi_mode_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_spi_mode_get(const stmdev_ctx_t *ctx, lis331dlh_sim_t *val); typedef enum @@ -648,9 +648,9 @@ typedef enum LIS331DLH_PAD1_DRDY = 2, LIS331DLH_PAD1_BOOT = 3, } lis331dlh_i1_cfg_t; -int32_t lis331dlh_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_pin_int1_route_set(const stmdev_ctx_t *ctx, lis331dlh_i1_cfg_t val); -int32_t lis331dlh_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_pin_int1_route_get(const stmdev_ctx_t *ctx, lis331dlh_i1_cfg_t *val); typedef enum @@ -658,9 +658,9 @@ typedef enum LIS331DLH_INT1_PULSED = 0, LIS331DLH_INT1_LATCHED = 1, } lis331dlh_lir1_t; -int32_t lis331dlh_int1_notification_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_int1_notification_set(const stmdev_ctx_t *ctx, lis331dlh_lir1_t val); -int32_t lis331dlh_int1_notification_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_int1_notification_get(const stmdev_ctx_t *ctx, lis331dlh_lir1_t *val); typedef enum @@ -670,9 +670,9 @@ typedef enum LIS331DLH_PAD2_DRDY = 2, LIS331DLH_PAD2_BOOT = 3, } lis331dlh_i2_cfg_t; -int32_t lis331dlh_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_pin_int2_route_set(const stmdev_ctx_t *ctx, lis331dlh_i2_cfg_t val); -int32_t lis331dlh_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_pin_int2_route_get(const stmdev_ctx_t *ctx, lis331dlh_i2_cfg_t *val); typedef enum @@ -680,9 +680,9 @@ typedef enum LIS331DLH_INT2_PULSED = 0, LIS331DLH_INT2_LATCHED = 1, } lis331dlh_lir2_t; -int32_t lis331dlh_int2_notification_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_int2_notification_set(const stmdev_ctx_t *ctx, lis331dlh_lir2_t val); -int32_t lis331dlh_int2_notification_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_int2_notification_get(const stmdev_ctx_t *ctx, lis331dlh_lir2_t *val); typedef enum @@ -690,9 +690,9 @@ typedef enum LIS331DLH_PUSH_PULL = 0, LIS331DLH_OPEN_DRAIN = 1, } lis331dlh_pp_od_t; -int32_t lis331dlh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_pin_mode_set(const stmdev_ctx_t *ctx, lis331dlh_pp_od_t val); -int32_t lis331dlh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_pin_mode_get(const stmdev_ctx_t *ctx, lis331dlh_pp_od_t *val); typedef enum @@ -700,9 +700,9 @@ typedef enum LIS331DLH_ACTIVE_HIGH = 0, LIS331DLH_ACTIVE_LOW = 1, } lis331dlh_ihl_t; -int32_t lis331dlh_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_pin_polarity_set(const stmdev_ctx_t *ctx, lis331dlh_ihl_t val); -int32_t lis331dlh_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_pin_polarity_get(const stmdev_ctx_t *ctx, lis331dlh_ihl_t *val); typedef struct @@ -714,9 +714,9 @@ typedef struct uint8_t int1_zlie : 1; uint8_t int1_zhie : 1; } int1_on_th_conf_t; -int32_t lis331dlh_int1_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_int1_on_threshold_conf_set(const stmdev_ctx_t *ctx, int1_on_th_conf_t val); -int32_t lis331dlh_int1_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_int1_on_threshold_conf_get(const stmdev_ctx_t *ctx, int1_on_th_conf_t *val); typedef enum @@ -724,19 +724,19 @@ typedef enum LIS331DLH_INT1_ON_THRESHOLD_OR = 0, LIS331DLH_INT1_ON_THRESHOLD_AND = 1, } lis331dlh_int1_aoi_t; -int32_t lis331dlh_int1_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_int1_on_threshold_mode_set(const stmdev_ctx_t *ctx, lis331dlh_int1_aoi_t val); -int32_t lis331dlh_int1_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_int1_on_threshold_mode_get(const stmdev_ctx_t *ctx, lis331dlh_int1_aoi_t *val); -int32_t lis331dlh_int1_src_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_int1_src_get(const stmdev_ctx_t *ctx, lis331dlh_int1_src_t *val); -int32_t lis331dlh_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis331dlh_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis331dlh_int1_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis331dlh_int1_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis331dlh_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis331dlh_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis331dlh_int1_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis331dlh_int1_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -747,9 +747,9 @@ typedef struct uint8_t int2_zlie : 1; uint8_t int2_zhie : 1; } int2_on_th_conf_t; -int32_t lis331dlh_int2_on_threshold_conf_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_int2_on_threshold_conf_set(const stmdev_ctx_t *ctx, int2_on_th_conf_t val); -int32_t lis331dlh_int2_on_threshold_conf_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_int2_on_threshold_conf_get(const stmdev_ctx_t *ctx, int2_on_th_conf_t *val); typedef enum @@ -757,22 +757,22 @@ typedef enum LIS331DLH_INT2_ON_THRESHOLD_OR = 0, LIS331DLH_INT2_ON_THRESHOLD_AND = 1, } lis331dlh_int2_aoi_t; -int32_t lis331dlh_int2_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_int2_on_threshold_mode_set(const stmdev_ctx_t *ctx, lis331dlh_int2_aoi_t val); -int32_t lis331dlh_int2_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_int2_on_threshold_mode_get(const stmdev_ctx_t *ctx, lis331dlh_int2_aoi_t *val); -int32_t lis331dlh_int2_src_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_int2_src_get(const stmdev_ctx_t *ctx, lis331dlh_int2_src_t *val); -int32_t lis331dlh_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis331dlh_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis331dlh_int2_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis331dlh_int2_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis331dlh_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis331dlh_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis331dlh_int2_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis331dlh_int2_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis331dlh_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis331dlh_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis331dlh_wkup_to_sleep_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis331dlh_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -780,18 +780,18 @@ typedef enum LIS331DLH_6D_INT1_MOVEMENT = 1, LIS331DLH_6D_INT1_POSITION = 3, } lis331dlh_int1_6d_t; -int32_t lis331dlh_int1_6d_mode_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_int1_6d_mode_set(const stmdev_ctx_t *ctx, lis331dlh_int1_6d_t val); -int32_t lis331dlh_int1_6d_mode_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_int1_6d_mode_get(const stmdev_ctx_t *ctx, lis331dlh_int1_6d_t *val); -int32_t lis331dlh_int1_6d_src_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_int1_6d_src_get(const stmdev_ctx_t *ctx, lis331dlh_int1_src_t *val); -int32_t lis331dlh_int1_6d_treshold_set(stmdev_ctx_t *ctx, - uint8_t val); -int32_t lis331dlh_int1_6d_treshold_get(stmdev_ctx_t *ctx, - uint8_t *val); +int32_t lis331dlh_int1_6d_threshold_set(const stmdev_ctx_t *ctx, + uint8_t val); +int32_t lis331dlh_int1_6d_threshold_get(const stmdev_ctx_t *ctx, + uint8_t *val); typedef enum { @@ -799,18 +799,18 @@ typedef enum LIS331DLH_6D_INT2_MOVEMENT = 1, LIS331DLH_6D_INT2_POSITION = 3, } lis331dlh_int2_6d_t; -int32_t lis331dlh_int2_6d_mode_set(stmdev_ctx_t *ctx, +int32_t lis331dlh_int2_6d_mode_set(const stmdev_ctx_t *ctx, lis331dlh_int2_6d_t val); -int32_t lis331dlh_int2_6d_mode_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_int2_6d_mode_get(const stmdev_ctx_t *ctx, lis331dlh_int2_6d_t *val); -int32_t lis331dlh_int2_6d_src_get(stmdev_ctx_t *ctx, +int32_t lis331dlh_int2_6d_src_get(const stmdev_ctx_t *ctx, lis331dlh_int2_src_t *val); -int32_t lis331dlh_int2_6d_treshold_set(stmdev_ctx_t *ctx, - uint8_t val); -int32_t lis331dlh_int2_6d_treshold_get(stmdev_ctx_t *ctx, - uint8_t *val); +int32_t lis331dlh_int2_6d_threshold_set(const stmdev_ctx_t *ctx, + uint8_t val); +int32_t lis331dlh_int2_6d_threshold_get(const stmdev_ctx_t *ctx, + uint8_t *val); /** *@} diff --git a/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.c b/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.c index cce50368..3183fb4a 100644 --- a/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.c +++ b/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.c @@ -46,11 +46,16 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis3de_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, +int32_t __weak lis3de_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -66,12 +71,17 @@ int32_t __weak lis3de_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis3de_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lis3de_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -134,7 +144,7 @@ float_t lis3de_from_lsb_to_celsius(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis3de_temp_status_reg_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -150,7 +160,7 @@ int32_t lis3de_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3de_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3de_status_reg_aux_t status_reg_aux; int32_t ret; @@ -169,7 +179,7 @@ int32_t lis3de_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3de_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3de_status_reg_aux_t status_reg_aux; int32_t ret; @@ -188,7 +198,7 @@ int32_t lis3de_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis3de_temperature_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -217,7 +227,7 @@ int32_t lis3de_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_adc_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lis3de_adc_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -241,7 +251,7 @@ int32_t lis3de_adc_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_aux_adc_set(stmdev_ctx_t *ctx, lis3de_temp_en_t val) +int32_t lis3de_aux_adc_set(const stmdev_ctx_t *ctx, lis3de_temp_en_t val) { lis3de_temp_cfg_reg_t temp_cfg_reg; int32_t ret; @@ -277,7 +287,7 @@ int32_t lis3de_aux_adc_set(stmdev_ctx_t *ctx, lis3de_temp_en_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_aux_adc_get(stmdev_ctx_t *ctx, lis3de_temp_en_t *val) +int32_t lis3de_aux_adc_get(const stmdev_ctx_t *ctx, lis3de_temp_en_t *val) { lis3de_temp_cfg_reg_t temp_cfg_reg; int32_t ret; @@ -313,7 +323,7 @@ int32_t lis3de_aux_adc_get(stmdev_ctx_t *ctx, lis3de_temp_en_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_operating_mode_set(stmdev_ctx_t *ctx, +int32_t lis3de_operating_mode_set(const stmdev_ctx_t *ctx, lis3de_op_md_t val) { lis3de_ctrl_reg1_t ctrl_reg1; @@ -338,7 +348,7 @@ int32_t lis3de_operating_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_operating_mode_get(stmdev_ctx_t *ctx, +int32_t lis3de_operating_mode_get(const stmdev_ctx_t *ctx, lis3de_op_md_t *val) { lis3de_ctrl_reg1_t ctrl_reg1; @@ -370,7 +380,7 @@ int32_t lis3de_operating_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_data_rate_set(stmdev_ctx_t *ctx, lis3de_odr_t val) +int32_t lis3de_data_rate_set(const stmdev_ctx_t *ctx, lis3de_odr_t val) { lis3de_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -394,7 +404,7 @@ int32_t lis3de_data_rate_set(stmdev_ctx_t *ctx, lis3de_odr_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_data_rate_get(stmdev_ctx_t *ctx, lis3de_odr_t *val) +int32_t lis3de_data_rate_get(const stmdev_ctx_t *ctx, lis3de_odr_t *val) { lis3de_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -460,7 +470,7 @@ int32_t lis3de_data_rate_get(stmdev_ctx_t *ctx, lis3de_odr_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_high_pass_on_outputs_set(stmdev_ctx_t *ctx, +int32_t lis3de_high_pass_on_outputs_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3de_ctrl_reg2_t ctrl_reg2; @@ -486,7 +496,7 @@ int32_t lis3de_high_pass_on_outputs_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_high_pass_on_outputs_get(stmdev_ctx_t *ctx, +int32_t lis3de_high_pass_on_outputs_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3de_ctrl_reg2_t ctrl_reg2; @@ -512,7 +522,7 @@ int32_t lis3de_high_pass_on_outputs_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_high_pass_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lis3de_high_pass_bandwidth_set(const stmdev_ctx_t *ctx, lis3de_hpcf_t val) { lis3de_ctrl_reg2_t ctrl_reg2; @@ -543,7 +553,7 @@ int32_t lis3de_high_pass_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_high_pass_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lis3de_high_pass_bandwidth_get(const stmdev_ctx_t *ctx, lis3de_hpcf_t *val) { lis3de_ctrl_reg2_t ctrl_reg2; @@ -585,7 +595,7 @@ int32_t lis3de_high_pass_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_high_pass_mode_set(stmdev_ctx_t *ctx, lis3de_hpm_t val) +int32_t lis3de_high_pass_mode_set(const stmdev_ctx_t *ctx, lis3de_hpm_t val) { lis3de_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -609,7 +619,7 @@ int32_t lis3de_high_pass_mode_set(stmdev_ctx_t *ctx, lis3de_hpm_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_high_pass_mode_get(stmdev_ctx_t *ctx, +int32_t lis3de_high_pass_mode_get(const stmdev_ctx_t *ctx, lis3de_hpm_t *val) { lis3de_ctrl_reg2_t ctrl_reg2; @@ -651,7 +661,7 @@ int32_t lis3de_high_pass_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_full_scale_set(stmdev_ctx_t *ctx, lis3de_fs_t val) +int32_t lis3de_full_scale_set(const stmdev_ctx_t *ctx, lis3de_fs_t val) { lis3de_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -675,7 +685,7 @@ int32_t lis3de_full_scale_set(stmdev_ctx_t *ctx, lis3de_fs_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_full_scale_get(stmdev_ctx_t *ctx, lis3de_fs_t *val) +int32_t lis3de_full_scale_get(const stmdev_ctx_t *ctx, lis3de_fs_t *val) { lis3de_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -716,7 +726,7 @@ int32_t lis3de_full_scale_get(stmdev_ctx_t *ctx, lis3de_fs_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3de_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3de_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -740,7 +750,7 @@ int32_t lis3de_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3de_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3de_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -760,7 +770,7 @@ int32_t lis3de_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis3de_filter_reference_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -778,7 +788,7 @@ int32_t lis3de_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_filter_reference_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis3de_filter_reference_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -794,7 +804,7 @@ int32_t lis3de_filter_reference_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3de_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3de_status_reg_t status_reg; int32_t ret; @@ -812,7 +822,7 @@ int32_t lis3de_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3de_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3de_status_reg_t status_reg; int32_t ret; @@ -830,7 +840,7 @@ int32_t lis3de_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *buff) +int32_t lis3de_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) { int32_t ret; @@ -873,7 +883,7 @@ int32_t lis3de_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis3de_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -889,7 +899,7 @@ int32_t lis3de_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_self_test_set(stmdev_ctx_t *ctx, lis3de_st_t val) +int32_t lis3de_self_test_set(const stmdev_ctx_t *ctx, lis3de_st_t val) { lis3de_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -913,7 +923,7 @@ int32_t lis3de_self_test_set(stmdev_ctx_t *ctx, lis3de_st_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_self_test_get(stmdev_ctx_t *ctx, lis3de_st_t *val) +int32_t lis3de_self_test_get(const stmdev_ctx_t *ctx, lis3de_st_t *val) { lis3de_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -950,7 +960,7 @@ int32_t lis3de_self_test_get(stmdev_ctx_t *ctx, lis3de_st_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3de_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3de_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -974,7 +984,7 @@ int32_t lis3de_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3de_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3de_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -993,7 +1003,7 @@ int32_t lis3de_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_status_get(stmdev_ctx_t *ctx, lis3de_status_reg_t *val) +int32_t lis3de_status_get(const stmdev_ctx_t *ctx, lis3de_status_reg_t *val) { int32_t ret; @@ -1022,7 +1032,7 @@ int32_t lis3de_status_get(stmdev_ctx_t *ctx, lis3de_status_reg_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_int1_gen_conf_set(stmdev_ctx_t *ctx, +int32_t lis3de_int1_gen_conf_set(const stmdev_ctx_t *ctx, lis3de_ig1_cfg_t *val) { int32_t ret; @@ -1040,7 +1050,7 @@ int32_t lis3de_int1_gen_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_int1_gen_conf_get(stmdev_ctx_t *ctx, +int32_t lis3de_int1_gen_conf_get(const stmdev_ctx_t *ctx, lis3de_ig1_cfg_t *val) { int32_t ret; @@ -1058,7 +1068,7 @@ int32_t lis3de_int1_gen_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_int1_gen_source_get(stmdev_ctx_t *ctx, +int32_t lis3de_int1_gen_source_get(const stmdev_ctx_t *ctx, lis3de_ig1_source_t *val) { int32_t ret; @@ -1077,7 +1087,7 @@ int32_t lis3de_int1_gen_source_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_int1_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3de_int1_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3de_ig1_ths_t int1_ths; int32_t ret; @@ -1103,7 +1113,7 @@ int32_t lis3de_int1_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_int1_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3de_int1_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3de_ig1_ths_t int1_ths; int32_t ret; @@ -1123,7 +1133,7 @@ int32_t lis3de_int1_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3de_int1_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3de_ig1_duration_t int1_duration; int32_t ret; @@ -1150,7 +1160,7 @@ int32_t lis3de_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3de_int1_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3de_ig1_duration_t int1_duration; int32_t ret; @@ -1183,7 +1193,7 @@ int32_t lis3de_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_int2_gen_conf_set(stmdev_ctx_t *ctx, +int32_t lis3de_int2_gen_conf_set(const stmdev_ctx_t *ctx, lis3de_ig2_cfg_t *val) { int32_t ret; @@ -1201,7 +1211,7 @@ int32_t lis3de_int2_gen_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_int2_gen_conf_get(stmdev_ctx_t *ctx, +int32_t lis3de_int2_gen_conf_get(const stmdev_ctx_t *ctx, lis3de_ig2_cfg_t *val) { int32_t ret; @@ -1218,7 +1228,7 @@ int32_t lis3de_int2_gen_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_int2_gen_source_get(stmdev_ctx_t *ctx, +int32_t lis3de_int2_gen_source_get(const stmdev_ctx_t *ctx, lis3de_ig2_source_t *val) { int32_t ret; @@ -1237,7 +1247,7 @@ int32_t lis3de_int2_gen_source_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_int2_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3de_int2_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3de_ig2_ths_t int2_ths; int32_t ret; @@ -1263,7 +1273,7 @@ int32_t lis3de_int2_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_int2_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3de_int2_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3de_ig2_ths_t int2_ths; int32_t ret; @@ -1283,7 +1293,7 @@ int32_t lis3de_int2_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3de_int2_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3de_ig2_duration_t int2_duration; int32_t ret; @@ -1310,7 +1320,7 @@ int32_t lis3de_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3de_int2_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3de_ig2_duration_t int2_duration; int32_t ret; @@ -1342,7 +1352,7 @@ int32_t lis3de_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_high_pass_int_conf_set(stmdev_ctx_t *ctx, +int32_t lis3de_high_pass_int_conf_set(const stmdev_ctx_t *ctx, lis3de_hp_t val) { lis3de_ctrl_reg2_t ctrl_reg2; @@ -1367,7 +1377,7 @@ int32_t lis3de_high_pass_int_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_high_pass_int_conf_get(stmdev_ctx_t *ctx, +int32_t lis3de_high_pass_int_conf_get(const stmdev_ctx_t *ctx, lis3de_hp_t *val) { lis3de_ctrl_reg2_t ctrl_reg2; @@ -1425,7 +1435,7 @@ int32_t lis3de_high_pass_int_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_pin_int1_config_set(stmdev_ctx_t *ctx, +int32_t lis3de_pin_int1_config_set(const stmdev_ctx_t *ctx, lis3de_ctrl_reg3_t *val) { int32_t ret; @@ -1443,7 +1453,7 @@ int32_t lis3de_pin_int1_config_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_pin_int1_config_get(stmdev_ctx_t *ctx, +int32_t lis3de_pin_int1_config_get(const stmdev_ctx_t *ctx, lis3de_ctrl_reg3_t *val) { int32_t ret; @@ -1462,7 +1472,7 @@ int32_t lis3de_pin_int1_config_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3de_int2_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3de_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1487,7 +1497,7 @@ int32_t lis3de_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3de_int2_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3de_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1508,7 +1518,7 @@ int32_t lis3de_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_int2_pin_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis3de_int2_pin_notification_mode_set(const stmdev_ctx_t *ctx, lis3de_lir_int2_t val) { lis3de_ctrl_reg5_t ctrl_reg5; @@ -1535,7 +1545,7 @@ int32_t lis3de_int2_pin_notification_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_int2_pin_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis3de_int2_pin_notification_mode_get(const stmdev_ctx_t *ctx, lis3de_lir_int2_t *val) { lis3de_ctrl_reg5_t ctrl_reg5; @@ -1570,7 +1580,7 @@ int32_t lis3de_int2_pin_notification_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3de_int1_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3de_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1595,7 +1605,7 @@ int32_t lis3de_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3de_int1_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3de_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1615,7 +1625,7 @@ int32_t lis3de_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_int1_pin_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis3de_int1_pin_notification_mode_set(const stmdev_ctx_t *ctx, lis3de_lir_int1_t val) { lis3de_ctrl_reg5_t ctrl_reg5; @@ -1641,7 +1651,7 @@ int32_t lis3de_int1_pin_notification_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_int1_pin_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis3de_int1_pin_notification_mode_get(const stmdev_ctx_t *ctx, lis3de_lir_int1_t *val) { lis3de_ctrl_reg5_t ctrl_reg5; @@ -1675,7 +1685,7 @@ int32_t lis3de_int1_pin_notification_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_pin_int2_config_set(stmdev_ctx_t *ctx, +int32_t lis3de_pin_int2_config_set(const stmdev_ctx_t *ctx, lis3de_ctrl_reg6_t *val) { int32_t ret; @@ -1693,7 +1703,7 @@ int32_t lis3de_pin_int2_config_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_pin_int2_config_get(stmdev_ctx_t *ctx, +int32_t lis3de_pin_int2_config_get(const stmdev_ctx_t *ctx, lis3de_ctrl_reg6_t *val) { int32_t ret; @@ -1722,7 +1732,7 @@ int32_t lis3de_pin_int2_config_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_fifo_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3de_fifo_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3de_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1746,7 +1756,7 @@ int32_t lis3de_fifo_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_fifo_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3de_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3de_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1765,7 +1775,7 @@ int32_t lis3de_fifo_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3de_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3de_fifo_ctrl_reg_t fifo_ctrl_reg; int32_t ret; @@ -1791,7 +1801,7 @@ int32_t lis3de_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3de_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3de_fifo_ctrl_reg_t fifo_ctrl_reg; int32_t ret; @@ -1811,7 +1821,7 @@ int32_t lis3de_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_fifo_trigger_event_set(stmdev_ctx_t *ctx, +int32_t lis3de_fifo_trigger_event_set(const stmdev_ctx_t *ctx, lis3de_tr_t val) { lis3de_fifo_ctrl_reg_t fifo_ctrl_reg; @@ -1838,7 +1848,7 @@ int32_t lis3de_fifo_trigger_event_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_fifo_trigger_event_get(stmdev_ctx_t *ctx, +int32_t lis3de_fifo_trigger_event_get(const stmdev_ctx_t *ctx, lis3de_tr_t *val) { lis3de_fifo_ctrl_reg_t fifo_ctrl_reg; @@ -1873,7 +1883,7 @@ int32_t lis3de_fifo_trigger_event_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_fifo_mode_set(stmdev_ctx_t *ctx, lis3de_fm_t val) +int32_t lis3de_fifo_mode_set(const stmdev_ctx_t *ctx, lis3de_fm_t val) { lis3de_fifo_ctrl_reg_t fifo_ctrl_reg; int32_t ret; @@ -1899,7 +1909,7 @@ int32_t lis3de_fifo_mode_set(stmdev_ctx_t *ctx, lis3de_fm_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_fifo_mode_get(stmdev_ctx_t *ctx, lis3de_fm_t *val) +int32_t lis3de_fifo_mode_get(const stmdev_ctx_t *ctx, lis3de_fm_t *val) { lis3de_fifo_ctrl_reg_t fifo_ctrl_reg; int32_t ret; @@ -1941,7 +1951,7 @@ int32_t lis3de_fifo_mode_get(stmdev_ctx_t *ctx, lis3de_fm_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lis3de_fifo_status_get(const stmdev_ctx_t *ctx, lis3de_fifo_src_reg_t *val) { int32_t ret; @@ -1958,7 +1968,7 @@ int32_t lis3de_fifo_status_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3de_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3de_fifo_src_reg_t fifo_src_reg; int32_t ret; @@ -1977,7 +1987,7 @@ int32_t lis3de_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3de_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3de_fifo_src_reg_t fifo_src_reg; int32_t ret; @@ -1996,7 +2006,7 @@ int32_t lis3de_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3de_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3de_fifo_src_reg_t fifo_src_reg; int32_t ret; @@ -2015,7 +2025,7 @@ int32_t lis3de_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3de_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3de_fifo_src_reg_t fifo_src_reg; int32_t ret; @@ -2047,7 +2057,7 @@ int32_t lis3de_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_tap_conf_set(stmdev_ctx_t *ctx, +int32_t lis3de_tap_conf_set(const stmdev_ctx_t *ctx, lis3de_click_cfg_t *val) { int32_t ret; @@ -2065,7 +2075,7 @@ int32_t lis3de_tap_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_tap_conf_get(stmdev_ctx_t *ctx, +int32_t lis3de_tap_conf_get(const stmdev_ctx_t *ctx, lis3de_click_cfg_t *val) { int32_t ret; @@ -2082,7 +2092,7 @@ int32_t lis3de_tap_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_tap_source_get(stmdev_ctx_t *ctx, +int32_t lis3de_tap_source_get(const stmdev_ctx_t *ctx, lis3de_click_src_t *val) { int32_t ret; @@ -2100,7 +2110,7 @@ int32_t lis3de_tap_source_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3de_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3de_click_ths_t click_ths; int32_t ret; @@ -2125,7 +2135,7 @@ int32_t lis3de_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3de_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3de_click_ths_t click_ths; int32_t ret; @@ -2147,7 +2157,7 @@ int32_t lis3de_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_tap_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis3de_tap_notification_mode_set(const stmdev_ctx_t *ctx, lis3de_lir_t val) { lis3de_click_ths_t click_ths; @@ -2175,7 +2185,7 @@ int32_t lis3de_tap_notification_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_tap_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis3de_tap_notification_mode_get(const stmdev_ctx_t *ctx, lis3de_lir_t *val) { lis3de_click_ths_t click_ths; @@ -2211,7 +2221,7 @@ int32_t lis3de_tap_notification_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3de_shock_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3de_time_limit_t time_limit; int32_t ret; @@ -2237,7 +2247,7 @@ int32_t lis3de_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3de_shock_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3de_time_limit_t time_limit; int32_t ret; @@ -2259,7 +2269,7 @@ int32_t lis3de_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3de_quiet_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3de_time_latency_t time_latency; int32_t ret; @@ -2288,7 +2298,7 @@ int32_t lis3de_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3de_quiet_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3de_time_latency_t time_latency; int32_t ret; @@ -2311,7 +2321,7 @@ int32_t lis3de_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3de_double_tap_timeout_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3de_time_window_t time_window; int32_t ret; @@ -2340,7 +2350,7 @@ int32_t lis3de_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_double_tap_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3de_double_tap_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3de_time_window_t time_window; int32_t ret; @@ -2375,7 +2385,7 @@ int32_t lis3de_double_tap_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3de_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3de_act_ths_t act_ths; int32_t ret; @@ -2401,7 +2411,7 @@ int32_t lis3de_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3de_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3de_act_ths_t act_ths; int32_t ret; @@ -2421,7 +2431,7 @@ int32_t lis3de_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3de_act_timeout_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3de_act_dur_t act_dur; int32_t ret; @@ -2446,7 +2456,7 @@ int32_t lis3de_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3de_act_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3de_act_dur_t act_dur; int32_t ret; @@ -2478,7 +2488,7 @@ int32_t lis3de_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_spi_mode_set(stmdev_ctx_t *ctx, lis3de_sim_t val) +int32_t lis3de_spi_mode_set(const stmdev_ctx_t *ctx, lis3de_sim_t val) { lis3de_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -2502,7 +2512,7 @@ int32_t lis3de_spi_mode_set(stmdev_ctx_t *ctx, lis3de_sim_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3de_spi_mode_get(stmdev_ctx_t *ctx, lis3de_sim_t *val) +int32_t lis3de_spi_mode_get(const stmdev_ctx_t *ctx, lis3de_sim_t *val) { lis3de_ctrl_reg4_t ctrl_reg4; int32_t ret; diff --git a/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.h b/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.h index 938d9bbe..665c4710 100644 --- a/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.h +++ b/sensor/stmemsc/lis3de_STdC/driver/lis3de_reg.h @@ -716,9 +716,9 @@ typedef union * them with a custom implementation. */ -int32_t lis3de_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, +int32_t lis3de_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lis3de_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lis3de_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -729,13 +729,13 @@ float_t lis3de_from_fs16_to_mg(int16_t lsb); float_t lis3de_from_lsb_to_celsius(int16_t lsb); -int32_t lis3de_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis3de_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3de_temp_status_reg_get(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis3de_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3de_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3de_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3de_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis3de_adc_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lis3de_temperature_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis3de_adc_raw_get(const stmdev_ctx_t *ctx, int16_t *val); typedef enum { @@ -743,17 +743,17 @@ typedef enum LIS3DE_AUX_ON_TEMPERATURE = 3, LIS3DE_AUX_ON_PADS = 1, } lis3de_temp_en_t; -int32_t lis3de_aux_adc_set(stmdev_ctx_t *ctx, lis3de_temp_en_t val); -int32_t lis3de_aux_adc_get(stmdev_ctx_t *ctx, lis3de_temp_en_t *val); +int32_t lis3de_aux_adc_set(const stmdev_ctx_t *ctx, lis3de_temp_en_t val); +int32_t lis3de_aux_adc_get(const stmdev_ctx_t *ctx, lis3de_temp_en_t *val); typedef enum { LIS3DE_NM = 0, LIS3DE_LP = 1, } lis3de_op_md_t; -int32_t lis3de_operating_mode_set(stmdev_ctx_t *ctx, +int32_t lis3de_operating_mode_set(const stmdev_ctx_t *ctx, lis3de_op_md_t val); -int32_t lis3de_operating_mode_get(stmdev_ctx_t *ctx, +int32_t lis3de_operating_mode_get(const stmdev_ctx_t *ctx, lis3de_op_md_t *val); typedef enum @@ -769,12 +769,12 @@ typedef enum LIS3DE_ODR_1kHz6 = 0x08, LIS3DE_ODR_5kHz376_LP_1kHz344_NM = 0x09, } lis3de_odr_t; -int32_t lis3de_data_rate_set(stmdev_ctx_t *ctx, lis3de_odr_t val); -int32_t lis3de_data_rate_get(stmdev_ctx_t *ctx, lis3de_odr_t *val); +int32_t lis3de_data_rate_set(const stmdev_ctx_t *ctx, lis3de_odr_t val); +int32_t lis3de_data_rate_get(const stmdev_ctx_t *ctx, lis3de_odr_t *val); -int32_t lis3de_high_pass_on_outputs_set(stmdev_ctx_t *ctx, +int32_t lis3de_high_pass_on_outputs_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3de_high_pass_on_outputs_get(stmdev_ctx_t *ctx, +int32_t lis3de_high_pass_on_outputs_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -784,9 +784,9 @@ typedef enum LIS3DE_MEDIUM = 2, LIS3DE_LIGHT = 3, } lis3de_hpcf_t; -int32_t lis3de_high_pass_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lis3de_high_pass_bandwidth_set(const stmdev_ctx_t *ctx, lis3de_hpcf_t val); -int32_t lis3de_high_pass_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lis3de_high_pass_bandwidth_get(const stmdev_ctx_t *ctx, lis3de_hpcf_t *val); typedef enum @@ -796,9 +796,9 @@ typedef enum LIS3DE_NORMAL = 2, LIS3DE_AUTORST_ON_INT = 3, } lis3de_hpm_t; -int32_t lis3de_high_pass_mode_set(stmdev_ctx_t *ctx, +int32_t lis3de_high_pass_mode_set(const stmdev_ctx_t *ctx, lis3de_hpm_t val); -int32_t lis3de_high_pass_mode_get(stmdev_ctx_t *ctx, +int32_t lis3de_high_pass_mode_get(const stmdev_ctx_t *ctx, lis3de_hpm_t *val); typedef enum @@ -808,22 +808,22 @@ typedef enum LIS3DE_8g = 2, LIS3DE_16g = 3, } lis3de_fs_t; -int32_t lis3de_full_scale_set(stmdev_ctx_t *ctx, lis3de_fs_t val); -int32_t lis3de_full_scale_get(stmdev_ctx_t *ctx, lis3de_fs_t *val); +int32_t lis3de_full_scale_set(const stmdev_ctx_t *ctx, lis3de_fs_t val); +int32_t lis3de_full_scale_get(const stmdev_ctx_t *ctx, lis3de_fs_t *val); -int32_t lis3de_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3de_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3de_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3de_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3de_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis3de_filter_reference_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis3de_filter_reference_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis3de_filter_reference_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis3de_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3de_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3de_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3de_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3de_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *buff); +int32_t lis3de_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *buff); -int32_t lis3de_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis3de_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); typedef enum { @@ -831,44 +831,44 @@ typedef enum LIS3DE_ST_POSITIVE = 1, LIS3DE_ST_NEGATIVE = 2, } lis3de_st_t; -int32_t lis3de_self_test_set(stmdev_ctx_t *ctx, lis3de_st_t val); -int32_t lis3de_self_test_get(stmdev_ctx_t *ctx, lis3de_st_t *val); +int32_t lis3de_self_test_set(const stmdev_ctx_t *ctx, lis3de_st_t val); +int32_t lis3de_self_test_get(const stmdev_ctx_t *ctx, lis3de_st_t *val); -int32_t lis3de_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3de_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3de_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3de_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3de_status_get(stmdev_ctx_t *ctx, +int32_t lis3de_status_get(const stmdev_ctx_t *ctx, lis3de_status_reg_t *val); -int32_t lis3de_int1_gen_conf_set(stmdev_ctx_t *ctx, +int32_t lis3de_int1_gen_conf_set(const stmdev_ctx_t *ctx, lis3de_ig1_cfg_t *val); -int32_t lis3de_int1_gen_conf_get(stmdev_ctx_t *ctx, +int32_t lis3de_int1_gen_conf_get(const stmdev_ctx_t *ctx, lis3de_ig1_cfg_t *val); -int32_t lis3de_int1_gen_source_get(stmdev_ctx_t *ctx, +int32_t lis3de_int1_gen_source_get(const stmdev_ctx_t *ctx, lis3de_ig1_source_t *val); -int32_t lis3de_int1_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3de_int1_gen_threshold_get(stmdev_ctx_t *ctx, +int32_t lis3de_int1_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3de_int1_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3de_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3de_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3de_int1_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3de_int1_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3de_int2_gen_conf_set(stmdev_ctx_t *ctx, +int32_t lis3de_int2_gen_conf_set(const stmdev_ctx_t *ctx, lis3de_ig2_cfg_t *val); -int32_t lis3de_int2_gen_conf_get(stmdev_ctx_t *ctx, +int32_t lis3de_int2_gen_conf_get(const stmdev_ctx_t *ctx, lis3de_ig2_cfg_t *val); -int32_t lis3de_int2_gen_source_get(stmdev_ctx_t *ctx, +int32_t lis3de_int2_gen_source_get(const stmdev_ctx_t *ctx, lis3de_ig2_source_t *val); -int32_t lis3de_int2_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3de_int2_gen_threshold_get(stmdev_ctx_t *ctx, +int32_t lis3de_int2_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3de_int2_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3de_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3de_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3de_int2_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3de_int2_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -881,18 +881,18 @@ typedef enum LIS3DE_ON_INT2_TAP_GEN = 6, LIS3DE_ON_INT1_INT2_TAP_GEN = 7, } lis3de_hp_t; -int32_t lis3de_high_pass_int_conf_set(stmdev_ctx_t *ctx, +int32_t lis3de_high_pass_int_conf_set(const stmdev_ctx_t *ctx, lis3de_hp_t val); -int32_t lis3de_high_pass_int_conf_get(stmdev_ctx_t *ctx, +int32_t lis3de_high_pass_int_conf_get(const stmdev_ctx_t *ctx, lis3de_hp_t *val); -int32_t lis3de_pin_int1_config_set(stmdev_ctx_t *ctx, +int32_t lis3de_pin_int1_config_set(const stmdev_ctx_t *ctx, lis3de_ctrl_reg3_t *val); -int32_t lis3de_pin_int1_config_get(stmdev_ctx_t *ctx, +int32_t lis3de_pin_int1_config_get(const stmdev_ctx_t *ctx, lis3de_ctrl_reg3_t *val); -int32_t lis3de_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3de_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, +int32_t lis3de_int2_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3de_int2_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -900,13 +900,13 @@ typedef enum LIS3DE_INT2_PULSED = 0, LIS3DE_INT2_LATCHED = 1, } lis3de_lir_int2_t; -int32_t lis3de_int2_pin_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis3de_int2_pin_notification_mode_set(const stmdev_ctx_t *ctx, lis3de_lir_int2_t val); -int32_t lis3de_int2_pin_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis3de_int2_pin_notification_mode_get(const stmdev_ctx_t *ctx, lis3de_lir_int2_t *val); -int32_t lis3de_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3de_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, +int32_t lis3de_int1_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3de_int1_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -914,30 +914,30 @@ typedef enum LIS3DE_INT1_PULSED = 0, LIS3DE_INT1_LATCHED = 1, } lis3de_lir_int1_t; -int32_t lis3de_int1_pin_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis3de_int1_pin_notification_mode_set(const stmdev_ctx_t *ctx, lis3de_lir_int1_t val); -int32_t lis3de_int1_pin_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis3de_int1_pin_notification_mode_get(const stmdev_ctx_t *ctx, lis3de_lir_int1_t *val); -int32_t lis3de_pin_int2_config_set(stmdev_ctx_t *ctx, +int32_t lis3de_pin_int2_config_set(const stmdev_ctx_t *ctx, lis3de_ctrl_reg6_t *val); -int32_t lis3de_pin_int2_config_get(stmdev_ctx_t *ctx, +int32_t lis3de_pin_int2_config_get(const stmdev_ctx_t *ctx, lis3de_ctrl_reg6_t *val); -int32_t lis3de_fifo_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3de_fifo_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3de_fifo_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3de_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3de_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3de_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3de_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3de_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LIS3DE_INT1_GEN = 0, LIS3DE_INT2_GEN = 1, } lis3de_tr_t; -int32_t lis3de_fifo_trigger_event_set(stmdev_ctx_t *ctx, +int32_t lis3de_fifo_trigger_event_set(const stmdev_ctx_t *ctx, lis3de_tr_t val); -int32_t lis3de_fifo_trigger_event_get(stmdev_ctx_t *ctx, +int32_t lis3de_fifo_trigger_event_get(const stmdev_ctx_t *ctx, lis3de_tr_t *val); typedef enum @@ -947,64 +947,64 @@ typedef enum LIS3DE_DYNAMIC_STREAM_MODE = 2, LIS3DE_STREAM_TO_FIFO_MODE = 3, } lis3de_fm_t; -int32_t lis3de_fifo_mode_set(stmdev_ctx_t *ctx, lis3de_fm_t val); -int32_t lis3de_fifo_mode_get(stmdev_ctx_t *ctx, lis3de_fm_t *val); +int32_t lis3de_fifo_mode_set(const stmdev_ctx_t *ctx, lis3de_fm_t val); +int32_t lis3de_fifo_mode_get(const stmdev_ctx_t *ctx, lis3de_fm_t *val); -int32_t lis3de_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lis3de_fifo_status_get(const stmdev_ctx_t *ctx, lis3de_fifo_src_reg_t *val); -int32_t lis3de_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3de_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3de_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3de_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3de_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3de_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3de_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3de_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3de_tap_conf_set(stmdev_ctx_t *ctx, +int32_t lis3de_tap_conf_set(const stmdev_ctx_t *ctx, lis3de_click_cfg_t *val); -int32_t lis3de_tap_conf_get(stmdev_ctx_t *ctx, +int32_t lis3de_tap_conf_get(const stmdev_ctx_t *ctx, lis3de_click_cfg_t *val); -int32_t lis3de_tap_source_get(stmdev_ctx_t *ctx, +int32_t lis3de_tap_source_get(const stmdev_ctx_t *ctx, lis3de_click_src_t *val); -int32_t lis3de_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3de_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3de_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3de_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LIS3DE_TAP_PULSED = 0, LIS3DE_TAP_LATCHED = 1, } lis3de_lir_t; -int32_t lis3de_tap_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis3de_tap_notification_mode_set(const stmdev_ctx_t *ctx, lis3de_lir_t val); -int32_t lis3de_tap_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis3de_tap_notification_mode_get(const stmdev_ctx_t *ctx, lis3de_lir_t *val); -int32_t lis3de_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3de_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3de_shock_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3de_shock_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3de_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3de_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3de_quiet_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3de_quiet_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3de_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3de_double_tap_timeout_get(stmdev_ctx_t *ctx, +int32_t lis3de_double_tap_timeout_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3de_double_tap_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3de_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3de_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3de_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3de_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3de_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3de_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3de_act_timeout_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3de_act_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LIS3DE_SPI_4_WIRE = 0, LIS3DE_SPI_3_WIRE = 1, } lis3de_sim_t; -int32_t lis3de_spi_mode_set(stmdev_ctx_t *ctx, lis3de_sim_t val); -int32_t lis3de_spi_mode_get(stmdev_ctx_t *ctx, lis3de_sim_t *val); +int32_t lis3de_spi_mode_set(const stmdev_ctx_t *ctx, lis3de_sim_t val); +int32_t lis3de_spi_mode_get(const stmdev_ctx_t *ctx, lis3de_sim_t *val); /** * @} diff --git a/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.c b/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.c index 47d2526b..e4457a5a 100644 --- a/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.c +++ b/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.c @@ -46,11 +46,16 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis3dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, +int32_t __weak lis3dh_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -66,12 +71,17 @@ int32_t __weak lis3dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis3dh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lis3dh_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -184,7 +194,7 @@ float_t lis3dh_from_lsb_lp_to_celsius(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis3dh_temp_status_reg_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -200,7 +210,7 @@ int32_t lis3dh_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dh_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dh_status_reg_aux_t status_reg_aux; int32_t ret; @@ -219,7 +229,7 @@ int32_t lis3dh_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dh_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dh_status_reg_aux_t status_reg_aux; int32_t ret; @@ -238,7 +248,7 @@ int32_t lis3dh_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lis3dh_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -270,7 +280,7 @@ int32_t lis3dh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_adc_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lis3dh_adc_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -294,7 +304,7 @@ int32_t lis3dh_adc_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_aux_adc_set(stmdev_ctx_t *ctx, lis3dh_temp_en_t val) +int32_t lis3dh_aux_adc_set(const stmdev_ctx_t *ctx, lis3dh_temp_en_t val) { lis3dh_temp_cfg_reg_t temp_cfg_reg; int32_t ret; @@ -330,7 +340,7 @@ int32_t lis3dh_aux_adc_set(stmdev_ctx_t *ctx, lis3dh_temp_en_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_aux_adc_get(stmdev_ctx_t *ctx, lis3dh_temp_en_t *val) +int32_t lis3dh_aux_adc_get(const stmdev_ctx_t *ctx, lis3dh_temp_en_t *val) { lis3dh_temp_cfg_reg_t temp_cfg_reg; int32_t ret; @@ -367,7 +377,7 @@ int32_t lis3dh_aux_adc_get(stmdev_ctx_t *ctx, lis3dh_temp_en_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_operating_mode_set(stmdev_ctx_t *ctx, +int32_t lis3dh_operating_mode_set(const stmdev_ctx_t *ctx, lis3dh_op_md_t val) { lis3dh_ctrl_reg1_t ctrl_reg1; @@ -422,7 +432,7 @@ int32_t lis3dh_operating_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_operating_mode_get(stmdev_ctx_t *ctx, +int32_t lis3dh_operating_mode_get(const stmdev_ctx_t *ctx, lis3dh_op_md_t *val) { lis3dh_ctrl_reg1_t ctrl_reg1; @@ -462,7 +472,7 @@ int32_t lis3dh_operating_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_data_rate_set(stmdev_ctx_t *ctx, lis3dh_odr_t val) +int32_t lis3dh_data_rate_set(const stmdev_ctx_t *ctx, lis3dh_odr_t val) { lis3dh_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -486,7 +496,7 @@ int32_t lis3dh_data_rate_set(stmdev_ctx_t *ctx, lis3dh_odr_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_data_rate_get(stmdev_ctx_t *ctx, lis3dh_odr_t *val) +int32_t lis3dh_data_rate_get(const stmdev_ctx_t *ctx, lis3dh_odr_t *val) { lis3dh_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -552,7 +562,7 @@ int32_t lis3dh_data_rate_get(stmdev_ctx_t *ctx, lis3dh_odr_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_high_pass_on_outputs_set(stmdev_ctx_t *ctx, +int32_t lis3dh_high_pass_on_outputs_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dh_ctrl_reg2_t ctrl_reg2; @@ -578,7 +588,7 @@ int32_t lis3dh_high_pass_on_outputs_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_high_pass_on_outputs_get(stmdev_ctx_t *ctx, +int32_t lis3dh_high_pass_on_outputs_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dh_ctrl_reg2_t ctrl_reg2; @@ -604,7 +614,7 @@ int32_t lis3dh_high_pass_on_outputs_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_high_pass_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lis3dh_high_pass_bandwidth_set(const stmdev_ctx_t *ctx, lis3dh_hpcf_t val) { lis3dh_ctrl_reg2_t ctrl_reg2; @@ -635,7 +645,7 @@ int32_t lis3dh_high_pass_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_high_pass_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lis3dh_high_pass_bandwidth_get(const stmdev_ctx_t *ctx, lis3dh_hpcf_t *val) { lis3dh_ctrl_reg2_t ctrl_reg2; @@ -677,7 +687,7 @@ int32_t lis3dh_high_pass_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_high_pass_mode_set(stmdev_ctx_t *ctx, lis3dh_hpm_t val) +int32_t lis3dh_high_pass_mode_set(const stmdev_ctx_t *ctx, lis3dh_hpm_t val) { lis3dh_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -701,7 +711,7 @@ int32_t lis3dh_high_pass_mode_set(stmdev_ctx_t *ctx, lis3dh_hpm_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_high_pass_mode_get(stmdev_ctx_t *ctx, +int32_t lis3dh_high_pass_mode_get(const stmdev_ctx_t *ctx, lis3dh_hpm_t *val) { lis3dh_ctrl_reg2_t ctrl_reg2; @@ -743,7 +753,7 @@ int32_t lis3dh_high_pass_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_full_scale_set(stmdev_ctx_t *ctx, lis3dh_fs_t val) +int32_t lis3dh_full_scale_set(const stmdev_ctx_t *ctx, lis3dh_fs_t val) { lis3dh_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -767,7 +777,7 @@ int32_t lis3dh_full_scale_set(stmdev_ctx_t *ctx, lis3dh_fs_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_full_scale_get(stmdev_ctx_t *ctx, lis3dh_fs_t *val) +int32_t lis3dh_full_scale_get(const stmdev_ctx_t *ctx, lis3dh_fs_t *val) { lis3dh_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -808,7 +818,7 @@ int32_t lis3dh_full_scale_get(stmdev_ctx_t *ctx, lis3dh_fs_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dh_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dh_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -832,7 +842,7 @@ int32_t lis3dh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dh_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dh_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -852,7 +862,7 @@ int32_t lis3dh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis3dh_filter_reference_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -870,7 +880,7 @@ int32_t lis3dh_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_filter_reference_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis3dh_filter_reference_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -886,7 +896,7 @@ int32_t lis3dh_filter_reference_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dh_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dh_status_reg_t status_reg; int32_t ret; @@ -904,7 +914,7 @@ int32_t lis3dh_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dh_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dh_status_reg_t status_reg; int32_t ret; @@ -922,7 +932,7 @@ int32_t lis3dh_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lis3dh_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -957,7 +967,7 @@ int32_t lis3dh_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis3dh_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -973,7 +983,7 @@ int32_t lis3dh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_self_test_set(stmdev_ctx_t *ctx, lis3dh_st_t val) +int32_t lis3dh_self_test_set(const stmdev_ctx_t *ctx, lis3dh_st_t val) { lis3dh_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -997,7 +1007,7 @@ int32_t lis3dh_self_test_set(stmdev_ctx_t *ctx, lis3dh_st_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_self_test_get(stmdev_ctx_t *ctx, lis3dh_st_t *val) +int32_t lis3dh_self_test_get(const stmdev_ctx_t *ctx, lis3dh_st_t *val) { lis3dh_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -1034,7 +1044,7 @@ int32_t lis3dh_self_test_get(stmdev_ctx_t *ctx, lis3dh_st_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_data_format_set(stmdev_ctx_t *ctx, lis3dh_ble_t val) +int32_t lis3dh_data_format_set(const stmdev_ctx_t *ctx, lis3dh_ble_t val) { lis3dh_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -1058,7 +1068,7 @@ int32_t lis3dh_data_format_set(stmdev_ctx_t *ctx, lis3dh_ble_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_data_format_get(stmdev_ctx_t *ctx, lis3dh_ble_t *val) +int32_t lis3dh_data_format_get(const stmdev_ctx_t *ctx, lis3dh_ble_t *val) { lis3dh_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -1091,7 +1101,7 @@ int32_t lis3dh_data_format_get(stmdev_ctx_t *ctx, lis3dh_ble_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dh_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dh_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1115,7 +1125,7 @@ int32_t lis3dh_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dh_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dh_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1134,7 +1144,7 @@ int32_t lis3dh_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_status_get(stmdev_ctx_t *ctx, lis3dh_status_reg_t *val) +int32_t lis3dh_status_get(const stmdev_ctx_t *ctx, lis3dh_status_reg_t *val) { int32_t ret; @@ -1163,7 +1173,7 @@ int32_t lis3dh_status_get(stmdev_ctx_t *ctx, lis3dh_status_reg_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_int1_gen_conf_set(stmdev_ctx_t *ctx, +int32_t lis3dh_int1_gen_conf_set(const stmdev_ctx_t *ctx, lis3dh_int1_cfg_t *val) { int32_t ret; @@ -1181,7 +1191,7 @@ int32_t lis3dh_int1_gen_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_int1_gen_conf_get(stmdev_ctx_t *ctx, +int32_t lis3dh_int1_gen_conf_get(const stmdev_ctx_t *ctx, lis3dh_int1_cfg_t *val) { int32_t ret; @@ -1199,7 +1209,7 @@ int32_t lis3dh_int1_gen_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_int1_gen_source_get(stmdev_ctx_t *ctx, +int32_t lis3dh_int1_gen_source_get(const stmdev_ctx_t *ctx, lis3dh_int1_src_t *val) { int32_t ret; @@ -1218,7 +1228,7 @@ int32_t lis3dh_int1_gen_source_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_int1_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dh_int1_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dh_int1_ths_t int1_ths; int32_t ret; @@ -1244,7 +1254,7 @@ int32_t lis3dh_int1_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_int1_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dh_int1_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dh_int1_ths_t int1_ths; int32_t ret; @@ -1264,7 +1274,7 @@ int32_t lis3dh_int1_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dh_int1_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dh_int1_duration_t int1_duration; int32_t ret; @@ -1291,7 +1301,7 @@ int32_t lis3dh_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dh_int1_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dh_int1_duration_t int1_duration; int32_t ret; @@ -1324,7 +1334,7 @@ int32_t lis3dh_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_int2_gen_conf_set(stmdev_ctx_t *ctx, +int32_t lis3dh_int2_gen_conf_set(const stmdev_ctx_t *ctx, lis3dh_int2_cfg_t *val) { int32_t ret; @@ -1342,7 +1352,7 @@ int32_t lis3dh_int2_gen_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_int2_gen_conf_get(stmdev_ctx_t *ctx, +int32_t lis3dh_int2_gen_conf_get(const stmdev_ctx_t *ctx, lis3dh_int2_cfg_t *val) { int32_t ret; @@ -1359,7 +1369,7 @@ int32_t lis3dh_int2_gen_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_int2_gen_source_get(stmdev_ctx_t *ctx, +int32_t lis3dh_int2_gen_source_get(const stmdev_ctx_t *ctx, lis3dh_int2_src_t *val) { int32_t ret; @@ -1378,7 +1388,7 @@ int32_t lis3dh_int2_gen_source_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_int2_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dh_int2_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dh_int2_ths_t int2_ths; int32_t ret; @@ -1404,7 +1414,7 @@ int32_t lis3dh_int2_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_int2_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dh_int2_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dh_int2_ths_t int2_ths; int32_t ret; @@ -1424,7 +1434,7 @@ int32_t lis3dh_int2_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dh_int2_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dh_int2_duration_t int2_duration; int32_t ret; @@ -1451,7 +1461,7 @@ int32_t lis3dh_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dh_int2_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dh_int2_duration_t int2_duration; int32_t ret; @@ -1483,7 +1493,7 @@ int32_t lis3dh_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_high_pass_int_conf_set(stmdev_ctx_t *ctx, +int32_t lis3dh_high_pass_int_conf_set(const stmdev_ctx_t *ctx, lis3dh_hp_t val) { lis3dh_ctrl_reg2_t ctrl_reg2; @@ -1508,7 +1518,7 @@ int32_t lis3dh_high_pass_int_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_high_pass_int_conf_get(stmdev_ctx_t *ctx, +int32_t lis3dh_high_pass_int_conf_get(const stmdev_ctx_t *ctx, lis3dh_hp_t *val) { lis3dh_ctrl_reg2_t ctrl_reg2; @@ -1566,7 +1576,7 @@ int32_t lis3dh_high_pass_int_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_pin_int1_config_set(stmdev_ctx_t *ctx, +int32_t lis3dh_pin_int1_config_set(const stmdev_ctx_t *ctx, lis3dh_ctrl_reg3_t *val) { int32_t ret; @@ -1584,7 +1594,7 @@ int32_t lis3dh_pin_int1_config_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_pin_int1_config_get(stmdev_ctx_t *ctx, +int32_t lis3dh_pin_int1_config_get(const stmdev_ctx_t *ctx, lis3dh_ctrl_reg3_t *val) { int32_t ret; @@ -1603,7 +1613,7 @@ int32_t lis3dh_pin_int1_config_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dh_int2_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dh_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1628,7 +1638,7 @@ int32_t lis3dh_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dh_int2_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dh_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1649,7 +1659,7 @@ int32_t lis3dh_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_int2_pin_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis3dh_int2_pin_notification_mode_set(const stmdev_ctx_t *ctx, lis3dh_lir_int2_t val) { lis3dh_ctrl_reg5_t ctrl_reg5; @@ -1676,7 +1686,7 @@ int32_t lis3dh_int2_pin_notification_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_int2_pin_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis3dh_int2_pin_notification_mode_get(const stmdev_ctx_t *ctx, lis3dh_lir_int2_t *val) { lis3dh_ctrl_reg5_t ctrl_reg5; @@ -1711,7 +1721,7 @@ int32_t lis3dh_int2_pin_notification_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dh_int1_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dh_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1736,7 +1746,7 @@ int32_t lis3dh_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dh_int1_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dh_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1756,7 +1766,7 @@ int32_t lis3dh_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_int1_pin_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis3dh_int1_pin_notification_mode_set(const stmdev_ctx_t *ctx, lis3dh_lir_int1_t val) { lis3dh_ctrl_reg5_t ctrl_reg5; @@ -1782,7 +1792,7 @@ int32_t lis3dh_int1_pin_notification_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_int1_pin_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis3dh_int1_pin_notification_mode_get(const stmdev_ctx_t *ctx, lis3dh_lir_int1_t *val) { lis3dh_ctrl_reg5_t ctrl_reg5; @@ -1816,7 +1826,7 @@ int32_t lis3dh_int1_pin_notification_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_pin_int2_config_set(stmdev_ctx_t *ctx, +int32_t lis3dh_pin_int2_config_set(const stmdev_ctx_t *ctx, lis3dh_ctrl_reg6_t *val) { int32_t ret; @@ -1834,7 +1844,7 @@ int32_t lis3dh_pin_int2_config_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_pin_int2_config_get(stmdev_ctx_t *ctx, +int32_t lis3dh_pin_int2_config_get(const stmdev_ctx_t *ctx, lis3dh_ctrl_reg6_t *val) { int32_t ret; @@ -1863,7 +1873,7 @@ int32_t lis3dh_pin_int2_config_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_fifo_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dh_fifo_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dh_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1887,7 +1897,7 @@ int32_t lis3dh_fifo_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_fifo_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dh_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dh_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1906,7 +1916,7 @@ int32_t lis3dh_fifo_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dh_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg; int32_t ret; @@ -1932,7 +1942,7 @@ int32_t lis3dh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dh_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg; int32_t ret; @@ -1952,7 +1962,7 @@ int32_t lis3dh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_fifo_trigger_event_set(stmdev_ctx_t *ctx, +int32_t lis3dh_fifo_trigger_event_set(const stmdev_ctx_t *ctx, lis3dh_tr_t val) { lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg; @@ -1979,7 +1989,7 @@ int32_t lis3dh_fifo_trigger_event_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_fifo_trigger_event_get(stmdev_ctx_t *ctx, +int32_t lis3dh_fifo_trigger_event_get(const stmdev_ctx_t *ctx, lis3dh_tr_t *val) { lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg; @@ -2014,7 +2024,7 @@ int32_t lis3dh_fifo_trigger_event_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_fifo_mode_set(stmdev_ctx_t *ctx, lis3dh_fm_t val) +int32_t lis3dh_fifo_mode_set(const stmdev_ctx_t *ctx, lis3dh_fm_t val) { lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg; int32_t ret; @@ -2040,7 +2050,7 @@ int32_t lis3dh_fifo_mode_set(stmdev_ctx_t *ctx, lis3dh_fm_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_fifo_mode_get(stmdev_ctx_t *ctx, lis3dh_fm_t *val) +int32_t lis3dh_fifo_mode_get(const stmdev_ctx_t *ctx, lis3dh_fm_t *val) { lis3dh_fifo_ctrl_reg_t fifo_ctrl_reg; int32_t ret; @@ -2082,7 +2092,7 @@ int32_t lis3dh_fifo_mode_get(stmdev_ctx_t *ctx, lis3dh_fm_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lis3dh_fifo_status_get(const stmdev_ctx_t *ctx, lis3dh_fifo_src_reg_t *val) { int32_t ret; @@ -2099,7 +2109,7 @@ int32_t lis3dh_fifo_status_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dh_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dh_fifo_src_reg_t fifo_src_reg; int32_t ret; @@ -2118,7 +2128,7 @@ int32_t lis3dh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dh_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dh_fifo_src_reg_t fifo_src_reg; int32_t ret; @@ -2137,7 +2147,7 @@ int32_t lis3dh_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dh_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dh_fifo_src_reg_t fifo_src_reg; int32_t ret; @@ -2156,7 +2166,7 @@ int32_t lis3dh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dh_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dh_fifo_src_reg_t fifo_src_reg; int32_t ret; @@ -2188,7 +2198,7 @@ int32_t lis3dh_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_tap_conf_set(stmdev_ctx_t *ctx, +int32_t lis3dh_tap_conf_set(const stmdev_ctx_t *ctx, lis3dh_click_cfg_t *val) { int32_t ret; @@ -2206,7 +2216,7 @@ int32_t lis3dh_tap_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_tap_conf_get(stmdev_ctx_t *ctx, +int32_t lis3dh_tap_conf_get(const stmdev_ctx_t *ctx, lis3dh_click_cfg_t *val) { int32_t ret; @@ -2223,7 +2233,7 @@ int32_t lis3dh_tap_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_tap_source_get(stmdev_ctx_t *ctx, +int32_t lis3dh_tap_source_get(const stmdev_ctx_t *ctx, lis3dh_click_src_t *val) { int32_t ret; @@ -2241,7 +2251,7 @@ int32_t lis3dh_tap_source_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dh_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dh_click_ths_t click_ths; int32_t ret; @@ -2266,7 +2276,7 @@ int32_t lis3dh_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dh_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dh_click_ths_t click_ths; int32_t ret; @@ -2288,7 +2298,7 @@ int32_t lis3dh_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_tap_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis3dh_tap_notification_mode_set(const stmdev_ctx_t *ctx, lis3dh_lir_click_t val) { lis3dh_click_ths_t click_ths; @@ -2316,7 +2326,7 @@ int32_t lis3dh_tap_notification_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_tap_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis3dh_tap_notification_mode_get(const stmdev_ctx_t *ctx, lis3dh_lir_click_t *val) { lis3dh_click_ths_t click_ths; @@ -2352,7 +2362,7 @@ int32_t lis3dh_tap_notification_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dh_shock_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dh_time_limit_t time_limit; int32_t ret; @@ -2378,7 +2388,7 @@ int32_t lis3dh_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dh_shock_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dh_time_limit_t time_limit; int32_t ret; @@ -2400,7 +2410,7 @@ int32_t lis3dh_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dh_quiet_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dh_time_latency_t time_latency; int32_t ret; @@ -2429,7 +2439,7 @@ int32_t lis3dh_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dh_quiet_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dh_time_latency_t time_latency; int32_t ret; @@ -2452,7 +2462,7 @@ int32_t lis3dh_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dh_double_tap_timeout_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dh_time_window_t time_window; int32_t ret; @@ -2481,7 +2491,7 @@ int32_t lis3dh_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_double_tap_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dh_double_tap_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dh_time_window_t time_window; int32_t ret; @@ -2516,7 +2526,7 @@ int32_t lis3dh_double_tap_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dh_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dh_act_ths_t act_ths; int32_t ret; @@ -2542,7 +2552,7 @@ int32_t lis3dh_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dh_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dh_act_ths_t act_ths; int32_t ret; @@ -2562,7 +2572,7 @@ int32_t lis3dh_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dh_act_timeout_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dh_act_dur_t act_dur; int32_t ret; @@ -2587,7 +2597,7 @@ int32_t lis3dh_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dh_act_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dh_act_dur_t act_dur; int32_t ret; @@ -2619,7 +2629,7 @@ int32_t lis3dh_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_pin_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t lis3dh_pin_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, lis3dh_sdo_pu_disc_t val) { lis3dh_ctrl_reg0_t ctrl_reg0; @@ -2644,7 +2654,7 @@ int32_t lis3dh_pin_sdo_sa0_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_pin_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t lis3dh_pin_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, lis3dh_sdo_pu_disc_t *val) { lis3dh_ctrl_reg0_t ctrl_reg0; @@ -2678,7 +2688,7 @@ int32_t lis3dh_pin_sdo_sa0_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_spi_mode_set(stmdev_ctx_t *ctx, lis3dh_sim_t val) +int32_t lis3dh_spi_mode_set(const stmdev_ctx_t *ctx, lis3dh_sim_t val) { lis3dh_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -2702,7 +2712,7 @@ int32_t lis3dh_spi_mode_set(stmdev_ctx_t *ctx, lis3dh_sim_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3dh_spi_mode_get(stmdev_ctx_t *ctx, lis3dh_sim_t *val) +int32_t lis3dh_spi_mode_get(const stmdev_ctx_t *ctx, lis3dh_sim_t *val) { lis3dh_ctrl_reg4_t ctrl_reg4; int32_t ret; diff --git a/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.h b/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.h index cb8d478d..ada8f20a 100644 --- a/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.h +++ b/sensor/stmemsc/lis3dh_STdC/driver/lis3dh_reg.h @@ -229,11 +229,11 @@ typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t not_used_01 : 6; - uint8_t adc_pd : 1; uint8_t temp_en : 1; + uint8_t adc_pd : 1; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t temp_en : 1; uint8_t adc_pd : 1; + uint8_t temp_en : 1; uint8_t not_used_01 : 6; #endif /* DRV_BYTE_ORDER */ } lis3dh_temp_cfg_reg_t; @@ -731,9 +731,9 @@ typedef union * them with a custom implementation. */ -int32_t lis3dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, +int32_t lis3dh_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lis3dh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lis3dh_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -755,14 +755,14 @@ float_t lis3dh_from_fs8_lp_to_mg(int16_t lsb); float_t lis3dh_from_fs16_lp_to_mg(int16_t lsb); float_t lis3dh_from_lsb_lp_to_celsius(int16_t lsb); -int32_t lis3dh_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis3dh_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dh_temp_status_reg_get(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis3dh_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dh_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dh_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lis3dh_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lis3dh_adc_raw_get(stmdev_ctx_t *ctx, int16_t *buff); +int32_t lis3dh_adc_raw_get(const stmdev_ctx_t *ctx, int16_t *buff); typedef enum { @@ -770,8 +770,8 @@ typedef enum LIS3DH_AUX_ON_TEMPERATURE = 3, LIS3DH_AUX_ON_PADS = 1, } lis3dh_temp_en_t; -int32_t lis3dh_aux_adc_set(stmdev_ctx_t *ctx, lis3dh_temp_en_t val); -int32_t lis3dh_aux_adc_get(stmdev_ctx_t *ctx, lis3dh_temp_en_t *val); +int32_t lis3dh_aux_adc_set(const stmdev_ctx_t *ctx, lis3dh_temp_en_t val); +int32_t lis3dh_aux_adc_get(const stmdev_ctx_t *ctx, lis3dh_temp_en_t *val); typedef enum { @@ -779,9 +779,9 @@ typedef enum LIS3DH_NM_10bit = 1, LIS3DH_LP_8bit = 2, } lis3dh_op_md_t; -int32_t lis3dh_operating_mode_set(stmdev_ctx_t *ctx, +int32_t lis3dh_operating_mode_set(const stmdev_ctx_t *ctx, lis3dh_op_md_t val); -int32_t lis3dh_operating_mode_get(stmdev_ctx_t *ctx, +int32_t lis3dh_operating_mode_get(const stmdev_ctx_t *ctx, lis3dh_op_md_t *val); typedef enum @@ -797,12 +797,12 @@ typedef enum LIS3DH_ODR_1kHz620_LP = 0x08, LIS3DH_ODR_5kHz376_LP_1kHz344_NM_HP = 0x09, } lis3dh_odr_t; -int32_t lis3dh_data_rate_set(stmdev_ctx_t *ctx, lis3dh_odr_t val); -int32_t lis3dh_data_rate_get(stmdev_ctx_t *ctx, lis3dh_odr_t *val); +int32_t lis3dh_data_rate_set(const stmdev_ctx_t *ctx, lis3dh_odr_t val); +int32_t lis3dh_data_rate_get(const stmdev_ctx_t *ctx, lis3dh_odr_t *val); -int32_t lis3dh_high_pass_on_outputs_set(stmdev_ctx_t *ctx, +int32_t lis3dh_high_pass_on_outputs_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dh_high_pass_on_outputs_get(stmdev_ctx_t *ctx, +int32_t lis3dh_high_pass_on_outputs_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -812,9 +812,9 @@ typedef enum LIS3DH_MEDIUM = 2, LIS3DH_LIGHT = 3, } lis3dh_hpcf_t; -int32_t lis3dh_high_pass_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lis3dh_high_pass_bandwidth_set(const stmdev_ctx_t *ctx, lis3dh_hpcf_t val); -int32_t lis3dh_high_pass_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lis3dh_high_pass_bandwidth_get(const stmdev_ctx_t *ctx, lis3dh_hpcf_t *val); typedef enum @@ -824,9 +824,9 @@ typedef enum LIS3DH_NORMAL = 2, LIS3DH_AUTORST_ON_INT = 3, } lis3dh_hpm_t; -int32_t lis3dh_high_pass_mode_set(stmdev_ctx_t *ctx, +int32_t lis3dh_high_pass_mode_set(const stmdev_ctx_t *ctx, lis3dh_hpm_t val); -int32_t lis3dh_high_pass_mode_get(stmdev_ctx_t *ctx, +int32_t lis3dh_high_pass_mode_get(const stmdev_ctx_t *ctx, lis3dh_hpm_t *val); typedef enum @@ -836,22 +836,22 @@ typedef enum LIS3DH_8g = 2, LIS3DH_16g = 3, } lis3dh_fs_t; -int32_t lis3dh_full_scale_set(stmdev_ctx_t *ctx, lis3dh_fs_t val); -int32_t lis3dh_full_scale_get(stmdev_ctx_t *ctx, lis3dh_fs_t *val); +int32_t lis3dh_full_scale_set(const stmdev_ctx_t *ctx, lis3dh_fs_t val); +int32_t lis3dh_full_scale_get(const stmdev_ctx_t *ctx, lis3dh_fs_t *val); -int32_t lis3dh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dh_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dh_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dh_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis3dh_filter_reference_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis3dh_filter_reference_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis3dh_filter_reference_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis3dh_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dh_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dh_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dh_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dh_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lis3dh_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lis3dh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis3dh_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); typedef enum { @@ -859,52 +859,52 @@ typedef enum LIS3DH_ST_POSITIVE = 1, LIS3DH_ST_NEGATIVE = 2, } lis3dh_st_t; -int32_t lis3dh_self_test_set(stmdev_ctx_t *ctx, lis3dh_st_t val); -int32_t lis3dh_self_test_get(stmdev_ctx_t *ctx, lis3dh_st_t *val); +int32_t lis3dh_self_test_set(const stmdev_ctx_t *ctx, lis3dh_st_t val); +int32_t lis3dh_self_test_get(const stmdev_ctx_t *ctx, lis3dh_st_t *val); typedef enum { LIS3DH_LSB_AT_LOW_ADD = 0, LIS3DH_MSB_AT_LOW_ADD = 1, } lis3dh_ble_t; -int32_t lis3dh_data_format_set(stmdev_ctx_t *ctx, lis3dh_ble_t val); -int32_t lis3dh_data_format_get(stmdev_ctx_t *ctx, lis3dh_ble_t *val); +int32_t lis3dh_data_format_set(const stmdev_ctx_t *ctx, lis3dh_ble_t val); +int32_t lis3dh_data_format_get(const stmdev_ctx_t *ctx, lis3dh_ble_t *val); -int32_t lis3dh_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dh_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dh_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dh_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dh_status_get(stmdev_ctx_t *ctx, +int32_t lis3dh_status_get(const stmdev_ctx_t *ctx, lis3dh_status_reg_t *val); -int32_t lis3dh_int1_gen_conf_set(stmdev_ctx_t *ctx, +int32_t lis3dh_int1_gen_conf_set(const stmdev_ctx_t *ctx, lis3dh_int1_cfg_t *val); -int32_t lis3dh_int1_gen_conf_get(stmdev_ctx_t *ctx, +int32_t lis3dh_int1_gen_conf_get(const stmdev_ctx_t *ctx, lis3dh_int1_cfg_t *val); -int32_t lis3dh_int1_gen_source_get(stmdev_ctx_t *ctx, +int32_t lis3dh_int1_gen_source_get(const stmdev_ctx_t *ctx, lis3dh_int1_src_t *val); -int32_t lis3dh_int1_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dh_int1_gen_threshold_get(stmdev_ctx_t *ctx, +int32_t lis3dh_int1_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dh_int1_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dh_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dh_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dh_int1_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dh_int1_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dh_int2_gen_conf_set(stmdev_ctx_t *ctx, +int32_t lis3dh_int2_gen_conf_set(const stmdev_ctx_t *ctx, lis3dh_int2_cfg_t *val); -int32_t lis3dh_int2_gen_conf_get(stmdev_ctx_t *ctx, +int32_t lis3dh_int2_gen_conf_get(const stmdev_ctx_t *ctx, lis3dh_int2_cfg_t *val); -int32_t lis3dh_int2_gen_source_get(stmdev_ctx_t *ctx, +int32_t lis3dh_int2_gen_source_get(const stmdev_ctx_t *ctx, lis3dh_int2_src_t *val); -int32_t lis3dh_int2_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dh_int2_gen_threshold_get(stmdev_ctx_t *ctx, +int32_t lis3dh_int2_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dh_int2_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dh_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dh_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dh_int2_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dh_int2_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -917,18 +917,18 @@ typedef enum LIS3DH_ON_INT2_TAP_GEN = 6, LIS3DH_ON_INT1_INT2_TAP_GEN = 7, } lis3dh_hp_t; -int32_t lis3dh_high_pass_int_conf_set(stmdev_ctx_t *ctx, +int32_t lis3dh_high_pass_int_conf_set(const stmdev_ctx_t *ctx, lis3dh_hp_t val); -int32_t lis3dh_high_pass_int_conf_get(stmdev_ctx_t *ctx, +int32_t lis3dh_high_pass_int_conf_get(const stmdev_ctx_t *ctx, lis3dh_hp_t *val); -int32_t lis3dh_pin_int1_config_set(stmdev_ctx_t *ctx, +int32_t lis3dh_pin_int1_config_set(const stmdev_ctx_t *ctx, lis3dh_ctrl_reg3_t *val); -int32_t lis3dh_pin_int1_config_get(stmdev_ctx_t *ctx, +int32_t lis3dh_pin_int1_config_get(const stmdev_ctx_t *ctx, lis3dh_ctrl_reg3_t *val); -int32_t lis3dh_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dh_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, +int32_t lis3dh_int2_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dh_int2_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -936,13 +936,13 @@ typedef enum LIS3DH_INT2_PULSED = 0, LIS3DH_INT2_LATCHED = 1, } lis3dh_lir_int2_t; -int32_t lis3dh_int2_pin_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis3dh_int2_pin_notification_mode_set(const stmdev_ctx_t *ctx, lis3dh_lir_int2_t val); -int32_t lis3dh_int2_pin_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis3dh_int2_pin_notification_mode_get(const stmdev_ctx_t *ctx, lis3dh_lir_int2_t *val); -int32_t lis3dh_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dh_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, +int32_t lis3dh_int1_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dh_int1_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -950,30 +950,30 @@ typedef enum LIS3DH_INT1_PULSED = 0, LIS3DH_INT1_LATCHED = 1, } lis3dh_lir_int1_t; -int32_t lis3dh_int1_pin_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis3dh_int1_pin_notification_mode_set(const stmdev_ctx_t *ctx, lis3dh_lir_int1_t val); -int32_t lis3dh_int1_pin_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis3dh_int1_pin_notification_mode_get(const stmdev_ctx_t *ctx, lis3dh_lir_int1_t *val); -int32_t lis3dh_pin_int2_config_set(stmdev_ctx_t *ctx, +int32_t lis3dh_pin_int2_config_set(const stmdev_ctx_t *ctx, lis3dh_ctrl_reg6_t *val); -int32_t lis3dh_pin_int2_config_get(stmdev_ctx_t *ctx, +int32_t lis3dh_pin_int2_config_get(const stmdev_ctx_t *ctx, lis3dh_ctrl_reg6_t *val); -int32_t lis3dh_fifo_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dh_fifo_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dh_fifo_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dh_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dh_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dh_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LIS3DH_INT1_GEN = 0, LIS3DH_INT2_GEN = 1, } lis3dh_tr_t; -int32_t lis3dh_fifo_trigger_event_set(stmdev_ctx_t *ctx, +int32_t lis3dh_fifo_trigger_event_set(const stmdev_ctx_t *ctx, lis3dh_tr_t val); -int32_t lis3dh_fifo_trigger_event_get(stmdev_ctx_t *ctx, +int32_t lis3dh_fifo_trigger_event_get(const stmdev_ctx_t *ctx, lis3dh_tr_t *val); typedef enum @@ -983,65 +983,65 @@ typedef enum LIS3DH_DYNAMIC_STREAM_MODE = 2, LIS3DH_STREAM_TO_FIFO_MODE = 3, } lis3dh_fm_t; -int32_t lis3dh_fifo_mode_set(stmdev_ctx_t *ctx, lis3dh_fm_t val); -int32_t lis3dh_fifo_mode_get(stmdev_ctx_t *ctx, lis3dh_fm_t *val); +int32_t lis3dh_fifo_mode_set(const stmdev_ctx_t *ctx, lis3dh_fm_t val); +int32_t lis3dh_fifo_mode_get(const stmdev_ctx_t *ctx, lis3dh_fm_t *val); -int32_t lis3dh_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lis3dh_fifo_status_get(const stmdev_ctx_t *ctx, lis3dh_fifo_src_reg_t *val); -int32_t lis3dh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dh_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dh_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dh_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dh_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dh_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dh_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dh_tap_conf_set(stmdev_ctx_t *ctx, +int32_t lis3dh_tap_conf_set(const stmdev_ctx_t *ctx, lis3dh_click_cfg_t *val); -int32_t lis3dh_tap_conf_get(stmdev_ctx_t *ctx, +int32_t lis3dh_tap_conf_get(const stmdev_ctx_t *ctx, lis3dh_click_cfg_t *val); -int32_t lis3dh_tap_source_get(stmdev_ctx_t *ctx, +int32_t lis3dh_tap_source_get(const stmdev_ctx_t *ctx, lis3dh_click_src_t *val); -int32_t lis3dh_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dh_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dh_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dh_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LIS3DH_TAP_PULSED = 0, LIS3DH_TAP_LATCHED = 1, } lis3dh_lir_click_t; -int32_t lis3dh_tap_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis3dh_tap_notification_mode_set(const stmdev_ctx_t *ctx, lis3dh_lir_click_t val); -int32_t lis3dh_tap_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis3dh_tap_notification_mode_get(const stmdev_ctx_t *ctx, lis3dh_lir_click_t *val); -int32_t lis3dh_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dh_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dh_shock_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dh_shock_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dh_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dh_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dh_quiet_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dh_quiet_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dh_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dh_double_tap_timeout_get(stmdev_ctx_t *ctx, +int32_t lis3dh_double_tap_timeout_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dh_double_tap_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dh_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dh_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dh_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dh_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dh_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dh_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dh_act_timeout_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dh_act_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { - LIS3DH_PULL_UP_DISCONNECT = 0, - LIS3DH_PULL_UP_CONNECT = 1, + LIS3DH_PULL_UP_CONNECT = 0, + LIS3DH_PULL_UP_DISCONNECT = 1, } lis3dh_sdo_pu_disc_t; -int32_t lis3dh_pin_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t lis3dh_pin_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, lis3dh_sdo_pu_disc_t val); -int32_t lis3dh_pin_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t lis3dh_pin_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, lis3dh_sdo_pu_disc_t *val); typedef enum @@ -1049,8 +1049,8 @@ typedef enum LIS3DH_SPI_4_WIRE = 0, LIS3DH_SPI_3_WIRE = 1, } lis3dh_sim_t; -int32_t lis3dh_spi_mode_set(stmdev_ctx_t *ctx, lis3dh_sim_t val); -int32_t lis3dh_spi_mode_get(stmdev_ctx_t *ctx, lis3dh_sim_t *val); +int32_t lis3dh_spi_mode_set(const stmdev_ctx_t *ctx, lis3dh_sim_t val); +int32_t lis3dh_spi_mode_get(const stmdev_ctx_t *ctx, lis3dh_sim_t *val); /** * @} diff --git a/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.c b/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.c index 9fc7aab4..5572d150 100644 --- a/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.c +++ b/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis3dhh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lis3dhh_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lis3dhh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis3dhh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lis3dhh_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -121,7 +131,7 @@ float_t lis3dhh_from_lsb_to_celsius(int16_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dhh_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dhh_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -145,7 +155,7 @@ int32_t lis3dhh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dhh_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dhh_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -164,7 +174,7 @@ int32_t lis3dhh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_data_rate_set(stmdev_ctx_t *ctx, +int32_t lis3dhh_data_rate_set(const stmdev_ctx_t *ctx, lis3dhh_norm_mod_en_t val) { lis3dhh_ctrl_reg1_t ctrl_reg1; @@ -189,7 +199,7 @@ int32_t lis3dhh_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_data_rate_get(stmdev_ctx_t *ctx, +int32_t lis3dhh_data_rate_get(const stmdev_ctx_t *ctx, lis3dhh_norm_mod_en_t *val) { lis3dhh_ctrl_reg1_t ctrl_reg1; @@ -223,7 +233,7 @@ int32_t lis3dhh_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lis3dhh_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -243,7 +253,7 @@ int32_t lis3dhh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lis3dhh_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -267,7 +277,7 @@ int32_t lis3dhh_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dhh_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dhh_status_t status; int32_t ret; @@ -286,7 +296,7 @@ int32_t lis3dhh_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dhh_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dhh_status_t status; int32_t ret; @@ -317,7 +327,7 @@ int32_t lis3dhh_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis3dhh_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -334,7 +344,7 @@ int32_t lis3dhh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dhh_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dhh_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -358,7 +368,7 @@ int32_t lis3dhh_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dhh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dhh_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -377,7 +387,7 @@ int32_t lis3dhh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dhh_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dhh_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -401,7 +411,7 @@ int32_t lis3dhh_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dhh_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dhh_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -420,7 +430,7 @@ int32_t lis3dhh_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_self_test_set(stmdev_ctx_t *ctx, lis3dhh_st_t val) +int32_t lis3dhh_self_test_set(const stmdev_ctx_t *ctx, lis3dhh_st_t val) { lis3dhh_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -444,7 +454,7 @@ int32_t lis3dhh_self_test_set(stmdev_ctx_t *ctx, lis3dhh_st_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_self_test_get(stmdev_ctx_t *ctx, lis3dhh_st_t *val) +int32_t lis3dhh_self_test_get(const stmdev_ctx_t *ctx, lis3dhh_st_t *val) { lis3dhh_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -481,7 +491,7 @@ int32_t lis3dhh_self_test_get(stmdev_ctx_t *ctx, lis3dhh_st_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_filter_config_set(stmdev_ctx_t *ctx, +int32_t lis3dhh_filter_config_set(const stmdev_ctx_t *ctx, lis3dhh_dsp_t val) { lis3dhh_ctrl_reg4_t ctrl_reg4; @@ -506,7 +516,7 @@ int32_t lis3dhh_filter_config_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_filter_config_get(stmdev_ctx_t *ctx, +int32_t lis3dhh_filter_config_get(const stmdev_ctx_t *ctx, lis3dhh_dsp_t *val) { lis3dhh_ctrl_reg4_t ctrl_reg4; @@ -548,7 +558,7 @@ int32_t lis3dhh_filter_config_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_status_get(stmdev_ctx_t *ctx, lis3dhh_status_t *val) +int32_t lis3dhh_status_get(const stmdev_ctx_t *ctx, lis3dhh_status_t *val) { int32_t ret; @@ -577,7 +587,7 @@ int32_t lis3dhh_status_get(stmdev_ctx_t *ctx, lis3dhh_status_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_drdy_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis3dhh_drdy_notification_mode_set(const stmdev_ctx_t *ctx, lis3dhh_drdy_pulse_t val) { lis3dhh_ctrl_reg1_t ctrl_reg1; @@ -602,7 +612,7 @@ int32_t lis3dhh_drdy_notification_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_drdy_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis3dhh_drdy_notification_mode_get(const stmdev_ctx_t *ctx, lis3dhh_drdy_pulse_t *val) { lis3dhh_ctrl_reg1_t ctrl_reg1; @@ -637,7 +647,7 @@ int32_t lis3dhh_drdy_notification_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_int1_mode_set(stmdev_ctx_t *ctx, +int32_t lis3dhh_int1_mode_set(const stmdev_ctx_t *ctx, lis3dhh_int1_ext_t val) { lis3dhh_int1_ctrl_t int1_ctrl; @@ -663,7 +673,7 @@ int32_t lis3dhh_int1_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_int1_mode_get(stmdev_ctx_t *ctx, +int32_t lis3dhh_int1_mode_get(const stmdev_ctx_t *ctx, lis3dhh_int1_ext_t *val) { lis3dhh_int1_ctrl_t int1_ctrl; @@ -697,7 +707,7 @@ int32_t lis3dhh_int1_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_fifo_threshold_on_int1_set(stmdev_ctx_t *ctx, +int32_t lis3dhh_fifo_threshold_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dhh_int1_ctrl_t int1_ctrl; @@ -722,7 +732,7 @@ int32_t lis3dhh_fifo_threshold_on_int1_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_fifo_threshold_on_int1_get(stmdev_ctx_t *ctx, +int32_t lis3dhh_fifo_threshold_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dhh_int1_ctrl_t int1_ctrl; @@ -742,7 +752,7 @@ int32_t lis3dhh_fifo_threshold_on_int1_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_fifo_full_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dhh_fifo_full_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dhh_int1_ctrl_t int1_ctrl; int32_t ret; @@ -766,7 +776,7 @@ int32_t lis3dhh_fifo_full_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_fifo_full_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dhh_fifo_full_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dhh_int1_ctrl_t int1_ctrl; int32_t ret; @@ -785,7 +795,7 @@ int32_t lis3dhh_fifo_full_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_fifo_ovr_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dhh_fifo_ovr_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dhh_int1_ctrl_t int1_ctrl; int32_t ret; @@ -809,7 +819,7 @@ int32_t lis3dhh_fifo_ovr_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_fifo_ovr_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dhh_fifo_ovr_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dhh_int1_ctrl_t int1_ctrl; int32_t ret; @@ -828,7 +838,7 @@ int32_t lis3dhh_fifo_ovr_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_boot_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dhh_boot_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dhh_int1_ctrl_t int1_ctrl; int32_t ret; @@ -852,7 +862,7 @@ int32_t lis3dhh_boot_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_boot_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dhh_boot_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dhh_int1_ctrl_t int1_ctrl; int32_t ret; @@ -871,7 +881,7 @@ int32_t lis3dhh_boot_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dhh_drdy_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dhh_int1_ctrl_t int1_ctrl; int32_t ret; @@ -895,7 +905,7 @@ int32_t lis3dhh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dhh_drdy_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dhh_int1_ctrl_t int1_ctrl; int32_t ret; @@ -914,7 +924,7 @@ int32_t lis3dhh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_fifo_threshold_on_int2_set(stmdev_ctx_t *ctx, +int32_t lis3dhh_fifo_threshold_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dhh_int2_ctrl_t int2_ctrl; @@ -939,7 +949,7 @@ int32_t lis3dhh_fifo_threshold_on_int2_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_fifo_threshold_on_int2_get(stmdev_ctx_t *ctx, +int32_t lis3dhh_fifo_threshold_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dhh_int2_ctrl_t int2_ctrl; @@ -959,7 +969,7 @@ int32_t lis3dhh_fifo_threshold_on_int2_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_fifo_full_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dhh_fifo_full_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dhh_int2_ctrl_t int2_ctrl; int32_t ret; @@ -983,7 +993,7 @@ int32_t lis3dhh_fifo_full_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_fifo_full_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dhh_fifo_full_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dhh_int2_ctrl_t int2_ctrl; int32_t ret; @@ -1002,7 +1012,7 @@ int32_t lis3dhh_fifo_full_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_fifo_ovr_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dhh_fifo_ovr_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dhh_int2_ctrl_t int2_ctrl; int32_t ret; @@ -1026,7 +1036,7 @@ int32_t lis3dhh_fifo_ovr_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_fifo_ovr_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dhh_fifo_ovr_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dhh_int2_ctrl_t int2_ctrl; int32_t ret; @@ -1045,7 +1055,7 @@ int32_t lis3dhh_fifo_ovr_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_boot_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dhh_boot_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dhh_int2_ctrl_t int2_ctrl; int32_t ret; @@ -1069,7 +1079,7 @@ int32_t lis3dhh_boot_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_boot_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dhh_boot_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dhh_int2_ctrl_t int2_ctrl; int32_t ret; @@ -1088,7 +1098,7 @@ int32_t lis3dhh_boot_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dhh_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dhh_int2_ctrl_t int2_ctrl; int32_t ret; @@ -1112,7 +1122,7 @@ int32_t lis3dhh_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dhh_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dhh_int2_ctrl_t int2_ctrl; int32_t ret; @@ -1131,7 +1141,7 @@ int32_t lis3dhh_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_pin_mode_set(stmdev_ctx_t *ctx, lis3dhh_pp_od_t val) +int32_t lis3dhh_pin_mode_set(const stmdev_ctx_t *ctx, lis3dhh_pp_od_t val) { lis3dhh_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -1155,7 +1165,7 @@ int32_t lis3dhh_pin_mode_set(stmdev_ctx_t *ctx, lis3dhh_pp_od_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_pin_mode_get(stmdev_ctx_t *ctx, lis3dhh_pp_od_t *val) +int32_t lis3dhh_pin_mode_get(const stmdev_ctx_t *ctx, lis3dhh_pp_od_t *val) { lis3dhh_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -1209,7 +1219,7 @@ int32_t lis3dhh_pin_mode_get(stmdev_ctx_t *ctx, lis3dhh_pp_od_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_fifo_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dhh_fifo_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dhh_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -1233,7 +1243,7 @@ int32_t lis3dhh_fifo_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_fifo_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dhh_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dhh_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -1255,7 +1265,7 @@ int32_t lis3dhh_fifo_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_fifo_block_spi_hs_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dhh_fifo_block_spi_hs_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dhh_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1282,7 +1292,7 @@ int32_t lis3dhh_fifo_block_spi_hs_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_fifo_block_spi_hs_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dhh_fifo_block_spi_hs_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dhh_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -1301,7 +1311,7 @@ int32_t lis3dhh_fifo_block_spi_hs_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dhh_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dhh_fifo_ctrl_t fifo_ctrl; int32_t ret; @@ -1325,7 +1335,7 @@ int32_t lis3dhh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dhh_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dhh_fifo_ctrl_t fifo_ctrl; int32_t ret; @@ -1344,7 +1354,7 @@ int32_t lis3dhh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_fifo_mode_set(stmdev_ctx_t *ctx, lis3dhh_fmode_t val) +int32_t lis3dhh_fifo_mode_set(const stmdev_ctx_t *ctx, lis3dhh_fmode_t val) { lis3dhh_fifo_ctrl_t fifo_ctrl; int32_t ret; @@ -1368,7 +1378,7 @@ int32_t lis3dhh_fifo_mode_set(stmdev_ctx_t *ctx, lis3dhh_fmode_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_fifo_mode_get(stmdev_ctx_t *ctx, lis3dhh_fmode_t *val) +int32_t lis3dhh_fifo_mode_get(const stmdev_ctx_t *ctx, lis3dhh_fmode_t *val) { lis3dhh_fifo_ctrl_t fifo_ctrl; int32_t ret; @@ -1413,7 +1423,7 @@ int32_t lis3dhh_fifo_mode_get(stmdev_ctx_t *ctx, lis3dhh_fmode_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lis3dhh_fifo_status_get(const stmdev_ctx_t *ctx, lis3dhh_fifo_src_t *val) { int32_t ret; @@ -1431,7 +1441,7 @@ int32_t lis3dhh_fifo_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dhh_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dhh_fifo_src_t fifo_src; int32_t ret; @@ -1450,7 +1460,7 @@ int32_t lis3dhh_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dhh_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dhh_fifo_src_t fifo_src; int32_t ret; @@ -1469,7 +1479,7 @@ int32_t lis3dhh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dhh_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dhh_fifo_src_t fifo_src; int32_t ret; @@ -1502,7 +1512,7 @@ int32_t lis3dhh_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_auto_add_inc_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3dhh_auto_add_inc_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3dhh_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -1527,7 +1537,7 @@ int32_t lis3dhh_auto_add_inc_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lis3dhh_auto_add_inc_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3dhh_auto_add_inc_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3dhh_ctrl_reg1_t ctrl_reg1; int32_t ret; diff --git a/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.h b/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.h index 543b6033..3a0dc236 100644 --- a/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.h +++ b/sensor/stmemsc/lis3dhh_STdC/driver/lis3dhh_reg.h @@ -373,18 +373,18 @@ typedef union * them with a custom implementation. */ -int32_t lis3dhh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lis3dhh_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lis3dhh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lis3dhh_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); float_t lis3dhh_from_lsb_to_mg(int16_t lsb); float_t lis3dhh_from_lsb_to_celsius(int16_t lsb); -int32_t lis3dhh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dhh_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lis3dhh_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dhh_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -392,25 +392,25 @@ typedef enum LIS3DHH_POWER_DOWN = 0, LIS3DHH_1kHz1 = 1, } lis3dhh_norm_mod_en_t; -int32_t lis3dhh_data_rate_set(stmdev_ctx_t *ctx, +int32_t lis3dhh_data_rate_set(const stmdev_ctx_t *ctx, lis3dhh_norm_mod_en_t val); -int32_t lis3dhh_data_rate_get(stmdev_ctx_t *ctx, +int32_t lis3dhh_data_rate_get(const stmdev_ctx_t *ctx, lis3dhh_norm_mod_en_t *val); -int32_t lis3dhh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); -int32_t lis3dhh_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lis3dhh_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); +int32_t lis3dhh_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lis3dhh_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dhh_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dhh_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dhh_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dhh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis3dhh_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis3dhh_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dhh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dhh_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dhh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dhh_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dhh_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dhh_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dhh_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -418,8 +418,8 @@ typedef enum LIS3DHH_ST_POSITIVE = 1, LIS3DHH_ST_NEGATIVE = 2, } lis3dhh_st_t; -int32_t lis3dhh_self_test_set(stmdev_ctx_t *ctx, lis3dhh_st_t val); -int32_t lis3dhh_self_test_get(stmdev_ctx_t *ctx, lis3dhh_st_t *val); +int32_t lis3dhh_self_test_set(const stmdev_ctx_t *ctx, lis3dhh_st_t val); +int32_t lis3dhh_self_test_get(const stmdev_ctx_t *ctx, lis3dhh_st_t *val); typedef enum { @@ -428,21 +428,21 @@ typedef enum LIS3DHH_NO_LINEAR_PHASE_440Hz = 2, LIS3DHH_NO_LINEAR_PHASE_235Hz = 3, } lis3dhh_dsp_t; -int32_t lis3dhh_filter_config_set(stmdev_ctx_t *ctx, +int32_t lis3dhh_filter_config_set(const stmdev_ctx_t *ctx, lis3dhh_dsp_t val); -int32_t lis3dhh_filter_config_get(stmdev_ctx_t *ctx, +int32_t lis3dhh_filter_config_get(const stmdev_ctx_t *ctx, lis3dhh_dsp_t *val); -int32_t lis3dhh_status_get(stmdev_ctx_t *ctx, lis3dhh_status_t *val); +int32_t lis3dhh_status_get(const stmdev_ctx_t *ctx, lis3dhh_status_t *val); typedef enum { LIS3DHH_LATCHED = 0, LIS3DHH_PULSED = 1, } lis3dhh_drdy_pulse_t; -int32_t lis3dhh_drdy_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis3dhh_drdy_notification_mode_set(const stmdev_ctx_t *ctx, lis3dhh_drdy_pulse_t val); -int32_t lis3dhh_drdy_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis3dhh_drdy_notification_mode_get(const stmdev_ctx_t *ctx, lis3dhh_drdy_pulse_t *val); @@ -451,47 +451,47 @@ typedef enum LIS3DHH_PIN_AS_INTERRUPT = 0, LIS3DHH_PIN_AS_TRIGGER = 1, } lis3dhh_int1_ext_t; -int32_t lis3dhh_int1_mode_set(stmdev_ctx_t *ctx, +int32_t lis3dhh_int1_mode_set(const stmdev_ctx_t *ctx, lis3dhh_int1_ext_t val); -int32_t lis3dhh_int1_mode_get(stmdev_ctx_t *ctx, +int32_t lis3dhh_int1_mode_get(const stmdev_ctx_t *ctx, lis3dhh_int1_ext_t *val); -int32_t lis3dhh_fifo_threshold_on_int1_set(stmdev_ctx_t *ctx, +int32_t lis3dhh_fifo_threshold_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dhh_fifo_threshold_on_int1_get(stmdev_ctx_t *ctx, +int32_t lis3dhh_fifo_threshold_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dhh_fifo_full_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dhh_fifo_full_on_int1_get(stmdev_ctx_t *ctx, +int32_t lis3dhh_fifo_full_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dhh_fifo_full_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dhh_fifo_ovr_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dhh_fifo_ovr_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dhh_fifo_ovr_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dhh_fifo_ovr_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dhh_boot_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dhh_boot_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dhh_boot_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dhh_boot_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dhh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dhh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dhh_drdy_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dhh_drdy_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dhh_fifo_threshold_on_int2_set(stmdev_ctx_t *ctx, +int32_t lis3dhh_fifo_threshold_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dhh_fifo_threshold_on_int2_get(stmdev_ctx_t *ctx, +int32_t lis3dhh_fifo_threshold_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dhh_fifo_full_on_int2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dhh_fifo_full_on_int2_get(stmdev_ctx_t *ctx, +int32_t lis3dhh_fifo_full_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dhh_fifo_full_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dhh_fifo_ovr_on_int2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dhh_fifo_ovr_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dhh_fifo_ovr_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dhh_fifo_ovr_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dhh_boot_on_int2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dhh_boot_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dhh_boot_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dhh_boot_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dhh_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dhh_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dhh_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dhh_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -500,18 +500,18 @@ typedef enum LIS3DHH_INT1_PP_INT2_OD = 2, LIS3DHH_ALL_OPEN_DRAIN = 3, } lis3dhh_pp_od_t; -int32_t lis3dhh_pin_mode_set(stmdev_ctx_t *ctx, lis3dhh_pp_od_t val); -int32_t lis3dhh_pin_mode_get(stmdev_ctx_t *ctx, lis3dhh_pp_od_t *val); +int32_t lis3dhh_pin_mode_set(const stmdev_ctx_t *ctx, lis3dhh_pp_od_t val); +int32_t lis3dhh_pin_mode_get(const stmdev_ctx_t *ctx, lis3dhh_pp_od_t *val); -int32_t lis3dhh_fifo_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dhh_fifo_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dhh_fifo_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dhh_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dhh_fifo_block_spi_hs_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dhh_fifo_block_spi_hs_get(stmdev_ctx_t *ctx, +int32_t lis3dhh_fifo_block_spi_hs_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dhh_fifo_block_spi_hs_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dhh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dhh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dhh_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dhh_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -521,21 +521,21 @@ typedef enum LIS3DHH_BYPASS_TO_STREAM_MODE = 4, LIS3DHH_DYNAMIC_STREAM_MODE = 6, } lis3dhh_fmode_t; -int32_t lis3dhh_fifo_mode_set(stmdev_ctx_t *ctx, lis3dhh_fmode_t val); -int32_t lis3dhh_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lis3dhh_fifo_mode_set(const stmdev_ctx_t *ctx, lis3dhh_fmode_t val); +int32_t lis3dhh_fifo_mode_get(const stmdev_ctx_t *ctx, lis3dhh_fmode_t *val); -int32_t lis3dhh_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lis3dhh_fifo_status_get(const stmdev_ctx_t *ctx, lis3dhh_fifo_src_t *val); -int32_t lis3dhh_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dhh_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dhh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dhh_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dhh_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dhh_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3dhh_auto_add_inc_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3dhh_auto_add_inc_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3dhh_auto_add_inc_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3dhh_auto_add_inc_get(const stmdev_ctx_t *ctx, uint8_t *val); /** *@} diff --git a/sensor/stmemsc/lis3dsh_STdC/driver/lis3dsh_reg.c b/sensor/stmemsc/lis3dsh_STdC/driver/lis3dsh_reg.c deleted file mode 100644 index c8a97207..00000000 --- a/sensor/stmemsc/lis3dsh_STdC/driver/lis3dsh_reg.c +++ /dev/null @@ -1,881 +0,0 @@ -/** - ****************************************************************************** - * @file lis3dsh_reg.c - * @author Sensors Software Solution Team - * @brief LIS3DSH driver file - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -#include "lis3dsh_reg.h" - -/** - * @defgroup LIS3DSH - * @brief This file provides a set of functions needed to drive the - * lis3dsh enhanced inertial module. - * @{ - * - */ - -/** - * @defgroup LIS3DSH_Interfaces_Functions - * @brief This section provide a set of functions used to read and - * write a generic register of the device. - * MANDATORY: return 0 -> no Error. - * @{ - * - */ - -/** - * @brief Read generic device register - * - * @param ctx communication interface handler.(ptr) - * @param reg first register address to read. - * @param data buffer for data read.(ptr) - * @param len number of consecutive register to read. - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t __weak lis3dsh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) -{ - int32_t ret; - - ret = ctx->read_reg(ctx->handle, reg, data, len); - - return ret; -} - -/** - * @brief Write generic device register - * - * @param ctx communication interface handler.(ptr) - * @param reg first register address to write. - * @param data the buffer contains data to be written.(ptr) - * @param len number of consecutive register to write. - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t __weak lis3dsh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) -{ - int32_t ret; - - ret = ctx->write_reg(ctx->handle, reg, data, len); - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LIS3DSH_Private_functions - * @brief Section collect all the utility functions needed by APIs. - * @{ - * - */ - -static void bytecpy(uint8_t *target, uint8_t *source) -{ - if ((target != NULL) && (source != NULL)) - { - *target = *source; - } -} - -/** - * @} - * - */ - -/** - * @defgroup LIS3DSH_Sensitivity - * @brief These functions convert raw-data into engineering units. - * @{ - * - */ -float_t lis3dsh_from_fs2_to_mg(int16_t lsb) -{ - return ((float_t)lsb) * 0.06f; -} - -float_t lis3dsh_from_fs4_to_mg(int16_t lsb) -{ - return ((float_t)lsb) * 0.12f; -} - -float_t lis3dsh_from_fs6_to_mg(int16_t lsb) -{ - return ((float_t)lsb) * 0.18f; -} - -float_t lis3dsh_from_fs8_to_mg(int16_t lsb) -{ - return ((float_t)lsb) * 0.24f; -} - -float_t lis3dsh_from_fs16_to_mg(int16_t lsb) -{ - return ((float_t)lsb) * 0.73f; -} - -float_t lis3dsh_from_lsb_to_celsius(int8_t lsb) -{ - return ((float_t)lsb + 25.0f); -} - -/** - * @} - * - */ - -/** - * @defgroup Basic configuration - * @brief This section groups all the functions concerning - * device basic configuration. - * @{ - * - */ - -/** - * @brief Device "Who am I".[get] - * - * @param ctx communication interface handler.(ptr) - * @param val ID values.(ptr) - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis3dsh_id_get(stmdev_ctx_t *ctx, lis3dsh_id_t *val) -{ - uint8_t reg[3]; - int32_t ret; - - ret = lis3dsh_read_reg(ctx, LIS3DSH_INFO1, reg, 3); - val->info1 = reg[0]; - val->info2 = reg[1]; - val->whoami = reg[2]; - - return ret; -} - -/** - * @brief Configures the bus operating mode.[set] - * - * @param ctx communication interface handler.(ptr) - * @param val configures the bus operating mode.(ptr) - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis3dsh_bus_mode_set(stmdev_ctx_t *ctx, - lis3dsh_bus_mode_t *val) -{ - lis3dsh_ctrl_reg5_t ctrl_reg5; - int32_t ret; - - ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); - - if (ret == 0) - { - ctrl_reg5.sim = (uint8_t) * val; - ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); - } - - return ret; -} - -/** - * @brief Get the bus operating mode.[get] - * - * @param ctx communication interface handler.(ptr) - * @param val retrieves the bus operating.(ptr) - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis3dsh_bus_mode_get(stmdev_ctx_t *ctx, - lis3dsh_bus_mode_t *val) -{ - lis3dsh_ctrl_reg5_t ctrl_reg5; - int32_t ret; - - ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); - - switch (ctrl_reg5.sim) - { - case LIS3DSH_SEL_BY_HW: - *val = LIS3DSH_SEL_BY_HW; - break; - - case LIS3DSH_SPI_3W: - *val = LIS3DSH_SPI_3W; - break; - - default: - *val = LIS3DSH_SEL_BY_HW; - break; - } - - return ret; -} - -/** - * @brief Re-initialize the device.[set] - * - * @param ctx communication interface handler.(ptr) - * @param val re-initialization mode. Refer to datasheet - * and application note for more information - * about differencies between boot and sw_reset - * procedure.(ptr) - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis3dsh_init_set(stmdev_ctx_t *ctx, lis3dsh_init_t val) -{ - lis3dsh_ctrl_reg3_t ctrl_reg3; - lis3dsh_ctrl_reg4_t ctrl_reg4; - lis3dsh_ctrl_reg6_t ctrl_reg6; - int32_t ret; - - - switch (val) - { - case LIS3DSH_BOOT: - ctrl_reg6.boot = (uint8_t)val & (uint8_t)LIS3DSH_BOOT; - ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - break; - - case LIS3DSH_RESET: - ctrl_reg3.strt = ((uint8_t)val & (uint8_t)LIS3DSH_RESET) >> 1; - ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG6, (uint8_t *)&ctrl_reg6, 1); - break; - - case LIS3DSH_DRV_RDY: - ctrl_reg4.xen = PROPERTY_ENABLE; - ctrl_reg4.yen = PROPERTY_ENABLE; - ctrl_reg4.zen = PROPERTY_ENABLE; - ctrl_reg4.bdu = PROPERTY_ENABLE; - ctrl_reg6.add_inc = PROPERTY_ENABLE; - ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); - - if (ret == 0) - { - ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG6, - (uint8_t *)&ctrl_reg6, 1); - } - - break; - - default: - ctrl_reg3.strt = ((uint8_t)val & (uint8_t)LIS3DSH_RESET) >> 1; - ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG6, (uint8_t *)&ctrl_reg6, 1); - break; - } - - return ret; -} - -/** - * @brief Get the status of the device.[get] - * - * @param ctx communication interface handler.(ptr) - * @param val the status of the device.(ptr) - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis3dsh_status_get(stmdev_ctx_t *ctx, - lis3dsh_status_var_t *val) -{ - lis3dsh_ctrl_reg3_t ctrl_reg3; - lis3dsh_ctrl_reg6_t ctrl_reg6; - lis3dsh_stat_t stat; - int32_t ret; - - ret = lis3dsh_read_reg(ctx, LIS3DSH_STAT, (uint8_t *)&stat, 1); - - if (ret == 0) - { - ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - } - - if (ret == 0) - { - ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG6, (uint8_t *)&ctrl_reg6, 1); - } - - val->sw_reset = ctrl_reg3.strt; - val->boot = ctrl_reg6.boot; - val->drdy_xl = stat.drdy; - val->ovrn_xl = stat.dor; - - return ret; -} - -/** - * @brief Interrupt pins hardware signal configuration.[set] - * - * @param ctx communication interface handler.(ptr) - * @param val the pins hardware signal settings.(ptr) - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis3dsh_interrupt_mode_set(stmdev_ctx_t *ctx, - lis3dsh_int_mode_t *val) -{ - lis3dsh_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - - if (ret == 0) - { - ctrl_reg3.iel = ~(val->latched); - ctrl_reg3.iea = ~(val->active_low); - ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - } - - return ret; -} - -/** - * @brief Interrupt pins hardware signal configuration.[get] - * - * @param ctx communication interface handler.(ptr) - * @param val the pins hardware signal settings.(ptr) - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis3dsh_interrupt_mode_get(stmdev_ctx_t *ctx, - lis3dsh_int_mode_t *val) -{ - lis3dsh_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - val->latched = ~(ctrl_reg3.iel); - val->active_low = ~(ctrl_reg3.iea); - - return ret; -} - -/** - * @brief Route interrupt signals on int1 pin.[set] - * - * @param ctx communication interface handler.(ptr) - * @param val the signals to route on int1 pin.(ptr) - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis3dsh_pin_int1_route_set(stmdev_ctx_t *ctx, - lis3dsh_pin_int1_route_t *val) -{ - lis3dsh_ctrl_reg1_t ctrl_reg1; - lis3dsh_ctrl_reg2_t ctrl_reg2; - lis3dsh_ctrl_reg3_t ctrl_reg3; - lis3dsh_ctrl_reg6_t ctrl_reg6; - uint8_t reg[5]; - int32_t ret; - - ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG1, (uint8_t *)®, 5); - bytecpy((uint8_t *)&ctrl_reg1, ®[0]); - bytecpy((uint8_t *)&ctrl_reg2, ®[1]); - bytecpy((uint8_t *)&ctrl_reg3, ®[2]); - bytecpy((uint8_t *)&ctrl_reg6, ®[4]); - ctrl_reg1.sm1_pin = ~(val->fsm1); - ctrl_reg2.sm2_pin = ~(val->fsm2); - ctrl_reg3.dr_en = val->drdy_xl; - ctrl_reg6.p1_wtm = val->fifo_th; - ctrl_reg6.p1_empty = val->fifo_empty; - ctrl_reg6.p1_overrun = val->fifo_full; - - if ((val->fsm1 | val->fsm2 | val->drdy_xl | - val->fifo_empty | val->fifo_th | - val->fifo_full) == PROPERTY_ENABLE) - { - ctrl_reg3.int1_en = PROPERTY_ENABLE; - } - - else - { - ctrl_reg3.int1_en = PROPERTY_DISABLE; - } - - bytecpy(®[0], (uint8_t *)&ctrl_reg1); - bytecpy(®[1], (uint8_t *)&ctrl_reg2); - bytecpy(®[2], (uint8_t *)&ctrl_reg3); - bytecpy(®[4], (uint8_t *)&ctrl_reg6); - - if (ret == 0) - { - ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG1, (uint8_t *)®, 5); - } - - return ret; -} - -/** - * @brief Route interrupt signals on int1 pin.[get] - * - * @param ctx communication interface handler.(ptr) - * @param val the signals that are routed on int1 pin.(ptr) - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis3dsh_pin_int1_route_get(stmdev_ctx_t *ctx, - lis3dsh_pin_int1_route_t *val) -{ - lis3dsh_ctrl_reg1_t ctrl_reg1; - lis3dsh_ctrl_reg2_t ctrl_reg2; - lis3dsh_ctrl_reg3_t ctrl_reg3; - lis3dsh_ctrl_reg6_t ctrl_reg6; - uint8_t reg[5]; - int32_t ret; - - ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG1, (uint8_t *)®, 5); - bytecpy((uint8_t *)&ctrl_reg1, ®[0]); - bytecpy((uint8_t *)&ctrl_reg2, ®[1]); - bytecpy((uint8_t *)&ctrl_reg3, ®[2]); - bytecpy((uint8_t *)&ctrl_reg6, ®[4]); - - if (ctrl_reg3.int1_en == PROPERTY_ENABLE) - { - val->fsm1 = ~(ctrl_reg1.sm1_pin); - val->fsm2 = ~(ctrl_reg2.sm2_pin); - val->drdy_xl = ctrl_reg3.dr_en; - val->fifo_th = ctrl_reg6.p1_wtm; - val->fifo_empty = ctrl_reg6.p1_empty; - val->fifo_full = ctrl_reg6.p1_overrun; - } - - else - { - val->fsm1 = PROPERTY_DISABLE; - val->fsm2 = PROPERTY_DISABLE; - val->drdy_xl = PROPERTY_DISABLE; - val->fifo_th = PROPERTY_DISABLE; - val->fifo_empty = PROPERTY_DISABLE; - val->fifo_full = PROPERTY_DISABLE; - } - - return ret; -} - -/** - * @brief Route interrupt signals on int2 pin.[set] - * - * @param ctx communication interface handler.(ptr) - * @param val the signals to route on int2 pin.(ptr) - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis3dsh_pin_int2_route_set(stmdev_ctx_t *ctx, - lis3dsh_pin_int2_route_t *val) -{ - lis3dsh_ctrl_reg1_t ctrl_reg1; - lis3dsh_ctrl_reg2_t ctrl_reg2; - lis3dsh_ctrl_reg3_t ctrl_reg3; - lis3dsh_ctrl_reg6_t ctrl_reg6; - uint8_t reg[5]; - int32_t ret; - - ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG1, (uint8_t *)®, 5); - bytecpy((uint8_t *)&ctrl_reg1, ®[0]); - bytecpy((uint8_t *)&ctrl_reg2, ®[1]); - bytecpy((uint8_t *)&ctrl_reg3, ®[2]); - bytecpy((uint8_t *)&ctrl_reg6, ®[4]); - ctrl_reg1.sm1_pin = val->fsm1; - ctrl_reg2.sm2_pin = val->fsm2; - ctrl_reg6.p2_boot = val->boot; - - if ((val->fsm1 | val->fsm2 | val->boot) == PROPERTY_ENABLE) - { - ctrl_reg3.int1_en = PROPERTY_ENABLE; - } - - else - { - ctrl_reg3.int1_en = PROPERTY_DISABLE; - } - - bytecpy(®[0], (uint8_t *)&ctrl_reg1); - bytecpy(®[1], (uint8_t *)&ctrl_reg2); - bytecpy(®[2], (uint8_t *)&ctrl_reg3); - bytecpy(®[4], (uint8_t *)&ctrl_reg6); - - if (ret == 0) - { - ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG1, (uint8_t *)®, 5); - } - - return ret; -} - -/** - * @brief Route interrupt signals on int2 pin.[get] - * - * @param ctx communication interface handler. Use NULL to ignore - * this interface.(ptr) - * @param aux_ctx auxiliary communication interface handler. Use NULL - * to ignore this interface.(ptr) - * @param val the signals that are routed on int2 pin.(ptr) - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis3dsh_pin_int2_route_get(stmdev_ctx_t *ctx, - lis3dsh_pin_int2_route_t *val) -{ - lis3dsh_ctrl_reg1_t ctrl_reg1; - lis3dsh_ctrl_reg2_t ctrl_reg2; - lis3dsh_ctrl_reg3_t ctrl_reg3; - lis3dsh_ctrl_reg6_t ctrl_reg6; - uint8_t reg[5]; - int32_t ret; - - ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG1, (uint8_t *)®, 5); - bytecpy((uint8_t *)&ctrl_reg1, ®[0]); - bytecpy((uint8_t *)&ctrl_reg2, ®[1]); - bytecpy((uint8_t *)&ctrl_reg3, ®[2]); - bytecpy((uint8_t *)&ctrl_reg6, ®[4]); - - if (ctrl_reg3.int1_en == PROPERTY_ENABLE) - { - val->fsm1 = ctrl_reg1.sm1_pin; - val->fsm2 = ctrl_reg2.sm2_pin; - val->boot = ctrl_reg6.p2_boot; - } - - else - { - val->fsm1 = PROPERTY_DISABLE; - val->fsm2 = PROPERTY_DISABLE; - val->boot = PROPERTY_DISABLE; - } - - return ret; -} - -/** - * @brief Get the status of all the interrupt sources.[get] - * - * @param ctx communication interface handler.(ptr) - * @param val the status of all the interrupt sources.(ptr) - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis3dsh_all_sources_get(stmdev_ctx_t *ctx, - lis3dsh_all_sources_t *val) -{ - lis3dsh_fifo_src_t fifo_src; - lis3dsh_stat_t stat; - int32_t ret; - - ret = lis3dsh_read_reg(ctx, LIS3DSH_STAT, (uint8_t *)&stat, 1); - - if (ret == 0) - { - ret = lis3dsh_read_reg(ctx, LIS3DSH_FIFO_SRC, (uint8_t *)&fifo_src, 1); - } - - val->drdy_xl = stat.drdy; - val->ovrn_xl = stat.dor; - val->fsm_lc = stat.l_count; - val->fsm_ext_sync = stat.syncw; - val->fsm1_wait_fsm2 = stat.sync1; - val->fsm2_wait_fsm1 = stat.sync2; - val->fsm1 = stat.int_sm1; - val->fsm2 = stat.int_sm2; - val->fifo_ovr = fifo_src.ovrn_fifo; - val->fifo_empty = fifo_src.empty; - val->fifo_full = fifo_src.ovrn_fifo; - val->fifo_th = fifo_src.wtm; - - return ret; -} - -/** - * @brief Sensor conversion parameters selection.[set] - * - * @param ctx communication interface handler.(ptr) - * @param val set the sensor conversion parameters by checking - * the constraints of the device.(ptr) - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis3dsh_mode_set(stmdev_ctx_t *ctx, lis3dsh_md_t *val) -{ - lis3dsh_ctrl_reg4_t ctrl_reg4; - lis3dsh_ctrl_reg5_t ctrl_reg5; - int32_t ret; - - ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); - - if (ret == 0) - { - ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); - } - - ctrl_reg4.odr = (uint8_t)val->odr; - ctrl_reg5.fscale = (uint8_t)val->fs; - - if (ret == 0) - { - ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); - } - - if (ret == 0) - { - ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); - } - - return ret; -} - -/** - * @brief Sensor conversion parameters selection.[get] - * - * @param ctx communication interface handler.(ptr) - * @param val get the sensor conversion parameters.(ptr) - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis3dsh_mode_get(stmdev_ctx_t *ctx, lis3dsh_md_t *val) -{ - lis3dsh_ctrl_reg4_t ctrl_reg4; - lis3dsh_ctrl_reg5_t ctrl_reg5; - int32_t ret; - - ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); - - if (ret == 0) - { - ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); - } - - switch (ctrl_reg4.odr) - { - case LIS3DSH_OFF: - val->odr = LIS3DSH_OFF; - break; - - case LIS3DSH_3Hz125: - val->odr = LIS3DSH_3Hz125; - break; - - case LIS3DSH_6Hz25: - val->odr = LIS3DSH_6Hz25; - break; - - case LIS3DSH_12Hz5: - val->odr = LIS3DSH_12Hz5; - break; - - case LIS3DSH_25Hz: - val->odr = LIS3DSH_25Hz; - break; - - case LIS3DSH_50Hz: - val->odr = LIS3DSH_50Hz; - break; - - case LIS3DSH_100Hz: - val->odr = LIS3DSH_100Hz; - break; - - case LIS3DSH_400Hz: - val->odr = LIS3DSH_400Hz; - break; - - case LIS3DSH_800Hz: - val->odr = LIS3DSH_800Hz; - break; - - case LIS3DSH_1kHz6: - val->odr = LIS3DSH_1kHz6; - break; - - default: - val->odr = LIS3DSH_OFF; - break; - } - - switch (ctrl_reg5.fscale) - { - case LIS3DSH_2g: - val->fs = LIS3DSH_2g; - break; - - case LIS3DSH_4g: - val->fs = LIS3DSH_4g; - break; - - case LIS3DSH_6g: - val->fs = LIS3DSH_6g; - break; - - case LIS3DSH_8g: - val->fs = LIS3DSH_8g; - break; - - case LIS3DSH_16g: - val->fs = LIS3DSH_16g; - break; - - default: - val->fs = LIS3DSH_2g; - break; - } - - return ret; -} - -/** - * @brief Read data in engineering unit.[get] - * - * @param ctx communication interface handler.(ptr) - * @param md the sensor conversion parameters.(ptr) - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis3dsh_data_get(stmdev_ctx_t *ctx, lis3dsh_md_t *md, - lis3dsh_data_t *data) -{ - uint8_t buff[6]; - int32_t ret; - - uint8_t i; - uint8_t j; - ret = lis3dsh_read_reg(ctx, LIS3DSH_OUT_T, (uint8_t *)&data->heat.raw, 1); - - if (ret == 0) - { - ret = lis3dsh_read_reg(ctx, LIS3DSH_OUT_X_L, (uint8_t *)&buff, 6); - } - - /* temperature conversion */ - data->heat.deg_c = lis3dsh_from_lsb_to_celsius(data->heat.raw); - /* acceleration conversion */ - j = 0U; - - for (i = 0U; i < 3U; i++) - { - data->xl.raw[i] = (int16_t)buff[j + 1U]; - data->xl.raw[i] = (data->xl.raw[i] * 256) + (int16_t) buff[j]; - j += 2U; - - switch (md->fs) - { - case LIS3DSH_2g: - data->xl.mg[i] = lis3dsh_from_fs2_to_mg(data->xl.raw[i]); - break; - - case LIS3DSH_4g: - data->xl.mg[i] = lis3dsh_from_fs4_to_mg(data->xl.raw[i]); - break; - - case LIS3DSH_6g: - data->xl.mg[i] = lis3dsh_from_fs6_to_mg(data->xl.raw[i]); - break; - - case LIS3DSH_8g: - data->xl.mg[i] = lis3dsh_from_fs8_to_mg(data->xl.raw[i]); - break; - - case LIS3DSH_16g: - data->xl.mg[i] = lis3dsh_from_fs16_to_mg(data->xl.raw[i]); - break; - - default: - data->xl.mg[i] = 0.0f; - break; - } - } - - return ret; -} - - -/** - * @} - * - */ - -/** - * @brief Configures the self test.[set] - * - * @param ctx communication interface handler.(ptr) - * @param val Self test mode mode.(ptr) - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis3dsh_self_test_set(stmdev_ctx_t *ctx, lis3dsh_st_t val) -{ - lis3dsh_ctrl_reg5_t ctrl_reg5; - int32_t ret; - - ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); - - if (ret == 0) - { - ctrl_reg5.st = (uint8_t) val; - ret = lis3dsh_write_reg(ctx, LIS3DSH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); - } - - return ret; -} - -/** - * @brief Get self test configuration.[set] - * - * @param ctx communication interface handler.(ptr) - * @param val Self test mode mode.(ptr) - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lis3dsh_self_test_get(stmdev_ctx_t *ctx, lis3dsh_st_t *val) -{ - lis3dsh_ctrl_reg5_t ctrl_reg5; - int32_t ret; - - ret = lis3dsh_read_reg(ctx, LIS3DSH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1); - - switch (ctrl_reg5.st) - { - case LIS3DSH_ST_DISABLE: - *val = LIS3DSH_ST_DISABLE; - break; - - case LIS3DSH_ST_POSITIVE: - *val = LIS3DSH_ST_POSITIVE; - break; - - case LIS3DSH_ST_NEGATIVE: - *val = LIS3DSH_ST_NEGATIVE; - break; - - default: - *val = LIS3DSH_ST_DISABLE; - break; - } - - return ret; -} - -/** - * @} - * - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis3dsh_STdC/driver/lis3dsh_reg.h b/sensor/stmemsc/lis3dsh_STdC/driver/lis3dsh_reg.h deleted file mode 100644 index 0aa1e384..00000000 --- a/sensor/stmemsc/lis3dsh_STdC/driver/lis3dsh_reg.h +++ /dev/null @@ -1,908 +0,0 @@ -/** - ****************************************************************************** - * @file lis3dsh_reg.h - * @author Sensors Software Solution Team - * @brief This file contains all the functions prototypes for the - * lis3dsh_reg.c driver. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef LIS3DSH_REGS_H -#define LIS3DSH_REGS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include -#include -#include - -/** @addtogroup LIS3DSH - * @{ - * - */ - -/** @defgroup Endianness definitions - * @{ - * - */ - -#ifndef DRV_BYTE_ORDER -#ifndef __BYTE_ORDER__ - -#define DRV_LITTLE_ENDIAN 1234 -#define DRV_BIG_ENDIAN 4321 - -/** if _BYTE_ORDER is not defined, choose the endianness of your architecture - * by uncommenting the define which fits your platform endianness - */ -//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN -#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN - -#else /* defined __BYTE_ORDER__ */ - -#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ -#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ -#define DRV_BYTE_ORDER __BYTE_ORDER__ - -#endif /* __BYTE_ORDER__*/ -#endif /* DRV_BYTE_ORDER */ - -/** - * @} - * - */ - -/** @defgroup STMicroelectronics sensors common types - * @{ - * - */ - -#ifndef MEMS_SHARED_TYPES -#define MEMS_SHARED_TYPES - -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t bit0 : 1; - uint8_t bit1 : 1; - uint8_t bit2 : 1; - uint8_t bit3 : 1; - uint8_t bit4 : 1; - uint8_t bit5 : 1; - uint8_t bit6 : 1; - uint8_t bit7 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t bit7 : 1; - uint8_t bit6 : 1; - uint8_t bit5 : 1; - uint8_t bit4 : 1; - uint8_t bit3 : 1; - uint8_t bit2 : 1; - uint8_t bit1 : 1; - uint8_t bit0 : 1; -#endif /* DRV_BYTE_ORDER */ -} bitwise_t; - -/** - * @} - * - */ - -#define PROPERTY_DISABLE (0U) -#define PROPERTY_ENABLE (1U) - -/** @addtogroup Interfaces_Functions - * @brief This section provide a set of functions used to read and - * write a generic register of the device. - * MANDATORY: return 0 -> no Error. - * @{ - * - */ - -typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); -typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); -typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); - -typedef struct -{ - /** Component mandatory fields **/ - stmdev_write_ptr write_reg; - stmdev_read_ptr read_reg; - /** Component optional fields **/ - stmdev_mdelay_ptr mdelay; - /** Customizable optional pointer **/ - void *handle; -} stmdev_ctx_t; - -/** - * @} - * - */ - -#endif /* MEMS_SHARED_TYPES */ - -#ifndef MEMS_UCF_SHARED_TYPES -#define MEMS_UCF_SHARED_TYPES - -/** @defgroup Generic address-data structure definition - * @brief This structure is useful to load a predefined configuration - * of a sensor. - * You can create a sensor configuration by your own or using - * Unico / Unicleo tools available on STMicroelectronics - * web site. - * - * @{ - * - */ - -typedef struct -{ - uint8_t address; - uint8_t data; -} ucf_line_t; - -/** - * @} - * - */ - -#endif /* MEMS_UCF_SHARED_TYPES */ - -/** - * @} - * - */ - -/** @defgroup LIS3DSH_Infos - * @{ - * - */ - -/** I2C Device Address 8 bit format if SA0=0 -> 3D if SA0=1 -> 3B **/ -#define LIS3DSH_I2C_ADD_L 0x3D -#define LIS3DSH_I2C_ADD_H 0x3B - -/** Device Identification (Who am I) **/ -#define LIS3DSH_ID 0x3F - -/** - * @} - * - */ - -#define LIS3DSH_OUT_T 0x0CU -#define LIS3DSH_INFO1 0x0DU -#define LIS3DSH_INFO2 0x0EU -#define LIS3DSH_WHO_AM_I 0x0FU - -#define LIS3DSH_OFF_X 0x10U -#define LIS3DSH_OFF_Y 0x11U -#define LIS3DSH_OFF_Z 0x12U - -#define LIS3DSH_CS_X 0x13U -#define LIS3DSH_CS_Y 0x14U -#define LIS3DSH_CS_Z 0x15U - -#define LIS3DSH_LC_L 0x16U -#define LIS3DSH_LC_H 0x17U - -#define LIS3DSH_STAT 0x18U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t drdy : 1; - uint8_t dor : 1; - uint8_t int_sm2 : 1; - uint8_t int_sm1 : 1; - uint8_t sync1 : 1; - uint8_t sync2 : 1; - uint8_t syncw : 1; - uint8_t l_count : 1; //alias LONG -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t l_count : 1; //alias LONG - uint8_t syncw : 1; - uint8_t sync2 : 1; - uint8_t sync1 : 1; - uint8_t int_sm1 : 1; - uint8_t int_sm2 : 1; - uint8_t dor : 1; - uint8_t drdy : 1; -#endif /* DRV_BYTE_ORDER */ -} lis3dsh_stat_t; - -#define LIS3DSH_PEAK1 0x19U -#define LIS3DSH_PEAK2 0x1AU - -#define LIS3DSH_VFC_1 0x1BU -#define LIS3DSH_VFC_2 0x1CU -#define LIS3DSH_VFC_3 0x1DU -#define LIS3DSH_VFC_4 0x1EU - -#define LIS3DSH_THRS3 0x1FU -#define LIS3DSH_CTRL_REG4 0x20U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t xen : 1; - uint8_t yen : 1; - uint8_t zen : 1; - uint8_t bdu : 1; - uint8_t odr : 4; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t odr : 4; - uint8_t bdu : 1; - uint8_t zen : 1; - uint8_t yen : 1; - uint8_t xen : 1; -#endif /* DRV_BYTE_ORDER */ -} lis3dsh_ctrl_reg4_t; - -#define LIS3DSH_CTRL_REG1 0x21U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t sm1_en : 1; - uint8_t not_used_01 : 2; - uint8_t sm1_pin : 1; - uint8_t not_used_02 : 1; - uint8_t hyst_1 : 3; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t hyst_1 : 3; - uint8_t not_used_02 : 1; - uint8_t sm1_pin : 1; - uint8_t not_used_01 : 2; - uint8_t sm1_en : 1; -#endif /* DRV_BYTE_ORDER */ -} lis3dsh_ctrl_reg1_t; - -#define LIS3DSH_CTRL_REG2 0x22U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t sm2_en : 1; - uint8_t not_used_01 : 2; - uint8_t sm2_pin : 1; - uint8_t not_used_02 : 1; - uint8_t hyst_2 : 3; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t hyst_2 : 3; - uint8_t not_used_02 : 1; - uint8_t sm2_pin : 1; - uint8_t not_used_01 : 2; - uint8_t sm2_en : 1; -#endif /* DRV_BYTE_ORDER */ -} lis3dsh_ctrl_reg2_t; - -#define LIS3DSH_CTRL_REG3 0x23U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t strt : 1; - uint8_t not_used_01 : 1; - uint8_t vfilt : 1; - uint8_t int1_en : 1; - uint8_t int2_en : 1; - uint8_t iel : 1; - uint8_t iea : 1; - uint8_t dr_en : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t dr_en : 1; - uint8_t iea : 1; - uint8_t iel : 1; - uint8_t int2_en : 1; - uint8_t int1_en : 1; - uint8_t vfilt : 1; - uint8_t not_used_01 : 1; - uint8_t strt : 1; -#endif /* DRV_BYTE_ORDER */ -} lis3dsh_ctrl_reg3_t; - -#define LIS3DSH_CTRL_REG5 0x24U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t sim : 1; - uint8_t st : 2; - uint8_t fscale : 3; - uint8_t bw : 2; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t bw : 2; - uint8_t fscale : 3; - uint8_t st : 2; - uint8_t sim : 1; -#endif /* DRV_BYTE_ORDER */ -} lis3dsh_ctrl_reg5_t; - -#define LIS3DSH_CTRL_REG6 0x25U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t p2_boot : 1; - uint8_t p1_overrun : 1; - uint8_t p1_wtm : 1; - uint8_t p1_empty : 1; - uint8_t add_inc : 1; - uint8_t wtm_en : 1; - uint8_t fifo_en : 1; - uint8_t boot : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t boot : 1; - uint8_t fifo_en : 1; - uint8_t wtm_en : 1; - uint8_t add_inc : 1; - uint8_t p1_empty : 1; - uint8_t p1_wtm : 1; - uint8_t p1_overrun : 1; - uint8_t p2_boot : 1; -#endif /* DRV_BYTE_ORDER */ -} lis3dsh_ctrl_reg6_t; - -#define LIS3DSH_STATUS 0x27U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t xda : 1; - uint8_t yda : 1; - uint8_t zda : 1; - uint8_t zyxda : 1; - uint8_t _xor : 1; - uint8_t yor : 1; - uint8_t zor : 1; - uint8_t zyxor : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t zyxor : 1; - uint8_t zor : 1; - uint8_t yor : 1; - uint8_t _xor : 1; - uint8_t zyxda : 1; - uint8_t zda : 1; - uint8_t yda : 1; - uint8_t xda : 1; -#endif /* DRV_BYTE_ORDER */ -} lis3dsh_status_t; - -#define LIS3DSH_OUT_X_L 0x28U -#define LIS3DSH_OUT_X_H 0x29U -#define LIS3DSH_OUT_Y_L 0x2AU -#define LIS3DSH_OUT_Y_H 0x2BU -#define LIS3DSH_OUT_Z_L 0x2CU -#define LIS3DSH_OUT_Z_H 0x2DU -#define LIS3DSH_FIFO_CTRL 0X2EU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t wtmp : 5; - uint8_t fmode : 3; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t fmode : 3; - uint8_t wtmp : 5; -#endif /* DRV_BYTE_ORDER */ -} lis3dsh_fifo_ctrl_t; - -#define LIS3DSH_FIFO_SRC 0x2FU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t fss : 5; - uint8_t empty : 1; - uint8_t ovrn_fifo : 1; - uint8_t wtm : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t wtm : 1; - uint8_t ovrn_fifo : 1; - uint8_t empty : 1; - uint8_t fss : 5; -#endif /* DRV_BYTE_ORDER */ -} lis3dsh_fifo_src_t; - -/* State Machine 1 */ - -#define LIS3DSH_ST0_1 0x40U -#define LIS3DSH_ST1_1 0x41U -#define LIS3DSH_ST2_1 0x42U -#define LIS3DSH_ST3_1 0x43U -#define LIS3DSH_ST4_1 0x44U -#define LIS3DSH_ST5_1 0x45U -#define LIS3DSH_ST6_1 0x46U -#define LIS3DSH_ST7_1 0x47U -#define LIS3DSH_ST8_1 0x48U -#define LIS3DSH_ST9_1 0x49U -#define LIS3DSH_ST10_1 0x4AU -#define LIS3DSH_ST11_1 0x4BU -#define LIS3DSH_ST12_1 0x4CU -#define LIS3DSH_ST13_1 0x4DU -#define LIS3DSH_ST14_1 0x4EU -#define LIS3DSH_ST15_1 0x4FU -#define LIS3DSH_TIM4_1 0x50U -#define LIS3DSH_TIM3_1 0x51U -#define LIS3DSH_TIM2_1_L 0x52U -#define LIS3DSH_TIM2_1_H 0x53U -#define LIS3DSH_TIM1_1_L 0x54U -#define LIS3DSH_TIM1_1_H 0x55U -#define LIS3DSH_THRS2_1 0x56U -#define LIS3DSH_THRS1_1 0x57U -#define LIS3DSH_MASK1_B 0x59U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t n_v : 1; - uint8_t p_v : 1; - uint8_t n_z : 1; - uint8_t p_z : 1; - uint8_t n_y : 1; - uint8_t p_y : 1; - uint8_t n_x : 1; - uint8_t p_x : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t p_x : 1; - uint8_t n_x : 1; - uint8_t p_y : 1; - uint8_t n_y : 1; - uint8_t p_z : 1; - uint8_t n_z : 1; - uint8_t p_v : 1; - uint8_t n_v : 1; -#endif /* DRV_BYTE_ORDER */ -} lis3dsh_mask1_b_t; - -#define LIS3DSH_MASK1_A 0x5AU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t n_v : 1; - uint8_t p_v : 1; - uint8_t n_z : 1; - uint8_t p_z : 1; - uint8_t n_y : 1; - uint8_t p_y : 1; - uint8_t n_x : 1; - uint8_t p_x : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t p_x : 1; - uint8_t n_x : 1; - uint8_t p_y : 1; - uint8_t n_y : 1; - uint8_t p_z : 1; - uint8_t n_z : 1; - uint8_t p_v : 1; - uint8_t n_v : 1; -#endif /* DRV_BYTE_ORDER */ -} lis3dsh_mask1_a_t; - -#define LIS3DSH_SETT1 0x5BU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t sitr : 1; - uint8_t r_tam : 1; - uint8_t thr3_ma : 1; - uint8_t not_used_01 : 2; - uint8_t abs : 1; - uint8_t thr3_sa : 1; - uint8_t p_det : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t p_det : 1; - uint8_t thr3_sa : 1; - uint8_t abs : 1; - uint8_t not_used_01 : 2; - uint8_t thr3_ma : 1; - uint8_t r_tam : 1; - uint8_t sitr : 1; -#endif /* DRV_BYTE_ORDER */ -} lis3dsh_sett1_t; - -#define LIS3DSH_PR1 0x5CU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t pp : 4; - uint8_t rp : 4; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t rp : 4; - uint8_t pp : 4; -#endif /* DRV_BYTE_ORDER */ -} lis3dsh_pr1_t; - -#define LIS3DSH_TC1_L 0x5DU -#define LIS3DSH_TC1_H 0x5EU -#define LIS3DSH_OUTS1 0x5FU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t n_v : 1; - uint8_t p_v : 1; - uint8_t n_z : 1; - uint8_t p_z : 1; - uint8_t n_y : 1; - uint8_t p_y : 1; - uint8_t n_x : 1; - uint8_t p_x : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t p_x : 1; - uint8_t n_x : 1; - uint8_t p_y : 1; - uint8_t n_y : 1; - uint8_t p_z : 1; - uint8_t n_z : 1; - uint8_t p_v : 1; - uint8_t n_v : 1; -#endif /* DRV_BYTE_ORDER */ -} lis3dsh_outs1_t; - -/* State Machine 2 */ - -#define LIS3DSH_ST0_2 0x60U -#define LIS3DSH_ST1_2 0x61U -#define LIS3DSH_ST2_2 0x62U -#define LIS3DSH_ST3_2 0x63U -#define LIS3DSH_ST4_2 0x64U -#define LIS3DSH_ST5_2 0x65U -#define LIS3DSH_ST6_2 0x66U -#define LIS3DSH_ST7_2 0x67U -#define LIS3DSH_ST8_2 0x68U -#define LIS3DSH_ST9_2 0x69U -#define LIS3DSH_ST10_2 0x6AU -#define LIS3DSH_ST11_2 0x6BU -#define LIS3DSH_ST12_2 0x6CU -#define LIS3DSH_ST13_2 0x6DU -#define LIS3DSH_ST14_2 0x6EU -#define LIS3DSH_ST15_2 0x6FU -#define LIS3DSH_TIM4_2 0x70U -#define LIS3DSH_TIM3_2 0x71U -#define LIS3DSH_TIM2_2_L 0x72U -#define LIS3DSH_TIM2_2_H 0x73U -#define LIS3DSH_TIM1_2_L 0x74U -#define LIS3DSH_TIM1_2_H 0x75U -#define LIS3DSH_THRS2_2 0x76U -#define LIS3DSH_THRS1_2 0x77U -#define LIS3DSH_DES2 0x78U -#define LIS3DSH_MASK2_B 0x79U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t n_v : 1; - uint8_t p_v : 1; - uint8_t n_z : 1; - uint8_t p_z : 1; - uint8_t n_y : 1; - uint8_t p_y : 1; - uint8_t n_x : 1; - uint8_t p_x : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t p_x : 1; - uint8_t n_x : 1; - uint8_t p_y : 1; - uint8_t n_y : 1; - uint8_t p_z : 1; - uint8_t n_z : 1; - uint8_t p_v : 1; - uint8_t n_v : 1; -#endif /* DRV_BYTE_ORDER */ -} lis3dsh_mask2_b_t; - -#define LIS3DSH_MASK2_A 0x7AU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t n_v : 1; - uint8_t p_v : 1; - uint8_t n_z : 1; - uint8_t p_z : 1; - uint8_t n_y : 1; - uint8_t p_y : 1; - uint8_t n_x : 1; - uint8_t p_x : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t p_x : 1; - uint8_t n_x : 1; - uint8_t p_y : 1; - uint8_t n_y : 1; - uint8_t p_z : 1; - uint8_t n_z : 1; - uint8_t p_v : 1; - uint8_t n_v : 1; -#endif /* DRV_BYTE_ORDER */ -} lis3dsh_mask2_a_t; - -#define LIS3DSH_SETT2 0x7BU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t sitr : 1; - uint8_t r_tam : 1; - uint8_t thr3_ma : 1; - uint8_t d_cs : 1; - uint8_t radi : 1; - uint8_t abs : 1; - uint8_t thr3_sa : 1; - uint8_t p_det : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t p_det : 1; - uint8_t thr3_sa : 1; - uint8_t abs : 1; - uint8_t radi : 1; - uint8_t d_cs : 1; - uint8_t thr3_ma : 1; - uint8_t r_tam : 1; - uint8_t sitr : 1; -#endif /* DRV_BYTE_ORDER */ -} lis3dsh_sett2_t; - -#define LIS3DSH_PR2 0x7CU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t pp : 4; - uint8_t rp : 4; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t rp : 4; - uint8_t pp : 4; -#endif /* DRV_BYTE_ORDER */ -} lis3dsh_pr2_t; - -#define LIS3DSH_TC2_L 0x7DU -#define LIS3DSH_TC2_H 0x7EU -#define LIS3DSH_OUTS2 0x7FU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t n_v : 1; - uint8_t p_v : 1; - uint8_t n_z : 1; - uint8_t p_z : 1; - uint8_t n_y : 1; - uint8_t p_y : 1; - uint8_t n_x : 1; - uint8_t p_x : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t p_x : 1; - uint8_t n_x : 1; - uint8_t p_y : 1; - uint8_t n_y : 1; - uint8_t p_z : 1; - uint8_t n_z : 1; - uint8_t p_v : 1; - uint8_t n_v : 1; -#endif /* DRV_BYTE_ORDER */ -} lis3dsh_outs2_t; - -/** - * @defgroup LIS3DSH_Register_Union - * @brief This union group all the registers having a bit-field - * description. - * This union is useful but it's not needed by the driver. - * - * REMOVING this union you are compliant with: - * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " - * - * @{ - * - */ -typedef union -{ - lis3dsh_stat_t stat; - lis3dsh_ctrl_reg4_t ctrl_reg4; - lis3dsh_ctrl_reg1_t ctrl_reg1; - lis3dsh_ctrl_reg2_t ctrl_reg2; - lis3dsh_ctrl_reg3_t ctrl_reg3; - lis3dsh_ctrl_reg5_t ctrl_reg5; - lis3dsh_ctrl_reg6_t ctrl_reg6; - lis3dsh_status_t status; - lis3dsh_fifo_ctrl_t fifo_ctrl; - lis3dsh_fifo_src_t fifo_src; - lis3dsh_mask1_b_t mask1_b; - lis3dsh_mask1_a_t mask1_a; - lis3dsh_sett1_t sett1; - lis3dsh_pr1_t pr1; - lis3dsh_outs1_t outs1; - lis3dsh_mask2_b_t mask2_b; - lis3dsh_mask2_a_t mask2_a; - lis3dsh_sett2_t sett2; - lis3dsh_pr2_t pr2; - lis3dsh_outs2_t outs2; - bitwise_t bitwise; - uint8_t byte; -} lis3dsh_reg_t; - -/** - * @} - * - */ - -#ifndef __weak -#define __weak __attribute__((weak)) -#endif /* __weak */ - -/* - * These are the basic platform dependent I/O routines to read - * and write device registers connected on a standard bus. - * The driver keeps offering a default implementation based on function - * pointers to read/write routines for backward compatibility. - * The __weak directive allows the final application to overwrite - * them with a custom implementation. - */ - -int32_t lis3dsh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len); -int32_t lis3dsh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len); - -float_t lis3dsh_from_fs2_to_mg(int16_t lsb); -float_t lis3dsh_from_fs4_to_mg(int16_t lsb); -float_t lis3dsh_from_fs6_to_mg(int16_t lsb); -float_t lis3dsh_from_fs8_to_mg(int16_t lsb); -float_t lis3dsh_from_fs16_to_mg(int16_t lsb); -float_t lis3dsh_from_lsb_to_celsius(int8_t lsb); - -typedef struct -{ - uint8_t whoami; - uint8_t info1; - uint8_t info2; -} lis3dsh_id_t; -int32_t lis3dsh_id_get(stmdev_ctx_t *ctx, lis3dsh_id_t *val); - -typedef enum -{ - LIS3DSH_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */ - LIS3DSH_SPI_3W = 0x01, /* SDO / SDI share the same pin */ -} lis3dsh_bus_mode_t; -int32_t lis3dsh_bus_mode_set(stmdev_ctx_t *ctx, - lis3dsh_bus_mode_t *val); -int32_t lis3dsh_bus_mode_get(stmdev_ctx_t *ctx, - lis3dsh_bus_mode_t *val); - -typedef enum -{ - LIS3DSH_DRV_RDY = 0x00, /* Initialize the device for driver usage */ - LIS3DSH_BOOT = 0x01, /* Restore calib. param. ( it takes 10ms ) */ - LIS3DSH_RESET = 0x02, /* Reset configuration registers */ -} lis3dsh_init_t; -int32_t lis3dsh_init_set(stmdev_ctx_t *ctx, lis3dsh_init_t val); - -typedef struct -{ -uint8_t sw_reset : - 1; /* Restoring configuration registers */ - uint8_t boot : 1; /* Restoring calibration parameters */ - uint8_t drdy_xl : 1; /* Accelerometer data ready */ - uint8_t ovrn_xl : 1; /* Accelerometer data overrun */ -} lis3dsh_status_var_t; -int32_t lis3dsh_status_get(stmdev_ctx_t *ctx, - lis3dsh_status_var_t *val); - -typedef struct -{ - uint8_t active_low : 1; /* 1 = active low / 0 = active high */ - uint8_t latched : 1; /* Signals 1 = latched / 0 = pulsed */ -} lis3dsh_int_mode_t; -int32_t lis3dsh_interrupt_mode_set(stmdev_ctx_t *ctx, - lis3dsh_int_mode_t *val); -int32_t lis3dsh_interrupt_mode_get(stmdev_ctx_t *ctx, - lis3dsh_int_mode_t *val); - -typedef struct -{ - uint8_t drdy_xl : 1; /* Accelerometer data ready. */ - uint8_t fifo_empty : 1; /* FIFO empty indication. */ - uint8_t fifo_th : 1; /* FIFO threshold reached */ - uint8_t fifo_full : 1; /* FIFO full */ - uint8_t fsm1 : 1; /* State machine 1 interrupt event */ - uint8_t fsm2 : 1; /* State machine 2 interrupt event */ -} lis3dsh_pin_int1_route_t; -int32_t lis3dsh_pin_int1_route_set(stmdev_ctx_t *ctx, - lis3dsh_pin_int1_route_t *val); -int32_t lis3dsh_pin_int1_route_get(stmdev_ctx_t *ctx, - lis3dsh_pin_int1_route_t *val); - -typedef struct -{ - uint8_t fsm1 : 1; /* State machine 1 interrupt event */ - uint8_t fsm2 : 1; /* State machine 2 interrupt event */ - uint8_t boot : 1; /* Restoring calibration parameters */ -} lis3dsh_pin_int2_route_t; -int32_t lis3dsh_pin_int2_route_set(stmdev_ctx_t *ctx, - lis3dsh_pin_int2_route_t *val); -int32_t lis3dsh_pin_int2_route_get(stmdev_ctx_t *ctx, - lis3dsh_pin_int2_route_t *val); - -typedef struct -{ - uint8_t drdy_xl : 1; /* Accelerometer data ready */ - uint8_t ovrn_xl : 1; /* Accelerometer data overrun */ - uint8_t fsm_lc : 1; /* long counter flag (for both SM) */ -uint8_t fsm_ext_sync : - 1; /* Synchronization with ext-host requested */ - uint8_t fsm1_wait_fsm2 : 1; /* fsm1 wait fsm2 */ - uint8_t fsm2_wait_fsm1 : 1; /* fsm2 wait fsm1 */ - uint8_t fsm1 : 1; /* fsm 1 interrupt event */ - uint8_t fsm2 : 1; /* fsm 2 interrupt event */ - uint8_t fifo_ovr : 1; /* FIFO overrun */ - uint8_t fifo_empty : 1; /* FIFO empty indication. */ - uint8_t fifo_full : 1; /* FIFO full */ - uint8_t fifo_th : 1; /* FIFO threshold reached */ -} lis3dsh_all_sources_t; -int32_t lis3dsh_all_sources_get(stmdev_ctx_t *ctx, - lis3dsh_all_sources_t *val); - -typedef struct -{ - enum - { - LIS3DSH_OFF = 0x00, /* in power down */ - LIS3DSH_3Hz125 = 0x01, /* Data rate @3.125 Hz */ - LIS3DSH_6Hz25 = 0x02, /* Data rate @6.25 Hz */ - LIS3DSH_12Hz5 = 0x03, /* Data rate @12.5 Hz */ - LIS3DSH_25Hz = 0x04, /* Data rate @25 Hz */ - LIS3DSH_50Hz = 0x05, /* Data rate @50 Hz */ - LIS3DSH_100Hz = 0x06, /* Data rate @100 Hz */ - LIS3DSH_400Hz = 0x07, /* Data rate @400 Hz */ - LIS3DSH_800Hz = 0x08, /* Data rate @800 Hz */ - LIS3DSH_1kHz6 = 0x09, /* Data rate @1600 Hz */ - } odr; - enum - { - LIS3DSH_2g = 0, - LIS3DSH_4g = 1, - LIS3DSH_6g = 2, - LIS3DSH_8g = 3, - LIS3DSH_16g = 4, - } fs; -} lis3dsh_md_t; -int32_t lis3dsh_mode_set(stmdev_ctx_t *ctx, lis3dsh_md_t *val); -int32_t lis3dsh_mode_get(stmdev_ctx_t *ctx, lis3dsh_md_t *val); - -typedef struct -{ - struct - { - float_t mg[3]; - int16_t raw[3]; - } xl; - struct - { - float_t deg_c; - int8_t raw; - } heat; -} lis3dsh_data_t; -int32_t lis3dsh_data_get(stmdev_ctx_t *ctx, lis3dsh_md_t *md, - lis3dsh_data_t *data); - -typedef enum -{ - LIS3DSH_ST_DISABLE = 0, - LIS3DSH_ST_POSITIVE = 1, - LIS3DSH_ST_NEGATIVE = 2, -} lis3dsh_st_t; -int32_t lis3dsh_self_test_set(stmdev_ctx_t *ctx, lis3dsh_st_t val); -int32_t lis3dsh_self_test_get(stmdev_ctx_t *ctx, lis3dsh_st_t *val); - -/** - * @} - * - */ - -#ifdef __cplusplus -} -#endif - -#endif /*LIS3DSH_DRIVER_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.c b/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.c index 14024fd8..47af7bf9 100644 --- a/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.c +++ b/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis3mdl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lis3mdl_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lis3mdl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lis3mdl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lis3mdl_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -136,7 +146,7 @@ float_t lis3mdl_from_lsb_to_celsius(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_data_rate_set(stmdev_ctx_t *ctx, lis3mdl_om_t val) +int32_t lis3mdl_data_rate_set(const stmdev_ctx_t *ctx, lis3mdl_om_t val) { lis3mdl_ctrl_reg1_t ctrl_reg1; lis3mdl_ctrl_reg4_t ctrl_reg4; @@ -174,7 +184,7 @@ int32_t lis3mdl_data_rate_set(stmdev_ctx_t *ctx, lis3mdl_om_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_data_rate_get(stmdev_ctx_t *ctx, lis3mdl_om_t *val) +int32_t lis3mdl_data_rate_get(const stmdev_ctx_t *ctx, lis3mdl_om_t *val) { lis3mdl_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -332,7 +342,7 @@ int32_t lis3mdl_data_rate_get(stmdev_ctx_t *ctx, lis3mdl_om_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_temperature_meas_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3mdl_temperature_meas_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3mdl_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -356,7 +366,7 @@ int32_t lis3mdl_temperature_meas_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_temperature_meas_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3mdl_temperature_meas_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3mdl_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -375,7 +385,7 @@ int32_t lis3mdl_temperature_meas_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_full_scale_set(stmdev_ctx_t *ctx, lis3mdl_fs_t val) +int32_t lis3mdl_full_scale_set(const stmdev_ctx_t *ctx, lis3mdl_fs_t val) { lis3mdl_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -399,7 +409,7 @@ int32_t lis3mdl_full_scale_set(stmdev_ctx_t *ctx, lis3mdl_fs_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_full_scale_get(stmdev_ctx_t *ctx, lis3mdl_fs_t *val) +int32_t lis3mdl_full_scale_get(const stmdev_ctx_t *ctx, lis3mdl_fs_t *val) { lis3mdl_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -440,7 +450,7 @@ int32_t lis3mdl_full_scale_get(stmdev_ctx_t *ctx, lis3mdl_fs_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_operating_mode_set(stmdev_ctx_t *ctx, +int32_t lis3mdl_operating_mode_set(const stmdev_ctx_t *ctx, lis3mdl_md_t val) { lis3mdl_ctrl_reg3_t ctrl_reg3; @@ -465,7 +475,7 @@ int32_t lis3mdl_operating_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_operating_mode_get(stmdev_ctx_t *ctx, +int32_t lis3mdl_operating_mode_get(const stmdev_ctx_t *ctx, lis3mdl_md_t *val) { lis3mdl_ctrl_reg3_t ctrl_reg3; @@ -503,7 +513,7 @@ int32_t lis3mdl_operating_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_fast_low_power_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3mdl_fast_low_power_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3mdl_ctrl_reg3_t ctrl_reg3; int32_t ret; @@ -527,7 +537,7 @@ int32_t lis3mdl_fast_low_power_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_fast_low_power_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3mdl_fast_low_power_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3mdl_ctrl_reg3_t ctrl_reg3; int32_t ret; @@ -546,7 +556,7 @@ int32_t lis3mdl_fast_low_power_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3mdl_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3mdl_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -570,7 +580,7 @@ int32_t lis3mdl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3mdl_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3mdl_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -590,7 +600,7 @@ int32_t lis3mdl_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_high_part_cycle_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3mdl_high_part_cycle_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3mdl_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -615,7 +625,7 @@ int32_t lis3mdl_high_part_cycle_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_high_part_cycle_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3mdl_high_part_cycle_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3mdl_ctrl_reg5_t ctrl_reg5; int32_t ret; @@ -634,7 +644,7 @@ int32_t lis3mdl_high_part_cycle_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_mag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3mdl_mag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3mdl_status_reg_t status_reg; int32_t ret; @@ -654,7 +664,7 @@ int32_t lis3mdl_mag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_mag_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3mdl_mag_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3mdl_status_reg_t status_reg; int32_t ret; @@ -673,7 +683,7 @@ int32_t lis3mdl_mag_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lis3mdl_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -696,7 +706,7 @@ int32_t lis3mdl_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lis3mdl_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -728,7 +738,7 @@ int32_t lis3mdl_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lis3mdl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -744,7 +754,7 @@ int32_t lis3mdl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_self_test_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3mdl_self_test_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3mdl_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -768,7 +778,7 @@ int32_t lis3mdl_self_test_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_self_test_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3mdl_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3mdl_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -787,7 +797,7 @@ int32_t lis3mdl_self_test_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3mdl_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3mdl_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -811,7 +821,7 @@ int32_t lis3mdl_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3mdl_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3mdl_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -830,7 +840,7 @@ int32_t lis3mdl_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3mdl_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3mdl_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -854,7 +864,7 @@ int32_t lis3mdl_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3mdl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3mdl_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -873,7 +883,7 @@ int32_t lis3mdl_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_data_format_set(stmdev_ctx_t *ctx, lis3mdl_ble_t val) +int32_t lis3mdl_data_format_set(const stmdev_ctx_t *ctx, lis3mdl_ble_t val) { lis3mdl_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -897,7 +907,7 @@ int32_t lis3mdl_data_format_set(stmdev_ctx_t *ctx, lis3mdl_ble_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_data_format_get(stmdev_ctx_t *ctx, lis3mdl_ble_t *val) +int32_t lis3mdl_data_format_get(const stmdev_ctx_t *ctx, lis3mdl_ble_t *val) { lis3mdl_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -930,7 +940,7 @@ int32_t lis3mdl_data_format_get(stmdev_ctx_t *ctx, lis3mdl_ble_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_status_get(stmdev_ctx_t *ctx, +int32_t lis3mdl_status_get(const stmdev_ctx_t *ctx, lis3mdl_status_reg_t *val) { return lis3mdl_read_reg(ctx, LIS3MDL_STATUS_REG, (uint8_t *) val, 1); @@ -955,7 +965,7 @@ int32_t lis3mdl_status_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_int_config_set(stmdev_ctx_t *ctx, +int32_t lis3mdl_int_config_set(const stmdev_ctx_t *ctx, lis3mdl_int_cfg_t *val) { return lis3mdl_write_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *) val, 1); @@ -969,7 +979,7 @@ int32_t lis3mdl_int_config_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_int_config_get(stmdev_ctx_t *ctx, +int32_t lis3mdl_int_config_get(const stmdev_ctx_t *ctx, lis3mdl_int_cfg_t *val) { return lis3mdl_read_reg(ctx, LIS3MDL_INT_CFG, (uint8_t *) val, 1); @@ -982,7 +992,7 @@ int32_t lis3mdl_int_config_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_int_generation_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3mdl_int_generation_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3mdl_int_cfg_t int_cfg; int32_t ret; @@ -1006,7 +1016,7 @@ int32_t lis3mdl_int_generation_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3mdl_int_generation_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3mdl_int_cfg_t int_cfg; int32_t ret; @@ -1026,7 +1036,7 @@ int32_t lis3mdl_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_int_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis3mdl_int_notification_mode_set(const stmdev_ctx_t *ctx, lis3mdl_lir_t val) { lis3mdl_int_cfg_t int_cfg; @@ -1052,7 +1062,7 @@ int32_t lis3mdl_int_notification_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_int_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis3mdl_int_notification_mode_get(const stmdev_ctx_t *ctx, lis3mdl_lir_t *val) { lis3mdl_int_cfg_t int_cfg; @@ -1086,7 +1096,7 @@ int32_t lis3mdl_int_notification_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_int_polarity_set(stmdev_ctx_t *ctx, lis3mdl_iea_t val) +int32_t lis3mdl_int_polarity_set(const stmdev_ctx_t *ctx, lis3mdl_iea_t val) { lis3mdl_int_cfg_t int_cfg; int32_t ret; @@ -1110,7 +1120,7 @@ int32_t lis3mdl_int_polarity_set(stmdev_ctx_t *ctx, lis3mdl_iea_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_int_polarity_get(stmdev_ctx_t *ctx, +int32_t lis3mdl_int_polarity_get(const stmdev_ctx_t *ctx, lis3mdl_iea_t *val) { lis3mdl_int_cfg_t int_cfg; @@ -1144,7 +1154,7 @@ int32_t lis3mdl_int_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_int_on_z_ax_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3mdl_int_on_z_ax_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3mdl_int_cfg_t int_cfg; int32_t ret; @@ -1168,7 +1178,7 @@ int32_t lis3mdl_int_on_z_ax_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_int_on_z_ax_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3mdl_int_on_z_ax_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3mdl_int_cfg_t int_cfg; int32_t ret; @@ -1187,7 +1197,7 @@ int32_t lis3mdl_int_on_z_ax_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_int_on_y_ax_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3mdl_int_on_y_ax_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3mdl_int_cfg_t int_cfg; int32_t ret; @@ -1211,7 +1221,7 @@ int32_t lis3mdl_int_on_y_ax_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_int_on_y_ax_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3mdl_int_on_y_ax_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3mdl_int_cfg_t int_cfg; int32_t ret; @@ -1230,7 +1240,7 @@ int32_t lis3mdl_int_on_y_ax_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_int_on_x_ax_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lis3mdl_int_on_x_ax_set(const stmdev_ctx_t *ctx, uint8_t val) { lis3mdl_int_cfg_t int_cfg; int32_t ret; @@ -1254,7 +1264,7 @@ int32_t lis3mdl_int_on_x_ax_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_int_on_x_ax_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3mdl_int_on_x_ax_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3mdl_int_cfg_t int_cfg; int32_t ret; @@ -1273,7 +1283,7 @@ int32_t lis3mdl_int_on_x_ax_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_int_source_get(stmdev_ctx_t *ctx, +int32_t lis3mdl_int_source_get(const stmdev_ctx_t *ctx, lis3mdl_int_src_t *val) { return lis3mdl_read_reg(ctx, LIS3MDL_INT_SRC, (uint8_t *) val, 1); @@ -1287,7 +1297,7 @@ int32_t lis3mdl_int_source_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_interrupt_event_flag_get(stmdev_ctx_t *ctx, +int32_t lis3mdl_interrupt_event_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3mdl_int_src_t int_src; @@ -1307,7 +1317,7 @@ int32_t lis3mdl_interrupt_event_flag_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_int_mag_over_range_flag_get(stmdev_ctx_t *ctx, +int32_t lis3mdl_int_mag_over_range_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3mdl_int_src_t int_src; @@ -1327,7 +1337,7 @@ int32_t lis3mdl_int_mag_over_range_flag_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_int_neg_z_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3mdl_int_neg_z_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3mdl_int_src_t int_src; int32_t ret; @@ -1346,7 +1356,7 @@ int32_t lis3mdl_int_neg_z_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_int_neg_y_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3mdl_int_neg_y_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3mdl_int_src_t int_src; int32_t ret; @@ -1364,7 +1374,7 @@ int32_t lis3mdl_int_neg_y_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_int_neg_x_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3mdl_int_neg_x_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3mdl_int_src_t int_src; int32_t ret; @@ -1382,7 +1392,7 @@ int32_t lis3mdl_int_neg_x_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_int_pos_z_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3mdl_int_pos_z_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3mdl_int_src_t int_src; int32_t ret; @@ -1400,7 +1410,7 @@ int32_t lis3mdl_int_pos_z_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_int_pos_y_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3mdl_int_pos_y_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3mdl_int_src_t int_src; int32_t ret; @@ -1418,7 +1428,7 @@ int32_t lis3mdl_int_pos_y_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_int_pos_x_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lis3mdl_int_pos_x_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lis3mdl_int_src_t int_src; int32_t ret; @@ -1436,7 +1446,7 @@ int32_t lis3mdl_int_pos_x_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_int_threshold_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lis3mdl_int_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -1456,7 +1466,7 @@ int32_t lis3mdl_int_threshold_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_int_threshold_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lis3mdl_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1489,7 +1499,7 @@ int32_t lis3mdl_int_threshold_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_spi_mode_set(stmdev_ctx_t *ctx, lis3mdl_sim_t val) +int32_t lis3mdl_spi_mode_set(const stmdev_ctx_t *ctx, lis3mdl_sim_t val) { lis3mdl_ctrl_reg3_t ctrl_reg3; int32_t ret; @@ -1513,7 +1523,7 @@ int32_t lis3mdl_spi_mode_set(stmdev_ctx_t *ctx, lis3mdl_sim_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lis3mdl_spi_mode_get(stmdev_ctx_t *ctx, lis3mdl_sim_t *val) +int32_t lis3mdl_spi_mode_get(const stmdev_ctx_t *ctx, lis3mdl_sim_t *val) { lis3mdl_ctrl_reg3_t ctrl_reg3; int32_t ret; diff --git a/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.h b/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.h index f76934af..e444c15b 100644 --- a/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.h +++ b/sensor/stmemsc/lis3mdl_STdC/driver/lis3mdl_reg.h @@ -388,10 +388,10 @@ typedef union * them with a custom implementation. */ -int32_t lis3mdl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lis3mdl_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lis3mdl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lis3mdl_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -443,11 +443,11 @@ typedef enum LIS3MDL_UHP_80Hz = 0x3E, } lis3mdl_om_t; -int32_t lis3mdl_data_rate_set(stmdev_ctx_t *ctx, lis3mdl_om_t val); -int32_t lis3mdl_data_rate_get(stmdev_ctx_t *ctx, lis3mdl_om_t *val); +int32_t lis3mdl_data_rate_set(const stmdev_ctx_t *ctx, lis3mdl_om_t val); +int32_t lis3mdl_data_rate_get(const stmdev_ctx_t *ctx, lis3mdl_om_t *val); -int32_t lis3mdl_temperature_meas_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3mdl_temperature_meas_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3mdl_temperature_meas_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3mdl_temperature_meas_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -456,8 +456,8 @@ typedef enum LIS3MDL_12_GAUSS = 2, LIS3MDL_16_GAUSS = 3, } lis3mdl_fs_t; -int32_t lis3mdl_full_scale_set(stmdev_ctx_t *ctx, lis3mdl_fs_t val); -int32_t lis3mdl_full_scale_get(stmdev_ctx_t *ctx, lis3mdl_fs_t *val); +int32_t lis3mdl_full_scale_set(const stmdev_ctx_t *ctx, lis3mdl_fs_t val); +int32_t lis3mdl_full_scale_get(const stmdev_ctx_t *ctx, lis3mdl_fs_t *val); typedef enum { @@ -465,68 +465,68 @@ typedef enum LIS3MDL_SINGLE_TRIGGER = 1, LIS3MDL_POWER_DOWN = 2, } lis3mdl_md_t; -int32_t lis3mdl_operating_mode_set(stmdev_ctx_t *ctx, +int32_t lis3mdl_operating_mode_set(const stmdev_ctx_t *ctx, lis3mdl_md_t val); -int32_t lis3mdl_operating_mode_get(stmdev_ctx_t *ctx, +int32_t lis3mdl_operating_mode_get(const stmdev_ctx_t *ctx, lis3mdl_md_t *val); -int32_t lis3mdl_fast_low_power_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3mdl_fast_low_power_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3mdl_fast_low_power_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3mdl_fast_low_power_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3mdl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3mdl_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lis3mdl_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3mdl_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3mdl_high_part_cycle_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3mdl_high_part_cycle_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3mdl_high_part_cycle_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3mdl_high_part_cycle_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3mdl_mag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3mdl_mag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3mdl_mag_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3mdl_mag_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3mdl_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lis3mdl_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lis3mdl_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lis3mdl_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lis3mdl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lis3mdl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lis3mdl_self_test_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3mdl_self_test_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3mdl_self_test_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3mdl_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3mdl_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3mdl_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3mdl_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3mdl_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3mdl_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3mdl_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3mdl_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3mdl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LIS3MDL_LSB_AT_LOW_ADD = 0, LIS3MDL_MSB_AT_LOW_ADD = 1, } lis3mdl_ble_t; -int32_t lis3mdl_data_format_set(stmdev_ctx_t *ctx, lis3mdl_ble_t val); -int32_t lis3mdl_data_format_get(stmdev_ctx_t *ctx, +int32_t lis3mdl_data_format_set(const stmdev_ctx_t *ctx, lis3mdl_ble_t val); +int32_t lis3mdl_data_format_get(const stmdev_ctx_t *ctx, lis3mdl_ble_t *val); -int32_t lis3mdl_status_get(stmdev_ctx_t *ctx, +int32_t lis3mdl_status_get(const stmdev_ctx_t *ctx, lis3mdl_status_reg_t *val); -int32_t lis3mdl_int_config_set(stmdev_ctx_t *ctx, +int32_t lis3mdl_int_config_set(const stmdev_ctx_t *ctx, lis3mdl_int_cfg_t *val); -int32_t lis3mdl_int_config_get(stmdev_ctx_t *ctx, +int32_t lis3mdl_int_config_get(const stmdev_ctx_t *ctx, lis3mdl_int_cfg_t *val); -int32_t lis3mdl_int_generation_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3mdl_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3mdl_int_generation_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3mdl_int_generation_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LIS3MDL_INT_PULSED = 0, LIS3MDL_INT_LATCHED = 1, } lis3mdl_lir_t; -int32_t lis3mdl_int_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lis3mdl_int_notification_mode_set(const stmdev_ctx_t *ctx, lis3mdl_lir_t val); -int32_t lis3mdl_int_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lis3mdl_int_notification_mode_get(const stmdev_ctx_t *ctx, lis3mdl_lir_t *val); typedef enum @@ -534,51 +534,51 @@ typedef enum LIS3MDL_ACTIVE_HIGH = 0, LIS3MDL_ACTIVE_LOW = 1, } lis3mdl_iea_t; -int32_t lis3mdl_int_polarity_set(stmdev_ctx_t *ctx, +int32_t lis3mdl_int_polarity_set(const stmdev_ctx_t *ctx, lis3mdl_iea_t val); -int32_t lis3mdl_int_polarity_get(stmdev_ctx_t *ctx, +int32_t lis3mdl_int_polarity_get(const stmdev_ctx_t *ctx, lis3mdl_iea_t *val); -int32_t lis3mdl_int_on_z_ax_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3mdl_int_on_z_ax_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3mdl_int_on_z_ax_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3mdl_int_on_z_ax_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3mdl_int_on_y_ax_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3mdl_int_on_y_ax_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3mdl_int_on_y_ax_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3mdl_int_on_y_ax_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3mdl_int_on_x_ax_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lis3mdl_int_on_x_ax_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3mdl_int_on_x_ax_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lis3mdl_int_on_x_ax_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3mdl_int_source_get(stmdev_ctx_t *ctx, +int32_t lis3mdl_int_source_get(const stmdev_ctx_t *ctx, lis3mdl_int_src_t *val); -int32_t lis3mdl_interrupt_event_flag_get(stmdev_ctx_t *ctx, +int32_t lis3mdl_interrupt_event_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3mdl_int_mag_over_range_flag_get(stmdev_ctx_t *ctx, +int32_t lis3mdl_int_mag_over_range_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3mdl_int_neg_z_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3mdl_int_neg_z_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3mdl_int_neg_y_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3mdl_int_neg_y_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3mdl_int_neg_x_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3mdl_int_neg_x_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3mdl_int_pos_z_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3mdl_int_pos_z_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3mdl_int_pos_y_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3mdl_int_pos_y_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3mdl_int_pos_x_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lis3mdl_int_pos_x_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lis3mdl_int_threshold_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lis3mdl_int_threshold_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lis3mdl_int_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lis3mdl_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum { LIS3MDL_SPI_4_WIRE = 0, LIS3MDL_SPI_3_WIRE = 1, } lis3mdl_sim_t; -int32_t lis3mdl_spi_mode_set(stmdev_ctx_t *ctx, lis3mdl_sim_t val); -int32_t lis3mdl_spi_mode_get(stmdev_ctx_t *ctx, lis3mdl_sim_t *val); +int32_t lis3mdl_spi_mode_set(const stmdev_ctx_t *ctx, lis3mdl_sim_t val); +int32_t lis3mdl_spi_mode_get(const stmdev_ctx_t *ctx, lis3mdl_sim_t *val); /** *@} diff --git a/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.c b/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.c index 23a1a976..9ff29d08 100644 --- a/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.c +++ b/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lps22ch_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lps22ch_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lps22ch_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lps22ch_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lps22ch_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -120,7 +130,7 @@ float_t lps22ch_from_lsb_to_celsius(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22ch_autozero_rst_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22ch_interrupt_cfg_t reg; int32_t ret; @@ -144,7 +154,7 @@ int32_t lps22ch_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22ch_autozero_rst_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22ch_interrupt_cfg_t reg; int32_t ret; @@ -163,7 +173,7 @@ int32_t lps22ch_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_autozero_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22ch_autozero_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22ch_interrupt_cfg_t reg; int32_t ret; @@ -187,7 +197,7 @@ int32_t lps22ch_autozero_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_autozero_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22ch_autozero_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22ch_interrupt_cfg_t reg; int32_t ret; @@ -206,7 +216,7 @@ int32_t lps22ch_autozero_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_pressure_snap_rst_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22ch_pressure_snap_rst_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22ch_interrupt_cfg_t reg; int32_t ret; @@ -230,7 +240,7 @@ int32_t lps22ch_pressure_snap_rst_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_pressure_snap_rst_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22ch_pressure_snap_rst_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22ch_interrupt_cfg_t reg; int32_t ret; @@ -249,7 +259,7 @@ int32_t lps22ch_pressure_snap_rst_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22ch_pressure_snap_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22ch_interrupt_cfg_t reg; int32_t ret; @@ -273,7 +283,7 @@ int32_t lps22ch_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22ch_pressure_snap_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22ch_interrupt_cfg_t reg; int32_t ret; @@ -292,7 +302,7 @@ int32_t lps22ch_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22ch_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22ch_ctrl_reg1_t reg; int32_t ret; @@ -316,7 +326,7 @@ int32_t lps22ch_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22ch_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22ch_ctrl_reg1_t reg; int32_t ret; @@ -335,7 +345,7 @@ int32_t lps22ch_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_data_rate_set(stmdev_ctx_t *ctx, lps22ch_odr_t val) +int32_t lps22ch_data_rate_set(const stmdev_ctx_t *ctx, lps22ch_odr_t val) { lps22ch_ctrl_reg1_t ctrl_reg1; lps22ch_ctrl_reg2_t ctrl_reg2; @@ -372,7 +382,7 @@ int32_t lps22ch_data_rate_set(stmdev_ctx_t *ctx, lps22ch_odr_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_data_rate_get(stmdev_ctx_t *ctx, lps22ch_odr_t *val) +int32_t lps22ch_data_rate_get(const stmdev_ctx_t *ctx, lps22ch_odr_t *val) { lps22ch_ctrl_reg1_t ctrl_reg1; lps22ch_ctrl_reg2_t ctrl_reg2; @@ -467,7 +477,7 @@ int32_t lps22ch_data_rate_get(stmdev_ctx_t *ctx, lps22ch_odr_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_pressure_ref_set(stmdev_ctx_t *ctx, int16_t val) +int32_t lps22ch_pressure_ref_set(const stmdev_ctx_t *ctx, int16_t val) { uint8_t buff[2]; int32_t ret; @@ -490,7 +500,7 @@ int32_t lps22ch_pressure_ref_set(stmdev_ctx_t *ctx, int16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_pressure_ref_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lps22ch_pressure_ref_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -512,7 +522,7 @@ int32_t lps22ch_pressure_ref_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val) +int32_t lps22ch_pressure_offset_set(const stmdev_ctx_t *ctx, int16_t val) { uint8_t buff[2]; int32_t ret; @@ -535,7 +545,7 @@ int32_t lps22ch_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lps22ch_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -555,7 +565,7 @@ int32_t lps22ch_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_all_sources_get(stmdev_ctx_t *ctx, +int32_t lps22ch_all_sources_get(const stmdev_ctx_t *ctx, lps22ch_all_sources_t *val) { int32_t ret; @@ -586,7 +596,7 @@ int32_t lps22ch_all_sources_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_status_reg_get(stmdev_ctx_t *ctx, +int32_t lps22ch_status_reg_get(const stmdev_ctx_t *ctx, lps22ch_status_t *val) { int32_t ret; @@ -604,7 +614,7 @@ int32_t lps22ch_status_reg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_press_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lps22ch_press_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22ch_status_t reg; @@ -624,7 +634,7 @@ int32_t lps22ch_press_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lps22ch_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22ch_status_t reg; @@ -656,7 +666,7 @@ int32_t lps22ch_temp_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff) +int32_t lps22ch_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff) { int32_t ret; @@ -678,7 +688,7 @@ int32_t lps22ch_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff) +int32_t lps22ch_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) { int32_t ret; @@ -698,7 +708,7 @@ int32_t lps22ch_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_fifo_pressure_raw_get(stmdev_ctx_t *ctx, +int32_t lps22ch_fifo_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff) { int32_t ret; @@ -721,7 +731,7 @@ int32_t lps22ch_fifo_pressure_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_fifo_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t lps22ch_fifo_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) { int32_t ret; @@ -754,7 +764,7 @@ int32_t lps22ch_fifo_temperature_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lps22ch_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -772,7 +782,7 @@ int32_t lps22ch_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22ch_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22ch_ctrl_reg2_t reg; int32_t ret; @@ -797,7 +807,7 @@ int32_t lps22ch_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22ch_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22ch_ctrl_reg2_t reg; int32_t ret; @@ -818,7 +828,7 @@ int32_t lps22ch_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22ch_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22ch_ctrl_reg2_t reg; int32_t ret; @@ -844,7 +854,7 @@ int32_t lps22ch_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22ch_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22ch_ctrl_reg2_t reg; int32_t ret; @@ -864,7 +874,7 @@ int32_t lps22ch_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22ch_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22ch_ctrl_reg2_t reg; int32_t ret; @@ -889,7 +899,7 @@ int32_t lps22ch_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22ch_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22ch_ctrl_reg2_t reg; int32_t ret; @@ -921,7 +931,7 @@ int32_t lps22ch_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lps22ch_lp_bandwidth_set(const stmdev_ctx_t *ctx, lps22ch_lpfp_cfg_t val) { lps22ch_ctrl_reg1_t reg; @@ -946,7 +956,7 @@ int32_t lps22ch_lp_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lps22ch_lp_bandwidth_get(const stmdev_ctx_t *ctx, lps22ch_lpfp_cfg_t *val) { lps22ch_ctrl_reg1_t reg; @@ -997,7 +1007,7 @@ int32_t lps22ch_lp_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lps22ch_i2c_interface_set(const stmdev_ctx_t *ctx, lps22ch_i2c_disable_t val) { lps22ch_if_ctrl_t reg; @@ -1022,7 +1032,7 @@ int32_t lps22ch_i2c_interface_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lps22ch_i2c_interface_get(const stmdev_ctx_t *ctx, lps22ch_i2c_disable_t *val) { lps22ch_if_ctrl_t reg; @@ -1056,7 +1066,7 @@ int32_t lps22ch_i2c_interface_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_i3c_interface_set(stmdev_ctx_t *ctx, +int32_t lps22ch_i3c_interface_set(const stmdev_ctx_t *ctx, lps22ch_i3c_disable_t val) { lps22ch_if_ctrl_t reg; @@ -1082,7 +1092,7 @@ int32_t lps22ch_i3c_interface_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_i3c_interface_get(stmdev_ctx_t *ctx, +int32_t lps22ch_i3c_interface_get(const stmdev_ctx_t *ctx, lps22ch_i3c_disable_t *val) { lps22ch_if_ctrl_t reg; @@ -1116,7 +1126,7 @@ int32_t lps22ch_i3c_interface_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t lps22ch_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, lps22ch_pu_en_t val) { lps22ch_if_ctrl_t reg; @@ -1141,7 +1151,7 @@ int32_t lps22ch_sdo_sa0_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t lps22ch_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, lps22ch_pu_en_t *val) { lps22ch_if_ctrl_t reg; @@ -1175,7 +1185,7 @@ int32_t lps22ch_sdo_sa0_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_sda_mode_set(stmdev_ctx_t *ctx, lps22ch_pu_en_t val) +int32_t lps22ch_sda_mode_set(const stmdev_ctx_t *ctx, lps22ch_pu_en_t val) { lps22ch_if_ctrl_t reg; int32_t ret; @@ -1199,7 +1209,7 @@ int32_t lps22ch_sda_mode_set(stmdev_ctx_t *ctx, lps22ch_pu_en_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_sda_mode_get(stmdev_ctx_t *ctx, lps22ch_pu_en_t *val) +int32_t lps22ch_sda_mode_get(const stmdev_ctx_t *ctx, lps22ch_pu_en_t *val) { lps22ch_if_ctrl_t reg; int32_t ret; @@ -1232,7 +1242,7 @@ int32_t lps22ch_sda_mode_get(stmdev_ctx_t *ctx, lps22ch_pu_en_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_spi_mode_set(stmdev_ctx_t *ctx, lps22ch_sim_t val) +int32_t lps22ch_spi_mode_set(const stmdev_ctx_t *ctx, lps22ch_sim_t val) { lps22ch_ctrl_reg1_t reg; int32_t ret; @@ -1256,7 +1266,7 @@ int32_t lps22ch_spi_mode_set(stmdev_ctx_t *ctx, lps22ch_sim_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_spi_mode_get(stmdev_ctx_t *ctx, lps22ch_sim_t *val) +int32_t lps22ch_spi_mode_get(const stmdev_ctx_t *ctx, lps22ch_sim_t *val) { lps22ch_ctrl_reg1_t reg; int32_t ret; @@ -1302,7 +1312,7 @@ int32_t lps22ch_spi_mode_get(stmdev_ctx_t *ctx, lps22ch_sim_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_int_notification_set(stmdev_ctx_t *ctx, +int32_t lps22ch_int_notification_set(const stmdev_ctx_t *ctx, lps22ch_lir_t val) { lps22ch_interrupt_cfg_t reg; @@ -1327,7 +1337,7 @@ int32_t lps22ch_int_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_int_notification_get(stmdev_ctx_t *ctx, +int32_t lps22ch_int_notification_get(const stmdev_ctx_t *ctx, lps22ch_lir_t *val) { lps22ch_interrupt_cfg_t reg; @@ -1361,7 +1371,7 @@ int32_t lps22ch_int_notification_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_pin_mode_set(stmdev_ctx_t *ctx, lps22ch_pp_od_t val) +int32_t lps22ch_pin_mode_set(const stmdev_ctx_t *ctx, lps22ch_pp_od_t val) { lps22ch_ctrl_reg2_t reg; int32_t ret; @@ -1385,7 +1395,7 @@ int32_t lps22ch_pin_mode_set(stmdev_ctx_t *ctx, lps22ch_pp_od_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_pin_mode_get(stmdev_ctx_t *ctx, lps22ch_pp_od_t *val) +int32_t lps22ch_pin_mode_get(const stmdev_ctx_t *ctx, lps22ch_pp_od_t *val) { lps22ch_ctrl_reg2_t reg; int32_t ret; @@ -1418,7 +1428,7 @@ int32_t lps22ch_pin_mode_get(stmdev_ctx_t *ctx, lps22ch_pp_od_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lps22ch_pin_polarity_set(const stmdev_ctx_t *ctx, lps22ch_int_h_l_t val) { lps22ch_ctrl_reg2_t reg; @@ -1443,7 +1453,7 @@ int32_t lps22ch_pin_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lps22ch_pin_polarity_get(const stmdev_ctx_t *ctx, lps22ch_int_h_l_t *val) { lps22ch_ctrl_reg2_t reg; @@ -1477,7 +1487,7 @@ int32_t lps22ch_pin_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_pin_int_route_set(stmdev_ctx_t *ctx, +int32_t lps22ch_pin_int_route_set(const stmdev_ctx_t *ctx, lps22ch_ctrl_reg3_t *val) { int32_t ret; @@ -1495,7 +1505,7 @@ int32_t lps22ch_pin_int_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_pin_int_route_get(stmdev_ctx_t *ctx, +int32_t lps22ch_pin_int_route_get(const stmdev_ctx_t *ctx, lps22ch_ctrl_reg3_t *val) { int32_t ret; @@ -1526,7 +1536,7 @@ int32_t lps22ch_pin_int_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_int_on_threshold_set(stmdev_ctx_t *ctx, +int32_t lps22ch_int_on_threshold_set(const stmdev_ctx_t *ctx, lps22ch_pe_t val) { lps22ch_interrupt_cfg_t reg; @@ -1562,7 +1572,7 @@ int32_t lps22ch_int_on_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_int_on_threshold_get(stmdev_ctx_t *ctx, +int32_t lps22ch_int_on_threshold_get(const stmdev_ctx_t *ctx, lps22ch_pe_t *val) { lps22ch_interrupt_cfg_t reg; @@ -1604,7 +1614,7 @@ int32_t lps22ch_int_on_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_int_treshold_set(stmdev_ctx_t *ctx, uint16_t buff) +int32_t lps22ch_int_threshold_set(const stmdev_ctx_t *ctx, uint16_t buff) { int32_t ret; @@ -1632,7 +1642,7 @@ int32_t lps22ch_int_treshold_set(stmdev_ctx_t *ctx, uint16_t buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_int_treshold_get(stmdev_ctx_t *ctx, uint16_t *buff) +int32_t lps22ch_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *buff) { int32_t ret; @@ -1672,7 +1682,7 @@ int32_t lps22ch_int_treshold_get(stmdev_ctx_t *ctx, uint16_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_fifo_mode_set(stmdev_ctx_t *ctx, lps22ch_f_mode_t val) +int32_t lps22ch_fifo_mode_set(const stmdev_ctx_t *ctx, lps22ch_f_mode_t val) { lps22ch_fifo_ctrl_t reg; int32_t ret; @@ -1696,7 +1706,7 @@ int32_t lps22ch_fifo_mode_set(stmdev_ctx_t *ctx, lps22ch_f_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lps22ch_fifo_mode_get(const stmdev_ctx_t *ctx, lps22ch_f_mode_t *val) { lps22ch_fifo_ctrl_t reg; @@ -1751,7 +1761,7 @@ int32_t lps22ch_fifo_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22ch_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22ch_fifo_ctrl_t reg; int32_t ret; @@ -1776,7 +1786,7 @@ int32_t lps22ch_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22ch_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22ch_fifo_ctrl_t reg; int32_t ret; @@ -1795,7 +1805,7 @@ int32_t lps22ch_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22ch_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22ch_fifo_wtm_t reg; int32_t ret; @@ -1819,7 +1829,7 @@ int32_t lps22ch_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22ch_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22ch_fifo_wtm_t reg; int32_t ret; @@ -1838,7 +1848,7 @@ int32_t lps22ch_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lps22ch_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1855,7 +1865,7 @@ int32_t lps22ch_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_fifo_src_get(stmdev_ctx_t *ctx, +int32_t lps22ch_fifo_src_get(const stmdev_ctx_t *ctx, lps22ch_fifo_status2_t *val) { int32_t ret; @@ -1873,7 +1883,7 @@ int32_t lps22ch_fifo_src_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22ch_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22ch_fifo_status2_t reg; int32_t ret; @@ -1892,7 +1902,7 @@ int32_t lps22ch_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22ch_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22ch_fifo_status2_t reg; int32_t ret; @@ -1911,7 +1921,7 @@ int32_t lps22ch_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22ch_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22ch_fifo_status2_t reg; int32_t ret; @@ -1930,7 +1940,7 @@ int32_t lps22ch_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22ch_fifo_ovr_on_int_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22ch_ctrl_reg3_t reg; int32_t ret; @@ -1954,7 +1964,7 @@ int32_t lps22ch_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22ch_fifo_ovr_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22ch_ctrl_reg3_t reg; int32_t ret; @@ -1973,7 +1983,7 @@ int32_t lps22ch_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, +int32_t lps22ch_fifo_threshold_on_int_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22ch_ctrl_reg3_t reg; @@ -1998,7 +2008,7 @@ int32_t lps22ch_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, +int32_t lps22ch_fifo_threshold_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22ch_ctrl_reg3_t reg; @@ -2018,7 +2028,7 @@ int32_t lps22ch_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22ch_fifo_full_on_int_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22ch_ctrl_reg3_t reg; int32_t ret; @@ -2042,7 +2052,7 @@ int32_t lps22ch_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22ch_fifo_full_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22ch_fifo_full_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22ch_ctrl_reg3_t reg; int32_t ret; diff --git a/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.h b/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.h index aa876c62..d28cd4df 100644 --- a/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.h +++ b/sensor/stmemsc/lps22ch_STdC/driver/lps22ch_reg.h @@ -309,15 +309,13 @@ typedef struct typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN -uint8_t f_mode : - 3; /* f_mode + trig_modes */ + uint8_t f_mode : 3; /* f_mode + trig_modes */ uint8_t stop_on_wtm : 1; uint8_t not_used_01 : 4; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN uint8_t not_used_01 : 4; uint8_t stop_on_wtm : 1; -uint8_t f_mode : - 3; /* f_mode + trig_modes */ + uint8_t f_mode : 3; /* f_mode + trig_modes */ #endif /* DRV_BYTE_ORDER */ } lps22ch_fifo_ctrl_t; @@ -449,10 +447,10 @@ typedef union * them with a custom implementation. */ -int32_t lps22ch_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lps22ch_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lps22ch_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lps22ch_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -460,21 +458,21 @@ float_t lps22ch_from_lsb_to_hpa(uint32_t lsb); float_t lps22ch_from_lsb_to_celsius(int16_t lsb); -int32_t lps22ch_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22ch_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22ch_autozero_rst_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22ch_autozero_rst_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22ch_autozero_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22ch_autozero_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22ch_autozero_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22ch_autozero_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22ch_pressure_snap_rst_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22ch_pressure_snap_rst_get(stmdev_ctx_t *ctx, +int32_t lps22ch_pressure_snap_rst_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22ch_pressure_snap_rst_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22ch_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22ch_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22ch_pressure_snap_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22ch_pressure_snap_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22ch_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22ch_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lps22ch_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22ch_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -494,14 +492,14 @@ typedef enum LPS22CH_100_Hz = 0x06, LPS22CH_200_Hz = 0x07, } lps22ch_odr_t; -int32_t lps22ch_data_rate_set(stmdev_ctx_t *ctx, lps22ch_odr_t val); -int32_t lps22ch_data_rate_get(stmdev_ctx_t *ctx, lps22ch_odr_t *val); +int32_t lps22ch_data_rate_set(const stmdev_ctx_t *ctx, lps22ch_odr_t val); +int32_t lps22ch_data_rate_get(const stmdev_ctx_t *ctx, lps22ch_odr_t *val); -int32_t lps22ch_pressure_ref_set(stmdev_ctx_t *ctx, int16_t val); -int32_t lps22ch_pressure_ref_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lps22ch_pressure_ref_set(const stmdev_ctx_t *ctx, int16_t val); +int32_t lps22ch_pressure_ref_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lps22ch_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val); -int32_t lps22ch_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lps22ch_pressure_offset_set(const stmdev_ctx_t *ctx, int16_t val); +int32_t lps22ch_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val); typedef struct { @@ -509,38 +507,38 @@ typedef struct lps22ch_fifo_status2_t fifo_status2; lps22ch_status_t status; } lps22ch_all_sources_t; -int32_t lps22ch_all_sources_get(stmdev_ctx_t *ctx, +int32_t lps22ch_all_sources_get(const stmdev_ctx_t *ctx, lps22ch_all_sources_t *val); -int32_t lps22ch_status_reg_get(stmdev_ctx_t *ctx, +int32_t lps22ch_status_reg_get(const stmdev_ctx_t *ctx, lps22ch_status_t *val); -int32_t lps22ch_press_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lps22ch_press_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22ch_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lps22ch_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22ch_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff); +int32_t lps22ch_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff); -int32_t lps22ch_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff); +int32_t lps22ch_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff); -int32_t lps22ch_fifo_pressure_raw_get(stmdev_ctx_t *ctx, +int32_t lps22ch_fifo_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff); -int32_t lps22ch_fifo_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t lps22ch_fifo_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff); -int32_t lps22ch_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lps22ch_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lps22ch_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22ch_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22ch_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22ch_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22ch_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22ch_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22ch_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22ch_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22ch_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22ch_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22ch_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22ch_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -548,9 +546,9 @@ typedef enum LPS22CH_LPF_ODR_DIV_9 = 2, LPS22CH_LPF_ODR_DIV_20 = 3, } lps22ch_lpfp_cfg_t; -int32_t lps22ch_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lps22ch_lp_bandwidth_set(const stmdev_ctx_t *ctx, lps22ch_lpfp_cfg_t val); -int32_t lps22ch_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lps22ch_lp_bandwidth_get(const stmdev_ctx_t *ctx, lps22ch_lpfp_cfg_t *val); typedef enum @@ -558,9 +556,9 @@ typedef enum LPS22CH_I2C_ENABLE = 0, LPS22CH_I2C_DISABLE = 1, } lps22ch_i2c_disable_t; -int32_t lps22ch_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lps22ch_i2c_interface_set(const stmdev_ctx_t *ctx, lps22ch_i2c_disable_t val); -int32_t lps22ch_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lps22ch_i2c_interface_get(const stmdev_ctx_t *ctx, lps22ch_i2c_disable_t *val); typedef enum @@ -568,9 +566,9 @@ typedef enum LPS22CH_I3C_ENABLE = 0, LPS22CH_I3C_DISABLE = 1, } lps22ch_i3c_disable_t; -int32_t lps22ch_i3c_interface_set(stmdev_ctx_t *ctx, +int32_t lps22ch_i3c_interface_set(const stmdev_ctx_t *ctx, lps22ch_i3c_disable_t val); -int32_t lps22ch_i3c_interface_get(stmdev_ctx_t *ctx, +int32_t lps22ch_i3c_interface_get(const stmdev_ctx_t *ctx, lps22ch_i3c_disable_t *val); typedef enum @@ -578,29 +576,29 @@ typedef enum LPS22CH_PULL_UP_DISCONNECT = 0, LPS22CH_PULL_UP_CONNECT = 1, } lps22ch_pu_en_t; -int32_t lps22ch_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t lps22ch_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, lps22ch_pu_en_t val); -int32_t lps22ch_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t lps22ch_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, lps22ch_pu_en_t *val); -int32_t lps22ch_sda_mode_set(stmdev_ctx_t *ctx, lps22ch_pu_en_t val); -int32_t lps22ch_sda_mode_get(stmdev_ctx_t *ctx, lps22ch_pu_en_t *val); +int32_t lps22ch_sda_mode_set(const stmdev_ctx_t *ctx, lps22ch_pu_en_t val); +int32_t lps22ch_sda_mode_get(const stmdev_ctx_t *ctx, lps22ch_pu_en_t *val); typedef enum { LPS22CH_SPI_4_WIRE = 0, LPS22CH_SPI_3_WIRE = 1, } lps22ch_sim_t; -int32_t lps22ch_spi_mode_set(stmdev_ctx_t *ctx, lps22ch_sim_t val); -int32_t lps22ch_spi_mode_get(stmdev_ctx_t *ctx, lps22ch_sim_t *val); +int32_t lps22ch_spi_mode_set(const stmdev_ctx_t *ctx, lps22ch_sim_t val); +int32_t lps22ch_spi_mode_get(const stmdev_ctx_t *ctx, lps22ch_sim_t *val); typedef enum { LPS22CH_INT_PULSED = 0, LPS22CH_INT_LATCHED = 1, } lps22ch_lir_t; -int32_t lps22ch_int_notification_set(stmdev_ctx_t *ctx, +int32_t lps22ch_int_notification_set(const stmdev_ctx_t *ctx, lps22ch_lir_t val); -int32_t lps22ch_int_notification_get(stmdev_ctx_t *ctx, +int32_t lps22ch_int_notification_get(const stmdev_ctx_t *ctx, lps22ch_lir_t *val); typedef enum @@ -608,22 +606,22 @@ typedef enum LPS22CH_PUSH_PULL = 0, LPS22CH_OPEN_DRAIN = 1, } lps22ch_pp_od_t; -int32_t lps22ch_pin_mode_set(stmdev_ctx_t *ctx, lps22ch_pp_od_t val); -int32_t lps22ch_pin_mode_get(stmdev_ctx_t *ctx, lps22ch_pp_od_t *val); +int32_t lps22ch_pin_mode_set(const stmdev_ctx_t *ctx, lps22ch_pp_od_t val); +int32_t lps22ch_pin_mode_get(const stmdev_ctx_t *ctx, lps22ch_pp_od_t *val); typedef enum { LPS22CH_ACTIVE_HIGH = 0, LPS22CH_ACTIVE_LOW = 1, } lps22ch_int_h_l_t; -int32_t lps22ch_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lps22ch_pin_polarity_set(const stmdev_ctx_t *ctx, lps22ch_int_h_l_t val); -int32_t lps22ch_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lps22ch_pin_polarity_get(const stmdev_ctx_t *ctx, lps22ch_int_h_l_t *val); -int32_t lps22ch_pin_int_route_set(stmdev_ctx_t *ctx, +int32_t lps22ch_pin_int_route_set(const stmdev_ctx_t *ctx, lps22ch_ctrl_reg3_t *val); -int32_t lps22ch_pin_int_route_get(stmdev_ctx_t *ctx, +int32_t lps22ch_pin_int_route_get(const stmdev_ctx_t *ctx, lps22ch_ctrl_reg3_t *val); typedef enum @@ -633,13 +631,13 @@ typedef enum LPS22CH_NEGATIVE = 2, LPS22CH_BOTH = 3, } lps22ch_pe_t; -int32_t lps22ch_int_on_threshold_set(stmdev_ctx_t *ctx, +int32_t lps22ch_int_on_threshold_set(const stmdev_ctx_t *ctx, lps22ch_pe_t val); -int32_t lps22ch_int_on_threshold_get(stmdev_ctx_t *ctx, +int32_t lps22ch_int_on_threshold_get(const stmdev_ctx_t *ctx, lps22ch_pe_t *val); -int32_t lps22ch_int_treshold_set(stmdev_ctx_t *ctx, uint16_t buff); -int32_t lps22ch_int_treshold_get(stmdev_ctx_t *ctx, uint16_t *buff); +int32_t lps22ch_int_threshold_set(const stmdev_ctx_t *ctx, uint16_t buff); +int32_t lps22ch_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *buff); typedef enum { @@ -651,38 +649,38 @@ typedef enum LPS22CH_BYPASS_TO_STREAM_MODE = 6, LPS22CH_STREAM_TO_FIFO_MODE = 7, } lps22ch_f_mode_t; -int32_t lps22ch_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lps22ch_fifo_mode_set(const stmdev_ctx_t *ctx, lps22ch_f_mode_t val); -int32_t lps22ch_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lps22ch_fifo_mode_get(const stmdev_ctx_t *ctx, lps22ch_f_mode_t *val); -int32_t lps22ch_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22ch_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22ch_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22ch_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22ch_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22ch_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22ch_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22ch_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22ch_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lps22ch_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lps22ch_fifo_src_get(stmdev_ctx_t *ctx, +int32_t lps22ch_fifo_src_get(const stmdev_ctx_t *ctx, lps22ch_fifo_status2_t *val); -int32_t lps22ch_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22ch_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22ch_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22ch_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22ch_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22ch_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22ch_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22ch_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22ch_fifo_ovr_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22ch_fifo_ovr_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22ch_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, +int32_t lps22ch_fifo_threshold_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22ch_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, +int32_t lps22ch_fifo_threshold_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22ch_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22ch_fifo_full_on_int_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22ch_fifo_full_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22ch_fifo_full_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val); /** * @} diff --git a/sensor/stmemsc/lps22df_STdC/driver/lps22df_reg.c b/sensor/stmemsc/lps22df_STdC/driver/lps22df_reg.c index c9a23364..727ffe47 100644 --- a/sensor/stmemsc/lps22df_STdC/driver/lps22df_reg.c +++ b/sensor/stmemsc/lps22df_STdC/driver/lps22df_reg.c @@ -46,12 +46,18 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lps22df_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, +int32_t __weak lps22df_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); + return ret; } @@ -65,12 +71,18 @@ int32_t __weak lps22df_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lps22df_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, +int32_t __weak lps22df_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); + return ret; } @@ -137,7 +149,7 @@ float_t lps22df_from_lsb_to_celsius(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_id_get(stmdev_ctx_t *ctx, lps22df_id_t *val) +int32_t lps22df_id_get(const stmdev_ctx_t *ctx, lps22df_id_t *val) { uint8_t reg; int32_t ret; @@ -156,7 +168,7 @@ int32_t lps22df_id_get(stmdev_ctx_t *ctx, lps22df_id_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_bus_mode_set(stmdev_ctx_t *ctx, lps22df_bus_mode_t *val) +int32_t lps22df_bus_mode_set(const stmdev_ctx_t *ctx, lps22df_bus_mode_t *val) { lps22df_i3c_if_ctrl_add_t i3c_if_ctrl_add; lps22df_if_ctrl_t if_ctrl; @@ -193,7 +205,7 @@ int32_t lps22df_bus_mode_set(stmdev_ctx_t *ctx, lps22df_bus_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_bus_mode_get(stmdev_ctx_t *ctx, lps22df_bus_mode_t *val) +int32_t lps22df_bus_mode_get(const stmdev_ctx_t *ctx, lps22df_bus_mode_t *val) { lps22df_i3c_if_ctrl_add_t i3c_if_ctrl_add; lps22df_if_ctrl_t if_ctrl; @@ -268,11 +280,13 @@ int32_t lps22df_bus_mode_get(stmdev_ctx_t *ctx, lps22df_bus_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_init_set(stmdev_ctx_t *ctx, lps22df_init_t val) +int32_t lps22df_init_set(const stmdev_ctx_t *ctx, lps22df_init_t val) { lps22df_ctrl_reg2_t ctrl_reg2; lps22df_ctrl_reg3_t ctrl_reg3; - uint8_t reg[2]; + lps22df_int_source_t int_src; + lps22df_stat_t status; + uint8_t reg[2], cnt = 0; int32_t ret; ret = lps22df_read_reg(ctx, LPS22DF_CTRL_REG2, reg, 2); @@ -287,11 +301,71 @@ int32_t lps22df_init_set(stmdev_ctx_t *ctx, lps22df_init_t val) ctrl_reg2.boot = PROPERTY_ENABLE; ret = lps22df_write_reg(ctx, LPS22DF_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) + { + break; + } + + do + { + ret = lps22df_read_reg(ctx, LPS22DF_INT_SOURCE, (uint8_t *)&int_src, 1); + if (ret != 0) + { + break; + } + + /* boot procedue ended correctly */ + if (int_src.boot_on == 0U) + { + break; + } + + if (ctx->mdelay != NULL) + { + ctx->mdelay(10); /* 10ms of boot time */ + } + } while (cnt++ < 5U); + + if (cnt >= 5U) + { + ret = -1; /* boot procedure failed */ + } + break; case LPS22DF_RESET: ctrl_reg2.swreset = PROPERTY_ENABLE; ret = lps22df_write_reg(ctx, LPS22DF_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); + if (ret != 0) + { + break; + } + + do + { + ret = lps22df_status_get(ctx, &status); + if (ret != 0) + { + break; + } + + /* sw-reset procedue ended correctly */ + if (status.sw_reset == 0U) + { + break; + } + + if (ctx->mdelay != NULL) + { + ctx->mdelay(1); /* should be 50 us */ + } + } while (cnt++ < 5U); + + if (cnt >= 5U) + { + ret = -1; /* sw-reset procedure failed */ + } + break; case LPS22DF_DRV_RDY: ctrl_reg2.bdu = PROPERTY_ENABLE; @@ -318,7 +392,7 @@ int32_t lps22df_init_set(stmdev_ctx_t *ctx, lps22df_init_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_status_get(stmdev_ctx_t *ctx, lps22df_stat_t *val) +int32_t lps22df_status_get(const stmdev_ctx_t *ctx, lps22df_stat_t *val) { lps22df_interrupt_cfg_t interrupt_cfg; lps22df_int_source_t int_source; @@ -361,7 +435,7 @@ int32_t lps22df_status_get(stmdev_ctx_t *ctx, lps22df_stat_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_pin_conf_set(stmdev_ctx_t *ctx, lps22df_pin_conf_t *val) +int32_t lps22df_pin_conf_set(const stmdev_ctx_t *ctx, lps22df_pin_conf_t *val) { lps22df_ctrl_reg3_t ctrl_reg3; lps22df_if_ctrl_t if_ctrl; @@ -397,7 +471,7 @@ int32_t lps22df_pin_conf_set(stmdev_ctx_t *ctx, lps22df_pin_conf_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_pin_conf_get(stmdev_ctx_t *ctx, lps22df_pin_conf_t *val) +int32_t lps22df_pin_conf_get(const stmdev_ctx_t *ctx, lps22df_pin_conf_t *val) { lps22df_ctrl_reg3_t ctrl_reg3; lps22df_if_ctrl_t if_ctrl; @@ -425,7 +499,7 @@ int32_t lps22df_pin_conf_get(stmdev_ctx_t *ctx, lps22df_pin_conf_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_all_sources_get(stmdev_ctx_t *ctx, +int32_t lps22df_all_sources_get(const stmdev_ctx_t *ctx, lps22df_all_sources_t *val) { lps22df_fifo_status2_t fifo_status2; @@ -466,7 +540,7 @@ int32_t lps22df_all_sources_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_mode_set(stmdev_ctx_t *ctx, lps22df_md_t *val) +int32_t lps22df_mode_set(const stmdev_ctx_t *ctx, lps22df_md_t *val) { lps22df_ctrl_reg1_t ctrl_reg1; lps22df_ctrl_reg2_t ctrl_reg2; @@ -501,7 +575,7 @@ int32_t lps22df_mode_set(stmdev_ctx_t *ctx, lps22df_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_mode_get(stmdev_ctx_t *ctx, lps22df_md_t *val) +int32_t lps22df_mode_get(const stmdev_ctx_t *ctx, lps22df_md_t *val) { lps22df_ctrl_reg1_t ctrl_reg1; lps22df_ctrl_reg2_t ctrl_reg2; @@ -607,7 +681,7 @@ int32_t lps22df_mode_get(stmdev_ctx_t *ctx, lps22df_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_trigger_sw(stmdev_ctx_t *ctx, lps22df_md_t *md) +int32_t lps22df_trigger_sw(const stmdev_ctx_t *ctx, lps22df_md_t *md) { lps22df_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -632,7 +706,7 @@ int32_t lps22df_trigger_sw(stmdev_ctx_t *ctx, lps22df_md_t *md) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_data_get(stmdev_ctx_t *ctx, lps22df_data_t *data) +int32_t lps22df_data_get(const stmdev_ctx_t *ctx, lps22df_data_t *data) { uint8_t buff[5]; int32_t ret; @@ -656,6 +730,48 @@ int32_t lps22df_data_get(stmdev_ctx_t *ctx, lps22df_data_t *data) return ret; } +/** + * @brief Pressure output value.[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lps22df_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff) +{ + int32_t ret; + uint8_t reg[3]; + + ret = lps22df_read_reg(ctx, LPS22DF_PRESS_OUT_XL, reg, 3); + *buff = reg[2]; + *buff = (*buff * 256U) + reg[1]; + *buff = (*buff * 256U) + reg[0]; + *buff *= 256U; + + return ret; +} + +/** + * @brief Temperature output value.[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lps22df_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) +{ + int32_t ret; + uint8_t reg[2]; + + ret = lps22df_read_reg(ctx, LPS22DF_TEMP_OUT_L, reg, 2); + *buff = (int16_t)reg[1]; + *buff = (*buff * 256) + (int16_t)reg[0]; + + return ret; +} + /** * @} * @@ -677,7 +793,7 @@ int32_t lps22df_data_get(stmdev_ctx_t *ctx, lps22df_data_t *data) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_fifo_mode_set(stmdev_ctx_t *ctx, lps22df_fifo_md_t *val) +int32_t lps22df_fifo_mode_set(const stmdev_ctx_t *ctx, lps22df_fifo_md_t *val) { lps22df_fifo_ctrl_t fifo_ctrl; lps22df_fifo_wtm_t fifo_wtm; @@ -720,7 +836,7 @@ int32_t lps22df_fifo_mode_set(stmdev_ctx_t *ctx, lps22df_fifo_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_fifo_mode_get(stmdev_ctx_t *ctx, lps22df_fifo_md_t *val) +int32_t lps22df_fifo_mode_get(const stmdev_ctx_t *ctx, lps22df_fifo_md_t *val) { lps22df_fifo_ctrl_t fifo_ctrl; lps22df_fifo_wtm_t fifo_wtm; @@ -770,7 +886,7 @@ int32_t lps22df_fifo_mode_get(stmdev_ctx_t *ctx, lps22df_fifo_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_fifo_level_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22df_fifo_level_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22df_fifo_status1_t fifo_status1; int32_t ret; @@ -792,7 +908,7 @@ int32_t lps22df_fifo_level_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_fifo_data_get(stmdev_ctx_t *ctx, uint8_t samp, lps22df_fifo_data_t *data) +int32_t lps22df_fifo_data_get(const stmdev_ctx_t *ctx, uint8_t samp, lps22df_fifo_data_t *data) { uint8_t fifo_data[3]; uint8_t i; @@ -832,7 +948,7 @@ int32_t lps22df_fifo_data_get(stmdev_ctx_t *ctx, uint8_t samp, lps22df_fifo_data * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_interrupt_mode_set(stmdev_ctx_t *ctx, +int32_t lps22df_interrupt_mode_set(const stmdev_ctx_t *ctx, lps22df_int_mode_t *val) { lps22df_interrupt_cfg_t interrupt_cfg; @@ -877,7 +993,7 @@ int32_t lps22df_interrupt_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_interrupt_mode_get(stmdev_ctx_t *ctx, +int32_t lps22df_interrupt_mode_get(const stmdev_ctx_t *ctx, lps22df_int_mode_t *val) { lps22df_interrupt_cfg_t interrupt_cfg; @@ -911,7 +1027,7 @@ int32_t lps22df_interrupt_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_pin_int_route_set(stmdev_ctx_t *ctx, +int32_t lps22df_pin_int_route_set(const stmdev_ctx_t *ctx, lps22df_pin_int_route_t *val) { lps22df_ctrl_reg4_t ctrl_reg4; @@ -938,7 +1054,7 @@ int32_t lps22df_pin_int_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_pin_int_route_get(stmdev_ctx_t *ctx, +int32_t lps22df_pin_int_route_get(const stmdev_ctx_t *ctx, lps22df_pin_int_route_t *val) { lps22df_ctrl_reg4_t ctrl_reg4; @@ -976,7 +1092,7 @@ int32_t lps22df_pin_int_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_int_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t lps22df_int_on_threshold_mode_set(const stmdev_ctx_t *ctx, lps22df_int_th_md_t *val) { lps22df_ctrl_reg4_t ctrl_reg4; @@ -1007,12 +1123,12 @@ int32_t lps22df_int_on_threshold_mode_set(stmdev_ctx_t *ctx, if (ret == 0) { - ret = lps22df_read_reg(ctx, LPS22DF_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); - if (ret == 0) - { - ctrl_reg4.int_en = PROPERTY_ENABLE; - ret = lps22df_write_reg(ctx, LPS22DF_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); - } + ret = lps22df_read_reg(ctx, LPS22DF_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + if (ret == 0) + { + ctrl_reg4.int_en = PROPERTY_ENABLE; + ret = lps22df_write_reg(ctx, LPS22DF_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1); + } } return ret; } @@ -1025,7 +1141,7 @@ int32_t lps22df_int_on_threshold_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_int_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t lps22df_int_on_threshold_mode_get(const stmdev_ctx_t *ctx, lps22df_int_th_md_t *val) { lps22df_interrupt_cfg_t interrupt_cfg; @@ -1069,7 +1185,7 @@ int32_t lps22df_int_on_threshold_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_reference_mode_set(stmdev_ctx_t *ctx, lps22df_ref_md_t *val) +int32_t lps22df_reference_mode_set(const stmdev_ctx_t *ctx, lps22df_ref_md_t *val) { lps22df_interrupt_cfg_t interrupt_cfg; int32_t ret; @@ -1099,7 +1215,7 @@ int32_t lps22df_reference_mode_set(stmdev_ctx_t *ctx, lps22df_ref_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_reference_mode_get(stmdev_ctx_t *ctx, lps22df_ref_md_t *val) +int32_t lps22df_reference_mode_get(const stmdev_ctx_t *ctx, lps22df_ref_md_t *val) { lps22df_interrupt_cfg_t interrupt_cfg; int32_t ret; @@ -1134,7 +1250,7 @@ int32_t lps22df_reference_mode_get(stmdev_ctx_t *ctx, lps22df_ref_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_opc_set(stmdev_ctx_t *ctx, int16_t val) +int32_t lps22df_opc_set(const stmdev_ctx_t *ctx, int16_t val) { uint8_t reg[2]; int32_t ret; @@ -1155,7 +1271,7 @@ int32_t lps22df_opc_set(stmdev_ctx_t *ctx, int16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22df_opc_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lps22df_opc_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t reg[2]; int32_t ret; diff --git a/sensor/stmemsc/lps22df_STdC/driver/lps22df_reg.h b/sensor/stmemsc/lps22df_STdC/driver/lps22df_reg.h index 696e09e1..bde22959 100644 --- a/sensor/stmemsc/lps22df_STdC/driver/lps22df_reg.h +++ b/sensor/stmemsc/lps22df_STdC/driver/lps22df_reg.h @@ -488,7 +488,7 @@ typedef union lps22df_status_t status; bitwise_t bitwise; uint8_t byte; -} lis2du12_reg_t; +} lps22df_reg_t; #ifndef __weak #define __weak __attribute__((weak)) @@ -503,9 +503,9 @@ typedef union * them with a custom implementation. */ -int32_t lps22df_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lps22df_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lps22df_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lps22df_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); extern float_t lps22df_from_lsb_to_hPa(int32_t lsb); @@ -515,32 +515,38 @@ typedef struct { uint8_t whoami; } lps22df_id_t; -int32_t lps22df_id_get(stmdev_ctx_t *ctx, lps22df_id_t *val); +int32_t lps22df_id_get(const stmdev_ctx_t *ctx, lps22df_id_t *val); + +typedef enum +{ + LPS22DF_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */ + LPS22DF_SPI_4W = 0x02, /* Only SPI: SDO / SDI separated pins */ + LPS22DF_SPI_3W = 0x03, /* Only SPI: SDO / SDI share the same pin */ + LPS22DF_INT_PIN_ON_I3C = 0x04, /* INT pin polarized as OUT with I3C */ +} lps22df_interface_t; + +typedef enum +{ + LPS22DF_AUTO = 0x00, /* bus mode select by HW (SPI 3W disable) */ + LPS22DF_ALWAYS_ON = 0x01, /* Only SPI: SDO / SDI separated pins */ +} lps22df_filter_t; + +typedef enum +{ + LPS22DF_IBI_50us = 0x0, + LPS22DF_IBI_2us = 0x1, + LPS22DF_IBI_1ms = 0x2, + LPS22DF_IBI_25ms = 0x3 +} lps22df_i3c_ibi_time_t; typedef struct { - enum - { - LPS22DF_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */ - LPS22DF_SPI_4W = 0x02, /* Only SPI: SDO / SDI separated pins */ - LPS22DF_SPI_3W = 0x03, /* Only SPI: SDO / SDI share the same pin */ - LPS22DF_INT_PIN_ON_I3C = 0x04, /* INT pin polarized as OUT with I3C */ - } interface; - enum - { - LPS22DF_AUTO = 0x00, /* bus mode select by HW (SPI 3W disable) */ - LPS22DF_ALWAYS_ON = 0x01, /* Only SPI: SDO / SDI separated pins */ - } filter; - enum - { - LPS22DF_IBI_50us = 0x0, - LPS22DF_IBI_2us = 0x1, - LPS22DF_IBI_1ms = 0x2, - LPS22DF_IBI_25ms = 0x3 - } i3c_ibi_time; + lps22df_interface_t interface; + lps22df_filter_t filter; + lps22df_i3c_ibi_time_t i3c_ibi_time; } lps22df_bus_mode_t; -int32_t lps22df_bus_mode_set(stmdev_ctx_t *ctx, lps22df_bus_mode_t *val); -int32_t lps22df_bus_mode_get(stmdev_ctx_t *ctx, lps22df_bus_mode_t *val); +int32_t lps22df_bus_mode_set(const stmdev_ctx_t *ctx, lps22df_bus_mode_t *val); +int32_t lps22df_bus_mode_get(const stmdev_ctx_t *ctx, lps22df_bus_mode_t *val); typedef enum { @@ -548,7 +554,7 @@ typedef enum LPS22DF_BOOT = 0x01, /* Restore calib. param. ( it takes 10ms ) */ LPS22DF_RESET = 0x02, /* Reset configuration registers */ } lps22df_init_t; -int32_t lps22df_init_set(stmdev_ctx_t *ctx, lps22df_init_t val); +int32_t lps22df_init_set(const stmdev_ctx_t *ctx, lps22df_init_t val); typedef struct { @@ -561,7 +567,7 @@ typedef struct uint8_t end_meas : 1; /* Single measurement is finished. */ uint8_t ref_done : 1; /* Auto-Zero value is set. */ } lps22df_stat_t; -int32_t lps22df_status_get(stmdev_ctx_t *ctx, lps22df_stat_t *val); +int32_t lps22df_status_get(const stmdev_ctx_t *ctx, lps22df_stat_t *val); typedef struct { @@ -571,8 +577,8 @@ typedef struct uint8_t sdo_pull_up : 1; /* 1 = pull-up enabled */ uint8_t cs_pull_up : 1; /* 1 = pull-up enabled */ } lps22df_pin_conf_t; -int32_t lps22df_pin_conf_set(stmdev_ctx_t *ctx, lps22df_pin_conf_t *val); -int32_t lps22df_pin_conf_get(stmdev_ctx_t *ctx, lps22df_pin_conf_t *val); +int32_t lps22df_pin_conf_set(const stmdev_ctx_t *ctx, lps22df_pin_conf_t *val); +int32_t lps22df_pin_conf_get(const stmdev_ctx_t *ctx, lps22df_pin_conf_t *val); typedef struct { @@ -585,44 +591,50 @@ typedef struct uint8_t fifo_ovr : 1; /* FIFO overrun */ uint8_t fifo_th : 1; /* FIFO threshold reached */ } lps22df_all_sources_t; -int32_t lps22df_all_sources_get(stmdev_ctx_t *ctx, lps22df_all_sources_t *val); +int32_t lps22df_all_sources_get(const stmdev_ctx_t *ctx, lps22df_all_sources_t *val); + +typedef enum +{ + LPS22DF_ONE_SHOT = 0x00, /* Device in power down till software trigger */ + LPS22DF_1Hz = 0x01, + LPS22DF_4Hz = 0x02, + LPS22DF_10Hz = 0x03, + LPS22DF_25Hz = 0x04, + LPS22DF_50Hz = 0x05, + LPS22DF_75Hz = 0x06, + LPS22DF_100Hz = 0x07, + LPS22DF_200Hz = 0x08, +} lps22df_odr_t; + +typedef enum +{ + LPS22DF_4_AVG = 0, + LPS22DF_8_AVG = 1, + LPS22DF_16_AVG = 2, + LPS22DF_32_AVG = 3, + LPS22DF_64_AVG = 4, + LPS22DF_128_AVG = 5, + LPS22DF_256_AVG = 6, + LPS22DF_512_AVG = 7, +} lps22df_avg_t; + +typedef enum +{ + LPS22DF_LPF_DISABLE = 0, + LPS22DF_LPF_ODR_DIV_4 = 1, + LPS22DF_LPF_ODR_DIV_9 = 3, +} lps22df_lpf_t; typedef struct { - enum - { - LPS22DF_ONE_SHOT = 0x00, /* Device in power down till software trigger */ - LPS22DF_1Hz = 0x01, - LPS22DF_4Hz = 0x02, - LPS22DF_10Hz = 0x03, - LPS22DF_25Hz = 0x04, - LPS22DF_50Hz = 0x05, - LPS22DF_75Hz = 0x06, - LPS22DF_100Hz = 0x07, - LPS22DF_200Hz = 0x08, - } odr; - enum - { - LPS22DF_4_AVG = 0, - LPS22DF_8_AVG = 1, - LPS22DF_16_AVG = 2, - LPS22DF_32_AVG = 3, - LPS22DF_64_AVG = 4, - LPS22DF_128_AVG = 5, - LPS22DF_256_AVG = 6, - LPS22DF_512_AVG = 7, - } avg; - enum - { - LPS22DF_LPF_DISABLE = 0, - LPS22DF_LPF_ODR_DIV_4 = 1, - LPS22DF_LPF_ODR_DIV_9 = 3, - } lpf; + lps22df_odr_t odr; + lps22df_avg_t avg; + lps22df_lpf_t lpf; } lps22df_md_t; -int32_t lps22df_mode_set(stmdev_ctx_t *ctx, lps22df_md_t *val); -int32_t lps22df_mode_get(stmdev_ctx_t *ctx, lps22df_md_t *val); +int32_t lps22df_mode_set(const stmdev_ctx_t *ctx, lps22df_md_t *val); +int32_t lps22df_mode_get(const stmdev_ctx_t *ctx, lps22df_md_t *val); -int32_t lps22df_trigger_sw(stmdev_ctx_t *ctx, lps22df_md_t *md); +int32_t lps22df_trigger_sw(const stmdev_ctx_t *ctx, lps22df_md_t *md); typedef struct { @@ -637,32 +649,37 @@ typedef struct int16_t raw; } heat; } lps22df_data_t; -int32_t lps22df_data_get(stmdev_ctx_t *ctx, lps22df_data_t *data); +int32_t lps22df_data_get(const stmdev_ctx_t *ctx, lps22df_data_t *data); + +int32_t lps22df_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff); +int32_t lps22df_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff); + +typedef enum +{ + LPS22DF_BYPASS = 0, + LPS22DF_FIFO = 1, + LPS22DF_STREAM = 2, + LPS22DF_STREAM_TO_FIFO = 7, /* Dynamic-Stream, FIFO on Trigger */ + LPS22DF_BYPASS_TO_STREAM = 6, /* Bypass, Dynamic-Stream on Trigger */ + LPS22DF_BYPASS_TO_FIFO = 5, /* Bypass, FIFO on Trigger */ +} lps22df_operation_t; typedef struct { - enum - { - LPS22DF_BYPASS = 0, - LPS22DF_FIFO = 1, - LPS22DF_STREAM = 2, - LPS22DF_STREAM_TO_FIFO = 7, /* Dynamic-Stream, FIFO on Trigger */ - LPS22DF_BYPASS_TO_STREAM = 6, /* Bypass, Dynamic-Stream on Trigger */ - LPS22DF_BYPASS_TO_FIFO = 5, /* Bypass, FIFO on Trigger */ - } operation; + lps22df_operation_t operation; uint8_t watermark; /* (0 disable) max 128.*/ } lps22df_fifo_md_t; -int32_t lps22df_fifo_mode_set(stmdev_ctx_t *ctx, lps22df_fifo_md_t *val); -int32_t lps22df_fifo_mode_get(stmdev_ctx_t *ctx, lps22df_fifo_md_t *val); +int32_t lps22df_fifo_mode_set(const stmdev_ctx_t *ctx, lps22df_fifo_md_t *val); +int32_t lps22df_fifo_mode_get(const stmdev_ctx_t *ctx, lps22df_fifo_md_t *val); -int32_t lps22df_fifo_level_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22df_fifo_level_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { float_t hpa; int32_t raw; } lps22df_fifo_data_t; -int32_t lps22df_fifo_data_get(stmdev_ctx_t *ctx, uint8_t samp, lps22df_fifo_data_t *data); +int32_t lps22df_fifo_data_get(const stmdev_ctx_t *ctx, uint8_t samp, lps22df_fifo_data_t *data); typedef struct { @@ -670,8 +687,8 @@ typedef struct uint8_t active_low : 1; /* 1 = active low / 0 = active high */ uint8_t drdy_latched : 1; /* pulsed ~5 μs with enabled drdy_pres " */ } lps22df_int_mode_t; -int32_t lps22df_interrupt_mode_set(stmdev_ctx_t *ctx, lps22df_int_mode_t *val); -int32_t lps22df_interrupt_mode_get(stmdev_ctx_t *ctx, lps22df_int_mode_t *val); +int32_t lps22df_interrupt_mode_set(const stmdev_ctx_t *ctx, lps22df_int_mode_t *val); +int32_t lps22df_interrupt_mode_get(const stmdev_ctx_t *ctx, lps22df_int_mode_t *val); typedef struct { @@ -680,9 +697,9 @@ typedef struct uint8_t fifo_ovr : 1; /* FIFO overrun */ uint8_t fifo_full : 1; /* FIFO full */ } lps22df_pin_int_route_t; -int32_t lps22df_pin_int_route_set(stmdev_ctx_t *ctx, +int32_t lps22df_pin_int_route_set(const stmdev_ctx_t *ctx, lps22df_pin_int_route_t *val); -int32_t lps22df_pin_int_route_get(stmdev_ctx_t *ctx, +int32_t lps22df_pin_int_route_get(const stmdev_ctx_t *ctx, lps22df_pin_int_route_t *val); typedef struct @@ -691,28 +708,30 @@ typedef struct uint8_t over_th : 1; /* Pressure data over threshold event */ uint8_t under_th : 1; /* Pressure data under threshold event */ } lps22df_int_th_md_t; -int32_t lps22df_int_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t lps22df_int_on_threshold_mode_set(const stmdev_ctx_t *ctx, lps22df_int_th_md_t *val); -int32_t lps22df_int_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t lps22df_int_on_threshold_mode_get(const stmdev_ctx_t *ctx, lps22df_int_th_md_t *val); +typedef enum +{ + LPS22DF_OUT_AND_INTERRUPT = 0, + LPS22DF_ONLY_INTERRUPT = 1, + LPS22DF_RST_REFS = 2, +} lps22df_apply_ref_t; + typedef struct { - enum - { - LPS22DF_OUT_AND_INTERRUPT = 0, - LPS22DF_ONLY_INTERRUPT = 1, - LPS22DF_RST_REFS = 2, - } apply_ref; + lps22df_apply_ref_t apply_ref; uint8_t get_ref : 1; /* Use current pressure value as reference */ } lps22df_ref_md_t; -int32_t lps22df_reference_mode_set(stmdev_ctx_t *ctx, +int32_t lps22df_reference_mode_set(const stmdev_ctx_t *ctx, lps22df_ref_md_t *val); -int32_t lps22df_reference_mode_get(stmdev_ctx_t *ctx, +int32_t lps22df_reference_mode_get(const stmdev_ctx_t *ctx, lps22df_ref_md_t *val); -int32_t lps22df_opc_set(stmdev_ctx_t *ctx, int16_t val); -int32_t lps22df_opc_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lps22df_opc_set(const stmdev_ctx_t *ctx, int16_t val); +int32_t lps22df_opc_get(const stmdev_ctx_t *ctx, int16_t *val); /** *@} diff --git a/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.c b/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.c index eaef600e..1c63c65e 100644 --- a/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.c +++ b/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.c @@ -45,12 +45,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lps22hb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lps22hb_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -66,12 +71,17 @@ int32_t __weak lps22hb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lps22hb_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lps22hb_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -91,7 +101,26 @@ int32_t __weak lps22hb_write_reg(stmdev_ctx_t *ctx, uint8_t reg, float_t lps22hb_from_lsb_to_hpa(int32_t lsb) { - return ((float_t)lsb / 1048576.0f); + return ((float_t)lsb / 4096.0f); +} + +float_t lps22hb_from_lsb_to_kpa(int32_t lsb) +{ + return lps22hb_from_lsb_to_hpa(lsb) / 10.0f; +} + +float_t lps22hb_from_lsb_to_psi(int32_t lsb) +{ + return lps22hb_from_lsb_to_hpa(lsb) * 0.0145038f; +} + +float_t lps22hb_from_lsb_to_altitude(int32_t lsb) +{ + float_t atmospheric = lps22hb_from_lsb_to_hpa(lsb); + // The altitude in meters can be calculated with the + // international barometric formula. + // Average sea level pressure is 1013.25 hPa. + return 44330.0 * (1.0 - pow(atmospheric / 1013.25f, (1.0 / 5.255))); } float_t lps22hb_from_lsb_to_degc(int16_t lsb) @@ -122,7 +151,7 @@ float_t lps22hb_from_lsb_to_degc(int16_t lsb) * */ -int32_t lps22hb_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22hb_autozero_rst_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hb_interrupt_cfg_t interrupt_cfg; int32_t ret; @@ -148,7 +177,7 @@ int32_t lps22hb_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hb_autozero_rst_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_interrupt_cfg_t interrupt_cfg; int32_t ret; @@ -168,7 +197,7 @@ int32_t lps22hb_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_autozero_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22hb_autozero_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hb_interrupt_cfg_t interrupt_cfg; int32_t ret; @@ -194,7 +223,7 @@ int32_t lps22hb_autozero_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_autozero_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hb_autozero_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_interrupt_cfg_t interrupt_cfg; int32_t ret; @@ -214,7 +243,7 @@ int32_t lps22hb_autozero_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_pressure_snap_rst_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22hb_pressure_snap_rst_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hb_interrupt_cfg_t interrupt_cfg; int32_t ret; @@ -240,7 +269,7 @@ int32_t lps22hb_pressure_snap_rst_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_pressure_snap_rst_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hb_pressure_snap_rst_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_interrupt_cfg_t interrupt_cfg; int32_t ret; @@ -260,7 +289,7 @@ int32_t lps22hb_pressure_snap_rst_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22hb_pressure_snap_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hb_interrupt_cfg_t interrupt_cfg; int32_t ret; @@ -286,7 +315,7 @@ int32_t lps22hb_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hb_pressure_snap_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_interrupt_cfg_t interrupt_cfg; int32_t ret; @@ -306,7 +335,7 @@ int32_t lps22hb_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22hb_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hb_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -330,7 +359,7 @@ int32_t lps22hb_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hb_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -349,7 +378,7 @@ int32_t lps22hb_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_low_pass_filter_mode_set(stmdev_ctx_t *ctx, +int32_t lps22hb_low_pass_filter_mode_set(const stmdev_ctx_t *ctx, lps22hb_lpfp_t val) { lps22hb_ctrl_reg1_t ctrl_reg1; @@ -374,7 +403,7 @@ int32_t lps22hb_low_pass_filter_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_low_pass_filter_mode_get(stmdev_ctx_t *ctx, +int32_t lps22hb_low_pass_filter_mode_get(const stmdev_ctx_t *ctx, lps22hb_lpfp_t *val) { lps22hb_ctrl_reg1_t ctrl_reg1; @@ -412,7 +441,7 @@ int32_t lps22hb_low_pass_filter_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_data_rate_set(stmdev_ctx_t *ctx, lps22hb_odr_t val) +int32_t lps22hb_data_rate_set(const stmdev_ctx_t *ctx, lps22hb_odr_t val) { lps22hb_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -436,7 +465,7 @@ int32_t lps22hb_data_rate_set(stmdev_ctx_t *ctx, lps22hb_odr_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_data_rate_get(stmdev_ctx_t *ctx, lps22hb_odr_t *val) +int32_t lps22hb_data_rate_get(const stmdev_ctx_t *ctx, lps22hb_odr_t *val) { lps22hb_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -485,7 +514,7 @@ int32_t lps22hb_data_rate_get(stmdev_ctx_t *ctx, lps22hb_odr_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22hb_one_shoot_trigger_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hb_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -509,7 +538,7 @@ int32_t lps22hb_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hb_one_shoot_trigger_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -530,7 +559,7 @@ int32_t lps22hb_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_pressure_ref_set(stmdev_ctx_t *ctx, int32_t val) +int32_t lps22hb_pressure_ref_set(const stmdev_ctx_t *ctx, int32_t val) { uint8_t buff[3]; int32_t ret; @@ -554,7 +583,7 @@ int32_t lps22hb_pressure_ref_set(stmdev_ctx_t *ctx, int32_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_pressure_ref_get(stmdev_ctx_t *ctx, int32_t *val) +int32_t lps22hb_pressure_ref_get(const stmdev_ctx_t *ctx, int32_t *val) { uint8_t buff[3]; int32_t ret; @@ -576,7 +605,7 @@ int32_t lps22hb_pressure_ref_get(stmdev_ctx_t *ctx, int32_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val) +int32_t lps22hb_pressure_offset_set(const stmdev_ctx_t *ctx, int16_t val) { uint8_t buff[2]; int32_t ret; @@ -597,7 +626,7 @@ int32_t lps22hb_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lps22hb_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -617,7 +646,7 @@ int32_t lps22hb_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_press_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hb_press_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_status_t status; int32_t ret; @@ -636,7 +665,7 @@ int32_t lps22hb_press_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hb_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_status_t status; int32_t ret; @@ -647,6 +676,27 @@ int32_t lps22hb_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) return ret; } +/** + * @brief Pressure and temperature data available.[get] + * + * @param ctx Read / write interface definitions + * @param press_val Change the values of p_da in reg STATUS + * @param temp_val Change the values of t_da in reg STATUS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lps22hb_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *press_val, uint8_t *temp_val) +{ + lps22hb_status_t status; + int32_t ret; + + ret = lps22hb_read_reg(ctx, LPS22HB_STATUS, (uint8_t *)&status, 1); + *press_val = status.p_da; + *temp_val = status.t_da; + + return ret; +} + /** * @brief Pressure data overrun.[get] * @@ -655,7 +705,7 @@ int32_t lps22hb_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_press_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hb_press_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_status_t status; int32_t ret; @@ -674,7 +724,7 @@ int32_t lps22hb_press_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hb_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_status_t status; int32_t ret; @@ -693,7 +743,7 @@ int32_t lps22hb_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff) +int32_t lps22hb_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff) { uint8_t reg[3]; int32_t ret; @@ -715,7 +765,7 @@ int32_t lps22hb_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff) +int32_t lps22hb_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) { uint8_t reg[2]; int32_t ret; @@ -727,6 +777,52 @@ int32_t lps22hb_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff) return ret; } +/** + * @defgroup LPS22HB_FIFO_Output_Data + * @brief These functions convert FIFO output data to seperate + * (pressure, temperautre) fields. + * @{ + * + */ + +int32_t lps22hb_fifo_output_data_to_raw_pressure(lps22hb_fifo_output_data_t *val) +{ + int32_t pressure = val->bytes[2]; + pressure = (pressure * 256) + val->bytes[1]; + return (pressure * 256) + val->bytes[0]; +} + +int16_t lps22hb_fifo_output_data_to_raw_temperature(lps22hb_fifo_output_data_t *val) +{ + int16_t temperature = val->bytes[4]; + return (temperature * 256) + val->bytes[3]; +} + +/** + * @} + * + */ + +/** + * @brief Burst read fifo output data. + * + * @param ctx Read / write interface definitions + * @param buff Buffer that stores data read. + * @param len How many pressure-temperature pairs to read from the fifo. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lps22hb_fifo_output_data_burst_get(const stmdev_ctx_t *ctx, + lps22hb_fifo_output_data_t *buff, uint8_t len) +{ + if (len > 32) + { + len = 32; + } + return lps22hb_read_reg(ctx, LPS22HB_PRESS_OUT_XL, (uint8_t *)&buff[0], + len * sizeof(lps22hb_fifo_output_data_t)); +} + /** * @brief Low-pass filter reset register. If the LPFP is active, in * order to avoid the transitory phase, the filter can be @@ -738,7 +834,7 @@ int32_t lps22hb_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_low_pass_rst_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lps22hb_low_pass_rst_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -767,7 +863,7 @@ int32_t lps22hb_low_pass_rst_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lps22hb_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -784,7 +880,7 @@ int32_t lps22hb_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22hb_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hb_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -808,7 +904,7 @@ int32_t lps22hb_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hb_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -827,7 +923,7 @@ int32_t lps22hb_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22hb_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hb_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -851,7 +947,7 @@ int32_t lps22hb_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hb_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -870,7 +966,7 @@ int32_t lps22hb_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_low_power_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22hb_low_power_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hb_res_conf_t res_conf; int32_t ret; @@ -894,7 +990,7 @@ int32_t lps22hb_low_power_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_low_power_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hb_low_power_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_res_conf_t res_conf; int32_t ret; @@ -913,7 +1009,7 @@ int32_t lps22hb_low_power_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_boot_status_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hb_boot_status_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_int_source_t int_source; int32_t ret; @@ -933,7 +1029,7 @@ int32_t lps22hb_boot_status_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_dev_status_get(stmdev_ctx_t *ctx, +int32_t lps22hb_dev_status_get(const stmdev_ctx_t *ctx, lps22hb_dev_stat_t *val) { int32_t ret; @@ -963,7 +1059,7 @@ int32_t lps22hb_dev_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_sign_of_int_threshold_set(stmdev_ctx_t *ctx, +int32_t lps22hb_sign_of_int_threshold_set(const stmdev_ctx_t *ctx, lps22hb_pe_t val) { lps22hb_interrupt_cfg_t interrupt_cfg; @@ -990,7 +1086,7 @@ int32_t lps22hb_sign_of_int_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_sign_of_int_threshold_get(stmdev_ctx_t *ctx, +int32_t lps22hb_sign_of_int_threshold_get(const stmdev_ctx_t *ctx, lps22hb_pe_t *val) { lps22hb_interrupt_cfg_t interrupt_cfg; @@ -1034,7 +1130,7 @@ int32_t lps22hb_sign_of_int_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_int_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lps22hb_int_notification_mode_set(const stmdev_ctx_t *ctx, lps22hb_lir_t val) { lps22hb_interrupt_cfg_t interrupt_cfg; @@ -1062,7 +1158,7 @@ int32_t lps22hb_int_notification_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_int_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lps22hb_int_notification_mode_get(const stmdev_ctx_t *ctx, lps22hb_lir_t *val) { lps22hb_interrupt_cfg_t interrupt_cfg; @@ -1097,7 +1193,7 @@ int32_t lps22hb_int_notification_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_int_generation_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22hb_int_generation_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hb_interrupt_cfg_t interrupt_cfg; int32_t ret; @@ -1123,7 +1219,7 @@ int32_t lps22hb_int_generation_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hb_int_generation_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_interrupt_cfg_t interrupt_cfg; int32_t ret; @@ -1143,7 +1239,7 @@ int32_t lps22hb_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_int_threshold_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lps22hb_int_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -1163,7 +1259,7 @@ int32_t lps22hb_int_threshold_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_int_threshold_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lps22hb_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1183,7 +1279,7 @@ int32_t lps22hb_int_threshold_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_int_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lps22hb_int_pin_mode_set(const stmdev_ctx_t *ctx, lps22hb_int_s_t val) { lps22hb_ctrl_reg3_t ctrl_reg3; @@ -1208,7 +1304,7 @@ int32_t lps22hb_int_pin_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_int_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lps22hb_int_pin_mode_get(const stmdev_ctx_t *ctx, lps22hb_int_s_t *val) { lps22hb_ctrl_reg3_t ctrl_reg3; @@ -1250,7 +1346,7 @@ int32_t lps22hb_int_pin_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_drdy_on_int_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22hb_drdy_on_int_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hb_ctrl_reg3_t ctrl_reg3; int32_t ret; @@ -1274,7 +1370,7 @@ int32_t lps22hb_drdy_on_int_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hb_drdy_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_ctrl_reg3_t ctrl_reg3; int32_t ret; @@ -1293,7 +1389,7 @@ int32_t lps22hb_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22hb_fifo_ovr_on_int_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hb_ctrl_reg3_t ctrl_reg3; int32_t ret; @@ -1317,7 +1413,7 @@ int32_t lps22hb_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hb_fifo_ovr_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_ctrl_reg3_t ctrl_reg3; int32_t ret; @@ -1336,7 +1432,7 @@ int32_t lps22hb_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, +int32_t lps22hb_fifo_threshold_on_int_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hb_ctrl_reg3_t ctrl_reg3; @@ -1361,7 +1457,7 @@ int32_t lps22hb_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, +int32_t lps22hb_fifo_threshold_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_ctrl_reg3_t ctrl_reg3; @@ -1381,7 +1477,7 @@ int32_t lps22hb_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22hb_fifo_full_on_int_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hb_ctrl_reg3_t ctrl_reg3; int32_t ret; @@ -1405,7 +1501,7 @@ int32_t lps22hb_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_fifo_full_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hb_fifo_full_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_ctrl_reg3_t ctrl_reg3; int32_t ret; @@ -1424,7 +1520,7 @@ int32_t lps22hb_fifo_full_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_pin_mode_set(stmdev_ctx_t *ctx, lps22hb_pp_od_t val) +int32_t lps22hb_pin_mode_set(const stmdev_ctx_t *ctx, lps22hb_pp_od_t val) { lps22hb_ctrl_reg3_t ctrl_reg3; int32_t ret; @@ -1448,7 +1544,7 @@ int32_t lps22hb_pin_mode_set(stmdev_ctx_t *ctx, lps22hb_pp_od_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_pin_mode_get(stmdev_ctx_t *ctx, lps22hb_pp_od_t *val) +int32_t lps22hb_pin_mode_get(const stmdev_ctx_t *ctx, lps22hb_pp_od_t *val) { lps22hb_ctrl_reg3_t ctrl_reg3; int32_t ret; @@ -1481,7 +1577,7 @@ int32_t lps22hb_pin_mode_get(stmdev_ctx_t *ctx, lps22hb_pp_od_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_int_polarity_set(stmdev_ctx_t *ctx, +int32_t lps22hb_int_polarity_set(const stmdev_ctx_t *ctx, lps22hb_int_h_l_t val) { lps22hb_ctrl_reg3_t ctrl_reg3; @@ -1506,7 +1602,7 @@ int32_t lps22hb_int_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_int_polarity_get(stmdev_ctx_t *ctx, +int32_t lps22hb_int_polarity_get(const stmdev_ctx_t *ctx, lps22hb_int_h_l_t *val) { lps22hb_ctrl_reg3_t ctrl_reg3; @@ -1540,7 +1636,7 @@ int32_t lps22hb_int_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_int_source_get(stmdev_ctx_t *ctx, +int32_t lps22hb_int_source_get(const stmdev_ctx_t *ctx, lps22hb_int_source_t *val) { int32_t ret; @@ -1558,7 +1654,7 @@ int32_t lps22hb_int_source_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_int_on_press_high_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hb_int_on_press_high_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_int_source_t int_source; int32_t ret; @@ -1578,7 +1674,7 @@ int32_t lps22hb_int_on_press_high_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_int_on_press_low_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hb_int_on_press_low_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_int_source_t int_source; int32_t ret; @@ -1598,7 +1694,7 @@ int32_t lps22hb_int_on_press_low_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_interrupt_event_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hb_interrupt_event_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_int_source_t int_source; int32_t ret; @@ -1631,7 +1727,7 @@ int32_t lps22hb_interrupt_event_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx, +int32_t lps22hb_stop_on_fifo_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hb_ctrl_reg2_t ctrl_reg2; @@ -1656,7 +1752,7 @@ int32_t lps22hb_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_stop_on_fifo_threshold_get(stmdev_ctx_t *ctx, +int32_t lps22hb_stop_on_fifo_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_ctrl_reg2_t ctrl_reg2; @@ -1676,7 +1772,7 @@ int32_t lps22hb_stop_on_fifo_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_fifo_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22hb_fifo_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hb_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -1700,7 +1796,7 @@ int32_t lps22hb_fifo_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_fifo_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hb_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -1719,7 +1815,7 @@ int32_t lps22hb_fifo_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22hb_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hb_fifo_ctrl_t fifo_ctrl; int32_t ret; @@ -1743,7 +1839,7 @@ int32_t lps22hb_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hb_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_fifo_ctrl_t fifo_ctrl; int32_t ret; @@ -1762,7 +1858,7 @@ int32_t lps22hb_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_fifo_mode_set(stmdev_ctx_t *ctx, lps22hb_f_mode_t val) +int32_t lps22hb_fifo_mode_set(const stmdev_ctx_t *ctx, lps22hb_f_mode_t val) { lps22hb_fifo_ctrl_t fifo_ctrl; int32_t ret; @@ -1786,7 +1882,7 @@ int32_t lps22hb_fifo_mode_set(stmdev_ctx_t *ctx, lps22hb_f_mode_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lps22hb_fifo_mode_get(const stmdev_ctx_t *ctx, lps22hb_f_mode_t *val) { lps22hb_fifo_ctrl_t fifo_ctrl; @@ -1840,7 +1936,7 @@ int32_t lps22hb_fifo_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hb_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_fifo_status_t fifo_status; int32_t ret; @@ -1860,7 +1956,7 @@ int32_t lps22hb_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hb_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_fifo_status_t fifo_status; int32_t ret; @@ -1880,7 +1976,7 @@ int32_t lps22hb_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hb_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_fifo_status_t fifo_status; int32_t ret; @@ -1913,7 +2009,7 @@ int32_t lps22hb_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_spi_mode_set(stmdev_ctx_t *ctx, lps22hb_sim_t val) +int32_t lps22hb_spi_mode_set(const stmdev_ctx_t *ctx, lps22hb_sim_t val) { lps22hb_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -1937,7 +2033,7 @@ int32_t lps22hb_spi_mode_set(stmdev_ctx_t *ctx, lps22hb_sim_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_spi_mode_get(stmdev_ctx_t *ctx, lps22hb_sim_t *val) +int32_t lps22hb_spi_mode_get(const stmdev_ctx_t *ctx, lps22hb_sim_t *val) { lps22hb_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -1970,7 +2066,7 @@ int32_t lps22hb_spi_mode_get(stmdev_ctx_t *ctx, lps22hb_sim_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lps22hb_i2c_interface_set(const stmdev_ctx_t *ctx, lps22hb_i2c_dis_t val) { lps22hb_ctrl_reg2_t ctrl_reg2; @@ -1995,7 +2091,7 @@ int32_t lps22hb_i2c_interface_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lps22hb_i2c_interface_get(const stmdev_ctx_t *ctx, lps22hb_i2c_dis_t *val) { lps22hb_ctrl_reg2_t ctrl_reg2; @@ -2030,7 +2126,7 @@ int32_t lps22hb_i2c_interface_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_auto_add_inc_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22hb_auto_add_inc_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hb_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -2055,7 +2151,7 @@ int32_t lps22hb_auto_add_inc_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps22hb_auto_add_inc_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hb_auto_add_inc_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hb_ctrl_reg2_t ctrl_reg2; int32_t ret; diff --git a/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.h b/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.h index b100480a..afecd8b5 100644 --- a/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.h +++ b/sensor/stmemsc/lps22hb_STdC/driver/lps22hb_reg.h @@ -113,7 +113,7 @@ typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); -typedef struct +typedef struct _stmdev_ctx_t { /** Component mandatory fields **/ stmdev_write_ptr write_reg; @@ -409,32 +409,38 @@ typedef union * them with a custom implementation. */ -int32_t lps22hb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lps22hb_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lps22hb_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lps22hb_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); float_t lps22hb_from_lsb_to_hpa(int32_t lsb); +float_t lps22hb_from_lsb_to_kpa(int32_t lsb); + +float_t lps22hb_from_lsb_to_psi(int32_t lsb); + +float_t lps22hb_from_lsb_to_altitude(int32_t lsb); + float_t lps22hb_from_lsb_to_degc(int16_t lsb); -int32_t lps22hb_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hb_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hb_autozero_rst_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22hb_autozero_rst_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hb_autozero_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hb_autozero_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hb_autozero_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22hb_autozero_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hb_pressure_snap_rst_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hb_pressure_snap_rst_get(stmdev_ctx_t *ctx, +int32_t lps22hb_pressure_snap_rst_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22hb_pressure_snap_rst_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hb_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hb_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hb_pressure_snap_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22hb_pressure_snap_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hb_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hb_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lps22hb_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22hb_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -443,9 +449,9 @@ typedef enum LPS22HB_LPF_ODR_DIV_9 = 2, LPS22HB_LPF_ODR_DIV_20 = 3, } lps22hb_lpfp_t; -int32_t lps22hb_low_pass_filter_mode_set(stmdev_ctx_t *ctx, +int32_t lps22hb_low_pass_filter_mode_set(const stmdev_ctx_t *ctx, lps22hb_lpfp_t val); -int32_t lps22hb_low_pass_filter_mode_get(stmdev_ctx_t *ctx, +int32_t lps22hb_low_pass_filter_mode_get(const stmdev_ctx_t *ctx, lps22hb_lpfp_t *val); typedef enum @@ -457,52 +463,66 @@ typedef enum LPS22HB_ODR_50_Hz = 4, LPS22HB_ODR_75_Hz = 5, } lps22hb_odr_t; -int32_t lps22hb_data_rate_set(stmdev_ctx_t *ctx, lps22hb_odr_t val); -int32_t lps22hb_data_rate_get(stmdev_ctx_t *ctx, lps22hb_odr_t *val); +int32_t lps22hb_data_rate_set(const stmdev_ctx_t *ctx, lps22hb_odr_t val); +int32_t lps22hb_data_rate_get(const stmdev_ctx_t *ctx, lps22hb_odr_t *val); -int32_t lps22hb_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hb_one_shoot_trigger_get(stmdev_ctx_t *ctx, +int32_t lps22hb_one_shoot_trigger_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22hb_one_shoot_trigger_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hb_pressure_ref_set(stmdev_ctx_t *ctx, int32_t val); -int32_t lps22hb_pressure_ref_get(stmdev_ctx_t *ctx, int32_t *val); +int32_t lps22hb_pressure_ref_set(const stmdev_ctx_t *ctx, int32_t val); +int32_t lps22hb_pressure_ref_get(const stmdev_ctx_t *ctx, int32_t *val); + +int32_t lps22hb_pressure_offset_set(const stmdev_ctx_t *ctx, int16_t val); +int32_t lps22hb_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lps22hb_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val); -int32_t lps22hb_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lps22hb_press_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hb_press_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hb_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hb_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hb_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *press_val, uint8_t *temp_val); -int32_t lps22hb_press_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hb_press_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lps22hb_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lps22hb_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff); + +int32_t lps22hb_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff); + +typedef struct __attribute__((packed)) _lps22hb_fifo_output_data_t +{ + uint8_t bytes[5]; +} lps22hb_fifo_output_data_t; -int32_t lps22hb_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hb_fifo_output_data_to_raw_pressure(lps22hb_fifo_output_data_t *val); -int32_t lps22hb_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff); +int16_t lps22hb_fifo_output_data_to_raw_temperature(lps22hb_fifo_output_data_t *val); -int32_t lps22hb_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff); +int32_t lps22hb_fifo_output_data_burst_get(const stmdev_ctx_t *ctx, + lps22hb_fifo_output_data_t *buff, uint8_t len); -int32_t lps22hb_low_pass_rst_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lps22hb_low_pass_rst_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lps22hb_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lps22hb_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lps22hb_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hb_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hb_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22hb_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hb_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hb_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hb_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22hb_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hb_low_power_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hb_low_power_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hb_low_power_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22hb_low_power_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hb_boot_status_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hb_boot_status_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { lps22hb_fifo_status_t fifo_status; lps22hb_status_t status; } lps22hb_dev_stat_t; -int32_t lps22hb_dev_status_get(stmdev_ctx_t *ctx, +int32_t lps22hb_dev_status_get(const stmdev_ctx_t *ctx, lps22hb_dev_stat_t *val); typedef enum @@ -512,9 +532,9 @@ typedef enum LPS22HB_NEGATIVE = 2, LPS22HB_BOTH = 3, } lps22hb_pe_t; -int32_t lps22hb_sign_of_int_threshold_set(stmdev_ctx_t *ctx, +int32_t lps22hb_sign_of_int_threshold_set(const stmdev_ctx_t *ctx, lps22hb_pe_t val); -int32_t lps22hb_sign_of_int_threshold_get(stmdev_ctx_t *ctx, +int32_t lps22hb_sign_of_int_threshold_get(const stmdev_ctx_t *ctx, lps22hb_pe_t *val); typedef enum @@ -522,16 +542,16 @@ typedef enum LPS22HB_INT_PULSED = 0, LPS22HB_INT_LATCHED = 1, } lps22hb_lir_t; -int32_t lps22hb_int_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lps22hb_int_notification_mode_set(const stmdev_ctx_t *ctx, lps22hb_lir_t val); -int32_t lps22hb_int_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lps22hb_int_notification_mode_get(const stmdev_ctx_t *ctx, lps22hb_lir_t *val); -int32_t lps22hb_int_generation_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hb_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hb_int_generation_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22hb_int_generation_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hb_int_threshold_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lps22hb_int_threshold_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lps22hb_int_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lps22hb_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum { @@ -540,63 +560,63 @@ typedef enum LPS22HB_LOW_PRES_INT = 2, LPS22HB_EVERY_PRES_INT = 3, } lps22hb_int_s_t; -int32_t lps22hb_int_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lps22hb_int_pin_mode_set(const stmdev_ctx_t *ctx, lps22hb_int_s_t val); -int32_t lps22hb_int_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lps22hb_int_pin_mode_get(const stmdev_ctx_t *ctx, lps22hb_int_s_t *val); -int32_t lps22hb_drdy_on_int_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hb_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hb_drdy_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22hb_drdy_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hb_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hb_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hb_fifo_ovr_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22hb_fifo_ovr_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hb_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, +int32_t lps22hb_fifo_threshold_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hb_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, +int32_t lps22hb_fifo_threshold_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hb_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hb_fifo_full_on_int_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hb_fifo_full_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22hb_fifo_full_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LPS22HB_PUSH_PULL = 0, LPS22HB_OPEN_DRAIN = 1, } lps22hb_pp_od_t; -int32_t lps22hb_pin_mode_set(stmdev_ctx_t *ctx, lps22hb_pp_od_t val); -int32_t lps22hb_pin_mode_get(stmdev_ctx_t *ctx, lps22hb_pp_od_t *val); +int32_t lps22hb_pin_mode_set(const stmdev_ctx_t *ctx, lps22hb_pp_od_t val); +int32_t lps22hb_pin_mode_get(const stmdev_ctx_t *ctx, lps22hb_pp_od_t *val); typedef enum { LPS22HB_ACTIVE_HIGH = 0, LPS22HB_ACTIVE_LOW = 1, } lps22hb_int_h_l_t; -int32_t lps22hb_int_polarity_set(stmdev_ctx_t *ctx, +int32_t lps22hb_int_polarity_set(const stmdev_ctx_t *ctx, lps22hb_int_h_l_t val); -int32_t lps22hb_int_polarity_get(stmdev_ctx_t *ctx, +int32_t lps22hb_int_polarity_get(const stmdev_ctx_t *ctx, lps22hb_int_h_l_t *val); -int32_t lps22hb_int_source_get(stmdev_ctx_t *ctx, +int32_t lps22hb_int_source_get(const stmdev_ctx_t *ctx, lps22hb_int_source_t *val); -int32_t lps22hb_int_on_press_high_get(stmdev_ctx_t *ctx, +int32_t lps22hb_int_on_press_high_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hb_int_on_press_low_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hb_int_on_press_low_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hb_interrupt_event_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hb_interrupt_event_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hb_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx, +int32_t lps22hb_stop_on_fifo_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hb_stop_on_fifo_threshold_get(stmdev_ctx_t *ctx, +int32_t lps22hb_stop_on_fifo_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hb_fifo_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hb_fifo_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hb_fifo_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22hb_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hb_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hb_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hb_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22hb_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -608,37 +628,37 @@ typedef enum LPS22HB_DYNAMIC_STREAM_MODE = 6, LPS22HB_BYPASS_TO_FIFO_MODE = 7, } lps22hb_f_mode_t; -int32_t lps22hb_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lps22hb_fifo_mode_set(const stmdev_ctx_t *ctx, lps22hb_f_mode_t val); -int32_t lps22hb_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lps22hb_fifo_mode_get(const stmdev_ctx_t *ctx, lps22hb_f_mode_t *val); -int32_t lps22hb_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hb_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hb_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hb_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hb_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hb_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LPS22HB_SPI_4_WIRE = 0, LPS22HB_SPI_3_WIRE = 1, } lps22hb_sim_t; -int32_t lps22hb_spi_mode_set(stmdev_ctx_t *ctx, lps22hb_sim_t val); -int32_t lps22hb_spi_mode_get(stmdev_ctx_t *ctx, lps22hb_sim_t *val); +int32_t lps22hb_spi_mode_set(const stmdev_ctx_t *ctx, lps22hb_sim_t val); +int32_t lps22hb_spi_mode_get(const stmdev_ctx_t *ctx, lps22hb_sim_t *val); typedef enum { LPS22HB_I2C_ENABLE = 0, LPS22HB_I2C_DISABLE = 1, } lps22hb_i2c_dis_t; -int32_t lps22hb_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lps22hb_i2c_interface_set(const stmdev_ctx_t *ctx, lps22hb_i2c_dis_t val); -int32_t lps22hb_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lps22hb_i2c_interface_get(const stmdev_ctx_t *ctx, lps22hb_i2c_dis_t *val); -int32_t lps22hb_auto_add_inc_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hb_auto_add_inc_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hb_auto_add_inc_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22hb_auto_add_inc_get(const stmdev_ctx_t *ctx, uint8_t *val); /** *@} diff --git a/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.c b/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.c index c9cb90d3..2bad0aad 100644 --- a/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.c +++ b/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lps22hh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lps22hh_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lps22hh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lps22hh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lps22hh_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -120,7 +130,7 @@ float_t lps22hh_from_lsb_to_celsius(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22hh_autozero_rst_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hh_interrupt_cfg_t reg; int32_t ret; @@ -144,7 +154,7 @@ int32_t lps22hh_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hh_autozero_rst_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hh_interrupt_cfg_t reg; int32_t ret; @@ -163,7 +173,7 @@ int32_t lps22hh_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_autozero_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22hh_autozero_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hh_interrupt_cfg_t reg; int32_t ret; @@ -187,7 +197,7 @@ int32_t lps22hh_autozero_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_autozero_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hh_autozero_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hh_interrupt_cfg_t reg; int32_t ret; @@ -206,7 +216,7 @@ int32_t lps22hh_autozero_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_pressure_snap_rst_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22hh_pressure_snap_rst_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hh_interrupt_cfg_t reg; int32_t ret; @@ -230,7 +240,7 @@ int32_t lps22hh_pressure_snap_rst_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_pressure_snap_rst_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hh_pressure_snap_rst_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hh_interrupt_cfg_t reg; int32_t ret; @@ -249,7 +259,7 @@ int32_t lps22hh_pressure_snap_rst_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22hh_pressure_snap_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hh_interrupt_cfg_t reg; int32_t ret; @@ -273,7 +283,7 @@ int32_t lps22hh_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hh_pressure_snap_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hh_interrupt_cfg_t reg; int32_t ret; @@ -292,7 +302,7 @@ int32_t lps22hh_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22hh_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hh_ctrl_reg1_t reg; int32_t ret; @@ -316,7 +326,7 @@ int32_t lps22hh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hh_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hh_ctrl_reg1_t reg; int32_t ret; @@ -335,7 +345,7 @@ int32_t lps22hh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_data_rate_set(stmdev_ctx_t *ctx, lps22hh_odr_t val) +int32_t lps22hh_data_rate_set(const stmdev_ctx_t *ctx, lps22hh_odr_t val) { lps22hh_ctrl_reg1_t ctrl_reg1; lps22hh_ctrl_reg2_t ctrl_reg2; @@ -372,7 +382,7 @@ int32_t lps22hh_data_rate_set(stmdev_ctx_t *ctx, lps22hh_odr_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_data_rate_get(stmdev_ctx_t *ctx, lps22hh_odr_t *val) +int32_t lps22hh_data_rate_get(const stmdev_ctx_t *ctx, lps22hh_odr_t *val) { lps22hh_ctrl_reg1_t ctrl_reg1; lps22hh_ctrl_reg2_t ctrl_reg2; @@ -467,7 +477,7 @@ int32_t lps22hh_data_rate_get(stmdev_ctx_t *ctx, lps22hh_odr_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_pressure_ref_set(stmdev_ctx_t *ctx, int16_t val) +int32_t lps22hh_pressure_ref_set(const stmdev_ctx_t *ctx, int16_t val) { uint8_t buff[2]; int32_t ret; @@ -490,7 +500,7 @@ int32_t lps22hh_pressure_ref_set(stmdev_ctx_t *ctx, int16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_pressure_ref_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lps22hh_pressure_ref_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -512,7 +522,7 @@ int32_t lps22hh_pressure_ref_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val) +int32_t lps22hh_pressure_offset_set(const stmdev_ctx_t *ctx, int16_t val) { uint8_t buff[2]; int32_t ret; @@ -535,7 +545,7 @@ int32_t lps22hh_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lps22hh_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -555,7 +565,7 @@ int32_t lps22hh_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_all_sources_get(stmdev_ctx_t *ctx, +int32_t lps22hh_all_sources_get(const stmdev_ctx_t *ctx, lps22hh_all_sources_t *val) { int32_t ret; @@ -586,7 +596,7 @@ int32_t lps22hh_all_sources_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_status_reg_get(stmdev_ctx_t *ctx, +int32_t lps22hh_status_reg_get(const stmdev_ctx_t *ctx, lps22hh_status_t *val) { int32_t ret; @@ -604,7 +614,7 @@ int32_t lps22hh_status_reg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_press_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lps22hh_press_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hh_status_t reg; @@ -624,7 +634,7 @@ int32_t lps22hh_press_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lps22hh_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hh_status_t reg; @@ -656,7 +666,7 @@ int32_t lps22hh_temp_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff) +int32_t lps22hh_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff) { int32_t ret; @@ -678,7 +688,7 @@ int32_t lps22hh_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff) +int32_t lps22hh_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) { int32_t ret; uint8_t reg[2]; @@ -698,7 +708,7 @@ int32_t lps22hh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_fifo_pressure_raw_get(stmdev_ctx_t *ctx, +int32_t lps22hh_fifo_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff) { int32_t ret; @@ -721,7 +731,7 @@ int32_t lps22hh_fifo_pressure_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_fifo_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t lps22hh_fifo_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) { int32_t ret; @@ -754,7 +764,7 @@ int32_t lps22hh_fifo_temperature_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lps22hh_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -772,7 +782,7 @@ int32_t lps22hh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22hh_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hh_ctrl_reg2_t reg; int32_t ret; @@ -797,7 +807,7 @@ int32_t lps22hh_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hh_ctrl_reg2_t reg; int32_t ret; @@ -818,7 +828,7 @@ int32_t lps22hh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22hh_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hh_ctrl_reg2_t reg; int32_t ret; @@ -844,7 +854,7 @@ int32_t lps22hh_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hh_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hh_ctrl_reg2_t reg; int32_t ret; @@ -864,7 +874,7 @@ int32_t lps22hh_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22hh_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hh_ctrl_reg2_t reg; int32_t ret; @@ -889,7 +899,7 @@ int32_t lps22hh_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hh_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hh_ctrl_reg2_t reg; int32_t ret; @@ -921,7 +931,7 @@ int32_t lps22hh_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lps22hh_lp_bandwidth_set(const stmdev_ctx_t *ctx, lps22hh_lpfp_cfg_t val) { lps22hh_ctrl_reg1_t reg; @@ -946,7 +956,7 @@ int32_t lps22hh_lp_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lps22hh_lp_bandwidth_get(const stmdev_ctx_t *ctx, lps22hh_lpfp_cfg_t *val) { lps22hh_ctrl_reg1_t reg; @@ -997,7 +1007,7 @@ int32_t lps22hh_lp_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lps22hh_i2c_interface_set(const stmdev_ctx_t *ctx, lps22hh_i2c_disable_t val) { lps22hh_if_ctrl_t reg; @@ -1022,7 +1032,7 @@ int32_t lps22hh_i2c_interface_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lps22hh_i2c_interface_get(const stmdev_ctx_t *ctx, lps22hh_i2c_disable_t *val) { lps22hh_if_ctrl_t reg; @@ -1056,7 +1066,7 @@ int32_t lps22hh_i2c_interface_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_i3c_interface_set(stmdev_ctx_t *ctx, +int32_t lps22hh_i3c_interface_set(const stmdev_ctx_t *ctx, lps22hh_i3c_disable_t val) { lps22hh_if_ctrl_t reg; @@ -1082,7 +1092,7 @@ int32_t lps22hh_i3c_interface_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_i3c_interface_get(stmdev_ctx_t *ctx, +int32_t lps22hh_i3c_interface_get(const stmdev_ctx_t *ctx, lps22hh_i3c_disable_t *val) { lps22hh_if_ctrl_t reg; @@ -1120,7 +1130,7 @@ int32_t lps22hh_i3c_interface_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t lps22hh_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, lps22hh_pu_en_t val) { lps22hh_if_ctrl_t reg; @@ -1145,7 +1155,7 @@ int32_t lps22hh_sdo_sa0_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t lps22hh_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, lps22hh_pu_en_t *val) { lps22hh_if_ctrl_t reg; @@ -1179,7 +1189,7 @@ int32_t lps22hh_sdo_sa0_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_sda_mode_set(stmdev_ctx_t *ctx, lps22hh_pu_en_t val) +int32_t lps22hh_sda_mode_set(const stmdev_ctx_t *ctx, lps22hh_pu_en_t val) { lps22hh_if_ctrl_t reg; int32_t ret; @@ -1203,7 +1213,7 @@ int32_t lps22hh_sda_mode_set(stmdev_ctx_t *ctx, lps22hh_pu_en_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_sda_mode_get(stmdev_ctx_t *ctx, lps22hh_pu_en_t *val) +int32_t lps22hh_sda_mode_get(const stmdev_ctx_t *ctx, lps22hh_pu_en_t *val) { lps22hh_if_ctrl_t reg; int32_t ret; @@ -1236,7 +1246,7 @@ int32_t lps22hh_sda_mode_get(stmdev_ctx_t *ctx, lps22hh_pu_en_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_spi_mode_set(stmdev_ctx_t *ctx, lps22hh_sim_t val) +int32_t lps22hh_spi_mode_set(const stmdev_ctx_t *ctx, lps22hh_sim_t val) { lps22hh_ctrl_reg1_t reg; int32_t ret; @@ -1260,7 +1270,7 @@ int32_t lps22hh_spi_mode_set(stmdev_ctx_t *ctx, lps22hh_sim_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_spi_mode_get(stmdev_ctx_t *ctx, lps22hh_sim_t *val) +int32_t lps22hh_spi_mode_get(const stmdev_ctx_t *ctx, lps22hh_sim_t *val) { lps22hh_ctrl_reg1_t reg; int32_t ret; @@ -1306,7 +1316,7 @@ int32_t lps22hh_spi_mode_get(stmdev_ctx_t *ctx, lps22hh_sim_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_int_notification_set(stmdev_ctx_t *ctx, +int32_t lps22hh_int_notification_set(const stmdev_ctx_t *ctx, lps22hh_lir_t val) { lps22hh_interrupt_cfg_t reg; @@ -1331,7 +1341,7 @@ int32_t lps22hh_int_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_int_notification_get(stmdev_ctx_t *ctx, +int32_t lps22hh_int_notification_get(const stmdev_ctx_t *ctx, lps22hh_lir_t *val) { lps22hh_interrupt_cfg_t reg; @@ -1365,7 +1375,7 @@ int32_t lps22hh_int_notification_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_pin_mode_set(stmdev_ctx_t *ctx, lps22hh_pp_od_t val) +int32_t lps22hh_pin_mode_set(const stmdev_ctx_t *ctx, lps22hh_pp_od_t val) { lps22hh_ctrl_reg2_t reg; int32_t ret; @@ -1389,7 +1399,7 @@ int32_t lps22hh_pin_mode_set(stmdev_ctx_t *ctx, lps22hh_pp_od_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_pin_mode_get(stmdev_ctx_t *ctx, lps22hh_pp_od_t *val) +int32_t lps22hh_pin_mode_get(const stmdev_ctx_t *ctx, lps22hh_pp_od_t *val) { lps22hh_ctrl_reg2_t reg; int32_t ret; @@ -1422,7 +1432,7 @@ int32_t lps22hh_pin_mode_get(stmdev_ctx_t *ctx, lps22hh_pp_od_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lps22hh_pin_polarity_set(const stmdev_ctx_t *ctx, lps22hh_int_h_l_t val) { lps22hh_ctrl_reg2_t reg; @@ -1447,7 +1457,7 @@ int32_t lps22hh_pin_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lps22hh_pin_polarity_get(const stmdev_ctx_t *ctx, lps22hh_int_h_l_t *val) { lps22hh_ctrl_reg2_t reg; @@ -1481,7 +1491,7 @@ int32_t lps22hh_pin_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_pin_int_route_set(stmdev_ctx_t *ctx, +int32_t lps22hh_pin_int_route_set(const stmdev_ctx_t *ctx, lps22hh_pin_int_route_t *val) { lps22hh_ctrl_reg3_t ctrl_reg3; @@ -1508,7 +1518,7 @@ int32_t lps22hh_pin_int_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_pin_int_route_get(stmdev_ctx_t *ctx, +int32_t lps22hh_pin_int_route_get(const stmdev_ctx_t *ctx, lps22hh_pin_int_route_t *val) { lps22hh_ctrl_reg3_t ctrl_reg3; @@ -1545,7 +1555,7 @@ int32_t lps22hh_pin_int_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_int_on_threshold_set(stmdev_ctx_t *ctx, +int32_t lps22hh_int_on_threshold_set(const stmdev_ctx_t *ctx, lps22hh_pe_t val) { lps22hh_interrupt_cfg_t reg; @@ -1581,7 +1591,7 @@ int32_t lps22hh_int_on_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_int_on_threshold_get(stmdev_ctx_t *ctx, +int32_t lps22hh_int_on_threshold_get(const stmdev_ctx_t *ctx, lps22hh_pe_t *val) { lps22hh_interrupt_cfg_t reg; @@ -1623,7 +1633,7 @@ int32_t lps22hh_int_on_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_int_treshold_set(stmdev_ctx_t *ctx, uint16_t buff) +int32_t lps22hh_int_threshold_set(const stmdev_ctx_t *ctx, uint16_t buff) { int32_t ret; @@ -1651,7 +1661,7 @@ int32_t lps22hh_int_treshold_set(stmdev_ctx_t *ctx, uint16_t buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_int_treshold_get(stmdev_ctx_t *ctx, uint16_t *buff) +int32_t lps22hh_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *buff) { int32_t ret; @@ -1691,7 +1701,7 @@ int32_t lps22hh_int_treshold_get(stmdev_ctx_t *ctx, uint16_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_fifo_mode_set(stmdev_ctx_t *ctx, lps22hh_f_mode_t val) +int32_t lps22hh_fifo_mode_set(const stmdev_ctx_t *ctx, lps22hh_f_mode_t val) { lps22hh_fifo_ctrl_t reg; int32_t ret; @@ -1715,7 +1725,7 @@ int32_t lps22hh_fifo_mode_set(stmdev_ctx_t *ctx, lps22hh_f_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lps22hh_fifo_mode_get(const stmdev_ctx_t *ctx, lps22hh_f_mode_t *val) { lps22hh_fifo_ctrl_t reg; @@ -1770,7 +1780,7 @@ int32_t lps22hh_fifo_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22hh_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hh_fifo_ctrl_t reg; int32_t ret; @@ -1795,7 +1805,7 @@ int32_t lps22hh_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hh_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hh_fifo_ctrl_t reg; int32_t ret; @@ -1814,7 +1824,7 @@ int32_t lps22hh_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps22hh_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { lps22hh_fifo_wtm_t reg; int32_t ret; @@ -1838,7 +1848,7 @@ int32_t lps22hh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hh_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hh_fifo_wtm_t reg; int32_t ret; @@ -1857,7 +1867,7 @@ int32_t lps22hh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *num) +int32_t lps22hh_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *num) { int32_t ret; @@ -1874,7 +1884,7 @@ int32_t lps22hh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *num) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_fifo_src_get(stmdev_ctx_t *ctx, +int32_t lps22hh_fifo_src_get(const stmdev_ctx_t *ctx, lps22hh_fifo_status2_t *val) { int32_t ret; @@ -1892,7 +1902,7 @@ int32_t lps22hh_fifo_src_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hh_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hh_fifo_status2_t reg; int32_t ret; @@ -1911,7 +1921,7 @@ int32_t lps22hh_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hh_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hh_fifo_status2_t reg; int32_t ret; @@ -1930,7 +1940,7 @@ int32_t lps22hh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps22hh_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps22hh_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps22hh_fifo_status2_t reg; int32_t ret; diff --git a/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.h b/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.h index 7cf08468..ddcb4d10 100644 --- a/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.h +++ b/sensor/stmemsc/lps22hh_STdC/driver/lps22hh_reg.h @@ -309,15 +309,13 @@ typedef struct typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN -uint8_t f_mode : - 3; /* f_mode + trig_modes */ + uint8_t f_mode : 3; /* f_mode + trig_modes */ uint8_t stop_on_wtm : 1; uint8_t not_used_01 : 4; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN uint8_t not_used_01 : 4; uint8_t stop_on_wtm : 1; -uint8_t f_mode : - 3; /* f_mode + trig_modes */ + uint8_t f_mode : 3; /* f_mode + trig_modes */ #endif /* DRV_BYTE_ORDER */ } lps22hh_fifo_ctrl_t; @@ -448,32 +446,32 @@ typedef union * The __weak directive allows the final application to overwrite * them with a custom implementation. */ -int32_t lps22hh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len); -int32_t lps22hh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len); +int32_t lps22hh_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); +int32_t lps22hh_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); float_t lps22hh_from_lsb_to_hpa(uint32_t lsb); float_t lps22hh_from_lsb_to_celsius(int16_t lsb); -int32_t lps22hh_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hh_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hh_autozero_rst_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22hh_autozero_rst_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hh_autozero_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hh_autozero_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hh_autozero_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22hh_autozero_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hh_pressure_snap_rst_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hh_pressure_snap_rst_get(stmdev_ctx_t *ctx, +int32_t lps22hh_pressure_snap_rst_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22hh_pressure_snap_rst_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hh_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hh_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hh_pressure_snap_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22hh_pressure_snap_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hh_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lps22hh_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22hh_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -493,14 +491,14 @@ typedef enum LPS22HH_100_Hz = 0x06, LPS22HH_200_Hz = 0x07, } lps22hh_odr_t; -int32_t lps22hh_data_rate_set(stmdev_ctx_t *ctx, lps22hh_odr_t val); -int32_t lps22hh_data_rate_get(stmdev_ctx_t *ctx, lps22hh_odr_t *val); +int32_t lps22hh_data_rate_set(const stmdev_ctx_t *ctx, lps22hh_odr_t val); +int32_t lps22hh_data_rate_get(const stmdev_ctx_t *ctx, lps22hh_odr_t *val); -int32_t lps22hh_pressure_ref_set(stmdev_ctx_t *ctx, int16_t val); -int32_t lps22hh_pressure_ref_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lps22hh_pressure_ref_set(const stmdev_ctx_t *ctx, int16_t val); +int32_t lps22hh_pressure_ref_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lps22hh_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val); -int32_t lps22hh_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lps22hh_pressure_offset_set(const stmdev_ctx_t *ctx, int16_t val); +int32_t lps22hh_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val); typedef struct { @@ -508,38 +506,38 @@ typedef struct lps22hh_fifo_status2_t fifo_status2; lps22hh_status_t status; } lps22hh_all_sources_t; -int32_t lps22hh_all_sources_get(stmdev_ctx_t *ctx, +int32_t lps22hh_all_sources_get(const stmdev_ctx_t *ctx, lps22hh_all_sources_t *val); -int32_t lps22hh_status_reg_get(stmdev_ctx_t *ctx, +int32_t lps22hh_status_reg_get(const stmdev_ctx_t *ctx, lps22hh_status_t *val); -int32_t lps22hh_press_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lps22hh_press_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hh_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lps22hh_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hh_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff); +int32_t lps22hh_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff); -int32_t lps22hh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff); +int32_t lps22hh_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff); -int32_t lps22hh_fifo_pressure_raw_get(stmdev_ctx_t *ctx, +int32_t lps22hh_fifo_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff); -int32_t lps22hh_fifo_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t lps22hh_fifo_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff); -int32_t lps22hh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lps22hh_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lps22hh_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hh_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22hh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hh_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hh_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hh_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22hh_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hh_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hh_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hh_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22hh_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -547,9 +545,9 @@ typedef enum LPS22HH_LPF_ODR_DIV_9 = 2, LPS22HH_LPF_ODR_DIV_20 = 3, } lps22hh_lpfp_cfg_t; -int32_t lps22hh_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lps22hh_lp_bandwidth_set(const stmdev_ctx_t *ctx, lps22hh_lpfp_cfg_t val); -int32_t lps22hh_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lps22hh_lp_bandwidth_get(const stmdev_ctx_t *ctx, lps22hh_lpfp_cfg_t *val); typedef enum @@ -557,9 +555,9 @@ typedef enum LPS22HH_I2C_ENABLE = 0, LPS22HH_I2C_DISABLE = 1, } lps22hh_i2c_disable_t; -int32_t lps22hh_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lps22hh_i2c_interface_set(const stmdev_ctx_t *ctx, lps22hh_i2c_disable_t val); -int32_t lps22hh_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lps22hh_i2c_interface_get(const stmdev_ctx_t *ctx, lps22hh_i2c_disable_t *val); typedef enum @@ -568,9 +566,9 @@ typedef enum LPS22HH_I3C_ENABLE_INT_PIN_ENABLE = 0x10, LPS22HH_I3C_DISABLE = 0x11, } lps22hh_i3c_disable_t; -int32_t lps22hh_i3c_interface_set(stmdev_ctx_t *ctx, +int32_t lps22hh_i3c_interface_set(const stmdev_ctx_t *ctx, lps22hh_i3c_disable_t val); -int32_t lps22hh_i3c_interface_get(stmdev_ctx_t *ctx, +int32_t lps22hh_i3c_interface_get(const stmdev_ctx_t *ctx, lps22hh_i3c_disable_t *val); typedef enum @@ -578,29 +576,29 @@ typedef enum LPS22HH_PULL_UP_DISCONNECT = 0, LPS22HH_PULL_UP_CONNECT = 1, } lps22hh_pu_en_t; -int32_t lps22hh_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t lps22hh_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, lps22hh_pu_en_t val); -int32_t lps22hh_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t lps22hh_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, lps22hh_pu_en_t *val); -int32_t lps22hh_sda_mode_set(stmdev_ctx_t *ctx, lps22hh_pu_en_t val); -int32_t lps22hh_sda_mode_get(stmdev_ctx_t *ctx, lps22hh_pu_en_t *val); +int32_t lps22hh_sda_mode_set(const stmdev_ctx_t *ctx, lps22hh_pu_en_t val); +int32_t lps22hh_sda_mode_get(const stmdev_ctx_t *ctx, lps22hh_pu_en_t *val); typedef enum { LPS22HH_SPI_4_WIRE = 0, LPS22HH_SPI_3_WIRE = 1, } lps22hh_sim_t; -int32_t lps22hh_spi_mode_set(stmdev_ctx_t *ctx, lps22hh_sim_t val); -int32_t lps22hh_spi_mode_get(stmdev_ctx_t *ctx, lps22hh_sim_t *val); +int32_t lps22hh_spi_mode_set(const stmdev_ctx_t *ctx, lps22hh_sim_t val); +int32_t lps22hh_spi_mode_get(const stmdev_ctx_t *ctx, lps22hh_sim_t *val); typedef enum { LPS22HH_INT_PULSED = 0, LPS22HH_INT_LATCHED = 1, } lps22hh_lir_t; -int32_t lps22hh_int_notification_set(stmdev_ctx_t *ctx, +int32_t lps22hh_int_notification_set(const stmdev_ctx_t *ctx, lps22hh_lir_t val); -int32_t lps22hh_int_notification_get(stmdev_ctx_t *ctx, +int32_t lps22hh_int_notification_get(const stmdev_ctx_t *ctx, lps22hh_lir_t *val); typedef enum @@ -608,17 +606,17 @@ typedef enum LPS22HH_PUSH_PULL = 0, LPS22HH_OPEN_DRAIN = 1, } lps22hh_pp_od_t; -int32_t lps22hh_pin_mode_set(stmdev_ctx_t *ctx, lps22hh_pp_od_t val); -int32_t lps22hh_pin_mode_get(stmdev_ctx_t *ctx, lps22hh_pp_od_t *val); +int32_t lps22hh_pin_mode_set(const stmdev_ctx_t *ctx, lps22hh_pp_od_t val); +int32_t lps22hh_pin_mode_get(const stmdev_ctx_t *ctx, lps22hh_pp_od_t *val); typedef enum { LPS22HH_ACTIVE_HIGH = 0, LPS22HH_ACTIVE_LOW = 1, } lps22hh_int_h_l_t; -int32_t lps22hh_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lps22hh_pin_polarity_set(const stmdev_ctx_t *ctx, lps22hh_int_h_l_t val); -int32_t lps22hh_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lps22hh_pin_polarity_get(const stmdev_ctx_t *ctx, lps22hh_int_h_l_t *val); typedef struct @@ -628,9 +626,9 @@ typedef struct uint8_t fifo_ovr : 1; /* FIFO overrun */ uint8_t fifo_full : 1; /* FIFO full */ } lps22hh_pin_int_route_t; -int32_t lps22hh_pin_int_route_set(stmdev_ctx_t *ctx, +int32_t lps22hh_pin_int_route_set(const stmdev_ctx_t *ctx, lps22hh_pin_int_route_t *val); -int32_t lps22hh_pin_int_route_get(stmdev_ctx_t *ctx, +int32_t lps22hh_pin_int_route_get(const stmdev_ctx_t *ctx, lps22hh_pin_int_route_t *val); typedef enum @@ -640,13 +638,13 @@ typedef enum LPS22HH_NEGATIVE = 2, LPS22HH_BOTH = 3, } lps22hh_pe_t; -int32_t lps22hh_int_on_threshold_set(stmdev_ctx_t *ctx, +int32_t lps22hh_int_on_threshold_set(const stmdev_ctx_t *ctx, lps22hh_pe_t val); -int32_t lps22hh_int_on_threshold_get(stmdev_ctx_t *ctx, +int32_t lps22hh_int_on_threshold_get(const stmdev_ctx_t *ctx, lps22hh_pe_t *val); -int32_t lps22hh_int_treshold_set(stmdev_ctx_t *ctx, uint16_t buff); -int32_t lps22hh_int_treshold_get(stmdev_ctx_t *ctx, uint16_t *buff); +int32_t lps22hh_int_threshold_set(const stmdev_ctx_t *ctx, uint16_t buff); +int32_t lps22hh_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *buff); typedef enum { @@ -658,27 +656,27 @@ typedef enum LPS22HH_BYPASS_TO_STREAM_MODE = 6, LPS22HH_STREAM_TO_FIFO_MODE = 7, } lps22hh_f_mode_t; -int32_t lps22hh_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lps22hh_fifo_mode_set(const stmdev_ctx_t *ctx, lps22hh_f_mode_t val); -int32_t lps22hh_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lps22hh_fifo_mode_get(const stmdev_ctx_t *ctx, lps22hh_f_mode_t *val); -int32_t lps22hh_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hh_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hh_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22hh_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps22hh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hh_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps22hh_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *num); +int32_t lps22hh_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *num); -int32_t lps22hh_fifo_src_get(stmdev_ctx_t *ctx, +int32_t lps22hh_fifo_src_get(const stmdev_ctx_t *ctx, lps22hh_fifo_status2_t *val); -int32_t lps22hh_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hh_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hh_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps22hh_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps22hh_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); /** * @} diff --git a/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.c b/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.c index fbe6925f..1f8b0410 100644 --- a/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.c +++ b/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.c @@ -45,12 +45,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lps25hb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lps25hb_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -66,12 +71,17 @@ int32_t __weak lps25hb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lps25hb_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lps25hb_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -121,7 +131,7 @@ float_t lps25hb_from_lsb_to_degc(int16_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_pressure_ref_set(stmdev_ctx_t *ctx, int32_t val) +int32_t lps25hb_pressure_ref_set(const stmdev_ctx_t *ctx, int32_t val) { uint8_t buff[3]; int32_t ret; @@ -145,7 +155,7 @@ int32_t lps25hb_pressure_ref_set(stmdev_ctx_t *ctx, int32_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_pressure_ref_get(stmdev_ctx_t *ctx, int32_t *val) +int32_t lps25hb_pressure_ref_get(const stmdev_ctx_t *ctx, int32_t *val) { uint8_t buff[3]; int32_t ret; @@ -166,7 +176,7 @@ int32_t lps25hb_pressure_ref_get(stmdev_ctx_t *ctx, int32_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_pressure_avg_set(stmdev_ctx_t *ctx, +int32_t lps25hb_pressure_avg_set(const stmdev_ctx_t *ctx, lps25hb_avgp_t val) { lps25hb_res_conf_t reg; @@ -191,7 +201,7 @@ int32_t lps25hb_pressure_avg_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_pressure_avg_get(stmdev_ctx_t *ctx, +int32_t lps25hb_pressure_avg_get(const stmdev_ctx_t *ctx, lps25hb_avgp_t *val) { lps25hb_res_conf_t reg; @@ -233,7 +243,7 @@ int32_t lps25hb_pressure_avg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_temperature_avg_set(stmdev_ctx_t *ctx, +int32_t lps25hb_temperature_avg_set(const stmdev_ctx_t *ctx, lps25hb_avgt_t val) { lps25hb_res_conf_t reg; @@ -258,7 +268,7 @@ int32_t lps25hb_temperature_avg_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_temperature_avg_get(stmdev_ctx_t *ctx, +int32_t lps25hb_temperature_avg_get(const stmdev_ctx_t *ctx, lps25hb_avgt_t *val) { lps25hb_res_conf_t reg; @@ -300,7 +310,7 @@ int32_t lps25hb_temperature_avg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps25hb_autozero_rst_set(const stmdev_ctx_t *ctx, uint8_t val) { lps25hb_ctrl_reg1_t reg; int32_t ret; @@ -324,7 +334,7 @@ int32_t lps25hb_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps25hb_autozero_rst_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps25hb_ctrl_reg1_t reg; int32_t ret; @@ -343,7 +353,7 @@ int32_t lps25hb_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps25hb_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lps25hb_ctrl_reg1_t reg; int32_t ret; @@ -367,7 +377,7 @@ int32_t lps25hb_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps25hb_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps25hb_ctrl_reg1_t reg; int32_t ret; @@ -386,7 +396,7 @@ int32_t lps25hb_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_data_rate_set(stmdev_ctx_t *ctx, lps25hb_odr_t val) +int32_t lps25hb_data_rate_set(const stmdev_ctx_t *ctx, lps25hb_odr_t val) { lps25hb_ctrl_reg1_t reg; int32_t ret; @@ -410,7 +420,7 @@ int32_t lps25hb_data_rate_set(stmdev_ctx_t *ctx, lps25hb_odr_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_data_rate_get(stmdev_ctx_t *ctx, lps25hb_odr_t *val) +int32_t lps25hb_data_rate_get(const stmdev_ctx_t *ctx, lps25hb_odr_t *val) { lps25hb_ctrl_reg1_t reg; int32_t ret; @@ -459,7 +469,7 @@ int32_t lps25hb_data_rate_get(stmdev_ctx_t *ctx, lps25hb_odr_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps25hb_one_shoot_trigger_set(const stmdev_ctx_t *ctx, uint8_t val) { lps25hb_ctrl_reg2_t reg; int32_t ret; @@ -483,7 +493,7 @@ int32_t lps25hb_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps25hb_one_shoot_trigger_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps25hb_ctrl_reg2_t reg; int32_t ret; @@ -502,7 +512,7 @@ int32_t lps25hb_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_autozero_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps25hb_autozero_set(const stmdev_ctx_t *ctx, uint8_t val) { lps25hb_ctrl_reg2_t reg; int32_t ret; @@ -526,7 +536,7 @@ int32_t lps25hb_autozero_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_autozero_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps25hb_autozero_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps25hb_ctrl_reg2_t reg; int32_t ret; @@ -546,7 +556,7 @@ int32_t lps25hb_autozero_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_fifo_mean_decimator_set(stmdev_ctx_t *ctx, +int32_t lps25hb_fifo_mean_decimator_set(const stmdev_ctx_t *ctx, uint8_t val) { lps25hb_ctrl_reg2_t reg; @@ -572,7 +582,7 @@ int32_t lps25hb_fifo_mean_decimator_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_fifo_mean_decimator_get(stmdev_ctx_t *ctx, +int32_t lps25hb_fifo_mean_decimator_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps25hb_ctrl_reg2_t reg; @@ -592,7 +602,7 @@ int32_t lps25hb_fifo_mean_decimator_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_press_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps25hb_press_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps25hb_status_reg_t reg; int32_t ret; @@ -611,7 +621,7 @@ int32_t lps25hb_press_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps25hb_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps25hb_status_reg_t reg; int32_t ret; @@ -630,7 +640,7 @@ int32_t lps25hb_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps25hb_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps25hb_status_reg_t reg; int32_t ret; @@ -649,7 +659,7 @@ int32_t lps25hb_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_press_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps25hb_press_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps25hb_status_reg_t reg; int32_t ret; @@ -668,7 +678,7 @@ int32_t lps25hb_press_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff) +int32_t lps25hb_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff) { uint8_t reg[3]; int32_t ret; @@ -690,7 +700,7 @@ int32_t lps25hb_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff) +int32_t lps25hb_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) { uint8_t reg[2]; int32_t ret; @@ -711,7 +721,7 @@ int32_t lps25hb_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val) +int32_t lps25hb_pressure_offset_set(const stmdev_ctx_t *ctx, int16_t val) { uint8_t buff[2]; int32_t ret; @@ -732,7 +742,7 @@ int32_t lps25hb_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lps25hb_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -764,7 +774,7 @@ int32_t lps25hb_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lps25hb_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -781,7 +791,7 @@ int32_t lps25hb_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps25hb_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lps25hb_ctrl_reg2_t reg; int32_t ret; @@ -805,7 +815,7 @@ int32_t lps25hb_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps25hb_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps25hb_ctrl_reg2_t reg; int32_t ret; @@ -824,7 +834,7 @@ int32_t lps25hb_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps25hb_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lps25hb_ctrl_reg2_t reg; int32_t ret; @@ -848,7 +858,7 @@ int32_t lps25hb_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps25hb_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps25hb_ctrl_reg2_t reg; int32_t ret; @@ -867,7 +877,7 @@ int32_t lps25hb_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_status_get(stmdev_ctx_t *ctx, +int32_t lps25hb_status_get(const stmdev_ctx_t *ctx, lps25hb_status_reg_t *val) { int32_t ret; @@ -897,7 +907,7 @@ int32_t lps25hb_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_int_generation_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps25hb_int_generation_set(const stmdev_ctx_t *ctx, uint8_t val) { lps25hb_ctrl_reg1_t reg; int32_t ret; @@ -921,7 +931,7 @@ int32_t lps25hb_int_generation_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps25hb_int_generation_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps25hb_ctrl_reg1_t reg; int32_t ret; @@ -940,7 +950,7 @@ int32_t lps25hb_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_int_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lps25hb_int_pin_mode_set(const stmdev_ctx_t *ctx, lps25hb_int_s_t val) { lps25hb_ctrl_reg3_t reg; @@ -965,7 +975,7 @@ int32_t lps25hb_int_pin_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_int_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lps25hb_int_pin_mode_get(const stmdev_ctx_t *ctx, lps25hb_int_s_t *val) { lps25hb_ctrl_reg3_t reg; @@ -1007,7 +1017,7 @@ int32_t lps25hb_int_pin_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_pin_mode_set(stmdev_ctx_t *ctx, lps25hb_pp_od_t val) +int32_t lps25hb_pin_mode_set(const stmdev_ctx_t *ctx, lps25hb_pp_od_t val) { lps25hb_ctrl_reg3_t reg; int32_t ret; @@ -1031,7 +1041,7 @@ int32_t lps25hb_pin_mode_set(stmdev_ctx_t *ctx, lps25hb_pp_od_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_pin_mode_get(stmdev_ctx_t *ctx, lps25hb_pp_od_t *val) +int32_t lps25hb_pin_mode_get(const stmdev_ctx_t *ctx, lps25hb_pp_od_t *val) { lps25hb_ctrl_reg3_t reg; int32_t ret; @@ -1064,7 +1074,7 @@ int32_t lps25hb_pin_mode_get(stmdev_ctx_t *ctx, lps25hb_pp_od_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_int_polarity_set(stmdev_ctx_t *ctx, +int32_t lps25hb_int_polarity_set(const stmdev_ctx_t *ctx, lps25hb_int_h_l_t val) { lps25hb_ctrl_reg3_t reg; @@ -1089,7 +1099,7 @@ int32_t lps25hb_int_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_int_polarity_get(stmdev_ctx_t *ctx, +int32_t lps25hb_int_polarity_get(const stmdev_ctx_t *ctx, lps25hb_int_h_l_t *val) { lps25hb_ctrl_reg3_t reg; @@ -1123,7 +1133,7 @@ int32_t lps25hb_int_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_drdy_on_int_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps25hb_drdy_on_int_set(const stmdev_ctx_t *ctx, uint8_t val) { lps25hb_ctrl_reg4_t reg; int32_t ret; @@ -1147,7 +1157,7 @@ int32_t lps25hb_drdy_on_int_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps25hb_drdy_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps25hb_ctrl_reg4_t reg; int32_t ret; @@ -1166,7 +1176,7 @@ int32_t lps25hb_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps25hb_fifo_ovr_on_int_set(const stmdev_ctx_t *ctx, uint8_t val) { lps25hb_ctrl_reg4_t reg; int32_t ret; @@ -1190,7 +1200,7 @@ int32_t lps25hb_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps25hb_fifo_ovr_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps25hb_ctrl_reg4_t reg; int32_t ret; @@ -1209,7 +1219,7 @@ int32_t lps25hb_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, +int32_t lps25hb_fifo_threshold_on_int_set(const stmdev_ctx_t *ctx, uint8_t val) { lps25hb_ctrl_reg4_t reg; @@ -1234,7 +1244,7 @@ int32_t lps25hb_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, +int32_t lps25hb_fifo_threshold_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps25hb_ctrl_reg4_t reg; @@ -1254,7 +1264,7 @@ int32_t lps25hb_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_fifo_empty_on_int_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps25hb_fifo_empty_on_int_set(const stmdev_ctx_t *ctx, uint8_t val) { lps25hb_ctrl_reg4_t reg; int32_t ret; @@ -1278,7 +1288,7 @@ int32_t lps25hb_fifo_empty_on_int_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_fifo_empty_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps25hb_fifo_empty_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps25hb_ctrl_reg4_t reg; int32_t ret; @@ -1297,7 +1307,7 @@ int32_t lps25hb_fifo_empty_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_sign_of_int_threshold_set(stmdev_ctx_t *ctx, +int32_t lps25hb_sign_of_int_threshold_set(const stmdev_ctx_t *ctx, lps25hb_pe_t val) { lps25hb_interrupt_cfg_t reg; @@ -1322,7 +1332,7 @@ int32_t lps25hb_sign_of_int_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_sign_of_int_threshold_get(stmdev_ctx_t *ctx, +int32_t lps25hb_sign_of_int_threshold_get(const stmdev_ctx_t *ctx, lps25hb_pe_t *val) { lps25hb_interrupt_cfg_t reg; @@ -1364,7 +1374,7 @@ int32_t lps25hb_sign_of_int_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_int_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lps25hb_int_notification_mode_set(const stmdev_ctx_t *ctx, lps25hb_lir_t val) { lps25hb_interrupt_cfg_t reg; @@ -1389,7 +1399,7 @@ int32_t lps25hb_int_notification_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_int_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lps25hb_int_notification_mode_get(const stmdev_ctx_t *ctx, lps25hb_lir_t *val) { lps25hb_interrupt_cfg_t reg; @@ -1423,7 +1433,7 @@ int32_t lps25hb_int_notification_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_int_source_get(stmdev_ctx_t *ctx, +int32_t lps25hb_int_source_get(const stmdev_ctx_t *ctx, lps25hb_int_source_t *val) { int32_t ret; @@ -1441,7 +1451,7 @@ int32_t lps25hb_int_source_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_int_on_press_high_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps25hb_int_on_press_high_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps25hb_int_source_t reg; int32_t ret; @@ -1460,7 +1470,7 @@ int32_t lps25hb_int_on_press_high_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_int_on_press_low_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps25hb_int_on_press_low_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps25hb_int_source_t reg; int32_t ret; @@ -1479,7 +1489,7 @@ int32_t lps25hb_int_on_press_low_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_interrupt_event_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps25hb_interrupt_event_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps25hb_int_source_t reg; int32_t ret; @@ -1498,7 +1508,7 @@ int32_t lps25hb_interrupt_event_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_int_threshold_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lps25hb_int_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -1518,7 +1528,7 @@ int32_t lps25hb_int_threshold_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_int_threshold_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lps25hb_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1550,7 +1560,7 @@ int32_t lps25hb_int_threshold_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx, +int32_t lps25hb_stop_on_fifo_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lps25hb_ctrl_reg2_t reg; @@ -1575,7 +1585,7 @@ int32_t lps25hb_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_stop_on_fifo_threshold_get(stmdev_ctx_t *ctx, +int32_t lps25hb_stop_on_fifo_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps25hb_ctrl_reg2_t reg; @@ -1595,7 +1605,7 @@ int32_t lps25hb_stop_on_fifo_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_fifo_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps25hb_fifo_set(const stmdev_ctx_t *ctx, uint8_t val) { lps25hb_ctrl_reg2_t reg; int32_t ret; @@ -1619,7 +1629,7 @@ int32_t lps25hb_fifo_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_fifo_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps25hb_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps25hb_ctrl_reg2_t reg; int32_t ret; @@ -1638,7 +1648,7 @@ int32_t lps25hb_fifo_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps25hb_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { lps25hb_fifo_ctrl_t reg; int32_t ret; @@ -1662,7 +1672,7 @@ int32_t lps25hb_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps25hb_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps25hb_fifo_ctrl_t reg; int32_t ret; @@ -1681,7 +1691,7 @@ int32_t lps25hb_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_fifo_mode_set(stmdev_ctx_t *ctx, lps25hb_f_mode_t val) +int32_t lps25hb_fifo_mode_set(const stmdev_ctx_t *ctx, lps25hb_f_mode_t val) { lps25hb_fifo_ctrl_t reg; int32_t ret; @@ -1705,7 +1715,7 @@ int32_t lps25hb_fifo_mode_set(stmdev_ctx_t *ctx, lps25hb_f_mode_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lps25hb_fifo_mode_get(const stmdev_ctx_t *ctx, lps25hb_f_mode_t *val) { lps25hb_fifo_ctrl_t reg; @@ -1759,7 +1769,7 @@ int32_t lps25hb_fifo_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lps25hb_fifo_status_get(const stmdev_ctx_t *ctx, lps25hb_fifo_status_t *val) { int32_t ret; @@ -1777,7 +1787,7 @@ int32_t lps25hb_fifo_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps25hb_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps25hb_fifo_status_t reg; int32_t ret; @@ -1796,7 +1806,7 @@ int32_t lps25hb_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps25hb_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps25hb_fifo_status_t reg; int32_t ret; @@ -1815,7 +1825,7 @@ int32_t lps25hb_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps25hb_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps25hb_fifo_status_t reg; int32_t ret; @@ -1834,7 +1844,7 @@ int32_t lps25hb_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps25hb_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps25hb_fifo_status_t reg; int32_t ret; @@ -1866,7 +1876,7 @@ int32_t lps25hb_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_spi_mode_set(stmdev_ctx_t *ctx, lps25hb_sim_t val) +int32_t lps25hb_spi_mode_set(const stmdev_ctx_t *ctx, lps25hb_sim_t val) { lps25hb_ctrl_reg1_t reg; int32_t ret; @@ -1890,7 +1900,7 @@ int32_t lps25hb_spi_mode_set(stmdev_ctx_t *ctx, lps25hb_sim_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_spi_mode_get(stmdev_ctx_t *ctx, lps25hb_sim_t *val) +int32_t lps25hb_spi_mode_get(const stmdev_ctx_t *ctx, lps25hb_sim_t *val) { lps25hb_ctrl_reg1_t reg; int32_t ret; @@ -1923,7 +1933,7 @@ int32_t lps25hb_spi_mode_get(stmdev_ctx_t *ctx, lps25hb_sim_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lps25hb_i2c_interface_set(const stmdev_ctx_t *ctx, lps25hb_i2c_dis_t val) { lps25hb_ctrl_reg2_t reg; @@ -1948,7 +1958,7 @@ int32_t lps25hb_i2c_interface_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps25hb_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lps25hb_i2c_interface_get(const stmdev_ctx_t *ctx, lps25hb_i2c_dis_t *val) { lps25hb_ctrl_reg2_t reg; diff --git a/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.h b/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.h index d21bcdd7..8b78f803 100644 --- a/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.h +++ b/sensor/stmemsc/lps25hb_STdC/driver/lps25hb_reg.h @@ -409,10 +409,10 @@ typedef union * them with a custom implementation. */ -int32_t lps25hb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lps25hb_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lps25hb_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lps25hb_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -420,8 +420,8 @@ float_t lps25hb_from_lsb_to_hpa(uint32_t lsb); float_t lps25hb_from_lsb_to_degc(int16_t lsb); -int32_t lps25hb_pressure_ref_set(stmdev_ctx_t *ctx, int32_t val); -int32_t lps25hb_pressure_ref_get(stmdev_ctx_t *ctx, int32_t *val); +int32_t lps25hb_pressure_ref_set(const stmdev_ctx_t *ctx, int32_t val); +int32_t lps25hb_pressure_ref_get(const stmdev_ctx_t *ctx, int32_t *val); typedef enum { @@ -430,9 +430,9 @@ typedef enum LPS25HB_P_AVG_32 = 2, LPS25HB_P_AVG_64 = 3, } lps25hb_avgp_t; -int32_t lps25hb_pressure_avg_set(stmdev_ctx_t *ctx, +int32_t lps25hb_pressure_avg_set(const stmdev_ctx_t *ctx, lps25hb_avgp_t val); -int32_t lps25hb_pressure_avg_get(stmdev_ctx_t *ctx, +int32_t lps25hb_pressure_avg_get(const stmdev_ctx_t *ctx, lps25hb_avgp_t *val); typedef enum @@ -442,16 +442,16 @@ typedef enum LPS25HB_T_AVG_32 = 2, LPS25HB_T_AVG_64 = 3, } lps25hb_avgt_t; -int32_t lps25hb_temperature_avg_set(stmdev_ctx_t *ctx, +int32_t lps25hb_temperature_avg_set(const stmdev_ctx_t *ctx, lps25hb_avgt_t val); -int32_t lps25hb_temperature_avg_get(stmdev_ctx_t *ctx, +int32_t lps25hb_temperature_avg_get(const stmdev_ctx_t *ctx, lps25hb_avgt_t *val); -int32_t lps25hb_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps25hb_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps25hb_autozero_rst_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps25hb_autozero_rst_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps25hb_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps25hb_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lps25hb_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps25hb_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -463,49 +463,49 @@ typedef enum LPS25HB_ODR_25Hz = 12, LPS25HB_ONE_SHOT = 8, } lps25hb_odr_t; -int32_t lps25hb_data_rate_set(stmdev_ctx_t *ctx, lps25hb_odr_t val); -int32_t lps25hb_data_rate_get(stmdev_ctx_t *ctx, lps25hb_odr_t *val); +int32_t lps25hb_data_rate_set(const stmdev_ctx_t *ctx, lps25hb_odr_t val); +int32_t lps25hb_data_rate_get(const stmdev_ctx_t *ctx, lps25hb_odr_t *val); -int32_t lps25hb_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps25hb_one_shoot_trigger_get(stmdev_ctx_t *ctx, +int32_t lps25hb_one_shoot_trigger_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps25hb_one_shoot_trigger_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps25hb_autozero_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps25hb_autozero_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps25hb_autozero_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps25hb_autozero_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps25hb_fifo_mean_decimator_set(stmdev_ctx_t *ctx, +int32_t lps25hb_fifo_mean_decimator_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lps25hb_fifo_mean_decimator_get(stmdev_ctx_t *ctx, +int32_t lps25hb_fifo_mean_decimator_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps25hb_press_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps25hb_press_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps25hb_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps25hb_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps25hb_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps25hb_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps25hb_press_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps25hb_press_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps25hb_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff); +int32_t lps25hb_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff); -int32_t lps25hb_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff); +int32_t lps25hb_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff); -int32_t lps25hb_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val); -int32_t lps25hb_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lps25hb_pressure_offset_set(const stmdev_ctx_t *ctx, int16_t val); +int32_t lps25hb_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lps25hb_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lps25hb_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lps25hb_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps25hb_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps25hb_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps25hb_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps25hb_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps25hb_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps25hb_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps25hb_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps25hb_status_get(stmdev_ctx_t *ctx, +int32_t lps25hb_status_get(const stmdev_ctx_t *ctx, lps25hb_status_reg_t *val); -int32_t lps25hb_int_generation_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps25hb_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps25hb_int_generation_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps25hb_int_generation_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -514,9 +514,9 @@ typedef enum LPS25HB_LOW_PRES_INT = 2, LPS25HB_EVERY_PRES_INT = 3, } lps25hb_int_s_t; -int32_t lps25hb_int_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lps25hb_int_pin_mode_set(const stmdev_ctx_t *ctx, lps25hb_int_s_t val); -int32_t lps25hb_int_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lps25hb_int_pin_mode_get(const stmdev_ctx_t *ctx, lps25hb_int_s_t *val); typedef enum @@ -524,32 +524,32 @@ typedef enum LPS25HB_PUSH_PULL = 0, LPS25HB_OPEN_DRAIN = 1, } lps25hb_pp_od_t; -int32_t lps25hb_pin_mode_set(stmdev_ctx_t *ctx, lps25hb_pp_od_t val); -int32_t lps25hb_pin_mode_get(stmdev_ctx_t *ctx, lps25hb_pp_od_t *val); +int32_t lps25hb_pin_mode_set(const stmdev_ctx_t *ctx, lps25hb_pp_od_t val); +int32_t lps25hb_pin_mode_get(const stmdev_ctx_t *ctx, lps25hb_pp_od_t *val); typedef enum { LPS25HB_ACTIVE_HIGH = 0, LPS25HB_ACTIVE_LOW = 1, } lps25hb_int_h_l_t; -int32_t lps25hb_int_polarity_set(stmdev_ctx_t *ctx, +int32_t lps25hb_int_polarity_set(const stmdev_ctx_t *ctx, lps25hb_int_h_l_t val); -int32_t lps25hb_int_polarity_get(stmdev_ctx_t *ctx, +int32_t lps25hb_int_polarity_get(const stmdev_ctx_t *ctx, lps25hb_int_h_l_t *val); -int32_t lps25hb_drdy_on_int_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps25hb_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps25hb_drdy_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps25hb_drdy_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps25hb_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps25hb_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps25hb_fifo_ovr_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps25hb_fifo_ovr_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps25hb_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, +int32_t lps25hb_fifo_threshold_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lps25hb_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, +int32_t lps25hb_fifo_threshold_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps25hb_fifo_empty_on_int_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps25hb_fifo_empty_on_int_get(stmdev_ctx_t *ctx, +int32_t lps25hb_fifo_empty_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps25hb_fifo_empty_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -559,9 +559,9 @@ typedef enum LPS25HB_NEGATIVE = 2, LPS25HB_BOTH = 3, } lps25hb_pe_t; -int32_t lps25hb_sign_of_int_threshold_set(stmdev_ctx_t *ctx, +int32_t lps25hb_sign_of_int_threshold_set(const stmdev_ctx_t *ctx, lps25hb_pe_t val); -int32_t lps25hb_sign_of_int_threshold_get(stmdev_ctx_t *ctx, +int32_t lps25hb_sign_of_int_threshold_get(const stmdev_ctx_t *ctx, lps25hb_pe_t *val); typedef enum @@ -569,34 +569,34 @@ typedef enum LPS25HB_INT_PULSED = 0, LPS25HB_INT_LATCHED = 1, } lps25hb_lir_t; -int32_t lps25hb_int_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lps25hb_int_notification_mode_set(const stmdev_ctx_t *ctx, lps25hb_lir_t val); -int32_t lps25hb_int_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lps25hb_int_notification_mode_get(const stmdev_ctx_t *ctx, lps25hb_lir_t *val); -int32_t lps25hb_int_source_get(stmdev_ctx_t *ctx, +int32_t lps25hb_int_source_get(const stmdev_ctx_t *ctx, lps25hb_int_source_t *val); -int32_t lps25hb_int_on_press_high_get(stmdev_ctx_t *ctx, +int32_t lps25hb_int_on_press_high_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps25hb_int_on_press_low_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps25hb_int_on_press_low_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps25hb_interrupt_event_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps25hb_interrupt_event_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps25hb_int_threshold_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lps25hb_int_threshold_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lps25hb_int_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lps25hb_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lps25hb_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx, +int32_t lps25hb_stop_on_fifo_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lps25hb_stop_on_fifo_threshold_get(stmdev_ctx_t *ctx, +int32_t lps25hb_stop_on_fifo_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps25hb_fifo_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps25hb_fifo_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps25hb_fifo_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps25hb_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps25hb_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps25hb_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps25hb_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps25hb_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -608,38 +608,38 @@ typedef enum LPS25HB_MEAN_MODE = 6, LPS25HB_BYPASS_TO_FIFO_MODE = 7, } lps25hb_f_mode_t; -int32_t lps25hb_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lps25hb_fifo_mode_set(const stmdev_ctx_t *ctx, lps25hb_f_mode_t val); -int32_t lps25hb_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lps25hb_fifo_mode_get(const stmdev_ctx_t *ctx, lps25hb_f_mode_t *val); -int32_t lps25hb_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lps25hb_fifo_status_get(const stmdev_ctx_t *ctx, lps25hb_fifo_status_t *val); -int32_t lps25hb_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps25hb_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps25hb_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps25hb_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps25hb_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps25hb_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps25hb_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps25hb_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LPS25HB_SPI_4_WIRE = 0, LPS25HB_SPI_3_WIRE = 1, } lps25hb_sim_t; -int32_t lps25hb_spi_mode_set(stmdev_ctx_t *ctx, lps25hb_sim_t val); -int32_t lps25hb_spi_mode_get(stmdev_ctx_t *ctx, lps25hb_sim_t *val); +int32_t lps25hb_spi_mode_set(const stmdev_ctx_t *ctx, lps25hb_sim_t val); +int32_t lps25hb_spi_mode_get(const stmdev_ctx_t *ctx, lps25hb_sim_t *val); typedef enum { LPS25HB_I2C_ENABLE = 0, LPS25HB_I2C_DISABLE = 1, } lps25hb_i2c_dis_t; -int32_t lps25hb_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lps25hb_i2c_interface_set(const stmdev_ctx_t *ctx, lps25hb_i2c_dis_t val); -int32_t lps25hb_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lps25hb_i2c_interface_get(const stmdev_ctx_t *ctx, lps25hb_i2c_dis_t *val); /** diff --git a/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.c b/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.c index ed3291d6..ebd20c3b 100644 --- a/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.c +++ b/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lps27hhtw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lps27hhtw_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lps27hhtw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lps27hhtw_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lps27hhtw_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -120,7 +130,7 @@ float_t lps27hhtw_from_lsb_to_celsius(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps27hhtw_autozero_rst_set(const stmdev_ctx_t *ctx, uint8_t val) { lps27hhtw_interrupt_cfg_t reg; int32_t ret; @@ -146,7 +156,7 @@ int32_t lps27hhtw_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps27hhtw_autozero_rst_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhtw_interrupt_cfg_t reg; int32_t ret; @@ -166,7 +176,7 @@ int32_t lps27hhtw_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_autozero_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps27hhtw_autozero_set(const stmdev_ctx_t *ctx, uint8_t val) { lps27hhtw_interrupt_cfg_t reg; int32_t ret; @@ -192,7 +202,7 @@ int32_t lps27hhtw_autozero_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_autozero_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps27hhtw_autozero_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhtw_interrupt_cfg_t reg; int32_t ret; @@ -212,7 +222,7 @@ int32_t lps27hhtw_autozero_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_pressure_snap_rst_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_pressure_snap_rst_set(const stmdev_ctx_t *ctx, uint8_t val) { lps27hhtw_interrupt_cfg_t reg; @@ -239,7 +249,7 @@ int32_t lps27hhtw_pressure_snap_rst_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_pressure_snap_rst_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_pressure_snap_rst_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhtw_interrupt_cfg_t reg; @@ -260,7 +270,7 @@ int32_t lps27hhtw_pressure_snap_rst_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps27hhtw_pressure_snap_set(const stmdev_ctx_t *ctx, uint8_t val) { lps27hhtw_interrupt_cfg_t reg; int32_t ret; @@ -286,7 +296,7 @@ int32_t lps27hhtw_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps27hhtw_pressure_snap_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhtw_interrupt_cfg_t reg; int32_t ret; @@ -306,7 +316,7 @@ int32_t lps27hhtw_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_block_data_update_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lps27hhtw_ctrl_reg1_t reg; @@ -331,7 +341,7 @@ int32_t lps27hhtw_block_data_update_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhtw_ctrl_reg1_t reg; @@ -351,7 +361,7 @@ int32_t lps27hhtw_block_data_update_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_data_rate_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_data_rate_set(const stmdev_ctx_t *ctx, lps27hhtw_odr_t val) { lps27hhtw_ctrl_reg1_t ctrl_reg1; @@ -393,7 +403,7 @@ int32_t lps27hhtw_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_data_rate_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_data_rate_get(const stmdev_ctx_t *ctx, lps27hhtw_odr_t *val) { lps27hhtw_ctrl_reg1_t ctrl_reg1; @@ -492,7 +502,7 @@ int32_t lps27hhtw_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_pressure_ref_set(stmdev_ctx_t *ctx, int16_t val) +int32_t lps27hhtw_pressure_ref_set(const stmdev_ctx_t *ctx, int16_t val) { uint8_t buff[2]; int32_t ret; @@ -515,7 +525,7 @@ int32_t lps27hhtw_pressure_ref_set(stmdev_ctx_t *ctx, int16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_pressure_ref_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lps27hhtw_pressure_ref_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -537,7 +547,7 @@ int32_t lps27hhtw_pressure_ref_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val) +int32_t lps27hhtw_pressure_offset_set(const stmdev_ctx_t *ctx, int16_t val) { uint8_t buff[2]; int32_t ret; @@ -560,7 +570,7 @@ int32_t lps27hhtw_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lps27hhtw_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -580,7 +590,7 @@ int32_t lps27hhtw_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_all_sources_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_all_sources_get(const stmdev_ctx_t *ctx, lps27hhtw_all_sources_t *val) { int32_t ret; @@ -611,7 +621,7 @@ int32_t lps27hhtw_all_sources_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_status_reg_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_status_reg_get(const stmdev_ctx_t *ctx, lps27hhtw_status_t *val) { int32_t ret; @@ -629,7 +639,7 @@ int32_t lps27hhtw_status_reg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_press_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_press_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhtw_status_t reg; @@ -649,7 +659,7 @@ int32_t lps27hhtw_press_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhtw_status_t reg; @@ -681,7 +691,7 @@ int32_t lps27hhtw_temp_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff) +int32_t lps27hhtw_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff) { uint8_t reg[3]; int32_t ret; @@ -703,7 +713,7 @@ int32_t lps27hhtw_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) { uint8_t reg[2]; @@ -724,7 +734,7 @@ int32_t lps27hhtw_temperature_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_fifo_pressure_raw_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_fifo_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff) { uint8_t reg[3]; @@ -748,7 +758,7 @@ int32_t lps27hhtw_fifo_pressure_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_fifo_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_fifo_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) { uint8_t reg[2]; @@ -782,7 +792,7 @@ int32_t lps27hhtw_fifo_temperature_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lps27hhtw_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -800,7 +810,7 @@ int32_t lps27hhtw_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps27hhtw_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lps27hhtw_ctrl_reg2_t reg; int32_t ret; @@ -825,7 +835,7 @@ int32_t lps27hhtw_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps27hhtw_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhtw_ctrl_reg2_t reg; int32_t ret; @@ -846,7 +856,7 @@ int32_t lps27hhtw_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps27hhtw_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { lps27hhtw_ctrl_reg2_t reg; int32_t ret; @@ -872,7 +882,7 @@ int32_t lps27hhtw_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps27hhtw_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhtw_ctrl_reg2_t reg; int32_t ret; @@ -892,7 +902,7 @@ int32_t lps27hhtw_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps27hhtw_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lps27hhtw_ctrl_reg2_t reg; int32_t ret; @@ -917,7 +927,7 @@ int32_t lps27hhtw_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps27hhtw_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhtw_ctrl_reg2_t reg; int32_t ret; @@ -949,7 +959,7 @@ int32_t lps27hhtw_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_lp_bandwidth_set(const stmdev_ctx_t *ctx, lps27hhtw_lpfp_cfg_t val) { lps27hhtw_ctrl_reg1_t reg; @@ -974,7 +984,7 @@ int32_t lps27hhtw_lp_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_lp_bandwidth_get(const stmdev_ctx_t *ctx, lps27hhtw_lpfp_cfg_t *val) { lps27hhtw_ctrl_reg1_t reg; @@ -1025,7 +1035,7 @@ int32_t lps27hhtw_lp_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_i2c_interface_set(const stmdev_ctx_t *ctx, lps27hhtw_i2c_disable_t val) { lps27hhtw_if_ctrl_t reg; @@ -1050,7 +1060,7 @@ int32_t lps27hhtw_i2c_interface_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_i2c_interface_get(const stmdev_ctx_t *ctx, lps27hhtw_i2c_disable_t *val) { lps27hhtw_if_ctrl_t reg; @@ -1084,7 +1094,7 @@ int32_t lps27hhtw_i2c_interface_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_i3c_interface_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_i3c_interface_set(const stmdev_ctx_t *ctx, lps27hhtw_i3c_disable_t val) { lps27hhtw_if_ctrl_t reg; @@ -1110,7 +1120,7 @@ int32_t lps27hhtw_i3c_interface_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_i3c_interface_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_i3c_interface_get(const stmdev_ctx_t *ctx, lps27hhtw_i3c_disable_t *val) { lps27hhtw_if_ctrl_t reg; @@ -1148,7 +1158,7 @@ int32_t lps27hhtw_i3c_interface_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, lps27hhtw_pu_en_t val) { lps27hhtw_if_ctrl_t reg; @@ -1173,7 +1183,7 @@ int32_t lps27hhtw_sdo_sa0_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, lps27hhtw_pu_en_t *val) { lps27hhtw_if_ctrl_t reg; @@ -1207,7 +1217,7 @@ int32_t lps27hhtw_sdo_sa0_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_sda_mode_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_sda_mode_set(const stmdev_ctx_t *ctx, lps27hhtw_pu_en_t val) { lps27hhtw_if_ctrl_t reg; @@ -1232,7 +1242,7 @@ int32_t lps27hhtw_sda_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_sda_mode_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_sda_mode_get(const stmdev_ctx_t *ctx, lps27hhtw_pu_en_t *val) { lps27hhtw_if_ctrl_t reg; @@ -1266,7 +1276,7 @@ int32_t lps27hhtw_sda_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_spi_mode_set(stmdev_ctx_t *ctx, lps27hhtw_sim_t val) +int32_t lps27hhtw_spi_mode_set(const stmdev_ctx_t *ctx, lps27hhtw_sim_t val) { lps27hhtw_ctrl_reg1_t reg; int32_t ret; @@ -1290,7 +1300,7 @@ int32_t lps27hhtw_spi_mode_set(stmdev_ctx_t *ctx, lps27hhtw_sim_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_spi_mode_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_spi_mode_get(const stmdev_ctx_t *ctx, lps27hhtw_sim_t *val) { lps27hhtw_ctrl_reg1_t reg; @@ -1337,7 +1347,7 @@ int32_t lps27hhtw_spi_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_int_notification_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_int_notification_set(const stmdev_ctx_t *ctx, lps27hhtw_lir_t val) { lps27hhtw_interrupt_cfg_t reg; @@ -1364,7 +1374,7 @@ int32_t lps27hhtw_int_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_int_notification_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_int_notification_get(const stmdev_ctx_t *ctx, lps27hhtw_lir_t *val) { lps27hhtw_interrupt_cfg_t reg; @@ -1399,7 +1409,7 @@ int32_t lps27hhtw_int_notification_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_pin_mode_set(const stmdev_ctx_t *ctx, lps27hhtw_pp_od_t val) { lps27hhtw_ctrl_reg2_t reg; @@ -1424,7 +1434,7 @@ int32_t lps27hhtw_pin_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_pin_mode_get(const stmdev_ctx_t *ctx, lps27hhtw_pp_od_t *val) { lps27hhtw_ctrl_reg2_t reg; @@ -1458,7 +1468,7 @@ int32_t lps27hhtw_pin_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_pin_polarity_set(const stmdev_ctx_t *ctx, lps27hhtw_int_h_l_t val) { lps27hhtw_ctrl_reg2_t reg; @@ -1483,7 +1493,7 @@ int32_t lps27hhtw_pin_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_pin_polarity_get(const stmdev_ctx_t *ctx, lps27hhtw_int_h_l_t *val) { lps27hhtw_ctrl_reg2_t reg; @@ -1517,7 +1527,7 @@ int32_t lps27hhtw_pin_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_pin_int_route_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_pin_int_route_set(const stmdev_ctx_t *ctx, lps27hhtw_ctrl_reg3_t *val) { int32_t ret; @@ -1535,7 +1545,7 @@ int32_t lps27hhtw_pin_int_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_pin_int_route_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_pin_int_route_get(const stmdev_ctx_t *ctx, lps27hhtw_ctrl_reg3_t *val) { int32_t ret; @@ -1566,7 +1576,7 @@ int32_t lps27hhtw_pin_int_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_int_on_threshold_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_int_on_threshold_set(const stmdev_ctx_t *ctx, lps27hhtw_pe_t val) { lps27hhtw_interrupt_cfg_t reg; @@ -1604,7 +1614,7 @@ int32_t lps27hhtw_int_on_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_int_on_threshold_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_int_on_threshold_get(const stmdev_ctx_t *ctx, lps27hhtw_pe_t *val) { lps27hhtw_interrupt_cfg_t reg; @@ -1647,7 +1657,7 @@ int32_t lps27hhtw_int_on_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_int_treshold_set(stmdev_ctx_t *ctx, uint16_t buff) +int32_t lps27hhtw_int_threshold_set(const stmdev_ctx_t *ctx, uint16_t buff) { int32_t ret; @@ -1675,7 +1685,7 @@ int32_t lps27hhtw_int_treshold_set(stmdev_ctx_t *ctx, uint16_t buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_int_treshold_get(stmdev_ctx_t *ctx, uint16_t *buff) +int32_t lps27hhtw_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *buff) { int32_t ret; @@ -1715,7 +1725,7 @@ int32_t lps27hhtw_int_treshold_get(stmdev_ctx_t *ctx, uint16_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_fifo_mode_set(const stmdev_ctx_t *ctx, lps27hhtw_f_mode_t val) { lps27hhtw_fifo_ctrl_t reg; @@ -1740,7 +1750,7 @@ int32_t lps27hhtw_fifo_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_fifo_mode_get(const stmdev_ctx_t *ctx, lps27hhtw_f_mode_t *val) { lps27hhtw_fifo_ctrl_t reg; @@ -1795,7 +1805,7 @@ int32_t lps27hhtw_fifo_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps27hhtw_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) { lps27hhtw_fifo_ctrl_t reg; int32_t ret; @@ -1820,7 +1830,7 @@ int32_t lps27hhtw_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhtw_fifo_ctrl_t reg; @@ -1840,7 +1850,7 @@ int32_t lps27hhtw_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps27hhtw_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { lps27hhtw_fifo_wtm_t reg; int32_t ret; @@ -1864,7 +1874,7 @@ int32_t lps27hhtw_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps27hhtw_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhtw_fifo_wtm_t reg; int32_t ret; @@ -1883,7 +1893,7 @@ int32_t lps27hhtw_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_fifo_data_level_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1901,7 +1911,7 @@ int32_t lps27hhtw_fifo_data_level_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_fifo_src_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_fifo_src_get(const stmdev_ctx_t *ctx, lps27hhtw_fifo_status2_t *val) { int32_t ret; @@ -1920,7 +1930,7 @@ int32_t lps27hhtw_fifo_src_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps27hhtw_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhtw_fifo_status2_t reg; int32_t ret; @@ -1940,7 +1950,7 @@ int32_t lps27hhtw_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps27hhtw_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhtw_fifo_status2_t reg; int32_t ret; @@ -1960,7 +1970,7 @@ int32_t lps27hhtw_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps27hhtw_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhtw_fifo_status2_t reg; int32_t ret; @@ -1979,7 +1989,7 @@ int32_t lps27hhtw_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps27hhtw_fifo_ovr_on_int_set(const stmdev_ctx_t *ctx, uint8_t val) { lps27hhtw_ctrl_reg3_t reg; int32_t ret; @@ -2003,7 +2013,7 @@ int32_t lps27hhtw_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps27hhtw_fifo_ovr_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhtw_ctrl_reg3_t reg; int32_t ret; @@ -2022,7 +2032,7 @@ int32_t lps27hhtw_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_fifo_threshold_on_int_set(const stmdev_ctx_t *ctx, uint8_t val) { lps27hhtw_ctrl_reg3_t reg; @@ -2047,7 +2057,7 @@ int32_t lps27hhtw_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_fifo_threshold_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhtw_ctrl_reg3_t reg; @@ -2067,7 +2077,7 @@ int32_t lps27hhtw_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps27hhtw_fifo_full_on_int_set(const stmdev_ctx_t *ctx, uint8_t val) { lps27hhtw_ctrl_reg3_t reg; int32_t ret; @@ -2091,7 +2101,7 @@ int32_t lps27hhtw_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhtw_fifo_full_on_int_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_fifo_full_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhtw_ctrl_reg3_t reg; diff --git a/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.h b/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.h index b4106a94..0b2f2b07 100644 --- a/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.h +++ b/sensor/stmemsc/lps27hhtw_STdC/driver/lps27hhtw_reg.h @@ -311,15 +311,13 @@ typedef struct typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN -uint8_t f_mode : - 3; /* f_mode + trig_modes */ + uint8_t f_mode : 3; /* f_mode + trig_modes */ uint8_t stop_on_wtm : 1; uint8_t not_used_01 : 4; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN uint8_t not_used_01 : 4; uint8_t stop_on_wtm : 1; -uint8_t f_mode : - 3; /* f_mode + trig_modes */ + uint8_t f_mode : 3; /* f_mode + trig_modes */ #endif /* DRV_BYTE_ORDER */ } lps27hhtw_fifo_ctrl_t; @@ -451,10 +449,10 @@ typedef union * them with a custom implementation. */ -int32_t lps27hhtw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lps27hhtw_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lps27hhtw_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lps27hhtw_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -462,23 +460,23 @@ float_t lps27hhtw_from_lsb_to_hpa(int32_t lsb); float_t lps27hhtw_from_lsb_to_celsius(int16_t lsb); -int32_t lps27hhtw_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps27hhtw_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps27hhtw_autozero_rst_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps27hhtw_autozero_rst_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhtw_autozero_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps27hhtw_autozero_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps27hhtw_autozero_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps27hhtw_autozero_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhtw_pressure_snap_rst_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_pressure_snap_rst_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lps27hhtw_pressure_snap_rst_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_pressure_snap_rst_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhtw_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps27hhtw_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps27hhtw_pressure_snap_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps27hhtw_pressure_snap_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhtw_block_data_update_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lps27hhtw_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -498,16 +496,16 @@ typedef enum LPS27HHTW_100_Hz = 0x06, LPS27HHTW_200_Hz = 0x07, } lps27hhtw_odr_t; -int32_t lps27hhtw_data_rate_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_data_rate_set(const stmdev_ctx_t *ctx, lps27hhtw_odr_t val); -int32_t lps27hhtw_data_rate_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_data_rate_get(const stmdev_ctx_t *ctx, lps27hhtw_odr_t *val); -int32_t lps27hhtw_pressure_ref_set(stmdev_ctx_t *ctx, int16_t val); -int32_t lps27hhtw_pressure_ref_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lps27hhtw_pressure_ref_set(const stmdev_ctx_t *ctx, int16_t val); +int32_t lps27hhtw_pressure_ref_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lps27hhtw_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val); -int32_t lps27hhtw_pressure_offset_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_pressure_offset_set(const stmdev_ctx_t *ctx, int16_t val); +int32_t lps27hhtw_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val); typedef struct @@ -516,39 +514,39 @@ typedef struct lps27hhtw_fifo_status2_t fifo_status2; lps27hhtw_status_t status; } lps27hhtw_all_sources_t; -int32_t lps27hhtw_all_sources_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_all_sources_get(const stmdev_ctx_t *ctx, lps27hhtw_all_sources_t *val); -int32_t lps27hhtw_status_reg_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_status_reg_get(const stmdev_ctx_t *ctx, lps27hhtw_status_t *val); -int32_t lps27hhtw_press_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_press_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhtw_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhtw_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff); +int32_t lps27hhtw_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff); -int32_t lps27hhtw_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff); -int32_t lps27hhtw_fifo_pressure_raw_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_fifo_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff); -int32_t lps27hhtw_fifo_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_fifo_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff); -int32_t lps27hhtw_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lps27hhtw_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lps27hhtw_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps27hhtw_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps27hhtw_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps27hhtw_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhtw_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps27hhtw_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps27hhtw_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps27hhtw_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhtw_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps27hhtw_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps27hhtw_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps27hhtw_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -556,9 +554,9 @@ typedef enum LPS27HHTW_LPF_ODR_DIV_9 = 2, LPS27HHTW_LPF_ODR_DIV_20 = 3, } lps27hhtw_lpfp_cfg_t; -int32_t lps27hhtw_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_lp_bandwidth_set(const stmdev_ctx_t *ctx, lps27hhtw_lpfp_cfg_t val); -int32_t lps27hhtw_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_lp_bandwidth_get(const stmdev_ctx_t *ctx, lps27hhtw_lpfp_cfg_t *val); typedef enum @@ -566,9 +564,9 @@ typedef enum LPS27HHTW_I2C_ENABLE = 0, LPS27HHTW_I2C_DISABLE = 1, } lps27hhtw_i2c_disable_t; -int32_t lps27hhtw_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_i2c_interface_set(const stmdev_ctx_t *ctx, lps27hhtw_i2c_disable_t val); -int32_t lps27hhtw_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_i2c_interface_get(const stmdev_ctx_t *ctx, lps27hhtw_i2c_disable_t *val); typedef enum @@ -577,9 +575,9 @@ typedef enum LPS27HHTW_I3C_ENABLE_INT_PIN_ENABLE = 0x10, LPS27HHTW_I3C_DISABLE = 0x11, } lps27hhtw_i3c_disable_t; -int32_t lps27hhtw_i3c_interface_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_i3c_interface_set(const stmdev_ctx_t *ctx, lps27hhtw_i3c_disable_t val); -int32_t lps27hhtw_i3c_interface_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_i3c_interface_get(const stmdev_ctx_t *ctx, lps27hhtw_i3c_disable_t *val); typedef enum @@ -587,13 +585,13 @@ typedef enum LPS27HHTW_PULL_UP_DISCONNECT = 0, LPS27HHTW_PULL_UP_CONNECT = 1, } lps27hhtw_pu_en_t; -int32_t lps27hhtw_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, lps27hhtw_pu_en_t val); -int32_t lps27hhtw_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, lps27hhtw_pu_en_t *val); -int32_t lps27hhtw_sda_mode_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_sda_mode_set(const stmdev_ctx_t *ctx, lps27hhtw_pu_en_t val); -int32_t lps27hhtw_sda_mode_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_sda_mode_get(const stmdev_ctx_t *ctx, lps27hhtw_pu_en_t *val); typedef enum @@ -601,9 +599,9 @@ typedef enum LPS27HHTW_SPI_4_WIRE = 0, LPS27HHTW_SPI_3_WIRE = 1, } lps27hhtw_sim_t; -int32_t lps27hhtw_spi_mode_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_spi_mode_set(const stmdev_ctx_t *ctx, lps27hhtw_sim_t val); -int32_t lps27hhtw_spi_mode_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_spi_mode_get(const stmdev_ctx_t *ctx, lps27hhtw_sim_t *val); typedef enum @@ -611,9 +609,9 @@ typedef enum LPS27HHTW_INT_PULSED = 0, LPS27HHTW_INT_LATCHED = 1, } lps27hhtw_lir_t; -int32_t lps27hhtw_int_notification_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_int_notification_set(const stmdev_ctx_t *ctx, lps27hhtw_lir_t val); -int32_t lps27hhtw_int_notification_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_int_notification_get(const stmdev_ctx_t *ctx, lps27hhtw_lir_t *val); typedef enum @@ -621,9 +619,9 @@ typedef enum LPS27HHTW_PUSH_PULL = 0, LPS27HHTW_OPEN_DRAIN = 1, } lps27hhtw_pp_od_t; -int32_t lps27hhtw_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_pin_mode_set(const stmdev_ctx_t *ctx, lps27hhtw_pp_od_t val); -int32_t lps27hhtw_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_pin_mode_get(const stmdev_ctx_t *ctx, lps27hhtw_pp_od_t *val); typedef enum @@ -631,14 +629,14 @@ typedef enum LPS27HHTW_ACTIVE_HIGH = 0, LPS27HHTW_ACTIVE_LOW = 1, } lps27hhtw_int_h_l_t; -int32_t lps27hhtw_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_pin_polarity_set(const stmdev_ctx_t *ctx, lps27hhtw_int_h_l_t val); -int32_t lps27hhtw_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_pin_polarity_get(const stmdev_ctx_t *ctx, lps27hhtw_int_h_l_t *val); -int32_t lps27hhtw_pin_int_route_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_pin_int_route_set(const stmdev_ctx_t *ctx, lps27hhtw_ctrl_reg3_t *val); -int32_t lps27hhtw_pin_int_route_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_pin_int_route_get(const stmdev_ctx_t *ctx, lps27hhtw_ctrl_reg3_t *val); typedef enum @@ -648,13 +646,13 @@ typedef enum LPS27HHTW_NEGATIVE = 2, LPS27HHTW_BOTH = 3, } lps27hhtw_pe_t; -int32_t lps27hhtw_int_on_threshold_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_int_on_threshold_set(const stmdev_ctx_t *ctx, lps27hhtw_pe_t val); -int32_t lps27hhtw_int_on_threshold_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_int_on_threshold_get(const stmdev_ctx_t *ctx, lps27hhtw_pe_t *val); -int32_t lps27hhtw_int_treshold_set(stmdev_ctx_t *ctx, uint16_t buff); -int32_t lps27hhtw_int_treshold_get(stmdev_ctx_t *ctx, uint16_t *buff); +int32_t lps27hhtw_int_threshold_set(const stmdev_ctx_t *ctx, uint16_t buff); +int32_t lps27hhtw_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *buff); typedef enum { @@ -666,43 +664,43 @@ typedef enum LPS27HHTW_BYPASS_TO_STREAM_MODE = 6, LPS27HHTW_STREAM_TO_FIFO_MODE = 7, } lps27hhtw_f_mode_t; -int32_t lps27hhtw_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_fifo_mode_set(const stmdev_ctx_t *ctx, lps27hhtw_f_mode_t val); -int32_t lps27hhtw_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_fifo_mode_get(const stmdev_ctx_t *ctx, lps27hhtw_f_mode_t *val); -int32_t lps27hhtw_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lps27hhtw_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhtw_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps27hhtw_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps27hhtw_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps27hhtw_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhtw_fifo_data_level_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lps27hhtw_fifo_src_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_fifo_src_get(const stmdev_ctx_t *ctx, lps27hhtw_fifo_status2_t *val); -int32_t lps27hhtw_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps27hhtw_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhtw_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps27hhtw_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhtw_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps27hhtw_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhtw_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps27hhtw_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_fifo_ovr_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps27hhtw_fifo_ovr_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhtw_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_fifo_threshold_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lps27hhtw_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_fifo_threshold_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhtw_fifo_full_on_int_set(stmdev_ctx_t *ctx, +int32_t lps27hhtw_fifo_full_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lps27hhtw_fifo_full_on_int_get(stmdev_ctx_t *ctx, +int32_t lps27hhtw_fifo_full_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val); /** diff --git a/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.c b/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.c index 74694618..24650a23 100644 --- a/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.c +++ b/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lps27hhw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lps27hhw_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lps27hhw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lps27hhw_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lps27hhw_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -120,7 +130,7 @@ float_t lps27hhw_from_lsb_to_celsius(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps27hhw_autozero_rst_set(const stmdev_ctx_t *ctx, uint8_t val) { lps27hhw_interrupt_cfg_t reg; int32_t ret; @@ -145,7 +155,7 @@ int32_t lps27hhw_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps27hhw_autozero_rst_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhw_interrupt_cfg_t reg; int32_t ret; @@ -164,7 +174,7 @@ int32_t lps27hhw_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_autozero_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps27hhw_autozero_set(const stmdev_ctx_t *ctx, uint8_t val) { lps27hhw_interrupt_cfg_t reg; int32_t ret; @@ -189,7 +199,7 @@ int32_t lps27hhw_autozero_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_autozero_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps27hhw_autozero_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhw_interrupt_cfg_t reg; int32_t ret; @@ -208,7 +218,7 @@ int32_t lps27hhw_autozero_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_pressure_snap_rst_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps27hhw_pressure_snap_rst_set(const stmdev_ctx_t *ctx, uint8_t val) { lps27hhw_interrupt_cfg_t reg; int32_t ret; @@ -233,7 +243,7 @@ int32_t lps27hhw_pressure_snap_rst_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_pressure_snap_rst_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_pressure_snap_rst_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhw_interrupt_cfg_t reg; @@ -253,7 +263,7 @@ int32_t lps27hhw_pressure_snap_rst_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps27hhw_pressure_snap_set(const stmdev_ctx_t *ctx, uint8_t val) { lps27hhw_interrupt_cfg_t reg; int32_t ret; @@ -278,7 +288,7 @@ int32_t lps27hhw_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps27hhw_pressure_snap_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhw_interrupt_cfg_t reg; int32_t ret; @@ -297,7 +307,7 @@ int32_t lps27hhw_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps27hhw_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lps27hhw_ctrl_reg1_t reg; int32_t ret; @@ -321,7 +331,7 @@ int32_t lps27hhw_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhw_ctrl_reg1_t reg; @@ -341,7 +351,7 @@ int32_t lps27hhw_block_data_update_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_data_rate_set(stmdev_ctx_t *ctx, lps27hhw_odr_t val) +int32_t lps27hhw_data_rate_set(const stmdev_ctx_t *ctx, lps27hhw_odr_t val) { lps27hhw_ctrl_reg1_t ctrl_reg1; lps27hhw_ctrl_reg2_t ctrl_reg2; @@ -382,7 +392,7 @@ int32_t lps27hhw_data_rate_set(stmdev_ctx_t *ctx, lps27hhw_odr_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_data_rate_get(stmdev_ctx_t *ctx, lps27hhw_odr_t *val) +int32_t lps27hhw_data_rate_get(const stmdev_ctx_t *ctx, lps27hhw_odr_t *val) { lps27hhw_ctrl_reg1_t ctrl_reg1; lps27hhw_ctrl_reg2_t ctrl_reg2; @@ -480,7 +490,7 @@ int32_t lps27hhw_data_rate_get(stmdev_ctx_t *ctx, lps27hhw_odr_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_pressure_ref_set(stmdev_ctx_t *ctx, int16_t val) +int32_t lps27hhw_pressure_ref_set(const stmdev_ctx_t *ctx, int16_t val) { uint8_t buff[2]; int32_t ret; @@ -503,7 +513,7 @@ int32_t lps27hhw_pressure_ref_set(stmdev_ctx_t *ctx, int16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_pressure_ref_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lps27hhw_pressure_ref_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -525,7 +535,7 @@ int32_t lps27hhw_pressure_ref_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val) +int32_t lps27hhw_pressure_offset_set(const stmdev_ctx_t *ctx, int16_t val) { uint8_t buff[2]; int32_t ret; @@ -548,7 +558,7 @@ int32_t lps27hhw_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lps27hhw_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -568,7 +578,7 @@ int32_t lps27hhw_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_all_sources_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_all_sources_get(const stmdev_ctx_t *ctx, lps27hhw_all_sources_t *val) { int32_t ret; @@ -599,7 +609,7 @@ int32_t lps27hhw_all_sources_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_status_reg_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_status_reg_get(const stmdev_ctx_t *ctx, lps27hhw_status_t *val) { int32_t ret; @@ -617,7 +627,7 @@ int32_t lps27hhw_status_reg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_press_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_press_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhw_status_t reg; @@ -637,7 +647,7 @@ int32_t lps27hhw_press_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhw_status_t reg; @@ -669,7 +679,7 @@ int32_t lps27hhw_temp_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff) +int32_t lps27hhw_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff) { uint8_t reg[3]; int32_t ret; @@ -691,7 +701,7 @@ int32_t lps27hhw_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff) +int32_t lps27hhw_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) { uint8_t reg[2]; int32_t ret; @@ -711,7 +721,7 @@ int32_t lps27hhw_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_fifo_pressure_raw_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_fifo_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff) { uint8_t reg[3]; @@ -735,7 +745,7 @@ int32_t lps27hhw_fifo_pressure_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_fifo_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_fifo_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) { uint8_t reg[2]; @@ -768,7 +778,7 @@ int32_t lps27hhw_fifo_temperature_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lps27hhw_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -786,7 +796,7 @@ int32_t lps27hhw_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps27hhw_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lps27hhw_ctrl_reg2_t reg; int32_t ret; @@ -811,7 +821,7 @@ int32_t lps27hhw_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps27hhw_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhw_ctrl_reg2_t reg; int32_t ret; @@ -832,7 +842,7 @@ int32_t lps27hhw_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps27hhw_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { lps27hhw_ctrl_reg2_t reg; int32_t ret; @@ -858,7 +868,7 @@ int32_t lps27hhw_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps27hhw_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhw_ctrl_reg2_t reg; int32_t ret; @@ -878,7 +888,7 @@ int32_t lps27hhw_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps27hhw_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lps27hhw_ctrl_reg2_t reg; int32_t ret; @@ -903,7 +913,7 @@ int32_t lps27hhw_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps27hhw_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhw_ctrl_reg2_t reg; int32_t ret; @@ -935,7 +945,7 @@ int32_t lps27hhw_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lps27hhw_lp_bandwidth_set(const stmdev_ctx_t *ctx, lps27hhw_lpfp_cfg_t val) { lps27hhw_ctrl_reg1_t reg; @@ -960,7 +970,7 @@ int32_t lps27hhw_lp_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_lp_bandwidth_get(const stmdev_ctx_t *ctx, lps27hhw_lpfp_cfg_t *val) { lps27hhw_ctrl_reg1_t reg; @@ -1011,7 +1021,7 @@ int32_t lps27hhw_lp_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lps27hhw_i2c_interface_set(const stmdev_ctx_t *ctx, lps27hhw_i2c_disable_t val) { lps27hhw_if_ctrl_t reg; @@ -1036,7 +1046,7 @@ int32_t lps27hhw_i2c_interface_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_i2c_interface_get(const stmdev_ctx_t *ctx, lps27hhw_i2c_disable_t *val) { lps27hhw_if_ctrl_t reg; @@ -1070,7 +1080,7 @@ int32_t lps27hhw_i2c_interface_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_i3c_interface_set(stmdev_ctx_t *ctx, +int32_t lps27hhw_i3c_interface_set(const stmdev_ctx_t *ctx, lps27hhw_i3c_disable_t val) { lps27hhw_if_ctrl_t reg; @@ -1096,7 +1106,7 @@ int32_t lps27hhw_i3c_interface_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_i3c_interface_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_i3c_interface_get(const stmdev_ctx_t *ctx, lps27hhw_i3c_disable_t *val) { lps27hhw_if_ctrl_t reg; @@ -1134,7 +1144,7 @@ int32_t lps27hhw_i3c_interface_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t lps27hhw_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, lps27hhw_pu_en_t val) { lps27hhw_if_ctrl_t reg; @@ -1159,7 +1169,7 @@ int32_t lps27hhw_sdo_sa0_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, lps27hhw_pu_en_t *val) { lps27hhw_if_ctrl_t reg; @@ -1193,7 +1203,7 @@ int32_t lps27hhw_sdo_sa0_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_sda_mode_set(stmdev_ctx_t *ctx, lps27hhw_pu_en_t val) +int32_t lps27hhw_sda_mode_set(const stmdev_ctx_t *ctx, lps27hhw_pu_en_t val) { lps27hhw_if_ctrl_t reg; int32_t ret; @@ -1217,7 +1227,7 @@ int32_t lps27hhw_sda_mode_set(stmdev_ctx_t *ctx, lps27hhw_pu_en_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_sda_mode_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_sda_mode_get(const stmdev_ctx_t *ctx, lps27hhw_pu_en_t *val) { lps27hhw_if_ctrl_t reg; @@ -1251,7 +1261,7 @@ int32_t lps27hhw_sda_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_spi_mode_set(stmdev_ctx_t *ctx, lps27hhw_sim_t val) +int32_t lps27hhw_spi_mode_set(const stmdev_ctx_t *ctx, lps27hhw_sim_t val) { lps27hhw_ctrl_reg1_t reg; int32_t ret; @@ -1275,7 +1285,7 @@ int32_t lps27hhw_spi_mode_set(stmdev_ctx_t *ctx, lps27hhw_sim_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_spi_mode_get(stmdev_ctx_t *ctx, lps27hhw_sim_t *val) +int32_t lps27hhw_spi_mode_get(const stmdev_ctx_t *ctx, lps27hhw_sim_t *val) { lps27hhw_ctrl_reg1_t reg; int32_t ret; @@ -1321,7 +1331,7 @@ int32_t lps27hhw_spi_mode_get(stmdev_ctx_t *ctx, lps27hhw_sim_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_int_notification_set(stmdev_ctx_t *ctx, +int32_t lps27hhw_int_notification_set(const stmdev_ctx_t *ctx, lps27hhw_lir_t val) { lps27hhw_interrupt_cfg_t reg; @@ -1347,7 +1357,7 @@ int32_t lps27hhw_int_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_int_notification_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_int_notification_get(const stmdev_ctx_t *ctx, lps27hhw_lir_t *val) { lps27hhw_interrupt_cfg_t reg; @@ -1381,7 +1391,7 @@ int32_t lps27hhw_int_notification_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_pin_mode_set(stmdev_ctx_t *ctx, lps27hhw_pp_od_t val) +int32_t lps27hhw_pin_mode_set(const stmdev_ctx_t *ctx, lps27hhw_pp_od_t val) { lps27hhw_ctrl_reg2_t reg; int32_t ret; @@ -1405,7 +1415,7 @@ int32_t lps27hhw_pin_mode_set(stmdev_ctx_t *ctx, lps27hhw_pp_od_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_pin_mode_get(const stmdev_ctx_t *ctx, lps27hhw_pp_od_t *val) { lps27hhw_ctrl_reg2_t reg; @@ -1439,7 +1449,7 @@ int32_t lps27hhw_pin_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lps27hhw_pin_polarity_set(const stmdev_ctx_t *ctx, lps27hhw_int_h_l_t val) { lps27hhw_ctrl_reg2_t reg; @@ -1464,7 +1474,7 @@ int32_t lps27hhw_pin_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_pin_polarity_get(const stmdev_ctx_t *ctx, lps27hhw_int_h_l_t *val) { lps27hhw_ctrl_reg2_t reg; @@ -1498,7 +1508,7 @@ int32_t lps27hhw_pin_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_pin_int_route_set(stmdev_ctx_t *ctx, +int32_t lps27hhw_pin_int_route_set(const stmdev_ctx_t *ctx, lps27hhw_ctrl_reg3_t *val) { int32_t ret; @@ -1516,7 +1526,7 @@ int32_t lps27hhw_pin_int_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_pin_int_route_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_pin_int_route_get(const stmdev_ctx_t *ctx, lps27hhw_ctrl_reg3_t *val) { int32_t ret; @@ -1547,7 +1557,7 @@ int32_t lps27hhw_pin_int_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_int_on_threshold_set(stmdev_ctx_t *ctx, +int32_t lps27hhw_int_on_threshold_set(const stmdev_ctx_t *ctx, lps27hhw_pe_t val) { lps27hhw_interrupt_cfg_t reg; @@ -1584,7 +1594,7 @@ int32_t lps27hhw_int_on_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_int_on_threshold_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_int_on_threshold_get(const stmdev_ctx_t *ctx, lps27hhw_pe_t *val) { lps27hhw_interrupt_cfg_t reg; @@ -1626,7 +1636,7 @@ int32_t lps27hhw_int_on_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_int_treshold_set(stmdev_ctx_t *ctx, uint16_t buff) +int32_t lps27hhw_int_threshold_set(const stmdev_ctx_t *ctx, uint16_t buff) { int32_t ret; @@ -1654,7 +1664,7 @@ int32_t lps27hhw_int_treshold_set(stmdev_ctx_t *ctx, uint16_t buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_int_treshold_get(stmdev_ctx_t *ctx, uint16_t *buff) +int32_t lps27hhw_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *buff) { int32_t ret; @@ -1694,7 +1704,7 @@ int32_t lps27hhw_int_treshold_get(stmdev_ctx_t *ctx, uint16_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lps27hhw_fifo_mode_set(const stmdev_ctx_t *ctx, lps27hhw_f_mode_t val) { lps27hhw_fifo_ctrl_t reg; @@ -1719,7 +1729,7 @@ int32_t lps27hhw_fifo_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_fifo_mode_get(const stmdev_ctx_t *ctx, lps27hhw_f_mode_t *val) { lps27hhw_fifo_ctrl_t reg; @@ -1774,7 +1784,7 @@ int32_t lps27hhw_fifo_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps27hhw_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) { lps27hhw_fifo_ctrl_t reg; int32_t ret; @@ -1799,7 +1809,7 @@ int32_t lps27hhw_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps27hhw_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhw_fifo_ctrl_t reg; int32_t ret; @@ -1818,7 +1828,7 @@ int32_t lps27hhw_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps27hhw_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { lps27hhw_fifo_wtm_t reg; int32_t ret; @@ -1842,7 +1852,7 @@ int32_t lps27hhw_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps27hhw_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhw_fifo_wtm_t reg; int32_t ret; @@ -1861,7 +1871,7 @@ int32_t lps27hhw_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lps27hhw_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1878,7 +1888,7 @@ int32_t lps27hhw_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_fifo_src_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_fifo_src_get(const stmdev_ctx_t *ctx, lps27hhw_fifo_status2_t *val) { int32_t ret; @@ -1896,7 +1906,7 @@ int32_t lps27hhw_fifo_src_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps27hhw_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhw_fifo_status2_t reg; int32_t ret; @@ -1915,7 +1925,7 @@ int32_t lps27hhw_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps27hhw_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhw_fifo_status2_t reg; int32_t ret; @@ -1934,7 +1944,7 @@ int32_t lps27hhw_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps27hhw_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhw_fifo_status2_t reg; int32_t ret; @@ -1953,7 +1963,7 @@ int32_t lps27hhw_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps27hhw_fifo_ovr_on_int_set(const stmdev_ctx_t *ctx, uint8_t val) { lps27hhw_ctrl_reg3_t reg; int32_t ret; @@ -1977,7 +1987,7 @@ int32_t lps27hhw_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps27hhw_fifo_ovr_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhw_ctrl_reg3_t reg; int32_t ret; @@ -1996,7 +2006,7 @@ int32_t lps27hhw_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, +int32_t lps27hhw_fifo_threshold_on_int_set(const stmdev_ctx_t *ctx, uint8_t val) { lps27hhw_ctrl_reg3_t reg; @@ -2021,7 +2031,7 @@ int32_t lps27hhw_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_fifo_threshold_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhw_ctrl_reg3_t reg; @@ -2041,7 +2051,7 @@ int32_t lps27hhw_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps27hhw_fifo_full_on_int_set(const stmdev_ctx_t *ctx, uint8_t val) { lps27hhw_ctrl_reg3_t reg; int32_t ret; @@ -2065,7 +2075,7 @@ int32_t lps27hhw_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps27hhw_fifo_full_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps27hhw_fifo_full_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps27hhw_ctrl_reg3_t reg; int32_t ret; diff --git a/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.h b/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.h index 0f40f641..c9071b15 100644 --- a/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.h +++ b/sensor/stmemsc/lps27hhw_STdC/driver/lps27hhw_reg.h @@ -311,15 +311,13 @@ typedef struct typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN -uint8_t f_mode : - 3; /* f_mode + trig_modes */ + uint8_t f_mode : 3; /* f_mode + trig_modes */ uint8_t stop_on_wtm : 1; uint8_t not_used_01 : 4; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN uint8_t not_used_01 : 4; uint8_t stop_on_wtm : 1; -uint8_t f_mode : - 3; /* f_mode + trig_modes */ + uint8_t f_mode : 3; /* f_mode + trig_modes */ #endif /* DRV_BYTE_ORDER */ } lps27hhw_fifo_ctrl_t; @@ -451,10 +449,10 @@ typedef union * them with a custom implementation. */ -int32_t lps27hhw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lps27hhw_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lps27hhw_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lps27hhw_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -462,23 +460,23 @@ float_t lps27hhw_from_lsb_to_hpa(int32_t lsb); float_t lps27hhw_from_lsb_to_celsius(int16_t lsb); -int32_t lps27hhw_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps27hhw_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps27hhw_autozero_rst_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps27hhw_autozero_rst_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhw_autozero_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps27hhw_autozero_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps27hhw_autozero_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps27hhw_autozero_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhw_pressure_snap_rst_set(stmdev_ctx_t *ctx, +int32_t lps27hhw_pressure_snap_rst_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lps27hhw_pressure_snap_rst_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_pressure_snap_rst_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhw_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps27hhw_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps27hhw_pressure_snap_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps27hhw_pressure_snap_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhw_block_data_update_set(stmdev_ctx_t *ctx, +int32_t lps27hhw_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lps27hhw_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -498,15 +496,15 @@ typedef enum LPS27HHW_100_Hz = 0x06, LPS27HHW_200_Hz = 0x07, } lps27hhw_odr_t; -int32_t lps27hhw_data_rate_set(stmdev_ctx_t *ctx, lps27hhw_odr_t val); -int32_t lps27hhw_data_rate_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_data_rate_set(const stmdev_ctx_t *ctx, lps27hhw_odr_t val); +int32_t lps27hhw_data_rate_get(const stmdev_ctx_t *ctx, lps27hhw_odr_t *val); -int32_t lps27hhw_pressure_ref_set(stmdev_ctx_t *ctx, int16_t val); -int32_t lps27hhw_pressure_ref_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lps27hhw_pressure_ref_set(const stmdev_ctx_t *ctx, int16_t val); +int32_t lps27hhw_pressure_ref_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lps27hhw_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val); -int32_t lps27hhw_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lps27hhw_pressure_offset_set(const stmdev_ctx_t *ctx, int16_t val); +int32_t lps27hhw_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val); typedef struct { @@ -514,39 +512,39 @@ typedef struct lps27hhw_fifo_status2_t fifo_status2; lps27hhw_status_t status; } lps27hhw_all_sources_t; -int32_t lps27hhw_all_sources_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_all_sources_get(const stmdev_ctx_t *ctx, lps27hhw_all_sources_t *val); -int32_t lps27hhw_status_reg_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_status_reg_get(const stmdev_ctx_t *ctx, lps27hhw_status_t *val); -int32_t lps27hhw_press_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_press_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhw_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhw_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff); +int32_t lps27hhw_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff); -int32_t lps27hhw_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff); -int32_t lps27hhw_fifo_pressure_raw_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_fifo_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff); -int32_t lps27hhw_fifo_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_fifo_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff); -int32_t lps27hhw_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lps27hhw_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lps27hhw_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps27hhw_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps27hhw_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps27hhw_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhw_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps27hhw_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps27hhw_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps27hhw_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhw_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps27hhw_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps27hhw_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps27hhw_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -554,9 +552,9 @@ typedef enum LPS27HHW_LPF_ODR_DIV_9 = 2, LPS27HHW_LPF_ODR_DIV_20 = 3, } lps27hhw_lpfp_cfg_t; -int32_t lps27hhw_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lps27hhw_lp_bandwidth_set(const stmdev_ctx_t *ctx, lps27hhw_lpfp_cfg_t val); -int32_t lps27hhw_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_lp_bandwidth_get(const stmdev_ctx_t *ctx, lps27hhw_lpfp_cfg_t *val); typedef enum @@ -564,9 +562,9 @@ typedef enum LPS27HHW_I2C_ENABLE = 0, LPS27HHW_I2C_DISABLE = 1, } lps27hhw_i2c_disable_t; -int32_t lps27hhw_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lps27hhw_i2c_interface_set(const stmdev_ctx_t *ctx, lps27hhw_i2c_disable_t val); -int32_t lps27hhw_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_i2c_interface_get(const stmdev_ctx_t *ctx, lps27hhw_i2c_disable_t *val); typedef enum @@ -575,9 +573,9 @@ typedef enum LPS27HHW_I3C_ENABLE_INT_PIN_ENABLE = 0x10, LPS27HHW_I3C_DISABLE = 0x11, } lps27hhw_i3c_disable_t; -int32_t lps27hhw_i3c_interface_set(stmdev_ctx_t *ctx, +int32_t lps27hhw_i3c_interface_set(const stmdev_ctx_t *ctx, lps27hhw_i3c_disable_t val); -int32_t lps27hhw_i3c_interface_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_i3c_interface_get(const stmdev_ctx_t *ctx, lps27hhw_i3c_disable_t *val); typedef enum @@ -585,13 +583,13 @@ typedef enum LPS27HHW_PULL_UP_DISCONNECT = 0, LPS27HHW_PULL_UP_CONNECT = 1, } lps27hhw_pu_en_t; -int32_t lps27hhw_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t lps27hhw_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, lps27hhw_pu_en_t val); -int32_t lps27hhw_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, lps27hhw_pu_en_t *val); -int32_t lps27hhw_sda_mode_set(stmdev_ctx_t *ctx, +int32_t lps27hhw_sda_mode_set(const stmdev_ctx_t *ctx, lps27hhw_pu_en_t val); -int32_t lps27hhw_sda_mode_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_sda_mode_get(const stmdev_ctx_t *ctx, lps27hhw_pu_en_t *val); typedef enum @@ -599,17 +597,17 @@ typedef enum LPS27HHW_SPI_4_WIRE = 0, LPS27HHW_SPI_3_WIRE = 1, } lps27hhw_sim_t; -int32_t lps27hhw_spi_mode_set(stmdev_ctx_t *ctx, lps27hhw_sim_t val); -int32_t lps27hhw_spi_mode_get(stmdev_ctx_t *ctx, lps27hhw_sim_t *val); +int32_t lps27hhw_spi_mode_set(const stmdev_ctx_t *ctx, lps27hhw_sim_t val); +int32_t lps27hhw_spi_mode_get(const stmdev_ctx_t *ctx, lps27hhw_sim_t *val); typedef enum { LPS27HHW_INT_PULSED = 0, LPS27HHW_INT_LATCHED = 1, } lps27hhw_lir_t; -int32_t lps27hhw_int_notification_set(stmdev_ctx_t *ctx, +int32_t lps27hhw_int_notification_set(const stmdev_ctx_t *ctx, lps27hhw_lir_t val); -int32_t lps27hhw_int_notification_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_int_notification_get(const stmdev_ctx_t *ctx, lps27hhw_lir_t *val); typedef enum @@ -617,9 +615,9 @@ typedef enum LPS27HHW_PUSH_PULL = 0, LPS27HHW_OPEN_DRAIN = 1, } lps27hhw_pp_od_t; -int32_t lps27hhw_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lps27hhw_pin_mode_set(const stmdev_ctx_t *ctx, lps27hhw_pp_od_t val); -int32_t lps27hhw_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_pin_mode_get(const stmdev_ctx_t *ctx, lps27hhw_pp_od_t *val); typedef enum @@ -627,14 +625,14 @@ typedef enum LPS27HHW_ACTIVE_HIGH = 0, LPS27HHW_ACTIVE_LOW = 1, } lps27hhw_int_h_l_t; -int32_t lps27hhw_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lps27hhw_pin_polarity_set(const stmdev_ctx_t *ctx, lps27hhw_int_h_l_t val); -int32_t lps27hhw_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_pin_polarity_get(const stmdev_ctx_t *ctx, lps27hhw_int_h_l_t *val); -int32_t lps27hhw_pin_int_route_set(stmdev_ctx_t *ctx, +int32_t lps27hhw_pin_int_route_set(const stmdev_ctx_t *ctx, lps27hhw_ctrl_reg3_t *val); -int32_t lps27hhw_pin_int_route_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_pin_int_route_get(const stmdev_ctx_t *ctx, lps27hhw_ctrl_reg3_t *val); typedef enum @@ -644,13 +642,13 @@ typedef enum LPS27HHW_NEGATIVE = 2, LPS27HHW_BOTH = 3, } lps27hhw_pe_t; -int32_t lps27hhw_int_on_threshold_set(stmdev_ctx_t *ctx, +int32_t lps27hhw_int_on_threshold_set(const stmdev_ctx_t *ctx, lps27hhw_pe_t val); -int32_t lps27hhw_int_on_threshold_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_int_on_threshold_get(const stmdev_ctx_t *ctx, lps27hhw_pe_t *val); -int32_t lps27hhw_int_treshold_set(stmdev_ctx_t *ctx, uint16_t buff); -int32_t lps27hhw_int_treshold_get(stmdev_ctx_t *ctx, uint16_t *buff); +int32_t lps27hhw_int_threshold_set(const stmdev_ctx_t *ctx, uint16_t buff); +int32_t lps27hhw_int_threshold_get(const stmdev_ctx_t *ctx, uint16_t *buff); typedef enum { @@ -662,40 +660,40 @@ typedef enum LPS27HHW_BYPASS_TO_STREAM_MODE = 6, LPS27HHW_STREAM_TO_FIFO_MODE = 7, } lps27hhw_f_mode_t; -int32_t lps27hhw_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lps27hhw_fifo_mode_set(const stmdev_ctx_t *ctx, lps27hhw_f_mode_t val); -int32_t lps27hhw_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_fifo_mode_get(const stmdev_ctx_t *ctx, lps27hhw_f_mode_t *val); -int32_t lps27hhw_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps27hhw_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps27hhw_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhw_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps27hhw_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps27hhw_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps27hhw_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhw_fifo_data_level_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lps27hhw_fifo_src_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_fifo_src_get(const stmdev_ctx_t *ctx, lps27hhw_fifo_status2_t *val); -int32_t lps27hhw_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps27hhw_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhw_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps27hhw_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhw_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps27hhw_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhw_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps27hhw_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps27hhw_fifo_ovr_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps27hhw_fifo_ovr_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhw_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, +int32_t lps27hhw_fifo_threshold_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lps27hhw_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_fifo_threshold_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps27hhw_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps27hhw_fifo_full_on_int_get(stmdev_ctx_t *ctx, +int32_t lps27hhw_fifo_full_on_int_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps27hhw_fifo_full_on_int_get(const stmdev_ctx_t *ctx, uint8_t *val); /** diff --git a/sensor/stmemsc/lps28dfw_STdC/driver/lps28dfw_reg.c b/sensor/stmemsc/lps28dfw_STdC/driver/lps28dfw_reg.c index 67031c60..b35b71f7 100644 --- a/sensor/stmemsc/lps28dfw_STdC/driver/lps28dfw_reg.c +++ b/sensor/stmemsc/lps28dfw_STdC/driver/lps28dfw_reg.c @@ -46,11 +46,18 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lps28dfw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, +int32_t __weak lps28dfw_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); + return ret; } @@ -64,11 +71,18 @@ int32_t __weak lps28dfw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lps28dfw_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, +int32_t __weak lps28dfw_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); + return ret; } @@ -140,7 +154,7 @@ float_t lps28dfw_from_lsb_to_celsius(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_id_get(stmdev_ctx_t *ctx, lps28dfw_id_t *val) +int32_t lps28dfw_id_get(const stmdev_ctx_t *ctx, lps28dfw_id_t *val) { uint8_t reg; int32_t ret; @@ -159,7 +173,7 @@ int32_t lps28dfw_id_get(stmdev_ctx_t *ctx, lps28dfw_id_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_bus_mode_set(stmdev_ctx_t *ctx, lps28dfw_bus_mode_t *val) +int32_t lps28dfw_bus_mode_set(const stmdev_ctx_t *ctx, lps28dfw_bus_mode_t *val) { lps28dfw_i3c_if_ctrl_add_t i3c_if_ctrl_add; lps28dfw_if_ctrl_t if_ctrl; @@ -194,7 +208,7 @@ int32_t lps28dfw_bus_mode_set(stmdev_ctx_t *ctx, lps28dfw_bus_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_bus_mode_get(stmdev_ctx_t *ctx, lps28dfw_bus_mode_t *val) +int32_t lps28dfw_bus_mode_get(const stmdev_ctx_t *ctx, lps28dfw_bus_mode_t *val) { lps28dfw_i3c_if_ctrl_add_t i3c_if_ctrl_add; lps28dfw_if_ctrl_t if_ctrl; @@ -262,7 +276,7 @@ int32_t lps28dfw_bus_mode_get(stmdev_ctx_t *ctx, lps28dfw_bus_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_init_set(stmdev_ctx_t *ctx, lps28dfw_init_t val) +int32_t lps28dfw_init_set(const stmdev_ctx_t *ctx, lps28dfw_init_t val) { lps28dfw_ctrl_reg2_t ctrl_reg2; lps28dfw_ctrl_reg3_t ctrl_reg3; @@ -312,7 +326,7 @@ int32_t lps28dfw_init_set(stmdev_ctx_t *ctx, lps28dfw_init_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_status_get(stmdev_ctx_t *ctx, lps28dfw_stat_t *val) +int32_t lps28dfw_status_get(const stmdev_ctx_t *ctx, lps28dfw_stat_t *val) { lps28dfw_interrupt_cfg_t interrupt_cfg; lps28dfw_int_source_t int_source; @@ -355,7 +369,7 @@ int32_t lps28dfw_status_get(stmdev_ctx_t *ctx, lps28dfw_stat_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_pin_conf_set(stmdev_ctx_t *ctx, lps28dfw_pin_conf_t *val) +int32_t lps28dfw_pin_conf_set(const stmdev_ctx_t *ctx, lps28dfw_pin_conf_t *val) { lps28dfw_ctrl_reg3_t ctrl_reg3; lps28dfw_if_ctrl_t if_ctrl; @@ -390,7 +404,7 @@ int32_t lps28dfw_pin_conf_set(stmdev_ctx_t *ctx, lps28dfw_pin_conf_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_pin_conf_get(stmdev_ctx_t *ctx, lps28dfw_pin_conf_t *val) +int32_t lps28dfw_pin_conf_get(const stmdev_ctx_t *ctx, lps28dfw_pin_conf_t *val) { lps28dfw_ctrl_reg3_t ctrl_reg3; lps28dfw_if_ctrl_t if_ctrl; @@ -417,7 +431,7 @@ int32_t lps28dfw_pin_conf_get(stmdev_ctx_t *ctx, lps28dfw_pin_conf_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_all_sources_get(stmdev_ctx_t *ctx, +int32_t lps28dfw_all_sources_get(const stmdev_ctx_t *ctx, lps28dfw_all_sources_t *val) { lps28dfw_fifo_status2_t fifo_status2; @@ -458,7 +472,7 @@ int32_t lps28dfw_all_sources_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_mode_set(stmdev_ctx_t *ctx, lps28dfw_md_t *val) +int32_t lps28dfw_mode_set(const stmdev_ctx_t *ctx, lps28dfw_md_t *val) { lps28dfw_ctrl_reg1_t ctrl_reg1; lps28dfw_ctrl_reg2_t ctrl_reg2; @@ -494,7 +508,7 @@ int32_t lps28dfw_mode_set(stmdev_ctx_t *ctx, lps28dfw_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_mode_get(stmdev_ctx_t *ctx, lps28dfw_md_t *val) +int32_t lps28dfw_mode_get(const stmdev_ctx_t *ctx, lps28dfw_md_t *val) { lps28dfw_ctrl_reg1_t ctrl_reg1; lps28dfw_ctrl_reg2_t ctrl_reg2; @@ -613,7 +627,7 @@ int32_t lps28dfw_mode_get(stmdev_ctx_t *ctx, lps28dfw_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_trigger_sw(stmdev_ctx_t *ctx, lps28dfw_md_t *md) +int32_t lps28dfw_trigger_sw(const stmdev_ctx_t *ctx, lps28dfw_md_t *md) { lps28dfw_ctrl_reg2_t ctrl_reg2; int32_t ret = 0; @@ -639,7 +653,7 @@ int32_t lps28dfw_trigger_sw(stmdev_ctx_t *ctx, lps28dfw_md_t *md) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_data_get(stmdev_ctx_t *ctx, lps28dfw_md_t *md, +int32_t lps28dfw_data_get(const stmdev_ctx_t *ctx, lps28dfw_md_t *md, lps28dfw_data_t *data) { uint8_t buff[5]; @@ -674,6 +688,48 @@ int32_t lps28dfw_data_get(stmdev_ctx_t *ctx, lps28dfw_md_t *md, return ret; } +/** + * @brief Pressure output value.[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lps28dfw_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff) +{ + int32_t ret; + uint8_t reg[3]; + + ret = lps28dfw_read_reg(ctx, LPS28DFW_PRESS_OUT_XL, reg, 3); + *buff = reg[2]; + *buff = (*buff * 256U) + reg[1]; + *buff = (*buff * 256U) + reg[0]; + *buff *= 256U; + + return ret; +} + +/** + * @brief Temperature output value.[get] + * + * @param ctx read / write interface definitions + * @param buff buffer that stores data read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lps28dfw_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) +{ + int32_t ret; + uint8_t reg[2]; + + ret = lps28dfw_read_reg(ctx, LPS28DFW_TEMP_OUT_L, reg, 2); + *buff = (int16_t)reg[1]; + *buff = (*buff * 256) + (int16_t)reg[0]; + + return ret; +} + /** * @} * @@ -695,7 +751,7 @@ int32_t lps28dfw_data_get(stmdev_ctx_t *ctx, lps28dfw_md_t *md, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_fifo_mode_set(stmdev_ctx_t *ctx, lps28dfw_fifo_md_t *val) +int32_t lps28dfw_fifo_mode_set(const stmdev_ctx_t *ctx, lps28dfw_fifo_md_t *val) { lps28dfw_fifo_ctrl_t fifo_ctrl; lps28dfw_fifo_wtm_t fifo_wtm; @@ -738,7 +794,7 @@ int32_t lps28dfw_fifo_mode_set(stmdev_ctx_t *ctx, lps28dfw_fifo_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_fifo_mode_get(stmdev_ctx_t *ctx, lps28dfw_fifo_md_t *val) +int32_t lps28dfw_fifo_mode_get(const stmdev_ctx_t *ctx, lps28dfw_fifo_md_t *val) { lps28dfw_fifo_ctrl_t fifo_ctrl; lps28dfw_fifo_wtm_t fifo_wtm; @@ -789,7 +845,7 @@ int32_t lps28dfw_fifo_mode_get(stmdev_ctx_t *ctx, lps28dfw_fifo_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_fifo_level_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps28dfw_fifo_level_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps28dfw_fifo_status1_t fifo_status1; int32_t ret; @@ -813,7 +869,7 @@ int32_t lps28dfw_fifo_level_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_fifo_data_get(stmdev_ctx_t *ctx, uint8_t samp, +int32_t lps28dfw_fifo_data_get(const stmdev_ctx_t *ctx, uint8_t samp, lps28dfw_md_t *md, lps28dfw_fifo_data_t *data) { uint8_t fifo_data[3]; @@ -867,7 +923,7 @@ int32_t lps28dfw_fifo_data_get(stmdev_ctx_t *ctx, uint8_t samp, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_interrupt_mode_set(stmdev_ctx_t *ctx, +int32_t lps28dfw_interrupt_mode_set(const stmdev_ctx_t *ctx, lps28dfw_int_mode_t *val) { lps28dfw_interrupt_cfg_t interrupt_cfg; @@ -912,7 +968,7 @@ int32_t lps28dfw_interrupt_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_interrupt_mode_get(stmdev_ctx_t *ctx, +int32_t lps28dfw_interrupt_mode_get(const stmdev_ctx_t *ctx, lps28dfw_int_mode_t *val) { lps28dfw_interrupt_cfg_t interrupt_cfg; @@ -946,7 +1002,7 @@ int32_t lps28dfw_interrupt_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_pin_int_route_set(stmdev_ctx_t *ctx, +int32_t lps28dfw_pin_int_route_set(const stmdev_ctx_t *ctx, lps28dfw_pin_int_route_t *val) { lps28dfw_ctrl_reg4_t ctrl_reg4; @@ -982,7 +1038,7 @@ int32_t lps28dfw_pin_int_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_pin_int_route_get(stmdev_ctx_t *ctx, +int32_t lps28dfw_pin_int_route_get(const stmdev_ctx_t *ctx, lps28dfw_pin_int_route_t *val) { lps28dfw_ctrl_reg4_t ctrl_reg4; @@ -1020,7 +1076,7 @@ int32_t lps28dfw_pin_int_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_int_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t lps28dfw_int_on_threshold_mode_set(const stmdev_ctx_t *ctx, lps28dfw_int_th_md_t *val) { lps28dfw_interrupt_cfg_t interrupt_cfg; @@ -1058,7 +1114,7 @@ int32_t lps28dfw_int_on_threshold_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_int_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t lps28dfw_int_on_threshold_mode_get(const stmdev_ctx_t *ctx, lps28dfw_int_th_md_t *val) { lps28dfw_interrupt_cfg_t interrupt_cfg; @@ -1102,7 +1158,7 @@ int32_t lps28dfw_int_on_threshold_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_reference_mode_set(stmdev_ctx_t *ctx, lps28dfw_ref_md_t *val) +int32_t lps28dfw_reference_mode_set(const stmdev_ctx_t *ctx, lps28dfw_ref_md_t *val) { lps28dfw_interrupt_cfg_t interrupt_cfg; int32_t ret; @@ -1119,7 +1175,7 @@ int32_t lps28dfw_reference_mode_set(stmdev_ctx_t *ctx, lps28dfw_ref_md_t *val) interrupt_cfg.reset_arp = ((uint8_t)val->apply_ref & 0x02U) >> 1; ret = lps28dfw_write_reg(ctx, LPS28DFW_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); + (uint8_t *)&interrupt_cfg, 1); } return ret; } @@ -1132,7 +1188,7 @@ int32_t lps28dfw_reference_mode_set(stmdev_ctx_t *ctx, lps28dfw_ref_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_reference_mode_get(stmdev_ctx_t *ctx, lps28dfw_ref_md_t *val) +int32_t lps28dfw_reference_mode_get(const stmdev_ctx_t *ctx, lps28dfw_ref_md_t *val) { lps28dfw_interrupt_cfg_t interrupt_cfg; int32_t ret; @@ -1166,7 +1222,7 @@ int32_t lps28dfw_reference_mode_get(stmdev_ctx_t *ctx, lps28dfw_ref_md_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_refp_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lps28dfw_refp_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t reg[2]; int32_t ret; @@ -1187,7 +1243,7 @@ int32_t lps28dfw_refp_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_opc_set(stmdev_ctx_t *ctx, int16_t val) +int32_t lps28dfw_opc_set(const stmdev_ctx_t *ctx, int16_t val) { uint8_t reg[2]; int32_t ret; @@ -1208,7 +1264,7 @@ int32_t lps28dfw_opc_set(stmdev_ctx_t *ctx, int16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lps28dfw_opc_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lps28dfw_opc_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t reg[2]; int32_t ret; diff --git a/sensor/stmemsc/lps28dfw_STdC/driver/lps28dfw_reg.h b/sensor/stmemsc/lps28dfw_STdC/driver/lps28dfw_reg.h index f38348a9..69899e21 100644 --- a/sensor/stmemsc/lps28dfw_STdC/driver/lps28dfw_reg.h +++ b/sensor/stmemsc/lps28dfw_STdC/driver/lps28dfw_reg.h @@ -499,9 +499,9 @@ typedef union * them with a custom implementation. */ -int32_t lps28dfw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lps28dfw_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lps28dfw_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lps28dfw_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); extern float_t lps28dfw_from_fs1260_to_hPa(int32_t lsb); @@ -513,30 +513,36 @@ typedef struct { uint8_t whoami; } lps28dfw_id_t; -int32_t lps28dfw_id_get(stmdev_ctx_t *ctx, lps28dfw_id_t *val); +int32_t lps28dfw_id_get(const stmdev_ctx_t *ctx, lps28dfw_id_t *val); + +typedef enum +{ + LPS28DFW_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */ + LPS28DFW_INT_PIN_ON_I3C = 0x04, /* INT pin polarized as OUT with I3C */ +} lps28dfw_interface_t; + +typedef enum +{ + LPS28DFW_AUTO = 0x00, /* bus mode select by HW (SPI 3W disable) */ + LPS28DFW_ALWAYS_ON = 0x01, /* Only SPI: SDO / SDI separated pins */ +} lps28dfw_filter_t; + +typedef enum +{ + LPS28DFW_BUS_AVB_TIME_50us = 0x00, /* bus available time equal to 50 us */ + LPS28DFW_BUS_AVB_TIME_2us = 0x01, /* bus available time equal to 2 us */ + LPS28DFW_BUS_AVB_TIME_1ms = 0x02, /* bus available time equal to 1 ms */ + LPS28DFW_BUS_AVB_TIME_25ms = 0x03, /* bus available time equal to 25 ms */ +} lps28dfw_bus_avb_time_t; typedef struct { - enum - { - LPS28DFW_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */ - LPS28DFW_INT_PIN_ON_I3C = 0x04, /* INT pin polarized as OUT with I3C */ - } interface; - enum - { - LPS28DFW_AUTO = 0x00, /* bus mode select by HW (SPI 3W disable) */ - LPS28DFW_ALWAYS_ON = 0x01, /* Only SPI: SDO / SDI separated pins */ - } filter; - enum - { - LPS28DFW_BUS_AVB_TIME_50us = 0x00, /* bus available time equal to 50 us */ - LPS28DFW_BUS_AVB_TIME_2us = 0x01, /* bus available time equal to 2 us */ - LPS28DFW_BUS_AVB_TIME_1ms = 0x02, /* bus available time equal to 1 ms */ - LPS28DFW_BUS_AVB_TIME_25ms = 0x03, /* bus available time equal to 25 ms */ - } bus_avb_time; + lps28dfw_interface_t interface; + lps28dfw_filter_t filter; + lps28dfw_bus_avb_time_t bus_avb_time; } lps28dfw_bus_mode_t; -int32_t lps28dfw_bus_mode_set(stmdev_ctx_t *ctx, lps28dfw_bus_mode_t *val); -int32_t lps28dfw_bus_mode_get(stmdev_ctx_t *ctx, lps28dfw_bus_mode_t *val); +int32_t lps28dfw_bus_mode_set(const stmdev_ctx_t *ctx, lps28dfw_bus_mode_t *val); +int32_t lps28dfw_bus_mode_get(const stmdev_ctx_t *ctx, lps28dfw_bus_mode_t *val); typedef enum { @@ -544,7 +550,7 @@ typedef enum LPS28DFW_BOOT = 0x01, /* Restore calib. param. ( it takes 10ms ) */ LPS28DFW_RESET = 0x02, /* Reset configuration registers */ } lps28dfw_init_t; -int32_t lps28dfw_init_set(stmdev_ctx_t *ctx, lps28dfw_init_t val); +int32_t lps28dfw_init_set(const stmdev_ctx_t *ctx, lps28dfw_init_t val); typedef struct { @@ -557,7 +563,7 @@ typedef struct uint8_t end_meas : 1; /* Single measurement is finished. */ uint8_t ref_done : 1; /* Auto-Zero value is set. */ } lps28dfw_stat_t; -int32_t lps28dfw_status_get(stmdev_ctx_t *ctx, lps28dfw_stat_t *val); +int32_t lps28dfw_status_get(const stmdev_ctx_t *ctx, lps28dfw_stat_t *val); typedef struct { @@ -565,8 +571,8 @@ typedef struct uint8_t int_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */ uint8_t sda_pull_up : 1; /* 1 = pull-up always disabled */ } lps28dfw_pin_conf_t; -int32_t lps28dfw_pin_conf_set(stmdev_ctx_t *ctx, lps28dfw_pin_conf_t *val); -int32_t lps28dfw_pin_conf_get(stmdev_ctx_t *ctx, lps28dfw_pin_conf_t *val); +int32_t lps28dfw_pin_conf_set(const stmdev_ctx_t *ctx, lps28dfw_pin_conf_t *val); +int32_t lps28dfw_pin_conf_get(const stmdev_ctx_t *ctx, lps28dfw_pin_conf_t *val); typedef struct { @@ -579,50 +585,58 @@ typedef struct uint8_t fifo_ovr : 1; /* FIFO overrun */ uint8_t fifo_th : 1; /* FIFO threshold reached */ } lps28dfw_all_sources_t; -int32_t lps28dfw_all_sources_get(stmdev_ctx_t *ctx, +int32_t lps28dfw_all_sources_get(const stmdev_ctx_t *ctx, lps28dfw_all_sources_t *val); +typedef enum +{ + LPS28DFW_1260hPa = 0x00, + LPS28DFW_4000hPa = 0x01, +} lps28dfw_fs_t; + +typedef enum +{ + LPS28DFW_ONE_SHOT = 0x00, /* Device in power down till software trigger */ + LPS28DFW_1Hz = 0x01, + LPS28DFW_4Hz = 0x02, + LPS28DFW_10Hz = 0x03, + LPS28DFW_25Hz = 0x04, + LPS28DFW_50Hz = 0x05, + LPS28DFW_75Hz = 0x06, + LPS28DFW_100Hz = 0x07, + LPS28DFW_200Hz = 0x08, +} lps28dfw_odr_t; + +typedef enum +{ + LPS28DFW_4_AVG = 0, + LPS28DFW_8_AVG = 1, + LPS28DFW_16_AVG = 2, + LPS28DFW_32_AVG = 3, + LPS28DFW_64_AVG = 4, + LPS28DFW_128_AVG = 5, + LPS28DFW_256_AVG = 6, + LPS28DFW_512_AVG = 7, +} lps28dfw_avg_t; + +typedef enum +{ + LPS28DFW_LPF_DISABLE = 0, + LPS28DFW_LPF_ODR_DIV_4 = 1, + LPS28DFW_LPF_ODR_DIV_9 = 3, +} lps28dfw_lpf_t; + typedef struct { - enum - { - LPS28DFW_1260hPa = 0x00, - LPS28DFW_4000hPa = 0x01, - } fs; - enum - { - LPS28DFW_ONE_SHOT = 0x00, /* Device in power down till software trigger */ - LPS28DFW_1Hz = 0x01, - LPS28DFW_4Hz = 0x02, - LPS28DFW_10Hz = 0x03, - LPS28DFW_25Hz = 0x04, - LPS28DFW_50Hz = 0x05, - LPS28DFW_75Hz = 0x06, - LPS28DFW_100Hz = 0x07, - LPS28DFW_200Hz = 0x08, - } odr; - enum - { - LPS28DFW_4_AVG = 0, - LPS28DFW_8_AVG = 1, - LPS28DFW_16_AVG = 2, - LPS28DFW_32_AVG = 3, - LPS28DFW_64_AVG = 4, - LPS28DFW_128_AVG = 5, - LPS28DFW_256_AVG = 6, - LPS28DFW_512_AVG = 7, - } avg; - enum - { - LPS28DFW_LPF_DISABLE = 0, - LPS28DFW_LPF_ODR_DIV_4 = 1, - LPS28DFW_LPF_ODR_DIV_9 = 3, - } lpf; + lps28dfw_fs_t fs; + lps28dfw_odr_t odr; + lps28dfw_avg_t avg; + lps28dfw_lpf_t lpf; } lps28dfw_md_t; -int32_t lps28dfw_mode_set(stmdev_ctx_t *ctx, lps28dfw_md_t *val); -int32_t lps28dfw_mode_get(stmdev_ctx_t *ctx, lps28dfw_md_t *val); +int32_t lps28dfw_mode_set(const stmdev_ctx_t *ctx, lps28dfw_md_t *val); +int32_t lps28dfw_mode_get(const stmdev_ctx_t *ctx, lps28dfw_md_t *val); -int32_t lps28dfw_trigger_sw(stmdev_ctx_t *ctx, lps28dfw_md_t *md); +int32_t lps28dfw_trigger_sw(const stmdev_ctx_t *ctx, lps28dfw_md_t *md); typedef struct { @@ -637,33 +651,38 @@ typedef struct int16_t raw; } heat; } lps28dfw_data_t; -int32_t lps28dfw_data_get(stmdev_ctx_t *ctx, lps28dfw_md_t *md, +int32_t lps28dfw_data_get(const stmdev_ctx_t *ctx, lps28dfw_md_t *md, lps28dfw_data_t *data); +int32_t lps28dfw_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff); +int32_t lps28dfw_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff); + +typedef enum +{ + LPS28DFW_BYPASS = 0, + LPS28DFW_FIFO = 1, + LPS28DFW_STREAM = 2, + LPS28DFW_STREAM_TO_FIFO = 7, /* Dynamic-Stream, FIFO on Trigger */ + LPS28DFW_BYPASS_TO_STREAM = 6, /* Bypass, Dynamic-Stream on Trigger */ + LPS28DFW_BYPASS_TO_FIFO = 5, /* Bypass, FIFO on Trigger */ +} lps28dfw_operation_t; + typedef struct { - enum - { - LPS28DFW_BYPASS = 0, - LPS28DFW_FIFO = 1, - LPS28DFW_STREAM = 2, - LPS28DFW_STREAM_TO_FIFO = 7, /* Dynamic-Stream, FIFO on Trigger */ - LPS28DFW_BYPASS_TO_STREAM = 6, /* Bypass, Dynamic-Stream on Trigger */ - LPS28DFW_BYPASS_TO_FIFO = 5, /* Bypass, FIFO on Trigger */ - } operation; + lps28dfw_operation_t operation; uint8_t watermark; /* (0 disable) max 128.*/ } lps28dfw_fifo_md_t; -int32_t lps28dfw_fifo_mode_set(stmdev_ctx_t *ctx, lps28dfw_fifo_md_t *val); -int32_t lps28dfw_fifo_mode_get(stmdev_ctx_t *ctx, lps28dfw_fifo_md_t *val); +int32_t lps28dfw_fifo_mode_set(const stmdev_ctx_t *ctx, lps28dfw_fifo_md_t *val); +int32_t lps28dfw_fifo_mode_get(const stmdev_ctx_t *ctx, lps28dfw_fifo_md_t *val); -int32_t lps28dfw_fifo_level_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps28dfw_fifo_level_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { float_t hpa; int32_t raw; } lps28dfw_fifo_data_t; -int32_t lps28dfw_fifo_data_get(stmdev_ctx_t *ctx, uint8_t samp, +int32_t lps28dfw_fifo_data_get(const stmdev_ctx_t *ctx, uint8_t samp, lps28dfw_md_t *md, lps28dfw_fifo_data_t *data); typedef struct @@ -672,9 +691,9 @@ typedef struct uint8_t active_low : 1; /* 1 = active low / 0 = active high */ uint8_t drdy_latched : 1; /* pulsed ~5 μs with enabled drdy_pres " */ } lps28dfw_int_mode_t; -int32_t lps28dfw_interrupt_mode_set(stmdev_ctx_t *ctx, +int32_t lps28dfw_interrupt_mode_set(const stmdev_ctx_t *ctx, lps28dfw_int_mode_t *val); -int32_t lps28dfw_interrupt_mode_get(stmdev_ctx_t *ctx, +int32_t lps28dfw_interrupt_mode_get(const stmdev_ctx_t *ctx, lps28dfw_int_mode_t *val); typedef struct @@ -684,9 +703,9 @@ typedef struct uint8_t fifo_ovr : 1; /* FIFO overrun */ uint8_t fifo_full : 1; /* FIFO full */ } lps28dfw_pin_int_route_t; -int32_t lps28dfw_pin_int_route_set(stmdev_ctx_t *ctx, +int32_t lps28dfw_pin_int_route_set(const stmdev_ctx_t *ctx, lps28dfw_pin_int_route_t *val); -int32_t lps28dfw_pin_int_route_get(stmdev_ctx_t *ctx, +int32_t lps28dfw_pin_int_route_get(const stmdev_ctx_t *ctx, lps28dfw_pin_int_route_t *val); typedef struct @@ -697,30 +716,32 @@ typedef struct uint8_t over_th : 1; /* Pressure data over threshold event */ uint8_t under_th : 1; /* Pressure data under threshold event */ } lps28dfw_int_th_md_t; -int32_t lps28dfw_int_on_threshold_mode_set(stmdev_ctx_t *ctx, +int32_t lps28dfw_int_on_threshold_mode_set(const stmdev_ctx_t *ctx, lps28dfw_int_th_md_t *val); -int32_t lps28dfw_int_on_threshold_mode_get(stmdev_ctx_t *ctx, +int32_t lps28dfw_int_on_threshold_mode_get(const stmdev_ctx_t *ctx, lps28dfw_int_th_md_t *val); +typedef enum +{ + LPS28DFW_OUT_AND_INTERRUPT = 0, + LPS28DFW_ONLY_INTERRUPT = 1, + LPS28DFW_RST_REFS = 2, +} lps28dfw_apply_ref_t; + typedef struct { - enum - { - LPS28DFW_OUT_AND_INTERRUPT = 0, - LPS28DFW_ONLY_INTERRUPT = 1, - LPS28DFW_RST_REFS = 2, - } apply_ref; + lps28dfw_apply_ref_t apply_ref; uint8_t get_ref : 1; /* Use current pressure value as reference */ } lps28dfw_ref_md_t; -int32_t lps28dfw_reference_mode_set(stmdev_ctx_t *ctx, +int32_t lps28dfw_reference_mode_set(const stmdev_ctx_t *ctx, lps28dfw_ref_md_t *val); -int32_t lps28dfw_reference_mode_get(stmdev_ctx_t *ctx, +int32_t lps28dfw_reference_mode_get(const stmdev_ctx_t *ctx, lps28dfw_ref_md_t *val); -int32_t lps28dfw_refp_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lps28dfw_refp_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lps28dfw_opc_set(stmdev_ctx_t *ctx, int16_t val); -int32_t lps28dfw_opc_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lps28dfw_opc_set(const stmdev_ctx_t *ctx, int16_t val); +int32_t lps28dfw_opc_get(const stmdev_ctx_t *ctx, int16_t *val); /** *@} diff --git a/sensor/stmemsc/lps33hw_STdC/driver/lps33hw_reg.c b/sensor/stmemsc/lps33hw_STdC/driver/lps33hw_reg.c deleted file mode 100644 index 820dab4a..00000000 --- a/sensor/stmemsc/lps33hw_STdC/driver/lps33hw_reg.c +++ /dev/null @@ -1,2079 +0,0 @@ -/** - ****************************************************************************** - * @file lps33hw_reg.c - * @author Sensors Software Solution Team - * @brief LPS33HW driver file - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -#include "lps33hw_reg.h" - -/** - * @defgroup LPS33HW - * @brief This file provides a set of functions needed to drive the - * ultra-compact piezoresistive absolute pressure sensor. - * @{ - * - */ - -/** - * @defgroup LPS33HW_Interfaces_functions - * @brief This section provide a set of functions used to read and - * write a generic register of the device. - * @{ - * - */ - -/** - * @brief Read generic device register - * - * @param ctx read / write interface definitions(ptr) - * @param reg register to read - * @param data pointer to buffer that store the data read(ptr) - * @param len number of consecutive register to read - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t __weak lps33hw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) -{ - int32_t ret; - - ret = ctx->read_reg(ctx->handle, reg, data, len); - - return ret; -} - -/** - * @brief Write generic device register - * - * @param ctx read / write interface definitions(ptr) - * @param reg register to write - * @param data pointer to data to write in register reg(ptr) - * @param len number of consecutive register to write - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t __weak lps33hw_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) -{ - int32_t ret; - - ret = ctx->write_reg(ctx->handle, reg, data, len); - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LPS33HW_Sensitivity - * @brief These functions convert raw-data into engineering units. - * @{ - * - */ - -float_t lps33hw_from_lsb_to_hpa(int32_t lsb) -{ - return ((float_t)lsb / 4096.0f); -} - -float_t lps33hw_from_lsb_to_degc(int16_t lsb) -{ - return ((float_t)lsb / 100.0f); -} - -/** - * @} - * - */ - -/** - * @defgroup LPS33HW_data_generation_c - * @brief This section group all the functions concerning data - * generation - * @{ - * - */ - - -/** - * @brief Reset Autozero function.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of reset_az in reg INTERRUPT_CFG - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ - -int32_t lps33hw_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33hw_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - - if (ret == 0) - { - interrupt_cfg.reset_az = val; - ret = lps33hw_write_reg(ctx, LPS33HW_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - } - - return ret; -} - -/** - * @brief Reset Autozero function.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of reset_az in reg INTERRUPT_CFG - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33hw_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - *val = interrupt_cfg.reset_az; - - return ret; -} - -/** - * @brief Enable Autozero function.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of autozero in reg INTERRUPT_CFG - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_autozero_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33hw_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - - if (ret == 0) - { - interrupt_cfg.autozero = val; - ret = lps33hw_write_reg(ctx, LPS33HW_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - } - - return ret; -} - -/** - * @brief Enable Autozero function.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of autozero in reg INTERRUPT_CFG - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_autozero_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33hw_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - *val = interrupt_cfg.autozero; - - return ret; -} - -/** - * @brief Reset AutoRifP function.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of reset_arp in reg INTERRUPT_CFG - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_pressure_snap_rst_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33hw_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - - if (ret == 0) - { - interrupt_cfg.reset_arp = val; - ret = lps33hw_write_reg(ctx, LPS33HW_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - } - - return ret; -} - -/** - * @brief Reset AutoRifP function.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of reset_arp in reg INTERRUPT_CFG - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_pressure_snap_rst_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33hw_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - *val = interrupt_cfg.reset_arp; - - return ret; -} - -/** - * @brief Enable AutoRifP function.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of autorifp in reg INTERRUPT_CFG. - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33hw_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - - if (ret == 0) - { - interrupt_cfg.autorifp = val; - ret = lps33hw_write_reg(ctx, LPS33HW_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - } - - return ret; -} - -/** - * @brief Enable AutoRifP function.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of autorifp in reg INTERRUPT_CFG - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33hw_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - *val = interrupt_cfg.autorifp; - - return ret; -} - -/** - * @brief Block data update.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of bdu in reg CTRL_REG1 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33hw_ctrl_reg1_t ctrl_reg1; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - - if (ret == 0) - { - ctrl_reg1.bdu = val; - ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - } - - return ret; -} - -/** - * @brief Block data update.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of bdu in reg CTRL_REG1 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33hw_ctrl_reg1_t ctrl_reg1; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - *val = ctrl_reg1.bdu; - - return ret; -} - -/** - * @brief Low-pass bandwidth selection.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of lpfp in reg CTRL_REG1 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_low_pass_filter_mode_set(stmdev_ctx_t *ctx, - lps33hw_lpfp_t val) -{ - lps33hw_ctrl_reg1_t ctrl_reg1; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - - if (ret == 0) - { - ctrl_reg1.lpfp = (uint8_t)val; - ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - } - - return ret; -} - -/** - * @brief Low-pass bandwidth selection.[get] - * - * @param ctx Read / write interface definitions - * @param val Get the values of lpfp in reg CTRL_REG1 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_low_pass_filter_mode_get(stmdev_ctx_t *ctx, - lps33hw_lpfp_t *val) -{ - lps33hw_ctrl_reg1_t ctrl_reg1; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - - switch (ctrl_reg1.lpfp) - { - case LPS33HW_LPF_ODR_DIV_2: - *val = LPS33HW_LPF_ODR_DIV_2; - break; - - case LPS33HW_LPF_ODR_DIV_9: - *val = LPS33HW_LPF_ODR_DIV_9; - break; - - case LPS33HW_LPF_ODR_DIV_20: - *val = LPS33HW_LPF_ODR_DIV_20; - break; - - default: - *val = LPS33HW_LPF_ODR_DIV_2; - break; - } - - return ret; -} - -/** - * @brief Output data rate selection.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of odr in reg CTRL_REG1 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_data_rate_set(stmdev_ctx_t *ctx, lps33hw_odr_t val) -{ - lps33hw_ctrl_reg1_t ctrl_reg1; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - - if (ret == 0) - { - ctrl_reg1.odr = (uint8_t)val; - ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - } - - return ret; -} - -/** - * @brief Output data rate selection.[get] - * - * @param ctx Read / write interface definitions - * @param val Get the values of odr in reg CTRL_REG1 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_data_rate_get(stmdev_ctx_t *ctx, lps33hw_odr_t *val) -{ - lps33hw_ctrl_reg1_t ctrl_reg1; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - - switch (ctrl_reg1.odr) - { - case LPS33HW_POWER_DOWN: - *val = LPS33HW_POWER_DOWN; - break; - - case LPS33HW_ODR_1_Hz: - *val = LPS33HW_ODR_1_Hz; - break; - - case LPS33HW_ODR_10_Hz: - *val = LPS33HW_ODR_10_Hz; - break; - - case LPS33HW_ODR_25_Hz: - *val = LPS33HW_ODR_25_Hz; - break; - - case LPS33HW_ODR_50_Hz: - *val = LPS33HW_ODR_50_Hz; - break; - - case LPS33HW_ODR_75_Hz: - *val = LPS33HW_ODR_75_Hz; - break; - - default: - *val = LPS33HW_ODR_1_Hz; - break; - } - - return ret; -} - -/** - * @brief One-shot mode. Device perform a single measure.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of one_shot in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33hw_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - - if (ret == 0) - { - ctrl_reg2.one_shot = val; - ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - } - - return ret; -} - -/** - * @brief One-shot mode. Device perform a single measure.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of one_shot in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33hw_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - *val = ctrl_reg2.one_shot; - - return ret; -} - -/** - * @brief pressure_ref: The Reference pressure value is a 24-bit data - * expressed as 2’s complement. The value is used when AUTOZERO - * or AUTORIFP function is enabled.[set] - * - * @param ctx Read / write interface definitions - * @param buff Buffer that contains data to write - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_pressure_ref_set(stmdev_ctx_t *ctx, int32_t val) -{ - uint8_t buff[3]; - int32_t ret; - - buff[2] = (uint8_t)((uint32_t)val / 65536U); - buff[1] = (uint8_t)((uint32_t)val - (buff[2] * 65536U)) / 256U; - buff[0] = (uint8_t)((uint32_t)val - (buff[2] * 65536U) - - (buff[1] * 256U)); - ret = lps33hw_write_reg(ctx, LPS33HW_REF_P_XL, buff, 3); - - return ret; -} - -/** - * @brief pressure_ref: The Reference pressure value is a 24-bit data - * expressed as 2’s complement. The value is used when AUTOZERO - * or AUTORIFP function is enabled.[get] - * - * @param ctx Read / write interface definitions - * @param buff Buffer that stores data read - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_pressure_ref_get(stmdev_ctx_t *ctx, int32_t *val) -{ - uint8_t buff[3]; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_REF_P_XL, buff, 3); - *val = (int32_t)buff[2]; - *val = (*val * 256) + (int32_t)buff[1]; - *val = (*val * 256) + (int32_t)buff[0]; - - return ret; -} - -/** - * @brief The pressure offset value is 16-bit data that can be used to - * implement one-point calibration (OPC) after soldering.[set] - * - * @param ctx Read / write interface definitions - * @param buff Buffer that contains data to write - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val) -{ - uint8_t buff[2]; - int32_t ret; - - buff[1] = (uint8_t)((uint16_t)val / 256U); - buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U)); - ret = lps33hw_write_reg(ctx, LPS33HW_RPDS_L, buff, 2); - - return ret; -} - -/** - * @brief The pressure offset value is 16-bit data that can be used to - * implement one-point calibration (OPC) after soldering.[get] - * - * @param ctx Read / write interface definitions - * @param buff Buffer that stores data read - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val) -{ - uint8_t buff[2]; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_RPDS_L, buff, 2); - *val = (int16_t)buff[1]; - *val = (*val * 256) + (int16_t)buff[0]; - - return ret; -} - -/** - * @brief Pressure data available.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of p_da in reg STATUS - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_press_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33hw_status_t status; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_STATUS, (uint8_t *)&status, 1); - *val = status.p_da; - - return ret; -} - -/** - * @brief Temperature data available.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of t_da in reg STATUS - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33hw_status_t status; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_STATUS, (uint8_t *)&status, 1); - *val = status.t_da; - - return ret; -} - -/** - * @brief Pressure data overrun.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of p_or in reg STATUS - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_press_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33hw_status_t status; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_STATUS, (uint8_t *)&status, 1); - *val = status.p_or; - - return ret; -} - -/** - * @brief Temperature data overrun.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of t_or in reg STATUS - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33hw_status_t status; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_STATUS, (uint8_t *)&status, 1); - *val = status.t_or; - - return ret; -} - -/** - * @brief Pressure output value[get] - * - * @param ctx Read / write interface definitions - * @param buff Buffer that stores data read - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff) -{ - uint8_t reg[3]; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_PRESS_OUT_XL, reg, 3); - *buff = reg[2]; - *buff = (*buff * 256) + reg[1]; - *buff = (*buff * 256) + reg[0]; - *buff *= 256; - - return ret; -} - -/** - * @brief temperature_raw: Temperature output value[get] - * - * @param ctx Read / write interface definitions - * @param buff Buffer that stores data read. - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff) -{ - uint8_t reg[2]; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_TEMP_OUT_L, (uint8_t *) reg, 2); - *buff = reg[1]; - *buff = (*buff * 256) + reg[0]; - - return ret; -} - -/** - * @brief Low-pass filter reset register. If the LPFP is active, in - * order to avoid the transitory phase, the filter can be - * reset by reading this register before generating pressure - * measurements.[get] - * - * @param ctx Read / write interface definitions - * @param buff Buffer that stores data read - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_low_pass_rst_get(stmdev_ctx_t *ctx, uint8_t *buff) -{ - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_LPFP_RES, (uint8_t *) buff, 1); - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LPS33HW_common - * @brief This section group common useful functions - * @{ - * - */ - -/** - * @brief Device Who am I[get] - * - * @param ctx Read / write interface definitions - * @param buff Buffer that stores data read - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) -{ - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_WHO_AM_I, (uint8_t *) buff, 1); - - return ret; -} - -/** - * @brief Software reset. Restore the default values in user registers[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of swreset in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_reset_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33hw_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - - if (ret == 0) - { - ctrl_reg2.swreset = val; - ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - } - - return ret; -} - -/** - * @brief Software reset. Restore the default values in user registers[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of swreset in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_reset_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33hw_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - *val = ctrl_reg2.swreset; - - return ret; -} - -/** - * @brief Reboot memory content. Reload the calibration parameters.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of boot in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_boot_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33hw_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - - if (ret == 0) - { - ctrl_reg2.boot = val; - ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - } - - return ret; -} - -/** - * @brief Reboot memory content. Reload the calibration parameters.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of boot in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_boot_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33hw_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - *val = ctrl_reg2.boot; - - return ret; -} - -/** - * @brief Low current mode.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of lc_en in reg RES_CONF - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_low_power_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33hw_res_conf_t res_conf; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_RES_CONF, (uint8_t *)&res_conf, 1); - - if (ret == 0) - { - res_conf.lc_en = val; - ret = lps33hw_write_reg(ctx, LPS33HW_RES_CONF, (uint8_t *)&res_conf, 1); - } - - return ret; -} - -/** - * @brief Low current mode.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of lc_en in reg RES_CONF - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_low_power_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33hw_res_conf_t res_conf; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_RES_CONF, (uint8_t *)&res_conf, 1); - *val = res_conf.lc_en; - - return ret; -} - -/** - * @brief If ‘1’ indicates that the Boot (Reboot) phase is running.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of boot_status in reg INT_SOURCE - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_boot_status_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33hw_int_source_t int_source; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_INT_SOURCE, - (uint8_t *)&int_source, 1); - *val = int_source.boot_status; - - return ret; -} - -/** - * @brief All the status bit, FIFO and data generation[get] - * - * @param ctx Read / write interface definitions - * @param val Structure of registers from FIFO_STATUS to STATUS - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_dev_status_get(stmdev_ctx_t *ctx, - lps33hw_dev_stat_t *val) -{ - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_FIFO_STATUS, (uint8_t *) val, 2); - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LPS33HW_interrupts - * @brief This section group all the functions that manage interrupts - * @{ - * - */ - -/** - * @brief Enable interrupt generation on pressure low/high event.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of pe in reg INTERRUPT_CFG - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_sign_of_int_threshold_set(stmdev_ctx_t *ctx, - lps33hw_pe_t val) -{ - lps33hw_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - - if (ret == 0) - { - interrupt_cfg.pe = (uint8_t)val; - ret = lps33hw_write_reg(ctx, LPS33HW_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - } - - return ret; -} - -/** - * @brief Enable interrupt generation on pressure low/high event.[get] - * - * @param ctx Read / write interface definitions - * @param val Get the values of pe in reg INTERRUPT_CFG - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_sign_of_int_threshold_get(stmdev_ctx_t *ctx, - lps33hw_pe_t *val) -{ - lps33hw_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - - switch (interrupt_cfg.pe) - { - case LPS33HW_NO_THRESHOLD: - *val = LPS33HW_NO_THRESHOLD; - break; - - case LPS33HW_POSITIVE: - *val = LPS33HW_POSITIVE; - break; - - case LPS33HW_NEGATIVE: - *val = LPS33HW_NEGATIVE; - break; - - case LPS33HW_BOTH: - *val = LPS33HW_BOTH; - break; - - default: - *val = LPS33HW_NO_THRESHOLD; - break; - } - - return ret; -} - -/** - * @brief Interrupt request to the INT_SOURCE (25h) register - * mode (pulsed / latched) [set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of lir in reg INTERRUPT_CFG - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_int_notification_mode_set(stmdev_ctx_t *ctx, - lps33hw_lir_t val) -{ - lps33hw_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - - if (ret == 0) - { - interrupt_cfg.lir = (uint8_t)val; - ret = lps33hw_write_reg(ctx, LPS33HW_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - } - - return ret; -} - -/** - * @brief Interrupt request to the INT_SOURCE (25h) register - * mode (pulsed / latched) [get] - * - * @param ctx Read / write interface definitions - * @param val Get the values of lir in reg INTERRUPT_CFG - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_int_notification_mode_get(stmdev_ctx_t *ctx, - lps33hw_lir_t *val) -{ - lps33hw_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - - switch (interrupt_cfg.lir) - { - case LPS33HW_INT_PULSED: - *val = LPS33HW_INT_PULSED; - break; - - case LPS33HW_INT_LATCHED: - *val = LPS33HW_INT_LATCHED; - break; - - default: - *val = LPS33HW_INT_PULSED; - break; - } - - return ret; -} - -/** - * @brief Enable interrupt generation.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of diff_en in reg INTERRUPT_CFG - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_int_generation_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33hw_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - - if (ret == 0) - { - interrupt_cfg.diff_en = val; - ret = lps33hw_write_reg(ctx, LPS33HW_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - } - - return ret; -} - -/** - * @brief Enable interrupt generation.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of diff_en in reg INTERRUPT_CFG - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33hw_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - *val = interrupt_cfg.diff_en; - - return ret; -} - -/** - * @brief User-defined threshold value for pressure interrupt event[set] - * - * @param ctx Read / write interface definitions - * @param buff Buffer that contains data to write - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_int_threshold_set(stmdev_ctx_t *ctx, uint16_t val) -{ - uint8_t buff[2]; - int32_t ret; - - buff[1] = (uint8_t)(val / 256U); - buff[0] = (uint8_t)(val - (buff[1] * 256U)); - ret = lps33hw_write_reg(ctx, LPS33HW_THS_P_L, (uint8_t *) buff, 2); - - return ret; -} - -/** - * @brief User-defined threshold value for pressure interrupt event[get] - * - * @param ctx Read / write interface definitions - * @param buff Buffer that stores data read - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_int_threshold_get(stmdev_ctx_t *ctx, uint16_t *val) -{ - uint8_t buff[2]; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_THS_P_L, (uint8_t *) buff, 2); - *val = buff[1]; - *val = (*val * 256) + buff[0]; - - return ret; -} - -/** - * @brief Data signal on INT_DRDY pin control bits.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of int_s in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_int_pin_mode_set(stmdev_ctx_t *ctx, - lps33hw_int_s_t val) -{ - lps33hw_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - - if (ret == 0) - { - ctrl_reg3.int_s = (uint8_t)val; - ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - } - - return ret; -} - -/** - * @brief Data signal on INT_DRDY pin control bits.[get] - * - * @param ctx Read / write interface definitions - * @param val Get the values of int_s in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_int_pin_mode_get(stmdev_ctx_t *ctx, - lps33hw_int_s_t *val) -{ - lps33hw_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - - switch (ctrl_reg3.int_s) - { - case LPS33HW_DRDY_OR_FIFO_FLAGS: - *val = LPS33HW_DRDY_OR_FIFO_FLAGS; - break; - - case LPS33HW_HIGH_PRES_INT: - *val = LPS33HW_HIGH_PRES_INT; - break; - - case LPS33HW_LOW_PRES_INT: - *val = LPS33HW_LOW_PRES_INT; - break; - - case LPS33HW_EVERY_PRES_INT: - *val = LPS33HW_EVERY_PRES_INT; - break; - - default: - *val = LPS33HW_DRDY_OR_FIFO_FLAGS; - break; - } - - return ret; -} - -/** - * @brief Data-ready signal on INT_DRDY pin.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of drdy in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_drdy_on_int_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33hw_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - - if (ret == 0) - { - ctrl_reg3.drdy = val; - ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - } - - return ret; -} - -/** - * @brief Data-ready signal on INT_DRDY pin.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of drdy in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33hw_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - *val = ctrl_reg3.drdy; - - return ret; -} - -/** - * @brief FIFO overrun interrupt on INT_DRDY pin.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of f_ovr in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33hw_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - - if (ret == 0) - { - ctrl_reg3.f_ovr = val; - ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - } - - return ret; -} - -/** - * @brief FIFO overrun interrupt on INT_DRDY pin.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of f_ovr in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33hw_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - *val = ctrl_reg3.f_ovr; - - return ret; -} - -/** - * @brief FIFO watermark status on INT_DRDY pin.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of f_fth in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, - uint8_t val) -{ - lps33hw_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - - if (ret == 0) - { - ctrl_reg3.f_fth = val; - ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - } - - return ret; -} - -/** - * @brief FIFO watermark status on INT_DRDY pin.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of f_fth in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - lps33hw_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - *val = ctrl_reg3.f_fth; - - return ret; -} - -/** - * @brief FIFO full flag on INT_DRDY pin.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of f_fss5 in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33hw_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - - if (ret == 0) - { - ctrl_reg3.f_fss5 = val; - ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - } - - return ret; -} - -/** - * @brief FIFO full flag on INT_DRDY pin.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of f_fss5 in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_fifo_full_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33hw_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - *val = ctrl_reg3.f_fss5; - - return ret; -} - -/** - * @brief Push-pull/open drain selection on interrupt pads.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of pp_od in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_pin_mode_set(stmdev_ctx_t *ctx, lps33hw_pp_od_t val) -{ - lps33hw_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - - if (ret == 0) - { - ctrl_reg3.pp_od = (uint8_t)val; - ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - } - - return ret; -} - -/** - * @brief Push-pull/open drain selection on interrupt pads.[get] - * - * @param ctx Read / write interface definitions - * @param val Get the values of pp_od in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_pin_mode_get(stmdev_ctx_t *ctx, lps33hw_pp_od_t *val) -{ - lps33hw_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - - switch (ctrl_reg3.pp_od) - { - case LPS33HW_PUSH_PULL: - *val = LPS33HW_PUSH_PULL; - break; - - case LPS33HW_OPEN_DRAIN: - *val = LPS33HW_OPEN_DRAIN; - break; - - default: - *val = LPS33HW_PUSH_PULL; - break; - } - - return ret; -} - -/** - * @brief Interrupt active-high/low.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of int_h_l in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_int_polarity_set(stmdev_ctx_t *ctx, - lps33hw_int_h_l_t val) -{ - lps33hw_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - - if (ret == 0) - { - ctrl_reg3.int_h_l = (uint8_t)val; - ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - } - - return ret; -} - -/** - * @brief Interrupt active-high/low.[get] - * - * @param ctx Read / write interface definitions - * @param val Get the values of int_h_l in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_int_polarity_get(stmdev_ctx_t *ctx, - lps33hw_int_h_l_t *val) -{ - lps33hw_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - - switch (ctrl_reg3.int_h_l) - { - case LPS33HW_ACTIVE_HIGH: - *val = LPS33HW_ACTIVE_HIGH; - break; - - case LPS33HW_ACTIVE_LOW: - *val = LPS33HW_ACTIVE_LOW; - break; - - default: - *val = LPS33HW_ACTIVE_HIGH; - break; - } - - return ret; -} - -/** - * @brief Interrupt source register[get] - * - * @param ctx Read / write interface definitions - * @param val Register INT_SOURCE - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_int_source_get(stmdev_ctx_t *ctx, - lps33hw_int_source_t *val) -{ - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_INT_SOURCE, (uint8_t *) val, 1); - - return ret; -} - -/** - * @brief Differential pressure high interrupt flag.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of ph in reg INT_SOURCE - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_int_on_press_high_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33hw_int_source_t int_source; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_INT_SOURCE, - (uint8_t *)&int_source, 1); - *val = int_source.ph; - - return ret; -} - -/** - * @brief Differential pressure low interrupt flag.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of pl in reg INT_SOURCE - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_int_on_press_low_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33hw_int_source_t int_source; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_INT_SOURCE, - (uint8_t *)&int_source, 1); - *val = int_source.pl; - - return ret; -} - -/** - * @brief Interrupt active flag.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of ia in reg INT_SOURCE - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_interrupt_event_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33hw_int_source_t int_source; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_INT_SOURCE, - (uint8_t *)&int_source, 1); - *val = int_source.ia; - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LPS33HW_fifo - * @brief This section group all the functions concerning the - * fifo usage - * @{ - * - */ - -/** - * @brief Stop on FIFO watermark. Enable FIFO watermark level use.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of stop_on_fth in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx, - uint8_t val) -{ - lps33hw_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - - if (ret == 0) - { - ctrl_reg2.stop_on_fth = val; - ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - } - - return ret; -} - -/** - * @brief Stop on FIFO watermark. Enable FIFO watermark level use.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of stop_on_fth in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_stop_on_fifo_threshold_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - lps33hw_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - *val = ctrl_reg2.stop_on_fth; - - return ret; -} - -/** - * @brief FIFO enable.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of fifo_en in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_fifo_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33hw_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - - if (ret == 0) - { - ctrl_reg2.fifo_en = val; - ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - } - - return ret; -} - -/** - * @brief FIFO enable.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of fifo_en in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_fifo_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33hw_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - *val = ctrl_reg2.fifo_en; - - return ret; -} - -/** - * @brief FIFO watermark level selection.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of wtm in reg FIFO_CTRL - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33hw_fifo_ctrl_t fifo_ctrl; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); - - if (ret == 0) - { - fifo_ctrl.wtm = val; - ret = lps33hw_write_reg(ctx, LPS33HW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); - } - - return ret; -} - -/** - * @brief FIFO watermark level selection.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of wtm in reg FIFO_CTRL - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33hw_fifo_ctrl_t fifo_ctrl; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); - *val = fifo_ctrl.wtm; - - return ret; -} - -/** - * @brief FIFO mode selection.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of f_mode in reg FIFO_CTRL - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_fifo_mode_set(stmdev_ctx_t *ctx, lps33hw_f_mode_t val) -{ - lps33hw_fifo_ctrl_t fifo_ctrl; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); - - if (ret == 0) - { - fifo_ctrl.f_mode = (uint8_t)val; - ret = lps33hw_write_reg(ctx, LPS33HW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); - } - - return ret; -} - -/** - * @brief FIFO mode selection.[get] - * - * @param ctx Read / write interface definitions - * @param val Get the values of f_mode in reg FIFO_CTRL - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_fifo_mode_get(stmdev_ctx_t *ctx, - lps33hw_f_mode_t *val) -{ - lps33hw_fifo_ctrl_t fifo_ctrl; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); - - switch (fifo_ctrl.f_mode) - { - case LPS33HW_BYPASS_MODE: - *val = LPS33HW_BYPASS_MODE; - break; - - case LPS33HW_FIFO_MODE: - *val = LPS33HW_FIFO_MODE; - break; - - case LPS33HW_STREAM_MODE: - *val = LPS33HW_STREAM_MODE; - break; - - case LPS33HW_STREAM_TO_FIFO_MODE: - *val = LPS33HW_STREAM_TO_FIFO_MODE; - break; - - case LPS33HW_BYPASS_TO_STREAM_MODE: - *val = LPS33HW_BYPASS_TO_STREAM_MODE; - break; - - case LPS33HW_DYNAMIC_STREAM_MODE: - *val = LPS33HW_DYNAMIC_STREAM_MODE; - break; - - case LPS33HW_BYPASS_TO_FIFO_MODE: - *val = LPS33HW_BYPASS_TO_FIFO_MODE; - break; - - default: - *val = LPS33HW_BYPASS_MODE; - break; - } - - return ret; -} - -/** - * @brief FIFO stored data level.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of fss in reg FIFO_STATUS - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33hw_fifo_status_t fifo_status; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_FIFO_STATUS, - (uint8_t *)&fifo_status, 1); - *val = fifo_status.fss; - - return ret; -} - -/** - * @brief FIFO overrun status.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of ovr in reg FIFO_STATUS - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33hw_fifo_status_t fifo_status; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_FIFO_STATUS, - (uint8_t *)&fifo_status, 1); - *val = fifo_status.ovr; - - return ret; -} - -/** - * @brief FIFO watermark status.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of fth_fifo in reg FIFO_STATUS - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33hw_fifo_status_t fifo_status; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_FIFO_STATUS, - (uint8_t *)&fifo_status, 1); - *val = fifo_status.fth_fifo; - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LPS33HW_serial_interface - * @brief This section group all the functions concerning serial - * interface management - * @{ - * - */ - -/** - * @brief SPI Serial Interface Mode selection.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of sim in reg CTRL_REG1 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_spi_mode_set(stmdev_ctx_t *ctx, lps33hw_sim_t val) -{ - lps33hw_ctrl_reg1_t ctrl_reg1; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - - if (ret == 0) - { - ctrl_reg1.sim = (uint8_t)val; - ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - } - - return ret; -} - -/** - * @brief SPI Serial Interface Mode selection.[get] - * - * @param ctx Read / write interface definitions - * @param val Get the values of sim in reg CTRL_REG1 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_spi_mode_get(stmdev_ctx_t *ctx, lps33hw_sim_t *val) -{ - lps33hw_ctrl_reg1_t ctrl_reg1; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - - switch (ctrl_reg1.sim) - { - case LPS33HW_SPI_4_WIRE: - *val = LPS33HW_SPI_4_WIRE; - break; - - case LPS33HW_SPI_3_WIRE: - *val = LPS33HW_SPI_3_WIRE; - break; - - default: - *val = LPS33HW_SPI_4_WIRE; - break; - } - - return ret; -} - -/** - * @brief Disable I2C interface.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of i2c_dis in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_i2c_interface_set(stmdev_ctx_t *ctx, - lps33hw_i2c_dis_t val) -{ - lps33hw_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - - if (ret == 0) - { - ctrl_reg2.i2c_dis = (uint8_t)val; - ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - } - - return ret; -} - -/** - * @brief Disable I2C interface.[get] - * - * @param ctx Read / write interface definitions - * @param val Get the values of i2c_dis in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_i2c_interface_get(stmdev_ctx_t *ctx, - lps33hw_i2c_dis_t *val) -{ - lps33hw_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - - switch (ctrl_reg2.i2c_dis) - { - case LPS33HW_I2C_ENABLE: - *val = LPS33HW_I2C_ENABLE; - break; - - case LPS33HW_I2C_DISABLE: - *val = LPS33HW_I2C_DISABLE; - break; - - default: - *val = LPS33HW_I2C_ENABLE; - break; - } - - return ret; -} - -/** - * @brief Register address automatically incremented during a - * multiple byte access with a serial interface (I2C or SPI).[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of if_add_inc in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_auto_add_inc_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33hw_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - - if (ret == 0) - { - ctrl_reg2.if_add_inc = val; - ret = lps33hw_write_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - } - - return ret; -} - -/** - * @brief Register address automatically incremented during a - * multiple byte access with a serial interface (I2C or SPI).[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of if_add_inc in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33hw_auto_add_inc_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33hw_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33hw_read_reg(ctx, LPS33HW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - *val = ctrl_reg2.if_add_inc; - - return ret; -} - -/** - * @} - * - */ - -/** - * @} - * - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lps33hw_STdC/driver/lps33hw_reg.h b/sensor/stmemsc/lps33hw_STdC/driver/lps33hw_reg.h deleted file mode 100644 index 3d0d6dca..00000000 --- a/sensor/stmemsc/lps33hw_STdC/driver/lps33hw_reg.h +++ /dev/null @@ -1,651 +0,0 @@ -/** - ****************************************************************************** - * @file lps33hw_reg.h - * @author Sensors Software Solution Team - * @brief This file contains all the functions prototypes for the - * lps33hw_reg.c driver. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef LPS33HW_REGS_H -#define LPS33HW_REGS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include -#include -#include - -/** @addtogroup LPS33HW - * @{ - * - */ - -/** @defgroup Endianness definitions - * @{ - * - */ - -#ifndef DRV_BYTE_ORDER -#ifndef __BYTE_ORDER__ - -#define DRV_LITTLE_ENDIAN 1234 -#define DRV_BIG_ENDIAN 4321 - -/** if _BYTE_ORDER is not defined, choose the endianness of your architecture - * by uncommenting the define which fits your platform endianness - */ -//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN -#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN - -#else /* defined __BYTE_ORDER__ */ - -#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ -#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ -#define DRV_BYTE_ORDER __BYTE_ORDER__ - -#endif /* __BYTE_ORDER__*/ -#endif /* DRV_BYTE_ORDER */ - -/** - * @} - * - */ - -/** @defgroup STMicroelectronics sensors common types - * @{ - * - */ - -#ifndef MEMS_SHARED_TYPES -#define MEMS_SHARED_TYPES - -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t bit0 : 1; - uint8_t bit1 : 1; - uint8_t bit2 : 1; - uint8_t bit3 : 1; - uint8_t bit4 : 1; - uint8_t bit5 : 1; - uint8_t bit6 : 1; - uint8_t bit7 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t bit7 : 1; - uint8_t bit6 : 1; - uint8_t bit5 : 1; - uint8_t bit4 : 1; - uint8_t bit3 : 1; - uint8_t bit2 : 1; - uint8_t bit1 : 1; - uint8_t bit0 : 1; -#endif /* DRV_BIG_ENDIAN */ -} bitwise_t; - -#define PROPERTY_DISABLE (0U) -#define PROPERTY_ENABLE (1U) - -/** @addtogroup Interfaces_Functions - * @brief This section provide a set of functions used to read and - * write a generic register of the device. - * MANDATORY: return 0 -> no Error. - * @{ - * - */ - -typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); -typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); -typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); - -typedef struct -{ - /** Component mandatory fields **/ - stmdev_write_ptr write_reg; - stmdev_read_ptr read_reg; - /** Component optional fields **/ - stmdev_mdelay_ptr mdelay; - /** Customizable optional pointer **/ - void *handle; -} stmdev_ctx_t; - -/** - * @} - * - */ - -#endif /* MEMS_SHARED_TYPES */ - -#ifndef MEMS_UCF_SHARED_TYPES -#define MEMS_UCF_SHARED_TYPES - -/** @defgroup Generic address-data structure definition - * @brief This structure is useful to load a predefined configuration - * of a sensor. - * You can create a sensor configuration by your own or using - * Unico / Unicleo tools available on STMicroelectronics - * web site. - * - * @{ - * - */ - -typedef struct -{ - uint8_t address; - uint8_t data; -} ucf_line_t; - -/** - * @} - * - */ - -#endif /* MEMS_UCF_SHARED_TYPES */ - -/** - * @} - * - */ - - -/** @defgroup LPS33HW_Infos - * @{ - * - */ - -/** I2C Device Address 8 bit format: if SA0=0 -> 0xB9 if SA0=1 -> 0xBB **/ -#define LPS33HW_I2C_ADD_H 0xBBU -#define LPS33HW_I2C_ADD_L 0xB9U - -/** Device Identification (Who am I) **/ -#define LPS33HW_ID 0xB1U - -/** - * @} - * - */ - -#define LPS33HW_INTERRUPT_CFG 0x0BU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t pe : 2; /* ple + phe -> pe */ - uint8_t lir : 1; - uint8_t diff_en : 1; - uint8_t reset_az : 1; - uint8_t autozero : 1; - uint8_t reset_arp : 1; - uint8_t autorifp : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t autorifp : 1; - uint8_t reset_arp : 1; - uint8_t autozero : 1; - uint8_t reset_az : 1; - uint8_t diff_en : 1; - uint8_t lir : 1; - uint8_t pe : 2; /* ple + phe -> pe */ -#endif /* DRV_BIG_ENDIAN */ -} lps33hw_interrupt_cfg_t; - -#define LPS33HW_THS_P_L 0x0CU -#define LPS33HW_THS_P_H 0x0DU -#define LPS33HW_WHO_AM_I 0x0FU -#define LPS33HW_CTRL_REG1 0x10U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t sim : 1; - uint8_t bdu : 1; - uint8_t lpfp : 2; /* en_lpfp + lpfp_cfg -> lpfp */ - uint8_t odr : 3; - uint8_t not_used_01 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 1; - uint8_t odr : 3; - uint8_t lpfp : 2; /* en_lpfp + lpfp_cfg -> lpfp */ - uint8_t bdu : 1; - uint8_t sim : 1; -#endif /* DRV_BIG_ENDIAN */ -} lps33hw_ctrl_reg1_t; - -#define LPS33HW_CTRL_REG2 0x11U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t one_shot : 1; - uint8_t not_used_01 : 1; - uint8_t swreset : 1; - uint8_t i2c_dis : 1; - uint8_t if_add_inc : 1; - uint8_t stop_on_fth : 1; - uint8_t fifo_en : 1; - uint8_t boot : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t boot : 1; - uint8_t fifo_en : 1; - uint8_t stop_on_fth : 1; - uint8_t if_add_inc : 1; - uint8_t i2c_dis : 1; - uint8_t swreset : 1; - uint8_t not_used_01 : 1; - uint8_t one_shot : 1; -#endif /* DRV_BIG_ENDIAN */ -} lps33hw_ctrl_reg2_t; - -#define LPS33HW_CTRL_REG3 0x12U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t int_s : 2; - uint8_t drdy : 1; - uint8_t f_ovr : 1; - uint8_t f_fth : 1; - uint8_t f_fss5 : 1; - uint8_t pp_od : 1; - uint8_t int_h_l : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t int_h_l : 1; - uint8_t pp_od : 1; - uint8_t f_fss5 : 1; - uint8_t f_fth : 1; - uint8_t f_ovr : 1; - uint8_t drdy : 1; - uint8_t int_s : 2; -#endif /* DRV_BIG_ENDIAN */ -} lps33hw_ctrl_reg3_t; - - -#define LPS33HW_FIFO_CTRL 0x14U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t wtm : 5; - uint8_t f_mode : 3; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t f_mode : 3; - uint8_t wtm : 5; -#endif /* DRV_BIG_ENDIAN */ -} lps33hw_fifo_ctrl_t; - -#define LPS33HW_REF_P_XL 0x15U -#define LPS33HW_REF_P_L 0x16U -#define LPS33HW_REF_P_H 0x17U -#define LPS33HW_RPDS_L 0x18U -#define LPS33HW_RPDS_H 0x19U - -#define LPS33HW_RES_CONF 0x1AU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t lc_en : 1; - uint8_t not_used_01 : 7; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 7; - uint8_t lc_en : 1; -#endif /* DRV_BIG_ENDIAN */ -} lps33hw_res_conf_t; - -#define LPS33HW_INT_SOURCE 0x25U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t ph : 1; - uint8_t pl : 1; - uint8_t ia : 1; - uint8_t not_used_01 : 4; - uint8_t boot_status : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t boot_status : 1; - uint8_t not_used_01 : 4; - uint8_t ia : 1; - uint8_t pl : 1; - uint8_t ph : 1; -#endif /* DRV_BIG_ENDIAN */ -} lps33hw_int_source_t; - -#define LPS33HW_FIFO_STATUS 0x26U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t fss : 6; - uint8_t ovr : 1; - uint8_t fth_fifo : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t fth_fifo : 1; - uint8_t ovr : 1; - uint8_t fss : 6; -#endif /* DRV_BIG_ENDIAN */ -} lps33hw_fifo_status_t; - -#define LPS33HW_STATUS 0x27U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t p_da : 1; - uint8_t t_da : 1; - uint8_t not_used_02 : 2; - uint8_t p_or : 1; - uint8_t t_or : 1; - uint8_t not_used_01 : 2; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 2; - uint8_t t_or : 1; - uint8_t p_or : 1; - uint8_t not_used_02 : 2; - uint8_t t_da : 1; - uint8_t p_da : 1; -#endif /* DRV_BIG_ENDIAN */ -} lps33hw_status_t; - -#define LPS33HW_PRESS_OUT_XL 0x28U -#define LPS33HW_PRESS_OUT_L 0x29U -#define LPS33HW_PRESS_OUT_H 0x2AU -#define LPS33HW_TEMP_OUT_L 0x2BU -#define LPS33HW_TEMP_OUT_H 0x2CU -#define LPS33HW_LPFP_RES 0x33U - -/** - * @defgroup LPS33HW_Register_Union - * @brief This union group all the registers having a bit-field - * description. - * This union is useful but it's not needed by the driver. - * - * REMOVING this union you are compliant with: - * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " - * - * @{ - * - */ - -typedef union -{ - lps33hw_interrupt_cfg_t interrupt_cfg; - lps33hw_ctrl_reg1_t ctrl_reg1; - lps33hw_ctrl_reg2_t ctrl_reg2; - lps33hw_ctrl_reg3_t ctrl_reg3; - lps33hw_fifo_ctrl_t fifo_ctrl; - lps33hw_res_conf_t res_conf; - lps33hw_int_source_t int_source; - lps33hw_fifo_status_t fifo_status; - lps33hw_status_t status; - bitwise_t bitwise; - uint8_t byte; -} lps33hw_reg_t; - -/** - * @} - * - */ - -#ifndef __weak -#define __weak __attribute__((weak)) -#endif /* __weak */ - -/* - * These are the basic platform dependent I/O routines to read - * and write device registers connected on a standard bus. - * The driver keeps offering a default implementation based on function - * pointers to read/write routines for backward compatibility. - * The __weak directive allows the final application to overwrite - * them with a custom implementation. - */ - -int32_t lps33hw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len); -int32_t lps33hw_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len); - -float_t lps33hw_from_lsb_to_hpa(int32_t lsb); - -float_t lps33hw_from_lsb_to_degc(int16_t lsb); - -int32_t lps33hw_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33hw_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33hw_autozero_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33hw_autozero_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33hw_pressure_snap_rst_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33hw_pressure_snap_rst_get(stmdev_ctx_t *ctx, - uint8_t *val); - -int32_t lps33hw_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33hw_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33hw_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33hw_block_data_update_get(stmdev_ctx_t *ctx, - uint8_t *val); - -typedef enum -{ - LPS33HW_LPF_ODR_DIV_2 = 0, - LPS33HW_LPF_ODR_DIV_9 = 2, - LPS33HW_LPF_ODR_DIV_20 = 3, -} lps33hw_lpfp_t; -int32_t lps33hw_low_pass_filter_mode_set(stmdev_ctx_t *ctx, - lps33hw_lpfp_t val); -int32_t lps33hw_low_pass_filter_mode_get(stmdev_ctx_t *ctx, - lps33hw_lpfp_t *val); - -typedef enum -{ - LPS33HW_POWER_DOWN = 0, - LPS33HW_ODR_1_Hz = 1, - LPS33HW_ODR_10_Hz = 2, - LPS33HW_ODR_25_Hz = 3, - LPS33HW_ODR_50_Hz = 4, - LPS33HW_ODR_75_Hz = 5, -} lps33hw_odr_t; -int32_t lps33hw_data_rate_set(stmdev_ctx_t *ctx, lps33hw_odr_t val); -int32_t lps33hw_data_rate_get(stmdev_ctx_t *ctx, lps33hw_odr_t *val); - -int32_t lps33hw_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33hw_one_shoot_trigger_get(stmdev_ctx_t *ctx, - uint8_t *val); - -int32_t lps33hw_pressure_ref_set(stmdev_ctx_t *ctx, int32_t val); -int32_t lps33hw_pressure_ref_get(stmdev_ctx_t *ctx, int32_t *val); - -int32_t lps33hw_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val); -int32_t lps33hw_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val); - -int32_t lps33hw_press_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33hw_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33hw_press_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33hw_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33hw_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff); - -int32_t lps33hw_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff); - -int32_t lps33hw_low_pass_rst_get(stmdev_ctx_t *ctx, uint8_t *buff); - -int32_t lps33hw_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); - -int32_t lps33hw_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33hw_reset_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33hw_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33hw_boot_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33hw_low_power_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33hw_low_power_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33hw_boot_status_get(stmdev_ctx_t *ctx, uint8_t *val); - -typedef struct -{ - lps33hw_fifo_status_t fifo_status; - lps33hw_status_t status; -} lps33hw_dev_stat_t; -int32_t lps33hw_dev_status_get(stmdev_ctx_t *ctx, - lps33hw_dev_stat_t *val); - -typedef enum -{ - LPS33HW_NO_THRESHOLD = 0, - LPS33HW_POSITIVE = 1, - LPS33HW_NEGATIVE = 2, - LPS33HW_BOTH = 3, -} lps33hw_pe_t; -int32_t lps33hw_sign_of_int_threshold_set(stmdev_ctx_t *ctx, - lps33hw_pe_t val); -int32_t lps33hw_sign_of_int_threshold_get(stmdev_ctx_t *ctx, - lps33hw_pe_t *val); - -typedef enum -{ - LPS33HW_INT_PULSED = 0, - LPS33HW_INT_LATCHED = 1, -} lps33hw_lir_t; -int32_t lps33hw_int_notification_mode_set(stmdev_ctx_t *ctx, - lps33hw_lir_t val); -int32_t lps33hw_int_notification_mode_get(stmdev_ctx_t *ctx, - lps33hw_lir_t *val); - -int32_t lps33hw_int_generation_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33hw_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33hw_int_threshold_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lps33hw_int_threshold_get(stmdev_ctx_t *ctx, uint16_t *val); - -typedef enum -{ - LPS33HW_DRDY_OR_FIFO_FLAGS = 0, - LPS33HW_HIGH_PRES_INT = 1, - LPS33HW_LOW_PRES_INT = 2, - LPS33HW_EVERY_PRES_INT = 3, -} lps33hw_int_s_t; -int32_t lps33hw_int_pin_mode_set(stmdev_ctx_t *ctx, - lps33hw_int_s_t val); -int32_t lps33hw_int_pin_mode_get(stmdev_ctx_t *ctx, - lps33hw_int_s_t *val); - -int32_t lps33hw_drdy_on_int_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33hw_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33hw_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33hw_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33hw_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, - uint8_t val); -int32_t lps33hw_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, - uint8_t *val); - -int32_t lps33hw_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33hw_fifo_full_on_int_get(stmdev_ctx_t *ctx, uint8_t *val); - -typedef enum -{ - LPS33HW_PUSH_PULL = 0, - LPS33HW_OPEN_DRAIN = 1, -} lps33hw_pp_od_t; -int32_t lps33hw_pin_mode_set(stmdev_ctx_t *ctx, lps33hw_pp_od_t val); -int32_t lps33hw_pin_mode_get(stmdev_ctx_t *ctx, lps33hw_pp_od_t *val); - -typedef enum -{ - LPS33HW_ACTIVE_HIGH = 0, - LPS33HW_ACTIVE_LOW = 1, -} lps33hw_int_h_l_t; -int32_t lps33hw_int_polarity_set(stmdev_ctx_t *ctx, - lps33hw_int_h_l_t val); -int32_t lps33hw_int_polarity_get(stmdev_ctx_t *ctx, - lps33hw_int_h_l_t *val); - -int32_t lps33hw_int_source_get(stmdev_ctx_t *ctx, - lps33hw_int_source_t *val); - -int32_t lps33hw_int_on_press_high_get(stmdev_ctx_t *ctx, - uint8_t *val); - -int32_t lps33hw_int_on_press_low_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33hw_interrupt_event_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33hw_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx, - uint8_t val); -int32_t lps33hw_stop_on_fifo_threshold_get(stmdev_ctx_t *ctx, - uint8_t *val); - -int32_t lps33hw_fifo_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33hw_fifo_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33hw_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33hw_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); - -typedef enum -{ - LPS33HW_BYPASS_MODE = 0, - LPS33HW_FIFO_MODE = 1, - LPS33HW_STREAM_MODE = 2, - LPS33HW_STREAM_TO_FIFO_MODE = 3, - LPS33HW_BYPASS_TO_STREAM_MODE = 4, - LPS33HW_DYNAMIC_STREAM_MODE = 6, - LPS33HW_BYPASS_TO_FIFO_MODE = 7, -} lps33hw_f_mode_t; -int32_t lps33hw_fifo_mode_set(stmdev_ctx_t *ctx, - lps33hw_f_mode_t val); -int32_t lps33hw_fifo_mode_get(stmdev_ctx_t *ctx, - lps33hw_f_mode_t *val); - -int32_t lps33hw_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33hw_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33hw_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val); - -typedef enum -{ - LPS33HW_SPI_4_WIRE = 0, - LPS33HW_SPI_3_WIRE = 1, -} lps33hw_sim_t; -int32_t lps33hw_spi_mode_set(stmdev_ctx_t *ctx, lps33hw_sim_t val); -int32_t lps33hw_spi_mode_get(stmdev_ctx_t *ctx, lps33hw_sim_t *val); - -typedef enum -{ - LPS33HW_I2C_ENABLE = 0, - LPS33HW_I2C_DISABLE = 1, -} lps33hw_i2c_dis_t; -int32_t lps33hw_i2c_interface_set(stmdev_ctx_t *ctx, - lps33hw_i2c_dis_t val); -int32_t lps33hw_i2c_interface_get(stmdev_ctx_t *ctx, - lps33hw_i2c_dis_t *val); - -int32_t lps33hw_auto_add_inc_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33hw_auto_add_inc_get(stmdev_ctx_t *ctx, uint8_t *val); - -/** - *@} - * - */ - -#ifdef __cplusplus -} -#endif - -#endif /* LPS33HW_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.c b/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.c index 42310a9b..40a1c356 100644 --- a/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.c +++ b/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.c @@ -45,11 +45,16 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lps33k_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, +int32_t __weak lps33k_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -65,12 +70,17 @@ int32_t __weak lps33k_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lps33k_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lps33k_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -119,7 +129,7 @@ float_t lps33k_from_lsb_to_degc(int16_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps33k_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps33k_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lps33k_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -143,7 +153,7 @@ int32_t lps33k_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps33k_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps33k_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps33k_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -162,7 +172,7 @@ int32_t lps33k_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps33k_low_pass_filter_mode_set(stmdev_ctx_t *ctx, +int32_t lps33k_low_pass_filter_mode_set(const stmdev_ctx_t *ctx, lps33k_lpfp_t val) { lps33k_ctrl_reg1_t ctrl_reg1; @@ -187,7 +197,7 @@ int32_t lps33k_low_pass_filter_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps33k_low_pass_filter_mode_get(stmdev_ctx_t *ctx, +int32_t lps33k_low_pass_filter_mode_get(const stmdev_ctx_t *ctx, lps33k_lpfp_t *val) { lps33k_ctrl_reg1_t ctrl_reg1; @@ -225,7 +235,7 @@ int32_t lps33k_low_pass_filter_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps33k_data_rate_set(stmdev_ctx_t *ctx, lps33k_odr_t val) +int32_t lps33k_data_rate_set(const stmdev_ctx_t *ctx, lps33k_odr_t val) { lps33k_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -249,7 +259,7 @@ int32_t lps33k_data_rate_set(stmdev_ctx_t *ctx, lps33k_odr_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps33k_data_rate_get(stmdev_ctx_t *ctx, lps33k_odr_t *val) +int32_t lps33k_data_rate_get(const stmdev_ctx_t *ctx, lps33k_odr_t *val) { lps33k_ctrl_reg1_t ctrl_reg1; int32_t ret; @@ -298,7 +308,7 @@ int32_t lps33k_data_rate_get(stmdev_ctx_t *ctx, lps33k_odr_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps33k_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps33k_one_shoot_trigger_set(const stmdev_ctx_t *ctx, uint8_t val) { lps33k_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -322,7 +332,7 @@ int32_t lps33k_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps33k_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps33k_one_shoot_trigger_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps33k_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -342,7 +352,7 @@ int32_t lps33k_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps33k_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val) +int32_t lps33k_pressure_offset_set(const stmdev_ctx_t *ctx, int16_t val) { uint8_t buff[2]; int32_t ret; @@ -363,7 +373,7 @@ int32_t lps33k_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps33k_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lps33k_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -383,7 +393,7 @@ int32_t lps33k_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps33k_press_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps33k_press_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps33k_status_t status; int32_t ret; @@ -402,7 +412,7 @@ int32_t lps33k_press_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps33k_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps33k_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps33k_status_t status; int32_t ret; @@ -421,7 +431,7 @@ int32_t lps33k_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps33k_press_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps33k_press_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps33k_status_t status; int32_t ret; @@ -440,7 +450,7 @@ int32_t lps33k_press_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps33k_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps33k_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps33k_status_t status; int32_t ret; @@ -459,7 +469,7 @@ int32_t lps33k_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps33k_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff) +int32_t lps33k_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff) { uint8_t reg[3]; int32_t ret; @@ -481,7 +491,7 @@ int32_t lps33k_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps33k_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff) +int32_t lps33k_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff) { uint8_t reg[2]; int32_t ret; @@ -504,7 +514,7 @@ int32_t lps33k_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps33k_low_pass_rst_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lps33k_low_pass_rst_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -533,7 +543,7 @@ int32_t lps33k_low_pass_rst_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps33k_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lps33k_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -550,7 +560,7 @@ int32_t lps33k_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps33k_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps33k_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lps33k_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -574,7 +584,7 @@ int32_t lps33k_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps33k_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps33k_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps33k_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -593,7 +603,7 @@ int32_t lps33k_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps33k_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps33k_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lps33k_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -617,7 +627,7 @@ int32_t lps33k_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps33k_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps33k_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps33k_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -636,7 +646,7 @@ int32_t lps33k_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps33k_low_power_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps33k_low_power_set(const stmdev_ctx_t *ctx, uint8_t val) { lps33k_res_conf_t res_conf; int32_t ret; @@ -660,7 +670,7 @@ int32_t lps33k_low_power_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps33k_low_power_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps33k_low_power_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps33k_res_conf_t res_conf; int32_t ret; @@ -693,7 +703,7 @@ int32_t lps33k_low_power_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps33k_auto_add_inc_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lps33k_auto_add_inc_set(const stmdev_ctx_t *ctx, uint8_t val) { lps33k_ctrl_reg2_t ctrl_reg2; int32_t ret; @@ -718,7 +728,7 @@ int32_t lps33k_auto_add_inc_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lps33k_auto_add_inc_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lps33k_auto_add_inc_get(const stmdev_ctx_t *ctx, uint8_t *val) { lps33k_ctrl_reg2_t ctrl_reg2; int32_t ret; diff --git a/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.h b/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.h index 656a2693..5d7917aa 100644 --- a/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.h +++ b/sensor/stmemsc/lps33k_STdC/driver/lps33k_reg.h @@ -304,9 +304,9 @@ typedef union * them with a custom implementation. */ -int32_t lps33k_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, +int32_t lps33k_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lps33k_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lps33k_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -314,8 +314,8 @@ float_t lps33k_from_lsb_to_hpa(int32_t lsb); float_t lps33k_from_lsb_to_degc(int16_t lsb); -int32_t lps33k_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33k_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps33k_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps33k_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -323,9 +323,9 @@ typedef enum LPS33K_LPF_ODR_DIV_9 = 2, LPS33K_LPF_ODR_DIV_20 = 3, } lps33k_lpfp_t; -int32_t lps33k_low_pass_filter_mode_set(stmdev_ctx_t *ctx, +int32_t lps33k_low_pass_filter_mode_set(const stmdev_ctx_t *ctx, lps33k_lpfp_t val); -int32_t lps33k_low_pass_filter_mode_get(stmdev_ctx_t *ctx, +int32_t lps33k_low_pass_filter_mode_get(const stmdev_ctx_t *ctx, lps33k_lpfp_t *val); typedef enum @@ -337,42 +337,42 @@ typedef enum LPS33K_ODR_50_Hz = 4, LPS33K_ODR_75_Hz = 5, } lps33k_odr_t; -int32_t lps33k_data_rate_set(stmdev_ctx_t *ctx, lps33k_odr_t val); -int32_t lps33k_data_rate_get(stmdev_ctx_t *ctx, lps33k_odr_t *val); +int32_t lps33k_data_rate_set(const stmdev_ctx_t *ctx, lps33k_odr_t val); +int32_t lps33k_data_rate_get(const stmdev_ctx_t *ctx, lps33k_odr_t *val); -int32_t lps33k_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33k_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps33k_one_shoot_trigger_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps33k_one_shoot_trigger_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps33k_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val); -int32_t lps33k_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lps33k_pressure_offset_set(const stmdev_ctx_t *ctx, int16_t val); +int32_t lps33k_pressure_offset_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lps33k_press_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps33k_press_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps33k_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps33k_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps33k_press_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps33k_press_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps33k_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps33k_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps33k_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff); +int32_t lps33k_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff); -int32_t lps33k_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff); +int32_t lps33k_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff); -int32_t lps33k_low_pass_rst_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lps33k_low_pass_rst_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lps33k_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lps33k_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lps33k_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33k_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps33k_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps33k_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps33k_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33k_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps33k_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps33k_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps33k_low_power_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33k_low_power_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps33k_low_power_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps33k_low_power_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lps33k_auto_add_inc_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33k_auto_add_inc_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lps33k_auto_add_inc_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lps33k_auto_add_inc_get(const stmdev_ctx_t *ctx, uint8_t *val); /** *@} diff --git a/sensor/stmemsc/lps33w_STdC/driver/lps33w_reg.c b/sensor/stmemsc/lps33w_STdC/driver/lps33w_reg.c deleted file mode 100644 index 5b9ca046..00000000 --- a/sensor/stmemsc/lps33w_STdC/driver/lps33w_reg.c +++ /dev/null @@ -1,2071 +0,0 @@ -/** - ****************************************************************************** - * @file lps33w_reg.c - * @author Sensors Software Solution Team - * @brief LPS33W driver file - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -#include "lps33w_reg.h" - -/** - * @defgroup LPS33W - * @brief This file provides a set of functions needed to drive the - * ultra-compact piezoresistive absolute pressure sensor. - * @{ - * - */ - -/** - * @defgroup LPS33W_Interfaces_functions - * @brief This section provide a set of functions used to read and - * write a generic register of the device. - * @{ - * - */ - -/** - * @brief Read generic device register - * - * @param ctx read / write interface definitions(ptr) - * @param reg register to read - * @param data pointer to buffer that store the data read(ptr) - * @param len number of consecutive register to read - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t __weak lps33w_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, - uint16_t len) -{ - int32_t ret; - - ret = ctx->read_reg(ctx->handle, reg, data, len); - - return ret; -} - -/** - * @brief Write generic device register - * - * @param ctx read / write interface definitions(ptr) - * @param reg register to write - * @param data pointer to data to write in register reg(ptr) - * @param len number of consecutive register to write - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t __weak lps33w_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) -{ - int32_t ret; - - ret = ctx->write_reg(ctx->handle, reg, data, len); - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LPS33W_Sensitivity - * @brief These functions convert raw-data into engineering units. - * @{ - * - */ - -float_t lps33w_from_lsb_to_hpa(uint32_t lsb) -{ - return ((float_t)lsb / 4096.0f); -} - -float_t lps33w_from_lsb_to_degc(int16_t lsb) -{ - return ((float_t)lsb / 100.0f); -} - -/** - * @} - * - */ - -/** - * @defgroup LPS33W_data_generation_c - * @brief This section group all the functions concerning data - * generation - * @{ - * - */ - - -/** - * @brief Reset Autozero function.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of reset_az in reg INTERRUPT_CFG - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33w_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - - if (ret == 0) - { - interrupt_cfg.reset_az = val; - ret = lps33w_write_reg(ctx, LPS33W_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - } - - return ret; -} - -/** - * @brief Reset Autozero function.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of reset_az in reg INTERRUPT_CFG - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33w_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - *val = interrupt_cfg.reset_az; - - return ret; -} - -/** - * @brief Enable Autozero function.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of autozero in reg INTERRUPT_CFG - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_autozero_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33w_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - - if (ret == 0) - { - interrupt_cfg.autozero = val; - ret = lps33w_write_reg(ctx, LPS33W_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - } - - return ret; -} - -/** - * @brief Enable Autozero function.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of autozero in reg INTERRUPT_CFG - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_autozero_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33w_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - *val = interrupt_cfg.autozero; - - return ret; -} - -/** - * @brief Reset AutoRifP function.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of reset_arp in reg INTERRUPT_CFG - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_pressure_snap_rst_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33w_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - - if (ret == 0) - { - interrupt_cfg.reset_arp = val; - ret = lps33w_write_reg(ctx, LPS33W_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - } - - return ret; -} - -/** - * @brief Reset AutoRifP function.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of reset_arp in reg INTERRUPT_CFG - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_pressure_snap_rst_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33w_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - *val = interrupt_cfg.reset_arp; - - return ret; -} - -/** - * @brief Enable AutoRifP function.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of autorifp in reg INTERRUPT_CFG. - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33w_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - - if (ret == 0) - { - interrupt_cfg.autorifp = val; - ret = lps33w_write_reg(ctx, LPS33W_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - } - - return ret; -} - -/** - * @brief Enable AutoRifP function.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of autorifp in reg INTERRUPT_CFG - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33w_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - *val = interrupt_cfg.autorifp; - - return ret; -} - -/** - * @brief Block data update.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of bdu in reg CTRL_REG1 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33w_ctrl_reg1_t ctrl_reg1; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - - if (ret == 0) - { - ctrl_reg1.bdu = val; - ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - } - - return ret; -} - -/** - * @brief Block data update.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of bdu in reg CTRL_REG1 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33w_ctrl_reg1_t ctrl_reg1; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - *val = ctrl_reg1.bdu; - - return ret; -} - -/** - * @brief Low-pass bandwidth selection.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of lpfp in reg CTRL_REG1 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_low_pass_filter_mode_set(stmdev_ctx_t *ctx, - lps33w_lpfp_t val) -{ - lps33w_ctrl_reg1_t ctrl_reg1; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - - if (ret == 0) - { - ctrl_reg1.lpfp = (uint8_t)val; - ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - } - - return ret; -} - -/** - * @brief Low-pass bandwidth selection.[get] - * - * @param ctx Read / write interface definitions - * @param val Get the values of lpfp in reg CTRL_REG1 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_low_pass_filter_mode_get(stmdev_ctx_t *ctx, - lps33w_lpfp_t *val) -{ - lps33w_ctrl_reg1_t ctrl_reg1; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - - switch (ctrl_reg1.lpfp) - { - case LPS33W_LPF_ODR_DIV_2: - *val = LPS33W_LPF_ODR_DIV_2; - break; - - case LPS33W_LPF_ODR_DIV_9: - *val = LPS33W_LPF_ODR_DIV_9; - break; - - case LPS33W_LPF_ODR_DIV_20: - *val = LPS33W_LPF_ODR_DIV_20; - break; - - default: - *val = LPS33W_LPF_ODR_DIV_2; - break; - } - - return ret; -} - -/** - * @brief Output data rate selection.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of odr in reg CTRL_REG1 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_data_rate_set(stmdev_ctx_t *ctx, lps33w_odr_t val) -{ - lps33w_ctrl_reg1_t ctrl_reg1; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - - if (ret == 0) - { - ctrl_reg1.odr = (uint8_t)val; - ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - } - - return ret; -} - -/** - * @brief Output data rate selection.[get] - * - * @param ctx Read / write interface definitions - * @param val Get the values of odr in reg CTRL_REG1 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_data_rate_get(stmdev_ctx_t *ctx, lps33w_odr_t *val) -{ - lps33w_ctrl_reg1_t ctrl_reg1; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - - switch (ctrl_reg1.odr) - { - case LPS33W_POWER_DOWN: - *val = LPS33W_POWER_DOWN; - break; - - case LPS33W_ODR_1_Hz: - *val = LPS33W_ODR_1_Hz; - break; - - case LPS33W_ODR_10_Hz: - *val = LPS33W_ODR_10_Hz; - break; - - case LPS33W_ODR_25_Hz: - *val = LPS33W_ODR_25_Hz; - break; - - case LPS33W_ODR_50_Hz: - *val = LPS33W_ODR_50_Hz; - break; - - case LPS33W_ODR_75_Hz: - *val = LPS33W_ODR_75_Hz; - break; - - default: - *val = LPS33W_ODR_1_Hz; - break; - } - - return ret; -} - -/** - * @brief One-shot mode. Device perform a single measure.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of one_shot in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33w_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - - if (ret == 0) - { - ctrl_reg2.one_shot = val; - ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - } - - return ret; -} - -/** - * @brief One-shot mode. Device perform a single measure.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of one_shot in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33w_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - *val = ctrl_reg2.one_shot; - - return ret; -} - -/** - * @brief pressure_ref: The Reference pressure value is a 24-bit data - * expressed as 2’s complement. The value is used when AUTOZERO - * or AUTORIFP function is enabled.[set] - * - * @param ctx Read / write interface definitions - * @param buff Buffer that contains data to write - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_pressure_ref_set(stmdev_ctx_t *ctx, int32_t val) -{ - uint8_t buff[3]; - int32_t ret; - - buff[2] = (uint8_t)((uint32_t)val / 65536U); - buff[1] = (uint8_t)((uint32_t)val - (buff[2] * 65536U)) / 256U; - buff[0] = (uint8_t)((uint32_t)val - (buff[2] * 65536U) - - (buff[1] * 256U)); - ret = lps33w_write_reg(ctx, LPS33W_REF_P_XL, buff, 3); - - return ret; -} - -/** - * @brief pressure_ref: The Reference pressure value is a 24-bit data - * expressed as 2’s complement. The value is used when AUTOZERO - * or AUTORIFP function is enabled.[get] - * - * @param ctx Read / write interface definitions - * @param buff Buffer that stores data read - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_pressure_ref_get(stmdev_ctx_t *ctx, int32_t *val) -{ - uint8_t buff[3]; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_REF_P_XL, buff, 3); - *val = (int32_t)buff[2]; - *val = (*val * 256) + (int32_t)buff[1]; - *val = (*val * 256) + (int32_t)buff[0]; - - return ret; -} - -/** - * @brief The pressure offset value is 16-bit data that can be used to - * implement one-point calibration (OPC) after soldering.[set] - * - * @param ctx Read / write interface definitions - * @param buff Buffer that contains data to write - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val) -{ - uint8_t buff[2]; - int32_t ret; - - buff[1] = (uint8_t)((uint16_t)val / 256U); - buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U)); - ret = lps33w_write_reg(ctx, LPS33W_RPDS_L, buff, 2); - - return ret; -} - -/** - * @brief The pressure offset value is 16-bit data that can be used to - * implement one-point calibration (OPC) after soldering.[get] - * - * @param ctx Read / write interface definitions - * @param buff Buffer that stores data read - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val) -{ - uint8_t buff[2]; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_RPDS_L, buff, 2); - *val = (int16_t)buff[1]; - *val = (*val * 256) + (int16_t)buff[0]; - - return ret; -} - -/** - * @brief Pressure data available.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of p_da in reg STATUS - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_press_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33w_status_t status; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_STATUS, (uint8_t *)&status, 1); - *val = status.p_da; - - return ret; -} - -/** - * @brief Temperature data available.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of t_da in reg STATUS - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33w_status_t status; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_STATUS, (uint8_t *)&status, 1); - *val = status.t_da; - - return ret; -} - -/** - * @brief Pressure data overrun.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of p_or in reg STATUS - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_press_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33w_status_t status; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_STATUS, (uint8_t *)&status, 1); - *val = status.p_or; - - return ret; -} - -/** - * @brief Temperature data overrun.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of t_or in reg STATUS - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33w_status_t status; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_STATUS, (uint8_t *)&status, 1); - *val = status.t_or; - - return ret; -} - -/** - * @brief Pressure output value[get] - * - * @param ctx Read / write interface definitions - * @param buff Buffer that stores data read - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *buff) -{ - uint8_t reg[3]; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_PRESS_OUT_XL, reg, 3); - *buff = reg[2]; - *buff = (*buff * 256) + reg[1]; - *buff = (*buff * 256) + reg[0]; - *buff *= 256; - - return ret; -} - -/** - * @brief temperature_raw: Temperature output value[get] - * - * @param ctx Read / write interface definitions - * @param buff Buffer that stores data read. - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *buff) -{ - uint8_t reg[2]; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_TEMP_OUT_L, (uint8_t *) reg, 2); - *buff = reg[1]; - *buff = (*buff * 256) + reg[0]; - - return ret; -} - -/** - * @brief Low-pass filter reset register. If the LPFP is active, in - * order to avoid the transitory phase, the filter can be - * reset by reading this register before generating pressure - * measurements.[get] - * - * @param ctx Read / write interface definitions - * @param buff Buffer that stores data read - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_low_pass_rst_get(stmdev_ctx_t *ctx, uint8_t *buff) -{ - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_LPFP_RES, (uint8_t *) buff, 1); - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LPS33W_common - * @brief This section group common useful functions - * @{ - * - */ - -/** - * @brief Device Who am I[get] - * - * @param ctx Read / write interface definitions - * @param buff Buffer that stores data read - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) -{ - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_WHO_AM_I, (uint8_t *) buff, 1); - - return ret; -} - -/** - * @brief Software reset. Restore the default values in user registers[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of swreset in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_reset_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33w_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - - if (ret == 0) - { - ctrl_reg2.swreset = val; - ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - } - - return ret; -} - -/** - * @brief Software reset. Restore the default values in user registers[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of swreset in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_reset_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33w_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - *val = ctrl_reg2.swreset; - - return ret; -} - -/** - * @brief Reboot memory content. Reload the calibration parameters.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of boot in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_boot_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33w_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - - if (ret == 0) - { - ctrl_reg2.boot = val; - ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - } - - return ret; -} - -/** - * @brief Reboot memory content. Reload the calibration parameters.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of boot in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_boot_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33w_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - *val = ctrl_reg2.boot; - - return ret; -} - -/** - * @brief Low current mode.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of lc_en in reg RES_CONF - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_low_power_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33w_res_conf_t res_conf; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_RES_CONF, (uint8_t *)&res_conf, 1); - - if (ret == 0) - { - res_conf.lc_en = val; - ret = lps33w_write_reg(ctx, LPS33W_RES_CONF, (uint8_t *)&res_conf, 1); - } - - return ret; -} - -/** - * @brief Low current mode.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of lc_en in reg RES_CONF - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_low_power_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33w_res_conf_t res_conf; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_RES_CONF, (uint8_t *)&res_conf, 1); - *val = res_conf.lc_en; - - return ret; -} - -/** - * @brief If ‘1’ indicates that the Boot (Reboot) phase is running.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of boot_status in reg INT_SOURCE - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_boot_status_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33w_int_source_t int_source; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_INT_SOURCE, (uint8_t *)&int_source, 1); - *val = int_source.boot_status; - - return ret; -} - -/** - * @brief All the status bit, FIFO and data generation[get] - * - * @param ctx Read / write interface definitions - * @param val Structure of registers from FIFO_STATUS to STATUS - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_dev_status_get(stmdev_ctx_t *ctx, - lps33w_dev_stat_t *val) -{ - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_FIFO_STATUS, (uint8_t *) val, 2); - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LPS33W_interrupts - * @brief This section group all the functions that manage interrupts - * @{ - * - */ - -/** - * @brief Enable interrupt generation on pressure low/high event.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of pe in reg INTERRUPT_CFG - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_sign_of_int_threshold_set(stmdev_ctx_t *ctx, - lps33w_pe_t val) -{ - lps33w_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - - if (ret == 0) - { - interrupt_cfg.pe = (uint8_t)val; - ret = lps33w_write_reg(ctx, LPS33W_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - } - - return ret; -} - -/** - * @brief Enable interrupt generation on pressure low/high event.[get] - * - * @param ctx Read / write interface definitions - * @param val Get the values of pe in reg INTERRUPT_CFG - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_sign_of_int_threshold_get(stmdev_ctx_t *ctx, - lps33w_pe_t *val) -{ - lps33w_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - - switch (interrupt_cfg.pe) - { - case LPS33W_NO_THRESHOLD: - *val = LPS33W_NO_THRESHOLD; - break; - - case LPS33W_POSITIVE: - *val = LPS33W_POSITIVE; - break; - - case LPS33W_NEGATIVE: - *val = LPS33W_NEGATIVE; - break; - - case LPS33W_BOTH: - *val = LPS33W_BOTH; - break; - - default: - *val = LPS33W_NO_THRESHOLD; - break; - } - - return ret; -} - -/** - * @brief Interrupt request to the INT_SOURCE (25h) register - * mode (pulsed / latched) [set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of lir in reg INTERRUPT_CFG - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_int_notification_mode_set(stmdev_ctx_t *ctx, - lps33w_lir_t val) -{ - lps33w_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - - if (ret == 0) - { - interrupt_cfg.lir = (uint8_t)val; - ret = lps33w_write_reg(ctx, LPS33W_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - } - - return ret; -} - -/** - * @brief Interrupt request to the INT_SOURCE (25h) register - * mode (pulsed / latched) [get] - * - * @param ctx Read / write interface definitions - * @param val Get the values of lir in reg INTERRUPT_CFG - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_int_notification_mode_get(stmdev_ctx_t *ctx, - lps33w_lir_t *val) -{ - lps33w_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - - switch (interrupt_cfg.lir) - { - case LPS33W_INT_PULSED: - *val = LPS33W_INT_PULSED; - break; - - case LPS33W_INT_LATCHED: - *val = LPS33W_INT_LATCHED; - break; - - default: - *val = LPS33W_INT_PULSED; - break; - } - - return ret; -} - -/** - * @brief Enable interrupt generation.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of diff_en in reg INTERRUPT_CFG - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_int_generation_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33w_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - - if (ret == 0) - { - interrupt_cfg.diff_en = val; - ret = lps33w_write_reg(ctx, LPS33W_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - } - - return ret; -} - -/** - * @brief Enable interrupt generation.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of diff_en in reg INTERRUPT_CFG - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33w_interrupt_cfg_t interrupt_cfg; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_INTERRUPT_CFG, - (uint8_t *)&interrupt_cfg, 1); - *val = interrupt_cfg.diff_en; - - return ret; -} - -/** - * @brief User-defined threshold value for pressure interrupt event[set] - * - * @param ctx Read / write interface definitions - * @param buff Buffer that contains data to write - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_int_threshold_set(stmdev_ctx_t *ctx, uint16_t val) -{ - uint8_t buff[2]; - int32_t ret; - - buff[1] = (uint8_t)(val / 256U); - buff[0] = (uint8_t)(val - (buff[1] * 256U)); - ret = lps33w_write_reg(ctx, LPS33W_THS_P_L, (uint8_t *) buff, 2); - - return ret; -} - -/** - * @brief User-defined threshold value for pressure interrupt event[get] - * - * @param ctx Read / write interface definitions - * @param buff Buffer that stores data read - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_int_threshold_get(stmdev_ctx_t *ctx, uint16_t *val) -{ - uint8_t buff[2]; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_THS_P_L, (uint8_t *) buff, 2); - *val = buff[1]; - *val = (*val * 256) + buff[0]; - - return ret; -} - -/** - * @brief Data signal on INT_DRDY pin control bits.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of int_s in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_int_pin_mode_set(stmdev_ctx_t *ctx, lps33w_int_s_t val) -{ - lps33w_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - - if (ret == 0) - { - ctrl_reg3.int_s = (uint8_t)val; - ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - } - - return ret; -} - -/** - * @brief Data signal on INT_DRDY pin control bits.[get] - * - * @param ctx Read / write interface definitions - * @param val Get the values of int_s in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_int_pin_mode_get(stmdev_ctx_t *ctx, - lps33w_int_s_t *val) -{ - lps33w_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - - switch (ctrl_reg3.int_s) - { - case LPS33W_DRDY_OR_FIFO_FLAGS: - *val = LPS33W_DRDY_OR_FIFO_FLAGS; - break; - - case LPS33W_HIGH_PRES_INT: - *val = LPS33W_HIGH_PRES_INT; - break; - - case LPS33W_LOW_PRES_INT: - *val = LPS33W_LOW_PRES_INT; - break; - - case LPS33W_EVERY_PRES_INT: - *val = LPS33W_EVERY_PRES_INT; - break; - - default: - *val = LPS33W_DRDY_OR_FIFO_FLAGS; - break; - } - - return ret; -} - -/** - * @brief Data-ready signal on INT_DRDY pin.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of drdy in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_drdy_on_int_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33w_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - - if (ret == 0) - { - ctrl_reg3.drdy = val; - ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - } - - return ret; -} - -/** - * @brief Data-ready signal on INT_DRDY pin.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of drdy in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33w_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - *val = ctrl_reg3.drdy; - - return ret; -} - -/** - * @brief FIFO overrun interrupt on INT_DRDY pin.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of f_ovr in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33w_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - - if (ret == 0) - { - ctrl_reg3.f_ovr = val; - ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - } - - return ret; -} - -/** - * @brief FIFO overrun interrupt on INT_DRDY pin.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of f_ovr in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33w_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - *val = ctrl_reg3.f_ovr; - - return ret; -} - -/** - * @brief FIFO watermark status on INT_DRDY pin.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of f_fth in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, - uint8_t val) -{ - lps33w_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - - if (ret == 0) - { - ctrl_reg3.f_fth = val; - ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - } - - return ret; -} - -/** - * @brief FIFO watermark status on INT_DRDY pin.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of f_fth in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - lps33w_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - *val = ctrl_reg3.f_fth; - - return ret; -} - -/** - * @brief FIFO full flag on INT_DRDY pin.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of f_fss5 in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33w_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - - if (ret == 0) - { - ctrl_reg3.f_fss5 = val; - ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - } - - return ret; -} - -/** - * @brief FIFO full flag on INT_DRDY pin.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of f_fss5 in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_fifo_full_on_int_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33w_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - *val = ctrl_reg3.f_fss5; - - return ret; -} - -/** - * @brief Push-pull/open drain selection on interrupt pads.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of pp_od in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_pin_mode_set(stmdev_ctx_t *ctx, lps33w_pp_od_t val) -{ - lps33w_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - - if (ret == 0) - { - ctrl_reg3.pp_od = (uint8_t)val; - ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - } - - return ret; -} - -/** - * @brief Push-pull/open drain selection on interrupt pads.[get] - * - * @param ctx Read / write interface definitions - * @param val Get the values of pp_od in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_pin_mode_get(stmdev_ctx_t *ctx, lps33w_pp_od_t *val) -{ - lps33w_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - - switch (ctrl_reg3.pp_od) - { - case LPS33W_PUSH_PULL: - *val = LPS33W_PUSH_PULL; - break; - - case LPS33W_OPEN_DRAIN: - *val = LPS33W_OPEN_DRAIN; - break; - - default: - *val = LPS33W_PUSH_PULL; - break; - } - - return ret; -} - -/** - * @brief Interrupt active-high/low.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of int_h_l in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_int_polarity_set(stmdev_ctx_t *ctx, - lps33w_int_h_l_t val) -{ - lps33w_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - - if (ret == 0) - { - ctrl_reg3.int_h_l = (uint8_t)val; - ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - } - - return ret; -} - -/** - * @brief Interrupt active-high/low.[get] - * - * @param ctx Read / write interface definitions - * @param val Get the values of int_h_l in reg CTRL_REG3 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_int_polarity_get(stmdev_ctx_t *ctx, - lps33w_int_h_l_t *val) -{ - lps33w_ctrl_reg3_t ctrl_reg3; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1); - - switch (ctrl_reg3.int_h_l) - { - case LPS33W_ACTIVE_HIGH: - *val = LPS33W_ACTIVE_HIGH; - break; - - case LPS33W_ACTIVE_LOW: - *val = LPS33W_ACTIVE_LOW; - break; - - default: - *val = LPS33W_ACTIVE_HIGH; - break; - } - - return ret; -} - -/** - * @brief Interrupt source register[get] - * - * @param ctx Read / write interface definitions - * @param val Register INT_SOURCE - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_int_source_get(stmdev_ctx_t *ctx, - lps33w_int_source_t *val) -{ - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_INT_SOURCE, (uint8_t *) val, 1); - - return ret; -} - -/** - * @brief Differential pressure high interrupt flag.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of ph in reg INT_SOURCE - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_int_on_press_high_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33w_int_source_t int_source; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_INT_SOURCE, (uint8_t *)&int_source, 1); - *val = int_source.ph; - - return ret; -} - -/** - * @brief Differential pressure low interrupt flag.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of pl in reg INT_SOURCE - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_int_on_press_low_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33w_int_source_t int_source; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_INT_SOURCE, (uint8_t *)&int_source, 1); - *val = int_source.pl; - - return ret; -} - -/** - * @brief Interrupt active flag.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of ia in reg INT_SOURCE - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_interrupt_event_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33w_int_source_t int_source; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_INT_SOURCE, (uint8_t *)&int_source, 1); - *val = int_source.ia; - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LPS33W_fifo - * @brief This section group all the functions concerning the - * fifo usage - * @{ - * - */ - -/** - * @brief Stop on FIFO watermark. Enable FIFO watermark level use.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of stop_on_fth in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx, - uint8_t val) -{ - lps33w_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - - if (ret == 0) - { - ctrl_reg2.stop_on_fth = val; - ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - } - - return ret; -} - -/** - * @brief Stop on FIFO watermark. Enable FIFO watermark level use.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of stop_on_fth in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_stop_on_fifo_threshold_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - lps33w_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - *val = ctrl_reg2.stop_on_fth; - - return ret; -} - -/** - * @brief FIFO enable.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of fifo_en in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_fifo_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33w_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - - if (ret == 0) - { - ctrl_reg2.fifo_en = val; - ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - } - - return ret; -} - -/** - * @brief FIFO enable.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of fifo_en in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_fifo_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33w_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - *val = ctrl_reg2.fifo_en; - - return ret; -} - -/** - * @brief FIFO watermark level selection.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of wtm in reg FIFO_CTRL - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33w_fifo_ctrl_t fifo_ctrl; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); - - if (ret == 0) - { - fifo_ctrl.wtm = val; - ret = lps33w_write_reg(ctx, LPS33W_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); - } - - return ret; -} - -/** - * @brief FIFO watermark level selection.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of wtm in reg FIFO_CTRL - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33w_fifo_ctrl_t fifo_ctrl; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); - *val = fifo_ctrl.wtm; - - return ret; -} - -/** - * @brief FIFO mode selection.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of f_mode in reg FIFO_CTRL - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_fifo_mode_set(stmdev_ctx_t *ctx, lps33w_f_mode_t val) -{ - lps33w_fifo_ctrl_t fifo_ctrl; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); - - if (ret == 0) - { - fifo_ctrl.f_mode = (uint8_t)val; - ret = lps33w_write_reg(ctx, LPS33W_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); - } - - return ret; -} - -/** - * @brief FIFO mode selection.[get] - * - * @param ctx Read / write interface definitions - * @param val Get the values of f_mode in reg FIFO_CTRL - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_fifo_mode_get(stmdev_ctx_t *ctx, lps33w_f_mode_t *val) -{ - lps33w_fifo_ctrl_t fifo_ctrl; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1); - - switch (fifo_ctrl.f_mode) - { - case LPS33W_BYPASS_MODE: - *val = LPS33W_BYPASS_MODE; - break; - - case LPS33W_FIFO_MODE: - *val = LPS33W_FIFO_MODE; - break; - - case LPS33W_STREAM_MODE: - *val = LPS33W_STREAM_MODE; - break; - - case LPS33W_STREAM_TO_FIFO_MODE: - *val = LPS33W_STREAM_TO_FIFO_MODE; - break; - - case LPS33W_BYPASS_TO_STREAM_MODE: - *val = LPS33W_BYPASS_TO_STREAM_MODE; - break; - - case LPS33W_DYNAMIC_STREAM_MODE: - *val = LPS33W_DYNAMIC_STREAM_MODE; - break; - - case LPS33W_BYPASS_TO_FIFO_MODE: - *val = LPS33W_BYPASS_TO_FIFO_MODE; - break; - - default: - *val = LPS33W_BYPASS_MODE; - break; - } - - return ret; -} - -/** - * @brief FIFO stored data level.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of fss in reg FIFO_STATUS - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33w_fifo_status_t fifo_status; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_FIFO_STATUS, - (uint8_t *)&fifo_status, 1); - *val = fifo_status.fss; - - return ret; -} - -/** - * @brief FIFO overrun status.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of ovr in reg FIFO_STATUS - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33w_fifo_status_t fifo_status; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_FIFO_STATUS, - (uint8_t *)&fifo_status, 1); - *val = fifo_status.ovr; - - return ret; -} - -/** - * @brief FIFO watermark status.[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of fth_fifo in reg FIFO_STATUS - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33w_fifo_status_t fifo_status; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_FIFO_STATUS, - (uint8_t *)&fifo_status, 1); - *val = fifo_status.fth_fifo; - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LPS33W_serial_interface - * @brief This section group all the functions concerning serial - * interface management - * @{ - * - */ - -/** - * @brief SPI Serial Interface Mode selection.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of sim in reg CTRL_REG1 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_spi_mode_set(stmdev_ctx_t *ctx, lps33w_sim_t val) -{ - lps33w_ctrl_reg1_t ctrl_reg1; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - - if (ret == 0) - { - ctrl_reg1.sim = (uint8_t)val; - ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - } - - return ret; -} - -/** - * @brief SPI Serial Interface Mode selection.[get] - * - * @param ctx Read / write interface definitions - * @param val Get the values of sim in reg CTRL_REG1 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_spi_mode_get(stmdev_ctx_t *ctx, lps33w_sim_t *val) -{ - lps33w_ctrl_reg1_t ctrl_reg1; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1); - - switch (ctrl_reg1.sim) - { - case LPS33W_SPI_4_WIRE: - *val = LPS33W_SPI_4_WIRE; - break; - - case LPS33W_SPI_3_WIRE: - *val = LPS33W_SPI_3_WIRE; - break; - - default: - *val = LPS33W_SPI_4_WIRE; - break; - } - - return ret; -} - -/** - * @brief Disable I2C interface.[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of i2c_dis in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_i2c_interface_set(stmdev_ctx_t *ctx, - lps33w_i2c_dis_t val) -{ - lps33w_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - - if (ret == 0) - { - ctrl_reg2.i2c_dis = (uint8_t)val; - ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - } - - return ret; -} - -/** - * @brief Disable I2C interface.[get] - * - * @param ctx Read / write interface definitions - * @param val Get the values of i2c_dis in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_i2c_interface_get(stmdev_ctx_t *ctx, - lps33w_i2c_dis_t *val) -{ - lps33w_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - - switch (ctrl_reg2.i2c_dis) - { - case LPS33W_I2C_ENABLE: - *val = LPS33W_I2C_ENABLE; - break; - - case LPS33W_I2C_DISABLE: - *val = LPS33W_I2C_DISABLE; - break; - - default: - *val = LPS33W_I2C_ENABLE; - break; - } - - return ret; -} - -/** - * @brief Register address automatically incremented during a - * multiple byte access with a serial interface (I2C or SPI).[set] - * - * @param ctx Read / write interface definitions - * @param val Change the values of if_add_inc in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_auto_add_inc_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lps33w_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - - if (ret == 0) - { - ctrl_reg2.if_add_inc = val; - ret = lps33w_write_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - } - - return ret; -} - -/** - * @brief Register address automatically incremented during a - * multiple byte access with a serial interface (I2C or SPI).[get] - * - * @param ctx Read / write interface definitions - * @param val Change the values of if_add_inc in reg CTRL_REG2 - * @retval Interface status (MANDATORY: return 0 -> no Error). - * - */ -int32_t lps33w_auto_add_inc_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lps33w_ctrl_reg2_t ctrl_reg2; - int32_t ret; - - ret = lps33w_read_reg(ctx, LPS33W_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1); - *val = ctrl_reg2.if_add_inc; - - return ret; -} - -/** - * @} - * - */ - -/** - * @} - * - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lps33w_STdC/driver/lps33w_reg.h b/sensor/stmemsc/lps33w_STdC/driver/lps33w_reg.h deleted file mode 100644 index 42cc4024..00000000 --- a/sensor/stmemsc/lps33w_STdC/driver/lps33w_reg.h +++ /dev/null @@ -1,644 +0,0 @@ -/** - ****************************************************************************** - * @file lps33w_reg.h - * @author Sensors Software Solution Team - * @brief This file contains all the functions prototypes for the - * lps33w_reg.c driver. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef LPS33W_REGS_H -#define LPS33W_REGS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include -#include -#include - -/** @addtogroup LPS33W - * @{ - * - */ - -/** @defgroup Endianness definitions - * @{ - * - */ - -#ifndef DRV_BYTE_ORDER -#ifndef __BYTE_ORDER__ - -#define DRV_LITTLE_ENDIAN 1234 -#define DRV_BIG_ENDIAN 4321 - -/** if _BYTE_ORDER is not defined, choose the endianness of your architecture - * by uncommenting the define which fits your platform endianness - */ -//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN -#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN - -#else /* defined __BYTE_ORDER__ */ - -#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ -#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ -#define DRV_BYTE_ORDER __BYTE_ORDER__ - -#endif /* __BYTE_ORDER__*/ -#endif /* DRV_BYTE_ORDER */ - -/** - * @} - * - */ - -/** @defgroup STMicroelectronics sensors common types - * @{ - * - */ - -#ifndef MEMS_SHARED_TYPES -#define MEMS_SHARED_TYPES - -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t bit0 : 1; - uint8_t bit1 : 1; - uint8_t bit2 : 1; - uint8_t bit3 : 1; - uint8_t bit4 : 1; - uint8_t bit5 : 1; - uint8_t bit6 : 1; - uint8_t bit7 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t bit7 : 1; - uint8_t bit6 : 1; - uint8_t bit5 : 1; - uint8_t bit4 : 1; - uint8_t bit3 : 1; - uint8_t bit2 : 1; - uint8_t bit1 : 1; - uint8_t bit0 : 1; -#endif /* DRV_BYTE_ORDER */ -} bitwise_t; - -#define PROPERTY_DISABLE (0U) -#define PROPERTY_ENABLE (1U) - -/** @addtogroup Interfaces_Functions - * @brief This section provide a set of functions used to read and - * write a generic register of the device. - * MANDATORY: return 0 -> no Error. - * @{ - * - */ - -typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); -typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); -typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); - -typedef struct -{ - /** Component mandatory fields **/ - stmdev_write_ptr write_reg; - stmdev_read_ptr read_reg; - /** Component optional fields **/ - stmdev_mdelay_ptr mdelay; - /** Customizable optional pointer **/ - void *handle; -} stmdev_ctx_t; - -/** - * @} - * - */ - -#endif /* MEMS_SHARED_TYPES */ - -#ifndef MEMS_UCF_SHARED_TYPES -#define MEMS_UCF_SHARED_TYPES - -/** @defgroup Generic address-data structure definition - * @brief This structure is useful to load a predefined configuration - * of a sensor. - * You can create a sensor configuration by your own or using - * Unico / Unicleo tools available on STMicroelectronics - * web site. - * - * @{ - * - */ - -typedef struct -{ - uint8_t address; - uint8_t data; -} ucf_line_t; - -/** - * @} - * - */ - -#endif /* MEMS_UCF_SHARED_TYPES */ - -/** - * @} - * - */ - - -/** @defgroup LSM9DS1_Infos - * @{ - * - */ - -/** I2C Device Address 8 bit format: if SA0=0 -> 0xB9 if SA0=1 -> 0xBB **/ -#define LPS33W_I2C_ADD_H 0xBBU -#define LPS33W_I2C_ADD_L 0xB9U - -/** Device Identification (Who am I) **/ -#define LPS33W_ID 0xB1U - -/** - * @} - * - */ - -#define LPS33W_INTERRUPT_CFG 0x0BU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t pe : 2; /* ple + phe -> pe */ - uint8_t lir : 1; - uint8_t diff_en : 1; - uint8_t reset_az : 1; - uint8_t autozero : 1; - uint8_t reset_arp : 1; - uint8_t autorifp : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t autorifp : 1; - uint8_t reset_arp : 1; - uint8_t autozero : 1; - uint8_t reset_az : 1; - uint8_t diff_en : 1; - uint8_t lir : 1; - uint8_t pe : 2; /* ple + phe -> pe */ -#endif /* DRV_BYTE_ORDER */ -} lps33w_interrupt_cfg_t; - -#define LPS33W_THS_P_L 0x0CU -#define LPS33W_THS_P_H 0x0DU -#define LPS33W_WHO_AM_I 0x0FU -#define LPS33W_CTRL_REG1 0x10U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t sim : 1; - uint8_t bdu : 1; - uint8_t lpfp : 2; /* en_lpfp + lpfp_cfg -> lpfp */ - uint8_t odr : 3; - uint8_t not_used_01 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 1; - uint8_t odr : 3; - uint8_t lpfp : 2; /* en_lpfp + lpfp_cfg -> lpfp */ - uint8_t bdu : 1; - uint8_t sim : 1; -#endif /* DRV_BYTE_ORDER */ -} lps33w_ctrl_reg1_t; - -#define LPS33W_CTRL_REG2 0x11U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t one_shot : 1; - uint8_t not_used_01 : 1; - uint8_t swreset : 1; - uint8_t i2c_dis : 1; - uint8_t if_add_inc : 1; - uint8_t stop_on_fth : 1; - uint8_t fifo_en : 1; - uint8_t boot : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t boot : 1; - uint8_t fifo_en : 1; - uint8_t stop_on_fth : 1; - uint8_t if_add_inc : 1; - uint8_t i2c_dis : 1; - uint8_t swreset : 1; - uint8_t not_used_01 : 1; - uint8_t one_shot : 1; -#endif /* DRV_BYTE_ORDER */ -} lps33w_ctrl_reg2_t; - -#define LPS33W_CTRL_REG3 0x12U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t int_s : 2; - uint8_t drdy : 1; - uint8_t f_ovr : 1; - uint8_t f_fth : 1; - uint8_t f_fss5 : 1; - uint8_t pp_od : 1; - uint8_t int_h_l : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t int_h_l : 1; - uint8_t pp_od : 1; - uint8_t f_fss5 : 1; - uint8_t f_fth : 1; - uint8_t f_ovr : 1; - uint8_t drdy : 1; - uint8_t int_s : 2; -#endif /* DRV_BYTE_ORDER */ -} lps33w_ctrl_reg3_t; - - -#define LPS33W_FIFO_CTRL 0x14U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t wtm : 5; - uint8_t f_mode : 3; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t f_mode : 3; - uint8_t wtm : 5; -#endif /* DRV_BYTE_ORDER */ -} lps33w_fifo_ctrl_t; - -#define LPS33W_REF_P_XL 0x15U -#define LPS33W_REF_P_L 0x16U -#define LPS33W_REF_P_H 0x17U -#define LPS33W_RPDS_L 0x18U -#define LPS33W_RPDS_H 0x19U - -#define LPS33W_RES_CONF 0x1AU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t lc_en : 1; - uint8_t not_used_01 : 7; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 7; - uint8_t lc_en : 1; -#endif /* DRV_BYTE_ORDER */ -} lps33w_res_conf_t; - -#define LPS33W_INT_SOURCE 0x25U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t ph : 1; - uint8_t pl : 1; - uint8_t ia : 1; - uint8_t not_used_01 : 4; - uint8_t boot_status : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t boot_status : 1; - uint8_t not_used_01 : 4; - uint8_t ia : 1; - uint8_t pl : 1; - uint8_t ph : 1; -#endif /* DRV_BYTE_ORDER */ -} lps33w_int_source_t; - -#define LPS33W_FIFO_STATUS 0x26U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t fss : 6; - uint8_t ovr : 1; - uint8_t fth_fifo : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t fth_fifo : 1; - uint8_t ovr : 1; - uint8_t fss : 6; -#endif /* DRV_BYTE_ORDER */ -} lps33w_fifo_status_t; - -#define LPS33W_STATUS 0x27U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t p_da : 1; - uint8_t t_da : 1; - uint8_t not_used_02 : 2; - uint8_t p_or : 1; - uint8_t t_or : 1; - uint8_t not_used_01 : 2; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 2; - uint8_t t_or : 1; - uint8_t p_or : 1; - uint8_t not_used_02 : 2; - uint8_t t_da : 1; - uint8_t p_da : 1; -#endif /* DRV_BYTE_ORDER */ -} lps33w_status_t; - -#define LPS33W_PRESS_OUT_XL 0x28U -#define LPS33W_PRESS_OUT_L 0x29U -#define LPS33W_PRESS_OUT_H 0x2AU -#define LPS33W_TEMP_OUT_L 0x2BU -#define LPS33W_TEMP_OUT_H 0x2CU -#define LPS33W_LPFP_RES 0x33U - -/** - * @defgroup LPS33W_Register_Union - * @brief This union group all the registers having a bit-field - * description. - * This union is useful but it's not needed by the driver. - * - * REMOVING this union you are compliant with: - * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " - * - * @{ - * - */ - -typedef union -{ - lps33w_interrupt_cfg_t interrupt_cfg; - lps33w_ctrl_reg1_t ctrl_reg1; - lps33w_ctrl_reg2_t ctrl_reg2; - lps33w_ctrl_reg3_t ctrl_reg3; - lps33w_fifo_ctrl_t fifo_ctrl; - lps33w_res_conf_t res_conf; - lps33w_int_source_t int_source; - lps33w_fifo_status_t fifo_status; - lps33w_status_t status; - bitwise_t bitwise; - uint8_t byte; -} lps33w_reg_t; - -/** - * @} - * - */ - -#ifndef __weak -#define __weak __attribute__((weak)) -#endif /* __weak */ - -/* - * These are the basic platform dependent I/O routines to read - * and write device registers connected on a standard bus. - * The driver keeps offering a default implementation based on function - * pointers to read/write routines for backward compatibility. - * The __weak directive allows the final application to overwrite - * them with a custom implementation. - */ - -int32_t lps33w_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, - uint16_t len); -int32_t lps33w_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len); - -float_t lps33w_from_lsb_to_hpa(uint32_t lsb); - -float_t lps33w_from_lsb_to_degc(int16_t lsb); - -int32_t lps33w_autozero_rst_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33w_autozero_rst_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33w_autozero_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33w_autozero_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33w_pressure_snap_rst_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33w_pressure_snap_rst_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33w_pressure_snap_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33w_pressure_snap_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33w_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33w_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); - -typedef enum -{ - LPS33W_LPF_ODR_DIV_2 = 0, - LPS33W_LPF_ODR_DIV_9 = 2, - LPS33W_LPF_ODR_DIV_20 = 3, -} lps33w_lpfp_t; -int32_t lps33w_low_pass_filter_mode_set(stmdev_ctx_t *ctx, - lps33w_lpfp_t val); -int32_t lps33w_low_pass_filter_mode_get(stmdev_ctx_t *ctx, - lps33w_lpfp_t *val); - -typedef enum -{ - LPS33W_POWER_DOWN = 0, - LPS33W_ODR_1_Hz = 1, - LPS33W_ODR_10_Hz = 2, - LPS33W_ODR_25_Hz = 3, - LPS33W_ODR_50_Hz = 4, - LPS33W_ODR_75_Hz = 5, -} lps33w_odr_t; -int32_t lps33w_data_rate_set(stmdev_ctx_t *ctx, lps33w_odr_t val); -int32_t lps33w_data_rate_get(stmdev_ctx_t *ctx, lps33w_odr_t *val); - -int32_t lps33w_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33w_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33w_pressure_ref_set(stmdev_ctx_t *ctx, int32_t val); -int32_t lps33w_pressure_ref_get(stmdev_ctx_t *ctx, int32_t *val); - -int32_t lps33w_pressure_offset_set(stmdev_ctx_t *ctx, int16_t val); -int32_t lps33w_pressure_offset_get(stmdev_ctx_t *ctx, int16_t *val); - -int32_t lps33w_press_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33w_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33w_press_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33w_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33w_pressure_raw_get(stmdev_ctx_t *ctx, uint32_t *val); - -int32_t lps33w_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); - -int32_t lps33w_low_pass_rst_get(stmdev_ctx_t *ctx, uint8_t *buff); - -int32_t lps33w_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); - -int32_t lps33w_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33w_reset_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33w_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33w_boot_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33w_low_power_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33w_low_power_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33w_boot_status_get(stmdev_ctx_t *ctx, uint8_t *val); - -typedef struct -{ - lps33w_fifo_status_t fifo_status; - lps33w_status_t status; -} lps33w_dev_stat_t; -int32_t lps33w_dev_status_get(stmdev_ctx_t *ctx, - lps33w_dev_stat_t *val); - -typedef enum -{ - LPS33W_NO_THRESHOLD = 0, - LPS33W_POSITIVE = 1, - LPS33W_NEGATIVE = 2, - LPS33W_BOTH = 3, -} lps33w_pe_t; -int32_t lps33w_sign_of_int_threshold_set(stmdev_ctx_t *ctx, - lps33w_pe_t val); -int32_t lps33w_sign_of_int_threshold_get(stmdev_ctx_t *ctx, - lps33w_pe_t *val); - -typedef enum -{ - LPS33W_INT_PULSED = 0, - LPS33W_INT_LATCHED = 1, -} lps33w_lir_t; -int32_t lps33w_int_notification_mode_set(stmdev_ctx_t *ctx, - lps33w_lir_t val); -int32_t lps33w_int_notification_mode_get(stmdev_ctx_t *ctx, - lps33w_lir_t *val); - -int32_t lps33w_int_generation_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33w_int_generation_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33w_int_threshold_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lps33w_int_threshold_get(stmdev_ctx_t *ctx, uint16_t *val); - -typedef enum -{ - LPS33W_DRDY_OR_FIFO_FLAGS = 0, - LPS33W_HIGH_PRES_INT = 1, - LPS33W_LOW_PRES_INT = 2, - LPS33W_EVERY_PRES_INT = 3, -} lps33w_int_s_t; -int32_t lps33w_int_pin_mode_set(stmdev_ctx_t *ctx, - lps33w_int_s_t val); -int32_t lps33w_int_pin_mode_get(stmdev_ctx_t *ctx, - lps33w_int_s_t *val); - -int32_t lps33w_drdy_on_int_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33w_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33w_fifo_ovr_on_int_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33w_fifo_ovr_on_int_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33w_fifo_threshold_on_int_set(stmdev_ctx_t *ctx, - uint8_t val); -int32_t lps33w_fifo_threshold_on_int_get(stmdev_ctx_t *ctx, - uint8_t *val); - -int32_t lps33w_fifo_full_on_int_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33w_fifo_full_on_int_get(stmdev_ctx_t *ctx, uint8_t *val); - -typedef enum -{ - LPS33W_PUSH_PULL = 0, - LPS33W_OPEN_DRAIN = 1, -} lps33w_pp_od_t; -int32_t lps33w_pin_mode_set(stmdev_ctx_t *ctx, lps33w_pp_od_t val); -int32_t lps33w_pin_mode_get(stmdev_ctx_t *ctx, lps33w_pp_od_t *val); - -typedef enum -{ - LPS33W_ACTIVE_HIGH = 0, - LPS33W_ACTIVE_LOW = 1, -} lps33w_int_h_l_t; -int32_t lps33w_int_polarity_set(stmdev_ctx_t *ctx, - lps33w_int_h_l_t val); -int32_t lps33w_int_polarity_get(stmdev_ctx_t *ctx, - lps33w_int_h_l_t *val); - -int32_t lps33w_int_source_get(stmdev_ctx_t *ctx, - lps33w_int_source_t *val); - -int32_t lps33w_int_on_press_high_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33w_int_on_press_low_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33w_interrupt_event_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33w_stop_on_fifo_threshold_set(stmdev_ctx_t *ctx, - uint8_t val); -int32_t lps33w_stop_on_fifo_threshold_get(stmdev_ctx_t *ctx, - uint8_t *val); - -int32_t lps33w_fifo_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33w_fifo_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33w_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33w_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); - -typedef enum -{ - LPS33W_BYPASS_MODE = 0, - LPS33W_FIFO_MODE = 1, - LPS33W_STREAM_MODE = 2, - LPS33W_STREAM_TO_FIFO_MODE = 3, - LPS33W_BYPASS_TO_STREAM_MODE = 4, - LPS33W_DYNAMIC_STREAM_MODE = 6, - LPS33W_BYPASS_TO_FIFO_MODE = 7, -} lps33w_f_mode_t; -int32_t lps33w_fifo_mode_set(stmdev_ctx_t *ctx, lps33w_f_mode_t val); -int32_t lps33w_fifo_mode_get(stmdev_ctx_t *ctx, lps33w_f_mode_t *val); - -int32_t lps33w_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33w_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lps33w_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val); - -typedef enum -{ - LPS33W_SPI_4_WIRE = 0, - LPS33W_SPI_3_WIRE = 1, -} lps33w_sim_t; -int32_t lps33w_spi_mode_set(stmdev_ctx_t *ctx, lps33w_sim_t val); -int32_t lps33w_spi_mode_get(stmdev_ctx_t *ctx, lps33w_sim_t *val); - -typedef enum -{ - LPS33W_I2C_ENABLE = 0, - LPS33W_I2C_DISABLE = 1, -} lps33w_i2c_dis_t; -int32_t lps33w_i2c_interface_set(stmdev_ctx_t *ctx, - lps33w_i2c_dis_t val); -int32_t lps33w_i2c_interface_get(stmdev_ctx_t *ctx, - lps33w_i2c_dis_t *val); - -int32_t lps33w_auto_add_inc_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lps33w_auto_add_inc_get(stmdev_ctx_t *ctx, uint8_t *val); - -/** - *@} - * - */ - -#ifdef __cplusplus -} -#endif - -#endif /* LPS33W_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.c b/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.c index 7b1c4624..ae3241f0 100644 --- a/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.c +++ b/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm303agr_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm303agr_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lsm303agr_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm303agr_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm303agr_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -190,7 +200,7 @@ float_t lsm303agr_from_lsb_to_mgauss(int16_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_temp_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_temp_status_reg_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -208,7 +218,7 @@ int32_t lsm303agr_temp_status_reg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303agr_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_status_reg_aux_a_t status_reg_aux_a; int32_t ret; @@ -228,7 +238,7 @@ int32_t lsm303agr_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303agr_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_status_reg_aux_a_t status_reg_aux_a; int32_t ret; @@ -248,7 +258,7 @@ int32_t lsm303agr_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm303agr_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -268,7 +278,7 @@ int32_t lsm303agr_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_temperature_meas_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_temperature_meas_set(const stmdev_ctx_t *ctx, lsm303agr_temp_en_a_t val) { lsm303agr_temp_cfg_reg_a_t temp_cfg_reg_a; @@ -295,7 +305,7 @@ int32_t lsm303agr_temperature_meas_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_temperature_meas_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_temperature_meas_get(const stmdev_ctx_t *ctx, lsm303agr_temp_en_a_t *val) { lsm303agr_temp_cfg_reg_a_t temp_cfg_reg_a; @@ -331,7 +341,7 @@ int32_t lsm303agr_temperature_meas_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_operating_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_operating_mode_set(const stmdev_ctx_t *ctx, lsm303agr_op_md_a_t val) { lsm303agr_ctrl_reg1_a_t ctrl_reg1_a; @@ -393,7 +403,7 @@ int32_t lsm303agr_xl_operating_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_operating_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_operating_mode_get(const stmdev_ctx_t *ctx, lsm303agr_op_md_a_t *val) { lsm303agr_ctrl_reg4_a_t ctrl_reg4_a; @@ -435,7 +445,7 @@ int32_t lsm303agr_xl_operating_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm303agr_odr_a_t val) { lsm303agr_ctrl_reg1_a_t ctrl_reg1_a; @@ -462,7 +472,7 @@ int32_t lsm303agr_xl_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm303agr_odr_a_t *val) { lsm303agr_ctrl_reg1_a_t ctrl_reg1_a; @@ -529,7 +539,7 @@ int32_t lsm303agr_xl_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_high_pass_on_outputs_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_high_pass_on_outputs_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303agr_ctrl_reg2_a_t ctrl_reg2_a; @@ -557,7 +567,7 @@ int32_t lsm303agr_xl_high_pass_on_outputs_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_high_pass_on_outputs_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_high_pass_on_outputs_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_ctrl_reg2_a_t ctrl_reg2_a; @@ -585,7 +595,7 @@ int32_t lsm303agr_xl_high_pass_on_outputs_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_high_pass_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_high_pass_bandwidth_set(const stmdev_ctx_t *ctx, lsm303agr_hpcf_a_t val) { lsm303agr_ctrl_reg2_a_t ctrl_reg2_a; @@ -619,7 +629,7 @@ int32_t lsm303agr_xl_high_pass_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_high_pass_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_high_pass_bandwidth_get(const stmdev_ctx_t *ctx, lsm303agr_hpcf_a_t *val) { lsm303agr_ctrl_reg2_a_t ctrl_reg2_a; @@ -662,7 +672,7 @@ int32_t lsm303agr_xl_high_pass_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_high_pass_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_high_pass_mode_set(const stmdev_ctx_t *ctx, lsm303agr_hpm_a_t val) { lsm303agr_ctrl_reg2_a_t ctrl_reg2_a; @@ -689,7 +699,7 @@ int32_t lsm303agr_xl_high_pass_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_high_pass_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_high_pass_mode_get(const stmdev_ctx_t *ctx, lsm303agr_hpm_a_t *val) { lsm303agr_ctrl_reg2_a_t ctrl_reg2_a; @@ -732,7 +742,7 @@ int32_t lsm303agr_xl_high_pass_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm303agr_fs_a_t val) { lsm303agr_ctrl_reg4_a_t ctrl_reg4_a; @@ -759,7 +769,7 @@ int32_t lsm303agr_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm303agr_fs_a_t *val) { lsm303agr_ctrl_reg4_a_t ctrl_reg4_a; @@ -802,7 +812,7 @@ int32_t lsm303agr_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_block_data_update_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303agr_ctrl_reg4_a_t ctrl_reg4_a; @@ -829,7 +839,7 @@ int32_t lsm303agr_xl_block_data_update_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_ctrl_reg4_a_t ctrl_reg4_a; @@ -851,7 +861,7 @@ int32_t lsm303agr_xl_block_data_update_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_filter_reference_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_filter_reference_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -870,7 +880,7 @@ int32_t lsm303agr_xl_filter_reference_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_filter_reference_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_filter_reference_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -888,7 +898,7 @@ int32_t lsm303agr_xl_filter_reference_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303agr_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_status_reg_a_t status_reg_a; int32_t ret; @@ -908,7 +918,7 @@ int32_t lsm303agr_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303agr_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_status_reg_a_t status_reg_a; int32_t ret; @@ -928,7 +938,7 @@ int32_t lsm303agr_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -960,7 +970,7 @@ int32_t lsm303agr_acceleration_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_user_offset_set(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm303agr_mag_user_offset_set(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -991,7 +1001,7 @@ int32_t lsm303agr_mag_user_offset_set(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_user_offset_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm303agr_mag_user_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1015,7 +1025,7 @@ int32_t lsm303agr_mag_user_offset_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_operating_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_operating_mode_set(const stmdev_ctx_t *ctx, lsm303agr_md_m_t val) { lsm303agr_cfg_reg_a_m_t cfg_reg_a_m; @@ -1042,7 +1052,7 @@ int32_t lsm303agr_mag_operating_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_operating_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_operating_mode_get(const stmdev_ctx_t *ctx, lsm303agr_md_m_t *val) { lsm303agr_cfg_reg_a_m_t cfg_reg_a_m; @@ -1081,7 +1091,7 @@ int32_t lsm303agr_mag_operating_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_data_rate_set(const stmdev_ctx_t *ctx, lsm303agr_mg_odr_m_t val) { lsm303agr_cfg_reg_a_m_t cfg_reg_a_m; @@ -1108,7 +1118,7 @@ int32_t lsm303agr_mag_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_data_rate_get(const stmdev_ctx_t *ctx, lsm303agr_mg_odr_m_t *val) { lsm303agr_cfg_reg_a_m_t cfg_reg_a_m; @@ -1151,7 +1161,7 @@ int32_t lsm303agr_mag_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_power_mode_set(const stmdev_ctx_t *ctx, lsm303agr_lp_m_t val) { lsm303agr_cfg_reg_a_m_t cfg_reg_a_m; @@ -1178,7 +1188,7 @@ int32_t lsm303agr_mag_power_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_power_mode_get(const stmdev_ctx_t *ctx, lsm303agr_lp_m_t *val) { lsm303agr_cfg_reg_a_m_t cfg_reg_a_m; @@ -1213,7 +1223,7 @@ int32_t lsm303agr_mag_power_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_offset_temp_comp_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_offset_temp_comp_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303agr_cfg_reg_a_m_t cfg_reg_a_m; @@ -1240,7 +1250,7 @@ int32_t lsm303agr_mag_offset_temp_comp_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_offset_temp_comp_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_offset_temp_comp_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_cfg_reg_a_m_t cfg_reg_a_m; @@ -1261,7 +1271,7 @@ int32_t lsm303agr_mag_offset_temp_comp_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_low_pass_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_low_pass_bandwidth_set(const stmdev_ctx_t *ctx, lsm303agr_lpf_m_t val) { lsm303agr_cfg_reg_b_m_t cfg_reg_b_m; @@ -1288,7 +1298,7 @@ int32_t lsm303agr_mag_low_pass_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_low_pass_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_low_pass_bandwidth_get(const stmdev_ctx_t *ctx, lsm303agr_lpf_m_t *val) { lsm303agr_cfg_reg_b_m_t cfg_reg_b_m; @@ -1323,7 +1333,7 @@ int32_t lsm303agr_mag_low_pass_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_set_rst_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_set_rst_mode_set(const stmdev_ctx_t *ctx, lsm303agr_set_rst_m_t val) { lsm303agr_cfg_reg_b_m_t cfg_reg_b_m; @@ -1350,7 +1360,7 @@ int32_t lsm303agr_mag_set_rst_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_set_rst_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_set_rst_mode_get(const stmdev_ctx_t *ctx, lsm303agr_set_rst_m_t *val) { lsm303agr_cfg_reg_b_m_t cfg_reg_b_m; @@ -1395,7 +1405,7 @@ int32_t lsm303agr_mag_set_rst_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_set_rst_sensor_single_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_set_rst_sensor_single_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303agr_cfg_reg_b_m_t cfg_reg_b_m; @@ -1429,7 +1439,7 @@ int32_t lsm303agr_mag_set_rst_sensor_single_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_set_rst_sensor_single_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_set_rst_sensor_single_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_cfg_reg_b_m_t cfg_reg_b_m; @@ -1450,7 +1460,7 @@ int32_t lsm303agr_mag_set_rst_sensor_single_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_block_data_update_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303agr_cfg_reg_c_m_t cfg_reg_c_m; @@ -1477,7 +1487,7 @@ int32_t lsm303agr_mag_block_data_update_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_cfg_reg_c_m_t cfg_reg_c_m; @@ -1498,7 +1508,7 @@ int32_t lsm303agr_mag_block_data_update_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303agr_mag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_status_reg_m_t status_reg_m; int32_t ret; @@ -1518,7 +1528,7 @@ int32_t lsm303agr_mag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303agr_mag_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_status_reg_m_t status_reg_m; int32_t ret; @@ -1538,7 +1548,7 @@ int32_t lsm303agr_mag_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm303agr_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1574,7 +1584,7 @@ int32_t lsm303agr_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm303agr_xl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1591,7 +1601,7 @@ int32_t lsm303agr_xl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_self_test_set(const stmdev_ctx_t *ctx, lsm303agr_st_a_t val) { lsm303agr_ctrl_reg4_a_t ctrl_reg4_a; @@ -1618,7 +1628,7 @@ int32_t lsm303agr_xl_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_self_test_get(const stmdev_ctx_t *ctx, lsm303agr_st_a_t *val) { lsm303agr_ctrl_reg4_a_t ctrl_reg4_a; @@ -1657,7 +1667,7 @@ int32_t lsm303agr_xl_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_data_format_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_data_format_set(const stmdev_ctx_t *ctx, lsm303agr_ble_a_t val) { lsm303agr_ctrl_reg4_a_t ctrl_reg4_a; @@ -1684,7 +1694,7 @@ int32_t lsm303agr_xl_data_format_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_data_format_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_data_format_get(const stmdev_ctx_t *ctx, lsm303agr_ble_a_t *val) { lsm303agr_ctrl_reg4_a_t ctrl_reg4_a; @@ -1719,7 +1729,7 @@ int32_t lsm303agr_xl_data_format_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303agr_xl_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303agr_ctrl_reg5_a_t ctrl_reg5_a; int32_t ret; @@ -1745,7 +1755,7 @@ int32_t lsm303agr_xl_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303agr_xl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_ctrl_reg5_a_t ctrl_reg5_a; int32_t ret; @@ -1765,7 +1775,7 @@ int32_t lsm303agr_xl_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_status_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_status_get(const stmdev_ctx_t *ctx, lsm303agr_status_reg_a_t *val) { int32_t ret; @@ -1783,7 +1793,7 @@ int32_t lsm303agr_xl_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm303agr_mag_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1800,7 +1810,7 @@ int32_t lsm303agr_mag_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303agr_mag_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303agr_cfg_reg_a_m_t cfg_reg_a_m; int32_t ret; @@ -1826,7 +1836,7 @@ int32_t lsm303agr_mag_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303agr_mag_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_cfg_reg_a_m_t cfg_reg_a_m; int32_t ret; @@ -1846,7 +1856,7 @@ int32_t lsm303agr_mag_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303agr_mag_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303agr_cfg_reg_a_m_t cfg_reg_a_m; int32_t ret; @@ -1872,7 +1882,7 @@ int32_t lsm303agr_mag_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303agr_mag_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_cfg_reg_a_m_t cfg_reg_a_m; int32_t ret; @@ -1892,7 +1902,7 @@ int32_t lsm303agr_mag_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_self_test_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303agr_mag_self_test_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303agr_cfg_reg_c_m_t cfg_reg_c_m; int32_t ret; @@ -1918,7 +1928,7 @@ int32_t lsm303agr_mag_self_test_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_self_test_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303agr_mag_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_cfg_reg_c_m_t cfg_reg_c_m; int32_t ret; @@ -1938,7 +1948,7 @@ int32_t lsm303agr_mag_self_test_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_data_format_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_data_format_set(const stmdev_ctx_t *ctx, lsm303agr_ble_m_t val) { lsm303agr_cfg_reg_c_m_t cfg_reg_c_m; @@ -1965,7 +1975,7 @@ int32_t lsm303agr_mag_data_format_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_data_format_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_data_format_get(const stmdev_ctx_t *ctx, lsm303agr_ble_m_t *val) { lsm303agr_cfg_reg_c_m_t cfg_reg_c_m; @@ -2000,7 +2010,7 @@ int32_t lsm303agr_mag_data_format_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_status_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_status_get(const stmdev_ctx_t *ctx, lsm303agr_status_reg_m_t *val) { int32_t ret; @@ -2031,7 +2041,7 @@ int32_t lsm303agr_mag_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_int1_gen_conf_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int1_gen_conf_set(const stmdev_ctx_t *ctx, lsm303agr_int1_cfg_a_t *val) { int32_t ret; @@ -2049,7 +2059,7 @@ int32_t lsm303agr_xl_int1_gen_conf_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_int1_gen_conf_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int1_gen_conf_get(const stmdev_ctx_t *ctx, lsm303agr_int1_cfg_a_t *val) { int32_t ret; @@ -2067,7 +2077,7 @@ int32_t lsm303agr_xl_int1_gen_conf_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_int1_gen_source_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int1_gen_source_get(const stmdev_ctx_t *ctx, lsm303agr_int1_src_a_t *val) { int32_t ret; @@ -2087,7 +2097,7 @@ int32_t lsm303agr_xl_int1_gen_source_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_int1_gen_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int1_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303agr_int1_ths_a_t int1_ths_a; @@ -2116,7 +2126,7 @@ int32_t lsm303agr_xl_int1_gen_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_int1_gen_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int1_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_int1_ths_a_t int1_ths_a; @@ -2138,7 +2148,7 @@ int32_t lsm303agr_xl_int1_gen_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_int1_gen_duration_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int1_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303agr_int1_duration_a_t int1_duration_a; @@ -2166,7 +2176,7 @@ int32_t lsm303agr_xl_int1_gen_duration_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_int1_gen_duration_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int1_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_int1_duration_a_t int1_duration_a; @@ -2200,7 +2210,7 @@ int32_t lsm303agr_xl_int1_gen_duration_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_int2_gen_conf_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int2_gen_conf_set(const stmdev_ctx_t *ctx, lsm303agr_int2_cfg_a_t *val) { int32_t ret; @@ -2218,7 +2228,7 @@ int32_t lsm303agr_xl_int2_gen_conf_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_int2_gen_conf_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int2_gen_conf_get(const stmdev_ctx_t *ctx, lsm303agr_int2_cfg_a_t *val) { int32_t ret; @@ -2236,7 +2246,7 @@ int32_t lsm303agr_xl_int2_gen_conf_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_int2_gen_source_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int2_gen_source_get(const stmdev_ctx_t *ctx, lsm303agr_int2_src_a_t *val) { int32_t ret; @@ -2256,7 +2266,7 @@ int32_t lsm303agr_xl_int2_gen_source_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_int2_gen_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int2_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303agr_int2_ths_a_t int2_ths_a; @@ -2285,7 +2295,7 @@ int32_t lsm303agr_xl_int2_gen_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_int2_gen_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int2_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_int2_ths_a_t int2_ths_a; @@ -2307,7 +2317,7 @@ int32_t lsm303agr_xl_int2_gen_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_int2_gen_duration_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int2_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303agr_int2_duration_a_t int2_duration_a; @@ -2335,7 +2345,7 @@ int32_t lsm303agr_xl_int2_gen_duration_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_int2_gen_duration_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int2_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_int2_duration_a_t int2_duration_a; @@ -2369,7 +2379,7 @@ int32_t lsm303agr_xl_int2_gen_duration_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_high_pass_int_conf_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_high_pass_int_conf_set(const stmdev_ctx_t *ctx, lsm303agr_hp_a_t val) { lsm303agr_ctrl_reg2_a_t ctrl_reg2_a; @@ -2396,7 +2406,7 @@ int32_t lsm303agr_xl_high_pass_int_conf_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_high_pass_int_conf_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_high_pass_int_conf_get(const stmdev_ctx_t *ctx, lsm303agr_hp_a_t *val) { lsm303agr_ctrl_reg2_a_t ctrl_reg2_a; @@ -2455,7 +2465,7 @@ int32_t lsm303agr_xl_high_pass_int_conf_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_pin_int1_config_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_pin_int1_config_set(const stmdev_ctx_t *ctx, lsm303agr_ctrl_reg3_a_t *val) { int32_t ret; @@ -2473,7 +2483,7 @@ int32_t lsm303agr_xl_pin_int1_config_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_pin_int1_config_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_pin_int1_config_get(const stmdev_ctx_t *ctx, lsm303agr_ctrl_reg3_a_t *val) { int32_t ret; @@ -2492,7 +2502,7 @@ int32_t lsm303agr_xl_pin_int1_config_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int2_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303agr_ctrl_reg5_a_t ctrl_reg5_a; @@ -2520,7 +2530,7 @@ int32_t lsm303agr_xl_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int2_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_ctrl_reg5_a_t ctrl_reg5_a; @@ -2543,7 +2553,7 @@ int32_t lsm303agr_xl_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_int2pin_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int2pin_notification_mode_set(const stmdev_ctx_t *ctx, lsm303agr_lir_int2_a_t val) { lsm303agr_ctrl_reg5_a_t ctrl_reg5_a; @@ -2572,7 +2582,7 @@ int32_t lsm303agr_xl_int2pin_notification_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_int2pin_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int2pin_notification_mode_get(const stmdev_ctx_t *ctx, lsm303agr_lir_int2_a_t *val) { lsm303agr_ctrl_reg5_a_t ctrl_reg5_a; @@ -2608,7 +2618,7 @@ int32_t lsm303agr_xl_int2pin_notification_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int1_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303agr_ctrl_reg5_a_t ctrl_reg5_a; @@ -2636,7 +2646,7 @@ int32_t lsm303agr_xl_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int1_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_ctrl_reg5_a_t ctrl_reg5_a; @@ -2659,7 +2669,7 @@ int32_t lsm303agr_xl_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_int1pin_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int1pin_notification_mode_set(const stmdev_ctx_t *ctx, lsm303agr_lir_int1_a_t val) { lsm303agr_ctrl_reg5_a_t ctrl_reg5_a; @@ -2688,7 +2698,7 @@ int32_t lsm303agr_xl_int1pin_notification_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_int1pin_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int1pin_notification_mode_get(const stmdev_ctx_t *ctx, lsm303agr_lir_int1_a_t *val) { lsm303agr_ctrl_reg5_a_t ctrl_reg5_a; @@ -2723,7 +2733,7 @@ int32_t lsm303agr_xl_int1pin_notification_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_pin_int2_config_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_pin_int2_config_set(const stmdev_ctx_t *ctx, lsm303agr_ctrl_reg6_a_t *val) { int32_t ret; @@ -2741,7 +2751,7 @@ int32_t lsm303agr_xl_pin_int2_config_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_pin_int2_config_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_pin_int2_config_get(const stmdev_ctx_t *ctx, lsm303agr_ctrl_reg6_a_t *val) { int32_t ret; @@ -2774,7 +2784,7 @@ int32_t lsm303agr_xl_pin_int2_config_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_offset_int_conf_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_offset_int_conf_set(const stmdev_ctx_t *ctx, lsm303agr_int_on_dataoff_m_t val) { lsm303agr_cfg_reg_b_m_t cfg_reg_b_m; @@ -2803,7 +2813,7 @@ int32_t lsm303agr_mag_offset_int_conf_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_offset_int_conf_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_offset_int_conf_get(const stmdev_ctx_t *ctx, lsm303agr_int_on_dataoff_m_t *val) { lsm303agr_cfg_reg_b_m_t cfg_reg_b_m; @@ -2838,7 +2848,7 @@ int32_t lsm303agr_mag_offset_int_conf_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_drdy_on_pin_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303agr_mag_drdy_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303agr_cfg_reg_c_m_t cfg_reg_c_m; int32_t ret; @@ -2864,7 +2874,7 @@ int32_t lsm303agr_mag_drdy_on_pin_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_drdy_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303agr_mag_drdy_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_cfg_reg_c_m_t cfg_reg_c_m; int32_t ret; @@ -2884,7 +2894,7 @@ int32_t lsm303agr_mag_drdy_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_int_on_pin_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303agr_mag_int_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303agr_cfg_reg_c_m_t cfg_reg_c_m; int32_t ret; @@ -2910,7 +2920,7 @@ int32_t lsm303agr_mag_int_on_pin_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_int_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303agr_mag_int_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_cfg_reg_c_m_t cfg_reg_c_m; int32_t ret; @@ -2930,7 +2940,7 @@ int32_t lsm303agr_mag_int_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_int_gen_conf_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_int_gen_conf_set(const stmdev_ctx_t *ctx, lsm303agr_int_crtl_reg_m_t *val) { int32_t ret; @@ -2949,7 +2959,7 @@ int32_t lsm303agr_mag_int_gen_conf_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_int_gen_conf_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_int_gen_conf_get(const stmdev_ctx_t *ctx, lsm303agr_int_crtl_reg_m_t *val) { int32_t ret; @@ -2968,7 +2978,7 @@ int32_t lsm303agr_mag_int_gen_conf_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_int_gen_source_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_int_gen_source_get(const stmdev_ctx_t *ctx, lsm303agr_int_source_reg_m_t *val) { int32_t ret; @@ -2990,8 +3000,8 @@ int32_t lsm303agr_mag_int_gen_source_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_int_gen_treshold_set(stmdev_ctx_t *ctx, - int16_t val) +int32_t lsm303agr_mag_int_gen_threshold_set(const stmdev_ctx_t *ctx, + int16_t val) { uint8_t buff[6]; int32_t ret; @@ -3014,8 +3024,8 @@ int32_t lsm303agr_mag_int_gen_treshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_int_gen_treshold_get(stmdev_ctx_t *ctx, - int16_t *val) +int32_t lsm303agr_mag_int_gen_threshold_get(const stmdev_ctx_t *ctx, + int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -3048,7 +3058,7 @@ int32_t lsm303agr_mag_int_gen_treshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_fifo_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303agr_xl_fifo_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303agr_ctrl_reg5_a_t ctrl_reg5_a; int32_t ret; @@ -3074,7 +3084,7 @@ int32_t lsm303agr_xl_fifo_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_fifo_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303agr_xl_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_ctrl_reg5_a_t ctrl_reg5_a; int32_t ret; @@ -3094,7 +3104,7 @@ int32_t lsm303agr_xl_fifo_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_fifo_watermark_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303agr_fifo_ctrl_reg_a_t fifo_ctrl_reg_a; @@ -3121,7 +3131,7 @@ int32_t lsm303agr_xl_fifo_watermark_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_fifo_watermark_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_fifo_ctrl_reg_a_t fifo_ctrl_reg_a; @@ -3142,7 +3152,7 @@ int32_t lsm303agr_xl_fifo_watermark_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_fifo_trigger_event_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_fifo_trigger_event_set(const stmdev_ctx_t *ctx, lsm303agr_tr_a_t val) { lsm303agr_fifo_ctrl_reg_a_t fifo_ctrl_reg_a; @@ -3169,7 +3179,7 @@ int32_t lsm303agr_xl_fifo_trigger_event_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_fifo_trigger_event_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_fifo_trigger_event_get(const stmdev_ctx_t *ctx, lsm303agr_tr_a_t *val) { lsm303agr_fifo_ctrl_reg_a_t fifo_ctrl_reg_a; @@ -3204,7 +3214,7 @@ int32_t lsm303agr_xl_fifo_trigger_event_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_fifo_mode_set(const stmdev_ctx_t *ctx, lsm303agr_fm_a_t val) { lsm303agr_fifo_ctrl_reg_a_t fifo_ctrl_reg_a; @@ -3231,7 +3241,7 @@ int32_t lsm303agr_xl_fifo_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_fifo_mode_get(const stmdev_ctx_t *ctx, lsm303agr_fm_a_t *val) { lsm303agr_fifo_ctrl_reg_a_t fifo_ctrl_reg_a; @@ -3274,7 +3284,7 @@ int32_t lsm303agr_xl_fifo_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_fifo_status_get(const stmdev_ctx_t *ctx, lsm303agr_fifo_src_reg_a_t *val) { int32_t ret; @@ -3293,7 +3303,7 @@ int32_t lsm303agr_xl_fifo_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_fifo_data_level_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_fifo_src_reg_a_t fifo_src_reg_a; @@ -3314,7 +3324,7 @@ int32_t lsm303agr_xl_fifo_data_level_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_fifo_empty_flag_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_fifo_src_reg_a_t fifo_src_reg_a; @@ -3335,7 +3345,7 @@ int32_t lsm303agr_xl_fifo_empty_flag_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_fifo_ovr_flag_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_fifo_src_reg_a_t fifo_src_reg_a; @@ -3356,7 +3366,7 @@ int32_t lsm303agr_xl_fifo_ovr_flag_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_fifo_fth_flag_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_fifo_src_reg_a_t fifo_src_reg_a; @@ -3390,7 +3400,7 @@ int32_t lsm303agr_xl_fifo_fth_flag_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_tap_conf_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_tap_conf_set(const stmdev_ctx_t *ctx, lsm303agr_click_cfg_a_t *val) { int32_t ret; @@ -3408,7 +3418,7 @@ int32_t lsm303agr_tap_conf_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_tap_conf_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_tap_conf_get(const stmdev_ctx_t *ctx, lsm303agr_click_cfg_a_t *val) { int32_t ret; @@ -3426,7 +3436,7 @@ int32_t lsm303agr_tap_conf_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_tap_source_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_tap_source_get(const stmdev_ctx_t *ctx, lsm303agr_click_src_a_t *val) { int32_t ret; @@ -3445,7 +3455,7 @@ int32_t lsm303agr_tap_source_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303agr_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303agr_click_ths_a_t click_ths_a; int32_t ret; @@ -3472,7 +3482,7 @@ int32_t lsm303agr_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303agr_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_click_ths_a_t click_ths_a; int32_t ret; @@ -3494,7 +3504,7 @@ int32_t lsm303agr_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303agr_shock_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303agr_time_limit_a_t time_limit_a; int32_t ret; @@ -3522,7 +3532,7 @@ int32_t lsm303agr_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303agr_shock_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_time_limit_a_t time_limit_a; int32_t ret; @@ -3545,7 +3555,7 @@ int32_t lsm303agr_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303agr_quiet_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303agr_time_latency_a_t time_latency_a; int32_t ret; @@ -3573,7 +3583,7 @@ int32_t lsm303agr_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303agr_quiet_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_time_latency_a_t time_latency_a; int32_t ret; @@ -3596,7 +3606,7 @@ int32_t lsm303agr_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_double_tap_timeout_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_double_tap_timeout_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303agr_time_window_a_t time_window_a; @@ -3626,7 +3636,7 @@ int32_t lsm303agr_double_tap_timeout_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_double_tap_timeout_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_double_tap_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_time_window_a_t time_window_a; @@ -3662,7 +3672,7 @@ int32_t lsm303agr_double_tap_timeout_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303agr_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303agr_act_ths_a_t act_ths_a; int32_t ret; @@ -3690,7 +3700,7 @@ int32_t lsm303agr_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303agr_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_act_ths_a_t act_ths_a; int32_t ret; @@ -3710,7 +3720,7 @@ int32_t lsm303agr_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303agr_act_timeout_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303agr_act_dur_a_t act_dur_a; int32_t ret; @@ -3736,7 +3746,7 @@ int32_t lsm303agr_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303agr_act_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303agr_act_dur_a_t act_dur_a; int32_t ret; @@ -3769,7 +3779,7 @@ int32_t lsm303agr_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_spi_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_spi_mode_set(const stmdev_ctx_t *ctx, lsm303agr_sim_a_t val) { lsm303agr_ctrl_reg4_a_t ctrl_reg4_a; @@ -3796,7 +3806,7 @@ int32_t lsm303agr_xl_spi_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_xl_spi_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_spi_mode_get(const stmdev_ctx_t *ctx, lsm303agr_sim_a_t *val) { lsm303agr_ctrl_reg4_a_t ctrl_reg4_a; @@ -3831,7 +3841,7 @@ int32_t lsm303agr_xl_spi_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_i2c_interface_set(const stmdev_ctx_t *ctx, lsm303agr_i2c_dis_m_t val) { lsm303agr_cfg_reg_c_m_t cfg_reg_c_m; @@ -3858,7 +3868,7 @@ int32_t lsm303agr_mag_i2c_interface_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303agr_mag_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_i2c_interface_get(const stmdev_ctx_t *ctx, lsm303agr_i2c_dis_m_t *val) { lsm303agr_cfg_reg_c_m_t cfg_reg_c_m; diff --git a/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.h b/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.h index e4b5fddf..1a332c17 100644 --- a/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.h +++ b/sensor/stmemsc/lsm303agr_STdC/driver/lsm303agr_reg.h @@ -238,8 +238,7 @@ typedef struct typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN -uint8_t hp : - 3; /* HPCLICK + HPIS2 + HPIS1 -> HP */ + uint8_t hp : 3; /* HPCLICK + HPIS2 + HPIS1 -> HP */ uint8_t fds : 1; uint8_t hpcf : 2; uint8_t hpm : 2; @@ -247,8 +246,7 @@ uint8_t hp : uint8_t hpm : 2; uint8_t hpcf : 2; uint8_t fds : 1; -uint8_t hp : - 3; /* HPCLICK + HPIS2 + HPIS1 -> HP */ + uint8_t hp : 3; /* HPCLICK + HPIS2 + HPIS1 -> HP */ #endif /* DRV_BYTE_ORDER */ } lsm303agr_ctrl_reg2_a_t; @@ -864,10 +862,10 @@ typedef union * them with a custom implementation. */ -int32_t lsm303agr_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm303agr_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lsm303agr_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm303agr_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -891,15 +889,15 @@ float_t lsm303agr_from_lsb_lp_to_celsius(int16_t lsb); float_t lsm303agr_from_lsb_to_mgauss(int16_t lsb); -int32_t lsm303agr_temp_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_temp_status_reg_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm303agr_temp_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303agr_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303agr_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303agr_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); typedef enum @@ -907,9 +905,9 @@ typedef enum LSM303AGR_TEMP_DISABLE = 0, LSM303AGR_TEMP_ENABLE = 3, } lsm303agr_temp_en_a_t; -int32_t lsm303agr_temperature_meas_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_temperature_meas_set(const stmdev_ctx_t *ctx, lsm303agr_temp_en_a_t val); -int32_t lsm303agr_temperature_meas_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_temperature_meas_get(const stmdev_ctx_t *ctx, lsm303agr_temp_en_a_t *val); typedef enum @@ -918,9 +916,9 @@ typedef enum LSM303AGR_NM_10bit = 1, LSM303AGR_LP_8bit = 2, } lsm303agr_op_md_a_t; -int32_t lsm303agr_xl_operating_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_operating_mode_set(const stmdev_ctx_t *ctx, lsm303agr_op_md_a_t val); -int32_t lsm303agr_xl_operating_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_operating_mode_get(const stmdev_ctx_t *ctx, lsm303agr_op_md_a_t *val); typedef enum @@ -936,14 +934,14 @@ typedef enum LSM303AGR_XL_ODR_1kHz620_LP = 8, LSM303AGR_XL_ODR_1kHz344_NM_HP_5kHz376_LP = 9, } lsm303agr_odr_a_t; -int32_t lsm303agr_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm303agr_odr_a_t val); -int32_t lsm303agr_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm303agr_odr_a_t *val); -int32_t lsm303agr_xl_high_pass_on_outputs_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_high_pass_on_outputs_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303agr_xl_high_pass_on_outputs_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_high_pass_on_outputs_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -953,9 +951,9 @@ typedef enum LSM303AGR_MEDIUM = 2, LSM303AGR_LIGHT = 3, } lsm303agr_hpcf_a_t; -int32_t lsm303agr_xl_high_pass_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_high_pass_bandwidth_set(const stmdev_ctx_t *ctx, lsm303agr_hpcf_a_t val); -int32_t lsm303agr_xl_high_pass_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_high_pass_bandwidth_get(const stmdev_ctx_t *ctx, lsm303agr_hpcf_a_t *val); typedef enum @@ -965,9 +963,9 @@ typedef enum LSM303AGR_NORMAL = 2, LSM303AGR_AUTORST_ON_INT = 3, } lsm303agr_hpm_a_t; -int32_t lsm303agr_xl_high_pass_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_high_pass_mode_set(const stmdev_ctx_t *ctx, lsm303agr_hpm_a_t val); -int32_t lsm303agr_xl_high_pass_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_high_pass_mode_get(const stmdev_ctx_t *ctx, lsm303agr_hpm_a_t *val); typedef enum @@ -977,29 +975,29 @@ typedef enum LSM303AGR_8g = 2, LSM303AGR_16g = 3, } lsm303agr_fs_a_t; -int32_t lsm303agr_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm303agr_fs_a_t val); -int32_t lsm303agr_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm303agr_fs_a_t *val); -int32_t lsm303agr_xl_block_data_update_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303agr_xl_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303agr_xl_filter_reference_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_filter_reference_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm303agr_xl_filter_reference_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_filter_reference_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm303agr_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303agr_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303agr_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303agr_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303agr_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm303agr_xl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm303agr_xl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); typedef enum { @@ -1007,9 +1005,9 @@ typedef enum LSM303AGR_ST_POSITIVE = 1, LSM303AGR_ST_NEGATIVE = 2, } lsm303agr_st_a_t; -int32_t lsm303agr_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_self_test_set(const stmdev_ctx_t *ctx, lsm303agr_st_a_t val); -int32_t lsm303agr_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_self_test_get(const stmdev_ctx_t *ctx, lsm303agr_st_a_t *val); typedef enum @@ -1017,51 +1015,51 @@ typedef enum LSM303AGR_XL_LSB_AT_LOW_ADD = 0, LSM303AGR_XL_MSB_AT_LOW_ADD = 1, } lsm303agr_ble_a_t; -int32_t lsm303agr_xl_data_format_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_data_format_set(const stmdev_ctx_t *ctx, lsm303agr_ble_a_t val); -int32_t lsm303agr_xl_data_format_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_data_format_get(const stmdev_ctx_t *ctx, lsm303agr_ble_a_t *val); -int32_t lsm303agr_xl_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303agr_xl_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303agr_xl_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303agr_xl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303agr_xl_status_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_status_get(const stmdev_ctx_t *ctx, lsm303agr_status_reg_a_t *val); -int32_t lsm303agr_xl_int1_gen_conf_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int1_gen_conf_set(const stmdev_ctx_t *ctx, lsm303agr_int1_cfg_a_t *val); -int32_t lsm303agr_xl_int1_gen_conf_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int1_gen_conf_get(const stmdev_ctx_t *ctx, lsm303agr_int1_cfg_a_t *val); -int32_t lsm303agr_xl_int1_gen_source_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int1_gen_source_get(const stmdev_ctx_t *ctx, lsm303agr_int1_src_a_t *val); -int32_t lsm303agr_xl_int1_gen_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int1_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303agr_xl_int1_gen_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int1_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303agr_xl_int1_gen_duration_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int1_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303agr_xl_int1_gen_duration_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int1_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303agr_xl_int2_gen_conf_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int2_gen_conf_set(const stmdev_ctx_t *ctx, lsm303agr_int2_cfg_a_t *val); -int32_t lsm303agr_xl_int2_gen_conf_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int2_gen_conf_get(const stmdev_ctx_t *ctx, lsm303agr_int2_cfg_a_t *val); -int32_t lsm303agr_xl_int2_gen_source_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int2_gen_source_get(const stmdev_ctx_t *ctx, lsm303agr_int2_src_a_t *val); -int32_t lsm303agr_xl_int2_gen_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int2_gen_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303agr_xl_int2_gen_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int2_gen_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303agr_xl_int2_gen_duration_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int2_gen_duration_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303agr_xl_int2_gen_duration_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int2_gen_duration_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -1075,19 +1073,19 @@ typedef enum LSM303AGR_ON_INT2_TAP_GEN = 6, LSM303AGR_ON_INT1_INT2_TAP_GEN = 7, } lsm303agr_hp_a_t; -int32_t lsm303agr_xl_high_pass_int_conf_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_high_pass_int_conf_set(const stmdev_ctx_t *ctx, lsm303agr_hp_a_t val); -int32_t lsm303agr_xl_high_pass_int_conf_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_high_pass_int_conf_get(const stmdev_ctx_t *ctx, lsm303agr_hp_a_t *val); -int32_t lsm303agr_xl_pin_int1_config_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_pin_int1_config_set(const stmdev_ctx_t *ctx, lsm303agr_ctrl_reg3_a_t *val); -int32_t lsm303agr_xl_pin_int1_config_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_pin_int1_config_get(const stmdev_ctx_t *ctx, lsm303agr_ctrl_reg3_a_t *val); -int32_t lsm303agr_xl_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int2_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303agr_xl_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int2_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -1095,14 +1093,14 @@ typedef enum LSM303AGR_INT2_PULSED = 0, LSM303AGR_INT2_LATCHED = 1, } lsm303agr_lir_int2_a_t; -int32_t lsm303agr_xl_int2pin_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int2pin_notification_mode_set(const stmdev_ctx_t *ctx, lsm303agr_lir_int2_a_t val); -int32_t lsm303agr_xl_int2pin_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int2pin_notification_mode_get(const stmdev_ctx_t *ctx, lsm303agr_lir_int2_a_t *val); -int32_t lsm303agr_xl_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int1_pin_detect_4d_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303agr_xl_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int1_pin_detect_4d_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -1110,22 +1108,22 @@ typedef enum LSM303AGR_INT1_PULSED = 0, LSM303AGR_INT1_LATCHED = 1, } lsm303agr_lir_int1_a_t; -int32_t lsm303agr_xl_int1pin_notification_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int1pin_notification_mode_set(const stmdev_ctx_t *ctx, lsm303agr_lir_int1_a_t val); -int32_t lsm303agr_xl_int1pin_notification_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_int1pin_notification_mode_get(const stmdev_ctx_t *ctx, lsm303agr_lir_int1_a_t *val); -int32_t lsm303agr_xl_pin_int2_config_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_pin_int2_config_set(const stmdev_ctx_t *ctx, lsm303agr_ctrl_reg6_a_t *val); -int32_t lsm303agr_xl_pin_int2_config_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_pin_int2_config_get(const stmdev_ctx_t *ctx, lsm303agr_ctrl_reg6_a_t *val); -int32_t lsm303agr_xl_fifo_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303agr_xl_fifo_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303agr_xl_fifo_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303agr_xl_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303agr_xl_fifo_watermark_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303agr_xl_fifo_watermark_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -1133,9 +1131,9 @@ typedef enum LSM303AGR_INT1_GEN = 0, LSM303AGR_INT2_GEN = 1, } lsm303agr_tr_a_t; -int32_t lsm303agr_xl_fifo_trigger_event_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_fifo_trigger_event_set(const stmdev_ctx_t *ctx, lsm303agr_tr_a_t val); -int32_t lsm303agr_xl_fifo_trigger_event_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_fifo_trigger_event_get(const stmdev_ctx_t *ctx, lsm303agr_tr_a_t *val); typedef enum @@ -1145,67 +1143,67 @@ typedef enum LSM303AGR_DYNAMIC_STREAM_MODE = 2, LSM303AGR_STREAM_TO_FIFO_MODE = 3, } lsm303agr_fm_a_t; -int32_t lsm303agr_xl_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_fifo_mode_set(const stmdev_ctx_t *ctx, lsm303agr_fm_a_t val); -int32_t lsm303agr_xl_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_fifo_mode_get(const stmdev_ctx_t *ctx, lsm303agr_fm_a_t *val); -int32_t lsm303agr_xl_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_fifo_status_get(const stmdev_ctx_t *ctx, lsm303agr_fifo_src_reg_a_t *val); -int32_t lsm303agr_xl_fifo_data_level_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303agr_xl_fifo_empty_flag_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303agr_xl_fifo_ovr_flag_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303agr_xl_fifo_fth_flag_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_fifo_fth_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303agr_tap_conf_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_tap_conf_set(const stmdev_ctx_t *ctx, lsm303agr_click_cfg_a_t *val); -int32_t lsm303agr_tap_conf_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_tap_conf_get(const stmdev_ctx_t *ctx, lsm303agr_click_cfg_a_t *val); -int32_t lsm303agr_tap_source_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_tap_source_get(const stmdev_ctx_t *ctx, lsm303agr_click_src_a_t *val); -int32_t lsm303agr_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303agr_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303agr_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303agr_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303agr_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303agr_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303agr_shock_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303agr_shock_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303agr_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303agr_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303agr_quiet_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303agr_quiet_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303agr_double_tap_timeout_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_double_tap_timeout_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303agr_double_tap_timeout_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_double_tap_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303agr_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303agr_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303agr_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303agr_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303agr_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303agr_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303agr_act_timeout_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303agr_act_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM303AGR_SPI_4_WIRE = 0, LSM303AGR_SPI_3_WIRE = 1, } lsm303agr_sim_a_t; -int32_t lsm303agr_xl_spi_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_spi_mode_set(const stmdev_ctx_t *ctx, lsm303agr_sim_a_t val); -int32_t lsm303agr_xl_spi_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_xl_spi_mode_get(const stmdev_ctx_t *ctx, lsm303agr_sim_a_t *val); -int32_t lsm303agr_mag_user_offset_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_user_offset_set(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm303agr_mag_user_offset_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_user_offset_get(const stmdev_ctx_t *ctx, int16_t *val); typedef enum @@ -1214,9 +1212,9 @@ typedef enum LSM303AGR_SINGLE_TRIGGER = 1, LSM303AGR_POWER_DOWN = 2, } lsm303agr_md_m_t; -int32_t lsm303agr_mag_operating_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_operating_mode_set(const stmdev_ctx_t *ctx, lsm303agr_md_m_t val); -int32_t lsm303agr_mag_operating_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_operating_mode_get(const stmdev_ctx_t *ctx, lsm303agr_md_m_t *val); typedef enum @@ -1226,9 +1224,9 @@ typedef enum LSM303AGR_MG_ODR_50Hz = 2, LSM303AGR_MG_ODR_100Hz = 3, } lsm303agr_mg_odr_m_t; -int32_t lsm303agr_mag_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_data_rate_set(const stmdev_ctx_t *ctx, lsm303agr_mg_odr_m_t val); -int32_t lsm303agr_mag_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_data_rate_get(const stmdev_ctx_t *ctx, lsm303agr_mg_odr_m_t *val); typedef enum @@ -1236,14 +1234,14 @@ typedef enum LSM303AGR_HIGH_RESOLUTION = 0, LSM303AGR_LOW_POWER = 1, } lsm303agr_lp_m_t; -int32_t lsm303agr_mag_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_power_mode_set(const stmdev_ctx_t *ctx, lsm303agr_lp_m_t val); -int32_t lsm303agr_mag_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_power_mode_get(const stmdev_ctx_t *ctx, lsm303agr_lp_m_t *val); -int32_t lsm303agr_mag_offset_temp_comp_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_offset_temp_comp_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303agr_mag_offset_temp_comp_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_offset_temp_comp_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -1251,9 +1249,9 @@ typedef enum LSM303AGR_ODR_DIV_2 = 0, LSM303AGR_ODR_DIV_4 = 1, } lsm303agr_lpf_m_t; -int32_t lsm303agr_mag_low_pass_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_low_pass_bandwidth_set(const stmdev_ctx_t *ctx, lsm303agr_lpf_m_t val); -int32_t lsm303agr_mag_low_pass_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_low_pass_bandwidth_get(const stmdev_ctx_t *ctx, lsm303agr_lpf_m_t *val); typedef enum @@ -1262,38 +1260,38 @@ typedef enum LSM303AGR_SENS_OFF_CANC_EVERY_ODR = 1, LSM303AGR_SET_SENS_ONLY_AT_POWER_ON = 2, } lsm303agr_set_rst_m_t; -int32_t lsm303agr_mag_set_rst_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_set_rst_mode_set(const stmdev_ctx_t *ctx, lsm303agr_set_rst_m_t val); -int32_t lsm303agr_mag_set_rst_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_set_rst_mode_get(const stmdev_ctx_t *ctx, lsm303agr_set_rst_m_t *val); -int32_t lsm303agr_mag_set_rst_sensor_single_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_set_rst_sensor_single_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303agr_mag_set_rst_sensor_single_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_set_rst_sensor_single_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303agr_mag_block_data_update_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303agr_mag_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303agr_mag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303agr_mag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303agr_mag_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303agr_mag_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303agr_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm303agr_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm303agr_mag_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm303agr_mag_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm303agr_mag_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303agr_mag_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303agr_mag_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303agr_mag_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303agr_mag_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303agr_mag_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303agr_mag_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303agr_mag_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303agr_mag_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_self_test_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303agr_mag_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -1301,12 +1299,12 @@ typedef enum LSM303AGR_MG_LSB_AT_LOW_ADD = 0, LSM303AGR_MG_MSB_AT_LOW_ADD = 1, } lsm303agr_ble_m_t; -int32_t lsm303agr_mag_data_format_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_data_format_set(const stmdev_ctx_t *ctx, lsm303agr_ble_m_t val); -int32_t lsm303agr_mag_data_format_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_data_format_get(const stmdev_ctx_t *ctx, lsm303agr_ble_m_t *val); -int32_t lsm303agr_mag_status_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_status_get(const stmdev_ctx_t *ctx, lsm303agr_status_reg_m_t *val); typedef enum @@ -1314,39 +1312,39 @@ typedef enum LSM303AGR_CHECK_BEFORE = 0, LSM303AGR_CHECK_AFTER = 1, } lsm303agr_int_on_dataoff_m_t; -int32_t lsm303agr_mag_offset_int_conf_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_offset_int_conf_set(const stmdev_ctx_t *ctx, lsm303agr_int_on_dataoff_m_t val); -int32_t lsm303agr_mag_offset_int_conf_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_offset_int_conf_get(const stmdev_ctx_t *ctx, lsm303agr_int_on_dataoff_m_t *val); -int32_t lsm303agr_mag_drdy_on_pin_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303agr_mag_drdy_on_pin_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_drdy_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303agr_mag_drdy_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303agr_mag_int_on_pin_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303agr_mag_int_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303agr_mag_int_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303agr_mag_int_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303agr_mag_int_gen_conf_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_int_gen_conf_set(const stmdev_ctx_t *ctx, lsm303agr_int_crtl_reg_m_t *val); -int32_t lsm303agr_mag_int_gen_conf_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_int_gen_conf_get(const stmdev_ctx_t *ctx, lsm303agr_int_crtl_reg_m_t *val); -int32_t lsm303agr_mag_int_gen_source_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_int_gen_source_get(const stmdev_ctx_t *ctx, lsm303agr_int_source_reg_m_t *val); -int32_t lsm303agr_mag_int_gen_treshold_set(stmdev_ctx_t *ctx, - int16_t val); -int32_t lsm303agr_mag_int_gen_treshold_get(stmdev_ctx_t *ctx, - int16_t *val); +int32_t lsm303agr_mag_int_gen_threshold_set(const stmdev_ctx_t *ctx, + int16_t val); +int32_t lsm303agr_mag_int_gen_threshold_get(const stmdev_ctx_t *ctx, + int16_t *val); typedef enum { LSM303AGR_I2C_ENABLE = 0, LSM303AGR_I2C_DISABLE = 1, } lsm303agr_i2c_dis_m_t; -int32_t lsm303agr_mag_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_i2c_interface_set(const stmdev_ctx_t *ctx, lsm303agr_i2c_dis_m_t val); -int32_t lsm303agr_mag_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lsm303agr_mag_i2c_interface_get(const stmdev_ctx_t *ctx, lsm303agr_i2c_dis_m_t *val); /** diff --git a/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.c b/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.c index 18e668f8..ae56f40b 100644 --- a/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.c +++ b/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm303ah_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm303ah_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lsm303ah_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm303ah_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm303ah_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -141,7 +151,7 @@ float_t lsm303ah_from_lsb_to_celsius(int16_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_all_sources_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_all_sources_get(const stmdev_ctx_t *ctx, lsm303ah_xl_all_sources_t *val) { int32_t ret; @@ -196,7 +206,7 @@ int32_t lsm303ah_xl_all_sources_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_block_data_update_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_ctrl1_a_t ctrl1_a; @@ -221,7 +231,7 @@ int32_t lsm303ah_xl_block_data_update_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_ctrl1_a_t ctrl1_a; @@ -241,7 +251,7 @@ int32_t lsm303ah_xl_block_data_update_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_block_data_update_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_cfg_reg_c_m_t cfg_reg_c_m; @@ -268,7 +278,7 @@ int32_t lsm303ah_mg_block_data_update_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_cfg_reg_c_m_t cfg_reg_c_m; @@ -289,7 +299,7 @@ int32_t lsm303ah_mg_block_data_update_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_data_format_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_data_format_set(const stmdev_ctx_t *ctx, lsm303ah_mg_ble_t val) { lsm303ah_cfg_reg_c_m_t cfg_reg_c_m; @@ -316,7 +326,7 @@ int32_t lsm303ah_mg_data_format_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_data_format_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_data_format_get(const stmdev_ctx_t *ctx, lsm303ah_mg_ble_t *val) { lsm303ah_cfg_reg_c_m_t cfg_reg_c_m; @@ -351,7 +361,7 @@ int32_t lsm303ah_mg_data_format_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm303ah_xl_fs_t val) { lsm303ah_ctrl1_a_t ctrl1_a; @@ -376,7 +386,7 @@ int32_t lsm303ah_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm303ah_xl_fs_t *val) { lsm303ah_ctrl1_a_t ctrl1_a; @@ -418,7 +428,7 @@ int32_t lsm303ah_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm303ah_xl_odr_t val) { lsm303ah_ctrl1_a_t ctrl1_a; @@ -444,7 +454,7 @@ int32_t lsm303ah_xl_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm303ah_xl_odr_t *val) { lsm303ah_ctrl1_a_t ctrl1_a; @@ -546,7 +556,7 @@ int32_t lsm303ah_xl_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_status_reg_get(const stmdev_ctx_t *ctx, lsm303ah_status_a_t *val) { int32_t ret; @@ -564,7 +574,7 @@ int32_t lsm303ah_xl_status_reg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_status_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_status_get(const stmdev_ctx_t *ctx, lsm303ah_status_reg_m_t *val) { int32_t ret; @@ -582,7 +592,7 @@ int32_t lsm303ah_mg_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_status_a_t status_a; @@ -602,7 +612,7 @@ int32_t lsm303ah_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303ah_mg_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_status_reg_m_t status_reg_m; int32_t ret; @@ -622,7 +632,7 @@ int32_t lsm303ah_mg_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303ah_mg_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_status_reg_m_t status_reg_m; int32_t ret; @@ -646,7 +656,7 @@ int32_t lsm303ah_mg_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_user_offset_set(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm303ah_mg_user_offset_set(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -674,7 +684,7 @@ int32_t lsm303ah_mg_user_offset_set(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_user_offset_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm303ah_mg_user_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -698,7 +708,7 @@ int32_t lsm303ah_mg_user_offset_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_operating_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_operating_mode_set(const stmdev_ctx_t *ctx, lsm303ah_mg_md_t val) { lsm303ah_cfg_reg_a_m_t cfg_reg_a_m; @@ -725,7 +735,7 @@ int32_t lsm303ah_mg_operating_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_operating_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_operating_mode_get(const stmdev_ctx_t *ctx, lsm303ah_mg_md_t *val) { lsm303ah_cfg_reg_a_m_t cfg_reg_a_m; @@ -764,7 +774,7 @@ int32_t lsm303ah_mg_operating_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_data_rate_set(const stmdev_ctx_t *ctx, lsm303ah_mg_odr_t val) { lsm303ah_cfg_reg_a_m_t cfg_reg_a_m; @@ -791,7 +801,7 @@ int32_t lsm303ah_mg_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_data_rate_get(const stmdev_ctx_t *ctx, lsm303ah_mg_odr_t *val) { lsm303ah_cfg_reg_a_m_t cfg_reg_a_m; @@ -834,7 +844,7 @@ int32_t lsm303ah_mg_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_power_mode_set(const stmdev_ctx_t *ctx, lsm303ah_mg_lp_t val) { lsm303ah_cfg_reg_a_m_t cfg_reg_a_m; @@ -861,7 +871,7 @@ int32_t lsm303ah_mg_power_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_power_mode_get(const stmdev_ctx_t *ctx, lsm303ah_mg_lp_t *val) { lsm303ah_cfg_reg_a_m_t cfg_reg_a_m; @@ -896,7 +906,7 @@ int32_t lsm303ah_mg_power_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_offset_temp_comp_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_offset_temp_comp_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_cfg_reg_a_m_t cfg_reg_a_m; @@ -923,7 +933,7 @@ int32_t lsm303ah_mg_offset_temp_comp_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_offset_temp_comp_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_offset_temp_comp_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_cfg_reg_a_m_t cfg_reg_a_m; @@ -944,7 +954,7 @@ int32_t lsm303ah_mg_offset_temp_comp_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_set_rst_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_set_rst_mode_set(const stmdev_ctx_t *ctx, lsm303ah_mg_set_rst_t val) { lsm303ah_cfg_reg_b_m_t cfg_reg_b_m; @@ -971,7 +981,7 @@ int32_t lsm303ah_mg_set_rst_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_set_rst_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_set_rst_mode_get(const stmdev_ctx_t *ctx, lsm303ah_mg_set_rst_t *val) { lsm303ah_cfg_reg_b_m_t cfg_reg_b_m; @@ -1013,7 +1023,7 @@ int32_t lsm303ah_mg_set_rst_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_set_rst_sensor_single_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_set_rst_sensor_single_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_cfg_reg_b_m_t cfg_reg_b_m; @@ -1043,7 +1053,7 @@ int32_t lsm303ah_mg_set_rst_sensor_single_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_set_rst_sensor_single_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_set_rst_sensor_single_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_cfg_reg_b_m_t cfg_reg_b_m; @@ -1076,7 +1086,7 @@ int32_t lsm303ah_mg_set_rst_sensor_single_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_acceleration_module_raw_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_acceleration_module_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1095,7 +1105,7 @@ int32_t lsm303ah_acceleration_module_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_temperature_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1114,7 +1124,7 @@ int32_t lsm303ah_xl_temperature_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm303ah_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1138,7 +1148,7 @@ int32_t lsm303ah_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm303ah_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1162,7 +1172,7 @@ int32_t lsm303ah_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm303ah_number_of_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1194,7 +1204,7 @@ int32_t lsm303ah_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm303ah_xl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1211,7 +1221,7 @@ int32_t lsm303ah_xl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm303ah_mg_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1229,7 +1239,7 @@ int32_t lsm303ah_mg_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303ah_xl_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_ctrl2_a_t ctrl2_a; int32_t ret; @@ -1254,7 +1264,7 @@ int32_t lsm303ah_xl_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_auto_increment_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_ctrl2_a_t ctrl2_a; @@ -1275,7 +1285,7 @@ int32_t lsm303ah_xl_auto_increment_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_mem_bank_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_mem_bank_set(const stmdev_ctx_t *ctx, lsm303ah_xl_func_cfg_en_t val) { lsm303ah_ctrl2_a_t ctrl2_a; @@ -1318,7 +1328,7 @@ int32_t lsm303ah_xl_mem_bank_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303ah_xl_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_ctrl2_a_t ctrl2_a; int32_t ret; @@ -1342,7 +1352,7 @@ int32_t lsm303ah_xl_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303ah_xl_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_ctrl2_a_t ctrl2_a; int32_t ret; @@ -1361,7 +1371,7 @@ int32_t lsm303ah_xl_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303ah_mg_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_cfg_reg_a_m_t cfg_reg_a_m; int32_t ret; @@ -1387,7 +1397,7 @@ int32_t lsm303ah_mg_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303ah_mg_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_cfg_reg_a_m_t cfg_reg_a_m; int32_t ret; @@ -1407,7 +1417,7 @@ int32_t lsm303ah_mg_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303ah_xl_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_ctrl2_a_t ctrl2_a; int32_t ret; @@ -1431,7 +1441,7 @@ int32_t lsm303ah_xl_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303ah_xl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_ctrl2_a_t ctrl2_a; int32_t ret; @@ -1450,7 +1460,7 @@ int32_t lsm303ah_xl_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303ah_mg_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_cfg_reg_a_m_t cfg_reg_a_m; int32_t ret; @@ -1476,7 +1486,7 @@ int32_t lsm303ah_mg_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303ah_mg_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_cfg_reg_a_m_t cfg_reg_a_m; int32_t ret; @@ -1496,7 +1506,7 @@ int32_t lsm303ah_mg_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_self_test_set(const stmdev_ctx_t *ctx, lsm303ah_xl_st_t val) { lsm303ah_ctrl3_a_t ctrl3_a; @@ -1521,7 +1531,7 @@ int32_t lsm303ah_xl_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_self_test_get(const stmdev_ctx_t *ctx, lsm303ah_xl_st_t *val) { lsm303ah_ctrl3_a_t ctrl3_a; @@ -1559,7 +1569,7 @@ int32_t lsm303ah_xl_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_self_test_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303ah_mg_self_test_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_cfg_reg_c_m_t cfg_reg_c_m; int32_t ret; @@ -1585,7 +1595,7 @@ int32_t lsm303ah_mg_self_test_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_self_test_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303ah_mg_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_cfg_reg_c_m_t cfg_reg_c_m; int32_t ret; @@ -1605,7 +1615,7 @@ int32_t lsm303ah_mg_self_test_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm303ah_xl_drdy_pulsed_t val) { lsm303ah_ctrl5_a_t ctrl5_a; @@ -1630,7 +1640,7 @@ int32_t lsm303ah_xl_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm303ah_xl_drdy_pulsed_t *val) { lsm303ah_ctrl5_a_t ctrl5_a; @@ -1677,7 +1687,7 @@ int32_t lsm303ah_xl_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_hp_path_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_hp_path_set(const stmdev_ctx_t *ctx, lsm303ah_xl_fds_slope_t val) { lsm303ah_ctrl2_a_t ctrl2_a; @@ -1702,7 +1712,7 @@ int32_t lsm303ah_xl_hp_path_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_hp_path_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_hp_path_get(const stmdev_ctx_t *ctx, lsm303ah_xl_fds_slope_t *val) { lsm303ah_ctrl2_a_t ctrl2_a; @@ -1736,7 +1746,7 @@ int32_t lsm303ah_xl_hp_path_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_low_pass_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_low_pass_bandwidth_set(const stmdev_ctx_t *ctx, lsm303ah_mg_lpf_t val) { lsm303ah_cfg_reg_b_m_t cfg_reg_b_m; @@ -1763,7 +1773,7 @@ int32_t lsm303ah_mg_low_pass_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_low_pass_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_low_pass_bandwidth_get(const stmdev_ctx_t *ctx, lsm303ah_mg_lpf_t *val) { lsm303ah_cfg_reg_b_m_t cfg_reg_b_m; @@ -1811,7 +1821,7 @@ int32_t lsm303ah_mg_low_pass_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_spi_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_spi_mode_set(const stmdev_ctx_t *ctx, lsm303ah_xl_sim_t val) { lsm303ah_ctrl2_a_t ctrl2_a; @@ -1836,7 +1846,7 @@ int32_t lsm303ah_xl_spi_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_spi_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_spi_mode_get(const stmdev_ctx_t *ctx, lsm303ah_xl_sim_t *val) { lsm303ah_ctrl2_a_t ctrl2_a; @@ -1870,7 +1880,7 @@ int32_t lsm303ah_xl_spi_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_i2c_interface_set(const stmdev_ctx_t *ctx, lsm303ah_xl_i2c_disable_t val) { lsm303ah_ctrl2_a_t ctrl2_a; @@ -1895,7 +1905,7 @@ int32_t lsm303ah_xl_i2c_interface_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_i2c_interface_get(const stmdev_ctx_t *ctx, lsm303ah_xl_i2c_disable_t *val) { lsm303ah_ctrl2_a_t ctrl2_a; @@ -1929,7 +1939,7 @@ int32_t lsm303ah_xl_i2c_interface_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_i2c_interface_set(const stmdev_ctx_t *ctx, lsm303ah_mg_i2c_dis_t val) { lsm303ah_cfg_reg_c_m_t cfg_reg_c_m; @@ -1956,7 +1966,7 @@ int32_t lsm303ah_mg_i2c_interface_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_i2c_interface_get(const stmdev_ctx_t *ctx, lsm303ah_mg_i2c_dis_t *val) { lsm303ah_cfg_reg_c_m_t cfg_reg_c_m; @@ -1991,7 +2001,7 @@ int32_t lsm303ah_mg_i2c_interface_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_cs_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_cs_mode_set(const stmdev_ctx_t *ctx, lsm303ah_xl_if_cs_pu_dis_t val) { lsm303ah_fifo_ctrl_a_t fifo_ctrl_a; @@ -2018,7 +2028,7 @@ int32_t lsm303ah_xl_cs_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_cs_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_cs_mode_get(const stmdev_ctx_t *ctx, lsm303ah_xl_if_cs_pu_dis_t *val) { lsm303ah_fifo_ctrl_a_t fifo_ctrl_a; @@ -2066,7 +2076,7 @@ int32_t lsm303ah_xl_cs_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pin_mode_set(const stmdev_ctx_t *ctx, lsm303ah_xl_pp_od_t val) { lsm303ah_ctrl3_a_t ctrl3_a; @@ -2091,7 +2101,7 @@ int32_t lsm303ah_xl_pin_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pin_mode_get(const stmdev_ctx_t *ctx, lsm303ah_xl_pp_od_t *val) { lsm303ah_ctrl3_a_t ctrl3_a; @@ -2125,7 +2135,7 @@ int32_t lsm303ah_xl_pin_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pin_polarity_set(const stmdev_ctx_t *ctx, lsm303ah_xl_h_lactive_t val) { lsm303ah_ctrl3_a_t ctrl3_a; @@ -2150,7 +2160,7 @@ int32_t lsm303ah_xl_pin_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pin_polarity_get(const stmdev_ctx_t *ctx, lsm303ah_xl_h_lactive_t *val) { lsm303ah_ctrl3_a_t ctrl3_a; @@ -2184,7 +2194,7 @@ int32_t lsm303ah_xl_pin_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_int_notification_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_int_notification_set(const stmdev_ctx_t *ctx, lsm303ah_xl_lir_t val) { lsm303ah_ctrl3_a_t ctrl3_a; @@ -2209,7 +2219,7 @@ int32_t lsm303ah_xl_int_notification_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_int_notification_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_int_notification_get(const stmdev_ctx_t *ctx, lsm303ah_xl_lir_t *val) { lsm303ah_ctrl3_a_t ctrl3_a; @@ -2243,7 +2253,7 @@ int32_t lsm303ah_xl_int_notification_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm303ah_xl_pin_int1_route_t val) { lsm303ah_ctrl4_a_t ctrl4_a; @@ -2288,7 +2298,7 @@ int32_t lsm303ah_xl_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm303ah_xl_pin_int1_route_t *val) { lsm303ah_ctrl4_a_t ctrl4_a; @@ -2327,7 +2337,7 @@ int32_t lsm303ah_xl_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm303ah_xl_pin_int2_route_t val) { lsm303ah_ctrl5_a_t ctrl5_a; @@ -2357,7 +2367,7 @@ int32_t lsm303ah_xl_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pin_int2_route_get(const stmdev_ctx_t *ctx, lsm303ah_xl_pin_int2_route_t *val) { lsm303ah_ctrl5_a_t ctrl5_a; @@ -2382,7 +2392,7 @@ int32_t lsm303ah_xl_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303ah_xl_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_ctrl5_a_t ctrl5_a; int32_t ret; @@ -2406,7 +2416,7 @@ int32_t lsm303ah_xl_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303ah_xl_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_ctrl5_a_t ctrl5_a; int32_t ret; @@ -2425,7 +2435,7 @@ int32_t lsm303ah_xl_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_drdy_on_pin_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303ah_mg_drdy_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_cfg_reg_c_m_t cfg_reg_c_m; int32_t ret; @@ -2451,7 +2461,7 @@ int32_t lsm303ah_mg_drdy_on_pin_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_drdy_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303ah_mg_drdy_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_cfg_reg_c_m_t cfg_reg_c_m; int32_t ret; @@ -2471,7 +2481,7 @@ int32_t lsm303ah_mg_drdy_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_int_on_pin_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303ah_mg_int_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_cfg_reg_c_m_t cfg_reg_c_m; int32_t ret; @@ -2497,7 +2507,7 @@ int32_t lsm303ah_mg_int_on_pin_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_int_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303ah_mg_int_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_cfg_reg_c_m_t cfg_reg_c_m; int32_t ret; @@ -2517,7 +2527,7 @@ int32_t lsm303ah_mg_int_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_int_gen_conf_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_int_gen_conf_set(const stmdev_ctx_t *ctx, lsm303ah_int_crtl_reg_m_t *val) { int32_t ret; @@ -2536,7 +2546,7 @@ int32_t lsm303ah_mg_int_gen_conf_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_int_gen_conf_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_int_gen_conf_get(const stmdev_ctx_t *ctx, lsm303ah_int_crtl_reg_m_t *val) { int32_t ret; @@ -2554,7 +2564,7 @@ int32_t lsm303ah_mg_int_gen_conf_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_int_gen_source_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_int_gen_source_get(const stmdev_ctx_t *ctx, lsm303ah_int_source_reg_m_t *val) { int32_t ret; @@ -2575,8 +2585,8 @@ int32_t lsm303ah_mg_int_gen_source_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_int_gen_treshold_set(stmdev_ctx_t *ctx, - uint16_t val) +int32_t lsm303ah_mg_int_gen_threshold_set(const stmdev_ctx_t *ctx, + uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -2598,8 +2608,8 @@ int32_t lsm303ah_mg_int_gen_treshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_int_gen_treshold_get(stmdev_ctx_t *ctx, - uint16_t *val) +int32_t lsm303ah_mg_int_gen_threshold_get(const stmdev_ctx_t *ctx, + uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -2647,7 +2657,7 @@ int32_t lsm303ah_mg_int_gen_treshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_offset_int_conf_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_offset_int_conf_set(const stmdev_ctx_t *ctx, lsm303ah_mg_int_on_dataoff_t val) { lsm303ah_cfg_reg_b_m_t cfg_reg_b_m; @@ -2675,7 +2685,7 @@ int32_t lsm303ah_mg_offset_int_conf_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_mg_offset_int_conf_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_offset_int_conf_get(const stmdev_ctx_t *ctx, lsm303ah_mg_int_on_dataoff_t *val) { lsm303ah_cfg_reg_b_m_t cfg_reg_b_m; @@ -2710,7 +2720,7 @@ int32_t lsm303ah_mg_offset_int_conf_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303ah_xl_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_wake_up_ths_a_t wake_up_ths_a; int32_t ret; @@ -2736,7 +2746,7 @@ int32_t lsm303ah_xl_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_wkup_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_wake_up_ths_a_t wake_up_ths_a; @@ -2757,7 +2767,7 @@ int32_t lsm303ah_xl_wkup_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303ah_xl_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_wake_up_dur_a_t wake_up_dur_a; int32_t ret; @@ -2783,7 +2793,7 @@ int32_t lsm303ah_xl_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303ah_xl_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_wake_up_dur_a_t wake_up_dur_a; int32_t ret; @@ -2815,7 +2825,7 @@ int32_t lsm303ah_xl_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303ah_xl_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_wake_up_ths_a_t wake_up_ths_a; int32_t ret; @@ -2841,7 +2851,7 @@ int32_t lsm303ah_xl_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303ah_xl_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_wake_up_ths_a_t wake_up_ths_a; int32_t ret; @@ -2861,7 +2871,7 @@ int32_t lsm303ah_xl_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303ah_xl_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_wake_up_dur_a_t wake_up_dur_a; int32_t ret; @@ -2887,7 +2897,7 @@ int32_t lsm303ah_xl_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303ah_xl_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_wake_up_dur_a_t wake_up_dur_a; int32_t ret; @@ -2920,7 +2930,7 @@ int32_t lsm303ah_xl_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_ctrl3_a_t ctrl3_a; @@ -2945,7 +2955,7 @@ int32_t lsm303ah_xl_tap_detection_on_z_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_ctrl3_a_t ctrl3_a; @@ -2965,7 +2975,7 @@ int32_t lsm303ah_xl_tap_detection_on_z_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_ctrl3_a_t ctrl3_a; @@ -2990,7 +3000,7 @@ int32_t lsm303ah_xl_tap_detection_on_y_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_ctrl3_a_t ctrl3_a; @@ -3010,7 +3020,7 @@ int32_t lsm303ah_xl_tap_detection_on_y_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_ctrl3_a_t ctrl3_a; @@ -3035,7 +3045,7 @@ int32_t lsm303ah_xl_tap_detection_on_x_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_ctrl3_a_t ctrl3_a; @@ -3055,7 +3065,7 @@ int32_t lsm303ah_xl_tap_detection_on_x_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303ah_xl_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_tap_6d_ths_a_t tap_6d_ths_a; int32_t ret; @@ -3081,7 +3091,7 @@ int32_t lsm303ah_xl_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303ah_xl_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_tap_6d_ths_a_t tap_6d_ths_a; int32_t ret; @@ -3105,7 +3115,7 @@ int32_t lsm303ah_xl_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303ah_xl_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_int_dur_a_t int_dur_a; int32_t ret; @@ -3135,7 +3145,7 @@ int32_t lsm303ah_xl_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303ah_xl_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_int_dur_a_t int_dur_a; int32_t ret; @@ -3159,7 +3169,7 @@ int32_t lsm303ah_xl_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303ah_xl_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_int_dur_a_t int_dur_a; int32_t ret; @@ -3189,7 +3199,7 @@ int32_t lsm303ah_xl_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303ah_xl_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_int_dur_a_t int_dur_a; int32_t ret; @@ -3213,7 +3223,7 @@ int32_t lsm303ah_xl_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303ah_xl_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_int_dur_a_t int_dur_a; int32_t ret; @@ -3243,7 +3253,7 @@ int32_t lsm303ah_xl_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303ah_xl_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_int_dur_a_t int_dur_a; int32_t ret; @@ -3263,7 +3273,7 @@ int32_t lsm303ah_xl_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_tap_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_tap_mode_set(const stmdev_ctx_t *ctx, lsm303ah_xl_single_double_tap_t val) { lsm303ah_wake_up_ths_a_t wake_up_ths_a; @@ -3290,7 +3300,7 @@ int32_t lsm303ah_xl_tap_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_tap_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_tap_mode_get(const stmdev_ctx_t *ctx, lsm303ah_xl_single_double_tap_t *val) { lsm303ah_wake_up_ths_a_t wake_up_ths_a; @@ -3325,7 +3335,7 @@ int32_t lsm303ah_xl_tap_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_tap_src_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_tap_src_get(const stmdev_ctx_t *ctx, lsm303ah_tap_src_a_t *val) { int32_t ret; @@ -3356,7 +3366,7 @@ int32_t lsm303ah_xl_tap_src_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_6d_threshold_set(const stmdev_ctx_t *ctx, lsm303ah_xl_6d_ths_t val) { lsm303ah_tap_6d_ths_a_t tap_6d_ths_a; @@ -3383,7 +3393,7 @@ int32_t lsm303ah_xl_6d_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_6d_threshold_get(const stmdev_ctx_t *ctx, lsm303ah_xl_6d_ths_t *val) { lsm303ah_tap_6d_ths_a_t tap_6d_ths_a; @@ -3426,7 +3436,7 @@ int32_t lsm303ah_xl_6d_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303ah_xl_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_tap_6d_ths_a_t tap_6d_ths_a; int32_t ret; @@ -3452,7 +3462,7 @@ int32_t lsm303ah_xl_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303ah_xl_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_tap_6d_ths_a_t tap_6d_ths_a; int32_t ret; @@ -3472,7 +3482,7 @@ int32_t lsm303ah_xl_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_6d_src_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_6d_src_get(const stmdev_ctx_t *ctx, lsm303ah_6d_src_a_t *val) { int32_t ret; @@ -3503,7 +3513,7 @@ int32_t lsm303ah_xl_6d_src_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303ah_xl_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_wake_up_dur_a_t wake_up_dur_a; lsm303ah_free_fall_a_t free_fall_a; @@ -3543,7 +3553,7 @@ int32_t lsm303ah_xl_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303ah_xl_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_wake_up_dur_a_t wake_up_dur_a; lsm303ah_free_fall_a_t free_fall_a; @@ -3571,7 +3581,7 @@ int32_t lsm303ah_xl_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_ff_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303ah_xl_ff_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_free_fall_a_t free_fall_a; int32_t ret; @@ -3597,7 +3607,7 @@ int32_t lsm303ah_xl_ff_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_ff_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303ah_xl_ff_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_free_fall_a_t free_fall_a; int32_t ret; @@ -3630,7 +3640,7 @@ int32_t lsm303ah_xl_ff_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_fifo_xl_module_batch_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_fifo_xl_module_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_fifo_ctrl_a_t fifo_ctrl_a; @@ -3658,7 +3668,7 @@ int32_t lsm303ah_xl_fifo_xl_module_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_fifo_xl_module_batch_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_fifo_xl_module_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_fifo_ctrl_a_t fifo_ctrl_a; @@ -3679,7 +3689,7 @@ int32_t lsm303ah_xl_fifo_xl_module_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_fifo_mode_set(const stmdev_ctx_t *ctx, lsm303ah_xl_fmode_t val) { lsm303ah_fifo_ctrl_a_t fifo_ctrl_a; @@ -3706,7 +3716,7 @@ int32_t lsm303ah_xl_fifo_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_fifo_mode_get(const stmdev_ctx_t *ctx, lsm303ah_xl_fmode_t *val) { lsm303ah_fifo_ctrl_a_t fifo_ctrl_a; @@ -3753,7 +3763,7 @@ int32_t lsm303ah_xl_fifo_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303ah_xl_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; @@ -3770,7 +3780,7 @@ int32_t lsm303ah_xl_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_fifo_watermark_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -3788,7 +3798,7 @@ int32_t lsm303ah_xl_fifo_watermark_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_fifo_full_flag_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_fifo_src_a_t fifo_src_a; @@ -3809,7 +3819,7 @@ int32_t lsm303ah_xl_fifo_full_flag_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303ah_xl_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_fifo_src_a_t fifo_src_a; int32_t ret; @@ -3829,7 +3839,7 @@ int32_t lsm303ah_xl_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303ah_xl_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_fifo_src_a_t fifo_src_a; int32_t ret; @@ -3849,7 +3859,7 @@ int32_t lsm303ah_xl_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_fifo_data_level_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm303ah_fifo_src_a_t fifo_src_a; @@ -3878,7 +3888,7 @@ int32_t lsm303ah_xl_fifo_data_level_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_fifo_src_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_fifo_src_get(const stmdev_ctx_t *ctx, lsm303ah_fifo_src_a_t *val) { int32_t ret; @@ -3908,7 +3918,7 @@ int32_t lsm303ah_xl_fifo_src_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303ah_xl_pedo_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_step_counter_minths_a_t step_counter_minths_a; int32_t ret; @@ -3934,7 +3944,7 @@ int32_t lsm303ah_xl_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_pedo_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pedo_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_step_counter_minths_a_t step_counter_minths_a; @@ -3955,7 +3965,7 @@ int32_t lsm303ah_xl_pedo_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_pedo_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pedo_full_scale_set(const stmdev_ctx_t *ctx, lsm303ah_xl_pedo4g_t val) { lsm303ah_step_counter_minths_a_t step_counter_minths_a; @@ -3982,7 +3992,7 @@ int32_t lsm303ah_xl_pedo_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_pedo_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pedo_full_scale_get(const stmdev_ctx_t *ctx, lsm303ah_xl_pedo4g_t *val) { lsm303ah_step_counter_minths_a_t step_counter_minths_a; @@ -4017,7 +4027,7 @@ int32_t lsm303ah_xl_pedo_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_pedo_step_reset_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pedo_step_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_step_counter_minths_a_t step_counter_minths_a; @@ -4044,7 +4054,7 @@ int32_t lsm303ah_xl_pedo_step_reset_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_pedo_step_reset_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pedo_step_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_step_counter_minths_a_t step_counter_minths_a; @@ -4065,7 +4075,7 @@ int32_t lsm303ah_xl_pedo_step_reset_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_pedo_step_detect_flag_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pedo_step_detect_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_func_ck_gate_a_t func_ck_gate_a; @@ -4086,7 +4096,7 @@ int32_t lsm303ah_xl_pedo_step_detect_flag_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303ah_xl_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_func_ctrl_a_t func_ctrl_a; int32_t ret; @@ -4112,7 +4122,7 @@ int32_t lsm303ah_xl_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303ah_xl_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_func_ctrl_a_t func_ctrl_a; int32_t ret; @@ -4132,7 +4142,7 @@ int32_t lsm303ah_xl_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_pedo_debounce_steps_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_pedo_deb_reg_a_t pedo_deb_reg_a; @@ -4169,7 +4179,7 @@ int32_t lsm303ah_xl_pedo_debounce_steps_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_pedo_debounce_steps_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_pedo_deb_reg_a_t pedo_deb_reg_a; @@ -4202,7 +4212,7 @@ int32_t lsm303ah_xl_pedo_debounce_steps_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303ah_xl_pedo_timeout_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_pedo_deb_reg_a_t pedo_deb_reg_a; int32_t ret; @@ -4240,7 +4250,7 @@ int32_t lsm303ah_xl_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303ah_xl_pedo_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_pedo_deb_reg_a_t pedo_deb_reg_a; int32_t ret; @@ -4271,7 +4281,7 @@ int32_t lsm303ah_xl_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_pedo_steps_period_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pedo_steps_period_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -4300,7 +4310,7 @@ int32_t lsm303ah_xl_pedo_steps_period_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_pedo_steps_period_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pedo_steps_period_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -4341,7 +4351,7 @@ int32_t lsm303ah_xl_pedo_steps_period_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_motion_data_ready_flag_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_motion_data_ready_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_func_ck_gate_a_t func_ck_gate_a; @@ -4362,7 +4372,7 @@ int32_t lsm303ah_xl_motion_data_ready_flag_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303ah_xl_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_func_ctrl_a_t func_ctrl_a; int32_t ret; @@ -4388,7 +4398,7 @@ int32_t lsm303ah_xl_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303ah_xl_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_func_ctrl_a_t func_ctrl_a; int32_t ret; @@ -4412,7 +4422,7 @@ int32_t lsm303ah_xl_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_motion_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_motion_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_sm_ths_a_t sm_ths_a; @@ -4451,7 +4461,7 @@ int32_t lsm303ah_xl_motion_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_motion_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_motion_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_sm_ths_a_t sm_ths_a; @@ -4494,7 +4504,7 @@ int32_t lsm303ah_xl_motion_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_tilt_data_ready_flag_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_tilt_data_ready_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_func_ck_gate_a_t func_ck_gate_a; @@ -4515,7 +4525,7 @@ int32_t lsm303ah_xl_tilt_data_ready_flag_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303ah_xl_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_func_ctrl_a_t func_ctrl_a; int32_t ret; @@ -4541,7 +4551,7 @@ int32_t lsm303ah_xl_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303ah_xl_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_func_ctrl_a_t func_ctrl_a; int32_t ret; @@ -4574,7 +4584,7 @@ int32_t lsm303ah_xl_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_module_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm303ah_xl_module_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm303ah_func_ctrl_a_t func_ctrl_a; int32_t ret; @@ -4600,7 +4610,7 @@ int32_t lsm303ah_xl_module_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm303ah_xl_module_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm303ah_xl_module_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm303ah_func_ctrl_a_t func_ctrl_a; int32_t ret; diff --git a/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.h b/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.h index 970fc4bc..126e9097 100644 --- a/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.h +++ b/sensor/stmemsc/lsm303ah_STdC/driver/lsm303ah_reg.h @@ -861,10 +861,10 @@ typedef union * them with a custom implementation. */ -int32_t lsm303ah_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm303ah_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lsm303ah_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm303ah_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -887,18 +887,18 @@ typedef struct lsm303ah_func_ck_gate_a_t func_ck_gate_a; lsm303ah_func_src_a_t func_src_a; } lsm303ah_xl_all_sources_t; -int32_t lsm303ah_xl_all_sources_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_all_sources_get(const stmdev_ctx_t *ctx, lsm303ah_xl_all_sources_t *val); -int32_t lsm303ah_xl_block_data_update_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_mg_block_data_update_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_mg_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -906,9 +906,9 @@ typedef enum LSM303AH_MG_LSB_AT_LOW_ADD = 0, LSM303AH_MG_MSB_AT_LOW_ADD = 1, } lsm303ah_mg_ble_t; -int32_t lsm303ah_mg_data_format_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_data_format_set(const stmdev_ctx_t *ctx, lsm303ah_mg_ble_t val); -int32_t lsm303ah_mg_data_format_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_data_format_get(const stmdev_ctx_t *ctx, lsm303ah_mg_ble_t *val); typedef enum @@ -918,9 +918,9 @@ typedef enum LSM303AH_XL_4g = 2, LSM303AH_XL_8g = 3, } lsm303ah_xl_fs_t; -int32_t lsm303ah_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm303ah_xl_fs_t val); -int32_t lsm303ah_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm303ah_xl_fs_t *val); typedef enum @@ -945,25 +945,25 @@ typedef enum LSM303AH_XL_ODR_3k2Hz_HF = 0x16, LSM303AH_XL_ODR_6k4Hz_HF = 0x17, } lsm303ah_xl_odr_t; -int32_t lsm303ah_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm303ah_xl_odr_t val); -int32_t lsm303ah_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm303ah_xl_odr_t *val); -int32_t lsm303ah_xl_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_status_reg_get(const stmdev_ctx_t *ctx, lsm303ah_status_a_t *val); -int32_t lsm303ah_mg_status_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_status_get(const stmdev_ctx_t *ctx, lsm303ah_status_reg_m_t *val); -int32_t lsm303ah_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_mg_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_mg_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303ah_mg_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303ah_mg_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_mg_user_offset_set(stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm303ah_mg_user_offset_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm303ah_mg_user_offset_set(const stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm303ah_mg_user_offset_get(const stmdev_ctx_t *ctx, int16_t *val); typedef enum { @@ -971,9 +971,9 @@ typedef enum LSM303AH_MG_SINGLE_TRIGGER = 1, LSM303AH_MG_POWER_DOWN = 2, } lsm303ah_mg_md_t; -int32_t lsm303ah_mg_operating_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_operating_mode_set(const stmdev_ctx_t *ctx, lsm303ah_mg_md_t val); -int32_t lsm303ah_mg_operating_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_operating_mode_get(const stmdev_ctx_t *ctx, lsm303ah_mg_md_t *val); typedef enum @@ -983,9 +983,9 @@ typedef enum LSM303AH_MG_ODR_50Hz = 2, LSM303AH_MG_ODR_100Hz = 3, } lsm303ah_mg_odr_t; -int32_t lsm303ah_mg_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_data_rate_set(const stmdev_ctx_t *ctx, lsm303ah_mg_odr_t val); -int32_t lsm303ah_mg_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_data_rate_get(const stmdev_ctx_t *ctx, lsm303ah_mg_odr_t *val); typedef enum @@ -993,14 +993,14 @@ typedef enum LSM303AH_MG_HIGH_RESOLUTION = 0, LSM303AH_MG_LOW_POWER = 1, } lsm303ah_mg_lp_t; -int32_t lsm303ah_mg_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_power_mode_set(const stmdev_ctx_t *ctx, lsm303ah_mg_lp_t val); -int32_t lsm303ah_mg_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_power_mode_get(const stmdev_ctx_t *ctx, lsm303ah_mg_lp_t *val); -int32_t lsm303ah_mg_offset_temp_comp_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_offset_temp_comp_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_mg_offset_temp_comp_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_offset_temp_comp_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -1009,37 +1009,37 @@ typedef enum LSM303AH_MG_SENS_OFF_CANC_EVERY_ODR = 1, LSM303AH_MG_SET_SENS_ONLY_AT_POWER_ON = 2, } lsm303ah_mg_set_rst_t; -int32_t lsm303ah_mg_set_rst_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_set_rst_mode_set(const stmdev_ctx_t *ctx, lsm303ah_mg_set_rst_t val); -int32_t lsm303ah_mg_set_rst_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_set_rst_mode_get(const stmdev_ctx_t *ctx, lsm303ah_mg_set_rst_t *val); -int32_t lsm303ah_mg_set_rst_sensor_single_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_set_rst_sensor_single_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_mg_set_rst_sensor_single_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_set_rst_sensor_single_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_acceleration_module_raw_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_acceleration_module_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm303ah_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm303ah_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm303ah_xl_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_temperature_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm303ah_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm303ah_number_of_steps_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_number_of_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm303ah_xl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm303ah_xl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm303ah_mg_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm303ah_mg_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm303ah_xl_auto_increment_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_auto_increment_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -1047,20 +1047,20 @@ typedef enum LSM303AH_XL_USER_BANK = 0, LSM303AH_XL_ADV_BANK = 1, } lsm303ah_xl_func_cfg_en_t; -int32_t lsm303ah_xl_mem_bank_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_mem_bank_set(const stmdev_ctx_t *ctx, lsm303ah_xl_func_cfg_en_t val); -int32_t lsm303ah_xl_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303ah_xl_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303ah_xl_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_mg_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_mg_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303ah_mg_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303ah_mg_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303ah_xl_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303ah_xl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_mg_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_mg_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303ah_mg_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303ah_mg_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -1068,22 +1068,22 @@ typedef enum LSM303AH_XL_ST_POSITIVE = 1, LSM303AH_XL_ST_NEGATIVE = 2, } lsm303ah_xl_st_t; -int32_t lsm303ah_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_self_test_set(const stmdev_ctx_t *ctx, lsm303ah_xl_st_t val); -int32_t lsm303ah_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_self_test_get(const stmdev_ctx_t *ctx, lsm303ah_xl_st_t *val); -int32_t lsm303ah_mg_self_test_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_mg_self_test_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303ah_mg_self_test_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303ah_mg_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM303AH_XL_DRDY_LATCHED = 0, LSM303AH_XL_DRDY_PULSED = 1, } lsm303ah_xl_drdy_pulsed_t; -int32_t lsm303ah_xl_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm303ah_xl_drdy_pulsed_t val); -int32_t lsm303ah_xl_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm303ah_xl_drdy_pulsed_t *val); typedef enum @@ -1091,9 +1091,9 @@ typedef enum LSM303AH_XL_HP_INTERNAL_ONLY = 0, LSM303AH_XL_HP_ON_OUTPUTS = 1, } lsm303ah_xl_fds_slope_t; -int32_t lsm303ah_xl_hp_path_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_hp_path_set(const stmdev_ctx_t *ctx, lsm303ah_xl_fds_slope_t val); -int32_t lsm303ah_xl_hp_path_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_hp_path_get(const stmdev_ctx_t *ctx, lsm303ah_xl_fds_slope_t *val); typedef enum @@ -1101,9 +1101,9 @@ typedef enum LSM303AH_MG_ODR_DIV_2 = 0, LSM303AH_MG_ODR_DIV_4 = 1, } lsm303ah_mg_lpf_t; -int32_t lsm303ah_mg_low_pass_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_low_pass_bandwidth_set(const stmdev_ctx_t *ctx, lsm303ah_mg_lpf_t val); -int32_t lsm303ah_mg_low_pass_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_low_pass_bandwidth_get(const stmdev_ctx_t *ctx, lsm303ah_mg_lpf_t *val); typedef enum @@ -1111,9 +1111,9 @@ typedef enum LSM303AH_XL_SPI_4_WIRE = 0, LSM303AH_XL_SPI_3_WIRE = 1, } lsm303ah_xl_sim_t; -int32_t lsm303ah_xl_spi_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_spi_mode_set(const stmdev_ctx_t *ctx, lsm303ah_xl_sim_t val); -int32_t lsm303ah_xl_spi_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_spi_mode_get(const stmdev_ctx_t *ctx, lsm303ah_xl_sim_t *val); typedef enum @@ -1121,9 +1121,9 @@ typedef enum LSM303AH_XL_I2C_ENABLE = 0, LSM303AH_XL_I2C_DISABLE = 1, } lsm303ah_xl_i2c_disable_t; -int32_t lsm303ah_xl_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_i2c_interface_set(const stmdev_ctx_t *ctx, lsm303ah_xl_i2c_disable_t val); -int32_t lsm303ah_xl_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_i2c_interface_get(const stmdev_ctx_t *ctx, lsm303ah_xl_i2c_disable_t *val); typedef enum @@ -1131,9 +1131,9 @@ typedef enum LSM303AH_MG_I2C_ENABLE = 0, LSM303AH_MG_I2C_DISABLE = 1, } lsm303ah_mg_i2c_dis_t; -int32_t lsm303ah_mg_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_i2c_interface_set(const stmdev_ctx_t *ctx, lsm303ah_mg_i2c_dis_t val); -int32_t lsm303ah_mg_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_i2c_interface_get(const stmdev_ctx_t *ctx, lsm303ah_mg_i2c_dis_t *val); typedef enum @@ -1141,9 +1141,9 @@ typedef enum LSM303AH_XL_PULL_UP_CONNECTED = 0, LSM303AH_XL_PULL_UP_DISCONNECTED = 1, } lsm303ah_xl_if_cs_pu_dis_t; -int32_t lsm303ah_xl_cs_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_cs_mode_set(const stmdev_ctx_t *ctx, lsm303ah_xl_if_cs_pu_dis_t val); -int32_t lsm303ah_xl_cs_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_cs_mode_get(const stmdev_ctx_t *ctx, lsm303ah_xl_if_cs_pu_dis_t *val); typedef enum @@ -1151,9 +1151,9 @@ typedef enum LSM303AH_XL_PUSH_PULL = 0, LSM303AH_XL_OPEN_DRAIN = 1, } lsm303ah_xl_pp_od_t; -int32_t lsm303ah_xl_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pin_mode_set(const stmdev_ctx_t *ctx, lsm303ah_xl_pp_od_t val); -int32_t lsm303ah_xl_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pin_mode_get(const stmdev_ctx_t *ctx, lsm303ah_xl_pp_od_t *val); typedef enum @@ -1161,9 +1161,9 @@ typedef enum LSM303AH_XL_ACTIVE_HIGH = 0, LSM303AH_XL_ACTIVE_LOW = 1, } lsm303ah_xl_h_lactive_t; -int32_t lsm303ah_xl_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pin_polarity_set(const stmdev_ctx_t *ctx, lsm303ah_xl_h_lactive_t val); -int32_t lsm303ah_xl_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pin_polarity_get(const stmdev_ctx_t *ctx, lsm303ah_xl_h_lactive_t *val); typedef enum @@ -1171,9 +1171,9 @@ typedef enum LSM303AH_XL_INT_PULSED = 0, LSM303AH_XL_INT_LATCHED = 1, } lsm303ah_xl_lir_t; -int32_t lsm303ah_xl_int_notification_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_int_notification_set(const stmdev_ctx_t *ctx, lsm303ah_xl_lir_t val); -int32_t lsm303ah_xl_int_notification_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_int_notification_get(const stmdev_ctx_t *ctx, lsm303ah_xl_lir_t *val); typedef struct @@ -1187,9 +1187,9 @@ typedef struct uint8_t int1_s_tap : 1; uint8_t int1_fss7 : 1; } lsm303ah_xl_pin_int1_route_t; -int32_t lsm303ah_xl_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm303ah_xl_pin_int1_route_t val); -int32_t lsm303ah_xl_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm303ah_xl_pin_int1_route_t *val); typedef struct @@ -1201,97 +1201,97 @@ typedef struct uint8_t int2_fth : 1; uint8_t int2_drdy : 1; } lsm303ah_xl_pin_int2_route_t; -int32_t lsm303ah_xl_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm303ah_xl_pin_int2_route_t val); -int32_t lsm303ah_xl_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pin_int2_route_get(const stmdev_ctx_t *ctx, lsm303ah_xl_pin_int2_route_t *val); -int32_t lsm303ah_xl_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303ah_xl_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303ah_xl_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_mg_drdy_on_pin_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_mg_drdy_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303ah_mg_drdy_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303ah_mg_drdy_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_mg_int_on_pin_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_mg_int_on_pin_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303ah_mg_int_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303ah_mg_int_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_mg_int_gen_conf_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_int_gen_conf_set(const stmdev_ctx_t *ctx, lsm303ah_int_crtl_reg_m_t *val); -int32_t lsm303ah_mg_int_gen_conf_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_int_gen_conf_get(const stmdev_ctx_t *ctx, lsm303ah_int_crtl_reg_m_t *val); -int32_t lsm303ah_mg_int_gen_source_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_int_gen_source_get(const stmdev_ctx_t *ctx, lsm303ah_int_source_reg_m_t *val); -int32_t lsm303ah_mg_int_gen_treshold_set(stmdev_ctx_t *ctx, - uint16_t val); -int32_t lsm303ah_mg_int_gen_treshold_get(stmdev_ctx_t *ctx, - uint16_t *val); +int32_t lsm303ah_mg_int_gen_threshold_set(const stmdev_ctx_t *ctx, + uint16_t val); +int32_t lsm303ah_mg_int_gen_threshold_get(const stmdev_ctx_t *ctx, + uint16_t *val); typedef enum { LSM303AH_MG_CHECK_BEFORE = 0, LSM303AH_MG_CHECK_AFTER = 1, } lsm303ah_mg_int_on_dataoff_t; -int32_t lsm303ah_mg_offset_int_conf_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_offset_int_conf_set(const stmdev_ctx_t *ctx, lsm303ah_mg_int_on_dataoff_t val); -int32_t lsm303ah_mg_offset_int_conf_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_mg_offset_int_conf_get(const stmdev_ctx_t *ctx, lsm303ah_mg_int_on_dataoff_t *val); -int32_t lsm303ah_xl_wkup_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_wkup_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303ah_xl_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303ah_xl_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303ah_xl_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303ah_xl_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_act_sleep_dur_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303ah_xl_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_tap_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303ah_xl_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303ah_xl_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303ah_xl_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303ah_xl_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303ah_xl_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303ah_xl_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303ah_xl_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM303AH_XL_ONLY_SINGLE = 0, LSM303AH_XL_ONLY_DOUBLE = 1, } lsm303ah_xl_single_double_tap_t; -int32_t lsm303ah_xl_tap_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_tap_mode_set(const stmdev_ctx_t *ctx, lsm303ah_xl_single_double_tap_t val); -int32_t lsm303ah_xl_tap_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_tap_mode_get(const stmdev_ctx_t *ctx, lsm303ah_xl_single_double_tap_t *val); -int32_t lsm303ah_xl_tap_src_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_tap_src_get(const stmdev_ctx_t *ctx, lsm303ah_tap_src_a_t *val); typedef enum @@ -1301,26 +1301,26 @@ typedef enum LSM303AH_XL_DEG_60 = 2, LSM303AH_XL_DEG_50 = 3, } lsm303ah_xl_6d_ths_t; -int32_t lsm303ah_xl_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_6d_threshold_set(const stmdev_ctx_t *ctx, lsm303ah_xl_6d_ths_t val); -int32_t lsm303ah_xl_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_6d_threshold_get(const stmdev_ctx_t *ctx, lsm303ah_xl_6d_ths_t *val); -int32_t lsm303ah_xl_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303ah_xl_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303ah_xl_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_6d_src_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_6d_src_get(const stmdev_ctx_t *ctx, lsm303ah_6d_src_a_t *val); -int32_t lsm303ah_xl_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303ah_xl_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303ah_xl_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_ff_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_ff_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303ah_xl_ff_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303ah_xl_ff_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_fifo_xl_module_batch_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_fifo_xl_module_batch_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_fifo_xl_module_batch_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_fifo_xl_module_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -1331,34 +1331,34 @@ typedef enum LSM303AH_XL_BYPASS_TO_STREAM_MODE = 4, LSM303AH_XL_STREAM_MODE = 6, } lsm303ah_xl_fmode_t; -int32_t lsm303ah_xl_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_fifo_mode_set(const stmdev_ctx_t *ctx, lsm303ah_xl_fmode_t val); -int32_t lsm303ah_xl_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_fifo_mode_get(const stmdev_ctx_t *ctx, lsm303ah_xl_fmode_t *val); -int32_t lsm303ah_xl_fifo_watermark_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_fifo_watermark_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_fifo_full_flag_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_fifo_ovr_flag_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_fifo_wtm_flag_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_fifo_data_level_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm303ah_xl_fifo_src_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_fifo_src_get(const stmdev_ctx_t *ctx, lsm303ah_fifo_src_a_t *val); -int32_t lsm303ah_xl_pedo_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pedo_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_pedo_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pedo_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -1366,53 +1366,53 @@ typedef enum LSM303AH_XL_PEDO_AT_2g = 0, LSM303AH_XL_PEDO_AT_4g = 1, } lsm303ah_xl_pedo4g_t; -int32_t lsm303ah_xl_pedo_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pedo_full_scale_set(const stmdev_ctx_t *ctx, lsm303ah_xl_pedo4g_t val); -int32_t lsm303ah_xl_pedo_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pedo_full_scale_get(const stmdev_ctx_t *ctx, lsm303ah_xl_pedo4g_t *val); -int32_t lsm303ah_xl_pedo_step_reset_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pedo_step_reset_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_pedo_step_reset_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pedo_step_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_pedo_step_detect_flag_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pedo_step_detect_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303ah_xl_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303ah_xl_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_pedo_debounce_steps_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_pedo_debounce_steps_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303ah_xl_pedo_timeout_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303ah_xl_pedo_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_pedo_steps_period_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pedo_steps_period_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm303ah_xl_pedo_steps_period_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_pedo_steps_period_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm303ah_xl_motion_data_ready_flag_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_motion_data_ready_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303ah_xl_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303ah_xl_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_motion_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_motion_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_motion_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_motion_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_tilt_data_ready_flag_get(stmdev_ctx_t *ctx, +int32_t lsm303ah_xl_tilt_data_ready_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303ah_xl_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303ah_xl_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm303ah_xl_module_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm303ah_xl_module_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm303ah_xl_module_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm303ah_xl_module_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); /** * @} diff --git a/sensor/stmemsc/lsm6ds3_STdC/driver/lsm6ds3_reg.c b/sensor/stmemsc/lsm6ds3_STdC/driver/lsm6ds3_reg.c deleted file mode 100644 index e3849a2d..00000000 --- a/sensor/stmemsc/lsm6ds3_STdC/driver/lsm6ds3_reg.c +++ /dev/null @@ -1,6873 +0,0 @@ -/** - ****************************************************************************** - * @file lsm6ds3_reg.c - * @author Sensors Software Solution Team - * @brief LSM6DS3 driver file - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -# include "lsm6ds3_reg.h" - -/** - * @defgroup LSM6DS3 - * @brief This file provides a set of functions needed to drive the - * lsm6ds3 enhanced inertial module. - * @{ - * - */ - -/** - * @defgroup LSM6DS3_Interfaces_Functions - * @brief This section provide a set of functions used to read and - * write a generic register of the device. - * MANDATORY: return 0 -> no Error. - * @{ - * - */ - -/** - * @brief Read generic device register - * - * @param ctx read / write interface definitions(ptr) - * @param reg register to read - * @param data pointer to buffer that store the data read(ptr) - * @param len number of consecutive register to read - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t __weak lsm6ds3_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) -{ - int32_t ret; - - ret = ctx->read_reg(ctx->handle, reg, data, len); - - return ret; -} - -/** - * @brief Write generic device register - * - * @param ctx read / write interface definitions(ptr) - * @param reg register to write - * @param data pointer to data to write in register reg(ptr) - * @param len number of consecutive register to write - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t __weak lsm6ds3_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len) -{ - int32_t ret; - - ret = ctx->write_reg(ctx->handle, reg, data, len); - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LSM6DS3_Sensitivity - * @brief These functions convert raw-data into engineering units. - * @{ - * - */ - -float_t lsm6ds3_from_fs2g_to_mg(int16_t lsb) -{ - return ((float_t)lsb * 61.0f / 1000.0f); -} - -float_t lsm6ds3_from_fs4g_to_mg(int16_t lsb) -{ - return ((float_t)lsb * 122.0f / 1000.0f); -} - -float_t lsm6ds3_from_fs8g_to_mg(int16_t lsb) -{ - return ((float_t)lsb * 244.0f / 1000.0f); -} - -float_t lsm6ds3_from_fs16g_to_mg(int16_t lsb) -{ - return ((float_t)lsb * 488.0f / 1000.0f); -} - -float_t lsm6ds3_from_fs125dps_to_mdps(int16_t lsb) -{ - return ((float_t)lsb * 4375.0f / 1000.0f); -} - -float_t lsm6ds3_from_fs250dps_to_mdps(int16_t lsb) -{ - return ((float_t)lsb * 8750.0f / 1000.0f); -} - -float_t lsm6ds3_from_fs500dps_to_mdps(int16_t lsb) -{ - return ((float_t)lsb * 1750.0f / 100.0f); -} - -float_t lsm6ds3_from_fs1000dps_to_mdps(int16_t lsb) -{ - return ((float_t)lsb * 35.0f); -} - -float_t lsm6ds3_from_fs2000dps_to_mdps(int16_t lsb) -{ - return ((float_t)lsb * 70.0f); -} - -float_t lsm6ds3_from_lsb_to_celsius(int16_t lsb) -{ - return ((float_t)lsb / 16.0f + 25.0f); -} - -/** - * @} - * - */ - -/** - * @defgroup LSM6DS3_Data_generation - * @brief This section groups all the functions concerning - * data generation - * @{ - * - */ - -/** - * @brief Gyroscope directional user-orientation selection.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of orient in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_gy_data_orient_set(stmdev_ctx_t *ctx, - lsm6ds3_gy_orient_t val) -{ - lsm6ds3_orient_cfg_g_t orient_cfg_g; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_ORIENT_CFG_G, - (uint8_t *)&orient_cfg_g, 1); - - if (ret == 0) - { - orient_cfg_g.orient = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_ORIENT_CFG_G, - (uint8_t *)&orient_cfg_g, 1); - } - - return ret; -} - -/** - * @brief Gyroscope directional user-orientation selection.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of orient in reg ORIENT_CFG_G - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_gy_data_orient_get(stmdev_ctx_t *ctx, - lsm6ds3_gy_orient_t *val) -{ - lsm6ds3_orient_cfg_g_t orient_cfg_g; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_ORIENT_CFG_G, - (uint8_t *)&orient_cfg_g, 1); - - switch (orient_cfg_g.orient) - { - case LSM6DS3_GY_ORIENT_XYZ: - *val = LSM6DS3_GY_ORIENT_XYZ; - break; - - case LSM6DS3_GY_ORIENT_XZY: - *val = LSM6DS3_GY_ORIENT_XZY; - break; - - case LSM6DS3_GY_ORIENT_YXZ: - *val = LSM6DS3_GY_ORIENT_YXZ; - break; - - case LSM6DS3_GY_ORIENT_YZX: - *val = LSM6DS3_GY_ORIENT_YZX; - break; - - case LSM6DS3_GY_ORIENT_ZXY: - *val = LSM6DS3_GY_ORIENT_ZXY; - break; - - case LSM6DS3_GY_ORIENT_ZYX: - *val = LSM6DS3_GY_ORIENT_ZYX; - break; - - default: - *val = LSM6DS3_GY_ORIENT_XYZ; - break; - } - - return ret; -} - -/** - * @brief angular rate sign.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of sign_g in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_gy_data_sign_set(stmdev_ctx_t *ctx, - lsm6ds3_gy_sgn_t val) -{ - lsm6ds3_orient_cfg_g_t orient_cfg_g; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_ORIENT_CFG_G, - (uint8_t *)&orient_cfg_g, 1); - - if (ret == 0) - { - orient_cfg_g.sign_g = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_ORIENT_CFG_G, - (uint8_t *)&orient_cfg_g, 1); - } - - return ret; -} - -/** - * @brief angularratesign.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of sign_g in reg ORIENT_CFG_G - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_gy_data_sign_get(stmdev_ctx_t *ctx, - lsm6ds3_gy_sgn_t *val) -{ - lsm6ds3_orient_cfg_g_t orient_cfg_g; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_ORIENT_CFG_G, - (uint8_t *)&orient_cfg_g, 1); - - switch (orient_cfg_g.sign_g) - { - case LSM6DS3_GY_SIGN_PPP: - *val = LSM6DS3_GY_SIGN_PPP; - break; - - case LSM6DS3_GY_SIGN_PPN: - *val = LSM6DS3_GY_SIGN_PPN; - break; - - case LSM6DS3_GY_SIGN_PNP: - *val = LSM6DS3_GY_SIGN_PNP; - break; - - case LSM6DS3_GY_SIGN_NPP: - *val = LSM6DS3_GY_SIGN_NPP; - break; - - case LSM6DS3_GY_SIGN_NNP: - *val = LSM6DS3_GY_SIGN_NNP; - break; - - case LSM6DS3_GY_SIGN_NPN: - *val = LSM6DS3_GY_SIGN_NPN; - break; - - case LSM6DS3_GY_SIGN_PNN: - *val = LSM6DS3_GY_SIGN_PNN; - break; - - case LSM6DS3_GY_SIGN_NNN: - *val = LSM6DS3_GY_SIGN_NNN; - break; - - default: - *val = LSM6DS3_GY_SIGN_PPP; - break; - } - - return ret; -} - -/** - * @brief Accelerometer full-scale selection.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of fs_xl in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_xl_full_scale_set(stmdev_ctx_t *ctx, - lsm6ds3_xl_fs_t val) -{ - lsm6ds3_ctrl1_xl_t ctrl1_xl; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); - - if (ret == 0) - { - ctrl1_xl.fs_xl = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); - } - - return ret; -} - -/** - * @brief Accelerometer full-scale selection.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of fs_xl in reg CTRL1_XL - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_xl_full_scale_get(stmdev_ctx_t *ctx, - lsm6ds3_xl_fs_t *val) -{ - lsm6ds3_ctrl1_xl_t ctrl1_xl; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); - - switch (ctrl1_xl.fs_xl) - { - case LSM6DS3_2g: - *val = LSM6DS3_2g; - break; - - case LSM6DS3_16g: - *val = LSM6DS3_16g; - break; - - case LSM6DS3_4g: - *val = LSM6DS3_4g; - break; - - case LSM6DS3_8g: - *val = LSM6DS3_8g; - break; - - default: - *val = LSM6DS3_2g; - break; - } - - return ret; -} - -/** - * @brief Accelerometer data rate selection.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of odr_xl in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_xl_data_rate_set(stmdev_ctx_t *ctx, - lsm6ds3_odr_xl_t val) -{ - lsm6ds3_ctrl1_xl_t ctrl1_xl; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); - - if (ret == 0) - { - ctrl1_xl.odr_xl = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); - } - - return ret; -} - -/** - * @brief Accelerometer data rate selection.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of odr_xl in reg CTRL1_XL - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_xl_data_rate_get(stmdev_ctx_t *ctx, - lsm6ds3_odr_xl_t *val) -{ - lsm6ds3_ctrl1_xl_t ctrl1_xl; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); - - switch (ctrl1_xl.odr_xl) - { - case LSM6DS3_XL_ODR_OFF: - *val = LSM6DS3_XL_ODR_OFF; - break; - - case LSM6DS3_XL_ODR_12Hz5: - *val = LSM6DS3_XL_ODR_12Hz5; - break; - - case LSM6DS3_XL_ODR_26Hz: - *val = LSM6DS3_XL_ODR_26Hz; - break; - - case LSM6DS3_XL_ODR_52Hz: - *val = LSM6DS3_XL_ODR_52Hz; - break; - - case LSM6DS3_XL_ODR_104Hz: - *val = LSM6DS3_XL_ODR_104Hz; - break; - - case LSM6DS3_XL_ODR_208Hz: - *val = LSM6DS3_XL_ODR_208Hz; - break; - - case LSM6DS3_XL_ODR_416Hz: - *val = LSM6DS3_XL_ODR_416Hz; - break; - - case LSM6DS3_XL_ODR_833Hz: - *val = LSM6DS3_XL_ODR_833Hz; - break; - - case LSM6DS3_XL_ODR_1k66Hz: - *val = LSM6DS3_XL_ODR_1k66Hz; - break; - - case LSM6DS3_XL_ODR_3k33Hz: - *val = LSM6DS3_XL_ODR_3k33Hz; - break; - - case LSM6DS3_XL_ODR_6k66Hz: - *val = LSM6DS3_XL_ODR_6k66Hz; - break; - - default: - *val = LSM6DS3_XL_ODR_OFF; - break; - } - - return ret; -} - -/** - * @brief Gyroscope UI chain full-scale selection.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of fs_g in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_gy_full_scale_set(stmdev_ctx_t *ctx, - lsm6ds3_fs_g_t val) -{ - lsm6ds3_ctrl2_g_t ctrl2_g; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL2_G, (uint8_t *)&ctrl2_g, 1); - - if (ret == 0) - { - ctrl2_g.fs_g = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL2_G, (uint8_t *)&ctrl2_g, 1); - } - - return ret; -} - -/** - * @brief Gyroscope UI chain full-scale selection.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of fs_g in reg CTRL2_G - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_gy_full_scale_get(stmdev_ctx_t *ctx, - lsm6ds3_fs_g_t *val) -{ - lsm6ds3_ctrl2_g_t ctrl2_g; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL2_G, (uint8_t *)&ctrl2_g, 1); - - switch (ctrl2_g.fs_g) - { - case LSM6DS3_250dps: - *val = LSM6DS3_250dps; - break; - - case LSM6DS3_125dps: - *val = LSM6DS3_125dps; - break; - - case LSM6DS3_500dps: - *val = LSM6DS3_500dps; - break; - - case LSM6DS3_1000dps: - *val = LSM6DS3_1000dps; - break; - - case LSM6DS3_2000dps: - *val = LSM6DS3_2000dps; - break; - - default: - *val = LSM6DS3_250dps; - break; - } - - return ret; -} - -/** - * @brief Gyroscope UI data rate selection.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of odr_g in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_gy_data_rate_set(stmdev_ctx_t *ctx, - lsm6ds3_odr_g_t val) -{ - lsm6ds3_ctrl2_g_t ctrl2_g; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL2_G, (uint8_t *)&ctrl2_g, 1); - - if (ret == 0) - { - ctrl2_g.odr_g = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL2_G, (uint8_t *)&ctrl2_g, 1); - } - - return ret; -} - -/** - * @brief Gyroscope UI data rate selection.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of odr_g in reg CTRL2_G - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_gy_data_rate_get(stmdev_ctx_t *ctx, - lsm6ds3_odr_g_t *val) -{ - lsm6ds3_ctrl2_g_t ctrl2_g; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL2_G, (uint8_t *)&ctrl2_g, 1); - - switch (ctrl2_g.odr_g) - { - case LSM6DS3_GY_ODR_OFF: - *val = LSM6DS3_GY_ODR_OFF; - break; - - case LSM6DS3_GY_ODR_12Hz5: - *val = LSM6DS3_GY_ODR_12Hz5; - break; - - case LSM6DS3_GY_ODR_26Hz: - *val = LSM6DS3_GY_ODR_26Hz; - break; - - case LSM6DS3_GY_ODR_52Hz: - *val = LSM6DS3_GY_ODR_52Hz; - break; - - case LSM6DS3_GY_ODR_104Hz: - *val = LSM6DS3_GY_ODR_104Hz; - break; - - case LSM6DS3_GY_ODR_208Hz: - *val = LSM6DS3_GY_ODR_208Hz; - break; - - case LSM6DS3_GY_ODR_416Hz: - *val = LSM6DS3_GY_ODR_416Hz; - break; - - case LSM6DS3_GY_ODR_833Hz: - *val = LSM6DS3_GY_ODR_833Hz; - break; - - case LSM6DS3_GY_ODR_1k66Hz: - *val = LSM6DS3_GY_ODR_1k66Hz; - break; - - default: - *val = LSM6DS3_GY_ODR_OFF; - break; - } - - return ret; -} - -/** - * @brief Blockdataupdate.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of bdu in reg CTRL3_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_ctrl3_c_t ctrl3_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - - if (ret == 0) - { - ctrl3_c.bdu = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - } - - return ret; -} - -/** - * @brief Blockdataupdate.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of bdu in reg CTRL3_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_ctrl3_c_t ctrl3_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - *val = (uint8_t)ctrl3_c.bdu; - - return ret; -} - -/** - * @brief High-performance operating mode for accelerometer.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of xl_hm_mode in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_xl_power_mode_set(stmdev_ctx_t *ctx, - lsm6ds3_xl_hm_mode_t val) -{ - lsm6ds3_ctrl6_c_t ctrl6_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL6_C, (uint8_t *)&ctrl6_c, 1); - - if (ret == 0) - { - ctrl6_c.xl_hm_mode = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL6_C, (uint8_t *)&ctrl6_c, 1); - } - - return ret; -} - -/** - * @brief High-performance operating mode for accelerometer.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of xl_hm_mode in reg CTRL6_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_xl_power_mode_get(stmdev_ctx_t *ctx, - lsm6ds3_xl_hm_mode_t *val) -{ - lsm6ds3_ctrl6_c_t ctrl6_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL6_C, (uint8_t *)&ctrl6_c, 1); - - switch (ctrl6_c.xl_hm_mode) - { - case LSM6DS3_XL_HIGH_PERFORMANCE: - *val = LSM6DS3_XL_HIGH_PERFORMANCE; - break; - - case LSM6DS3_XL_NORMAL: - *val = LSM6DS3_XL_NORMAL; - break; - - default: - *val = LSM6DS3_XL_HIGH_PERFORMANCE; - break; - } - - return ret; -} - -/** - * @brief Source register rounding function on ADD HERE ROUNDING REGISTERS.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of rounding_status in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_rounding_on_status_set(stmdev_ctx_t *ctx, - lsm6ds3_rnd_stat_t val) -{ - lsm6ds3_ctrl7_g_t ctrl7_g; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t *)&ctrl7_g, 1); - - if (ret == 0) - { - ctrl7_g.rounding_status = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t *)&ctrl7_g, 1); - } - - return ret; -} - -/** - * @brief Source register rounding function on ADD HERE ROUNDING REGISTERS.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of rounding_status in reg CTRL7_G - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_rounding_on_status_get(stmdev_ctx_t *ctx, - lsm6ds3_rnd_stat_t *val) -{ - lsm6ds3_ctrl7_g_t ctrl7_g; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t *)&ctrl7_g, 1); - - switch (ctrl7_g.rounding_status) - { - case LSM6DS3_STAT_RND_DISABLE: - *val = LSM6DS3_STAT_RND_DISABLE; - break; - - case LSM6DS3_STAT_RND_ENABLE: - *val = LSM6DS3_STAT_RND_ENABLE; - break; - - default: - *val = LSM6DS3_STAT_RND_DISABLE; - break; - } - - return ret; -} - -/** - * @brief High-performance operating mode disable for gyroscope.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of g_hm_mode in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_gy_power_mode_set(stmdev_ctx_t *ctx, - lsm6ds3_g_hm_mode_t val) -{ - lsm6ds3_ctrl7_g_t ctrl7_g; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t *)&ctrl7_g, 1); - - if (ret == 0) - { - ctrl7_g.g_hm_mode = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t *)&ctrl7_g, 1); - } - - return ret; -} - -/** - * @brief High-performance operating mode disable for gyroscope.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of g_hm_mode in reg CTRL7_G - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_gy_power_mode_get(stmdev_ctx_t *ctx, - lsm6ds3_g_hm_mode_t *val) -{ - lsm6ds3_ctrl7_g_t ctrl7_g; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t *)&ctrl7_g, 1); - - switch (ctrl7_g.g_hm_mode) - { - case LSM6DS3_GY_HIGH_PERFORMANCE: - *val = LSM6DS3_GY_HIGH_PERFORMANCE; - break; - - case LSM6DS3_GY_NORMAL: - *val = LSM6DS3_GY_NORMAL; - break; - - default: - *val = LSM6DS3_GY_HIGH_PERFORMANCE; - break; - } - - return ret; -} - -/** - * @brief Accelerometer X-axis output enable/disable.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of xen_xl in reg CTRL9_XL - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_xl_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_ctrl9_xl_t ctrl9_xl; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - - if (ret == 0) - { - ctrl9_xl.xen_xl = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - } - - return ret; -} - -/** - * @brief Accelerometer X-axis output enable/disable.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of xen_xl in reg CTRL9_XL - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_xl_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_ctrl9_xl_t ctrl9_xl; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - *val = (uint8_t)ctrl9_xl.xen_xl; - - return ret; -} - -/** - * @brief Accelerometer Y-axis output enable/disable.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of yen_xl in reg CTRL9_XL - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_xl_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_ctrl9_xl_t ctrl9_xl; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - - if (ret == 0) - { - ctrl9_xl.yen_xl = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - } - - return ret; -} - -/** - * @brief Accelerometer Y-axis output enable/disable.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of yen_xl in reg CTRL9_XL - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_xl_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_ctrl9_xl_t ctrl9_xl; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - *val = (uint8_t)ctrl9_xl.yen_xl; - - return ret; -} - -/** - * @brief Accelerometer Z-axis output enable/disable.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of zen_xl in reg CTRL9_XL - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_xl_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_ctrl9_xl_t ctrl9_xl; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - - if (ret == 0) - { - ctrl9_xl.zen_xl = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - } - - return ret; -} - -/** - * @brief Accelerometer Z-axis output enable/disable.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of zen_xl in reg CTRL9_XL - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_xl_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_ctrl9_xl_t ctrl9_xl; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - *val = (uint8_t)ctrl9_xl.zen_xl; - - return ret; -} - -/** - * @brief Gyroscope pitch axis (X) output enable/disable.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of xen_g in reg CTRL10_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_gy_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_ctrl10_c_t ctrl10_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1); - - if (ret == 0) - { - ctrl10_c.xen_g = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1); - } - - return ret; -} - -/** - * @brief Gyroscope pitch axis (X) output enable/disable.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of xen_g in reg CTRL10_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_gy_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_ctrl10_c_t ctrl10_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1); - *val = (uint8_t)ctrl10_c.xen_g; - - return ret; -} - -/** - * @brief Gyroscope pitch axis (Y) output enable/disable.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of yen_g in reg CTRL10_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_gy_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_ctrl10_c_t ctrl10_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1); - - if (ret == 0) - { - ctrl10_c.yen_g = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1); - } - - return ret; -} - -/** - * @brief Gyroscope pitch axis (Y) output enable/disable.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of yen_g in reg CTRL10_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_gy_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_ctrl10_c_t ctrl10_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1); - *val = (uint8_t)ctrl10_c.yen_g; - - return ret; -} - -/** - * @brief Gyroscope pitch axis (Z) output enable/disable.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of zen_g in reg CTRL10_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_gy_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_ctrl10_c_t ctrl10_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1); - - if (ret == 0) - { - ctrl10_c.zen_g = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1); - } - - return ret; -} - -/** - * @brief Gyroscope pitch axis (Z) output enable/disable.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of zen_g in reg CTRL10_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_gy_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_ctrl10_c_t ctrl10_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1); - *val = (uint8_t)ctrl10_c.zen_g; - - return ret; -} - -/** - * @brief Read all the interrupt/status flag of the device. ELENCA I REGISTRI[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val Read all the interrupt flag of the device: - * WAKE_UP_SRC, TAP_SRC, D6D_SRC, FUNC_SRC. - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_all_sources_get(stmdev_ctx_t *ctx, - lsm6ds3_all_src_t *val) -{ - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_SRC, - (uint8_t *) & (val->wake_up_src), 1); - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_SRC, - (uint8_t *) & (val->tap_src), 1); - } - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_D6D_SRC, - (uint8_t *) & (val->d6d_src), 1); - } - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_SRC, - (uint8_t *) & (val->func_src), 1); - } - - return ret; -} - -/** - * @brief The STATUS_REG register of the device.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val The STATUS_REG register of the device. - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_status_reg_get(stmdev_ctx_t *ctx, - lsm6ds3_status_reg_t *val) -{ - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_STATUS_REG, (uint8_t *)val, 1); - - return ret; -} - -/** - * @brief Accelerometer new data available.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of xlda in reg STATUS_REG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_xl_flag_data_ready_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - lsm6ds3_status_reg_t status_reg; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_STATUS_REG, - (uint8_t *)&status_reg, 1); - *val = (uint8_t)status_reg.xlda; - - return ret; -} - -/** - * @brief Gyroscope new data available.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of gda in reg STATUS_REG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_gy_flag_data_ready_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - lsm6ds3_status_reg_t status_reg; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_STATUS_REG, - (uint8_t *)&status_reg, 1); - *val = (uint8_t)status_reg.gda; - - return ret; -} - -/** - * @brief Temperature new data available.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of tda in reg STATUS_REG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_temp_flag_data_ready_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - lsm6ds3_status_reg_t status_reg; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_STATUS_REG, - (uint8_t *)&status_reg, 1); - *val = (uint8_t)status_reg.tda; - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LSM6DS3_Timestamp - * @brief This section groups all the functions that manage the - * timestamp generation. - * @{ - * - */ - -/** - * @brief Timestamp first byte data output register (r). The value is - * expressed as a 24-bit word and the bit resolution is defined - * by setting the value in WAKE_UP_DUR (5Ch).[get] - * - * @param ctx read / write interface definitions(ptr) - * @param buff buffer that stores data read - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) -{ - uint8_t buff[3]; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_TIMESTAMP0_REG, buff, 3); - *val = buff[2]; - *val = (*val * 256U) + buff[1]; - *val = (*val * 256U) + buff[0]; - - return ret; -} - -/** - * @brief Reset the timer.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param buff buffer that stores data to be write - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_timestamp_rst_set(stmdev_ctx_t *ctx) -{ - int32_t ret; - - uint8_t rst_val = 0xAA; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_TIMESTAMP2_REG, &rst_val, 1); - - return ret; -} - -/** - * @brief Timestamp count enable, output data are collected in - * TIMESTAMP0_REG (40h), TIMESTAMP1_REG (41h), - * TIMESTAMP2_REG (42h) register.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of timer_en in reg TAP_CFG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_tap_cfg_t tap_cfg; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1); - - if (ret == 0) - { - tap_cfg.timer_en = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1); - } - - return ret; -} - -/** - * @brief Timestamp count enable, output data are collected in - * TIMESTAMP0_REG (40h), TIMESTAMP1_REG (41h), - * TIMESTAMP2_REG (42h) register.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of timer_en in reg TAP_CFG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_tap_cfg_t tap_cfg; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1); - *val = (uint8_t)tap_cfg.timer_en; - - return ret; -} - -/** - * @brief Timestamp register resolution setting.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of timer_hr in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_timestamp_res_set(stmdev_ctx_t *ctx, - lsm6ds3_ts_res_t val) -{ - lsm6ds3_wake_up_dur_t wake_up_dur; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_DUR, - (uint8_t *)&wake_up_dur, 1); - - if (ret == 0) - { - wake_up_dur.timer_hr = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_WAKE_UP_DUR, - (uint8_t *)&wake_up_dur, 1); - } - - return ret; -} - -/** - * @brief Timestamp register resolution setting.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of timer_hr in reg WAKE_UP_DUR - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_timestamp_res_get(stmdev_ctx_t *ctx, - lsm6ds3_ts_res_t *val) -{ - lsm6ds3_wake_up_dur_t wake_up_dur; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_DUR, - (uint8_t *)&wake_up_dur, 1); - - switch (wake_up_dur.timer_hr) - { - case LSM6DS3_LSB_6ms4: - *val = LSM6DS3_LSB_6ms4; - break; - - case LSM6DS3_LSB_25us: - *val = LSM6DS3_LSB_25us; - break; - - default: - *val = LSM6DS3_LSB_6ms4; - break; - } - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LSM6DS3_Dataoutput - * @brief This section groups all the data output functions. - * @{ - * - */ - -/** - * @brief Circular burst-mode (rounding) read from output registers - * through the primary interface.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of rounding in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_rounding_mode_set(stmdev_ctx_t *ctx, - lsm6ds3_rounding_t val) -{ - lsm6ds3_ctrl5_c_t ctrl5_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t *)&ctrl5_c, 1); - - if (ret == 0) - { - ctrl5_c.rounding = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t *)&ctrl5_c, 1); - } - - return ret; -} - -/** - * @brief Circular burst-mode (rounding) read from output registers - * through the primary interface.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of rounding in reg CTRL5_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_rounding_mode_get(stmdev_ctx_t *ctx, - lsm6ds3_rounding_t *val) -{ - lsm6ds3_ctrl5_c_t ctrl5_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t *)&ctrl5_c, 1); - - switch (ctrl5_c.rounding) - { - case LSM6DS3_ROUND_DISABLE: - *val = LSM6DS3_ROUND_DISABLE; - break; - - case LSM6DS3_ROUND_XL: - *val = LSM6DS3_ROUND_XL; - break; - - case LSM6DS3_ROUND_GY: - *val = LSM6DS3_ROUND_GY; - break; - - case LSM6DS3_ROUND_GY_XL: - *val = LSM6DS3_ROUND_GY_XL; - break; - - case LSM6DS3_ROUND_SH1_TO_SH6: - *val = LSM6DS3_ROUND_SH1_TO_SH6; - break; - - case LSM6DS3_ROUND_XL_SH1_TO_SH6: - *val = LSM6DS3_ROUND_XL_SH1_TO_SH6; - break; - - case LSM6DS3_ROUND_GY_XL_SH1_TO_SH12: - *val = LSM6DS3_ROUND_GY_XL_SH1_TO_SH12; - break; - - case LSM6DS3_ROUND_GY_XL_SH1_TO_SH6: - *val = LSM6DS3_ROUND_GY_XL_SH1_TO_SH6; - break; - - default: - *val = LSM6DS3_ROUND_DISABLE; - break; - } - - return ret; -} - -/** - * @brief Temperature data output register (r). L and H registers together - * express a 16-bit word in two’s complement.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param buff buffer that stores data read - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) -{ - uint8_t buff[2]; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_OUT_TEMP_L, buff, 2); - *val = (int16_t)buff[1]; - *val = (*val * 256) + (int16_t)buff[0]; - - return ret; -} - -/** - * @brief Angular rate sensor. The value is expressed as a 16-bit word - * in two’s complement..[get] - * - * @param ctx read / write interface definitions(ptr) - * @param buff buffer that stores data read - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) -{ - uint8_t buff[6]; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_OUTX_L_G, buff, 6); - val[0] = (int16_t)buff[1]; - val[0] = (val[0] * 256) + (int16_t)buff[0]; - val[1] = (int16_t)buff[3]; - val[1] = (val[1] * 256) + (int16_t)buff[2]; - val[2] = (int16_t)buff[5]; - val[2] = (val[2] * 256) + (int16_t)buff[4]; - - return ret; -} - -/** - * @brief Linear acceleration output register. The value is expressed - * as a 16-bit word in two’s complement.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param buff buffer that stores data read - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) -{ - uint8_t buff[6]; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_OUTX_L_XL, buff, 6); - val[0] = (int16_t)buff[1]; - val[0] = (val[0] * 256) + (int16_t)buff[0]; - val[1] = (int16_t)buff[3]; - val[1] = (val[1] * 256) + (int16_t)buff[2]; - val[2] = (int16_t)buff[5]; - val[2] = (val[2] * 256) + (int16_t)buff[4]; - - return ret; -} - -/** - * @brief fifo_raw_data: [get] read data in FIFO. - * - * @param stmdev_ctx_t *ctx: read / write interface definitions - * @param uint8_t *: data buffer to store FIFO data. - * @param uint8_t : number of data to read from FIFO. - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer, - uint8_t len) -{ - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_DATA_OUT_L, buffer, len); - - return ret; -} - -/** - * @brief Step counter output register..[get] - * - * @param ctx read / write interface definitions(ptr) - * @param buff buffer that stores data read - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val) -{ - uint8_t buff[2]; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_STEP_COUNTER_L, buff, 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; - - return ret; -} - -/** - * @brief magnetometer raw data.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param buff buffer that stores data read - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_mag_calibrated_raw_get(stmdev_ctx_t *ctx, - int16_t *val) -{ - uint8_t buff[6]; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_OUT_MAG_RAW_X_L, buff, 6); - val[0] = (int16_t)buff[1]; - val[0] = (val[0] * 256) + (int16_t)buff[0]; - val[1] = (int16_t)buff[3]; - val[1] = (val[1] * 256) + (int16_t)buff[2]; - val[2] = (int16_t)buff[5]; - val[2] = (val[2] * 256) + (int16_t)buff[4]; - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LSM6DS3_Common - * @brief This section groups common useful functions. - * @{ - * - */ - -/** - * @brief Enable access to the embedded functions.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of func_cfg_en in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_mem_bank_set(stmdev_ctx_t *ctx, - lsm6ds3_func_cfg_en_t val) -{ - lsm6ds3_func_cfg_access_t func_cfg_access; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_CFG_ACCESS, - (uint8_t *)&func_cfg_access, 1); - - if (ret == 0) - { - func_cfg_access.func_cfg_en = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_FUNC_CFG_ACCESS, - (uint8_t *)&func_cfg_access, 1); - } - - return ret; -} - -/** - * @brief Enable access to the embedded functions.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of func_cfg_en in reg FUNC_CFG_ACCESS - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_mem_bank_get(stmdev_ctx_t *ctx, - lsm6ds3_func_cfg_en_t *val) -{ - lsm6ds3_func_cfg_access_t func_cfg_access; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_CFG_ACCESS, - (uint8_t *)&func_cfg_access, 1); - - switch (func_cfg_access.func_cfg_en) - { - case LSM6DS3_USER_BANK: - *val = LSM6DS3_USER_BANK; - break; - - case LSM6DS3_EMBEDDED_FUNC_BANK: - *val = LSM6DS3_EMBEDDED_FUNC_BANK; - break; - - default: - *val = LSM6DS3_USER_BANK; - break; - } - - return ret; -} - -/** - * @brief DeviceWhoamI..[get] - * - * @param ctx read / write interface definitions(ptr) - * @param buff buffer that stores data read - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) -{ - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_WHO_AM_I, buff, 1); - - return ret; -} - -/** - * @brief Software reset. Restore the default values in user registers.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of sw_reset in reg CTRL3_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_reset_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_ctrl3_c_t ctrl3_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - - if (ret == 0) - { - ctrl3_c.sw_reset = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - } - - return ret; -} - -/** - * @brief Software reset. Restore the default values in user registers.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of sw_reset in reg CTRL3_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_reset_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_ctrl3_c_t ctrl3_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - *val = (uint8_t)ctrl3_c.sw_reset; - - return ret; -} - -/** - * @brief Big/Little Endian Data selection.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of ble in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_data_format_set(stmdev_ctx_t *ctx, lsm6ds3_ble_t val) -{ - lsm6ds3_ctrl3_c_t ctrl3_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - - if (ret == 0) - { - ctrl3_c.ble = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - } - - return ret; -} - -/** - * @brief Big/Little Endian Data selection.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of ble in reg CTRL3_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_data_format_get(stmdev_ctx_t *ctx, lsm6ds3_ble_t *val) -{ - lsm6ds3_ctrl3_c_t ctrl3_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - - switch (ctrl3_c.ble) - { - case LSM6DS3_LSB_AT_LOW_ADD: - *val = LSM6DS3_LSB_AT_LOW_ADD; - break; - - case LSM6DS3_MSB_AT_LOW_ADD: - *val = LSM6DS3_MSB_AT_LOW_ADD; - break; - - default: - *val = LSM6DS3_LSB_AT_LOW_ADD; - break; - } - - return ret; -} - -/** - * @brief Register address automatically incremented during a multiple - * byte access with a serial interface.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of if_inc in reg CTRL3_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_ctrl3_c_t ctrl3_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - - if (ret == 0) - { - ctrl3_c.if_inc = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - } - - return ret; -} - -/** - * @brief Register address automatically incremented during a multiple - * byte access with a serial interface.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of if_inc in reg CTRL3_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_ctrl3_c_t ctrl3_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - *val = (uint8_t)ctrl3_c.if_inc; - - return ret; -} - -/** - * @brief Reboot memory content. Reload the calibration parameters.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of boot in reg CTRL3_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_boot_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_ctrl3_c_t ctrl3_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - - if (ret == 0) - { - ctrl3_c.boot = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - } - - return ret; -} - -/** - * @brief Reboot memory content. Reload the calibration parameters.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of boot in reg CTRL3_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_boot_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_ctrl3_c_t ctrl3_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - *val = (uint8_t)ctrl3_c.boot; - - return ret; -} - -/** - * @brief Linear acceleration sensor self-test enable.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of st_xl in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_xl_self_test_set(stmdev_ctx_t *ctx, - lsm6ds3_st_xl_t val) -{ - lsm6ds3_ctrl5_c_t ctrl5_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t *)&ctrl5_c, 1); - - if (ret == 0) - { - ctrl5_c.st_xl = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t *)&ctrl5_c, 1); - } - - return ret; -} - -/** - * @brief Linear acceleration sensor self-test enable.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of st_xl in reg CTRL5_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_xl_self_test_get(stmdev_ctx_t *ctx, - lsm6ds3_st_xl_t *val) -{ - lsm6ds3_ctrl5_c_t ctrl5_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t *)&ctrl5_c, 1); - - switch (ctrl5_c.st_xl) - { - case LSM6DS3_XL_ST_DISABLE: - *val = LSM6DS3_XL_ST_DISABLE; - break; - - case LSM6DS3_XL_ST_POSITIVE: - *val = LSM6DS3_XL_ST_POSITIVE; - break; - - case LSM6DS3_XL_ST_NEGATIVE: - *val = LSM6DS3_XL_ST_NEGATIVE; - break; - - default: - *val = LSM6DS3_XL_ST_DISABLE; - break; - } - - return ret; -} - -/** - * @brief Angular rate sensor self-test enable.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of st_g in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_gy_self_test_set(stmdev_ctx_t *ctx, - lsm6ds3_st_g_t val) -{ - lsm6ds3_ctrl5_c_t ctrl5_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t *)&ctrl5_c, 1); - - if (ret == 0) - { - ctrl5_c.st_g = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t *)&ctrl5_c, 1); - } - - return ret; -} - -/** - * @brief Angular rate sensor self-test enable.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of st_g in reg CTRL5_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_gy_self_test_get(stmdev_ctx_t *ctx, - lsm6ds3_st_g_t *val) -{ - lsm6ds3_ctrl5_c_t ctrl5_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t *)&ctrl5_c, 1); - - switch (ctrl5_c.st_g) - { - case LSM6DS3_GY_ST_DISABLE: - *val = LSM6DS3_GY_ST_DISABLE; - break; - - case LSM6DS3_GY_ST_POSITIVE: - *val = LSM6DS3_GY_ST_POSITIVE; - break; - - case LSM6DS3_GY_ST_NEGATIVE: - *val = LSM6DS3_GY_ST_NEGATIVE; - break; - - default: - *val = LSM6DS3_GY_ST_DISABLE; - break; - } - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LSM6DS3_Filters - * @brief This section group all the functions concerning the - * filters configuration - * @{ - * - */ - -/** - * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends - * (XL and Gyro independently masked).[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of drdy_mask in reg CTRL4_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_filter_settling_mask_set(stmdev_ctx_t *ctx, - uint8_t val) -{ - lsm6ds3_ctrl4_c_t ctrl4_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1); - - if (ret == 0) - { - ctrl4_c.drdy_mask = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1); - } - - return ret; -} - -/** - * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends - * (XL and Gyro independently masked).[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of drdy_mask in reg CTRL4_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_filter_settling_mask_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - lsm6ds3_ctrl4_c_t ctrl4_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1); - *val = (uint8_t)ctrl4_c.drdy_mask; - - return ret; -} - -/** - * @brief Gyroscope high-pass filter cutoff frequency selection.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of hpcf_g in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_gy_hp_bandwidth_set(stmdev_ctx_t *ctx, - lsm6ds3_hpcf_g_t val) -{ - lsm6ds3_ctrl7_g_t ctrl7_g; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t *)&ctrl7_g, 1); - - if (ret == 0) - { - ctrl7_g.hpcf_g = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t *)&ctrl7_g, 1); - } - - return ret; -} - -/** - * @brief Gyroscope high-pass filter cutoff frequency selection.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of hpcf_g in reg CTRL7_G - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_gy_hp_bandwidth_get(stmdev_ctx_t *ctx, - lsm6ds3_hpcf_g_t *val) -{ - lsm6ds3_ctrl7_g_t ctrl7_g; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t *)&ctrl7_g, 1); - - switch (ctrl7_g.hpcf_g) - { - case LSM6DS3_HP_CUT_OFF_8mHz1: - *val = LSM6DS3_HP_CUT_OFF_8mHz1; - break; - - case LSM6DS3_HP_CUT_OFF_32mHz4: - *val = LSM6DS3_HP_CUT_OFF_32mHz4; - break; - - case LSM6DS3_HP_CUT_OFF_2Hz07: - *val = LSM6DS3_HP_CUT_OFF_2Hz07; - break; - - case LSM6DS3_HP_CUT_OFF_16Hz32: - *val = LSM6DS3_HP_CUT_OFF_16Hz32; - break; - - default: - *val = LSM6DS3_HP_CUT_OFF_8mHz1; - break; - } - - return ret; -} - -/** - * @brief Gyro digital HP filter reset.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of hp_g_rst in reg CTRL7_G - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_gy_hp_reset_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_ctrl7_g_t ctrl7_g; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t *)&ctrl7_g, 1); - - if (ret == 0) - { - ctrl7_g.hp_g_rst = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t *)&ctrl7_g, 1); - } - - return ret; -} - -/** - * @brief Gyro digital HP filter reset.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of hp_g_rst in reg CTRL7_G - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_gy_hp_reset_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_ctrl7_g_t ctrl7_g; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t *)&ctrl7_g, 1); - *val = (uint8_t)ctrl7_g.hp_g_rst; - - return ret; -} - -/** - * @brief Accelerometer slope filter and high-pass filter configuration - * and cut-off setting.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of hp_slope_xl_en in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, - lsm6ds3_hp_bw_t val) -{ - lsm6ds3_ctrl8_xl_t ctrl8_xl; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); - - if (ret == 0) - { - ctrl8_xl.hp_slope_xl_en = PROPERTY_ENABLE; - ctrl8_xl.hpcf_xl = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); - } - - return ret; -} - -/** - * @brief Accelerometer slope filter and high-pass filter configuration - * and cut-off setting.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of hp_slope_xl_en in reg CTRL8_XL - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, - lsm6ds3_hp_bw_t *val) -{ - lsm6ds3_ctrl8_xl_t ctrl8_xl; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); - - switch (ctrl8_xl.hpcf_xl) - { - case LSM6DS3_XL_HP_ODR_DIV_4: - *val = LSM6DS3_XL_HP_ODR_DIV_4; - break; - - case LSM6DS3_XL_HP_ODR_DIV_100: - *val = LSM6DS3_XL_HP_ODR_DIV_100; - break; - - case LSM6DS3_XL_HP_ODR_DIV_9: - *val = LSM6DS3_XL_HP_ODR_DIV_9; - break; - - case LSM6DS3_XL_HP_ODR_DIV_400: - *val = LSM6DS3_XL_HP_ODR_DIV_400; - break; - - default: - *val = LSM6DS3_XL_HP_ODR_DIV_4; - break; - } - - return ret; -} - -/** - * @brief Accelerometer low-pass filter configuration and - * cut-off setting.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of lpf2_xl_en in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, - lsm6ds3_lp_bw_t val) -{ - lsm6ds3_ctrl8_xl_t ctrl8_xl; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); - - if (ret == 0) - { - ctrl8_xl.lpf2_xl_en = PROPERTY_ENABLE; - ctrl8_xl.hpcf_xl = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); - } - - return ret; -} - -/** - * @brief Accelerometer low-pass filter configuration and cut-off - * setting.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of lpf2_xl_en in reg CTRL8_XL - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, - lsm6ds3_lp_bw_t *val) -{ - lsm6ds3_ctrl8_xl_t ctrl8_xl; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); - - switch (ctrl8_xl.hpcf_xl) - { - case LSM6DS3_XL_LP_ODR_DIV_50: - *val = LSM6DS3_XL_LP_ODR_DIV_50; - break; - - case LSM6DS3_XL_LP_ODR_DIV_100: - *val = LSM6DS3_XL_LP_ODR_DIV_100; - break; - - case LSM6DS3_XL_LP_ODR_DIV_9: - *val = LSM6DS3_XL_LP_ODR_DIV_9; - break; - - case LSM6DS3_XL_LP_ODR_DIV_400: - *val = LSM6DS3_XL_LP_ODR_DIV_400; - break; - - default: - *val = LSM6DS3_XL_LP_ODR_DIV_50; - break; - } - - return ret; -} - -/** - * @brief Anti-aliasing filter bandwidth selection.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of bw_xl in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_xl_filter_analog_set(stmdev_ctx_t *ctx, - lsm6ds3_bw_xl_t val) -{ - lsm6ds3_ctrl1_xl_t ctrl1_xl; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); - - if (ret == 0) - { - ctrl1_xl.bw_xl = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); - } - - return ret; -} - -/** - * @brief Anti-aliasing filter bandwidth selection.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of bw_xl in reg CTRL1_XL - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_xl_filter_analog_get(stmdev_ctx_t *ctx, - lsm6ds3_bw_xl_t *val) -{ - lsm6ds3_ctrl1_xl_t ctrl1_xl; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1); - - switch (ctrl1_xl.bw_xl) - { - case LSM6DS3_ANTI_ALIASING_400Hz: - *val = LSM6DS3_ANTI_ALIASING_400Hz; - break; - - case LSM6DS3_ANTI_ALIASING_200Hz: - *val = LSM6DS3_ANTI_ALIASING_200Hz; - break; - - case LSM6DS3_ANTI_ALIASING_100Hz: - *val = LSM6DS3_ANTI_ALIASING_100Hz; - break; - - case LSM6DS3_ANTI_ALIASING_50Hz: - *val = LSM6DS3_ANTI_ALIASING_50Hz; - break; - - default: - *val = LSM6DS3_ANTI_ALIASING_400Hz; - break; - } - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LSM6DS3_Serial_interface - * @brief This section groups all the functions concerning main - * serial interface management (not auxiliary) - * @{ - * - */ - -/** - * @brief SPI Serial Interface Mode selection.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of sim in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_spi_mode_set(stmdev_ctx_t *ctx, lsm6ds3_sim_t val) -{ - lsm6ds3_ctrl3_c_t ctrl3_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - - if (ret == 0) - { - ctrl3_c.sim = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - } - - return ret; -} - -/** - * @brief SPI Serial Interface Mode selection.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of sim in reg CTRL3_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_spi_mode_get(stmdev_ctx_t *ctx, lsm6ds3_sim_t *val) -{ - lsm6ds3_ctrl3_c_t ctrl3_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - - switch (ctrl3_c.sim) - { - case LSM6DS3_SPI_4_WIRE: - *val = LSM6DS3_SPI_4_WIRE; - break; - - case LSM6DS3_SPI_3_WIRE: - *val = LSM6DS3_SPI_3_WIRE; - break; - - default: - *val = LSM6DS3_SPI_4_WIRE; - break; - } - - return ret; -} - -/** - * @brief Disable / Enable I2C interface.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of i2c_disable in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_i2c_interface_set(stmdev_ctx_t *ctx, - lsm6ds3_i2c_dis_t val) -{ - lsm6ds3_ctrl4_c_t ctrl4_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1); - - if (ret == 0) - { - ctrl4_c.i2c_disable = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1); - } - - return ret; -} - -/** - * @brief Disable / Enable I2C interface.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of i2c_disable in reg CTRL4_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_i2c_interface_get(stmdev_ctx_t *ctx, - lsm6ds3_i2c_dis_t *val) -{ - lsm6ds3_ctrl4_c_t ctrl4_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1); - - switch (ctrl4_c.i2c_disable) - { - case LSM6DS3_I2C_ENABLE: - *val = LSM6DS3_I2C_ENABLE; - break; - - case LSM6DS3_I2C_DISABLE: - *val = LSM6DS3_I2C_DISABLE; - break; - - default: - *val = LSM6DS3_I2C_ENABLE; - break; - } - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LSM6DS3_Interrupt_pins - * @brief This section groups all the functions that manage - * interrupt pins - * @{ - * - */ - -/** - * @brief Select the signal that need to route on int1 pad.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val Select the signal that need to route on int1 pad. - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_pin_int1_route_set(stmdev_ctx_t *ctx, - lsm6ds3_int1_route_t *val) -{ - lsm6ds3_int1_ctrl_t int1_ctrl; - lsm6ds3_md1_cfg_t md1_cfg; - lsm6ds3_master_config_t master_config; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, - (uint8_t *)&master_config, 1); - - if (ret == 0) - { - int1_ctrl.int1_drdy_xl = val->int1_drdy_xl; - int1_ctrl.int1_drdy_g = val->int1_drdy_g; - int1_ctrl.int1_boot = val->int1_boot; - int1_ctrl.int1_fth = val->int1_fth; - int1_ctrl.int1_fifo_ovr = val->int1_fifo_ovr; - int1_ctrl.int1_full_flag = val->int1_full_flag; - int1_ctrl.int1_sign_mot = val->int1_sign_mot; - int1_ctrl.int1_step_detector = val->int1_step_detector; - md1_cfg.int1_timer = val->int1_timer; - md1_cfg.int1_tilt = val->int1_tilt; - md1_cfg.int1_6d = val->int1_6d; - md1_cfg.int1_double_tap = val->int1_double_tap; - md1_cfg.int1_ff = val->int1_ff; - md1_cfg.int1_wu = val->int1_wu; - md1_cfg.int1_single_tap = val->int1_single_tap; - md1_cfg.int1_inact_state = val->int1_inact_state; - master_config.drdy_on_int1 = val->drdy_on_int1; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); - - if (ret == 0) - { - ret = lsm6ds3_write_reg(ctx, LSM6DS3_MD1_CFG, (uint8_t *)&md1_cfg, 1); - } - - if (ret == 0) - { - ret = lsm6ds3_write_reg(ctx, LSM6DS3_MASTER_CONFIG, - (uint8_t *)&master_config, 1); - } - } - - return ret; -} - -/** - * @brief Select the signal that need to route on int1 pad.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val Select the signal that need to route on int1 pad. - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_pin_int1_route_get(stmdev_ctx_t *ctx, - lsm6ds3_int1_route_t *val) -{ - lsm6ds3_int1_ctrl_t int1_ctrl; - lsm6ds3_md1_cfg_t md1_cfg; - lsm6ds3_master_config_t master_config; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_MD1_CFG, (uint8_t *)&md1_cfg, 1); - } - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, - (uint8_t *)&master_config, 1); - } - - if (ret == 0) - { - val->int1_drdy_xl = int1_ctrl.int1_drdy_xl; - val->int1_drdy_g = int1_ctrl.int1_drdy_g; - val->int1_boot = int1_ctrl.int1_boot; - val->int1_fth = int1_ctrl.int1_fth; - val->int1_fifo_ovr = int1_ctrl.int1_fifo_ovr; - val->int1_full_flag = int1_ctrl.int1_full_flag; - val->int1_sign_mot = int1_ctrl.int1_sign_mot; - val->int1_step_detector = int1_ctrl.int1_step_detector; - val->int1_timer = md1_cfg.int1_timer; - val->int1_tilt = md1_cfg.int1_tilt; - val->int1_6d = md1_cfg.int1_6d; - val->int1_double_tap = md1_cfg.int1_double_tap; - val->int1_ff = md1_cfg.int1_ff; - val->int1_wu = md1_cfg.int1_wu; - val->int1_single_tap = md1_cfg.int1_single_tap; - val->int1_inact_state = md1_cfg.int1_inact_state; - val->drdy_on_int1 = master_config.drdy_on_int1; - } - - return ret; -} - -/** - * @brief Select the signal that need to route on int1 pad.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val Select the signal that need to route on int1 pad. - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_pin_int2_route_set(stmdev_ctx_t *ctx, - lsm6ds3_int2_route_t *val) -{ - lsm6ds3_int2_ctrl_t int2_ctrl; - lsm6ds3_md2_cfg_t md2_cfg; - lsm6ds3_master_config_t master_config; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, - (uint8_t *)&master_config, 1); - - if (ret == 0) - { - int2_ctrl.int2_drdy_xl = val->int2_drdy_xl; - int2_ctrl.int2_drdy_g = val->int2_drdy_g; - int2_ctrl.int2_drdy_temp = val->int2_drdy_temp; - int2_ctrl.int2_fth = val->int2_fth; - int2_ctrl.int2_fifo_ovr = val->int2_fifo_ovr; - int2_ctrl.int2_full_flag = val->int2_full_flag; - int2_ctrl.int2_step_count_ov = val->int2_step_count_ov; - int2_ctrl.int2_step_delta = val->int2_step_delta; - md2_cfg.int2_iron = val->int2_iron; - md2_cfg.int2_tilt = val->int2_tilt; - md2_cfg.int2_6d = val->int2_6d; - md2_cfg.int2_double_tap = val->int2_double_tap; - md2_cfg.int2_ff = val->int2_ff; - md2_cfg.int2_wu = val->int2_wu; - md2_cfg.int2_single_tap = val->int2_single_tap; - md2_cfg.int2_inact_state = val->int2_inact_state; - master_config.start_config = val->start_config; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); - } - - if (ret == 0) - { - ret = lsm6ds3_write_reg(ctx, LSM6DS3_MD2_CFG, (uint8_t *)&md2_cfg, 1); - } - - if (ret == 0) - { - ret = lsm6ds3_write_reg(ctx, LSM6DS3_MASTER_CONFIG, - (uint8_t *)&master_config, 1); - } - - return ret; -} - -/** - * @brief Select the signal that need to route on int1 pad.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val Select the signal that need to route on int1 pad. - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_pin_int2_route_get(stmdev_ctx_t *ctx, - lsm6ds3_int2_route_t *val) -{ - lsm6ds3_int2_ctrl_t int2_ctrl; - lsm6ds3_md2_cfg_t md2_cfg; - lsm6ds3_master_config_t master_config; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_MD2_CFG, (uint8_t *)&md2_cfg, 1); - } - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, - (uint8_t *)&master_config, 1); - val->int2_drdy_xl = int2_ctrl.int2_drdy_xl; - val->int2_drdy_g = int2_ctrl.int2_drdy_g; - val->int2_drdy_temp = int2_ctrl.int2_drdy_temp; - val->int2_fth = int2_ctrl.int2_fth; - val->int2_fifo_ovr = int2_ctrl.int2_fifo_ovr; - val->int2_full_flag = int2_ctrl.int2_full_flag; - val->int2_step_count_ov = int2_ctrl.int2_step_count_ov; - val->int2_step_delta = int2_ctrl.int2_step_delta; - val->int2_iron = md2_cfg.int2_iron; - val->int2_tilt = md2_cfg.int2_tilt; - val->int2_6d = md2_cfg.int2_6d; - val->int2_double_tap = md2_cfg.int2_double_tap; - val->int2_ff = md2_cfg.int2_ff; - val->int2_wu = md2_cfg.int2_wu; - val->int2_single_tap = md2_cfg.int2_single_tap; - val->int2_inact_state = md2_cfg.int2_inact_state; - val->start_config = master_config.start_config; - } - - return ret; -} - -/** - * @brief Push-pull/open drain selection on interrupt pads.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of pp_od in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_pin_mode_set(stmdev_ctx_t *ctx, lsm6ds3_pp_od_t val) -{ - lsm6ds3_ctrl3_c_t ctrl3_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - - if (ret == 0) - { - ctrl3_c.pp_od = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - } - - return ret; -} - -/** - * @brief Push-pull/open drain selection on interrupt pads.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of pp_od in reg CTRL3_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_pin_mode_get(stmdev_ctx_t *ctx, lsm6ds3_pp_od_t *val) -{ - lsm6ds3_ctrl3_c_t ctrl3_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - - switch (ctrl3_c.pp_od) - { - case LSM6DS3_PUSH_PULL: - *val = LSM6DS3_PUSH_PULL; - break; - - case LSM6DS3_OPEN_DRAIN: - *val = LSM6DS3_OPEN_DRAIN; - break; - - default: - *val = LSM6DS3_PUSH_PULL; - break; - } - - return ret; -} - -/** - * @brief Interrupt active-high/low.Interrupt active-high/low.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of h_lactive in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_pin_polarity_set(stmdev_ctx_t *ctx, - lsm6ds3_pin_pol_t val) -{ - lsm6ds3_ctrl3_c_t ctrl3_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - - if (ret == 0) - { - ctrl3_c.h_lactive = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - } - - return ret; -} - -/** - * @brief Interrupt active-high/low.Interrupt active-high/low.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of h_lactive in reg CTRL3_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_pin_polarity_get(stmdev_ctx_t *ctx, - lsm6ds3_pin_pol_t *val) -{ - lsm6ds3_ctrl3_c_t ctrl3_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - - switch (ctrl3_c.h_lactive) - { - case LSM6DS3_ACTIVE_HIGH: - *val = LSM6DS3_ACTIVE_HIGH; - break; - - case LSM6DS3_ACTIVE_LOW: - *val = LSM6DS3_ACTIVE_LOW; - break; - - default: - *val = LSM6DS3_ACTIVE_HIGH; - break; - } - - return ret; -} - -/** - * @brief All interrupt signals become available on INT1 pin.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of int2_on_int1 in reg CTRL4_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_ctrl4_c_t ctrl4_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1); - - if (ret == 0) - { - ctrl4_c.int2_on_int1 = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1); - } - - return ret; -} - -/** - * @brief All interrupt signals become available on INT1 pin.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of int2_on_int1 in reg CTRL4_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_ctrl4_c_t ctrl4_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1); - *val = (uint8_t)ctrl4_c.int2_on_int1; - - return ret; -} - -/** - * @brief Latched/pulsed interrupt.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of lir in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_int_notification_set(stmdev_ctx_t *ctx, - lsm6ds3_lir_t val) -{ - lsm6ds3_tap_cfg_t tap_cfg; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1); - - if (ret == 0) - { - tap_cfg.lir = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1); - } - - return ret; -} - -/** - * @brief Latched/pulsed interrupt.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of lir in reg TAP_CFG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_int_notification_get(stmdev_ctx_t *ctx, - lsm6ds3_lir_t *val) -{ - lsm6ds3_tap_cfg_t tap_cfg; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1); - - switch (tap_cfg.lir) - { - case LSM6DS3_INT_PULSED: - *val = LSM6DS3_INT_PULSED; - break; - - case LSM6DS3_INT_LATCHED: - *val = LSM6DS3_INT_LATCHED; - break; - - default: - *val = LSM6DS3_INT_PULSED; - break; - } - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LSM6DS3_Wake_Up_event - * @brief This section groups all the functions that manage the - * Wake Up event generation. - * @{ - * - */ - -/** - * @brief Read the wake_up_src status flag of the device.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val Read the wake_up_src status flag of the device. - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_wkup_src_get(stmdev_ctx_t *ctx, - lsm6ds3_wake_up_src_t *val) -{ - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_SRC, (uint8_t *)val, 1); - - return ret; -} - -/** - * @brief Threshold for wakeup (1 LSB = FS_XL / 64).[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of wk_ths in reg WAKE_UP_THS - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_wake_up_ths_t wake_up_ths; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_THS, - (uint8_t *)&wake_up_ths, 1); - - if (ret == 0) - { - wake_up_ths.wk_ths = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_WAKE_UP_THS, - (uint8_t *)&wake_up_ths, 1); - } - - return ret; -} - -/** - * @brief Threshold for wakeup (1 LSB = FS_XL / 64).[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of wk_ths in reg WAKE_UP_THS - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_wake_up_ths_t wake_up_ths; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_THS, - (uint8_t *)&wake_up_ths, 1); - *val = (uint8_t)wake_up_ths.wk_ths; - - return ret; -} - -/** - * @brief Wake up duration event.1LSb = 1 / ODR[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of wake_dur in reg WAKE_UP_DUR - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_wake_up_dur_t wake_up_dur; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_DUR, - (uint8_t *)&wake_up_dur, 1); - - if (ret == 0) - { - wake_up_dur.wake_dur = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_WAKE_UP_DUR, - (uint8_t *)&wake_up_dur, 1); - } - - return ret; -} - -/** - * @brief Wake up duration event.1LSb = 1 / ODR[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of wake_dur in reg WAKE_UP_DUR - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_wake_up_dur_t wake_up_dur; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_DUR, - (uint8_t *)&wake_up_dur, 1); - *val = (uint8_t)wake_up_dur.wake_dur; - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LSM6DS3_Activity/Inactivity_detection - * @brief This section groups all the functions concerning - * activity/inactivity detection. - * @{ - * - */ - -/** - * @brief Enables gyroscope Sleep mode.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of sleep_g in reg CTRL4_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_ctrl4_c_t ctrl4_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1); - - if (ret == 0) - { - ctrl4_c.sleep_g = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1); - } - - return ret; -} - -/** - * @brief Enables gyroscope Sleep mode.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of sleep_g in reg CTRL4_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_ctrl4_c_t ctrl4_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1); - *val = (uint8_t)ctrl4_c.sleep_g; - - return ret; -} - -/** - * @brief Enable/Disable inactivity function.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of inactivity in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_act_mode_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_wake_up_ths_t wake_up_ths; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_THS, - (uint8_t *)&wake_up_ths, 1); - - if (ret == 0) - { - wake_up_ths.inactivity = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_WAKE_UP_THS, - (uint8_t *)&wake_up_ths, 1); - } - - return ret; -} - -/** - * @brief Enable/Disable inactivity function.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of inactivity in reg WAKE_UP_THS - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_act_mode_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_wake_up_ths_t wake_up_ths; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_THS, - (uint8_t *)&wake_up_ths, 1); - *val = wake_up_ths.inactivity; - - return ret; -} - -/** - * @brief Duration to go in sleep mode. 1 LSb = 512 / ODR[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of sleep_dur in reg WAKE_UP_DUR - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_wake_up_dur_t wake_up_dur; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_DUR, - (uint8_t *)&wake_up_dur, 1); - - if (ret == 0) - { - wake_up_dur.sleep_dur = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_WAKE_UP_DUR, - (uint8_t *)&wake_up_dur, 1); - } - - return ret; -} - -/** - * @brief Duration to go in sleep mode. 1 LSb = 512 / ODR[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of sleep_dur in reg WAKE_UP_DUR - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_wake_up_dur_t wake_up_dur; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_DUR, - (uint8_t *)&wake_up_dur, 1); - *val = (uint8_t)wake_up_dur.sleep_dur; - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LSM6DS3_Tap_generator - * @brief This section groups all the functions that manage the - * tap and double tap event generation. - * @{ - * - */ - -/** - * @brief Read the tap_src status flag of the device.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val Read the tap_src status flag of the device. - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_tap_src_get(stmdev_ctx_t *ctx, lsm6ds3_tap_src_t *val) -{ - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_SRC, (uint8_t *)val, 1); - - return ret; -} - -/** - * @brief Enable Z direction in tap recognition.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of tap_z_en in reg TAP_CFG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_tap_cfg_t tap_cfg; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1); - - if (ret == 0) - { - tap_cfg.tap_z_en = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1); - } - - return ret; -} - -/** - * @brief Enable Z direction in tap recognition.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of tap_z_en in reg TAP_CFG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_tap_detection_on_z_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - lsm6ds3_tap_cfg_t tap_cfg; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1); - *val = (uint8_t)tap_cfg.tap_z_en; - - return ret; -} - -/** - * @brief Enable Y direction in tap recognition.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of tap_y_en in reg TAP_CFG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_tap_cfg_t tap_cfg; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1); - - if (ret == 0) - { - tap_cfg.tap_y_en = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1); - } - - return ret; -} - -/** - * @brief Enable Y direction in tap recognition.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of tap_y_en in reg TAP_CFG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_tap_detection_on_y_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - lsm6ds3_tap_cfg_t tap_cfg; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1); - *val = (uint8_t)tap_cfg.tap_y_en; - - return ret; -} - -/** - * @brief Enable X direction in tap recognition.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of tap_x_en in reg TAP_CFG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_tap_cfg_t tap_cfg; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1); - - if (ret == 0) - { - tap_cfg.tap_x_en = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1); - } - - return ret; -} - -/** - * @brief Enable X direction in tap recognition.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of tap_x_en in reg TAP_CFG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_tap_detection_on_x_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - lsm6ds3_tap_cfg_t tap_cfg; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1); - *val = (uint8_t)tap_cfg.tap_x_en; - - return ret; -} - -/** - * @brief Threshold for tap recognition.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of tap_ths in reg TAP_THS_6D - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_tap_ths_6d_t tap_ths_6d; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_THS_6D, - (uint8_t *)&tap_ths_6d, 1); - - if (ret == 0) - { - tap_ths_6d.tap_ths = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_THS_6D, - (uint8_t *)&tap_ths_6d, 1); - } - - return ret; -} - -/** - * @brief Threshold for tap recognition.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of tap_ths in reg TAP_THS_6D - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_tap_ths_6d_t tap_ths_6d; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_THS_6D, - (uint8_t *)&tap_ths_6d, 1); - *val = (uint8_t)tap_ths_6d.tap_ths; - - return ret; -} - -/** - * @brief Maximum duration is the maximum time of an overthreshold signal - * detection to be recognized as a tap event. The default value - * of these bits is 00b which corresponds to 4*ODR_XL time. - * If the SHOCK[1:0] bits are set to a different value, - * 1LSB corresponds to 8*ODR_XL time.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of shock in reg INT_DUR2 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_int_dur2_t int_dur2; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t *)&int_dur2, 1); - - if (ret == 0) - { - int_dur2.shock = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t *)&int_dur2, 1); - } - - return ret; -} - -/** - * @brief Maximum duration is the maximum time of an overthreshold signal - * detection to be recognized as a tap event. - * The default value of these bits is 00b which corresponds - * to 4*ODR_XL time. If the SHOCK[1:0] bits are set to a different - * value, 1LSB corresponds to 8*ODR_XL time.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of shock in reg INT_DUR2 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_int_dur2_t int_dur2; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t *)&int_dur2, 1); - *val = (uint8_t)int_dur2.shock; - - return ret; -} - -/** - * @brief Quiet time is the time after the first detected tap in - * which there must not be any over-threshold event. - * The default value of these bits is 00b which corresponds - * to 2*ODR_XL time. If the QUIET[1:0] bits are set to a - * different value, 1LSB corresponds to 4*ODR_XL time.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of quiet in reg INT_DUR2 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_int_dur2_t int_dur2; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t *)&int_dur2, 1); - - if (ret == 0) - { - int_dur2.quiet = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t *)&int_dur2, 1); - } - - return ret; -} - -/** - * @brief Quiet time is the time after the first detected tap in which - * there must not be any over-threshold event. The default value - * of these bits is 00b which corresponds to 2*ODR_XL time. - * If the QUIET[1:0] bits are set to a different value, - * 1LSB corresponds to 4*ODR_XL time.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of quiet in reg INT_DUR2 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_int_dur2_t int_dur2; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t *)&int_dur2, 1); - *val = (uint8_t)int_dur2.quiet; - - return ret; -} - -/** - * @brief When double tap recognition is enabled, this register - * expresses the maximum time between two consecutive detected - * taps to determine a double tap event. The default value of - * these bits is 0000b which corresponds to 16*ODR_XL time. - * If the DUR[3:0] bits are set to a different value, - * 1LSB corresponds to 32*ODR_XL time.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of dur in reg INT_DUR2 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_int_dur2_t int_dur2; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t *)&int_dur2, 1); - - if (ret == 0) - { - int_dur2.dur = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t *)&int_dur2, 1); - } - - return ret; -} - -/** - * @brief When double tap recognition is enabled, this register - * expresses the maximum time between two consecutive detected - * taps to determine a double tap event. - * The default value of these bits is 0000b which corresponds - * to 16*ODR_XL time. If the DUR[3:0] bits are set to a - * different value, 1LSB corresponds to 32*ODR_XL time.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of dur in reg INT_DUR2 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_int_dur2_t int_dur2; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t *)&int_dur2, 1); - *val = (uint8_t)int_dur2.dur; - - return ret; -} - -/** - * @brief Single/double-tap event enable.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of single_double_tap in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_tap_mode_set(stmdev_ctx_t *ctx, lsm6ds3_tap_md_t val) -{ - lsm6ds3_wake_up_ths_t wake_up_ths; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_THS, - (uint8_t *)&wake_up_ths, 1); - - if (ret == 0) - { - wake_up_ths.single_double_tap = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_WAKE_UP_THS, - (uint8_t *)&wake_up_ths, 1); - } - - return ret; -} - -/** - * @brief Single/double-tap event enable.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of single_double_tap in reg WAKE_UP_THS - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_tap_mode_get(stmdev_ctx_t *ctx, lsm6ds3_tap_md_t *val) -{ - lsm6ds3_wake_up_ths_t wake_up_ths; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_THS, - (uint8_t *)&wake_up_ths, 1); - - switch (wake_up_ths.single_double_tap) - { - case LSM6DS3_ONLY_DOUBLE: - *val = LSM6DS3_ONLY_DOUBLE; - break; - - case LSM6DS3_SINGLE_DOUBLE: - *val = LSM6DS3_SINGLE_DOUBLE; - break; - - default: - *val = LSM6DS3_ONLY_DOUBLE; - break; - } - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LSM6DS3_Six_position_detection(6D/4D) - * @brief This section groups all the functions concerning - * six position detection (6D). - * @{ - * - */ - -/** - * @brief LPF2 feed 6D function selection.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of low_pass_on_6d in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_6d_feed_data_set(stmdev_ctx_t *ctx, - lsm6ds3_low_pass_on_6d_t val) -{ - lsm6ds3_ctrl8_xl_t ctrl8_xl; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); - - if (ret == 0) - { - ctrl8_xl.low_pass_on_6d = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); - } - - return ret; -} - -/** - * @brief LPF2 feed 6D function selection.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of low_pass_on_6d in reg CTRL8_XL - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_6d_feed_data_get(stmdev_ctx_t *ctx, - lsm6ds3_low_pass_on_6d_t *val) -{ - lsm6ds3_ctrl8_xl_t ctrl8_xl; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1); - - switch (ctrl8_xl.low_pass_on_6d) - { - case LSM6DS3_ODR_DIV_2_FEED: - *val = LSM6DS3_ODR_DIV_2_FEED; - break; - - case LSM6DS3_LPF2_FEED: - *val = LSM6DS3_LPF2_FEED; - break; - - default: - *val = LSM6DS3_ODR_DIV_2_FEED; - break; - } - - return ret; -} - -/** - * @brief Read the d6d_src status flag of the device.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val Read the d6d_src status flag of the device. - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_6d_src_get(stmdev_ctx_t *ctx, lsm6ds3_d6d_src_t *val) -{ - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_D6D_SRC, (uint8_t *)val, 1); - - return ret; -} - -/** - * @brief Threshold for 4D/6D function.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of sixd_ths in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_6d_threshold_set(stmdev_ctx_t *ctx, - lsm6ds3_sixd_ths_t val) -{ - lsm6ds3_tap_ths_6d_t tap_ths_6d; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_THS_6D, - (uint8_t *)&tap_ths_6d, 1); - - if (ret == 0) - { - tap_ths_6d.sixd_ths = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_THS_6D, - (uint8_t *)&tap_ths_6d, 1); - } - - return ret; -} - -/** - * @brief Threshold for 4D/6D function.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of sixd_ths in reg TAP_THS_6D - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_6d_threshold_get(stmdev_ctx_t *ctx, - lsm6ds3_sixd_ths_t *val) -{ - lsm6ds3_tap_ths_6d_t tap_ths_6d; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_THS_6D, - (uint8_t *)&tap_ths_6d, 1); - - switch (tap_ths_6d.sixd_ths) - { - case LSM6DS3_DEG_80: - *val = LSM6DS3_DEG_80; - break; - - case LSM6DS3_DEG_70: - *val = LSM6DS3_DEG_70; - break; - - case LSM6DS3_DEG_60: - *val = LSM6DS3_DEG_60; - break; - - case LSM6DS3_DEG_50: - *val = LSM6DS3_DEG_50; - break; - - default: - *val = LSM6DS3_DEG_80; - break; - } - - return ret; -} - -/** - * @brief 4D orientation detection enable.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of d4d_en in reg TAP_THS_6D - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_tap_ths_6d_t tap_ths_6d; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_THS_6D, - (uint8_t *)&tap_ths_6d, 1); - - if (ret == 0) - { - tap_ths_6d.d4d_en = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_THS_6D, - (uint8_t *)&tap_ths_6d, 1); - } - - return ret; -} - -/** - * @brief 4D orientation detection enable.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of d4d_en in reg TAP_THS_6D - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_tap_ths_6d_t tap_ths_6d; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_THS_6D, - (uint8_t *)&tap_ths_6d, 1); - *val = (uint8_t)tap_ths_6d.d4d_en; - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LSM6DS3_Free_fall - * @brief This section group all the functions concerning the - * free fall detection. - * @{ - * - */ - -/** - * @brief Free fall threshold setting.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of ff_ths in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_ff_threshold_set(stmdev_ctx_t *ctx, - lsm6ds3_ff_ths_t val) -{ - lsm6ds3_free_fall_t free_fall; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FREE_FALL, (uint8_t *)&free_fall, 1); - - if (ret == 0) - { - free_fall.ff_ths = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_FREE_FALL, (uint8_t *)&free_fall, 1); - } - - return ret; -} - -/** - * @brief Free fall threshold setting.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of ff_ths in reg FREE_FALL - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_ff_threshold_get(stmdev_ctx_t *ctx, - lsm6ds3_ff_ths_t *val) -{ - lsm6ds3_free_fall_t free_fall; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FREE_FALL, (uint8_t *)&free_fall, 1); - - switch (free_fall.ff_ths) - { - case LSM6DS3_156_mg: - *val = LSM6DS3_156_mg; - break; - - case LSM6DS3_219_mg: - *val = LSM6DS3_219_mg; - break; - - case LSM6DS3_250_mg: - *val = LSM6DS3_250_mg; - break; - - case LSM6DS3_312_mg: - *val = LSM6DS3_312_mg; - break; - - case LSM6DS3_344_mg: - *val = LSM6DS3_344_mg; - break; - - case LSM6DS3_406_mg: - *val = LSM6DS3_406_mg; - break; - - case LSM6DS3_469_mg: - *val = LSM6DS3_469_mg; - break; - - case LSM6DS3_500_mg: - *val = LSM6DS3_500_mg; - break; - - default: - *val = LSM6DS3_156_mg; - break; - } - - return ret; -} - -/** - * @brief Free-fall duration event. 1LSb = 1 / ODR[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of ff_dur in reg FREE_FALL - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_free_fall_t free_fall; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FREE_FALL, (uint8_t *)&free_fall, 1); - - if (ret == 0) - { - free_fall.ff_dur = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_FREE_FALL, (uint8_t *)&free_fall, 1); - } - - return ret; -} - -/** - * @brief Free-fall duration event. 1LSb = 1 / ODR[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of ff_dur in reg FREE_FALL - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_free_fall_t free_fall; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FREE_FALL, (uint8_t *)&free_fall, 1); - *val = (uint8_t)free_fall.ff_dur; - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LSM6DS3_Fifo - * @brief This section group all the functions concerning the - * fifo usage - * @{ - * - */ - -/** - * @brief FIFO watermark level selection.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of fth in reg FIFO_CTRL1 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) -{ - lsm6ds3_fifo_ctrl1_t fifo_ctrl1; - lsm6ds3_fifo_ctrl2_t fifo_ctrl2; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL1, - (uint8_t *)&fifo_ctrl1, 1); - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL2, - (uint8_t *)&fifo_ctrl2, 1); - } - - if (ret == 0) - { - fifo_ctrl2.fth = (uint8_t)((val & 0x0F00U) >> 8); - ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL2, - (uint8_t *)&fifo_ctrl2, 1); - } - - if (ret == 0) - { - fifo_ctrl1.fth = (uint8_t)(val & 0x00FFU); - ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL1, - (uint8_t *)&fifo_ctrl1, 1); - } - - return ret; -} - -/** - * @brief FIFO watermark level selection.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of fth in reg FIFO_CTRL1 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) -{ - lsm6ds3_fifo_ctrl1_t fifo_ctrl1; - lsm6ds3_fifo_ctrl2_t fifo_ctrl2; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL1, - (uint8_t *)&fifo_ctrl1, 1); - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL2, - (uint8_t *)&fifo_ctrl2, 1); - *val = (uint16_t)fifo_ctrl2.fth << 8; - *val |= fifo_ctrl1.fth; - } - - return ret; -} - -/** - * @brief trigger signal for FIFO write operation.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of timer_pedo_fifo_drdy in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_write_trigger_set(stmdev_ctx_t *ctx, - lsm6ds3_tmr_ped_fifo_drdy_t val) -{ - lsm6ds3_fifo_ctrl2_t fifo_ctrl2; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL2, - (uint8_t *)&fifo_ctrl2, 1); - - if (ret == 0) - { - fifo_ctrl2. timer_pedo_fifo_drdy = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL2, - (uint8_t *)&fifo_ctrl2, 1); - } - - return ret; -} - -/** - * @brief trigger signal for FIFO write operation.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of timer_pedo_fifo_drdy in - * reg FIFO_CTRL2 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_write_trigger_get(stmdev_ctx_t *ctx, - lsm6ds3_tmr_ped_fifo_drdy_t *val) -{ - lsm6ds3_fifo_ctrl2_t fifo_ctrl2; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL2, - (uint8_t *)&fifo_ctrl2, 1); - - switch (fifo_ctrl2. timer_pedo_fifo_drdy) - { - case LSM6DS3_TRG_XL_GY_DRDY: - *val = LSM6DS3_TRG_XL_GY_DRDY; - break; - - case LSM6DS3_TRG_STEP_DETECT: - *val = LSM6DS3_TRG_STEP_DETECT; - break; - - default: - *val = LSM6DS3_TRG_XL_GY_DRDY; - break; - } - - return ret; -} - -/** - * @brief Pedometer step counter and timestamp as 4th FIFO data set.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of timer_pedo_fifo_en in reg FIFO_CTRL2 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_fifo_ctrl2_t fifo_ctrl2; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL2, - (uint8_t *)&fifo_ctrl2, 1); - - if (ret == 0) - { - fifo_ctrl2.timer_pedo_fifo_en = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL2, - (uint8_t *)&fifo_ctrl2, 1); - } - - return ret; -} - -/** - * @brief Pedometer step counter and timestamp as 4th FIFO data set.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of timer_pedo_fifo_en in reg FIFO_CTRL2 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_fifo_ctrl2_t fifo_ctrl2; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL2, - (uint8_t *)&fifo_ctrl2, 1); - *val = (uint8_t)fifo_ctrl2.timer_pedo_fifo_en; - - return ret; -} - -/** - * @brief Selects Batching Data Rate (writing frequency in FIFO) for - * accelerometer data.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of dec_fifo_xl in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_xl_batch_set(stmdev_ctx_t *ctx, - lsm6ds3_dec_fifo_xl_t val) -{ - lsm6ds3_fifo_ctrl3_t fifo_ctrl3; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL3, - (uint8_t *)&fifo_ctrl3, 1); - - if (ret == 0) - { - fifo_ctrl3.dec_fifo_xl = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL3, - (uint8_t *)&fifo_ctrl3, 1); - } - - return ret; -} - -/** - * @brief Selects Batching Data Rate (writing frequency in FIFO) for - * accelerometer data.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of dec_fifo_xl in reg FIFO_CTRL3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_xl_batch_get(stmdev_ctx_t *ctx, - lsm6ds3_dec_fifo_xl_t *val) -{ - lsm6ds3_fifo_ctrl3_t fifo_ctrl3; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL3, - (uint8_t *)&fifo_ctrl3, 1); - - switch (fifo_ctrl3.dec_fifo_xl) - { - case LSM6DS3_FIFO_XL_DISABLE: - *val = LSM6DS3_FIFO_XL_DISABLE; - break; - - case LSM6DS3_FIFO_XL_NO_DEC: - *val = LSM6DS3_FIFO_XL_NO_DEC; - break; - - case LSM6DS3_FIFO_XL_DEC_2: - *val = LSM6DS3_FIFO_XL_DEC_2; - break; - - case LSM6DS3_FIFO_XL_DEC_3: - *val = LSM6DS3_FIFO_XL_DEC_3; - break; - - case LSM6DS3_FIFO_XL_DEC_4: - *val = LSM6DS3_FIFO_XL_DEC_4; - break; - - case LSM6DS3_FIFO_XL_DEC_8: - *val = LSM6DS3_FIFO_XL_DEC_8; - break; - - case LSM6DS3_FIFO_XL_DEC_16: - *val = LSM6DS3_FIFO_XL_DEC_16; - break; - - case LSM6DS3_FIFO_XL_DEC_32: - *val = LSM6DS3_FIFO_XL_DEC_32; - break; - - default: - *val = LSM6DS3_FIFO_XL_DISABLE; - break; - } - - return ret; -} - -/** - * @brief Selects Batching Data Rate (writing frequency in FIFO) - * for gyroscope data.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of dec_fifo_gyro in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_gy_batch_set(stmdev_ctx_t *ctx, - lsm6ds3_dec_fifo_gyro_t val) -{ - lsm6ds3_fifo_ctrl3_t fifo_ctrl3; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL3, - (uint8_t *)&fifo_ctrl3, 1); - - if (ret == 0) - { - fifo_ctrl3.dec_fifo_gyro = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL3, - (uint8_t *)&fifo_ctrl3, 1); - } - - return ret; -} - -/** - * @brief Selects Batching Data Rate (writing frequency in FIFO) - * for gyroscope data.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of dec_fifo_gyro in reg FIFO_CTRL3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_gy_batch_get(stmdev_ctx_t *ctx, - lsm6ds3_dec_fifo_gyro_t *val) -{ - lsm6ds3_fifo_ctrl3_t fifo_ctrl3; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL3, - (uint8_t *)&fifo_ctrl3, 1); - - switch (fifo_ctrl3.dec_fifo_gyro) - { - case LSM6DS3_FIFO_GY_DISABLE: - *val = LSM6DS3_FIFO_GY_DISABLE; - break; - - case LSM6DS3_FIFO_GY_NO_DEC: - *val = LSM6DS3_FIFO_GY_NO_DEC; - break; - - case LSM6DS3_FIFO_GY_DEC_2: - *val = LSM6DS3_FIFO_GY_DEC_2; - break; - - case LSM6DS3_FIFO_GY_DEC_3: - *val = LSM6DS3_FIFO_GY_DEC_3; - break; - - case LSM6DS3_FIFO_GY_DEC_4: - *val = LSM6DS3_FIFO_GY_DEC_4; - break; - - case LSM6DS3_FIFO_GY_DEC_8: - *val = LSM6DS3_FIFO_GY_DEC_8; - break; - - case LSM6DS3_FIFO_GY_DEC_16: - *val = LSM6DS3_FIFO_GY_DEC_16; - break; - - case LSM6DS3_FIFO_GY_DEC_32: - *val = LSM6DS3_FIFO_GY_DEC_32; - break; - - default: - *val = LSM6DS3_FIFO_GY_DISABLE; - break; - } - - return ret; -} - -/** - * @brief Selects Batching Data Rate (writing frequency in FIFO) - * for third data set.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of dec_ds3_fifo in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx, - lsm6ds3_dec_ds3_fifo_t val) -{ - lsm6ds3_fifo_ctrl4_t fifo_ctrl4; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL4, - (uint8_t *)&fifo_ctrl4, 1); - - if (ret == 0) - { - fifo_ctrl4.dec_ds3_fifo = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL4, - (uint8_t *)&fifo_ctrl4, 1); - } - - return ret; -} - -/** - * @brief Selects Batching Data Rate (writing frequency in FIFO) - * for third data set.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of dec_ds3_fifo in reg FIFO_CTRL4 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx, - lsm6ds3_dec_ds3_fifo_t *val) -{ - lsm6ds3_fifo_ctrl4_t fifo_ctrl4; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL4, - (uint8_t *)&fifo_ctrl4, 1); - - switch (fifo_ctrl4.dec_ds3_fifo) - { - case LSM6DS3_FIFO_DS3_DISABLE: - *val = LSM6DS3_FIFO_DS3_DISABLE; - break; - - case LSM6DS3_FIFO_DS3_NO_DEC: - *val = LSM6DS3_FIFO_DS3_NO_DEC; - break; - - case LSM6DS3_FIFO_DS3_DEC_2: - *val = LSM6DS3_FIFO_DS3_DEC_2; - break; - - case LSM6DS3_FIFO_DS3_DEC_3: - *val = LSM6DS3_FIFO_DS3_DEC_3; - break; - - case LSM6DS3_FIFO_DS3_DEC_4: - *val = LSM6DS3_FIFO_DS3_DEC_4; - break; - - case LSM6DS3_FIFO_DS3_DEC_8: - *val = LSM6DS3_FIFO_DS3_DEC_8; - break; - - case LSM6DS3_FIFO_DS3_DEC_16: - *val = LSM6DS3_FIFO_DS3_DEC_16; - break; - - case LSM6DS3_FIFO_DS3_DEC_32: - *val = LSM6DS3_FIFO_DS3_DEC_32; - break; - - default: - *val = LSM6DS3_FIFO_DS3_DISABLE; - break; - } - - return ret; -} - -/** - * @brief Selects Batching Data Rate (writing frequency in FIFO) - * for fourth data set.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of dec_ds4_fifo in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx, - lsm6ds3_dec_ds4_fifo_t val) -{ - lsm6ds3_fifo_ctrl4_t fifo_ctrl4; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL4, - (uint8_t *)&fifo_ctrl4, 1); - - if (ret == 0) - { - fifo_ctrl4.dec_ds4_fifo = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL4, - (uint8_t *)&fifo_ctrl4, 1); - } - - return ret; -} - -/** - * @brief Selects Batching Data Rate (writing frequency in FIFO) - * for fourth data set.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of dec_ds4_fifo in reg FIFO_CTRL4 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx, - lsm6ds3_dec_ds4_fifo_t *val) -{ - lsm6ds3_fifo_ctrl4_t fifo_ctrl4; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL4, - (uint8_t *)&fifo_ctrl4, 1); - - switch (fifo_ctrl4.dec_ds4_fifo) - { - case LSM6DS3_FIFO_DS4_DISABLE: - *val = LSM6DS3_FIFO_DS4_DISABLE; - break; - - case LSM6DS3_FIFO_DS4_NO_DEC: - *val = LSM6DS3_FIFO_DS4_NO_DEC; - break; - - case LSM6DS3_FIFO_DS4_DEC_2: - *val = LSM6DS3_FIFO_DS4_DEC_2; - break; - - case LSM6DS3_FIFO_DS4_DEC_3: - *val = LSM6DS3_FIFO_DS4_DEC_3; - break; - - case LSM6DS3_FIFO_DS4_DEC_4: - *val = LSM6DS3_FIFO_DS4_DEC_4; - break; - - case LSM6DS3_FIFO_DS4_DEC_8: - *val = LSM6DS3_FIFO_DS4_DEC_8; - break; - - case LSM6DS3_FIFO_DS4_DEC_16: - *val = LSM6DS3_FIFO_DS4_DEC_16; - break; - - case LSM6DS3_FIFO_DS4_DEC_32: - *val = LSM6DS3_FIFO_DS4_DEC_32; - break; - - default: - *val = LSM6DS3_FIFO_DS4_DISABLE; - break; - } - - return ret; -} - -/** - * @brief 8-bit data storage in FIFO.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of only_high_data in reg FIFO_CTRL4 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, - uint8_t val) -{ - lsm6ds3_fifo_ctrl4_t fifo_ctrl4; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL4, - (uint8_t *)&fifo_ctrl4, 1); - - if (ret == 0) - { - fifo_ctrl4.only_high_data = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL4, - (uint8_t *)&fifo_ctrl4, 1); - } - - return ret; -} - -/** - * @brief 8-bit data storage in FIFO.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of only_high_data in reg FIFO_CTRL4 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - lsm6ds3_fifo_ctrl4_t fifo_ctrl4; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL4, - (uint8_t *)&fifo_ctrl4, 1); - *val = (uint8_t)fifo_ctrl4.only_high_data; - - return ret; -} - -/** - * @brief FIFO mode selection.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of fifo_mode in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_mode_set(stmdev_ctx_t *ctx, - lsm6ds3_fifo_md_t val) -{ - lsm6ds3_fifo_ctrl5_t fifo_ctrl5; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL5, - (uint8_t *)&fifo_ctrl5, 1); - - if (ret == 0) - { - fifo_ctrl5.fifo_mode = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL5, - (uint8_t *)&fifo_ctrl5, 1); - } - - return ret; -} - -/** - * @brief FIFO mode selection.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of fifo_mode in reg FIFO_CTRL5 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_mode_get(stmdev_ctx_t *ctx, - lsm6ds3_fifo_md_t *val) -{ - lsm6ds3_fifo_ctrl5_t fifo_ctrl5; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL5, - (uint8_t *)&fifo_ctrl5, 1); - - switch (fifo_ctrl5.fifo_mode) - { - case LSM6DS3_BYPASS_MODE: - *val = LSM6DS3_BYPASS_MODE; - break; - - case LSM6DS3_FIFO_MODE: - *val = LSM6DS3_FIFO_MODE; - break; - - case LSM6DS3_STREAM_TO_FIFO_MODE: - *val = LSM6DS3_STREAM_TO_FIFO_MODE; - break; - - case LSM6DS3_BYPASS_TO_STREAM_MODE: - *val = LSM6DS3_BYPASS_TO_STREAM_MODE; - break; - - default: - *val = LSM6DS3_BYPASS_MODE; - break; - } - - return ret; -} - -/** - * @brief FIFO ODR selection, setting FIFO_MODE also.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of odr_fifo in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_data_rate_set(stmdev_ctx_t *ctx, - lsm6ds3_odr_fifo_t val) -{ - lsm6ds3_fifo_ctrl5_t fifo_ctrl5; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL5, - (uint8_t *)&fifo_ctrl5, 1); - - if (ret == 0) - { - fifo_ctrl5.odr_fifo = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL5, - (uint8_t *)&fifo_ctrl5, 1); - } - - return ret; -} - -/** - * @brief FIFO ODR selection, setting FIFO_MODE also.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of odr_fifo in reg FIFO_CTRL5 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_data_rate_get(stmdev_ctx_t *ctx, - lsm6ds3_odr_fifo_t *val) -{ - lsm6ds3_fifo_ctrl5_t fifo_ctrl5; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL5, - (uint8_t *)&fifo_ctrl5, 1); - - switch (fifo_ctrl5.odr_fifo) - { - case LSM6DS3_FIFO_DISABLE: - *val = LSM6DS3_FIFO_DISABLE; - break; - - case LSM6DS3_FIFO_12Hz5: - *val = LSM6DS3_FIFO_12Hz5; - break; - - case LSM6DS3_FIFO_26Hz: - *val = LSM6DS3_FIFO_26Hz; - break; - - case LSM6DS3_FIFO_52Hz: - *val = LSM6DS3_FIFO_52Hz; - break; - - case LSM6DS3_FIFO_104Hz: - *val = LSM6DS3_FIFO_104Hz; - break; - - case LSM6DS3_FIFO_208Hz: - *val = LSM6DS3_FIFO_208Hz; - break; - - case LSM6DS3_FIFO_416Hz: - *val = LSM6DS3_FIFO_416Hz; - break; - - case LSM6DS3_FIFO_833Hz: - *val = LSM6DS3_FIFO_833Hz; - break; - - case LSM6DS3_FIFO_1k66Hz: - *val = LSM6DS3_FIFO_1k66Hz; - break; - - case LSM6DS3_FIFO_3k33Hz: - *val = LSM6DS3_FIFO_3k33Hz; - break; - - case LSM6DS3_FIFO_6k66Hz: - *val = LSM6DS3_FIFO_6k66Hz; - break; - - default: - *val = LSM6DS3_FIFO_DISABLE; - break; - } - - return ret; -} - -/** - * @brief Sensing chain FIFO stop values memorization at - * threshold level.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of stop_on_fth in reg CTRL4_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_ctrl4_c_t ctrl4_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1); - - if (ret == 0) - { - ctrl4_c.stop_on_fth = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1); - } - - return ret; -} - -/** - * @brief Sensing chain FIFO stop values memorization at - * threshold level.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of stop_on_fth in reg CTRL4_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_ctrl4_c_t ctrl4_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1); - *val = (uint8_t)ctrl4_c.stop_on_fth; - - return ret; -} - -/** - * @brief batching of temperature data.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of fifo_temp_en in reg CTRL4_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_ctrl4_c_t ctrl4_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1); - - if (ret == 0) - { - ctrl4_c.fifo_temp_en = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1); - } - - return ret; -} - -/** - * @brief batching of temperature data.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of fifo_temp_en in reg CTRL4_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_ctrl4_c_t ctrl4_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t *)&ctrl4_c, 1); - *val = (uint8_t)ctrl4_c.fifo_temp_en; - - return ret; -} - -/** - * @brief Number of unread words (16-bit axes) stored in FIFO.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of diff_fifo in reg FIFO_STATUS1 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) -{ - lsm6ds3_fifo_status1_t fifo_status1; - lsm6ds3_fifo_status2_t fifo_status2; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_STATUS1, - (uint8_t *)&fifo_status1, 1); - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_STATUS2, - (uint8_t *)&fifo_status2, 1); - *val = (uint16_t)fifo_status2.diff_fifo << 8; - *val |= fifo_status1.diff_fifo; - } - - return ret; -} - -/** - * @brief Smart FIFO full status.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of fifo_empty in reg FIFO_STATUS2 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_fifo_status2_t fifo_status2; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_STATUS2, - (uint8_t *)&fifo_status2, 1); - *val = (uint8_t)fifo_status2.fifo_empty; - - return ret; -} - -/** - * @brief FIFO overrun status.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of fifo_full in reg FIFO_STATUS2 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_fifo_status2_t fifo_status2; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_STATUS2, - (uint8_t *)&fifo_status2, 1); - *val = (uint8_t)fifo_status2.fifo_full; - - return ret; -} - -/** - * @brief FIFO watermark status.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of fth in reg FIFO_STATUS2 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_fifo_status2_t fifo_status2; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_STATUS2, - (uint8_t *)&fifo_status2, 1); - *val = (uint8_t)fifo_status2.fth; - - return ret; -} - -/** - * @brief Word of recursive pattern read at the next reading.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of fifo_pattern in reg FIFO_STATUS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val) -{ - lsm6ds3_fifo_status3_t fifo_status3; - lsm6ds3_fifo_status4_t fifo_status4; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_STATUS3, - (uint8_t *)&fifo_status3, 1); - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_STATUS4, - (uint8_t *)&fifo_status4, 1); - *val = (uint16_t)fifo_status4.fifo_pattern << 8; - *val |= fifo_status3.fifo_pattern; - } - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LSM6DS3_DEN_functionality - * @brief This section groups all the functions concerning DEN - * functionality. - * @{ - * - */ - -/** - * @brief DEN functionality marking mode.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of den_mode in reg CTRL6_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_den_mode_set(stmdev_ctx_t *ctx, - lsm6ds3_den_mode_t val) -{ - lsm6ds3_ctrl6_c_t ctrl6_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL6_C, (uint8_t *)&ctrl6_c, 1); - - if (ret == 0) - { - ctrl6_c.den_mode = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL6_C, (uint8_t *)&ctrl6_c, 1); - } - - return ret; -} - -/** - * @brief DEN functionality marking mode.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of den_mode in reg CTRL6_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_den_mode_get(stmdev_ctx_t *ctx, - lsm6ds3_den_mode_t *val) -{ - lsm6ds3_ctrl6_c_t ctrl6_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL6_C, (uint8_t *)&ctrl6_c, 1); - - switch (ctrl6_c.den_mode) - { - case LSM6DS3_DEN_DISABLE: - *val = LSM6DS3_DEN_DISABLE; - break; - - case LSM6DS3_LEVEL_FIFO: - *val = LSM6DS3_LEVEL_FIFO; - break; - - case LSM6DS3_LEVEL_LETCHED: - *val = LSM6DS3_LEVEL_LETCHED; - break; - - case LSM6DS3_LEVEL_TRIGGER: - *val = LSM6DS3_LEVEL_TRIGGER; - break; - - case LSM6DS3_EDGE_TRIGGER: - *val = LSM6DS3_EDGE_TRIGGER; - break; - - default: - *val = LSM6DS3_DEN_DISABLE; - break; - } - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LSM6DS3_Pedometer - * @brief This section groups all the functions that manage pedometer. - * @{ - * - */ - -/** - * @brief Reset pedometer step counter.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of pedo_rst_step in reg CTRL10_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_ctrl10_c_t ctrl10_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1); - - if (ret == 0) - { - ctrl10_c.pedo_rst_step = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1); - } - - return ret; -} - -/** - * @brief Reset pedometer step counter.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of pedo_rst_step in reg CTRL10_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_ctrl10_c_t ctrl10_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1); - *val = (uint8_t)ctrl10_c.pedo_rst_step; - - return ret; -} - -/** - * @brief Step counter timestamp information register (r). When a step is - * detected, the value of TIMESTAMP_REG register is copied in - * STEP_TIMESTAMP_L.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param buff buffer that stores data read - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_pedo_timestamp_raw_get(stmdev_ctx_t *ctx, - uint16_t *val) -{ - uint8_t buff[2]; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_STEP_TIMESTAMP_L, buff, 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; - - return ret; -} - -/** - * @brief Step detector event detection status - * (0:not detected / 1:detected).[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of step_detected in reg FUNC_SRC - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_pedo_step_detect_flag_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - lsm6ds3_func_src_t func_src; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_SRC, (uint8_t *)&func_src, 1); - *val = (uint8_t)func_src.step_detected; - - return ret; -} - -/** - * @brief Enable pedometer algorithm.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of pedo_en in reg TAP_CFG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_ctrl10_c_t ctrl10_c; - lsm6ds3_tap_cfg_t tap_cfg; - int32_t ret; - - ret = 0; - - if (val == PROPERTY_ENABLE) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1); - - if (ret == 0) - { - ctrl10_c.func_en = PROPERTY_ENABLE; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1); - } - } - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1); - } - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1); - } - - if (ret == 0) - { - tap_cfg.pedo_en = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1); - } - - return ret; -} - -/** - * @brief Enable pedometer algorithm.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of pedo_en in reg TAP_CFG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_tap_cfg_t tap_cfg; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1); - *val = (uint8_t)tap_cfg.pedo_en; - - return ret; -} - -/** - * @brief Configurable minimum threshold (PEDO_4G 1LSB = 16 mg , - * PEDO_2G 1LSB = 32 mg).[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of ths_min in reg PEDO_THS_REG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_pedo_ths_reg_t pedo_ths_reg; - int32_t ret; - - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_PEDO_THS_REG, - (uint8_t *)&pedo_ths_reg, 1); - } - - if (ret == 0) - { - pedo_ths_reg.ths_min = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_PEDO_THS_REG, - (uint8_t *)&pedo_ths_reg, 1); - } - - if (ret == 0) - { - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); - } - - return ret; -} - -/** - * @brief Configurable minimum threshold (PEDO_4G 1LSB = 16 mg, - * PEDO_2G 1LSB = 32 mg).[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of ths_min in reg PEDO_THS_REG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_pedo_ths_reg_t pedo_ths_reg; - int32_t ret; - - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_PEDO_THS_REG, - (uint8_t *)&pedo_ths_reg, 1); - } - - if (ret == 0) - { - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); - *val = (uint8_t)pedo_ths_reg.ths_min; - } - - return ret; -} - -/** - * @brief This bit sets the internal full scale used in - * pedometer functions.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of pedo_4g in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_pedo_full_scale_set(stmdev_ctx_t *ctx, - lsm6ds3_pedo_fs_t val) -{ - lsm6ds3_pedo_ths_reg_t pedo_ths_reg; - int32_t ret; - - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_PEDO_THS_REG, - (uint8_t *)&pedo_ths_reg, 1); - } - - if (ret == 0) - { - pedo_ths_reg.pedo_4g = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_PEDO_THS_REG, - (uint8_t *)&pedo_ths_reg, 1); - } - - if (ret == 0) - { - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); - } - - return ret; -} - -/** - * @brief This bit sets the internal full scale used in pedometer - * functions.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of pedo_4g in reg PEDO_THS_REG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_pedo_full_scale_get(stmdev_ctx_t *ctx, - lsm6ds3_pedo_fs_t *val) -{ - lsm6ds3_pedo_ths_reg_t pedo_ths_reg; - int32_t ret; - - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_PEDO_THS_REG, - (uint8_t *)&pedo_ths_reg, 1); - - switch (pedo_ths_reg.pedo_4g) - { - case LSM6DS3_PEDO_AT_2g: - *val = LSM6DS3_PEDO_AT_2g; - break; - - case LSM6DS3_PEDO_AT_4g: - *val = LSM6DS3_PEDO_AT_4g; - break; - - default: - *val = LSM6DS3_PEDO_AT_2g; - break; - } - } - - if (ret == 0) - { - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); - } - - return ret; -} - -/** - * @brief Pedometer debounce configuration register (r/w).[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of deb_step in reg PEDO_DEB_REG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_pedo_debounce_steps_set(stmdev_ctx_t *ctx, - uint8_t val) -{ - lsm6ds3_pedo_deb_reg_t pedo_deb_reg; - int32_t ret; - - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_PEDO_DEB_REG, - (uint8_t *)&pedo_deb_reg, 1); - } - - if (ret == 0) - { - pedo_deb_reg.deb_step = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_PEDO_DEB_REG, - (uint8_t *)&pedo_deb_reg, 1); - } - - if (ret == 0) - { - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); - } - - return ret; -} - -/** - * @brief Pedometer debounce configuration register (r/w).[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of deb_step in reg PEDO_DEB_REG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_pedo_debounce_steps_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - lsm6ds3_pedo_deb_reg_t pedo_deb_reg; - int32_t ret; - - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_PEDO_DEB_REG, - (uint8_t *)&pedo_deb_reg, 1); - } - - if (ret == 0) - { - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); - *val = (uint8_t)pedo_deb_reg.deb_step; - } - - return ret; -} - -/** - * @brief Debounce time. If the time between two consecutive steps is - * greater than DEB_TIME*80ms, the debounce is reactivated.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of deb_time in reg PEDO_DEB_REG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_pedo_deb_reg_t pedo_deb_reg; - int32_t ret; - - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_PEDO_DEB_REG, - (uint8_t *)&pedo_deb_reg, 1); - } - - if (ret == 0) - { - pedo_deb_reg.deb_time = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_PEDO_DEB_REG, - (uint8_t *)&pedo_deb_reg, 1); - } - - if (ret == 0) - { - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); - } - - return ret; -} - -/** - * @brief Debounce time. If the time between two consecutive steps is - * greater than DEB_TIME*80ms, the debounce is reactivated.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of deb_time in reg PEDO_DEB_REG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_pedo_deb_reg_t pedo_deb_reg; - int32_t ret; - - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_PEDO_DEB_REG, - (uint8_t *)&pedo_deb_reg, 1); - } - - if (ret == 0) - { - *val = (uint8_t)pedo_deb_reg.deb_time; - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); - } - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LSM6DS3_Significant_motion - * @brief This section groups all the functions that manage the - * significant motion detection. - * @{ - * - */ - -/** - * @brief Enable significant motion detection function.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of sign_motion_en in reg CTRL10_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_ctrl10_c_t ctrl10_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1); - - if (ret == 0) - { - ctrl10_c.sign_motion_en = (uint8_t)val; - - if (val == PROPERTY_ENABLE) - { - ctrl10_c.func_en = PROPERTY_ENABLE; - } - - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1); - } - - return ret; -} - -/** - * @brief Enable significant motion detection function.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of sign_motion_en in reg CTRL10_C - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_ctrl10_c_t ctrl10_c; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1); - *val = (uint8_t)ctrl10_c.sign_motion_en; - - return ret; -} - -/** - * @brief Significant motion event detection status - * (0:not detected / 1:detected).[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of sign_motion_ia in reg FUNC_SRC - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_motion_event_flag_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_func_src_t func_src; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_SRC, (uint8_t *)&func_src, 1); - *val = (uint8_t)func_src.sign_motion_ia; - - return ret; -} - -/** - * @brief Significant motion threshold.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of sm_ths in reg SM_THS - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_sm_ths_t sm_ths; - int32_t ret; - - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_SM_THS, (uint8_t *)&sm_ths, 1); - } - - if (ret == 0) - { - sm_ths.sm_ths = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_SM_THS, (uint8_t *)&sm_ths, 1); - } - - if (ret == 0) - { - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); - } - - return ret; -} - -/** - * @brief Significant motion threshold.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of sm_ths in reg SM_THS - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_sm_ths_t sm_ths; - int32_t ret; - - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_SM_THS, (uint8_t *)&sm_ths, 1); - } - - if (ret == 0) - { - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); - *val = (uint8_t)sm_ths.sm_ths; - } - - return ret; -} - -/** - * @brief Time period register for step detection on delta time - * (1LSB = 1.6384 s).[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of sc_delta in reg STEP_COUNT_DELTA - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_sc_delta_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_step_count_delta_t step_count_delta; - int32_t ret; - - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_STEP_COUNT_DELTA, - (uint8_t *)& step_count_delta, 1); - } - - if (ret == 0) - { - step_count_delta.sc_delta = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_STEP_COUNT_DELTA, - (uint8_t *)& step_count_delta, 1); - } - - if (ret == 0) - { - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); - } - - return ret; -} - -/** - * @brief Time period register for step detection on delta time - * (1LSB = 1.6384 s).[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of sc_delta in reg STEP_COUNT_DELTA - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_sc_delta_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_step_count_delta_t step_count_delta; - int32_t ret; - - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_STEP_COUNT_DELTA, - (uint8_t *)& step_count_delta, 1); - } - - if (ret == 0) - { - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); - *val = (uint8_t) step_count_delta.sc_delta; - } - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LSM6DS3_Tilt_detection - * @brief This section groups all the functions that manage - * the tilt event detection. - * @{ - * - */ - -/** - * @brief Tilt event detection status(0:not detected / 1:detected).[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of tilt_ia in reg FUNC_SRC - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_tilt_event_flag_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_func_src_t func_src; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_SRC, (uint8_t *)&func_src, 1); - *val = (uint8_t)func_src.tilt_ia; - - return ret; -} - -/** - * @brief Enable tilt calculation.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of tilt_en in reg TAP_CFG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_ctrl10_c_t ctrl10_c; - lsm6ds3_tap_cfg_t tap_cfg; - int32_t ret; - - ret = 0; - - if (val == PROPERTY_ENABLE) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1); - - if (ret == 0) - { - ctrl10_c.func_en = PROPERTY_ENABLE; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1); - } - } - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1); - } - - if (ret == 0) - { - tap_cfg.tilt_en = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1); - } - - return ret; -} - -/** - * @brief Enable tilt calculation.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of tilt_en in reg TAP_CFG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_tap_cfg_t tap_cfg; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1); - *val = (uint8_t)tap_cfg.tilt_en; - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LSM6DS3_Magnetometer_sensor - * @brief This section groups all the functions that manage - * additional magnetometer sensor. - * @{ - * - */ - -/** - * @brief Enable soft-iron correction algorithm for magnetometer.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of soft_en in reg CTRL9_XL - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_ctrl10_c_t ctrl10_c; - lsm6ds3_ctrl9_xl_t ctrl9_xl; - int32_t ret; - - ret = 0; - - if (val == PROPERTY_ENABLE) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1); - - if (ret == 0) - { - ctrl10_c.func_en = PROPERTY_ENABLE; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1); - } - } - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - } - - if (ret == 0) - { - ctrl9_xl.soft_en = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - } - - return ret; -} - -/** - * @brief Enable soft-iron correction algorithm for magnetometer.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of soft_en in reg CTRL9_XL - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_ctrl9_xl_t ctrl9_xl; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); - *val = (uint8_t)ctrl9_xl.soft_en; - - return ret; -} - -/** - * @brief Enable hard-iron correction algorithm for magnetometer.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of iron_en in reg MASTER_CONFIG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_ctrl10_c_t ctrl10_c; - lsm6ds3_master_config_t master_config; - int32_t ret; - - ret = 0; - - if (val == PROPERTY_ENABLE) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1); - ctrl10_c.func_en = PROPERTY_ENABLE; - - if (ret == 0) - { - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1); - } - } - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, - (uint8_t *)&master_config, 1); - } - - if (ret == 0) - { - master_config.iron_en = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_MASTER_CONFIG, - (uint8_t *)&master_config, 1); - } - - return ret; -} - -/** - * @brief Enable hard-iron correction algorithm for magnetometer.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of iron_en in reg MASTER_CONFIG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_master_config_t master_config; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, - (uint8_t *)&master_config, 1); - *val = (uint8_t)master_config.iron_en; - - return ret; -} - -/** - * @brief Hard/soft-iron calculation status (0: on-going / 1: idle).[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of si_end_op in reg FUNC_SRC - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_mag_soft_iron_end_op_flag_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - lsm6ds3_func_src_t func_src; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_SRC, (uint8_t *)&func_src, 1); - *val = (uint8_t)func_src.si_end_op; - - return ret; -} - -/** - * @brief Soft-iron matrix correction registers[set] - * - * @param ctx read / write interface definitions(ptr) - * @param buff buffer that stores data to be write - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_mag_soft_iron_coeff_set(stmdev_ctx_t *ctx, - uint8_t *buff) -{ - int32_t ret; - - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = lsm6ds3_write_reg(ctx, LSM6DS3_MAG_SI_XX, buff, 9); - } - - if (ret == 0) - { - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); - } - - return ret; -} - -/** - * @brief Soft-iron matrix correction registers[get] - * - * @param ctx read / write interface definitions(ptr) - * @param buff buffer that stores data read - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_mag_soft_iron_coeff_get(stmdev_ctx_t *ctx, - uint8_t *buff) -{ - int32_t ret; - - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_MAG_SI_XX, buff, 9); - } - - if (ret == 0) - { - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); - } - - return ret; -} - -/** - * @brief Offset for hard-iron compensation register (r/w). - * The value is expressed as a 16-bit word in two’s complement.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param buff buffer that stores data to be write - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val) -{ - uint8_t buff[6]; - int32_t ret; - - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - buff[1] = (uint8_t)((uint16_t)val[0] / 256U); - buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U)); - buff[3] = (uint8_t)((uint16_t)val[1] / 256U); - buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U)); - buff[5] = (uint8_t)((uint16_t)val[2] / 256U); - buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U)); - ret = lsm6ds3_write_reg(ctx, LSM6DS3_MAG_OFFX_L, buff, 6); - } - - if (ret == 0) - { - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); - } - - return ret; -} - -/** - * @brief Offset for hard-iron compensation register(r/w). - * The value is expressed as a 16-bit word in two’s complement.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param buff buffer that stores data read - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val) -{ - uint8_t buff[6]; - int32_t ret; - - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_MAG_OFFX_L, buff, 6); - } - - if (ret == 0) - { - val[0] = (int16_t)buff[1]; - val[0] = (val[0] * 256) + (int16_t)buff[0]; - val[1] = (int16_t)buff[3]; - val[1] = (val[1] * 256) + (int16_t)buff[2]; - val[2] = (int16_t)buff[5]; - val[2] = (val[2] * 256) + (int16_t)buff[4]; - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); - } - - return ret; -} - -/** - * @} - * - */ - -/** - * @defgroup LSM6DS3_Sensor_hub - * @brief This section groups all the functions that manage the - * sensor hub functionality. - * @{ - * - */ - -/** - * @brief Sensor synchronization time frame with the step of 500 ms - * and full range of 5 s. Unsigned 8-bit.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of tph in reg SENSOR_SYNC_TIME_FRAME - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_sensor_sync_time_frame_t sensor_sync_time_frame; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_SENSOR_SYNC_TIME_FRAME, - (uint8_t *)& sensor_sync_time_frame, 1); - - if (ret == 0) - { - sensor_sync_time_frame.tph = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_SENSOR_SYNC_TIME_FRAME, - (uint8_t *)& sensor_sync_time_frame, 1); - } - - return ret; -} - -/** - * @brief Sensor synchronization time frame with the step of 500 ms and - * full range of 5 s. Unsigned 8-bit.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of tph in reg SENSOR_SYNC_TIME_FRAME - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, - uint8_t *val) -{ - lsm6ds3_sensor_sync_time_frame_t sensor_sync_time_frame; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_SENSOR_SYNC_TIME_FRAME, - (uint8_t *)& sensor_sync_time_frame, 1); - *val = (uint8_t) sensor_sync_time_frame.tph; - - return ret; -} -/** - * @brief Sensor hub I2C master enable.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of master_on in reg MASTER_CONFIG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_ctrl10_c_t ctrl10_c; - lsm6ds3_master_config_t master_config; - int32_t ret; - - ret = 0; - - if (val == PROPERTY_ENABLE) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1); - - if (ret == 0) - { - ctrl10_c.func_en = PROPERTY_ENABLE; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t *)&ctrl10_c, 1); - } - } - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, - (uint8_t *)&master_config, 1); - } - - if (ret == 0) - { - master_config.master_on = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_MASTER_CONFIG, - (uint8_t *)&master_config, 1); - } - - return ret; -} - -/** - * @brief Sensor hub I2C master enable.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of master_on in reg MASTER_CONFIG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_master_config_t master_config; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, - (uint8_t *)&master_config, 1); - *val = (uint8_t)master_config.master_on; - - return ret; -} -/** - * @brief I2C interface pass-through.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of pass_through_mode in - * reg MASTER_CONFIG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) -{ - lsm6ds3_master_config_t master_config; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, - (uint8_t *)&master_config, 1); - - if (ret == 0) - { - master_config.pass_through_mode = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_MASTER_CONFIG, - (uint8_t *)&master_config, 1); - } - - return ret; -} - -/** - * @brief I2C interface pass-through.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of pass_through_mode in reg MASTER_CONFIG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_master_config_t master_config; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, - (uint8_t *)&master_config, 1); - *val = (uint8_t)master_config.pass_through_mode; - - return ret; -} -/** - * @brief Master I2C pull-up enable/disable.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of pull_up_en in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_sh_pin_mode_set(stmdev_ctx_t *ctx, - lsm6ds3_sh_pin_md_t val) -{ - lsm6ds3_master_config_t master_config; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, - (uint8_t *)&master_config, 1); - - if (ret == 0) - { - master_config.pull_up_en = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_MASTER_CONFIG, - (uint8_t *)&master_config, 1); - } - - return ret; -} - -/** - * @brief Master I2C pull-up enable/disable.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of pull_up_en in reg MASTER_CONFIG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_sh_pin_mode_get(stmdev_ctx_t *ctx, - lsm6ds3_sh_pin_md_t *val) -{ - lsm6ds3_master_config_t master_config; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, - (uint8_t *)&master_config, 1); - - switch (master_config.pull_up_en) - { - case LSM6DS3_EXT_PULL_UP: - *val = LSM6DS3_EXT_PULL_UP; - break; - - case LSM6DS3_INTERNAL_PULL_UP: - *val = LSM6DS3_INTERNAL_PULL_UP; - break; - - default: - *val = LSM6DS3_EXT_PULL_UP; - break; - } - - return ret; -} - -/** - * @brief Sensor hub trigger signal selection.[set] - * - * @param ctx read / write interface definitions(ptr) - * @param val change the values of start_config in reg LSM6DS3 - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_sh_syncro_mode_set(stmdev_ctx_t *ctx, - lsm6ds3_start_cfg_t val) -{ - lsm6ds3_master_config_t master_config; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, - (uint8_t *)&master_config, 1); - - if (ret == 0) - { - master_config.start_config = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_MASTER_CONFIG, - (uint8_t *)&master_config, 1); - } - - return ret; -} - -/** - * @brief Sensor hub trigger signal selection.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of start_config in reg MASTER_CONFIG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_sh_syncro_mode_get(stmdev_ctx_t *ctx, - lsm6ds3_start_cfg_t *val) -{ - lsm6ds3_master_config_t master_config; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, - (uint8_t *)&master_config, 1); - - switch (master_config.start_config) - { - case LSM6DS3_XL_GY_DRDY: - *val = LSM6DS3_XL_GY_DRDY; - break; - - case LSM6DS3_EXT_ON_INT2_PIN: - *val = LSM6DS3_EXT_ON_INT2_PIN; - break; - - default: - *val = LSM6DS3_XL_GY_DRDY; - break; - } - - return ret; -} - -/** - * @brief Sensor hub output registers.[get] - * - * @param ctx read / write interface definitions(ptr) - * @param buff buffer that stores data read - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_sh_read_data_raw_get(stmdev_ctx_t *ctx, - lsm6ds3_sh_read_t *buff) -{ - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_SENSORHUB1_REG, - (uint8_t *) & (buff->sh_byte_1), 12); - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_SENSORHUB13_REG, - (uint8_t *) & (buff->sh_byte_13), 6); - } - - return ret; -} - -/** - * @brief sh_cfg_write: Configure slave 0 for perform a write. - * - * @param stmdev_ctx_t *ctx: read / write interface definitions - * @param lsm6ds3_sh_cfg_write_t: a structure that contain - * - uint8_t slv1_add; 8 bit i2c device address - * - uint8_t slv1_subadd; 8 bit register device address - * - uint8_t slv1_data; 8 bit data to write - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_sh_cfg_write(stmdev_ctx_t *ctx, - lsm6ds3_sh_cfg_write_t *val) -{ - lsm6ds3_slv0_add_t slv0_add; - int32_t ret; - - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - slv0_add.slave0_add = val->slv0_add >> 1; - slv0_add.rw_0 = 0; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV0_ADD, (uint8_t *)&slv0_add, 1); - } - - if (ret == 0) - { - ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV0_SUBADD, - &(val->slv0_subadd), 1); - } - - if (ret == 0) - { - ret = lsm6ds3_write_reg(ctx, LSM6DS3_DATAWRITE_SRC_MODE_SUB_SLV0, - &(val->slv0_data), 1); - } - - if (ret == 0) - { - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); - } - - return ret; -} - -/** - * @brief sh_slv0_cfg_read: [get] Configure slave 0 for perform a write/read. - * - * @param stmdev_ctx_t *ctx: read / write interface definitions - * @param lsm6ds3_sh_cfg_read_t: a structure that contain - * - uint8_t slv1_add; 8 bit i2c device address - * - uint8_t slv1_subadd; 8 bit register device address - * - uint8_t slv1_len; num of bit to read - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_sh_slv0_cfg_read(stmdev_ctx_t *ctx, - lsm6ds3_sh_cfg_read_t *val) -{ - lsm6ds3_slv0_add_t slv0_add; - lsm6ds3_slave0_config_t slave0_config; - int32_t ret; - - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - slv0_add.slave0_add = val->slv_add >> 1; - slv0_add.rw_0 = 1; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV0_ADD, (uint8_t *)&slv0_add, 1); - } - - if (ret == 0) - { - ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV0_SUBADD, - &(val->slv_subadd), 1); - } - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_SLAVE0_CONFIG, - (uint8_t *)&slave0_config, 1); - } - - if (ret == 0) - { - slave0_config.slave0_numop = val->slv_len; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLAVE0_CONFIG, - (uint8_t *)&slave0_config, 1); - } - - if (ret == 0) - { - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); - } - - return ret; -} - -/** - * @brief sh_slv1_cfg_read: [get] Configure slave 0 for perform a write/read. - * - * @param stmdev_ctx_t *ctx: read / write interface definitions - * @param lsm6ds3_sh_cfg_read_t: a structure that contain - * - uint8_t slv1_add; 8 bit i2c device address - * - uint8_t slv1_subadd; 8 bit register device address - * - uint8_t slv1_len; num of bit to read - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_sh_slv1_cfg_read(stmdev_ctx_t *ctx, - lsm6ds3_sh_cfg_read_t *val) -{ - lsm6ds3_slv1_add_t slv1_add; - lsm6ds3_slave1_config_t slave1_config; - int32_t ret; - - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - slv1_add.slave1_add = val->slv_add >> 1;; - slv1_add.r_1 = 1; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV1_ADD, (uint8_t *)&slv1_add, 1); - } - - if (ret == 0) - { - ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV1_SUBADD, - &(val->slv_subadd), 1); - } - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_SLAVE1_CONFIG, - (uint8_t *)&slave1_config, 1); - } - - if (ret == 0) - { - slave1_config.slave1_numop = val->slv_len; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLAVE1_CONFIG, - (uint8_t *)&slave1_config, 1); - } - - if (ret == 0) - { - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); - } - - return ret; -} - -/** - * @brief sh_slv2_cfg_read: [get] Configure slave 0 for perform a write/read. - * - * @param stmdev_ctx_t *ctx: read / write interface definitions - * @param lsm6ds3_sh_cfg_read_t: a structure that contain - * - uint8_t slv2_add; 8 bit i2c device address - * - uint8_t slv2_subadd; 8 bit register device address - * - uint8_t slv2_len; num of bit to read - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_sh_slv2_cfg_read(stmdev_ctx_t *ctx, - lsm6ds3_sh_cfg_read_t *val) -{ - lsm6ds3_slv2_add_t slv2_add; - lsm6ds3_slave2_config_t slave2_config; - int32_t ret; - - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - slv2_add.slave2_add = val->slv_add >> 1; - slv2_add.r_2 = 1; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV2_ADD, - (uint8_t *)&slv2_add, 1); - } - - if (ret == 0) - { - ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV2_SUBADD, - &(val->slv_subadd), 1); - } - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_SLAVE2_CONFIG, - (uint8_t *)&slave2_config, 1); - } - - if (ret == 0) - { - slave2_config.slave2_numop = val->slv_len; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLAVE2_CONFIG, - (uint8_t *)&slave2_config, 1); - } - - if (ret == 0) - { - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); - } - - return ret; -} - -/** - * @brief sh_slv3_cfg_read: [get] Configure slave 0 for perform a write/read. - * - * @param stmdev_ctx_t *ctx: read / write interface definitions - * @param lsm6ds3_sh_cfg_read_t: a structure that contain - * - uint8_t slv3_add; 8 bit i2c device address - * - uint8_t slv3_subadd; 8 bit register device address - * - uint8_t slv3_len; num of bit to read - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_sh_slv3_cfg_read(stmdev_ctx_t *ctx, - lsm6ds3_sh_cfg_read_t *val) -{ - lsm6ds3_slv3_add_t slv3_add; - lsm6ds3_slave3_config_t slave3_config; - int32_t ret; - - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - slv3_add.slave3_add = val->slv_add >> 1; - slv3_add.r_3 = 1; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV3_ADD, (uint8_t *)&slv3_add, 1); - } - - if (ret == 0) - { - ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV3_SUBADD, - &(val->slv_subadd), 1); - } - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_SLAVE3_CONFIG, - (uint8_t *)&slave3_config, 1); - } - - if (ret == 0) - { - slave3_config.slave3_numop = val->slv_len; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLAVE3_CONFIG, - (uint8_t *)&slave3_config, 1); - } - - if (ret == 0) - { - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); - } - - return ret; -} - -/** - * @brief Sensor hub communication status (0: on-going / 1: idle).[get] - * - * @param ctx read / write interface definitions(ptr) - * @param val get the values of sensor_hub_end_op in reg FUNC_SRC - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_sh_end_op_flag_get(stmdev_ctx_t *ctx, uint8_t *val) -{ - lsm6ds3_func_src_t func_src; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_SRC, (uint8_t *)&func_src, 1); - *val = (uint8_t)func_src.sensor_hub_end_op; - - return ret; -} - -/** - * @brief xl_hp_path_internal: [set] HPF or SLOPE filter selection on - * wake-up and Activity/Inactivity - * functions. - * - * @param stmdev_ctx_t *ctx: read / write interface definitions - * @param lsm6ds3_slope_fds_t: change the values of slope_fds in reg TAP_CFG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_xl_hp_path_internal_set(stmdev_ctx_t *ctx, - lsm6ds3_slope_fds_t val) -{ - lsm6ds3_tap_cfg_t tap_cfg; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1); - - if (ret == 0) - { - tap_cfg.slope_fds = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)&tap_cfg, 1); - } - - return ret; -} - -/** - * @brief xl_hp_path_internal: [get] HPF or SLOPE filter selection on - * wake-up and Activity/Inactivity - * functions. - * - * @param stmdev_ctx_t *ctx: read / write interface definitions - * @param lsm6ds3_slope_fds_t: Get the values of slope_fds in reg TAP_CFG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_xl_hp_path_internal_get(stmdev_ctx_t *ctx, - lsm6ds3_slope_fds_t *val) -{ - lsm6ds3_tap_cfg_t reg; - int32_t ret; - - ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t *)®, 1); - - switch (reg.slope_fds) - { - case LSM6DS3_USE_SLOPE: - *val = LSM6DS3_USE_SLOPE; - break; - - case LSM6DS3_USE_HPF: - *val = LSM6DS3_USE_HPF; - break; - - default: - *val = LSM6DS3_USE_SLOPE; - break; - } - - return ret; -} - -/** - * @brief sh_num_of_dev_connected: [set] Number of external sensors to - * be read by the sensor hub. - * - * @param stmdev_ctx_t *ctx: read / write interface definitions - * @param lsm6ds3_aux_sens_on_t: change the values of aux_sens_on in - * reg SLAVE0_CONFIG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx, - lsm6ds3_aux_sens_on_t val) -{ - lsm6ds3_slave0_config_t reg; - int32_t ret; - - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_SLAVE0_CONFIG, (uint8_t *)®, 1); - } - - if (ret == 0) - { - reg.aux_sens_on = (uint8_t)val; - ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLAVE0_CONFIG, (uint8_t *)®, 1); - } - - if (ret == 0) - { - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); - } - - return ret; -} - -/** - * @brief sh_num_of_dev_connected: [get] Number of external sensors to - * be read by the sensor hub. - * - * @param stmdev_ctx_t *ctx: read / write interface definitions - * @param lsm6ds3_aux_sens_on_t: Get the values of aux_sens_on in - * reg SLAVE0_CONFIG - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6ds3_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx, - lsm6ds3_aux_sens_on_t *val) -{ - lsm6ds3_slave0_config_t reg; - int32_t ret; - - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = lsm6ds3_read_reg(ctx, LSM6DS3_SLAVE0_CONFIG, (uint8_t *)®, 1); - - switch (reg.aux_sens_on) - { - case LSM6DS3_SLV_0: - *val = LSM6DS3_SLV_0; - break; - - case LSM6DS3_SLV_0_1: - *val = LSM6DS3_SLV_0_1; - break; - - case LSM6DS3_SLV_0_1_2: - *val = LSM6DS3_SLV_0_1_2; - break; - - case LSM6DS3_SLV_0_1_2_3: - *val = LSM6DS3_SLV_0_1_2_3; - break; - - default: - *val = LSM6DS3_SLV_0; - break; - } - } - - if (ret == 0) - { - ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); - } - - return ret; -} - -/** - * @} - * - */ - -/** - * @} - * - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6ds3_STdC/driver/lsm6ds3_reg.h b/sensor/stmemsc/lsm6ds3_STdC/driver/lsm6ds3_reg.h deleted file mode 100644 index 56a89a16..00000000 --- a/sensor/stmemsc/lsm6ds3_STdC/driver/lsm6ds3_reg.h +++ /dev/null @@ -1,2474 +0,0 @@ -/** - ****************************************************************************** - * @file lsm6ds3_reg.h - * @author Sensors Software Solution Team - * @brief This file contains all the functions prototypes for the - * lsm6ds3_reg.c driver. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef LSM6DS3_REGS_H -#define LSM6DS3_REGS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include -#include -#include - -/** @addtogroup LSM6DS3 - * @{ - * - */ - -/** @defgroup Endianness definitions - * @{ - * - */ - -#ifndef DRV_BYTE_ORDER -#ifndef __BYTE_ORDER__ - -#define DRV_LITTLE_ENDIAN 1234 -#define DRV_BIG_ENDIAN 4321 - -/** if _BYTE_ORDER is not defined, choose the endianness of your architecture - * by uncommenting the define which fits your platform endianness - */ -//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN -#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN - -#else /* defined __BYTE_ORDER__ */ - -#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ -#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ -#define DRV_BYTE_ORDER __BYTE_ORDER__ - -#endif /* __BYTE_ORDER__*/ -#endif /* DRV_BYTE_ORDER */ - -/** - * @} - * - */ - -/** @defgroup STMicroelectronics sensors common types - * @{ - * - */ - -#ifndef MEMS_SHARED_TYPES -#define MEMS_SHARED_TYPES - -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t bit0 : 1; - uint8_t bit1 : 1; - uint8_t bit2 : 1; - uint8_t bit3 : 1; - uint8_t bit4 : 1; - uint8_t bit5 : 1; - uint8_t bit6 : 1; - uint8_t bit7 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t bit7 : 1; - uint8_t bit6 : 1; - uint8_t bit5 : 1; - uint8_t bit4 : 1; - uint8_t bit3 : 1; - uint8_t bit2 : 1; - uint8_t bit1 : 1; - uint8_t bit0 : 1; -#endif /* DRV_BYTE_ORDER */ -} bitwise_t; - -#define PROPERTY_DISABLE (0U) -#define PROPERTY_ENABLE (1U) - -/** @addtogroup Interfaces_Functions - * @brief This section provide a set of functions used to read and - * write a generic register of the device. - * MANDATORY: return 0 -> no Error. - * @{ - * - */ - -typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); -typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); -typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); - -typedef struct -{ - /** Component mandatory fields **/ - stmdev_write_ptr write_reg; - stmdev_read_ptr read_reg; - /** Component optional fields **/ - stmdev_mdelay_ptr mdelay; - /** Customizable optional pointer **/ - void *handle; -} stmdev_ctx_t; - -/** - * @} - * - */ - -#endif /* MEMS_SHARED_TYPES */ - -#ifndef MEMS_UCF_SHARED_TYPES -#define MEMS_UCF_SHARED_TYPES - -/** @defgroup Generic address-data structure definition - * @brief This structure is useful to load a predefined configuration - * of a sensor. - * You can create a sensor configuration by your own or using - * Unico / Unicleo tools available on STMicroelectronics - * web site. - * - * @{ - * - */ - -typedef struct -{ - uint8_t address; - uint8_t data; -} ucf_line_t; - -/** - * @} - * - */ - -#endif /* MEMS_UCF_SHARED_TYPES */ - -/** - * @} - * - */ - -/** @defgroup LSM6DS3_Infos - * @{ - * - */ - -/** I2C Device Address 8 bit format if SA0=0 -> 0xD5 if SA0=1 -> 0xD7 **/ -#define LSM6DS3_I2C_ADD_L 0xD5U -#define LSM6DS3_I2C_ADD_H 0xD7U -/** Device Identification (Who am I) **/ -#define LSM6DS3_ID 0x69U - -/** - * @} - * - */ - -#define LSM6DS3_FUNC_CFG_ACCESS 0x01U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t not_used_01 : 7; - uint8_t func_cfg_en : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t func_cfg_en : 1; - uint8_t not_used_01 : 7; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_func_cfg_access_t; - -#define LSM6DS3_SENSOR_SYNC_TIME_FRAME 0x04U -typedef struct -{ - uint8_t tph : 8; -} lsm6ds3_sensor_sync_time_frame_t; - -#define LSM6DS3_FIFO_CTRL1 0x06U -typedef struct -{ - uint8_t fth : 8; -} lsm6ds3_fifo_ctrl1_t; - -#define LSM6DS3_FIFO_CTRL2 0x07U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t fth : 4; - uint8_t not_used_01 : 2; - uint8_t timer_pedo_fifo_drdy : 1; - uint8_t timer_pedo_fifo_en : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t timer_pedo_fifo_en : 1; - uint8_t timer_pedo_fifo_drdy : 1; - uint8_t not_used_01 : 2; - uint8_t fth : 4; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_fifo_ctrl2_t; - -#define LSM6DS3_FIFO_CTRL3 0x08U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t dec_fifo_xl : 3; - uint8_t dec_fifo_gyro : 3; - uint8_t not_used_01 : 2; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 2; - uint8_t dec_fifo_gyro : 3; - uint8_t dec_fifo_xl : 3; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_fifo_ctrl3_t; - -#define LSM6DS3_FIFO_CTRL4 0x09U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t dec_ds3_fifo : 3; - uint8_t dec_ds4_fifo : 3; - uint8_t only_high_data : 1; - uint8_t not_used_01 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 1; - uint8_t only_high_data : 1; - uint8_t dec_ds4_fifo : 3; - uint8_t dec_ds3_fifo : 3; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_fifo_ctrl4_t; - -#define LSM6DS3_FIFO_CTRL5 0x0AU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t fifo_mode : 3; - uint8_t odr_fifo : 4; - uint8_t not_used_01 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 1; - uint8_t odr_fifo : 4; - uint8_t fifo_mode : 3; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_fifo_ctrl5_t; - -#define LSM6DS3_ORIENT_CFG_G 0x0BU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t orient : 3; -uint8_t sign_g : - 3; /* SignX_G) + SignY_G + SignZ_G */ - uint8_t not_used_01 : 2; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 2; -uint8_t sign_g : - 3; /* SignX_G) + SignY_G + SignZ_G */ - uint8_t orient : 3; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_orient_cfg_g_t; - -#define LSM6DS3_INT1_CTRL 0x0DU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t int1_drdy_xl : 1; - uint8_t int1_drdy_g : 1; - uint8_t int1_boot : 1; - uint8_t int1_fth : 1; - uint8_t int1_fifo_ovr : 1; - uint8_t int1_full_flag : 1; - uint8_t int1_sign_mot : 1; - uint8_t int1_step_detector : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t int1_step_detector : 1; - uint8_t int1_sign_mot : 1; - uint8_t int1_full_flag : 1; - uint8_t int1_fifo_ovr : 1; - uint8_t int1_fth : 1; - uint8_t int1_boot : 1; - uint8_t int1_drdy_g : 1; - uint8_t int1_drdy_xl : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_int1_ctrl_t; - -#define LSM6DS3_INT2_CTRL 0x0EU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t int2_drdy_xl : 1; - uint8_t int2_drdy_g : 1; - uint8_t int2_drdy_temp : 1; - uint8_t int2_fth : 1; - uint8_t int2_fifo_ovr : 1; - uint8_t int2_full_flag : 1; - uint8_t int2_step_count_ov : 1; - uint8_t int2_step_delta : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t int2_step_delta : 1; - uint8_t int2_step_count_ov : 1; - uint8_t int2_full_flag : 1; - uint8_t int2_fifo_ovr : 1; - uint8_t int2_fth : 1; - uint8_t int2_drdy_temp : 1; - uint8_t int2_drdy_g : 1; - uint8_t int2_drdy_xl : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_int2_ctrl_t; - -#define LSM6DS3_WHO_AM_I 0x0FU -#define LSM6DS3_CTRL1_XL 0x10U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t bw_xl : 2; - uint8_t fs_xl : 2; - uint8_t odr_xl : 4; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t odr_xl : 4; - uint8_t fs_xl : 2; - uint8_t bw_xl : 2; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_ctrl1_xl_t; - -#define LSM6DS3_CTRL2_G 0x11U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t not_used_01 : 1; - uint8_t fs_g : 3; /* FS_G + FS_125 */ - uint8_t odr_g : 4; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t odr_g : 4; - uint8_t fs_g : 3; /* FS_G + FS_125 */ - uint8_t not_used_01 : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_ctrl2_g_t; - -#define LSM6DS3_CTRL3_C 0x12U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t sw_reset : 1; - uint8_t ble : 1; - uint8_t if_inc : 1; - uint8_t sim : 1; - uint8_t pp_od : 1; - uint8_t h_lactive : 1; - uint8_t bdu : 1; - uint8_t boot : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t boot : 1; - uint8_t bdu : 1; - uint8_t h_lactive : 1; - uint8_t pp_od : 1; - uint8_t sim : 1; - uint8_t if_inc : 1; - uint8_t ble : 1; - uint8_t sw_reset : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_ctrl3_c_t; - -#define LSM6DS3_CTRL4_C 0x13U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t stop_on_fth : 1; - uint8_t not_used_01 : 1; - uint8_t i2c_disable : 1; - uint8_t drdy_mask : 1; - uint8_t fifo_temp_en : 1; - uint8_t int2_on_int1 : 1; - uint8_t sleep_g : 1; - uint8_t xl_bw_scal_odr : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t xl_bw_scal_odr : 1; - uint8_t sleep_g : 1; - uint8_t int2_on_int1 : 1; - uint8_t fifo_temp_en : 1; - uint8_t drdy_mask : 1; - uint8_t i2c_disable : 1; - uint8_t not_used_01 : 1; - uint8_t stop_on_fth : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_ctrl4_c_t; - -#define LSM6DS3_CTRL5_C 0x14U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t st_xl : 2; - uint8_t st_g : 2; - uint8_t not_used_01 : 1; - uint8_t rounding : 3; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t rounding : 3; - uint8_t not_used_01 : 1; - uint8_t st_g : 2; - uint8_t st_xl : 2; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_ctrl5_c_t; - -#define LSM6DS3_CTRL6_C 0x15U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t not_used_01 : 4; - uint8_t xl_hm_mode : 1; -uint8_t den_mode : - 3; /* trig_en + lvl1_en + lvl2_en */ -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN -uint8_t den_mode : - 3; /* trig_en + lvl1_en + lvl2_en */ - uint8_t xl_hm_mode : 1; - uint8_t not_used_01 : 4; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_ctrl6_c_t; - -#define LSM6DS3_CTRL7_G 0x16U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t not_used_01 : 2; - uint8_t rounding_status : 1; - uint8_t hpcf_g : 2; - uint8_t hp_g_rst : 1; - uint8_t hp_g_en : 1; - uint8_t g_hm_mode : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t g_hm_mode : 1; - uint8_t hp_g_en : 1; - uint8_t hp_g_rst : 1; - uint8_t hpcf_g : 2; - uint8_t rounding_status : 1; - uint8_t not_used_01 : 2; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_ctrl7_g_t; - -#define LSM6DS3_CTRL8_XL 0x17U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t low_pass_on_6d : 1; - uint8_t not_used_01 : 1; - uint8_t hp_slope_xl_en : 1; - uint8_t not_used_02 : 2; - uint8_t hpcf_xl : 2; - uint8_t lpf2_xl_en : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t lpf2_xl_en : 1; - uint8_t hpcf_xl : 2; - uint8_t not_used_02 : 2; - uint8_t hp_slope_xl_en : 1; - uint8_t not_used_01 : 1; - uint8_t low_pass_on_6d : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_ctrl8_xl_t; - -#define LSM6DS3_CTRL9_XL 0x18U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t not_used_01 : 2; - uint8_t soft_en : 1; - uint8_t xen_xl : 1; - uint8_t yen_xl : 1; - uint8_t zen_xl : 1; - uint8_t not_used_02 : 2; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_02 : 2; - uint8_t zen_xl : 1; - uint8_t yen_xl : 1; - uint8_t xen_xl : 1; - uint8_t soft_en : 1; - uint8_t not_used_01 : 2; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_ctrl9_xl_t; - -#define LSM6DS3_CTRL10_C 0x19U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t sign_motion_en : 1; - uint8_t pedo_rst_step : 1; - uint8_t func_en : 1; - uint8_t xen_g : 1; - uint8_t yen_g : 1; - uint8_t zen_g : 1; - uint8_t not_used_01 : 2; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 2; - uint8_t zen_g : 1; - uint8_t yen_g : 1; - uint8_t xen_g : 1; - uint8_t func_en : 1; - uint8_t pedo_rst_step : 1; - uint8_t sign_motion_en : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_ctrl10_c_t; - -#define LSM6DS3_MASTER_CONFIG 0x1AU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t master_on : 1; - uint8_t iron_en : 1; - uint8_t pass_through_mode : 1; - uint8_t pull_up_en : 1; - uint8_t start_config : 1; - uint8_t not_used_01 : 1; - uint8_t data_valid_sel_fifo : 1; - uint8_t drdy_on_int1 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t drdy_on_int1 : 1; - uint8_t data_valid_sel_fifo : 1; - uint8_t not_used_01 : 1; - uint8_t start_config : 1; - uint8_t pull_up_en : 1; - uint8_t pass_through_mode : 1; - uint8_t iron_en : 1; - uint8_t master_on : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_master_config_t; - -#define LSM6DS3_WAKE_UP_SRC 0x1BU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t z_wu : 1; - uint8_t y_wu : 1; - uint8_t x_wu : 1; - uint8_t wu_ia : 1; - uint8_t sleep_state_ia : 1; - uint8_t ff_ia : 1; - uint8_t not_used_01 : 2; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 2; - uint8_t ff_ia : 1; - uint8_t sleep_state_ia : 1; - uint8_t wu_ia : 1; - uint8_t x_wu : 1; - uint8_t y_wu : 1; - uint8_t z_wu : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_wake_up_src_t; - -#define LSM6DS3_TAP_SRC 0x1CU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t z_tap : 1; - uint8_t y_tap : 1; - uint8_t x_tap : 1; - uint8_t tap_sign : 1; - uint8_t double_tap : 1; - uint8_t single_tap : 1; - uint8_t tap_ia : 1; - uint8_t not_used_01 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 1; - uint8_t tap_ia : 1; - uint8_t single_tap : 1; - uint8_t double_tap : 1; - uint8_t tap_sign : 1; - uint8_t x_tap : 1; - uint8_t y_tap : 1; - uint8_t z_tap : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_tap_src_t; - -#define LSM6DS3_D6D_SRC 0x1DU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t xl : 1; - uint8_t xh : 1; - uint8_t yl : 1; - uint8_t yh : 1; - uint8_t zl : 1; - uint8_t zh : 1; - uint8_t d6d_ia : 1; - uint8_t not_used_01 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 1; - uint8_t d6d_ia : 1; - uint8_t zh : 1; - uint8_t zl : 1; - uint8_t yh : 1; - uint8_t yl : 1; - uint8_t xh : 1; - uint8_t xl : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_d6d_src_t; - -#define LSM6DS3_STATUS_REG 0x1EU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t xlda : 1; - uint8_t gda : 1; - uint8_t tda : 1; - uint8_t not_used_01 : 5; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 5; - uint8_t tda : 1; - uint8_t gda : 1; - uint8_t xlda : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_status_reg_t; - -#define LSM6DS3_OUT_TEMP_L 0x20U -#define LSM6DS3_OUT_TEMP_H 0x21U -#define LSM6DS3_OUTX_L_G 0x22U -#define LSM6DS3_OUTX_H_G 0x23U -#define LSM6DS3_OUTY_L_G 0x24U -#define LSM6DS3_OUTY_H_G 0x25U -#define LSM6DS3_OUTZ_L_G 0x26U -#define LSM6DS3_OUTZ_H_G 0x27U -#define LSM6DS3_OUTX_L_XL 0x28U -#define LSM6DS3_OUTX_H_XL 0x29U -#define LSM6DS3_OUTY_L_XL 0x2AU -#define LSM6DS3_OUTY_H_XL 0x2BU -#define LSM6DS3_OUTZ_L_XL 0x2CU -#define LSM6DS3_OUTZ_H_XL 0x2DU -#define LSM6DS3_SENSORHUB1_REG 0x2EU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t shub1_0 : 1; - uint8_t shub1_1 : 1; - uint8_t shub1_2 : 1; - uint8_t shub1_3 : 1; - uint8_t shub1_4 : 1; - uint8_t shub1_5 : 1; - uint8_t shub1_6 : 1; - uint8_t shub1_7 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t shub1_7 : 1; - uint8_t shub1_6 : 1; - uint8_t shub1_5 : 1; - uint8_t shub1_4 : 1; - uint8_t shub1_3 : 1; - uint8_t shub1_2 : 1; - uint8_t shub1_1 : 1; - uint8_t shub1_0 : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_sensorhub1_reg_t; - -#define LSM6DS3_SENSORHUB2_REG 0x2FU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t shub2_0 : 1; - uint8_t shub2_1 : 1; - uint8_t shub2_2 : 1; - uint8_t shub2_3 : 1; - uint8_t shub2_4 : 1; - uint8_t shub2_5 : 1; - uint8_t shub2_6 : 1; - uint8_t shub2_7 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t shub2_7 : 1; - uint8_t shub2_6 : 1; - uint8_t shub2_5 : 1; - uint8_t shub2_4 : 1; - uint8_t shub2_3 : 1; - uint8_t shub2_2 : 1; - uint8_t shub2_1 : 1; - uint8_t shub2_0 : 1; -#endif /* DRV_BYTE_ORDER */ - -} lsm6ds3_sensorhub2_reg_t; - -#define LSM6DS3_SENSORHUB3_REG 0x30U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t shub3_0 : 1; - uint8_t shub3_1 : 1; - uint8_t shub3_2 : 1; - uint8_t shub3_3 : 1; - uint8_t shub3_4 : 1; - uint8_t shub3_5 : 1; - uint8_t shub3_6 : 1; - uint8_t shub3_7 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t shub3_7 : 1; - uint8_t shub3_6 : 1; - uint8_t shub3_5 : 1; - uint8_t shub3_4 : 1; - uint8_t shub3_3 : 1; - uint8_t shub3_2 : 1; - uint8_t shub3_1 : 1; - uint8_t shub3_0 : 1; -#endif /* DRV_BYTE_ORDER */ - -} lsm6ds3_sensorhub3_reg_t; - -#define LSM6DS3_SENSORHUB4_REG 0x31U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t shub4_0 : 1; - uint8_t shub4_1 : 1; - uint8_t shub4_2 : 1; - uint8_t shub4_3 : 1; - uint8_t shub4_4 : 1; - uint8_t shub4_5 : 1; - uint8_t shub4_6 : 1; - uint8_t shub4_7 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t shub4_7 : 1; - uint8_t shub4_6 : 1; - uint8_t shub4_5 : 1; - uint8_t shub4_4 : 1; - uint8_t shub4_3 : 1; - uint8_t shub4_2 : 1; - uint8_t shub4_1 : 1; - uint8_t shub4_0 : 1; -#endif /* DRV_BYTE_ORDER */ - -} lsm6ds3_sensorhub4_reg_t; - -#define LSM6DS3_SENSORHUB5_REG 0x32U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t shub5_0 : 1; - uint8_t shub5_1 : 1; - uint8_t shub5_2 : 1; - uint8_t shub5_3 : 1; - uint8_t shub5_4 : 1; - uint8_t shub5_5 : 1; - uint8_t shub5_6 : 1; - uint8_t shub5_7 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t shub5_7 : 1; - uint8_t shub5_6 : 1; - uint8_t shub5_5 : 1; - uint8_t shub5_4 : 1; - uint8_t shub5_3 : 1; - uint8_t shub5_2 : 1; - uint8_t shub5_1 : 1; - uint8_t shub5_0 : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_sensorhub5_reg_t; - -#define LSM6DS3_SENSORHUB6_REG 0x33U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t shub6_0 : 1; - uint8_t shub6_1 : 1; - uint8_t shub6_2 : 1; - uint8_t shub6_3 : 1; - uint8_t shub6_4 : 1; - uint8_t shub6_5 : 1; - uint8_t shub6_6 : 1; - uint8_t shub6_7 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t shub6_7 : 1; - uint8_t shub6_6 : 1; - uint8_t shub6_5 : 1; - uint8_t shub6_4 : 1; - uint8_t shub6_3 : 1; - uint8_t shub6_2 : 1; - uint8_t shub6_1 : 1; - uint8_t shub6_0 : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_sensorhub6_reg_t; - -#define LSM6DS3_SENSORHUB7_REG 0x34U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t shub7_0 : 1; - uint8_t shub7_1 : 1; - uint8_t shub7_2 : 1; - uint8_t shub7_3 : 1; - uint8_t shub7_4 : 1; - uint8_t shub7_5 : 1; - uint8_t shub7_6 : 1; - uint8_t shub7_7 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t shub7_7 : 1; - uint8_t shub7_6 : 1; - uint8_t shub7_5 : 1; - uint8_t shub7_4 : 1; - uint8_t shub7_3 : 1; - uint8_t shub7_2 : 1; - uint8_t shub7_1 : 1; - uint8_t shub7_0 : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_sensorhub7_reg_t; - -#define LSM6DS3_SENSORHUB8_REG 0x35U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t shub8_0 : 1; - uint8_t shub8_1 : 1; - uint8_t shub8_2 : 1; - uint8_t shub8_3 : 1; - uint8_t shub8_4 : 1; - uint8_t shub8_5 : 1; - uint8_t shub8_6 : 1; - uint8_t shub8_7 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t shub8_7 : 1; - uint8_t shub8_6 : 1; - uint8_t shub8_5 : 1; - uint8_t shub8_4 : 1; - uint8_t shub8_3 : 1; - uint8_t shub8_2 : 1; - uint8_t shub8_1 : 1; - uint8_t shub8_0 : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_sensorhub8_reg_t; - -#define LSM6DS3_SENSORHUB9_REG 0x36U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t shub9_0 : 1; - uint8_t shub9_1 : 1; - uint8_t shub9_2 : 1; - uint8_t shub9_3 : 1; - uint8_t shub9_4 : 1; - uint8_t shub9_5 : 1; - uint8_t shub9_6 : 1; - uint8_t shub9_7 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t shub9_7 : 1; - uint8_t shub9_6 : 1; - uint8_t shub9_5 : 1; - uint8_t shub9_4 : 1; - uint8_t shub9_3 : 1; - uint8_t shub9_2 : 1; - uint8_t shub9_1 : 1; - uint8_t shub9_0 : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_sensorhub9_reg_t; - -#define LSM6DS3_SENSORHUB10_REG 0x37U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t shub10_0 : 1; - uint8_t shub10_1 : 1; - uint8_t shub10_2 : 1; - uint8_t shub10_3 : 1; - uint8_t shub10_4 : 1; - uint8_t shub10_5 : 1; - uint8_t shub10_6 : 1; - uint8_t shub10_7 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t shub10_7 : 1; - uint8_t shub10_6 : 1; - uint8_t shub10_5 : 1; - uint8_t shub10_4 : 1; - uint8_t shub10_3 : 1; - uint8_t shub10_2 : 1; - uint8_t shub10_1 : 1; - uint8_t shub10_0 : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_sensorhub10_reg_t; - -#define LSM6DS3_SENSORHUB11_REG 0x38U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t shub11_0 : 1; - uint8_t shub11_1 : 1; - uint8_t shub11_2 : 1; - uint8_t shub11_3 : 1; - uint8_t shub11_4 : 1; - uint8_t shub11_5 : 1; - uint8_t shub11_6 : 1; - uint8_t shub11_7 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t shub11_7 : 1; - uint8_t shub11_6 : 1; - uint8_t shub11_5 : 1; - uint8_t shub11_4 : 1; - uint8_t shub11_3 : 1; - uint8_t shub11_2 : 1; - uint8_t shub11_1 : 1; - uint8_t shub11_0 : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_sensorhub11_reg_t; - -#define LSM6DS3_SENSORHUB12_REG 0x39U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t shub12_0 : 1; - uint8_t shub12_1 : 1; - uint8_t shub12_2 : 1; - uint8_t shub12_3 : 1; - uint8_t shub12_4 : 1; - uint8_t shub12_5 : 1; - uint8_t shub12_6 : 1; - uint8_t shub12_7 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t shub12_7 : 1; - uint8_t shub12_6 : 1; - uint8_t shub12_5 : 1; - uint8_t shub12_4 : 1; - uint8_t shub12_3 : 1; - uint8_t shub12_2 : 1; - uint8_t shub12_1 : 1; - uint8_t shub12_0 : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_sensorhub12_reg_t; - -#define LSM6DS3_FIFO_STATUS1 0x3AU -typedef struct -{ - uint8_t diff_fifo : 8; -} lsm6ds3_fifo_status1_t; - -#define LSM6DS3_FIFO_STATUS2 0x3BU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t diff_fifo : 4; - uint8_t fifo_empty : 1; - uint8_t fifo_full : 1; - uint8_t fifo_over_run : 1; - uint8_t fth : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t fth : 1; - uint8_t fifo_over_run : 1; - uint8_t fifo_full : 1; - uint8_t fifo_empty : 1; - uint8_t diff_fifo : 4; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_fifo_status2_t; - -#define LSM6DS3_FIFO_STATUS3 0x3CU -typedef struct -{ - uint8_t fifo_pattern : 8; -} lsm6ds3_fifo_status3_t; - -#define LSM6DS3_FIFO_STATUS4 0x3DU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t fifo_pattern : 2; - uint8_t not_used_01 : 6; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_01 : 6; - uint8_t fifo_pattern : 2; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_fifo_status4_t; - -#define LSM6DS3_FIFO_DATA_OUT_L 0x3EU -#define LSM6DS3_FIFO_DATA_OUT_H 0x3FU -#define LSM6DS3_TIMESTAMP0_REG 0x40U -#define LSM6DS3_TIMESTAMP1_REG 0x41U -#define LSM6DS3_TIMESTAMP2_REG 0x42U -#define LSM6DS3_STEP_TIMESTAMP_L 0x49U -#define LSM6DS3_STEP_TIMESTAMP_H 0x4AU -#define LSM6DS3_STEP_COUNTER_L 0x4BU -#define LSM6DS3_STEP_COUNTER_H 0x4CU -#define LSM6DS3_SENSORHUB13_REG 0x4DU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t shub13_0 : 1; - uint8_t shub13_1 : 1; - uint8_t shub13_2 : 1; - uint8_t shub13_3 : 1; - uint8_t shub13_4 : 1; - uint8_t shub13_5 : 1; - uint8_t shub13_6 : 1; - uint8_t shub13_7 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t shub13_7 : 1; - uint8_t shub13_6 : 1; - uint8_t shub13_5 : 1; - uint8_t shub13_4 : 1; - uint8_t shub13_3 : 1; - uint8_t shub13_2 : 1; - uint8_t shub13_1 : 1; - uint8_t shub13_0 : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_sensorhub13_reg_t; - -#define LSM6DS3_SENSORHUB14_REG 0x4EU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t shub14_0 : 1; - uint8_t shub14_1 : 1; - uint8_t shub14_2 : 1; - uint8_t shub14_3 : 1; - uint8_t shub14_4 : 1; - uint8_t shub14_5 : 1; - uint8_t shub14_6 : 1; - uint8_t shub14_7 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t shub14_7 : 1; - uint8_t shub14_6 : 1; - uint8_t shub14_5 : 1; - uint8_t shub14_4 : 1; - uint8_t shub14_3 : 1; - uint8_t shub14_2 : 1; - uint8_t shub14_1 : 1; - uint8_t shub14_0 : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_sensorhub14_reg_t; - -#define LSM6DS3_SENSORHUB15_REG 0x4FU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t shub15_0 : 1; - uint8_t shub15_1 : 1; - uint8_t shub15_2 : 1; - uint8_t shub15_3 : 1; - uint8_t shub15_4 : 1; - uint8_t shub15_5 : 1; - uint8_t shub15_6 : 1; - uint8_t shub15_7 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t shub15_7 : 1; - uint8_t shub15_6 : 1; - uint8_t shub15_5 : 1; - uint8_t shub15_4 : 1; - uint8_t shub15_3 : 1; - uint8_t shub15_2 : 1; - uint8_t shub15_1 : 1; - uint8_t shub15_0 : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_sensorhub15_reg_t; - -#define LSM6DS3_SENSORHUB16_REG 0x50U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t shub16_0 : 1; - uint8_t shub16_1 : 1; - uint8_t shub16_2 : 1; - uint8_t shub16_3 : 1; - uint8_t shub16_4 : 1; - uint8_t shub16_5 : 1; - uint8_t shub16_6 : 1; - uint8_t shub16_7 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t shub16_7 : 1; - uint8_t shub16_6 : 1; - uint8_t shub16_5 : 1; - uint8_t shub16_4 : 1; - uint8_t shub16_3 : 1; - uint8_t shub16_2 : 1; - uint8_t shub16_1 : 1; - uint8_t shub16_0 : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_sensorhub16_reg_t; - -#define LSM6DS3_SENSORHUB17_REG 0x51U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t shub17_0 : 1; - uint8_t shub17_1 : 1; - uint8_t shub17_2 : 1; - uint8_t shub17_3 : 1; - uint8_t shub17_4 : 1; - uint8_t shub17_5 : 1; - uint8_t shub17_6 : 1; - uint8_t shub17_7 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t shub17_7 : 1; - uint8_t shub17_6 : 1; - uint8_t shub17_5 : 1; - uint8_t shub17_4 : 1; - uint8_t shub17_3 : 1; - uint8_t shub17_2 : 1; - uint8_t shub17_1 : 1; - uint8_t shub17_0 : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_sensorhub17_reg_t; - -#define LSM6DS3_SENSORHUB18_REG 0x52U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t shub18_0 : 1; - uint8_t shub18_1 : 1; - uint8_t shub18_2 : 1; - uint8_t shub18_3 : 1; - uint8_t shub18_4 : 1; - uint8_t shub18_5 : 1; - uint8_t shub18_6 : 1; - uint8_t shub18_7 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t shub18_7 : 1; - uint8_t shub18_6 : 1; - uint8_t shub18_5 : 1; - uint8_t shub18_4 : 1; - uint8_t shub18_3 : 1; - uint8_t shub18_2 : 1; - uint8_t shub18_1 : 1; - uint8_t shub18_0 : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_sensorhub18_reg_t; - -#define LSM6DS3_FUNC_SRC 0x53U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t sensor_hub_end_op : 1; - uint8_t si_end_op : 1; - uint8_t not_used_01 : 1; - uint8_t step_overflow : 1; - uint8_t step_detected : 1; - uint8_t tilt_ia : 1; - uint8_t sign_motion_ia : 1; - uint8_t step_count_delta_ia : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t step_count_delta_ia : 1; - uint8_t sign_motion_ia : 1; - uint8_t tilt_ia : 1; - uint8_t step_detected : 1; - uint8_t step_overflow : 1; - uint8_t not_used_01 : 1; - uint8_t si_end_op : 1; - uint8_t sensor_hub_end_op : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_func_src_t; - -#define LSM6DS3_TAP_CFG 0x58U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t lir : 1; - uint8_t tap_z_en : 1; - uint8_t tap_y_en : 1; - uint8_t tap_x_en : 1; - uint8_t slope_fds : 1; - uint8_t tilt_en : 1; - uint8_t pedo_en : 1; - uint8_t timer_en : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t timer_en : 1; - uint8_t pedo_en : 1; - uint8_t tilt_en : 1; - uint8_t slope_fds : 1; - uint8_t tap_x_en : 1; - uint8_t tap_y_en : 1; - uint8_t tap_z_en : 1; - uint8_t lir : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_tap_cfg_t; - -#define LSM6DS3_TAP_THS_6D 0x59U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t tap_ths : 5; - uint8_t sixd_ths : 2; - uint8_t d4d_en : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t d4d_en : 1; - uint8_t sixd_ths : 2; - uint8_t tap_ths : 5; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_tap_ths_6d_t; - -#define LSM6DS3_INT_DUR2 0x5AU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t shock : 2; - uint8_t quiet : 2; - uint8_t dur : 4; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t dur : 4; - uint8_t quiet : 2; - uint8_t shock : 2; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_int_dur2_t; - -#define LSM6DS3_WAKE_UP_THS 0x5BU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t wk_ths : 6; - uint8_t inactivity : 1; - uint8_t single_double_tap : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t single_double_tap : 1; - uint8_t inactivity : 1; - uint8_t wk_ths : 6; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_wake_up_ths_t; - -#define LSM6DS3_WAKE_UP_DUR 0x5CU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t sleep_dur : 4; - uint8_t timer_hr : 1; - uint8_t wake_dur : 2; - uint8_t ff_dur : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t ff_dur : 1; - uint8_t wake_dur : 2; - uint8_t timer_hr : 1; - uint8_t sleep_dur : 4; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_wake_up_dur_t; - -#define LSM6DS3_FREE_FALL 0x5DU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t ff_ths : 3; - uint8_t ff_dur : 5; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t ff_dur : 5; - uint8_t ff_ths : 3; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_free_fall_t; - -#define LSM6DS3_MD1_CFG 0x5EU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t int1_timer : 1; - uint8_t int1_tilt : 1; - uint8_t int1_6d : 1; - uint8_t int1_double_tap : 1; - uint8_t int1_ff : 1; - uint8_t int1_wu : 1; - uint8_t int1_single_tap : 1; - uint8_t int1_inact_state : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t int1_inact_state : 1; - uint8_t int1_single_tap : 1; - uint8_t int1_wu : 1; - uint8_t int1_ff : 1; - uint8_t int1_double_tap : 1; - uint8_t int1_6d : 1; - uint8_t int1_tilt : 1; - uint8_t int1_timer : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_md1_cfg_t; - -#define LSM6DS3_MD2_CFG 0x5FU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t int2_iron : 1; - uint8_t int2_tilt : 1; - uint8_t int2_6d : 1; - uint8_t int2_double_tap : 1; - uint8_t int2_ff : 1; - uint8_t int2_wu : 1; - uint8_t int2_single_tap : 1; - uint8_t int2_inact_state : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t int2_inact_state : 1; - uint8_t int2_single_tap : 1; - uint8_t int2_wu : 1; - uint8_t int2_ff : 1; - uint8_t int2_double_tap : 1; - uint8_t int2_6d : 1; - uint8_t int2_tilt : 1; - uint8_t int2_iron : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_md2_cfg_t; - -#define LSM6DS3_OUT_MAG_RAW_X_L 0x66U -#define LSM6DS3_OUT_MAG_RAW_X_H 0x67U -#define LSM6DS3_OUT_MAG_RAW_Y_L 0x68U -#define LSM6DS3_OUT_MAG_RAW_Y_H 0x69U -#define LSM6DS3_OUT_MAG_RAW_Z_L 0x6AU -#define LSM6DS3_OUT_MAG_RAW_Z_H 0x6BU -#define LSM6DS3_SLV0_ADD 0x02U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t rw_0 : 1; - uint8_t slave0_add : 7; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t slave0_add : 7; - uint8_t rw_0 : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_slv0_add_t; - -#define LSM6DS3_SLV0_SUBADD 0x03U -typedef struct -{ - uint8_t slave0_reg : 8; -} lsm6ds3_slv0_subadd_t; - -#define LSM6DS3_SLAVE0_CONFIG 0x04U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t slave0_numop : 3; - uint8_t src_mode : 1; - uint8_t aux_sens_on : 2; - uint8_t slave0_rate : 2; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t slave0_rate : 2; - uint8_t aux_sens_on : 2; - uint8_t src_mode : 1; - uint8_t slave0_numop : 3; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_slave0_config_t; - -#define LSM6DS3_SLV1_ADD 0x05U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t r_1 : 1; - uint8_t slave1_add : 7; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t slave1_add : 7; - uint8_t r_1 : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_slv1_add_t; - -#define LSM6DS3_SLV1_SUBADD 0x06U -typedef struct -{ - uint8_t slave1_reg : 8; -} lsm6ds3_slv1_subadd_t; - -#define LSM6DS3_SLAVE1_CONFIG 0x07U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t slave1_numop : 3; - uint8_t not_used_01 : 3; - uint8_t slave1_rate : 2; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t slave1_rate : 2; - uint8_t not_used_01 : 3; - uint8_t slave1_numop : 3; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_slave1_config_t; - -#define LSM6DS3_SLV2_ADD 0x08U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t r_2 : 1; - uint8_t slave2_add : 7; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t slave2_add : 7; - uint8_t r_2 : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_slv2_add_t; - -#define LSM6DS3_SLV2_SUBADD 0x09U -typedef struct -{ - uint8_t slave2_reg : 8; -} lsm6ds3_slv2_subadd_t; - -#define LSM6DS3_SLAVE2_CONFIG 0x0AU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t slave2_numop : 3; - uint8_t not_used_01 : 3; - uint8_t slave2_rate : 2; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t slave2_rate : 2; - uint8_t not_used_01 : 3; - uint8_t slave2_numop : 3; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_slave2_config_t; - -#define LSM6DS3_SLV3_ADD 0x0BU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t r_3 : 1; - uint8_t slave3_add : 7; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t slave3_add : 7; - uint8_t r_3 : 1; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_slv3_add_t; - -#define LSM6DS3_SLV3_SUBADD 0x0CU -typedef struct -{ - uint8_t slave3_reg : 8; -} lsm6ds3_slv3_subadd_t; - -#define LSM6DS3_SLAVE3_CONFIG 0x0DU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t slave3_numop : 3; - uint8_t not_used_01 : 3; - uint8_t slave3_rate : 2; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t slave3_rate : 2; - uint8_t not_used_01 : 3; - uint8_t slave3_numop : 3; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_slave3_config_t; - -#define LSM6DS3_DATAWRITE_SRC_MODE_SUB_SLV0 0x0EU -typedef struct -{ - uint8_t slave_dataw : 8; -} lsm6ds3_datawrite_src_mode_sub_slv0_t; - -#define LSM6DS3_PEDO_THS_REG 0x0FU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t ths_min : 5; - uint8_t not_used_01 : 2; - uint8_t pedo_4g : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t pedo_4g : 1; - uint8_t not_used_01 : 2; - uint8_t ths_min : 5; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_pedo_ths_reg_t; - -#define LSM6DS3_SM_THS 0x13U -typedef struct -{ - uint8_t sm_ths : 8; -} lsm6ds3_sm_ths_t; - -#define LSM6DS3_PEDO_DEB_REG 0x14U -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t deb_step : 3; - uint8_t deb_time : 5; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t deb_time : 5; - uint8_t deb_step : 3; -#endif /* DRV_BYTE_ORDER */ -} lsm6ds3_pedo_deb_reg_t; - -#define LSM6DS3_STEP_COUNT_DELTA 0x15U -typedef struct -{ - uint8_t sc_delta : 8; -} lsm6ds3_step_count_delta_t; - -#define LSM6DS3_MAG_SI_XX 0x24U -#define LSM6DS3_MAG_SI_XY 0x25U -#define LSM6DS3_MAG_SI_XZ 0x26U -#define LSM6DS3_MAG_SI_YX 0x27U -#define LSM6DS3_MAG_SI_YY 0x28U -#define LSM6DS3_MAG_SI_YZ 0x29U -#define LSM6DS3_MAG_SI_ZX 0x2AU -#define LSM6DS3_MAG_SI_ZY 0x2BU -#define LSM6DS3_MAG_SI_ZZ 0x2CU -#define LSM6DS3_MAG_OFFX_L 0x2DU -#define LSM6DS3_MAG_OFFX_H 0x2EU -#define LSM6DS3_MAG_OFFY_L 0x2FU -#define LSM6DS3_MAG_OFFY_H 0x30U -#define LSM6DS3_MAG_OFFZ_L 0x31U -#define LSM6DS3_MAG_OFFZ_H 0x32U - -/** - * @defgroup LSM6DS3_Register_Union - * @brief This union group all the registers having a bit-field - * description. - * This union is useful but it's not needed by the driver. - * - * REMOVING this union you are compliant with: - * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " - * - * @{ - * - */ - -typedef union -{ - lsm6ds3_func_cfg_access_t func_cfg_access; - lsm6ds3_sensor_sync_time_frame_t sensor_sync_time_frame; - lsm6ds3_fifo_ctrl1_t fifo_ctrl1; - lsm6ds3_fifo_ctrl2_t fifo_ctrl2; - lsm6ds3_fifo_ctrl3_t fifo_ctrl3; - lsm6ds3_fifo_ctrl4_t fifo_ctrl4; - lsm6ds3_fifo_ctrl5_t fifo_ctrl5; - lsm6ds3_orient_cfg_g_t orient_cfg_g; - lsm6ds3_int1_ctrl_t int1_ctrl; - lsm6ds3_int2_ctrl_t int2_ctrl; - lsm6ds3_ctrl1_xl_t ctrl1_xl; - lsm6ds3_ctrl2_g_t ctrl2_g; - lsm6ds3_ctrl3_c_t ctrl3_c; - lsm6ds3_ctrl4_c_t ctrl4_c; - lsm6ds3_ctrl5_c_t ctrl5_c; - lsm6ds3_ctrl6_c_t ctrl6_c; - lsm6ds3_ctrl7_g_t ctrl7_g; - lsm6ds3_ctrl8_xl_t ctrl8_xl; - lsm6ds3_ctrl9_xl_t ctrl9_xl; - lsm6ds3_ctrl10_c_t ctrl10_c; - lsm6ds3_master_config_t master_config; - lsm6ds3_wake_up_src_t wake_up_src; - lsm6ds3_tap_src_t tap_src; - lsm6ds3_d6d_src_t d6d_src; - lsm6ds3_status_reg_t status_reg; - lsm6ds3_sensorhub1_reg_t sensorhub1_reg; - lsm6ds3_sensorhub2_reg_t sensorhub2_reg; - lsm6ds3_sensorhub3_reg_t sensorhub3_reg; - lsm6ds3_sensorhub4_reg_t sensorhub4_reg; - lsm6ds3_sensorhub5_reg_t sensorhub5_reg; - lsm6ds3_sensorhub6_reg_t sensorhub6_reg; - lsm6ds3_sensorhub7_reg_t sensorhub7_reg; - lsm6ds3_sensorhub8_reg_t sensorhub8_reg; - lsm6ds3_sensorhub9_reg_t sensorhub9_reg; - lsm6ds3_sensorhub10_reg_t sensorhub10_reg; - lsm6ds3_sensorhub11_reg_t sensorhub11_reg; - lsm6ds3_sensorhub12_reg_t sensorhub12_reg; - lsm6ds3_fifo_status1_t fifo_status1; - lsm6ds3_fifo_status2_t fifo_status2; - lsm6ds3_fifo_status3_t fifo_status3; - lsm6ds3_fifo_status4_t fifo_status4; - lsm6ds3_sensorhub13_reg_t sensorhub13_reg; - lsm6ds3_sensorhub14_reg_t sensorhub14_reg; - lsm6ds3_sensorhub15_reg_t sensorhub15_reg; - lsm6ds3_sensorhub16_reg_t sensorhub16_reg; - lsm6ds3_sensorhub17_reg_t sensorhub17_reg; - lsm6ds3_sensorhub18_reg_t sensorhub18_reg; - lsm6ds3_func_src_t func_src; - lsm6ds3_tap_cfg_t tap_cfg; - lsm6ds3_tap_ths_6d_t tap_ths_6d; - lsm6ds3_int_dur2_t int_dur2; - lsm6ds3_wake_up_ths_t wake_up_ths; - lsm6ds3_wake_up_dur_t wake_up_dur; - lsm6ds3_free_fall_t free_fall; - lsm6ds3_md1_cfg_t md1_cfg; - lsm6ds3_md2_cfg_t md2_cfg; - lsm6ds3_slv0_add_t slv0_add; - lsm6ds3_slv0_subadd_t slv0_subadd; - lsm6ds3_slave0_config_t slave0_config; - lsm6ds3_slv1_add_t slv1_add; - lsm6ds3_slv1_subadd_t slv1_subadd; - lsm6ds3_slave1_config_t slave1_config; - lsm6ds3_slv2_add_t slv2_add; - lsm6ds3_slv2_subadd_t slv2_subadd; - lsm6ds3_slave2_config_t slave2_config; - lsm6ds3_slv3_add_t slv3_add; - lsm6ds3_slv3_subadd_t slv3_subadd; - lsm6ds3_slave3_config_t slave3_config; - lsm6ds3_datawrite_src_mode_sub_slv0_t - datawrite_src_mode_sub_slv0; - lsm6ds3_pedo_ths_reg_t pedo_ths_reg; - lsm6ds3_sm_ths_t sm_ths; - lsm6ds3_pedo_deb_reg_t pedo_deb_reg; - lsm6ds3_step_count_delta_t step_count_delta; - bitwise_t bitwise; - uint8_t byte; -} lsm6ds3_reg_t; - -/** - * @} - * - */ - -#ifndef __weak -#define __weak __attribute__((weak)) -#endif /* __weak */ - -/* - * These are the basic platform dependent I/O routines to read - * and write device registers connected on a standard bus. - * The driver keeps offering a default implementation based on function - * pointers to read/write routines for backward compatibility. - * The __weak directive allows the final application to overwrite - * them with a custom implementation. - */ - -int32_t lsm6ds3_read_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len); -int32_t lsm6ds3_write_reg(stmdev_ctx_t *ctx, uint8_t reg, - uint8_t *data, - uint16_t len); - -float_t lsm6ds3_from_fs2g_to_mg(int16_t lsb); -float_t lsm6ds3_from_fs4g_to_mg(int16_t lsb); -float_t lsm6ds3_from_fs8g_to_mg(int16_t lsb); -float_t lsm6ds3_from_fs16g_to_mg(int16_t lsb); - -float_t lsm6ds3_from_fs125dps_to_mdps(int16_t lsb); -float_t lsm6ds3_from_fs250dps_to_mdps(int16_t lsb); -float_t lsm6ds3_from_fs500dps_to_mdps(int16_t lsb); -float_t lsm6ds3_from_fs1000dps_to_mdps(int16_t lsb); -float_t lsm6ds3_from_fs2000dps_to_mdps(int16_t lsb); - -float_t lsm6ds3_from_lsb_to_celsius(int16_t lsb); - -typedef enum -{ - LSM6DS3_GY_ORIENT_XYZ = 0, - LSM6DS3_GY_ORIENT_XZY = 1, - LSM6DS3_GY_ORIENT_YXZ = 2, - LSM6DS3_GY_ORIENT_YZX = 3, - LSM6DS3_GY_ORIENT_ZXY = 4, - LSM6DS3_GY_ORIENT_ZYX = 5, -} lsm6ds3_gy_orient_t; -int32_t lsm6ds3_gy_data_orient_set(stmdev_ctx_t *ctx, - lsm6ds3_gy_orient_t val); -int32_t lsm6ds3_gy_data_orient_get(stmdev_ctx_t *ctx, - lsm6ds3_gy_orient_t *val); - -typedef enum -{ - LSM6DS3_GY_SIGN_PPP = 0, - LSM6DS3_GY_SIGN_PPN = 1, - LSM6DS3_GY_SIGN_PNP = 2, - LSM6DS3_GY_SIGN_NPP = 4, - LSM6DS3_GY_SIGN_NNP = 6, - LSM6DS3_GY_SIGN_NPN = 5, - LSM6DS3_GY_SIGN_PNN = 3, - LSM6DS3_GY_SIGN_NNN = 7, -} lsm6ds3_gy_sgn_t; -int32_t lsm6ds3_gy_data_sign_set(stmdev_ctx_t *ctx, - lsm6ds3_gy_sgn_t val); -int32_t lsm6ds3_gy_data_sign_get(stmdev_ctx_t *ctx, - lsm6ds3_gy_sgn_t *val); - -typedef enum -{ - LSM6DS3_2g = 0, - LSM6DS3_16g = 1, - LSM6DS3_4g = 2, - LSM6DS3_8g = 3, -} lsm6ds3_xl_fs_t; -int32_t lsm6ds3_xl_full_scale_set(stmdev_ctx_t *ctx, - lsm6ds3_xl_fs_t val); -int32_t lsm6ds3_xl_full_scale_get(stmdev_ctx_t *ctx, - lsm6ds3_xl_fs_t *val); - -typedef enum -{ - LSM6DS3_XL_ODR_OFF = 0, - LSM6DS3_XL_ODR_12Hz5 = 1, - LSM6DS3_XL_ODR_26Hz = 2, - LSM6DS3_XL_ODR_52Hz = 3, - LSM6DS3_XL_ODR_104Hz = 4, - LSM6DS3_XL_ODR_208Hz = 5, - LSM6DS3_XL_ODR_416Hz = 6, - LSM6DS3_XL_ODR_833Hz = 7, - LSM6DS3_XL_ODR_1k66Hz = 8, - LSM6DS3_XL_ODR_3k33Hz = 9, - LSM6DS3_XL_ODR_6k66Hz = 10, -} lsm6ds3_odr_xl_t; -int32_t lsm6ds3_xl_data_rate_set(stmdev_ctx_t *ctx, - lsm6ds3_odr_xl_t val); -int32_t lsm6ds3_xl_data_rate_get(stmdev_ctx_t *ctx, - lsm6ds3_odr_xl_t *val); - -typedef enum -{ - LSM6DS3_250dps = 0, - LSM6DS3_125dps = 1, - LSM6DS3_500dps = 2, - LSM6DS3_1000dps = 4, - LSM6DS3_2000dps = 6, -} lsm6ds3_fs_g_t; -int32_t lsm6ds3_gy_full_scale_set(stmdev_ctx_t *ctx, - lsm6ds3_fs_g_t val); -int32_t lsm6ds3_gy_full_scale_get(stmdev_ctx_t *ctx, - lsm6ds3_fs_g_t *val); - -typedef enum -{ - LSM6DS3_GY_ODR_OFF = 0, - LSM6DS3_GY_ODR_12Hz5 = 1, - LSM6DS3_GY_ODR_26Hz = 2, - LSM6DS3_GY_ODR_52Hz = 3, - LSM6DS3_GY_ODR_104Hz = 4, - LSM6DS3_GY_ODR_208Hz = 5, - LSM6DS3_GY_ODR_416Hz = 6, - LSM6DS3_GY_ODR_833Hz = 7, - LSM6DS3_GY_ODR_1k66Hz = 8, -} lsm6ds3_odr_g_t; -int32_t lsm6ds3_gy_data_rate_set(stmdev_ctx_t *ctx, - lsm6ds3_odr_g_t val); -int32_t lsm6ds3_gy_data_rate_get(stmdev_ctx_t *ctx, - lsm6ds3_odr_g_t *val); - -int32_t lsm6ds3_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_block_data_update_get(stmdev_ctx_t *ctx, - uint8_t *val); - -typedef enum -{ - LSM6DS3_XL_HIGH_PERFORMANCE = 0, - LSM6DS3_XL_NORMAL = 1, -} lsm6ds3_xl_hm_mode_t; -int32_t lsm6ds3_xl_power_mode_set(stmdev_ctx_t *ctx, - lsm6ds3_xl_hm_mode_t val); -int32_t lsm6ds3_xl_power_mode_get(stmdev_ctx_t *ctx, - lsm6ds3_xl_hm_mode_t *val); - -typedef enum -{ - LSM6DS3_STAT_RND_DISABLE = 0, - LSM6DS3_STAT_RND_ENABLE = 1, -} lsm6ds3_rnd_stat_t; -int32_t lsm6ds3_rounding_on_status_set(stmdev_ctx_t *ctx, - lsm6ds3_rnd_stat_t val); -int32_t lsm6ds3_rounding_on_status_get(stmdev_ctx_t *ctx, - lsm6ds3_rnd_stat_t *val); - -typedef enum -{ - LSM6DS3_GY_HIGH_PERFORMANCE = 0, - LSM6DS3_GY_NORMAL = 1, -} lsm6ds3_g_hm_mode_t; -int32_t lsm6ds3_gy_power_mode_set(stmdev_ctx_t *ctx, - lsm6ds3_g_hm_mode_t val); -int32_t lsm6ds3_gy_power_mode_get(stmdev_ctx_t *ctx, - lsm6ds3_g_hm_mode_t *val); - -int32_t lsm6ds3_xl_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_xl_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_xl_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_xl_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_xl_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_xl_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_gy_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_gy_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_gy_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_gy_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_gy_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_gy_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val); - -typedef struct -{ - lsm6ds3_wake_up_src_t wake_up_src; - lsm6ds3_tap_src_t tap_src; - lsm6ds3_d6d_src_t d6d_src; - lsm6ds3_func_src_t func_src; -} lsm6ds3_all_src_t; -int32_t lsm6ds3_all_sources_get(stmdev_ctx_t *ctx, - lsm6ds3_all_src_t *val); - -int32_t lsm6ds3_status_reg_get(stmdev_ctx_t *ctx, - lsm6ds3_status_reg_t *val); - -int32_t lsm6ds3_xl_flag_data_ready_get(stmdev_ctx_t *ctx, - uint8_t *val); - -int32_t lsm6ds3_gy_flag_data_ready_get(stmdev_ctx_t *ctx, - uint8_t *val); - -int32_t lsm6ds3_temp_flag_data_ready_get(stmdev_ctx_t *ctx, - uint8_t *val); - -int32_t lsm6ds3_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); - -int32_t lsm6ds3_timestamp_rst_set(stmdev_ctx_t *ctx); - -int32_t lsm6ds3_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); -typedef enum -{ - LSM6DS3_LSB_6ms4 = 0, - LSM6DS3_LSB_25us = 1, -} lsm6ds3_ts_res_t; -int32_t lsm6ds3_timestamp_res_set(stmdev_ctx_t *ctx, - lsm6ds3_ts_res_t val); -int32_t lsm6ds3_timestamp_res_get(stmdev_ctx_t *ctx, - lsm6ds3_ts_res_t *val); - -typedef enum -{ - LSM6DS3_ROUND_DISABLE = 0, - LSM6DS3_ROUND_XL = 1, - LSM6DS3_ROUND_GY = 2, - LSM6DS3_ROUND_GY_XL = 3, - LSM6DS3_ROUND_SH1_TO_SH6 = 4, - LSM6DS3_ROUND_XL_SH1_TO_SH6 = 5, - LSM6DS3_ROUND_GY_XL_SH1_TO_SH12 = 6, - LSM6DS3_ROUND_GY_XL_SH1_TO_SH6 = 7, -} lsm6ds3_rounding_t; -int32_t lsm6ds3_rounding_mode_set(stmdev_ctx_t *ctx, - lsm6ds3_rounding_t val); -int32_t lsm6ds3_rounding_mode_get(stmdev_ctx_t *ctx, - lsm6ds3_rounding_t *val); - -int32_t lsm6ds3_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); - -int32_t lsm6ds3_angular_rate_raw_get(stmdev_ctx_t *ctx, - int16_t *val); - -int32_t lsm6ds3_acceleration_raw_get(stmdev_ctx_t *ctx, - int16_t *val); - -int32_t lsm6ds3_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer, - uint8_t len); - -int32_t lsm6ds3_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val); - -int32_t lsm6ds3_mag_calibrated_raw_get(stmdev_ctx_t *ctx, - int16_t *val); - -typedef enum -{ - LSM6DS3_USER_BANK = 0, - LSM6DS3_EMBEDDED_FUNC_BANK = 1, -} lsm6ds3_func_cfg_en_t; -int32_t lsm6ds3_mem_bank_set(stmdev_ctx_t *ctx, - lsm6ds3_func_cfg_en_t val); -int32_t lsm6ds3_mem_bank_get(stmdev_ctx_t *ctx, - lsm6ds3_func_cfg_en_t *val); - -int32_t lsm6ds3_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); - -int32_t lsm6ds3_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_reset_get(stmdev_ctx_t *ctx, uint8_t *val); - -typedef enum -{ - LSM6DS3_LSB_AT_LOW_ADD = 0, - LSM6DS3_MSB_AT_LOW_ADD = 1, -} lsm6ds3_ble_t; -int32_t lsm6ds3_data_format_set(stmdev_ctx_t *ctx, lsm6ds3_ble_t val); -int32_t lsm6ds3_data_format_get(stmdev_ctx_t *ctx, - lsm6ds3_ble_t *val); - -int32_t lsm6ds3_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_boot_get(stmdev_ctx_t *ctx, uint8_t *val); - -typedef enum -{ - LSM6DS3_XL_ST_DISABLE = 0, - LSM6DS3_XL_ST_POSITIVE = 1, - LSM6DS3_XL_ST_NEGATIVE = 2, -} lsm6ds3_st_xl_t; -int32_t lsm6ds3_xl_self_test_set(stmdev_ctx_t *ctx, - lsm6ds3_st_xl_t val); -int32_t lsm6ds3_xl_self_test_get(stmdev_ctx_t *ctx, - lsm6ds3_st_xl_t *val); - -typedef enum -{ - LSM6DS3_GY_ST_DISABLE = 0, - LSM6DS3_GY_ST_POSITIVE = 1, - LSM6DS3_GY_ST_NEGATIVE = 3, -} lsm6ds3_st_g_t; -int32_t lsm6ds3_gy_self_test_set(stmdev_ctx_t *ctx, - lsm6ds3_st_g_t val); -int32_t lsm6ds3_gy_self_test_get(stmdev_ctx_t *ctx, - lsm6ds3_st_g_t *val); - -int32_t lsm6ds3_filter_settling_mask_set(stmdev_ctx_t *ctx, - uint8_t val); -int32_t lsm6ds3_filter_settling_mask_get(stmdev_ctx_t *ctx, - uint8_t *val); - -typedef enum -{ - LSM6DS3_HP_CUT_OFF_8mHz1 = 0, - LSM6DS3_HP_CUT_OFF_32mHz4 = 1, - LSM6DS3_HP_CUT_OFF_2Hz07 = 2, - LSM6DS3_HP_CUT_OFF_16Hz32 = 3, -} lsm6ds3_hpcf_g_t; -int32_t lsm6ds3_gy_hp_bandwidth_set(stmdev_ctx_t *ctx, - lsm6ds3_hpcf_g_t val); -int32_t lsm6ds3_gy_hp_bandwidth_get(stmdev_ctx_t *ctx, - lsm6ds3_hpcf_g_t *val); - -int32_t lsm6ds3_gy_hp_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_gy_hp_reset_get(stmdev_ctx_t *ctx, uint8_t *val); - -typedef enum -{ - LSM6DS3_XL_HP_ODR_DIV_4 = 0, - LSM6DS3_XL_HP_ODR_DIV_100 = 1, - LSM6DS3_XL_HP_ODR_DIV_9 = 2, - LSM6DS3_XL_HP_ODR_DIV_400 = 3, -} lsm6ds3_hp_bw_t; -int32_t lsm6ds3_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, - lsm6ds3_hp_bw_t val); -int32_t lsm6ds3_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, - lsm6ds3_hp_bw_t *val); - -typedef enum -{ - LSM6DS3_XL_LP_ODR_DIV_50 = 0, - LSM6DS3_XL_LP_ODR_DIV_100 = 1, - LSM6DS3_XL_LP_ODR_DIV_9 = 2, - LSM6DS3_XL_LP_ODR_DIV_400 = 3, -} lsm6ds3_lp_bw_t; -int32_t lsm6ds3_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, - lsm6ds3_lp_bw_t val); -int32_t lsm6ds3_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, - lsm6ds3_lp_bw_t *val); - -typedef enum -{ - LSM6DS3_ANTI_ALIASING_400Hz = 0, - LSM6DS3_ANTI_ALIASING_200Hz = 1, - LSM6DS3_ANTI_ALIASING_100Hz = 2, - LSM6DS3_ANTI_ALIASING_50Hz = 3, -} lsm6ds3_bw_xl_t; -int32_t lsm6ds3_xl_filter_analog_set(stmdev_ctx_t *ctx, - lsm6ds3_bw_xl_t val); -int32_t lsm6ds3_xl_filter_analog_get(stmdev_ctx_t *ctx, - lsm6ds3_bw_xl_t *val); - -typedef enum -{ - LSM6DS3_SPI_4_WIRE = 0, - LSM6DS3_SPI_3_WIRE = 1, -} lsm6ds3_sim_t; -int32_t lsm6ds3_spi_mode_set(stmdev_ctx_t *ctx, lsm6ds3_sim_t val); -int32_t lsm6ds3_spi_mode_get(stmdev_ctx_t *ctx, lsm6ds3_sim_t *val); - -typedef enum -{ - LSM6DS3_I2C_ENABLE = 0, - LSM6DS3_I2C_DISABLE = 1, -} lsm6ds3_i2c_dis_t; -int32_t lsm6ds3_i2c_interface_set(stmdev_ctx_t *ctx, - lsm6ds3_i2c_dis_t val); -int32_t lsm6ds3_i2c_interface_get(stmdev_ctx_t *ctx, - lsm6ds3_i2c_dis_t *val); - -typedef struct -{ - uint8_t int1_drdy_xl : 1; - uint8_t int1_drdy_g : 1; - uint8_t int1_boot : 1; - uint8_t int1_fth : 1; - uint8_t int1_fifo_ovr : 1; - uint8_t int1_full_flag : 1; - uint8_t int1_sign_mot : 1; - uint8_t int1_step_detector : 1; - uint8_t int1_timer : 1; - uint8_t int1_tilt : 1; - uint8_t int1_6d : 1; - uint8_t int1_double_tap : 1; - uint8_t int1_ff : 1; - uint8_t int1_wu : 1; - uint8_t int1_single_tap : 1; - uint8_t int1_inact_state : 1; - uint8_t drdy_on_int1 : 1; -} lsm6ds3_int1_route_t; -int32_t lsm6ds3_pin_int1_route_set(stmdev_ctx_t *ctx, - lsm6ds3_int1_route_t *val); -int32_t lsm6ds3_pin_int1_route_get(stmdev_ctx_t *ctx, - lsm6ds3_int1_route_t *val); - -typedef struct -{ - uint8_t int2_drdy_xl : 1; - uint8_t int2_drdy_g : 1; - uint8_t int2_drdy_temp : 1; - uint8_t int2_fth : 1; - uint8_t int2_fifo_ovr : 1; - uint8_t int2_full_flag : 1; - uint8_t int2_step_count_ov : 1; - uint8_t int2_step_delta : 1; - uint8_t int2_iron : 1; - uint8_t int2_tilt : 1; - uint8_t int2_6d : 1; - uint8_t int2_double_tap : 1; - uint8_t int2_ff : 1; - uint8_t int2_wu : 1; - uint8_t int2_single_tap : 1; - uint8_t int2_inact_state : 1; - uint8_t start_config : 1; -} lsm6ds3_int2_route_t; -int32_t lsm6ds3_pin_int2_route_set(stmdev_ctx_t *ctx, - lsm6ds3_int2_route_t *val); -int32_t lsm6ds3_pin_int2_route_get(stmdev_ctx_t *ctx, - lsm6ds3_int2_route_t *val); - -typedef enum -{ - LSM6DS3_PUSH_PULL = 0, - LSM6DS3_OPEN_DRAIN = 1, -} lsm6ds3_pp_od_t; -int32_t lsm6ds3_pin_mode_set(stmdev_ctx_t *ctx, lsm6ds3_pp_od_t val); -int32_t lsm6ds3_pin_mode_get(stmdev_ctx_t *ctx, lsm6ds3_pp_od_t *val); - -typedef enum -{ - LSM6DS3_ACTIVE_HIGH = 0, - LSM6DS3_ACTIVE_LOW = 1, -} lsm6ds3_pin_pol_t; -int32_t lsm6ds3_pin_polarity_set(stmdev_ctx_t *ctx, - lsm6ds3_pin_pol_t val); -int32_t lsm6ds3_pin_polarity_get(stmdev_ctx_t *ctx, - lsm6ds3_pin_pol_t *val); - -int32_t lsm6ds3_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); - -typedef enum -{ - LSM6DS3_INT_PULSED = 0, - LSM6DS3_INT_LATCHED = 1, -} lsm6ds3_lir_t; -int32_t lsm6ds3_int_notification_set(stmdev_ctx_t *ctx, - lsm6ds3_lir_t val); -int32_t lsm6ds3_int_notification_get(stmdev_ctx_t *ctx, - lsm6ds3_lir_t *val); - -int32_t lsm6ds3_wkup_src_get(stmdev_ctx_t *ctx, - lsm6ds3_wake_up_src_t *val); - -int32_t lsm6ds3_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_act_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_act_mode_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_tap_src_get(stmdev_ctx_t *ctx, - lsm6ds3_tap_src_t *val); - -int32_t lsm6ds3_tap_detection_on_z_set(stmdev_ctx_t *ctx, - uint8_t val); -int32_t lsm6ds3_tap_detection_on_z_get(stmdev_ctx_t *ctx, - uint8_t *val); - -int32_t lsm6ds3_tap_detection_on_y_set(stmdev_ctx_t *ctx, - uint8_t val); -int32_t lsm6ds3_tap_detection_on_y_get(stmdev_ctx_t *ctx, - uint8_t *val); - -int32_t lsm6ds3_tap_detection_on_x_set(stmdev_ctx_t *ctx, - uint8_t val); -int32_t lsm6ds3_tap_detection_on_x_get(stmdev_ctx_t *ctx, - uint8_t *val); - -int32_t lsm6ds3_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); - -typedef enum -{ - LSM6DS3_ONLY_DOUBLE = 1, - LSM6DS3_SINGLE_DOUBLE = 0, -} lsm6ds3_tap_md_t; -int32_t lsm6ds3_tap_mode_set(stmdev_ctx_t *ctx, lsm6ds3_tap_md_t val); -int32_t lsm6ds3_tap_mode_get(stmdev_ctx_t *ctx, - lsm6ds3_tap_md_t *val); - -typedef enum -{ - LSM6DS3_ODR_DIV_2_FEED = 0, - LSM6DS3_LPF2_FEED = 1, -} lsm6ds3_low_pass_on_6d_t; -int32_t lsm6ds3_6d_feed_data_set(stmdev_ctx_t *ctx, - lsm6ds3_low_pass_on_6d_t val); -int32_t lsm6ds3_6d_feed_data_get(stmdev_ctx_t *ctx, - lsm6ds3_low_pass_on_6d_t *val); - -int32_t lsm6ds3_6d_src_get(stmdev_ctx_t *ctx, lsm6ds3_d6d_src_t *val); - -typedef enum -{ - LSM6DS3_DEG_80 = 0, - LSM6DS3_DEG_70 = 1, - LSM6DS3_DEG_60 = 2, - LSM6DS3_DEG_50 = 3, -} lsm6ds3_sixd_ths_t; -int32_t lsm6ds3_6d_threshold_set(stmdev_ctx_t *ctx, - lsm6ds3_sixd_ths_t val); -int32_t lsm6ds3_6d_threshold_get(stmdev_ctx_t *ctx, - lsm6ds3_sixd_ths_t *val); - -int32_t lsm6ds3_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); - -typedef enum -{ - LSM6DS3_156_mg = 0, - LSM6DS3_219_mg = 1, - LSM6DS3_250_mg = 2, - LSM6DS3_312_mg = 3, - LSM6DS3_344_mg = 4, - LSM6DS3_406_mg = 5, - LSM6DS3_469_mg = 6, - LSM6DS3_500_mg = 7, -} lsm6ds3_ff_ths_t; -int32_t lsm6ds3_ff_threshold_set(stmdev_ctx_t *ctx, - lsm6ds3_ff_ths_t val); -int32_t lsm6ds3_ff_threshold_get(stmdev_ctx_t *ctx, - lsm6ds3_ff_ths_t *val); - -int32_t lsm6ds3_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6ds3_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val); - -typedef enum -{ - LSM6DS3_TRG_XL_GY_DRDY = 0, - LSM6DS3_TRG_STEP_DETECT = 1, -} lsm6ds3_tmr_ped_fifo_drdy_t; -int32_t lsm6ds3_fifo_write_trigger_set(stmdev_ctx_t *ctx, - lsm6ds3_tmr_ped_fifo_drdy_t val); -int32_t lsm6ds3_fifo_write_trigger_get(stmdev_ctx_t *ctx, - lsm6ds3_tmr_ped_fifo_drdy_t *val); - -int32_t lsm6ds3_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val); - -typedef enum -{ - LSM6DS3_FIFO_XL_DISABLE = 0, - LSM6DS3_FIFO_XL_NO_DEC = 1, - LSM6DS3_FIFO_XL_DEC_2 = 2, - LSM6DS3_FIFO_XL_DEC_3 = 3, - LSM6DS3_FIFO_XL_DEC_4 = 4, - LSM6DS3_FIFO_XL_DEC_8 = 5, - LSM6DS3_FIFO_XL_DEC_16 = 6, - LSM6DS3_FIFO_XL_DEC_32 = 7, -} lsm6ds3_dec_fifo_xl_t; -int32_t lsm6ds3_fifo_xl_batch_set(stmdev_ctx_t *ctx, - lsm6ds3_dec_fifo_xl_t val); -int32_t lsm6ds3_fifo_xl_batch_get(stmdev_ctx_t *ctx, - lsm6ds3_dec_fifo_xl_t *val); - -typedef enum -{ - LSM6DS3_FIFO_GY_DISABLE = 0, - LSM6DS3_FIFO_GY_NO_DEC = 1, - LSM6DS3_FIFO_GY_DEC_2 = 2, - LSM6DS3_FIFO_GY_DEC_3 = 3, - LSM6DS3_FIFO_GY_DEC_4 = 4, - LSM6DS3_FIFO_GY_DEC_8 = 5, - LSM6DS3_FIFO_GY_DEC_16 = 6, - LSM6DS3_FIFO_GY_DEC_32 = 7, -} lsm6ds3_dec_fifo_gyro_t; -int32_t lsm6ds3_fifo_gy_batch_set(stmdev_ctx_t *ctx, - lsm6ds3_dec_fifo_gyro_t val); -int32_t lsm6ds3_fifo_gy_batch_get(stmdev_ctx_t *ctx, - lsm6ds3_dec_fifo_gyro_t *val); - -typedef enum -{ - LSM6DS3_FIFO_DS3_DISABLE = 0, - LSM6DS3_FIFO_DS3_NO_DEC = 1, - LSM6DS3_FIFO_DS3_DEC_2 = 2, - LSM6DS3_FIFO_DS3_DEC_3 = 3, - LSM6DS3_FIFO_DS3_DEC_4 = 4, - LSM6DS3_FIFO_DS3_DEC_8 = 5, - LSM6DS3_FIFO_DS3_DEC_16 = 6, - LSM6DS3_FIFO_DS3_DEC_32 = 7, -} lsm6ds3_dec_ds3_fifo_t; -int32_t lsm6ds3_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx, - lsm6ds3_dec_ds3_fifo_t val); -int32_t lsm6ds3_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx, - lsm6ds3_dec_ds3_fifo_t *val); - -typedef enum -{ - LSM6DS3_FIFO_DS4_DISABLE = 0, - LSM6DS3_FIFO_DS4_NO_DEC = 1, - LSM6DS3_FIFO_DS4_DEC_2 = 2, - LSM6DS3_FIFO_DS4_DEC_3 = 3, - LSM6DS3_FIFO_DS4_DEC_4 = 4, - LSM6DS3_FIFO_DS4_DEC_8 = 5, - LSM6DS3_FIFO_DS4_DEC_16 = 6, - LSM6DS3_FIFO_DS4_DEC_32 = 7, -} lsm6ds3_dec_ds4_fifo_t; -int32_t lsm6ds3_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx, - lsm6ds3_dec_ds4_fifo_t val); -int32_t lsm6ds3_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx, - lsm6ds3_dec_ds4_fifo_t *val); - -int32_t lsm6ds3_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, - uint8_t val); -int32_t lsm6ds3_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, - uint8_t *val); - -typedef enum -{ - LSM6DS3_BYPASS_MODE = 0, - LSM6DS3_FIFO_MODE = 1, - LSM6DS3_STREAM_TO_FIFO_MODE = 3, - LSM6DS3_BYPASS_TO_STREAM_MODE = 4, - LSM6DS3_STREAM_MODE = 6, -} lsm6ds3_fifo_md_t; -int32_t lsm6ds3_fifo_mode_set(stmdev_ctx_t *ctx, - lsm6ds3_fifo_md_t val); -int32_t lsm6ds3_fifo_mode_get(stmdev_ctx_t *ctx, - lsm6ds3_fifo_md_t *val); - -typedef enum -{ - LSM6DS3_FIFO_DISABLE = 0, - LSM6DS3_FIFO_12Hz5 = 1, - LSM6DS3_FIFO_26Hz = 2, - LSM6DS3_FIFO_52Hz = 3, - LSM6DS3_FIFO_104Hz = 4, - LSM6DS3_FIFO_208Hz = 5, - LSM6DS3_FIFO_416Hz = 6, - LSM6DS3_FIFO_833Hz = 7, - LSM6DS3_FIFO_1k66Hz = 8, - LSM6DS3_FIFO_3k33Hz = 9, - LSM6DS3_FIFO_6k66Hz = 10, -} lsm6ds3_odr_fifo_t; -int32_t lsm6ds3_fifo_data_rate_set(stmdev_ctx_t *ctx, - lsm6ds3_odr_fifo_t val); -int32_t lsm6ds3_fifo_data_rate_get(stmdev_ctx_t *ctx, - lsm6ds3_odr_fifo_t *val); - -int32_t lsm6ds3_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val); - -int32_t lsm6ds3_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val); - -typedef enum -{ - LSM6DS3_DEN_DISABLE = 0, - LSM6DS3_LEVEL_FIFO = 6, - LSM6DS3_LEVEL_LETCHED = 3, - LSM6DS3_LEVEL_TRIGGER = 2, - LSM6DS3_EDGE_TRIGGER = 4, -} lsm6ds3_den_mode_t; -int32_t lsm6ds3_den_mode_set(stmdev_ctx_t *ctx, - lsm6ds3_den_mode_t val); -int32_t lsm6ds3_den_mode_get(stmdev_ctx_t *ctx, - lsm6ds3_den_mode_t *val); - -int32_t lsm6ds3_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_pedo_timestamp_raw_get(stmdev_ctx_t *ctx, - uint16_t *val); - -int32_t lsm6ds3_pedo_step_detect_flag_get(stmdev_ctx_t *ctx, - uint8_t *val); - -int32_t lsm6ds3_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); - -typedef enum -{ - LSM6DS3_PEDO_AT_2g = 0, - LSM6DS3_PEDO_AT_4g = 1, -} lsm6ds3_pedo_fs_t; -int32_t lsm6ds3_pedo_full_scale_set(stmdev_ctx_t *ctx, - lsm6ds3_pedo_fs_t val); -int32_t lsm6ds3_pedo_full_scale_get(stmdev_ctx_t *ctx, - lsm6ds3_pedo_fs_t *val); - -int32_t lsm6ds3_pedo_debounce_steps_set(stmdev_ctx_t *ctx, - uint8_t val); -int32_t lsm6ds3_pedo_debounce_steps_get(stmdev_ctx_t *ctx, - uint8_t *val); - -int32_t lsm6ds3_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_motion_event_flag_get(stmdev_ctx_t *ctx, - uint8_t *val); - -int32_t lsm6ds3_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_sc_delta_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_sc_delta_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_tilt_event_flag_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_mag_soft_iron_end_op_flag_get(stmdev_ctx_t *ctx, - uint8_t *val); - -int32_t lsm6ds3_mag_soft_iron_coeff_set(stmdev_ctx_t *ctx, - uint8_t *buff); -int32_t lsm6ds3_mag_soft_iron_coeff_get(stmdev_ctx_t *ctx, - uint8_t *buff); - -int32_t lsm6ds3_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6ds3_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val); - -int32_t lsm6ds3_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, - uint8_t val); -int32_t lsm6ds3_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, - uint8_t *val); - -int32_t lsm6ds3_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); - -int32_t lsm6ds3_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val); - -typedef enum -{ - LSM6DS3_EXT_PULL_UP = 0, - LSM6DS3_INTERNAL_PULL_UP = 1, -} lsm6ds3_sh_pin_md_t; -int32_t lsm6ds3_sh_pin_mode_set(stmdev_ctx_t *ctx, - lsm6ds3_sh_pin_md_t val); -int32_t lsm6ds3_sh_pin_mode_get(stmdev_ctx_t *ctx, - lsm6ds3_sh_pin_md_t *val); - -typedef enum -{ - LSM6DS3_XL_GY_DRDY = 0, - LSM6DS3_EXT_ON_INT2_PIN = 1, -} lsm6ds3_start_cfg_t; -int32_t lsm6ds3_sh_syncro_mode_set(stmdev_ctx_t *ctx, - lsm6ds3_start_cfg_t val); -int32_t lsm6ds3_sh_syncro_mode_get(stmdev_ctx_t *ctx, - lsm6ds3_start_cfg_t *val); - -typedef struct -{ - lsm6ds3_sensorhub1_reg_t sh_byte_1; - lsm6ds3_sensorhub2_reg_t sh_byte_2; - lsm6ds3_sensorhub3_reg_t sh_byte_3; - lsm6ds3_sensorhub4_reg_t sh_byte_4; - lsm6ds3_sensorhub5_reg_t sh_byte_5; - lsm6ds3_sensorhub6_reg_t sh_byte_6; - lsm6ds3_sensorhub7_reg_t sh_byte_7; - lsm6ds3_sensorhub8_reg_t sh_byte_8; - lsm6ds3_sensorhub9_reg_t sh_byte_9; - lsm6ds3_sensorhub10_reg_t sh_byte_10; - lsm6ds3_sensorhub11_reg_t sh_byte_11; - lsm6ds3_sensorhub12_reg_t sh_byte_12; - lsm6ds3_sensorhub13_reg_t sh_byte_13; - lsm6ds3_sensorhub14_reg_t sh_byte_14; - lsm6ds3_sensorhub15_reg_t sh_byte_15; - lsm6ds3_sensorhub16_reg_t sh_byte_16; - lsm6ds3_sensorhub17_reg_t sh_byte_17; - lsm6ds3_sensorhub18_reg_t sh_byte_18; -} lsm6ds3_sh_read_t; -int32_t lsm6ds3_sh_read_data_raw_get(stmdev_ctx_t *ctx, - lsm6ds3_sh_read_t *buff); - -typedef enum -{ - LSM6DS3_SLV_0 = 0, - LSM6DS3_SLV_0_1 = 1, - LSM6DS3_SLV_0_1_2 = 2, - LSM6DS3_SLV_0_1_2_3 = 3, -} lsm6ds3_aux_sens_on_t; -int32_t lsm6ds3_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx, - lsm6ds3_aux_sens_on_t val); -int32_t lsm6ds3_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx, - lsm6ds3_aux_sens_on_t *val); - -typedef struct -{ - uint8_t slv0_add; - uint8_t slv0_subadd; - uint8_t slv0_data; -} lsm6ds3_sh_cfg_write_t; -int32_t lsm6ds3_sh_cfg_write(stmdev_ctx_t *ctx, - lsm6ds3_sh_cfg_write_t *val); - -typedef struct -{ - uint8_t slv_add; - uint8_t slv_subadd; - uint8_t slv_len; -} lsm6ds3_sh_cfg_read_t; -int32_t lsm6ds3_sh_slv0_cfg_read(stmdev_ctx_t *ctx, - lsm6ds3_sh_cfg_read_t *val); -int32_t lsm6ds3_sh_slv1_cfg_read(stmdev_ctx_t *ctx, - lsm6ds3_sh_cfg_read_t *val); -int32_t lsm6ds3_sh_slv2_cfg_read(stmdev_ctx_t *ctx, - lsm6ds3_sh_cfg_read_t *val); -int32_t lsm6ds3_sh_slv3_cfg_read(stmdev_ctx_t *ctx, - lsm6ds3_sh_cfg_read_t *val); - -int32_t lsm6ds3_sh_end_op_flag_get(stmdev_ctx_t *ctx, uint8_t *val); - -typedef enum -{ - LSM6DS3_USE_SLOPE = 0, - LSM6DS3_USE_HPF = 1, -} lsm6ds3_slope_fds_t; -int32_t lsm6ds3_xl_hp_path_internal_set(stmdev_ctx_t *ctx, - lsm6ds3_slope_fds_t val); -int32_t lsm6ds3_xl_hp_path_internal_get(stmdev_ctx_t *ctx, - lsm6ds3_slope_fds_t *val); - -/** - *@} - * - */ - -#ifdef __cplusplus -} -#endif - -#endif /* LSM6DS3_REGS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr-c_reg.c b/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr-c_reg.c index 0da47e10..6bc987f6 100644 --- a/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr-c_reg.c +++ b/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr-c_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm6ds3tr_c_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm6ds3tr_c_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lsm6ds3tr_c_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm6ds3tr_c_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm6ds3tr_c_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -162,7 +172,7 @@ float_t lsm6ds3tr_c_from_lsb_to_celsius(int16_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_xl_t val) { lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl; @@ -189,7 +199,7 @@ int32_t lsm6ds3tr_c_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_xl_t *val) { lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl; @@ -232,7 +242,7 @@ int32_t lsm6ds3tr_c_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_xl_t val) { lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl; @@ -259,7 +269,7 @@ int32_t lsm6ds3tr_c_xl_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_xl_t *val) { lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl; @@ -334,7 +344,7 @@ int32_t lsm6ds3tr_c_xl_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_g_t val) { lsm6ds3tr_c_ctrl2_g_t ctrl2_g; @@ -361,7 +371,7 @@ int32_t lsm6ds3tr_c_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_g_t *val) { lsm6ds3tr_c_ctrl2_g_t ctrl2_g; @@ -408,7 +418,7 @@ int32_t lsm6ds3tr_c_gy_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_gy_data_rate_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_g_t val) { lsm6ds3tr_c_ctrl2_g_t ctrl2_g; @@ -435,7 +445,7 @@ int32_t lsm6ds3tr_c_gy_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_g_t *val) { lsm6ds3tr_c_ctrl2_g_t ctrl2_g; @@ -506,7 +516,7 @@ int32_t lsm6ds3tr_c_gy_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_block_data_update_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_ctrl3_c_t ctrl3_c; @@ -533,7 +543,7 @@ int32_t lsm6ds3tr_c_block_data_update_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_ctrl3_c_t ctrl3_c; @@ -555,7 +565,7 @@ int32_t lsm6ds3tr_c_block_data_update_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_offset_weight_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_usr_off_w_t val) { lsm6ds3tr_c_ctrl6_c_t ctrl6_c; @@ -583,7 +593,7 @@ int32_t lsm6ds3tr_c_xl_offset_weight_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_offset_weight_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_usr_off_w_t *val) { lsm6ds3tr_c_ctrl6_c_t ctrl6_c; @@ -618,7 +628,7 @@ int32_t lsm6ds3tr_c_xl_offset_weight_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_xl_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_power_mode_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_xl_hm_mode_t val) { lsm6ds3tr_c_ctrl6_c_t ctrl6_c; @@ -645,7 +655,7 @@ int32_t lsm6ds3tr_c_xl_power_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_xl_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_power_mode_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_xl_hm_mode_t *val) { lsm6ds3tr_c_ctrl6_c_t ctrl6_c; @@ -682,7 +692,7 @@ int32_t lsm6ds3tr_c_xl_power_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_rounding_on_status_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_rounding_on_status_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_rounding_status_t val) { lsm6ds3tr_c_ctrl7_g_t ctrl7_g; @@ -711,7 +721,7 @@ int32_t lsm6ds3tr_c_rounding_on_status_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_rounding_on_status_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_rounding_on_status_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_rounding_status_t *val) { lsm6ds3tr_c_ctrl7_g_t ctrl7_g; @@ -746,7 +756,7 @@ int32_t lsm6ds3tr_c_rounding_on_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_gy_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_gy_power_mode_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_g_hm_mode_t val) { lsm6ds3tr_c_ctrl7_g_t ctrl7_g; @@ -773,7 +783,7 @@ int32_t lsm6ds3tr_c_gy_power_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_gy_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_gy_power_mode_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_g_hm_mode_t *val) { lsm6ds3tr_c_ctrl7_g_t ctrl7_g; @@ -809,7 +819,7 @@ int32_t lsm6ds3tr_c_gy_power_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_all_sources_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_all_sources_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_all_sources_t *val) { int32_t ret; @@ -879,7 +889,7 @@ int32_t lsm6ds3tr_c_all_sources_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_status_reg_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_status_reg_t *val) { int32_t ret; @@ -898,7 +908,7 @@ int32_t lsm6ds3tr_c_status_reg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_status_reg_t status_reg; @@ -919,7 +929,7 @@ int32_t lsm6ds3tr_c_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_status_reg_t status_reg; @@ -940,7 +950,7 @@ int32_t lsm6ds3tr_c_gy_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_status_reg_t status_reg; @@ -963,7 +973,7 @@ int32_t lsm6ds3tr_c_temp_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_xl_usr_offset_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -983,7 +993,7 @@ int32_t lsm6ds3tr_c_xl_usr_offset_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_xl_usr_offset_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1015,7 +1025,7 @@ int32_t lsm6ds3tr_c_xl_usr_offset_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6ds3tr_c_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_ctrl10_c_t ctrl10_c; int32_t ret; @@ -1047,7 +1057,7 @@ int32_t lsm6ds3tr_c_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6ds3tr_c_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_ctrl10_c_t ctrl10_c; int32_t ret; @@ -1072,7 +1082,7 @@ int32_t lsm6ds3tr_c_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_timestamp_res_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_timestamp_res_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_timer_hr_t val) { lsm6ds3tr_c_wake_up_dur_t wake_up_dur; @@ -1104,7 +1114,7 @@ int32_t lsm6ds3tr_c_timestamp_res_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_timestamp_res_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_timestamp_res_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_timer_hr_t *val) { lsm6ds3tr_c_wake_up_dur_t wake_up_dur; @@ -1152,7 +1162,7 @@ int32_t lsm6ds3tr_c_timestamp_res_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_rounding_mode_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_rounding_t val) { lsm6ds3tr_c_ctrl5_c_t ctrl5_c; @@ -1180,7 +1190,7 @@ int32_t lsm6ds3tr_c_rounding_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_rounding_mode_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_rounding_t *val) { lsm6ds3tr_c_ctrl5_c_t ctrl5_c; @@ -1240,7 +1250,7 @@ int32_t lsm6ds3tr_c_rounding_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; @@ -1262,7 +1272,7 @@ int32_t lsm6ds3tr_c_temperature_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_angular_rate_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -1288,7 +1298,7 @@ int32_t lsm6ds3tr_c_angular_rate_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -1313,7 +1323,7 @@ int32_t lsm6ds3tr_c_acceleration_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_mag_calibrated_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_mag_calibrated_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -1339,7 +1349,7 @@ int32_t lsm6ds3tr_c_mag_calibrated_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_fifo_raw_data_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_raw_data_get(const stmdev_ctx_t *ctx, uint8_t *buffer, uint8_t len) { @@ -1372,7 +1382,7 @@ int32_t lsm6ds3tr_c_fifo_raw_data_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_mem_bank_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_mem_bank_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_func_cfg_en_t val) { lsm6ds3tr_c_func_cfg_access_t func_cfg_access; @@ -1400,7 +1410,7 @@ int32_t lsm6ds3tr_c_mem_bank_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_mem_bank_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_mem_bank_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_func_cfg_en_t *val) { lsm6ds3tr_c_func_cfg_access_t func_cfg_access; @@ -1435,7 +1445,7 @@ int32_t lsm6ds3tr_c_mem_bank_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_drdy_pulsed_g_t val) { lsm6ds3tr_c_drdy_pulse_cfg_g_t drdy_pulse_cfg_g; @@ -1462,7 +1472,7 @@ int32_t lsm6ds3tr_c_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_drdy_pulsed_g_t *val) { lsm6ds3tr_c_drdy_pulse_cfg_g_t drdy_pulse_cfg_g; @@ -1497,7 +1507,7 @@ int32_t lsm6ds3tr_c_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6ds3tr_c_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1514,7 +1524,7 @@ int32_t lsm6ds3tr_c_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6ds3tr_c_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1540,7 +1550,7 @@ int32_t lsm6ds3tr_c_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6ds3tr_c_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1560,7 +1570,7 @@ int32_t lsm6ds3tr_c_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_data_format_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_data_format_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_ble_t val) { lsm6ds3tr_c_ctrl3_c_t ctrl3_c; @@ -1587,7 +1597,7 @@ int32_t lsm6ds3tr_c_data_format_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_data_format_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_data_format_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_ble_t *val) { lsm6ds3tr_c_ctrl3_c_t ctrl3_c; @@ -1623,7 +1633,7 @@ int32_t lsm6ds3tr_c_data_format_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6ds3tr_c_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1650,7 +1660,7 @@ int32_t lsm6ds3tr_c_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_auto_increment_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_ctrl3_c_t ctrl3_c; @@ -1671,7 +1681,7 @@ int32_t lsm6ds3tr_c_auto_increment_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6ds3tr_c_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1697,7 +1707,7 @@ int32_t lsm6ds3tr_c_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6ds3tr_c_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1717,7 +1727,7 @@ int32_t lsm6ds3tr_c_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_st_xl_t val) { lsm6ds3tr_c_ctrl5_c_t ctrl5_c; @@ -1744,7 +1754,7 @@ int32_t lsm6ds3tr_c_xl_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_st_xl_t *val) { lsm6ds3tr_c_ctrl5_c_t ctrl5_c; @@ -1783,7 +1793,7 @@ int32_t lsm6ds3tr_c_xl_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_st_g_t val) { lsm6ds3tr_c_ctrl5_c_t ctrl5_c; @@ -1810,7 +1820,7 @@ int32_t lsm6ds3tr_c_gy_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_st_g_t *val) { lsm6ds3tr_c_ctrl5_c_t ctrl5_c; @@ -1863,7 +1873,7 @@ int32_t lsm6ds3tr_c_gy_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_ctrl4_c_t ctrl4_c; @@ -1891,7 +1901,7 @@ int32_t lsm6ds3tr_c_filter_settling_mask_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_ctrl4_c_t ctrl4_c; @@ -1913,7 +1923,7 @@ int32_t lsm6ds3tr_c_filter_settling_mask_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_slope_fds_t val) { lsm6ds3tr_c_tap_cfg_t tap_cfg; @@ -1941,7 +1951,7 @@ int32_t lsm6ds3tr_c_xl_hp_path_internal_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_slope_fds_t *val) { lsm6ds3tr_c_tap_cfg_t tap_cfg; @@ -1990,7 +2000,7 @@ int32_t lsm6ds3tr_c_xl_hp_path_internal_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_xl_filter_analog_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_filter_analog_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_bw0_xl_t val) { lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl; @@ -2018,7 +2028,7 @@ int32_t lsm6ds3tr_c_xl_filter_analog_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_xl_filter_analog_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_filter_analog_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_bw0_xl_t *val) { lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl; @@ -2067,7 +2077,7 @@ int32_t lsm6ds3tr_c_xl_filter_analog_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_xl_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_lpf1_bw_sel_t val) { lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl; @@ -2110,7 +2120,7 @@ int32_t lsm6ds3tr_c_xl_lp1_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_xl_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_lpf1_bw_sel_t *val) { lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl; @@ -2161,7 +2171,7 @@ int32_t lsm6ds3tr_c_xl_lp1_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_input_composite_t val) { lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl; @@ -2191,7 +2201,7 @@ int32_t lsm6ds3tr_c_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_input_composite_t *val) { lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl; @@ -2262,7 +2272,7 @@ int32_t lsm6ds3tr_c_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_xl_reference_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl; @@ -2289,7 +2299,7 @@ int32_t lsm6ds3tr_c_xl_reference_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_xl_reference_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl; @@ -2310,7 +2320,7 @@ int32_t lsm6ds3tr_c_xl_reference_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_hp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_hpcf_xl_t val) { lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl; @@ -2339,7 +2349,7 @@ int32_t lsm6ds3tr_c_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_hp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_hpcf_xl_t *val) { lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl; @@ -2400,7 +2410,7 @@ int32_t lsm6ds3tr_c_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_gy_band_pass_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_gy_band_pass_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_lpf1_sel_g_t val) { lsm6ds3tr_c_ctrl4_c_t ctrl4_c; @@ -2456,7 +2466,7 @@ int32_t lsm6ds3tr_c_gy_band_pass_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_gy_band_pass_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_gy_band_pass_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_lpf1_sel_g_t *val) { lsm6ds3tr_c_ctrl4_c_t ctrl4_c; @@ -2559,7 +2569,7 @@ int32_t lsm6ds3tr_c_gy_band_pass_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_spi_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_spi_mode_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_sim_t val) { lsm6ds3tr_c_ctrl3_c_t ctrl3_c; @@ -2586,7 +2596,7 @@ int32_t lsm6ds3tr_c_spi_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_spi_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_spi_mode_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_sim_t *val) { lsm6ds3tr_c_ctrl3_c_t ctrl3_c; @@ -2621,7 +2631,7 @@ int32_t lsm6ds3tr_c_spi_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_i2c_interface_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_i2c_disable_t val) { lsm6ds3tr_c_ctrl4_c_t ctrl4_c; @@ -2648,7 +2658,7 @@ int32_t lsm6ds3tr_c_i2c_interface_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_i2c_interface_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_i2c_disable_t *val) { lsm6ds3tr_c_ctrl4_c_t ctrl4_c; @@ -2697,7 +2707,7 @@ int32_t lsm6ds3tr_c_i2c_interface_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_int1_route_t val) { lsm6ds3tr_c_master_config_t master_config; @@ -2822,7 +2832,7 @@ int32_t lsm6ds3tr_c_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_int1_route_t *val) { lsm6ds3tr_c_master_config_t master_config; @@ -2881,7 +2891,7 @@ int32_t lsm6ds3tr_c_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_int2_route_t val) { lsm6ds3tr_c_int2_ctrl_t int2_ctrl; @@ -2991,7 +3001,7 @@ int32_t lsm6ds3tr_c_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pin_int2_route_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_int2_route_t *val) { lsm6ds3tr_c_int2_ctrl_t int2_ctrl; @@ -3042,7 +3052,7 @@ int32_t lsm6ds3tr_c_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pin_mode_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_pp_od_t val) { lsm6ds3tr_c_ctrl3_c_t ctrl3_c; @@ -3069,7 +3079,7 @@ int32_t lsm6ds3tr_c_pin_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pin_mode_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_pp_od_t *val) { lsm6ds3tr_c_ctrl3_c_t ctrl3_c; @@ -3104,7 +3114,7 @@ int32_t lsm6ds3tr_c_pin_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pin_polarity_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_h_lactive_t val) { lsm6ds3tr_c_ctrl3_c_t ctrl3_c; @@ -3131,7 +3141,7 @@ int32_t lsm6ds3tr_c_pin_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pin_polarity_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_h_lactive_t *val) { lsm6ds3tr_c_ctrl3_c_t ctrl3_c; @@ -3166,7 +3176,7 @@ int32_t lsm6ds3tr_c_pin_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6ds3tr_c_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_ctrl4_c_t ctrl4_c; int32_t ret; @@ -3192,7 +3202,7 @@ int32_t lsm6ds3tr_c_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6ds3tr_c_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_ctrl4_c_t ctrl4_c; int32_t ret; @@ -3212,7 +3222,7 @@ int32_t lsm6ds3tr_c_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_int_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_int_notification_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_lir_t val) { lsm6ds3tr_c_tap_cfg_t tap_cfg; @@ -3239,7 +3249,7 @@ int32_t lsm6ds3tr_c_int_notification_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_int_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_int_notification_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_lir_t *val) { lsm6ds3tr_c_tap_cfg_t tap_cfg; @@ -3287,7 +3297,7 @@ int32_t lsm6ds3tr_c_int_notification_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6ds3tr_c_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_wake_up_ths_t wake_up_ths; int32_t ret; @@ -3313,7 +3323,7 @@ int32_t lsm6ds3tr_c_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_wkup_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_wake_up_ths_t wake_up_ths; @@ -3334,7 +3344,7 @@ int32_t lsm6ds3tr_c_wkup_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6ds3tr_c_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_wake_up_dur_t wake_up_dur; int32_t ret; @@ -3360,7 +3370,7 @@ int32_t lsm6ds3tr_c_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6ds3tr_c_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_wake_up_dur_t wake_up_dur; int32_t ret; @@ -3393,7 +3403,7 @@ int32_t lsm6ds3tr_c_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6ds3tr_c_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_ctrl4_c_t ctrl4_c; int32_t ret; @@ -3419,7 +3429,7 @@ int32_t lsm6ds3tr_c_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6ds3tr_c_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_ctrl4_c_t ctrl4_c; int32_t ret; @@ -3439,7 +3449,7 @@ int32_t lsm6ds3tr_c_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_act_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_act_mode_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_inact_en_t val) { lsm6ds3tr_c_tap_cfg_t tap_cfg; @@ -3466,7 +3476,7 @@ int32_t lsm6ds3tr_c_act_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_act_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_act_mode_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_inact_en_t *val) { lsm6ds3tr_c_tap_cfg_t tap_cfg; @@ -3509,7 +3519,7 @@ int32_t lsm6ds3tr_c_act_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6ds3tr_c_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_wake_up_dur_t wake_up_dur; int32_t ret; @@ -3535,7 +3545,7 @@ int32_t lsm6ds3tr_c_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6ds3tr_c_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_wake_up_dur_t wake_up_dur; int32_t ret; @@ -3568,7 +3578,7 @@ int32_t lsm6ds3tr_c_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_tap_src_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tap_src_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_tap_src_t *val) { int32_t ret; @@ -3585,7 +3595,7 @@ int32_t lsm6ds3tr_c_tap_src_get(stmdev_ctx_t *ctx, * @param val Change the values of tap_z_en in reg TAP_CFG * */ -int32_t lsm6ds3tr_c_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_tap_cfg_t tap_cfg; @@ -3612,7 +3622,7 @@ int32_t lsm6ds3tr_c_tap_detection_on_z_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_tap_cfg_t tap_cfg; @@ -3633,7 +3643,7 @@ int32_t lsm6ds3tr_c_tap_detection_on_z_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_tap_cfg_t tap_cfg; @@ -3660,7 +3670,7 @@ int32_t lsm6ds3tr_c_tap_detection_on_y_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_tap_cfg_t tap_cfg; @@ -3681,7 +3691,7 @@ int32_t lsm6ds3tr_c_tap_detection_on_y_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_tap_cfg_t tap_cfg; @@ -3708,7 +3718,7 @@ int32_t lsm6ds3tr_c_tap_detection_on_x_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_tap_cfg_t tap_cfg; @@ -3729,7 +3739,7 @@ int32_t lsm6ds3tr_c_tap_detection_on_x_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_tap_threshold_x_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_tap_ths_6d_t tap_ths_6d; @@ -3756,7 +3766,7 @@ int32_t lsm6ds3tr_c_tap_threshold_x_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_tap_threshold_x_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_tap_ths_6d_t tap_ths_6d; @@ -3782,7 +3792,7 @@ int32_t lsm6ds3tr_c_tap_threshold_x_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6ds3tr_c_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_int_dur2_t int_dur2; int32_t ret; @@ -3813,7 +3823,7 @@ int32_t lsm6ds3tr_c_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6ds3tr_c_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_int_dur2_t int_dur2; int32_t ret; @@ -3838,7 +3848,7 @@ int32_t lsm6ds3tr_c_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6ds3tr_c_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_int_dur2_t int_dur2; int32_t ret; @@ -3869,7 +3879,7 @@ int32_t lsm6ds3tr_c_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6ds3tr_c_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_int_dur2_t int_dur2; int32_t ret; @@ -3895,7 +3905,7 @@ int32_t lsm6ds3tr_c_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6ds3tr_c_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_int_dur2_t int_dur2; int32_t ret; @@ -3927,7 +3937,7 @@ int32_t lsm6ds3tr_c_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6ds3tr_c_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_int_dur2_t int_dur2; int32_t ret; @@ -3948,7 +3958,7 @@ int32_t lsm6ds3tr_c_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_tap_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tap_mode_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_single_double_tap_t val) { lsm6ds3tr_c_wake_up_ths_t wake_up_ths; @@ -3976,7 +3986,7 @@ int32_t lsm6ds3tr_c_tap_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_tap_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tap_mode_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_single_double_tap_t *val) { lsm6ds3tr_c_wake_up_ths_t wake_up_ths; @@ -4025,7 +4035,7 @@ int32_t lsm6ds3tr_c_tap_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_6d_feed_data_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_6d_feed_data_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_low_pass_on_6d_t val) { lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl; @@ -4052,7 +4062,7 @@ int32_t lsm6ds3tr_c_6d_feed_data_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_6d_feed_data_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_6d_feed_data_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_low_pass_on_6d_t *val) { lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl; @@ -4087,7 +4097,7 @@ int32_t lsm6ds3tr_c_6d_feed_data_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_6d_threshold_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_sixd_ths_t val) { lsm6ds3tr_c_tap_ths_6d_t tap_ths_6d; @@ -4114,7 +4124,7 @@ int32_t lsm6ds3tr_c_6d_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_6d_threshold_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_sixd_ths_t *val) { lsm6ds3tr_c_tap_ths_6d_t tap_ths_6d; @@ -4157,7 +4167,7 @@ int32_t lsm6ds3tr_c_6d_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6ds3tr_c_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -4183,7 +4193,7 @@ int32_t lsm6ds3tr_c_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6ds3tr_c_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -4216,7 +4226,7 @@ int32_t lsm6ds3tr_c_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6ds3tr_c_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_wake_up_dur_t wake_up_dur; lsm6ds3tr_c_free_fall_t free_fall; @@ -4256,7 +4266,7 @@ int32_t lsm6ds3tr_c_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6ds3tr_c_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_wake_up_dur_t wake_up_dur; lsm6ds3tr_c_free_fall_t free_fall; @@ -4284,7 +4294,7 @@ int32_t lsm6ds3tr_c_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_ff_threshold_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_ff_ths_t val) { lsm6ds3tr_c_free_fall_t free_fall; @@ -4311,7 +4321,7 @@ int32_t lsm6ds3tr_c_ff_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_ff_threshold_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_ff_ths_t *val) { lsm6ds3tr_c_free_fall_t free_fall; @@ -4383,7 +4393,7 @@ int32_t lsm6ds3tr_c_ff_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_fifo_watermark_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val) { lsm6ds3tr_c_fifo_ctrl1_t fifo_ctrl1; @@ -4418,7 +4428,7 @@ int32_t lsm6ds3tr_c_fifo_watermark_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_fifo_watermark_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6ds3tr_c_fifo_ctrl1_t fifo_ctrl1; @@ -4449,7 +4459,7 @@ int32_t lsm6ds3tr_c_fifo_watermark_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_fifo_data_level_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6ds3tr_c_fifo_status1_t fifo_status1; @@ -4478,7 +4488,7 @@ int32_t lsm6ds3tr_c_fifo_data_level_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6ds3tr_c_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_fifo_status2_t fifo_status2; int32_t ret; @@ -4499,7 +4509,7 @@ int32_t lsm6ds3tr_c_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6ds3tr_c_fifo_pattern_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6ds3tr_c_fifo_status3_t fifo_status3; lsm6ds3tr_c_fifo_status4_t fifo_status4; @@ -4527,7 +4537,7 @@ int32_t lsm6ds3tr_c_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_temp_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2; @@ -4554,7 +4564,7 @@ int32_t lsm6ds3tr_c_fifo_temp_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_temp_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2; @@ -4576,7 +4586,7 @@ int32_t lsm6ds3tr_c_fifo_temp_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_fifo_write_trigger_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_write_trigger_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_trigger_fifo_t val) { lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2; @@ -4618,7 +4628,7 @@ int32_t lsm6ds3tr_c_fifo_write_trigger_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_fifo_write_trigger_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_write_trigger_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_trigger_fifo_t *val) { lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2; @@ -4718,7 +4728,7 @@ int32_t lsm6ds3tr_c_fifo_pedo_and_timestamp_batch_get( * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_xl_batch_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_dec_fifo_xl_t val) { lsm6ds3tr_c_fifo_ctrl3_t fifo_ctrl3; @@ -4746,7 +4756,7 @@ int32_t lsm6ds3tr_c_fifo_xl_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_xl_batch_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_dec_fifo_xl_t *val) { lsm6ds3tr_c_fifo_ctrl3_t fifo_ctrl3; @@ -4806,7 +4816,7 @@ int32_t lsm6ds3tr_c_fifo_xl_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_gy_batch_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_dec_fifo_gyro_t val) { lsm6ds3tr_c_fifo_ctrl3_t fifo_ctrl3; @@ -4834,7 +4844,7 @@ int32_t lsm6ds3tr_c_fifo_gy_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_gy_batch_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_dec_fifo_gyro_t *val) { lsm6ds3tr_c_fifo_ctrl3_t fifo_ctrl3; @@ -4894,7 +4904,7 @@ int32_t lsm6ds3tr_c_fifo_gy_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_dataset_3_batch_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_dec_ds3_fifo_t val) { lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4; @@ -4922,7 +4932,7 @@ int32_t lsm6ds3tr_c_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_dataset_3_batch_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_dec_ds3_fifo_t *val) { lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4; @@ -4982,7 +4992,7 @@ int32_t lsm6ds3tr_c_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_dataset_4_batch_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_dec_ds4_fifo_t val) { lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4; @@ -5010,7 +5020,7 @@ int32_t lsm6ds3tr_c_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_dataset_4_batch_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_dec_ds4_fifo_t *val) { lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4; @@ -5069,7 +5079,7 @@ int32_t lsm6ds3tr_c_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4; @@ -5096,7 +5106,7 @@ int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4; @@ -5118,7 +5128,7 @@ int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4; @@ -5146,7 +5156,7 @@ int32_t lsm6ds3tr_c_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4; @@ -5167,7 +5177,7 @@ int32_t lsm6ds3tr_c_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_fifo_mode_t val) { lsm6ds3tr_c_fifo_ctrl5_t fifo_ctrl5; @@ -5194,7 +5204,7 @@ int32_t lsm6ds3tr_c_fifo_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_fifo_mode_t *val) { lsm6ds3tr_c_fifo_ctrl5_t fifo_ctrl5; @@ -5241,7 +5251,7 @@ int32_t lsm6ds3tr_c_fifo_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_fifo_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_data_rate_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_fifo_t val) { lsm6ds3tr_c_fifo_ctrl5_t fifo_ctrl5; @@ -5268,7 +5278,7 @@ int32_t lsm6ds3tr_c_fifo_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_fifo_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_data_rate_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_fifo_t *val) { lsm6ds3tr_c_fifo_ctrl5_t fifo_ctrl5; @@ -5352,7 +5362,7 @@ int32_t lsm6ds3tr_c_fifo_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_den_polarity_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_den_lh_t val) { lsm6ds3tr_c_ctrl5_c_t ctrl5_c; @@ -5379,7 +5389,7 @@ int32_t lsm6ds3tr_c_den_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_den_polarity_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_den_lh_t *val) { lsm6ds3tr_c_ctrl5_c_t ctrl5_c; @@ -5414,7 +5424,7 @@ int32_t lsm6ds3tr_c_den_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_den_mode_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_den_mode_t val) { lsm6ds3tr_c_ctrl6_c_t ctrl6_c; @@ -5441,7 +5451,7 @@ int32_t lsm6ds3tr_c_den_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_den_mode_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_den_mode_t *val) { lsm6ds3tr_c_ctrl6_c_t ctrl6_c; @@ -5485,7 +5495,7 @@ int32_t lsm6ds3tr_c_den_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_den_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_den_enable_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_den_xl_en_t val) { lsm6ds3tr_c_ctrl4_c_t ctrl4_c; @@ -5527,7 +5537,7 @@ int32_t lsm6ds3tr_c_den_enable_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_den_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_den_enable_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_den_xl_en_t *val) { lsm6ds3tr_c_ctrl4_c_t ctrl4_c; @@ -5573,7 +5583,7 @@ int32_t lsm6ds3tr_c_den_enable_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_den_mark_axis_z_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl; @@ -5600,7 +5610,7 @@ int32_t lsm6ds3tr_c_den_mark_axis_z_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_den_mark_axis_z_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl; @@ -5621,7 +5631,7 @@ int32_t lsm6ds3tr_c_den_mark_axis_z_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_den_mark_axis_y_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl; @@ -5648,7 +5658,7 @@ int32_t lsm6ds3tr_c_den_mark_axis_y_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_den_mark_axis_y_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl; @@ -5669,7 +5679,7 @@ int32_t lsm6ds3tr_c_den_mark_axis_y_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_den_mark_axis_x_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl; @@ -5696,7 +5706,7 @@ int32_t lsm6ds3tr_c_den_mark_axis_x_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_den_mark_axis_x_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl; @@ -5729,7 +5739,7 @@ int32_t lsm6ds3tr_c_den_mark_axis_x_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_pedo_step_reset_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pedo_step_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_ctrl10_c_t ctrl10_c; @@ -5756,7 +5766,7 @@ int32_t lsm6ds3tr_c_pedo_step_reset_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_pedo_step_reset_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pedo_step_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_ctrl10_c_t ctrl10_c; @@ -5777,7 +5787,7 @@ int32_t lsm6ds3tr_c_pedo_step_reset_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6ds3tr_c_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_ctrl10_c_t ctrl10_c; int32_t ret; @@ -5809,7 +5819,7 @@ int32_t lsm6ds3tr_c_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6ds3tr_c_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_ctrl10_c_t ctrl10_c; int32_t ret; @@ -5830,7 +5840,7 @@ int32_t lsm6ds3tr_c_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6ds3tr_c_pedo_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_config_pedo_ths_min_t config_pedo_ths_min; int32_t ret; @@ -5866,7 +5876,7 @@ int32_t lsm6ds3tr_c_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_pedo_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pedo_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_config_pedo_ths_min_t config_pedo_ths_min; @@ -5898,7 +5908,7 @@ int32_t lsm6ds3tr_c_pedo_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_pedo_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pedo_full_scale_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_pedo_fs_t val) { lsm6ds3tr_c_config_pedo_ths_min_t config_pedo_ths_min; @@ -5936,7 +5946,7 @@ int32_t lsm6ds3tr_c_pedo_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_pedo_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pedo_full_scale_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_pedo_fs_t *val) { lsm6ds3tr_c_config_pedo_ths_min_t config_pedo_ths_min; @@ -5981,7 +5991,7 @@ int32_t lsm6ds3tr_c_pedo_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_pedo_debounce_steps_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_pedo_deb_reg_t pedo_deb_reg; @@ -6018,7 +6028,7 @@ int32_t lsm6ds3tr_c_pedo_debounce_steps_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_pedo_debounce_steps_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_pedo_deb_reg_t pedo_deb_reg; @@ -6051,7 +6061,7 @@ int32_t lsm6ds3tr_c_pedo_debounce_steps_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6ds3tr_c_pedo_timeout_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_pedo_deb_reg_t pedo_deb_reg; int32_t ret; @@ -6089,7 +6099,7 @@ int32_t lsm6ds3tr_c_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6ds3tr_c_pedo_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_pedo_deb_reg_t pedo_deb_reg; int32_t ret; @@ -6119,7 +6129,7 @@ int32_t lsm6ds3tr_c_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_pedo_steps_period_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pedo_steps_period_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -6147,7 +6157,7 @@ int32_t lsm6ds3tr_c_pedo_steps_period_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_pedo_steps_period_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pedo_steps_period_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -6188,7 +6198,7 @@ int32_t lsm6ds3tr_c_pedo_steps_period_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6ds3tr_c_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_ctrl10_c_t ctrl10_c; int32_t ret; @@ -6219,7 +6229,7 @@ int32_t lsm6ds3tr_c_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6ds3tr_c_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_ctrl10_c_t ctrl10_c; int32_t ret; @@ -6239,7 +6249,7 @@ int32_t lsm6ds3tr_c_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_motion_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_motion_threshold_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -6267,7 +6277,7 @@ int32_t lsm6ds3tr_c_motion_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_motion_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_motion_threshold_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -6308,7 +6318,7 @@ int32_t lsm6ds3tr_c_motion_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6ds3tr_c_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_ctrl10_c_t ctrl10_c; int32_t ret; @@ -6340,7 +6350,7 @@ int32_t lsm6ds3tr_c_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6ds3tr_c_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_ctrl10_c_t ctrl10_c; int32_t ret; @@ -6360,7 +6370,7 @@ int32_t lsm6ds3tr_c_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_wrist_tilt_sens_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_wrist_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_ctrl10_c_t ctrl10_c; @@ -6393,7 +6403,7 @@ int32_t lsm6ds3tr_c_wrist_tilt_sens_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_wrist_tilt_sens_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_wrist_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_ctrl10_c_t ctrl10_c; @@ -6416,7 +6426,7 @@ int32_t lsm6ds3tr_c_wrist_tilt_sens_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_tilt_latency_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6ds3tr_c_tilt_latency_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -6445,7 +6455,7 @@ int32_t lsm6ds3tr_c_tilt_latency_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_tilt_latency_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6ds3tr_c_tilt_latency_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -6474,7 +6484,7 @@ int32_t lsm6ds3tr_c_tilt_latency_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_tilt_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tilt_threshold_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -6504,7 +6514,7 @@ int32_t lsm6ds3tr_c_tilt_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_tilt_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tilt_threshold_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -6532,7 +6542,7 @@ int32_t lsm6ds3tr_c_tilt_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_tilt_src_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tilt_src_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_a_wrist_tilt_mask_t *val) { int32_t ret; @@ -6561,7 +6571,7 @@ int32_t lsm6ds3tr_c_tilt_src_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_tilt_src_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tilt_src_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_a_wrist_tilt_mask_t *val) { int32_t ret; @@ -6603,7 +6613,7 @@ int32_t lsm6ds3tr_c_tilt_src_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6ds3tr_c_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -6629,7 +6639,7 @@ int32_t lsm6ds3tr_c_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6ds3tr_c_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -6649,7 +6659,7 @@ int32_t lsm6ds3tr_c_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6ds3tr_c_mag_hard_iron_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_master_config_t master_config; lsm6ds3tr_c_ctrl10_c_t ctrl10_c; @@ -6693,7 +6703,7 @@ int32_t lsm6ds3tr_c_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6ds3tr_c_mag_hard_iron_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_master_config_t master_config; int32_t ret; @@ -6714,7 +6724,7 @@ int32_t lsm6ds3tr_c_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_mag_soft_iron_mat_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -6743,7 +6753,7 @@ int32_t lsm6ds3tr_c_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_mag_soft_iron_mat_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_mag_soft_iron_mat_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -6772,7 +6782,7 @@ int32_t lsm6ds3tr_c_mag_soft_iron_mat_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6ds3tr_c_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -6807,7 +6817,7 @@ int32_t lsm6ds3tr_c_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6ds3tr_c_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -6854,7 +6864,7 @@ int32_t lsm6ds3tr_c_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_func_en_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6ds3tr_c_func_en_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_ctrl10_c_t ctrl10_c; int32_t ret; @@ -6881,7 +6891,7 @@ int32_t lsm6ds3tr_c_func_en_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_sync_sens_frame_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_sensor_sync_time_frame_t sensor_sync_time_frame; @@ -6909,7 +6919,7 @@ int32_t lsm6ds3tr_c_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_sync_sens_frame_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_sensor_sync_time_frame_t sensor_sync_time_frame; @@ -6930,7 +6940,7 @@ int32_t lsm6ds3tr_c_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_sync_sens_ratio_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_rr_t val) { lsm6ds3tr_c_sensor_sync_res_ratio_t sensor_sync_res_ratio; @@ -6957,7 +6967,7 @@ int32_t lsm6ds3tr_c_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_sync_sens_ratio_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_rr_t *val) { lsm6ds3tr_c_sensor_sync_res_ratio_t sensor_sync_res_ratio; @@ -7000,7 +7010,7 @@ int32_t lsm6ds3tr_c_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6ds3tr_c_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_master_config_t master_config; int32_t ret; @@ -7026,7 +7036,7 @@ int32_t lsm6ds3tr_c_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6ds3tr_c_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_master_config_t master_config; int32_t ret; @@ -7046,7 +7056,7 @@ int32_t lsm6ds3tr_c_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_pass_through_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_master_config_t master_config; @@ -7073,7 +7083,7 @@ int32_t lsm6ds3tr_c_sh_pass_through_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_pass_through_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_master_config_t master_config; @@ -7094,7 +7104,7 @@ int32_t lsm6ds3tr_c_sh_pass_through_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_pin_mode_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_pull_up_en_t val) { lsm6ds3tr_c_master_config_t master_config; @@ -7121,7 +7131,7 @@ int32_t lsm6ds3tr_c_sh_pin_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_pin_mode_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_pull_up_en_t *val) { lsm6ds3tr_c_master_config_t master_config; @@ -7156,7 +7166,7 @@ int32_t lsm6ds3tr_c_sh_pin_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_syncro_mode_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_start_config_t val) { lsm6ds3tr_c_master_config_t master_config; @@ -7183,7 +7193,7 @@ int32_t lsm6ds3tr_c_sh_syncro_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_syncro_mode_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_start_config_t *val) { lsm6ds3tr_c_master_config_t master_config; @@ -7218,7 +7228,7 @@ int32_t lsm6ds3tr_c_sh_syncro_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_drdy_on_int1_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_drdy_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_master_config_t master_config; @@ -7245,7 +7255,7 @@ int32_t lsm6ds3tr_c_sh_drdy_on_int1_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_drdy_on_int1_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_drdy_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_master_config_t master_config; @@ -7266,7 +7276,7 @@ int32_t lsm6ds3tr_c_sh_drdy_on_int1_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_read_data_raw_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_emb_sh_read_t *val) { int32_t ret; @@ -7292,7 +7302,7 @@ int32_t lsm6ds3tr_c_sh_read_data_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_cmd_sens_sync_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_master_cmd_code_t master_cmd_code; @@ -7320,7 +7330,7 @@ int32_t lsm6ds3tr_c_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_cmd_sens_sync_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_master_cmd_code_t master_cmd_code; @@ -7342,7 +7352,7 @@ int32_t lsm6ds3tr_c_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_spi_sync_error_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_spi_sync_error_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6ds3tr_c_sens_sync_spi_error_code_t sens_sync_spi_error_code; @@ -7370,7 +7380,7 @@ int32_t lsm6ds3tr_c_sh_spi_sync_error_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_spi_sync_error_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_spi_sync_error_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6ds3tr_c_sens_sync_spi_error_code_t sens_sync_spi_error_code; @@ -7391,7 +7401,7 @@ int32_t lsm6ds3tr_c_sh_spi_sync_error_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_num_of_dev_connected_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_aux_sens_on_t val) { lsm6ds3tr_c_slave0_config_t slave0_config; @@ -7428,7 +7438,7 @@ int32_t lsm6ds3tr_c_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_num_of_dev_connected_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_aux_sens_on_t *val) { lsm6ds3tr_c_slave0_config_t slave0_config; @@ -7484,7 +7494,7 @@ int32_t lsm6ds3tr_c_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_cfg_write(const stmdev_ctx_t *ctx, lsm6ds3tr_c_sh_cfg_write_t *val) { lsm6ds3tr_c_slv0_add_t slv0_add; @@ -7532,7 +7542,7 @@ int32_t lsm6ds3tr_c_sh_cfg_write(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_slv0_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, lsm6ds3tr_c_sh_cfg_read_t *val) { lsm6ds3tr_c_slave0_config_t slave0_config; @@ -7587,7 +7597,7 @@ int32_t lsm6ds3tr_c_sh_slv0_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_slv1_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, lsm6ds3tr_c_sh_cfg_read_t *val) { lsm6ds3tr_c_slave1_config_t slave1_config; @@ -7642,7 +7652,7 @@ int32_t lsm6ds3tr_c_sh_slv1_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_slv2_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, lsm6ds3tr_c_sh_cfg_read_t *val) { lsm6ds3tr_c_slv2_add_t slv2_add; @@ -7697,7 +7707,7 @@ int32_t lsm6ds3tr_c_sh_slv2_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_slv3_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, lsm6ds3tr_c_sh_cfg_read_t *val) { lsm6ds3tr_c_slave3_config_t slave3_config; @@ -7750,7 +7760,7 @@ int32_t lsm6ds3tr_c_sh_slv3_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_slave_0_dec_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_slave_0_dec_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_slave0_rate_t val) { lsm6ds3tr_c_slave0_config_t slave0_config; @@ -7788,7 +7798,7 @@ int32_t lsm6ds3tr_c_sh_slave_0_dec_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_slave_0_dec_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_slave_0_dec_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_slave0_rate_t *val) { lsm6ds3tr_c_slave0_config_t slave0_config; @@ -7844,7 +7854,7 @@ int32_t lsm6ds3tr_c_sh_slave_0_dec_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_write_mode_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_write_once_t val) { lsm6ds3tr_c_slave1_config_t slave1_config; @@ -7884,7 +7894,7 @@ int32_t lsm6ds3tr_c_sh_write_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_write_mode_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_write_once_t *val) { lsm6ds3tr_c_slave1_config_t slave1_config; @@ -7930,7 +7940,7 @@ int32_t lsm6ds3tr_c_sh_write_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_slave_1_dec_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_slave_1_dec_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_slave1_rate_t val) { lsm6ds3tr_c_slave1_config_t slave1_config; @@ -7967,7 +7977,7 @@ int32_t lsm6ds3tr_c_sh_slave_1_dec_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_slave_1_dec_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_slave_1_dec_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_slave1_rate_t *val) { lsm6ds3tr_c_slave1_config_t slave1_config; @@ -8021,7 +8031,7 @@ int32_t lsm6ds3tr_c_sh_slave_1_dec_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_slave_2_dec_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_slave_2_dec_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_slave2_rate_t val) { lsm6ds3tr_c_slave2_config_t slave2_config; @@ -8059,7 +8069,7 @@ int32_t lsm6ds3tr_c_sh_slave_2_dec_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_slave_2_dec_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_slave_2_dec_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_slave2_rate_t *val) { lsm6ds3tr_c_slave2_config_t slave2_config; @@ -8113,7 +8123,7 @@ int32_t lsm6ds3tr_c_sh_slave_2_dec_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_slave_3_dec_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_slave_3_dec_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_slave3_rate_t val) { lsm6ds3tr_c_slave3_config_t slave3_config; @@ -8151,7 +8161,7 @@ int32_t lsm6ds3tr_c_sh_slave_3_dec_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6ds3tr_c_sh_slave_3_dec_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_slave_3_dec_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_slave3_rate_t *val) { lsm6ds3tr_c_slave3_config_t slave3_config; diff --git a/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr-c_reg.h b/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr-c_reg.h index f8e71842..3411c790 100644 --- a/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr-c_reg.h +++ b/sensor/stmemsc/lsm6ds3tr-c_STdC/driver/lsm6ds3tr-c_reg.h @@ -185,11 +185,9 @@ typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t not_used_01 : 5; -uint8_t func_cfg_en : - 3; /* func_cfg_en + func_cfg_en_b */ + uint8_t func_cfg_en : 3; /* func_cfg_en + func_cfg_en_b */ #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN -uint8_t func_cfg_en : - 3; /* func_cfg_en + func_cfg_en_b */ + uint8_t func_cfg_en : 3; /* func_cfg_en + func_cfg_en_b */ uint8_t not_used_01 : 5; #endif /* DRV_BYTE_ORDER */ } lsm6ds3tr_c_func_cfg_access_t; @@ -451,11 +449,9 @@ typedef struct uint8_t not_used_01 : 1; uint8_t usr_off_w : 1; uint8_t xl_hm_mode : 1; -uint8_t den_mode : - 3; /* trig_en + lvl_en + lvl2_en */ + uint8_t den_mode : 3; /* trig_en + lvl_en + lvl2_en */ #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN -uint8_t den_mode : - 3; /* trig_en + lvl_en + lvl2_en */ + uint8_t den_mode : 3; /* trig_en + lvl_en + lvl2_en */ uint8_t xl_hm_mode : 1; uint8_t usr_off_w : 1; uint8_t not_used_01 : 1; @@ -992,21 +988,18 @@ typedef struct #define LSM6DS3TR_C_FIFO_STATUS3 0x3CU typedef struct { -uint8_t fifo_pattern : - 8; /* + FIFO_STATUS4(fifo_pattern) */ + uint8_t fifo_pattern : 8; /* + FIFO_STATUS4(fifo_pattern) */ } lsm6ds3tr_c_fifo_status3_t; #define LSM6DS3TR_C_FIFO_STATUS4 0x3DU typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN -uint8_t fifo_pattern : - 2; /* + FIFO_STATUS3(fifo_pattern) */ + uint8_t fifo_pattern : 2; /* + FIFO_STATUS3(fifo_pattern) */ uint8_t not_used_01 : 6; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN uint8_t not_used_01 : 6; -uint8_t fifo_pattern : - 2; /* + FIFO_STATUS3(fifo_pattern) */ + uint8_t fifo_pattern : 2; /* + FIFO_STATUS3(fifo_pattern) */ #endif /* DRV_BYTE_ORDER */ } lsm6ds3tr_c_fifo_status4_t; @@ -1713,10 +1706,10 @@ typedef union * them with a custom implementation. */ -int32_t lsm6ds3tr_c_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm6ds3tr_c_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lsm6ds3tr_c_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm6ds3tr_c_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -1741,9 +1734,9 @@ typedef enum LSM6DS3TR_C_8g = 3, LSM6DS3TR_C_XL_FS_ND = 4, /* ERROR CODE */ } lsm6ds3tr_c_fs_xl_t; -int32_t lsm6ds3tr_c_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_xl_t val); -int32_t lsm6ds3tr_c_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_xl_t *val); typedef enum @@ -1762,9 +1755,9 @@ typedef enum LSM6DS3TR_C_XL_ODR_1Hz6 = 11, LSM6DS3TR_C_XL_ODR_ND = 12, /* ERROR CODE */ } lsm6ds3tr_c_odr_xl_t; -int32_t lsm6ds3tr_c_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_xl_t val); -int32_t lsm6ds3tr_c_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_xl_t *val); typedef enum @@ -1776,9 +1769,9 @@ typedef enum LSM6DS3TR_C_2000dps = 6, LSM6DS3TR_C_GY_FS_ND = 7, /* ERROR CODE */ } lsm6ds3tr_c_fs_g_t; -int32_t lsm6ds3tr_c_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_g_t val); -int32_t lsm6ds3tr_c_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_g_t *val); typedef enum @@ -1796,14 +1789,14 @@ typedef enum LSM6DS3TR_C_GY_ODR_6k66Hz = 10, LSM6DS3TR_C_GY_ODR_ND = 11, /* ERROR CODE */ } lsm6ds3tr_c_odr_g_t; -int32_t lsm6ds3tr_c_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_gy_data_rate_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_g_t val); -int32_t lsm6ds3tr_c_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_g_t *val); -int32_t lsm6ds3tr_c_block_data_update_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -1812,9 +1805,9 @@ typedef enum LSM6DS3TR_C_LSb_16mg = 1, LSM6DS3TR_C_WEIGHT_ND = 2, } lsm6ds3tr_c_usr_off_w_t; -int32_t lsm6ds3tr_c_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_offset_weight_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_usr_off_w_t val); -int32_t lsm6ds3tr_c_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_offset_weight_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_usr_off_w_t *val); typedef enum @@ -1823,9 +1816,9 @@ typedef enum LSM6DS3TR_C_XL_NORMAL = 1, LSM6DS3TR_C_XL_PW_MODE_ND = 2, /* ERROR CODE */ } lsm6ds3tr_c_xl_hm_mode_t; -int32_t lsm6ds3tr_c_xl_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_power_mode_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_xl_hm_mode_t val); -int32_t lsm6ds3tr_c_xl_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_power_mode_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_xl_hm_mode_t *val); typedef enum @@ -1834,9 +1827,9 @@ typedef enum LSM6DS3TR_C_STAT_RND_ENABLE = 1, LSM6DS3TR_C_STAT_RND_ND = 2, /* ERROR CODE */ } lsm6ds3tr_c_rounding_status_t; -int32_t lsm6ds3tr_c_rounding_on_status_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_rounding_on_status_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_rounding_status_t val); -int32_t lsm6ds3tr_c_rounding_on_status_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_rounding_on_status_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_rounding_status_t *val); typedef enum @@ -1845,9 +1838,9 @@ typedef enum LSM6DS3TR_C_GY_NORMAL = 1, LSM6DS3TR_C_GY_PW_MODE_ND = 2, /* ERROR CODE */ } lsm6ds3tr_c_g_hm_mode_t; -int32_t lsm6ds3tr_c_gy_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_gy_power_mode_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_g_hm_mode_t val); -int32_t lsm6ds3tr_c_gy_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_gy_power_mode_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_g_hm_mode_t *val); typedef struct @@ -1861,27 +1854,27 @@ typedef struct lsm6ds3tr_c_wrist_tilt_ia_t wrist_tilt_ia; lsm6ds3tr_c_a_wrist_tilt_mask_t a_wrist_tilt_mask; } lsm6ds3tr_c_all_sources_t; -int32_t lsm6ds3tr_c_all_sources_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_all_sources_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_all_sources_t *val); -int32_t lsm6ds3tr_c_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_status_reg_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_status_reg_t *val); -int32_t lsm6ds3tr_c_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_xl_usr_offset_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6ds3tr_c_xl_usr_offset_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6ds3tr_c_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6ds3tr_c_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -1889,9 +1882,9 @@ typedef enum LSM6DS3TR_C_LSB_25us = 1, LSM6DS3TR_C_TS_RES_ND = 2, /* ERROR CODE */ } lsm6ds3tr_c_timer_hr_t; -int32_t lsm6ds3tr_c_timestamp_res_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_timestamp_res_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_timer_hr_t val); -int32_t lsm6ds3tr_c_timestamp_res_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_timestamp_res_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_timer_hr_t *val); typedef enum @@ -1906,22 +1899,22 @@ typedef enum LSM6DS3TR_C_ROUND_GY_XL_SH1_TO_SH6 = 7, LSM6DS3TR_C_ROUND_OUT_ND = 8, /* ERROR CODE */ } lsm6ds3tr_c_rounding_t; -int32_t lsm6ds3tr_c_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_rounding_mode_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_rounding_t val); -int32_t lsm6ds3tr_c_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_rounding_mode_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_rounding_t *val); -int32_t lsm6ds3tr_c_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6ds3tr_c_angular_rate_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6ds3tr_c_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6ds3tr_c_mag_calibrated_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_mag_calibrated_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6ds3tr_c_fifo_raw_data_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_raw_data_get(const stmdev_ctx_t *ctx, uint8_t *buffer, uint8_t len); @@ -1932,9 +1925,9 @@ typedef enum LSM6DS3TR_C_BANK_B = 5, LSM6DS3TR_C_BANK_ND = 6, /* ERROR CODE */ } lsm6ds3tr_c_func_cfg_en_t; -int32_t lsm6ds3tr_c_mem_bank_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_mem_bank_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_func_cfg_en_t val); -int32_t lsm6ds3tr_c_mem_bank_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_mem_bank_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_func_cfg_en_t *val); typedef enum @@ -1943,14 +1936,14 @@ typedef enum LSM6DS3TR_C_DRDY_PULSED = 1, LSM6DS3TR_C_DRDY_ND = 2, /* ERROR CODE */ } lsm6ds3tr_c_drdy_pulsed_g_t; -int32_t lsm6ds3tr_c_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_drdy_pulsed_g_t val); -int32_t lsm6ds3tr_c_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_drdy_pulsed_g_t *val); -int32_t lsm6ds3tr_c_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6ds3tr_c_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6ds3tr_c_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6ds3tr_c_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -1958,18 +1951,18 @@ typedef enum LSM6DS3TR_C_MSB_AT_LOW_ADD = 1, LSM6DS3TR_C_DATA_FMT_ND = 2, /* ERROR CODE */ } lsm6ds3tr_c_ble_t; -int32_t lsm6ds3tr_c_data_format_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_data_format_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_ble_t val); -int32_t lsm6ds3tr_c_data_format_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_data_format_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_ble_t *val); -int32_t lsm6ds3tr_c_auto_increment_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_auto_increment_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6ds3tr_c_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -1978,9 +1971,9 @@ typedef enum LSM6DS3TR_C_XL_ST_NEGATIVE = 2, LSM6DS3TR_C_XL_ST_ND = 3, /* ERROR CODE */ } lsm6ds3tr_c_st_xl_t; -int32_t lsm6ds3tr_c_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_st_xl_t val); -int32_t lsm6ds3tr_c_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_st_xl_t *val); typedef enum @@ -1990,14 +1983,14 @@ typedef enum LSM6DS3TR_C_GY_ST_NEGATIVE = 3, LSM6DS3TR_C_GY_ST_ND = 4, /* ERROR CODE */ } lsm6ds3tr_c_st_g_t; -int32_t lsm6ds3tr_c_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_st_g_t val); -int32_t lsm6ds3tr_c_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_st_g_t *val); -int32_t lsm6ds3tr_c_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2006,9 +1999,9 @@ typedef enum LSM6DS3TR_C_USE_HPF = 1, LSM6DS3TR_C_HP_PATH_ND = 2, /* ERROR CODE */ } lsm6ds3tr_c_slope_fds_t; -int32_t lsm6ds3tr_c_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_slope_fds_t val); -int32_t lsm6ds3tr_c_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_slope_fds_t *val); typedef enum @@ -2017,9 +2010,9 @@ typedef enum LSM6DS3TR_C_XL_ANA_BW_400Hz = 1, LSM6DS3TR_C_XL_ANA_BW_ND = 2, /* ERROR CODE */ } lsm6ds3tr_c_bw0_xl_t; -int32_t lsm6ds3tr_c_xl_filter_analog_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_filter_analog_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_bw0_xl_t val); -int32_t lsm6ds3tr_c_xl_filter_analog_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_filter_analog_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_bw0_xl_t *val); typedef enum @@ -2028,9 +2021,9 @@ typedef enum LSM6DS3TR_C_XL_LP1_ODR_DIV_4 = 1, LSM6DS3TR_C_XL_LP1_NA = 2, /* ERROR CODE */ } lsm6ds3tr_c_lpf1_bw_sel_t; -int32_t lsm6ds3tr_c_xl_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_lpf1_bw_sel_t val); -int32_t lsm6ds3tr_c_xl_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_lpf1_bw_sel_t *val); typedef enum @@ -2045,14 +2038,14 @@ typedef enum LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_400 = 0x13, LSM6DS3TR_C_XL_LP_NA = 0x20, /* ERROR CODE */ } lsm6ds3tr_c_input_composite_t; -int32_t lsm6ds3tr_c_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_input_composite_t val); -int32_t lsm6ds3tr_c_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_input_composite_t *val); -int32_t lsm6ds3tr_c_xl_reference_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_xl_reference_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2063,9 +2056,9 @@ typedef enum LSM6DS3TR_C_XL_HP_ODR_DIV_400 = 0x03, LSM6DS3TR_C_XL_HP_NA = 0x10, /* ERROR CODE */ } lsm6ds3tr_c_hpcf_xl_t; -int32_t lsm6ds3tr_c_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_hp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_hpcf_xl_t val); -int32_t lsm6ds3tr_c_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_xl_hp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_hpcf_xl_t *val); typedef enum @@ -2089,9 +2082,9 @@ typedef enum LSM6DS3TR_C_HP_GY_BAND_NA = 0xFF, /* ERROR CODE */ } lsm6ds3tr_c_lpf1_sel_g_t; -int32_t lsm6ds3tr_c_gy_band_pass_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_gy_band_pass_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_lpf1_sel_g_t val); -int32_t lsm6ds3tr_c_gy_band_pass_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_gy_band_pass_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_lpf1_sel_g_t *val); typedef enum @@ -2100,9 +2093,9 @@ typedef enum LSM6DS3TR_C_SPI_3_WIRE = 1, LSM6DS3TR_C_SPI_MODE_ND = 2, /* ERROR CODE */ } lsm6ds3tr_c_sim_t; -int32_t lsm6ds3tr_c_spi_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_spi_mode_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_sim_t val); -int32_t lsm6ds3tr_c_spi_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_spi_mode_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_sim_t *val); typedef enum @@ -2111,9 +2104,9 @@ typedef enum LSM6DS3TR_C_I2C_DISABLE = 1, LSM6DS3TR_C_I2C_MODE_ND = 2, /* ERROR CODE */ } lsm6ds3tr_c_i2c_disable_t; -int32_t lsm6ds3tr_c_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_i2c_interface_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_i2c_disable_t val); -int32_t lsm6ds3tr_c_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_i2c_interface_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_i2c_disable_t *val); typedef struct @@ -2137,9 +2130,9 @@ typedef struct uint8_t den_drdy_int1 : 1; uint8_t drdy_on_int1 : 1; } lsm6ds3tr_c_int1_route_t; -int32_t lsm6ds3tr_c_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_int1_route_t val); -int32_t lsm6ds3tr_c_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_int1_route_t *val); typedef struct @@ -2162,9 +2155,9 @@ typedef struct uint8_t int2_inact_state : 1; uint8_t int2_wrist_tilt : 1; } lsm6ds3tr_c_int2_route_t; -int32_t lsm6ds3tr_c_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_int2_route_t val); -int32_t lsm6ds3tr_c_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pin_int2_route_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_int2_route_t *val); typedef enum @@ -2173,9 +2166,9 @@ typedef enum LSM6DS3TR_C_OPEN_DRAIN = 1, LSM6DS3TR_C_PIN_MODE_ND = 2, /* ERROR CODE */ } lsm6ds3tr_c_pp_od_t; -int32_t lsm6ds3tr_c_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pin_mode_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_pp_od_t val); -int32_t lsm6ds3tr_c_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pin_mode_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_pp_od_t *val); typedef enum @@ -2184,13 +2177,13 @@ typedef enum LSM6DS3TR_C_ACTIVE_LOW = 1, LSM6DS3TR_C_POLARITY_ND = 2, /* ERROR CODE */ } lsm6ds3tr_c_h_lactive_t; -int32_t lsm6ds3tr_c_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pin_polarity_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_h_lactive_t val); -int32_t lsm6ds3tr_c_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pin_polarity_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_h_lactive_t *val); -int32_t lsm6ds3tr_c_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6ds3tr_c_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2198,21 +2191,21 @@ typedef enum LSM6DS3TR_C_INT_LATCHED = 1, LSM6DS3TR_C_INT_MODE = 2, /* ERROR CODE */ } lsm6ds3tr_c_lir_t; -int32_t lsm6ds3tr_c_int_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_int_notification_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_lir_t val); -int32_t lsm6ds3tr_c_int_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_int_notification_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_lir_t *val); -int32_t lsm6ds3tr_c_wkup_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_wkup_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6ds3tr_c_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_gy_sleep_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2223,46 +2216,46 @@ typedef enum LSM6DS3TR_C_XL_12Hz5_GY_PD = 3, LSM6DS3TR_C_ACT_MODE_ND = 4, /* ERROR CODE */ } lsm6ds3tr_c_inact_en_t; -int32_t lsm6ds3tr_c_act_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_act_mode_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_inact_en_t val); -int32_t lsm6ds3tr_c_act_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_act_mode_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_inact_en_t *val); -int32_t lsm6ds3tr_c_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_act_sleep_dur_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_tap_src_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tap_src_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_tap_src_t *val); -int32_t lsm6ds3tr_c_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_tap_threshold_x_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_tap_threshold_x_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6ds3tr_c_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6ds3tr_c_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6ds3tr_c_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2270,9 +2263,9 @@ typedef enum LSM6DS3TR_C_BOTH_SINGLE_DOUBLE = 1, LSM6DS3TR_C_TAP_MODE_ND = 2, /* ERROR CODE */ } lsm6ds3tr_c_single_double_tap_t; -int32_t lsm6ds3tr_c_tap_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tap_mode_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_single_double_tap_t val); -int32_t lsm6ds3tr_c_tap_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tap_mode_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_single_double_tap_t *val); typedef enum @@ -2281,9 +2274,9 @@ typedef enum LSM6DS3TR_C_LPF2_FEED = 1, LSM6DS3TR_C_6D_FEED_ND = 2, /* ERROR CODE */ } lsm6ds3tr_c_low_pass_on_6d_t; -int32_t lsm6ds3tr_c_6d_feed_data_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_6d_feed_data_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_low_pass_on_6d_t val); -int32_t lsm6ds3tr_c_6d_feed_data_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_6d_feed_data_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_low_pass_on_6d_t *val); typedef enum @@ -2294,16 +2287,16 @@ typedef enum LSM6DS3TR_C_DEG_50 = 3, LSM6DS3TR_C_6D_TH_ND = 4, /* ERROR CODE */ } lsm6ds3tr_c_sixd_ths_t; -int32_t lsm6ds3tr_c_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_6d_threshold_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_sixd_ths_t val); -int32_t lsm6ds3tr_c_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_6d_threshold_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_sixd_ths_t *val); -int32_t lsm6ds3tr_c_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6ds3tr_c_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6ds3tr_c_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2317,28 +2310,28 @@ typedef enum LSM6DS3TR_C_FF_TSH_500mg = 7, LSM6DS3TR_C_FF_TSH_ND = 8, /* ERROR CODE */ } lsm6ds3tr_c_ff_ths_t; -int32_t lsm6ds3tr_c_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_ff_threshold_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_ff_ths_t val); -int32_t lsm6ds3tr_c_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_ff_threshold_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_ff_ths_t *val); -int32_t lsm6ds3tr_c_fifo_watermark_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6ds3tr_c_fifo_watermark_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6ds3tr_c_fifo_data_level_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6ds3tr_c_fifo_wtm_flag_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_fifo_pattern_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_pattern_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6ds3tr_c_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_temp_batch_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_temp_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2348,9 +2341,9 @@ typedef enum LSM6DS3TR_C_TRG_SH_DRDY = 2, LSM6DS3TR_C_TRG_SH_ND = 3, /* ERROR CODE */ } lsm6ds3tr_c_trigger_fifo_t; -int32_t lsm6ds3tr_c_fifo_write_trigger_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_write_trigger_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_trigger_fifo_t val); -int32_t lsm6ds3tr_c_fifo_write_trigger_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_write_trigger_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_trigger_fifo_t *val); int32_t lsm6ds3tr_c_fifo_pedo_and_timestamp_batch_set( @@ -2372,9 +2365,9 @@ typedef enum LSM6DS3TR_C_FIFO_XL_DEC_32 = 7, LSM6DS3TR_C_FIFO_XL_DEC_ND = 8, /* ERROR CODE */ } lsm6ds3tr_c_dec_fifo_xl_t; -int32_t lsm6ds3tr_c_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_xl_batch_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_dec_fifo_xl_t val); -int32_t lsm6ds3tr_c_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_xl_batch_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_dec_fifo_xl_t *val); typedef enum @@ -2389,9 +2382,9 @@ typedef enum LSM6DS3TR_C_FIFO_GY_DEC_32 = 7, LSM6DS3TR_C_FIFO_GY_DEC_ND = 8, /* ERROR CODE */ } lsm6ds3tr_c_dec_fifo_gyro_t; -int32_t lsm6ds3tr_c_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_gy_batch_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_dec_fifo_gyro_t val); -int32_t lsm6ds3tr_c_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_gy_batch_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_dec_fifo_gyro_t *val); typedef enum @@ -2406,9 +2399,9 @@ typedef enum LSM6DS3TR_C_FIFO_DS3_DEC_32 = 7, LSM6DS3TR_C_FIFO_DS3_DEC_ND = 8, /* ERROR CODE */ } lsm6ds3tr_c_dec_ds3_fifo_t; -int32_t lsm6ds3tr_c_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_dataset_3_batch_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_dec_ds3_fifo_t val); -int32_t lsm6ds3tr_c_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_dataset_3_batch_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_dec_ds3_fifo_t *val); typedef enum @@ -2423,19 +2416,19 @@ typedef enum LSM6DS3TR_C_FIFO_DS4_DEC_32 = 7, LSM6DS3TR_C_FIFO_DS4_DEC_ND = 8, /* ERROR CODE */ } lsm6ds3tr_c_dec_ds4_fifo_t; -int32_t lsm6ds3tr_c_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_dataset_4_batch_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_dec_ds4_fifo_t val); -int32_t lsm6ds3tr_c_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_dataset_4_batch_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_dec_ds4_fifo_t *val); -int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2447,9 +2440,9 @@ typedef enum LSM6DS3TR_C_STREAM_MODE = 6, LSM6DS3TR_C_FIFO_MODE_ND = 8, /* ERROR CODE */ } lsm6ds3tr_c_fifo_mode_t; -int32_t lsm6ds3tr_c_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_fifo_mode_t val); -int32_t lsm6ds3tr_c_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_fifo_mode_t *val); typedef enum @@ -2467,9 +2460,9 @@ typedef enum LSM6DS3TR_C_FIFO_6k66Hz = 10, LSM6DS3TR_C_FIFO_RATE_ND = 11, /* ERROR CODE */ } lsm6ds3tr_c_odr_fifo_t; -int32_t lsm6ds3tr_c_fifo_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_data_rate_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_fifo_t val); -int32_t lsm6ds3tr_c_fifo_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_fifo_data_rate_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_fifo_t *val); typedef enum @@ -2478,9 +2471,9 @@ typedef enum LSM6DS3TR_C_DEN_ACT_HIGH = 1, LSM6DS3TR_C_DEN_POL_ND = 2, /* ERROR CODE */ } lsm6ds3tr_c_den_lh_t; -int32_t lsm6ds3tr_c_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_den_polarity_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_den_lh_t val); -int32_t lsm6ds3tr_c_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_den_polarity_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_den_lh_t *val); typedef enum @@ -2492,9 +2485,9 @@ typedef enum LSM6DS3TR_C_EDGE_TRIGGER = 4, LSM6DS3TR_C_DEN_MODE_ND = 5, /* ERROR CODE */ } lsm6ds3tr_c_den_mode_t; -int32_t lsm6ds3tr_c_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_den_mode_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_den_mode_t val); -int32_t lsm6ds3tr_c_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_den_mode_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_den_mode_t *val); typedef enum @@ -2504,37 +2497,37 @@ typedef enum LSM6DS3TR_C_STAMP_IN_GY_XL_DATA = 2, LSM6DS3TR_C_DEN_STAMP_ND = 3, /* ERROR CODE */ } lsm6ds3tr_c_den_xl_en_t; -int32_t lsm6ds3tr_c_den_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_den_enable_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_den_xl_en_t val); -int32_t lsm6ds3tr_c_den_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_den_enable_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_den_xl_en_t *val); -int32_t lsm6ds3tr_c_den_mark_axis_z_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_den_mark_axis_z_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_den_mark_axis_y_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_den_mark_axis_y_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_den_mark_axis_x_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_den_mark_axis_x_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_pedo_step_reset_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pedo_step_reset_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_pedo_step_reset_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pedo_step_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6ds3tr_c_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_pedo_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pedo_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_pedo_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pedo_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2543,76 +2536,76 @@ typedef enum LSM6DS3TR_C_PEDO_AT_4g = 1, LSM6DS3TR_C_PEDO_FS_ND = 2, /* ERROR CODE */ } lsm6ds3tr_c_pedo_fs_t; -int32_t lsm6ds3tr_c_pedo_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pedo_full_scale_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_pedo_fs_t val); -int32_t lsm6ds3tr_c_pedo_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pedo_full_scale_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_pedo_fs_t *val); -int32_t lsm6ds3tr_c_pedo_debounce_steps_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_pedo_debounce_steps_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6ds3tr_c_pedo_timeout_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_pedo_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_pedo_steps_period_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pedo_steps_period_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6ds3tr_c_pedo_steps_period_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_pedo_steps_period_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6ds3tr_c_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6ds3tr_c_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_motion_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_motion_threshold_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6ds3tr_c_motion_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_motion_threshold_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6ds3tr_c_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6ds3tr_c_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_wrist_tilt_sens_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_wrist_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_wrist_tilt_sens_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_wrist_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_tilt_latency_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tilt_latency_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6ds3tr_c_tilt_latency_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tilt_latency_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6ds3tr_c_tilt_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tilt_threshold_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6ds3tr_c_tilt_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tilt_threshold_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6ds3tr_c_tilt_src_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tilt_src_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_a_wrist_tilt_mask_t *val); -int32_t lsm6ds3tr_c_tilt_src_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_tilt_src_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_a_wrist_tilt_mask_t *val); -int32_t lsm6ds3tr_c_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_mag_soft_iron_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_mag_hard_iron_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_mag_hard_iron_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_mag_hard_iron_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_mag_soft_iron_mat_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6ds3tr_c_mag_soft_iron_mat_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_mag_soft_iron_mat_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6ds3tr_c_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6ds3tr_c_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6ds3tr_c_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6ds3tr_c_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6ds3tr_c_func_en_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_func_en_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_sync_sens_frame_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_sync_sens_frame_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2623,17 +2616,17 @@ typedef enum LSM6DS3TR_C_RES_RATIO_2_14 = 3, LSM6DS3TR_C_RES_RATIO_ND = 4, /* ERROR CODE */ } lsm6ds3tr_c_rr_t; -int32_t lsm6ds3tr_c_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_sync_sens_ratio_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_rr_t val); -int32_t lsm6ds3tr_c_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_sync_sens_ratio_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_rr_t *val); -int32_t lsm6ds3tr_c_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6ds3tr_c_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_sh_pass_through_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_sh_pass_through_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2642,9 +2635,9 @@ typedef enum LSM6DS3TR_C_INTERNAL_PULL_UP = 1, LSM6DS3TR_C_SH_PIN_MODE = 2, /* ERROR CODE */ } lsm6ds3tr_c_pull_up_en_t; -int32_t lsm6ds3tr_c_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_pin_mode_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_pull_up_en_t val); -int32_t lsm6ds3tr_c_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_pin_mode_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_pull_up_en_t *val); typedef enum @@ -2653,14 +2646,14 @@ typedef enum LSM6DS3TR_C_EXT_ON_INT2_PIN = 1, LSM6DS3TR_C_SH_SYNCRO_ND = 2, /* ERROR CODE */ } lsm6ds3tr_c_start_config_t; -int32_t lsm6ds3tr_c_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_syncro_mode_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_start_config_t val); -int32_t lsm6ds3tr_c_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_syncro_mode_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_start_config_t *val); -int32_t lsm6ds3tr_c_sh_drdy_on_int1_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_drdy_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_sh_drdy_on_int1_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_drdy_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct @@ -2684,17 +2677,17 @@ typedef struct lsm6ds3tr_c_sensorhub17_reg_t sh_byte_17; lsm6ds3tr_c_sensorhub18_reg_t sh_byte_18; } lsm6ds3tr_c_emb_sh_read_t; -int32_t lsm6ds3tr_c_sh_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_read_data_raw_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_emb_sh_read_t *val); -int32_t lsm6ds3tr_c_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_cmd_sens_sync_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_cmd_sens_sync_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6ds3tr_c_sh_spi_sync_error_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_spi_sync_error_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6ds3tr_c_sh_spi_sync_error_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_spi_sync_error_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2705,9 +2698,9 @@ typedef enum LSM6DS3TR_C_SLV_0_1_2_3 = 3, LSM6DS3TR_C_SLV_EN_ND = 4, /* ERROR CODE */ } lsm6ds3tr_c_aux_sens_on_t; -int32_t lsm6ds3tr_c_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_num_of_dev_connected_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_aux_sens_on_t val); -int32_t lsm6ds3tr_c_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_num_of_dev_connected_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_aux_sens_on_t *val); typedef struct @@ -2716,7 +2709,7 @@ typedef struct uint8_t slv0_subadd; uint8_t slv0_data; } lsm6ds3tr_c_sh_cfg_write_t; -int32_t lsm6ds3tr_c_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_cfg_write(const stmdev_ctx_t *ctx, lsm6ds3tr_c_sh_cfg_write_t *val); typedef struct @@ -2725,13 +2718,13 @@ typedef struct uint8_t slv_subadd; uint8_t slv_len; } lsm6ds3tr_c_sh_cfg_read_t; -int32_t lsm6ds3tr_c_sh_slv0_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, lsm6ds3tr_c_sh_cfg_read_t *val); -int32_t lsm6ds3tr_c_sh_slv1_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, lsm6ds3tr_c_sh_cfg_read_t *val); -int32_t lsm6ds3tr_c_sh_slv2_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, lsm6ds3tr_c_sh_cfg_read_t *val); -int32_t lsm6ds3tr_c_sh_slv3_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, lsm6ds3tr_c_sh_cfg_read_t *val); typedef enum @@ -2742,9 +2735,9 @@ typedef enum LSM6DS3TR_C_SL0_DEC_8 = 3, LSM6DS3TR_C_SL0_DEC_ND = 4, /* ERROR CODE */ } lsm6ds3tr_c_slave0_rate_t; -int32_t lsm6ds3tr_c_sh_slave_0_dec_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_slave_0_dec_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_slave0_rate_t val); -int32_t lsm6ds3tr_c_sh_slave_0_dec_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_slave_0_dec_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_slave0_rate_t *val); typedef enum @@ -2753,9 +2746,9 @@ typedef enum LSM6DS3TR_C_ONLY_FIRST_CYCLE = 1, LSM6DS3TR_C_SH_WR_MODE_ND = 2, /* ERROR CODE */ } lsm6ds3tr_c_write_once_t; -int32_t lsm6ds3tr_c_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_write_mode_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_write_once_t val); -int32_t lsm6ds3tr_c_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_write_mode_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_write_once_t *val); typedef enum @@ -2766,9 +2759,9 @@ typedef enum LSM6DS3TR_C_SL1_DEC_8 = 3, LSM6DS3TR_C_SL1_DEC_ND = 4, /* ERROR CODE */ } lsm6ds3tr_c_slave1_rate_t; -int32_t lsm6ds3tr_c_sh_slave_1_dec_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_slave_1_dec_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_slave1_rate_t val); -int32_t lsm6ds3tr_c_sh_slave_1_dec_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_slave_1_dec_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_slave1_rate_t *val); typedef enum @@ -2779,9 +2772,9 @@ typedef enum LSM6DS3TR_C_SL2_DEC_8 = 3, LSM6DS3TR_C_SL2_DEC_ND = 4, /* ERROR CODE */ } lsm6ds3tr_c_slave2_rate_t; -int32_t lsm6ds3tr_c_sh_slave_2_dec_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_slave_2_dec_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_slave2_rate_t val); -int32_t lsm6ds3tr_c_sh_slave_2_dec_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_slave_2_dec_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_slave2_rate_t *val); typedef enum @@ -2792,9 +2785,9 @@ typedef enum LSM6DS3TR_C_SL3_DEC_8 = 3, LSM6DS3TR_C_SL3_DEC_ND = 4, /* ERROR CODE */ } lsm6ds3tr_c_slave3_rate_t; -int32_t lsm6ds3tr_c_sh_slave_3_dec_set(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_slave_3_dec_set(const stmdev_ctx_t *ctx, lsm6ds3tr_c_slave3_rate_t val); -int32_t lsm6ds3tr_c_sh_slave_3_dec_get(stmdev_ctx_t *ctx, +int32_t lsm6ds3tr_c_sh_slave_3_dec_get(const stmdev_ctx_t *ctx, lsm6ds3tr_c_slave3_rate_t *val); /** diff --git a/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.c b/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.c index f44360d4..8192aff7 100644 --- a/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.c +++ b/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm6dsl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm6dsl_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lsm6dsl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm6dsl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm6dsl_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -162,7 +172,7 @@ float_t lsm6dsl_from_lsb_to_celsius(int16_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsl_fs_xl_t val) { lsm6dsl_ctrl1_xl_t ctrl1_xl; @@ -187,7 +197,7 @@ int32_t lsm6dsl_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsl_fs_xl_t *val) { lsm6dsl_ctrl1_xl_t ctrl1_xl; @@ -229,7 +239,7 @@ int32_t lsm6dsl_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsl_odr_xl_t val) { lsm6dsl_ctrl1_xl_t ctrl1_xl; @@ -254,7 +264,7 @@ int32_t lsm6dsl_xl_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsl_odr_xl_t *val) { lsm6dsl_ctrl1_xl_t ctrl1_xl; @@ -328,7 +338,7 @@ int32_t lsm6dsl_xl_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsl_fs_g_t val) { lsm6dsl_ctrl2_g_t ctrl2_g; @@ -353,7 +363,7 @@ int32_t lsm6dsl_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsl_fs_g_t *val) { lsm6dsl_ctrl2_g_t ctrl2_g; @@ -399,7 +409,7 @@ int32_t lsm6dsl_gy_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_gy_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsl_odr_g_t val) { lsm6dsl_ctrl2_g_t ctrl2_g; @@ -424,7 +434,7 @@ int32_t lsm6dsl_gy_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsl_odr_g_t *val) { lsm6dsl_ctrl2_g_t ctrl2_g; @@ -494,7 +504,7 @@ int32_t lsm6dsl_gy_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_ctrl3_c_t ctrl3_c; int32_t ret; @@ -518,7 +528,7 @@ int32_t lsm6dsl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_ctrl3_c_t ctrl3_c; int32_t ret; @@ -538,7 +548,7 @@ int32_t lsm6dsl_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_offset_weight_set(const stmdev_ctx_t *ctx, lsm6dsl_usr_off_w_t val) { lsm6dsl_ctrl6_c_t ctrl6_c; @@ -564,7 +574,7 @@ int32_t lsm6dsl_xl_offset_weight_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_offset_weight_get(const stmdev_ctx_t *ctx, lsm6dsl_usr_off_w_t *val) { lsm6dsl_ctrl6_c_t ctrl6_c; @@ -598,7 +608,7 @@ int32_t lsm6dsl_xl_offset_weight_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_xl_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_power_mode_set(const stmdev_ctx_t *ctx, lsm6dsl_xl_hm_mode_t val) { lsm6dsl_ctrl6_c_t ctrl6_c; @@ -623,7 +633,7 @@ int32_t lsm6dsl_xl_power_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_xl_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_power_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_xl_hm_mode_t *val) { lsm6dsl_ctrl6_c_t ctrl6_c; @@ -659,7 +669,7 @@ int32_t lsm6dsl_xl_power_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_rounding_on_status_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_rounding_on_status_set(const stmdev_ctx_t *ctx, lsm6dsl_rounding_status_t val) { lsm6dsl_ctrl7_g_t ctrl7_g; @@ -686,7 +696,7 @@ int32_t lsm6dsl_rounding_on_status_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_rounding_on_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_rounding_on_status_get(const stmdev_ctx_t *ctx, lsm6dsl_rounding_status_t *val) { lsm6dsl_ctrl7_g_t ctrl7_g; @@ -720,7 +730,7 @@ int32_t lsm6dsl_rounding_on_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_gy_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_gy_power_mode_set(const stmdev_ctx_t *ctx, lsm6dsl_g_hm_mode_t val) { lsm6dsl_ctrl7_g_t ctrl7_g; @@ -745,7 +755,7 @@ int32_t lsm6dsl_gy_power_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_gy_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_gy_power_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_g_hm_mode_t *val) { lsm6dsl_ctrl7_g_t ctrl7_g; @@ -780,7 +790,7 @@ int32_t lsm6dsl_gy_power_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_all_sources_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_all_sources_get(const stmdev_ctx_t *ctx, lsm6dsl_all_sources_t *val) { int32_t ret; @@ -850,7 +860,7 @@ int32_t lsm6dsl_all_sources_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_status_reg_get(const stmdev_ctx_t *ctx, lsm6dsl_status_reg_t *val) { int32_t ret; @@ -868,7 +878,7 @@ int32_t lsm6dsl_status_reg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_status_reg_t status_reg; @@ -889,7 +899,7 @@ int32_t lsm6dsl_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_status_reg_t status_reg; @@ -910,7 +920,7 @@ int32_t lsm6dsl_gy_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_status_reg_t status_reg; @@ -933,7 +943,7 @@ int32_t lsm6dsl_temp_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsl_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -952,7 +962,7 @@ int32_t lsm6dsl_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsl_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -983,7 +993,7 @@ int32_t lsm6dsl_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_ctrl10_c_t ctrl10_c; int32_t ret; @@ -1013,7 +1023,7 @@ int32_t lsm6dsl_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_ctrl10_c_t ctrl10_c; int32_t ret; @@ -1037,7 +1047,7 @@ int32_t lsm6dsl_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_timestamp_res_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_timestamp_res_set(const stmdev_ctx_t *ctx, lsm6dsl_timer_hr_t val) { lsm6dsl_wake_up_dur_t wake_up_dur; @@ -1069,7 +1079,7 @@ int32_t lsm6dsl_timestamp_res_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_timestamp_res_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_timestamp_res_get(const stmdev_ctx_t *ctx, lsm6dsl_timer_hr_t *val) { lsm6dsl_wake_up_dur_t wake_up_dur; @@ -1117,7 +1127,7 @@ int32_t lsm6dsl_timestamp_res_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_rounding_mode_set(const stmdev_ctx_t *ctx, lsm6dsl_rounding_t val) { lsm6dsl_ctrl5_c_t ctrl5_c; @@ -1143,7 +1153,7 @@ int32_t lsm6dsl_rounding_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_rounding_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_rounding_t *val) { lsm6dsl_ctrl5_c_t ctrl5_c; @@ -1202,7 +1212,7 @@ int32_t lsm6dsl_rounding_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsl_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1223,7 +1233,7 @@ int32_t lsm6dsl_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsl_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1248,7 +1258,7 @@ int32_t lsm6dsl_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsl_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1272,7 +1282,7 @@ int32_t lsm6dsl_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_mag_calibrated_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_mag_calibrated_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -1298,7 +1308,7 @@ int32_t lsm6dsl_mag_calibrated_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer, +int32_t lsm6dsl_fifo_raw_data_get(const stmdev_ctx_t *ctx, uint8_t *buffer, uint8_t len) { int32_t ret; @@ -1329,7 +1339,7 @@ int32_t lsm6dsl_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_mem_bank_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dsl_func_cfg_en_t val) { lsm6dsl_func_cfg_access_t func_cfg_access; @@ -1357,7 +1367,7 @@ int32_t lsm6dsl_mem_bank_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_mem_bank_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dsl_func_cfg_en_t *val) { lsm6dsl_func_cfg_access_t func_cfg_access; @@ -1392,7 +1402,7 @@ int32_t lsm6dsl_mem_bank_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm6dsl_drdy_pulsed_g_t val) { lsm6dsl_drdy_pulse_cfg_g_t drdy_pulse_cfg_g; @@ -1419,7 +1429,7 @@ int32_t lsm6dsl_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_drdy_pulsed_g_t *val) { lsm6dsl_drdy_pulse_cfg_g_t drdy_pulse_cfg_g; @@ -1454,7 +1464,7 @@ int32_t lsm6dsl_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1471,7 +1481,7 @@ int32_t lsm6dsl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1495,7 +1505,7 @@ int32_t lsm6dsl_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1514,7 +1524,7 @@ int32_t lsm6dsl_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_data_format_set(stmdev_ctx_t *ctx, lsm6dsl_ble_t val) +int32_t lsm6dsl_data_format_set(const stmdev_ctx_t *ctx, lsm6dsl_ble_t val) { lsm6dsl_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1538,7 +1548,7 @@ int32_t lsm6dsl_data_format_set(stmdev_ctx_t *ctx, lsm6dsl_ble_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_data_format_get(stmdev_ctx_t *ctx, lsm6dsl_ble_t *val) +int32_t lsm6dsl_data_format_get(const stmdev_ctx_t *ctx, lsm6dsl_ble_t *val) { lsm6dsl_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1572,7 +1582,7 @@ int32_t lsm6dsl_data_format_get(stmdev_ctx_t *ctx, lsm6dsl_ble_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1597,7 +1607,7 @@ int32_t lsm6dsl_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1616,7 +1626,7 @@ int32_t lsm6dsl_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1640,7 +1650,7 @@ int32_t lsm6dsl_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1659,7 +1669,7 @@ int32_t lsm6dsl_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dsl_st_xl_t val) { lsm6dsl_ctrl5_c_t ctrl5_c; @@ -1684,7 +1694,7 @@ int32_t lsm6dsl_xl_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dsl_st_xl_t *val) { lsm6dsl_ctrl5_c_t ctrl5_c; @@ -1722,7 +1732,7 @@ int32_t lsm6dsl_xl_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dsl_st_g_t val) { lsm6dsl_ctrl5_c_t ctrl5_c; @@ -1747,7 +1757,7 @@ int32_t lsm6dsl_gy_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dsl_st_g_t *val) { lsm6dsl_ctrl5_c_t ctrl5_c; @@ -1799,7 +1809,7 @@ int32_t lsm6dsl_gy_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_ctrl4_c_t ctrl4_c; @@ -1825,7 +1835,7 @@ int32_t lsm6dsl_filter_settling_mask_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_ctrl4_c_t ctrl4_c; @@ -1846,7 +1856,7 @@ int32_t lsm6dsl_filter_settling_mask_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dsl_slope_fds_t val) { lsm6dsl_tap_cfg_t tap_cfg; @@ -1872,7 +1882,7 @@ int32_t lsm6dsl_xl_hp_path_internal_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dsl_slope_fds_t *val) { lsm6dsl_tap_cfg_t tap_cfg; @@ -1920,7 +1930,7 @@ int32_t lsm6dsl_xl_hp_path_internal_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_xl_filter_analog_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_filter_analog_set(const stmdev_ctx_t *ctx, lsm6dsl_bw0_xl_t val) { lsm6dsl_ctrl1_xl_t ctrl1_xl; @@ -1946,7 +1956,7 @@ int32_t lsm6dsl_xl_filter_analog_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_xl_filter_analog_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_filter_analog_get(const stmdev_ctx_t *ctx, lsm6dsl_bw0_xl_t *val) { lsm6dsl_ctrl1_xl_t ctrl1_xl; @@ -1994,7 +2004,7 @@ int32_t lsm6dsl_xl_filter_analog_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_xl_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsl_lpf1_bw_sel_t val) { lsm6dsl_ctrl1_xl_t ctrl1_xl; @@ -2033,7 +2043,7 @@ int32_t lsm6dsl_xl_lp1_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_xl_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsl_lpf1_bw_sel_t *val) { lsm6dsl_ctrl1_xl_t ctrl1_xl; @@ -2082,7 +2092,7 @@ int32_t lsm6dsl_xl_lp1_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsl_input_composite_t val) { lsm6dsl_ctrl8_xl_t ctrl8_xl; @@ -2110,7 +2120,7 @@ int32_t lsm6dsl_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsl_input_composite_t *val) { lsm6dsl_ctrl8_xl_t ctrl8_xl; @@ -2180,7 +2190,7 @@ int32_t lsm6dsl_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_xl_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_xl_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -2204,7 +2214,7 @@ int32_t lsm6dsl_xl_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_xl_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_xl_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -2223,7 +2233,7 @@ int32_t lsm6dsl_xl_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_hp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsl_hpcf_xl_t val) { lsm6dsl_ctrl8_xl_t ctrl8_xl; @@ -2250,7 +2260,7 @@ int32_t lsm6dsl_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_hp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsl_hpcf_xl_t *val) { lsm6dsl_ctrl8_xl_t ctrl8_xl; @@ -2310,7 +2320,7 @@ int32_t lsm6dsl_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_gy_band_pass_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_gy_band_pass_set(const stmdev_ctx_t *ctx, lsm6dsl_lpf1_sel_g_t val) { lsm6dsl_ctrl4_c_t ctrl4_c; @@ -2362,7 +2372,7 @@ int32_t lsm6dsl_gy_band_pass_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_gy_band_pass_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_gy_band_pass_get(const stmdev_ctx_t *ctx, lsm6dsl_lpf1_sel_g_t *val) { lsm6dsl_ctrl4_c_t ctrl4_c; @@ -2462,7 +2472,7 @@ int32_t lsm6dsl_gy_band_pass_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsl_sim_t val) +int32_t lsm6dsl_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsl_sim_t val) { lsm6dsl_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2486,7 +2496,7 @@ int32_t lsm6dsl_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsl_sim_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsl_sim_t *val) +int32_t lsm6dsl_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_sim_t *val) { lsm6dsl_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2519,7 +2529,7 @@ int32_t lsm6dsl_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsl_sim_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_i2c_interface_set(const stmdev_ctx_t *ctx, lsm6dsl_i2c_disable_t val) { lsm6dsl_ctrl4_c_t ctrl4_c; @@ -2544,7 +2554,7 @@ int32_t lsm6dsl_i2c_interface_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_i2c_interface_get(const stmdev_ctx_t *ctx, lsm6dsl_i2c_disable_t *val) { lsm6dsl_ctrl4_c_t ctrl4_c; @@ -2592,7 +2602,7 @@ int32_t lsm6dsl_i2c_interface_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm6dsl_int1_route_t val) { lsm6dsl_master_config_t master_config; @@ -2708,7 +2718,7 @@ int32_t lsm6dsl_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm6dsl_int1_route_t *val) { lsm6dsl_master_config_t master_config; @@ -2764,7 +2774,7 @@ int32_t lsm6dsl_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm6dsl_int2_route_t val) { lsm6dsl_int2_ctrl_t int2_ctrl; @@ -2867,7 +2877,7 @@ int32_t lsm6dsl_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_pin_int2_route_get(const stmdev_ctx_t *ctx, lsm6dsl_int2_route_t *val) { lsm6dsl_int2_ctrl_t int2_ctrl; @@ -2916,7 +2926,7 @@ int32_t lsm6dsl_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsl_pp_od_t val) +int32_t lsm6dsl_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dsl_pp_od_t val) { lsm6dsl_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2940,7 +2950,7 @@ int32_t lsm6dsl_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsl_pp_od_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsl_pp_od_t *val) +int32_t lsm6dsl_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_pp_od_t *val) { lsm6dsl_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2973,7 +2983,7 @@ int32_t lsm6dsl_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsl_pp_od_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_pin_polarity_set(const stmdev_ctx_t *ctx, lsm6dsl_h_lactive_t val) { lsm6dsl_ctrl3_c_t ctrl3_c; @@ -2998,7 +3008,7 @@ int32_t lsm6dsl_pin_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_pin_polarity_get(const stmdev_ctx_t *ctx, lsm6dsl_h_lactive_t *val) { lsm6dsl_ctrl3_c_t ctrl3_c; @@ -3032,7 +3042,7 @@ int32_t lsm6dsl_pin_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_ctrl4_c_t ctrl4_c; int32_t ret; @@ -3056,7 +3066,7 @@ int32_t lsm6dsl_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_ctrl4_c_t ctrl4_c; int32_t ret; @@ -3075,7 +3085,7 @@ int32_t lsm6dsl_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_int_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_int_notification_set(const stmdev_ctx_t *ctx, lsm6dsl_lir_t val) { lsm6dsl_tap_cfg_t tap_cfg; @@ -3100,7 +3110,7 @@ int32_t lsm6dsl_int_notification_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_int_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_int_notification_get(const stmdev_ctx_t *ctx, lsm6dsl_lir_t *val) { lsm6dsl_tap_cfg_t tap_cfg; @@ -3147,7 +3157,7 @@ int32_t lsm6dsl_int_notification_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_wake_up_ths_t wake_up_ths; int32_t ret; @@ -3173,7 +3183,7 @@ int32_t lsm6dsl_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_wake_up_ths_t wake_up_ths; int32_t ret; @@ -3193,7 +3203,7 @@ int32_t lsm6dsl_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_wake_up_dur_t wake_up_dur; int32_t ret; @@ -3219,7 +3229,7 @@ int32_t lsm6dsl_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_wake_up_dur_t wake_up_dur; int32_t ret; @@ -3252,7 +3262,7 @@ int32_t lsm6dsl_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_ctrl4_c_t ctrl4_c; int32_t ret; @@ -3276,7 +3286,7 @@ int32_t lsm6dsl_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_ctrl4_c_t ctrl4_c; int32_t ret; @@ -3295,7 +3305,7 @@ int32_t lsm6dsl_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_act_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_act_mode_set(const stmdev_ctx_t *ctx, lsm6dsl_inact_en_t val) { lsm6dsl_tap_cfg_t tap_cfg; @@ -3320,7 +3330,7 @@ int32_t lsm6dsl_act_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_act_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_act_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_inact_en_t *val) { lsm6dsl_tap_cfg_t tap_cfg; @@ -3362,7 +3372,7 @@ int32_t lsm6dsl_act_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_wake_up_dur_t wake_up_dur; int32_t ret; @@ -3388,7 +3398,7 @@ int32_t lsm6dsl_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_wake_up_dur_t wake_up_dur; int32_t ret; @@ -3421,7 +3431,7 @@ int32_t lsm6dsl_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_tap_src_get(stmdev_ctx_t *ctx, lsm6dsl_tap_src_t *val) +int32_t lsm6dsl_tap_src_get(const stmdev_ctx_t *ctx, lsm6dsl_tap_src_t *val) { int32_t ret; @@ -3437,7 +3447,7 @@ int32_t lsm6dsl_tap_src_get(stmdev_ctx_t *ctx, lsm6dsl_tap_src_t *val) * @param val Change the values of tap_z_en in reg TAP_CFG * */ -int32_t lsm6dsl_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_tap_cfg_t tap_cfg; int32_t ret; @@ -3461,7 +3471,7 @@ int32_t lsm6dsl_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_tap_cfg_t tap_cfg; @@ -3481,7 +3491,7 @@ int32_t lsm6dsl_tap_detection_on_z_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_tap_cfg_t tap_cfg; int32_t ret; @@ -3505,7 +3515,7 @@ int32_t lsm6dsl_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_tap_cfg_t tap_cfg; @@ -3525,7 +3535,7 @@ int32_t lsm6dsl_tap_detection_on_y_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_tap_cfg_t tap_cfg; int32_t ret; @@ -3549,7 +3559,7 @@ int32_t lsm6dsl_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_tap_cfg_t tap_cfg; @@ -3569,7 +3579,7 @@ int32_t lsm6dsl_tap_detection_on_x_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -3595,7 +3605,7 @@ int32_t lsm6dsl_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -3620,7 +3630,7 @@ int32_t lsm6dsl_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_int_dur2_t int_dur2; int32_t ret; @@ -3649,7 +3659,7 @@ int32_t lsm6dsl_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_int_dur2_t int_dur2; int32_t ret; @@ -3673,7 +3683,7 @@ int32_t lsm6dsl_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_int_dur2_t int_dur2; int32_t ret; @@ -3702,7 +3712,7 @@ int32_t lsm6dsl_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_int_dur2_t int_dur2; int32_t ret; @@ -3727,7 +3737,7 @@ int32_t lsm6dsl_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_int_dur2_t int_dur2; int32_t ret; @@ -3757,7 +3767,7 @@ int32_t lsm6dsl_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_int_dur2_t int_dur2; int32_t ret; @@ -3777,7 +3787,7 @@ int32_t lsm6dsl_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_tap_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dsl_single_double_tap_t val) { lsm6dsl_wake_up_ths_t wake_up_ths; @@ -3805,7 +3815,7 @@ int32_t lsm6dsl_tap_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_tap_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_single_double_tap_t *val) { lsm6dsl_wake_up_ths_t wake_up_ths; @@ -3854,7 +3864,7 @@ int32_t lsm6dsl_tap_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_6d_feed_data_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_6d_feed_data_set(const stmdev_ctx_t *ctx, lsm6dsl_low_pass_on_6d_t val) { lsm6dsl_ctrl8_xl_t ctrl8_xl; @@ -3879,7 +3889,7 @@ int32_t lsm6dsl_6d_feed_data_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_6d_feed_data_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_6d_feed_data_get(const stmdev_ctx_t *ctx, lsm6dsl_low_pass_on_6d_t *val) { lsm6dsl_ctrl8_xl_t ctrl8_xl; @@ -3913,7 +3923,7 @@ int32_t lsm6dsl_6d_feed_data_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_6d_threshold_set(const stmdev_ctx_t *ctx, lsm6dsl_sixd_ths_t val) { lsm6dsl_tap_ths_6d_t tap_ths_6d; @@ -3940,7 +3950,7 @@ int32_t lsm6dsl_6d_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_6d_threshold_get(const stmdev_ctx_t *ctx, lsm6dsl_sixd_ths_t *val) { lsm6dsl_tap_ths_6d_t tap_ths_6d; @@ -3983,7 +3993,7 @@ int32_t lsm6dsl_6d_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -4009,7 +4019,7 @@ int32_t lsm6dsl_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -4042,7 +4052,7 @@ int32_t lsm6dsl_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_wake_up_dur_t wake_up_dur; lsm6dsl_free_fall_t free_fall; @@ -4080,7 +4090,7 @@ int32_t lsm6dsl_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_wake_up_dur_t wake_up_dur; lsm6dsl_free_fall_t free_fall; @@ -4107,7 +4117,7 @@ int32_t lsm6dsl_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_ff_threshold_set(const stmdev_ctx_t *ctx, lsm6dsl_ff_ths_t val) { lsm6dsl_free_fall_t free_fall; @@ -4132,7 +4142,7 @@ int32_t lsm6dsl_ff_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_ff_threshold_get(const stmdev_ctx_t *ctx, lsm6dsl_ff_ths_t *val) { lsm6dsl_free_fall_t free_fall; @@ -4203,7 +4213,7 @@ int32_t lsm6dsl_ff_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsl_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val) { lsm6dsl_fifo_ctrl1_t fifo_ctrl1; lsm6dsl_fifo_ctrl2_t fifo_ctrl2; @@ -4237,7 +4247,7 @@ int32_t lsm6dsl_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsl_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dsl_fifo_ctrl1_t fifo_ctrl1; lsm6dsl_fifo_ctrl2_t fifo_ctrl2; @@ -4267,7 +4277,7 @@ int32_t lsm6dsl_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsl_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dsl_fifo_status1_t fifo_status1; lsm6dsl_fifo_status2_t fifo_status2; @@ -4295,7 +4305,7 @@ int32_t lsm6dsl_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_fifo_status2_t fifo_status2; int32_t ret; @@ -4316,7 +4326,7 @@ int32_t lsm6dsl_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsl_fifo_pattern_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dsl_fifo_status3_t fifo_status3; lsm6dsl_fifo_status4_t fifo_status4; @@ -4344,7 +4354,7 @@ int32_t lsm6dsl_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_fifo_temp_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -4370,7 +4380,7 @@ int32_t lsm6dsl_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_fifo_temp_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -4391,7 +4401,7 @@ int32_t lsm6dsl_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_write_trigger_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_write_trigger_set(const stmdev_ctx_t *ctx, lsm6dsl_trigger_fifo_t val) { lsm6dsl_fifo_ctrl2_t fifo_ctrl2; @@ -4433,7 +4443,7 @@ int32_t lsm6dsl_fifo_write_trigger_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_write_trigger_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_write_trigger_get(const stmdev_ctx_t *ctx, lsm6dsl_trigger_fifo_t *val) { lsm6dsl_fifo_ctrl2_t fifo_ctrl2; @@ -4481,7 +4491,7 @@ int32_t lsm6dsl_fifo_write_trigger_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_pedo_and_timestamp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_pedo_and_timestamp_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_fifo_ctrl2_t fifo_ctrl2; @@ -4509,7 +4519,7 @@ int32_t lsm6dsl_fifo_pedo_and_timestamp_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_pedo_and_timestamp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_pedo_and_timestamp_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_fifo_ctrl2_t fifo_ctrl2; @@ -4531,7 +4541,7 @@ int32_t lsm6dsl_fifo_pedo_and_timestamp_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_xl_batch_set(const stmdev_ctx_t *ctx, lsm6dsl_dec_fifo_xl_t val) { lsm6dsl_fifo_ctrl3_t fifo_ctrl3; @@ -4559,7 +4569,7 @@ int32_t lsm6dsl_fifo_xl_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_xl_batch_get(const stmdev_ctx_t *ctx, lsm6dsl_dec_fifo_xl_t *val) { lsm6dsl_fifo_ctrl3_t fifo_ctrl3; @@ -4619,7 +4629,7 @@ int32_t lsm6dsl_fifo_xl_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_gy_batch_set(const stmdev_ctx_t *ctx, lsm6dsl_dec_fifo_gyro_t val) { lsm6dsl_fifo_ctrl3_t fifo_ctrl3; @@ -4647,7 +4657,7 @@ int32_t lsm6dsl_fifo_gy_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_gy_batch_get(const stmdev_ctx_t *ctx, lsm6dsl_dec_fifo_gyro_t *val) { lsm6dsl_fifo_ctrl3_t fifo_ctrl3; @@ -4707,7 +4717,7 @@ int32_t lsm6dsl_fifo_gy_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_dataset_3_batch_set(const stmdev_ctx_t *ctx, lsm6dsl_dec_ds3_fifo_t val) { lsm6dsl_fifo_ctrl4_t fifo_ctrl4; @@ -4735,7 +4745,7 @@ int32_t lsm6dsl_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_dataset_3_batch_get(const stmdev_ctx_t *ctx, lsm6dsl_dec_ds3_fifo_t *val) { lsm6dsl_fifo_ctrl4_t fifo_ctrl4; @@ -4795,7 +4805,7 @@ int32_t lsm6dsl_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_dataset_4_batch_set(const stmdev_ctx_t *ctx, lsm6dsl_dec_ds4_fifo_t val) { lsm6dsl_fifo_ctrl4_t fifo_ctrl4; @@ -4823,7 +4833,7 @@ int32_t lsm6dsl_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_dataset_4_batch_get(const stmdev_ctx_t *ctx, lsm6dsl_dec_ds4_fifo_t *val) { lsm6dsl_fifo_ctrl4_t fifo_ctrl4; @@ -4882,7 +4892,7 @@ int32_t lsm6dsl_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_xl_gy_8bit_format_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_fifo_ctrl4_t fifo_ctrl4; @@ -4909,7 +4919,7 @@ int32_t lsm6dsl_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_xl_gy_8bit_format_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_fifo_ctrl4_t fifo_ctrl4; @@ -4931,7 +4941,7 @@ int32_t lsm6dsl_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_fifo_ctrl4_t fifo_ctrl4; int32_t ret; @@ -4958,7 +4968,7 @@ int32_t lsm6dsl_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_fifo_ctrl4_t fifo_ctrl4; int32_t ret; @@ -4978,7 +4988,7 @@ int32_t lsm6dsl_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dsl_fifo_mode_t val) { lsm6dsl_fifo_ctrl5_t fifo_ctrl5; @@ -5005,7 +5015,7 @@ int32_t lsm6dsl_fifo_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_fifo_mode_t *val) { lsm6dsl_fifo_ctrl5_t fifo_ctrl5; @@ -5052,7 +5062,7 @@ int32_t lsm6dsl_fifo_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsl_odr_fifo_t val) { lsm6dsl_fifo_ctrl5_t fifo_ctrl5; @@ -5079,7 +5089,7 @@ int32_t lsm6dsl_fifo_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_fifo_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsl_odr_fifo_t *val) { lsm6dsl_fifo_ctrl5_t fifo_ctrl5; @@ -5163,7 +5173,7 @@ int32_t lsm6dsl_fifo_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dsl_den_lh_t val) { lsm6dsl_ctrl5_c_t ctrl5_c; @@ -5188,7 +5198,7 @@ int32_t lsm6dsl_den_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dsl_den_lh_t *val) { lsm6dsl_ctrl5_c_t ctrl5_c; @@ -5222,7 +5232,7 @@ int32_t lsm6dsl_den_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_den_mode_set(const stmdev_ctx_t *ctx, lsm6dsl_den_mode_t val) { lsm6dsl_ctrl6_c_t ctrl6_c; @@ -5247,7 +5257,7 @@ int32_t lsm6dsl_den_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_den_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_den_mode_t *val) { lsm6dsl_ctrl6_c_t ctrl6_c; @@ -5290,7 +5300,7 @@ int32_t lsm6dsl_den_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_den_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_den_enable_set(const stmdev_ctx_t *ctx, lsm6dsl_den_xl_en_t val) { lsm6dsl_ctrl4_c_t ctrl4_c; @@ -5328,7 +5338,7 @@ int32_t lsm6dsl_den_enable_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_den_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_den_enable_get(const stmdev_ctx_t *ctx, lsm6dsl_den_xl_en_t *val) { lsm6dsl_ctrl4_c_t ctrl4_c; @@ -5372,7 +5382,7 @@ int32_t lsm6dsl_den_enable_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -5396,7 +5406,7 @@ int32_t lsm6dsl_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -5415,7 +5425,7 @@ int32_t lsm6dsl_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -5439,7 +5449,7 @@ int32_t lsm6dsl_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -5458,7 +5468,7 @@ int32_t lsm6dsl_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -5482,7 +5492,7 @@ int32_t lsm6dsl_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -5513,7 +5523,7 @@ int32_t lsm6dsl_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_pedo_step_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_ctrl10_c_t ctrl10_c; int32_t ret; @@ -5537,7 +5547,7 @@ int32_t lsm6dsl_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_pedo_step_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_ctrl10_c_t ctrl10_c; int32_t ret; @@ -5556,7 +5566,7 @@ int32_t lsm6dsl_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_ctrl10_c_t ctrl10_c; int32_t ret; @@ -5586,7 +5596,7 @@ int32_t lsm6dsl_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_ctrl10_c_t ctrl10_c; int32_t ret; @@ -5606,7 +5616,7 @@ int32_t lsm6dsl_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_pedo_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_config_pedo_ths_min_t config_pedo_ths_min; int32_t ret; @@ -5642,7 +5652,7 @@ int32_t lsm6dsl_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_pedo_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_config_pedo_ths_min_t config_pedo_ths_min; int32_t ret; @@ -5673,7 +5683,7 @@ int32_t lsm6dsl_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_pedo_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_pedo_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsl_pedo_fs_t val) { lsm6dsl_config_pedo_ths_min_t config_pedo_ths_min; @@ -5711,7 +5721,7 @@ int32_t lsm6dsl_pedo_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_pedo_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_pedo_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsl_pedo_fs_t *val) { lsm6dsl_config_pedo_ths_min_t config_pedo_ths_min; @@ -5756,7 +5766,7 @@ int32_t lsm6dsl_pedo_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_pedo_debounce_steps_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_pedo_deb_reg_t pedo_deb_reg; @@ -5793,7 +5803,7 @@ int32_t lsm6dsl_pedo_debounce_steps_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_pedo_debounce_steps_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_pedo_deb_reg_t pedo_deb_reg; @@ -5826,7 +5836,7 @@ int32_t lsm6dsl_pedo_debounce_steps_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_pedo_timeout_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_pedo_deb_reg_t pedo_deb_reg; int32_t ret; @@ -5864,7 +5874,7 @@ int32_t lsm6dsl_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_pedo_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_pedo_deb_reg_t pedo_deb_reg; int32_t ret; @@ -5894,7 +5904,7 @@ int32_t lsm6dsl_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_pedo_steps_period_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_pedo_steps_period_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -5922,7 +5932,7 @@ int32_t lsm6dsl_pedo_steps_period_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_pedo_steps_period_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_pedo_steps_period_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -5963,7 +5973,7 @@ int32_t lsm6dsl_pedo_steps_period_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_ctrl10_c_t ctrl10_c; int32_t ret; @@ -5992,7 +6002,7 @@ int32_t lsm6dsl_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_ctrl10_c_t ctrl10_c; int32_t ret; @@ -6011,7 +6021,7 @@ int32_t lsm6dsl_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsl_motion_threshold_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -6038,7 +6048,7 @@ int32_t lsm6dsl_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsl_motion_threshold_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -6078,7 +6088,7 @@ int32_t lsm6dsl_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_ctrl10_c_t ctrl10_c; int32_t ret; @@ -6108,7 +6118,7 @@ int32_t lsm6dsl_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_ctrl10_c_t ctrl10_c; int32_t ret; @@ -6127,7 +6137,7 @@ int32_t lsm6dsl_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_wrist_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_wrist_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_ctrl10_c_t ctrl10_c; int32_t ret; @@ -6157,7 +6167,7 @@ int32_t lsm6dsl_wrist_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_wrist_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_wrist_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_ctrl10_c_t ctrl10_c; int32_t ret; @@ -6178,7 +6188,7 @@ int32_t lsm6dsl_wrist_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_tilt_latency_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsl_tilt_latency_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -6207,7 +6217,7 @@ int32_t lsm6dsl_tilt_latency_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_tilt_latency_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsl_tilt_latency_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -6236,7 +6246,7 @@ int32_t lsm6dsl_tilt_latency_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_tilt_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsl_tilt_threshold_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -6265,7 +6275,7 @@ int32_t lsm6dsl_tilt_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_tilt_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsl_tilt_threshold_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -6292,7 +6302,7 @@ int32_t lsm6dsl_tilt_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_tilt_src_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_tilt_src_set(const stmdev_ctx_t *ctx, lsm6dsl_a_wrist_tilt_mask_t *val) { int32_t ret; @@ -6321,7 +6331,7 @@ int32_t lsm6dsl_tilt_src_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_tilt_src_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_tilt_src_get(const stmdev_ctx_t *ctx, lsm6dsl_a_wrist_tilt_mask_t *val) { int32_t ret; @@ -6363,7 +6373,7 @@ int32_t lsm6dsl_tilt_src_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -6387,7 +6397,7 @@ int32_t lsm6dsl_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -6406,7 +6416,7 @@ int32_t lsm6dsl_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_mag_hard_iron_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_master_config_t master_config; lsm6dsl_ctrl10_c_t ctrl10_c; @@ -6449,7 +6459,7 @@ int32_t lsm6dsl_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_mag_hard_iron_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_master_config_t master_config; int32_t ret; @@ -6470,7 +6480,7 @@ int32_t lsm6dsl_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_mag_soft_iron_mat_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -6499,7 +6509,7 @@ int32_t lsm6dsl_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_mag_soft_iron_mat_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_mag_soft_iron_mat_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -6528,7 +6538,7 @@ int32_t lsm6dsl_mag_soft_iron_mat_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsl_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -6563,7 +6573,7 @@ int32_t lsm6dsl_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsl_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -6610,7 +6620,7 @@ int32_t lsm6dsl_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_func_en_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_func_en_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_ctrl10_c_t ctrl10_c; int32_t ret; @@ -6635,7 +6645,7 @@ int32_t lsm6dsl_func_en_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_sh_sync_sens_frame_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_sensor_sync_time_frame_t sensor_sync_time_frame; int32_t ret; @@ -6662,7 +6672,7 @@ int32_t lsm6dsl_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_sync_sens_frame_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_sensor_sync_time_frame_t sensor_sync_time_frame; @@ -6683,7 +6693,7 @@ int32_t lsm6dsl_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_sync_sens_ratio_set(const stmdev_ctx_t *ctx, lsm6dsl_rr_t val) { lsm6dsl_sensor_sync_res_ratio_t sensor_sync_res_ratio; @@ -6710,7 +6720,7 @@ int32_t lsm6dsl_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_sync_sens_ratio_get(const stmdev_ctx_t *ctx, lsm6dsl_rr_t *val) { lsm6dsl_sensor_sync_res_ratio_t sensor_sync_res_ratio; @@ -6753,7 +6763,7 @@ int32_t lsm6dsl_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_master_config_t master_config; int32_t ret; @@ -6779,7 +6789,7 @@ int32_t lsm6dsl_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_master_config_t master_config; int32_t ret; @@ -6799,7 +6809,7 @@ int32_t lsm6dsl_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_master_config_t master_config; int32_t ret; @@ -6825,7 +6835,7 @@ int32_t lsm6dsl_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_master_config_t master_config; int32_t ret; @@ -6845,7 +6855,7 @@ int32_t lsm6dsl_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dsl_pull_up_en_t val) { lsm6dsl_master_config_t master_config; @@ -6872,7 +6882,7 @@ int32_t lsm6dsl_sh_pin_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_pull_up_en_t *val) { lsm6dsl_master_config_t master_config; @@ -6907,7 +6917,7 @@ int32_t lsm6dsl_sh_pin_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_syncro_mode_set(const stmdev_ctx_t *ctx, lsm6dsl_start_config_t val) { lsm6dsl_master_config_t master_config; @@ -6934,7 +6944,7 @@ int32_t lsm6dsl_sh_syncro_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_syncro_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_start_config_t *val) { lsm6dsl_master_config_t master_config; @@ -6969,7 +6979,7 @@ int32_t lsm6dsl_sh_syncro_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_sh_drdy_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_master_config_t master_config; int32_t ret; @@ -6995,7 +7005,7 @@ int32_t lsm6dsl_sh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_sh_drdy_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_master_config_t master_config; int32_t ret; @@ -7015,7 +7025,7 @@ int32_t lsm6dsl_sh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_read_data_raw_get(const stmdev_ctx_t *ctx, lsm6dsl_emb_sh_read_t *val) { int32_t ret; @@ -7041,7 +7051,7 @@ int32_t lsm6dsl_sh_read_data_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_sh_cmd_sens_sync_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_master_cmd_code_t master_cmd_code; int32_t ret; @@ -7068,7 +7078,7 @@ int32_t lsm6dsl_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_sh_cmd_sens_sync_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_master_cmd_code_t master_cmd_code; int32_t ret; @@ -7089,7 +7099,7 @@ int32_t lsm6dsl_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_spi_sync_error_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsl_sh_spi_sync_error_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsl_sens_sync_spi_error_code_t sens_sync_spi_error_code; int32_t ret; @@ -7116,7 +7126,7 @@ int32_t lsm6dsl_sh_spi_sync_error_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_spi_sync_error_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsl_sh_spi_sync_error_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsl_sens_sync_spi_error_code_t sens_sync_spi_error_code; int32_t ret; @@ -7136,7 +7146,7 @@ int32_t lsm6dsl_sh_spi_sync_error_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_num_of_dev_connected_set(const stmdev_ctx_t *ctx, lsm6dsl_aux_sens_on_t val) { lsm6dsl_slave0_config_t slave0_config; @@ -7173,7 +7183,7 @@ int32_t lsm6dsl_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_num_of_dev_connected_get(const stmdev_ctx_t *ctx, lsm6dsl_aux_sens_on_t *val) { lsm6dsl_slave0_config_t slave0_config; @@ -7229,7 +7239,7 @@ int32_t lsm6dsl_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_cfg_write(const stmdev_ctx_t *ctx, lsm6dsl_sh_cfg_write_t *val) { lsm6dsl_slv0_add_t slv0_add; @@ -7275,7 +7285,7 @@ int32_t lsm6dsl_sh_cfg_write(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_slv0_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, lsm6dsl_sh_cfg_read_t *val) { lsm6dsl_slave0_config_t slave0_config; @@ -7329,7 +7339,7 @@ int32_t lsm6dsl_sh_slv0_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_slv1_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, lsm6dsl_sh_cfg_read_t *val) { lsm6dsl_slave1_config_t slave1_config; @@ -7383,7 +7393,7 @@ int32_t lsm6dsl_sh_slv1_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_slv2_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, lsm6dsl_sh_cfg_read_t *val) { lsm6dsl_slv2_add_t slv2_add; @@ -7437,7 +7447,7 @@ int32_t lsm6dsl_sh_slv2_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_slv3_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, lsm6dsl_sh_cfg_read_t *val) { lsm6dsl_slave3_config_t slave3_config; @@ -7489,7 +7499,7 @@ int32_t lsm6dsl_sh_slv3_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_slave_0_dec_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_slave_0_dec_set(const stmdev_ctx_t *ctx, lsm6dsl_slave0_rate_t val) { lsm6dsl_slave0_config_t slave0_config; @@ -7527,7 +7537,7 @@ int32_t lsm6dsl_sh_slave_0_dec_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_slave_0_dec_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_slave_0_dec_get(const stmdev_ctx_t *ctx, lsm6dsl_slave0_rate_t *val) { lsm6dsl_slave0_config_t slave0_config; @@ -7583,7 +7593,7 @@ int32_t lsm6dsl_sh_slave_0_dec_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_write_mode_set(const stmdev_ctx_t *ctx, lsm6dsl_write_once_t val) { lsm6dsl_slave1_config_t slave1_config; @@ -7623,7 +7633,7 @@ int32_t lsm6dsl_sh_write_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_write_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_write_once_t *val) { lsm6dsl_slave1_config_t slave1_config; @@ -7669,7 +7679,7 @@ int32_t lsm6dsl_sh_write_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_slave_1_dec_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_slave_1_dec_set(const stmdev_ctx_t *ctx, lsm6dsl_slave1_rate_t val) { lsm6dsl_slave1_config_t slave1_config; @@ -7706,7 +7716,7 @@ int32_t lsm6dsl_sh_slave_1_dec_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_slave_1_dec_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_slave_1_dec_get(const stmdev_ctx_t *ctx, lsm6dsl_slave1_rate_t *val) { lsm6dsl_slave1_config_t slave1_config; @@ -7760,7 +7770,7 @@ int32_t lsm6dsl_sh_slave_1_dec_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_slave_2_dec_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_slave_2_dec_set(const stmdev_ctx_t *ctx, lsm6dsl_slave2_rate_t val) { lsm6dsl_slave2_config_t slave2_config; @@ -7798,7 +7808,7 @@ int32_t lsm6dsl_sh_slave_2_dec_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_slave_2_dec_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_slave_2_dec_get(const stmdev_ctx_t *ctx, lsm6dsl_slave2_rate_t *val) { lsm6dsl_slave2_config_t slave2_config; @@ -7852,7 +7862,7 @@ int32_t lsm6dsl_sh_slave_2_dec_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_slave_3_dec_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_slave_3_dec_set(const stmdev_ctx_t *ctx, lsm6dsl_slave3_rate_t val) { lsm6dsl_slave3_config_t slave3_config; @@ -7890,7 +7900,7 @@ int32_t lsm6dsl_sh_slave_3_dec_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsl_sh_slave_3_dec_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_slave_3_dec_get(const stmdev_ctx_t *ctx, lsm6dsl_slave3_rate_t *val) { lsm6dsl_slave3_config_t slave3_config; diff --git a/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.h b/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.h index b9addf3d..51049ff6 100644 --- a/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.h +++ b/sensor/stmemsc/lsm6dsl_STdC/driver/lsm6dsl_reg.h @@ -185,11 +185,9 @@ typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t not_used_01 : 5; -uint8_t func_cfg_en : - 3; /* func_cfg_en + func_cfg_en_b */ + uint8_t func_cfg_en : 3; /* func_cfg_en + func_cfg_en_b */ #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN -uint8_t func_cfg_en : - 3; /* func_cfg_en + func_cfg_en_b */ + uint8_t func_cfg_en : 3; /* func_cfg_en + func_cfg_en_b */ uint8_t not_used_01 : 5; #endif /* DRV_BYTE_ORDER */ } lsm6dsl_func_cfg_access_t; @@ -451,11 +449,9 @@ typedef struct uint8_t not_used_01 : 1; uint8_t usr_off_w : 1; uint8_t xl_hm_mode : 1; -uint8_t den_mode : - 3; /* trig_en + lvl_en + lvl2_en */ + uint8_t den_mode : 3; /* trig_en + lvl_en + lvl2_en */ #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN -uint8_t den_mode : - 3; /* trig_en + lvl_en + lvl2_en */ + uint8_t den_mode : 3; /* trig_en + lvl_en + lvl2_en */ uint8_t xl_hm_mode : 1; uint8_t usr_off_w : 1; uint8_t not_used_01 : 1; @@ -992,21 +988,18 @@ typedef struct #define LSM6DSL_FIFO_STATUS3 0x3CU typedef struct { -uint8_t fifo_pattern : - 8; /* + FIFO_STATUS4(fifo_pattern) */ + uint8_t fifo_pattern : 8; /* + FIFO_STATUS4(fifo_pattern) */ } lsm6dsl_fifo_status3_t; #define LSM6DSL_FIFO_STATUS4 0x3DU typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN -uint8_t fifo_pattern : - 2; /* + FIFO_STATUS3(fifo_pattern) */ + uint8_t fifo_pattern : 2; /* + FIFO_STATUS3(fifo_pattern) */ uint8_t not_used_01 : 6; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN uint8_t not_used_01 : 6; -uint8_t fifo_pattern : - 2; /* + FIFO_STATUS3(fifo_pattern) */ + uint8_t fifo_pattern : 2; /* + FIFO_STATUS3(fifo_pattern) */ #endif /* DRV_BYTE_ORDER */ } lsm6dsl_fifo_status4_t; @@ -1712,10 +1705,10 @@ typedef union * them with a custom implementation. */ -int32_t lsm6dsl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm6dsl_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lsm6dsl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm6dsl_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -1740,9 +1733,9 @@ typedef enum LSM6DSL_8g = 3, LSM6DSL_XL_FS_ND = 4, /* ERROR CODE */ } lsm6dsl_fs_xl_t; -int32_t lsm6dsl_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsl_fs_xl_t val); -int32_t lsm6dsl_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsl_fs_xl_t *val); typedef enum @@ -1761,9 +1754,9 @@ typedef enum LSM6DSL_XL_ODR_1Hz6 = 11, LSM6DSL_XL_ODR_ND = 12, /* ERROR CODE */ } lsm6dsl_odr_xl_t; -int32_t lsm6dsl_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsl_odr_xl_t val); -int32_t lsm6dsl_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsl_odr_xl_t *val); typedef enum @@ -1775,9 +1768,9 @@ typedef enum LSM6DSL_2000dps = 6, LSM6DSL_GY_FS_ND = 7, /* ERROR CODE */ } lsm6dsl_fs_g_t; -int32_t lsm6dsl_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsl_fs_g_t val); -int32_t lsm6dsl_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsl_fs_g_t *val); typedef enum @@ -1795,13 +1788,13 @@ typedef enum LSM6DSL_GY_ODR_6k66Hz = 10, LSM6DSL_GY_ODR_ND = 11, /* ERROR CODE */ } lsm6dsl_odr_g_t; -int32_t lsm6dsl_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_gy_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsl_odr_g_t val); -int32_t lsm6dsl_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsl_odr_g_t *val); -int32_t lsm6dsl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -1810,9 +1803,9 @@ typedef enum LSM6DSL_LSb_16mg = 1, LSM6DSL_WEIGHT_ND = 2, } lsm6dsl_usr_off_w_t; -int32_t lsm6dsl_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_offset_weight_set(const stmdev_ctx_t *ctx, lsm6dsl_usr_off_w_t val); -int32_t lsm6dsl_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_offset_weight_get(const stmdev_ctx_t *ctx, lsm6dsl_usr_off_w_t *val); typedef enum @@ -1821,9 +1814,9 @@ typedef enum LSM6DSL_XL_NORMAL = 1, LSM6DSL_XL_PW_MODE_ND = 2, /* ERROR CODE */ } lsm6dsl_xl_hm_mode_t; -int32_t lsm6dsl_xl_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_power_mode_set(const stmdev_ctx_t *ctx, lsm6dsl_xl_hm_mode_t val); -int32_t lsm6dsl_xl_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_power_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_xl_hm_mode_t *val); typedef enum @@ -1832,9 +1825,9 @@ typedef enum LSM6DSL_STAT_RND_ENABLE = 1, LSM6DSL_STAT_RND_ND = 2, /* ERROR CODE */ } lsm6dsl_rounding_status_t; -int32_t lsm6dsl_rounding_on_status_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_rounding_on_status_set(const stmdev_ctx_t *ctx, lsm6dsl_rounding_status_t val); -int32_t lsm6dsl_rounding_on_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_rounding_on_status_get(const stmdev_ctx_t *ctx, lsm6dsl_rounding_status_t *val); typedef enum @@ -1843,9 +1836,9 @@ typedef enum LSM6DSL_GY_NORMAL = 1, LSM6DSL_GY_PW_MODE_ND = 2, /* ERROR CODE */ } lsm6dsl_g_hm_mode_t; -int32_t lsm6dsl_gy_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_gy_power_mode_set(const stmdev_ctx_t *ctx, lsm6dsl_g_hm_mode_t val); -int32_t lsm6dsl_gy_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_gy_power_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_g_hm_mode_t *val); typedef struct @@ -1859,25 +1852,25 @@ typedef struct lsm6dsl_wrist_tilt_ia_t wrist_tilt_ia; lsm6dsl_a_wrist_tilt_mask_t a_wrist_tilt_mask; } lsm6dsl_all_sources_t; -int32_t lsm6dsl_all_sources_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_all_sources_get(const stmdev_ctx_t *ctx, lsm6dsl_all_sources_t *val); -int32_t lsm6dsl_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_status_reg_get(const stmdev_ctx_t *ctx, lsm6dsl_status_reg_t *val); -int32_t lsm6dsl_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsl_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsl_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsl_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsl_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -1885,9 +1878,9 @@ typedef enum LSM6DSL_LSB_25us = 1, LSM6DSL_TS_RES_ND = 2, /* ERROR CODE */ } lsm6dsl_timer_hr_t; -int32_t lsm6dsl_timestamp_res_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_timestamp_res_set(const stmdev_ctx_t *ctx, lsm6dsl_timer_hr_t val); -int32_t lsm6dsl_timestamp_res_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_timestamp_res_get(const stmdev_ctx_t *ctx, lsm6dsl_timer_hr_t *val); typedef enum @@ -1902,19 +1895,19 @@ typedef enum LSM6DSL_ROUND_GY_XL_SH1_TO_SH6 = 7, LSM6DSL_ROUND_OUT_ND = 8, /* ERROR CODE */ } lsm6dsl_rounding_t; -int32_t lsm6dsl_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_rounding_mode_set(const stmdev_ctx_t *ctx, lsm6dsl_rounding_t val); -int32_t lsm6dsl_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_rounding_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_rounding_t *val); -int32_t lsm6dsl_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsl_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsl_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsl_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsl_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsl_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsl_mag_calibrated_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_mag_calibrated_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsl_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer, +int32_t lsm6dsl_fifo_raw_data_get(const stmdev_ctx_t *ctx, uint8_t *buffer, uint8_t len); typedef enum @@ -1924,9 +1917,9 @@ typedef enum LSM6DSL_BANK_B = 5, LSM6DSL_BANK_ND = 6, /* ERROR CODE */ } lsm6dsl_func_cfg_en_t; -int32_t lsm6dsl_mem_bank_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dsl_func_cfg_en_t val); -int32_t lsm6dsl_mem_bank_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dsl_func_cfg_en_t *val); typedef enum @@ -1935,14 +1928,14 @@ typedef enum LSM6DSL_DRDY_PULSED = 1, LSM6DSL_DRDY_ND = 2, /* ERROR CODE */ } lsm6dsl_drdy_pulsed_g_t; -int32_t lsm6dsl_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm6dsl_drdy_pulsed_g_t val); -int32_t lsm6dsl_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_drdy_pulsed_g_t *val); -int32_t lsm6dsl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsl_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsl_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -1950,15 +1943,15 @@ typedef enum LSM6DSL_MSB_AT_LOW_ADD = 1, LSM6DSL_DATA_FMT_ND = 2, /* ERROR CODE */ } lsm6dsl_ble_t; -int32_t lsm6dsl_data_format_set(stmdev_ctx_t *ctx, lsm6dsl_ble_t val); -int32_t lsm6dsl_data_format_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_data_format_set(const stmdev_ctx_t *ctx, lsm6dsl_ble_t val); +int32_t lsm6dsl_data_format_get(const stmdev_ctx_t *ctx, lsm6dsl_ble_t *val); -int32_t lsm6dsl_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -1967,9 +1960,9 @@ typedef enum LSM6DSL_XL_ST_NEGATIVE = 2, LSM6DSL_XL_ST_ND = 3, /* ERROR CODE */ } lsm6dsl_st_xl_t; -int32_t lsm6dsl_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dsl_st_xl_t val); -int32_t lsm6dsl_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dsl_st_xl_t *val); typedef enum @@ -1979,14 +1972,14 @@ typedef enum LSM6DSL_GY_ST_NEGATIVE = 3, LSM6DSL_GY_ST_ND = 4, /* ERROR CODE */ } lsm6dsl_st_g_t; -int32_t lsm6dsl_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dsl_st_g_t val); -int32_t lsm6dsl_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dsl_st_g_t *val); -int32_t lsm6dsl_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -1995,9 +1988,9 @@ typedef enum LSM6DSL_USE_HPF = 1, LSM6DSL_HP_PATH_ND = 2, /* ERROR CODE */ } lsm6dsl_slope_fds_t; -int32_t lsm6dsl_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dsl_slope_fds_t val); -int32_t lsm6dsl_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dsl_slope_fds_t *val); typedef enum @@ -2006,9 +1999,9 @@ typedef enum LSM6DSL_XL_ANA_BW_400Hz = 1, LSM6DSL_XL_ANA_BW_ND = 2, /* ERROR CODE */ } lsm6dsl_bw0_xl_t; -int32_t lsm6dsl_xl_filter_analog_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_filter_analog_set(const stmdev_ctx_t *ctx, lsm6dsl_bw0_xl_t val); -int32_t lsm6dsl_xl_filter_analog_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_filter_analog_get(const stmdev_ctx_t *ctx, lsm6dsl_bw0_xl_t *val); typedef enum @@ -2017,9 +2010,9 @@ typedef enum LSM6DSL_XL_LP1_ODR_DIV_4 = 1, LSM6DSL_XL_LP1_NA = 2, /* ERROR CODE */ } lsm6dsl_lpf1_bw_sel_t; -int32_t lsm6dsl_xl_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsl_lpf1_bw_sel_t val); -int32_t lsm6dsl_xl_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsl_lpf1_bw_sel_t *val); typedef enum @@ -2034,13 +2027,13 @@ typedef enum LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_400 = 0x13, LSM6DSL_XL_LP_NA = 0x20, /* ERROR CODE */ } lsm6dsl_input_composite_t; -int32_t lsm6dsl_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsl_input_composite_t val); -int32_t lsm6dsl_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsl_input_composite_t *val); -int32_t lsm6dsl_xl_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_xl_reference_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_xl_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2051,9 +2044,9 @@ typedef enum LSM6DSL_XL_HP_ODR_DIV_400 = 0x03, LSM6DSL_XL_HP_NA = 0x10, /* ERROR CODE */ } lsm6dsl_hpcf_xl_t; -int32_t lsm6dsl_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_hp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsl_hpcf_xl_t val); -int32_t lsm6dsl_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_xl_hp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsl_hpcf_xl_t *val); typedef enum @@ -2077,9 +2070,9 @@ typedef enum LSM6DSL_HP_GY_BAND_NA = 0xFF, /* ERROR CODE */ } lsm6dsl_lpf1_sel_g_t; -int32_t lsm6dsl_gy_band_pass_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_gy_band_pass_set(const stmdev_ctx_t *ctx, lsm6dsl_lpf1_sel_g_t val); -int32_t lsm6dsl_gy_band_pass_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_gy_band_pass_get(const stmdev_ctx_t *ctx, lsm6dsl_lpf1_sel_g_t *val); typedef enum @@ -2088,8 +2081,8 @@ typedef enum LSM6DSL_SPI_3_WIRE = 1, LSM6DSL_SPI_MODE_ND = 2, /* ERROR CODE */ } lsm6dsl_sim_t; -int32_t lsm6dsl_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsl_sim_t val); -int32_t lsm6dsl_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsl_sim_t *val); +int32_t lsm6dsl_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsl_sim_t val); +int32_t lsm6dsl_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_sim_t *val); typedef enum { @@ -2097,9 +2090,9 @@ typedef enum LSM6DSL_I2C_DISABLE = 1, LSM6DSL_I2C_MODE_ND = 2, /* ERROR CODE */ } lsm6dsl_i2c_disable_t; -int32_t lsm6dsl_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_i2c_interface_set(const stmdev_ctx_t *ctx, lsm6dsl_i2c_disable_t val); -int32_t lsm6dsl_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_i2c_interface_get(const stmdev_ctx_t *ctx, lsm6dsl_i2c_disable_t *val); typedef struct @@ -2123,9 +2116,9 @@ typedef struct uint8_t den_drdy_int1 : 1; uint8_t drdy_on_int1 : 1; } lsm6dsl_int1_route_t; -int32_t lsm6dsl_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm6dsl_int1_route_t val); -int32_t lsm6dsl_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm6dsl_int1_route_t *val); typedef struct @@ -2148,9 +2141,9 @@ typedef struct uint8_t int2_inact_state : 1; uint8_t int2_wrist_tilt : 1; } lsm6dsl_int2_route_t; -int32_t lsm6dsl_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm6dsl_int2_route_t val); -int32_t lsm6dsl_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_pin_int2_route_get(const stmdev_ctx_t *ctx, lsm6dsl_int2_route_t *val); typedef enum @@ -2159,8 +2152,8 @@ typedef enum LSM6DSL_OPEN_DRAIN = 1, LSM6DSL_PIN_MODE_ND = 2, /* ERROR CODE */ } lsm6dsl_pp_od_t; -int32_t lsm6dsl_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsl_pp_od_t val); -int32_t lsm6dsl_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsl_pp_od_t *val); +int32_t lsm6dsl_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dsl_pp_od_t val); +int32_t lsm6dsl_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_pp_od_t *val); typedef enum { @@ -2168,13 +2161,13 @@ typedef enum LSM6DSL_ACTIVE_LOW = 1, LSM6DSL_POLARITY_ND = 2, /* ERROR CODE */ } lsm6dsl_h_lactive_t; -int32_t lsm6dsl_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_pin_polarity_set(const stmdev_ctx_t *ctx, lsm6dsl_h_lactive_t val); -int32_t lsm6dsl_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_pin_polarity_get(const stmdev_ctx_t *ctx, lsm6dsl_h_lactive_t *val); -int32_t lsm6dsl_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2182,19 +2175,19 @@ typedef enum LSM6DSL_INT_LATCHED = 1, LSM6DSL_INT_MODE = 2, /* ERROR CODE */ } lsm6dsl_lir_t; -int32_t lsm6dsl_int_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_int_notification_set(const stmdev_ctx_t *ctx, lsm6dsl_lir_t val); -int32_t lsm6dsl_int_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_int_notification_get(const stmdev_ctx_t *ctx, lsm6dsl_lir_t *val); -int32_t lsm6dsl_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2204,43 +2197,43 @@ typedef enum LSM6DSL_XL_12Hz5_GY_PD = 3, LSM6DSL_ACT_MODE_ND = 4, /* ERROR CODE */ } lsm6dsl_inact_en_t; -int32_t lsm6dsl_act_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_act_mode_set(const stmdev_ctx_t *ctx, lsm6dsl_inact_en_t val); -int32_t lsm6dsl_act_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_act_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_inact_en_t *val); -int32_t lsm6dsl_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_tap_src_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_tap_src_get(const stmdev_ctx_t *ctx, lsm6dsl_tap_src_t *val); -int32_t lsm6dsl_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2248,9 +2241,9 @@ typedef enum LSM6DSL_BOTH_SINGLE_DOUBLE = 1, LSM6DSL_TAP_MODE_ND = 2, /* ERROR CODE */ } lsm6dsl_single_double_tap_t; -int32_t lsm6dsl_tap_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dsl_single_double_tap_t val); -int32_t lsm6dsl_tap_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_single_double_tap_t *val); typedef enum @@ -2259,9 +2252,9 @@ typedef enum LSM6DSL_LPF2_FEED = 1, LSM6DSL_6D_FEED_ND = 2, /* ERROR CODE */ } lsm6dsl_low_pass_on_6d_t; -int32_t lsm6dsl_6d_feed_data_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_6d_feed_data_set(const stmdev_ctx_t *ctx, lsm6dsl_low_pass_on_6d_t val); -int32_t lsm6dsl_6d_feed_data_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_6d_feed_data_get(const stmdev_ctx_t *ctx, lsm6dsl_low_pass_on_6d_t *val); typedef enum @@ -2272,16 +2265,16 @@ typedef enum LSM6DSL_DEG_50 = 3, LSM6DSL_6D_TH_ND = 4, /* ERROR CODE */ } lsm6dsl_sixd_ths_t; -int32_t lsm6dsl_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_6d_threshold_set(const stmdev_ctx_t *ctx, lsm6dsl_sixd_ths_t val); -int32_t lsm6dsl_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_6d_threshold_get(const stmdev_ctx_t *ctx, lsm6dsl_sixd_ths_t *val); -int32_t lsm6dsl_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2295,22 +2288,22 @@ typedef enum LSM6DSL_FF_TSH_500mg = 7, LSM6DSL_FF_TSH_ND = 8, /* ERROR CODE */ } lsm6dsl_ff_ths_t; -int32_t lsm6dsl_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_ff_threshold_set(const stmdev_ctx_t *ctx, lsm6dsl_ff_ths_t val); -int32_t lsm6dsl_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_ff_threshold_get(const stmdev_ctx_t *ctx, lsm6dsl_ff_ths_t *val); -int32_t lsm6dsl_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsl_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsl_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsl_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsl_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsl_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsl_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsl_fifo_pattern_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsl_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_fifo_temp_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_fifo_temp_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2319,14 +2312,14 @@ typedef enum LSM6DSL_TRG_SH_DRDY = 2, LSM6DSL_TRG_SH_ND = 3, /* ERROR CODE */ } lsm6dsl_trigger_fifo_t; -int32_t lsm6dsl_fifo_write_trigger_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_write_trigger_set(const stmdev_ctx_t *ctx, lsm6dsl_trigger_fifo_t val); -int32_t lsm6dsl_fifo_write_trigger_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_write_trigger_get(const stmdev_ctx_t *ctx, lsm6dsl_trigger_fifo_t *val); -int32_t lsm6dsl_fifo_pedo_and_timestamp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_pedo_and_timestamp_batch_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_fifo_pedo_and_timestamp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_pedo_and_timestamp_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2341,9 +2334,9 @@ typedef enum LSM6DSL_FIFO_XL_DEC_32 = 7, LSM6DSL_FIFO_XL_DEC_ND = 8, /* ERROR CODE */ } lsm6dsl_dec_fifo_xl_t; -int32_t lsm6dsl_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_xl_batch_set(const stmdev_ctx_t *ctx, lsm6dsl_dec_fifo_xl_t val); -int32_t lsm6dsl_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_xl_batch_get(const stmdev_ctx_t *ctx, lsm6dsl_dec_fifo_xl_t *val); typedef enum @@ -2358,9 +2351,9 @@ typedef enum LSM6DSL_FIFO_GY_DEC_32 = 7, LSM6DSL_FIFO_GY_DEC_ND = 8, /* ERROR CODE */ } lsm6dsl_dec_fifo_gyro_t; -int32_t lsm6dsl_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_gy_batch_set(const stmdev_ctx_t *ctx, lsm6dsl_dec_fifo_gyro_t val); -int32_t lsm6dsl_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_gy_batch_get(const stmdev_ctx_t *ctx, lsm6dsl_dec_fifo_gyro_t *val); typedef enum @@ -2375,9 +2368,9 @@ typedef enum LSM6DSL_FIFO_DS3_DEC_32 = 7, LSM6DSL_FIFO_DS3_DEC_ND = 8, /* ERROR CODE */ } lsm6dsl_dec_ds3_fifo_t; -int32_t lsm6dsl_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_dataset_3_batch_set(const stmdev_ctx_t *ctx, lsm6dsl_dec_ds3_fifo_t val); -int32_t lsm6dsl_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_dataset_3_batch_get(const stmdev_ctx_t *ctx, lsm6dsl_dec_ds3_fifo_t *val); typedef enum @@ -2392,18 +2385,18 @@ typedef enum LSM6DSL_FIFO_DS4_DEC_32 = 7, LSM6DSL_FIFO_DS4_DEC_ND = 8, /* ERROR CODE */ } lsm6dsl_dec_ds4_fifo_t; -int32_t lsm6dsl_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_dataset_4_batch_set(const stmdev_ctx_t *ctx, lsm6dsl_dec_ds4_fifo_t val); -int32_t lsm6dsl_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_dataset_4_batch_get(const stmdev_ctx_t *ctx, lsm6dsl_dec_ds4_fifo_t *val); -int32_t lsm6dsl_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_xl_gy_8bit_format_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_xl_gy_8bit_format_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2414,9 +2407,9 @@ typedef enum LSM6DSL_STREAM_MODE = 6, LSM6DSL_FIFO_MODE_ND = 8, /* ERROR CODE */ } lsm6dsl_fifo_mode_t; -int32_t lsm6dsl_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dsl_fifo_mode_t val); -int32_t lsm6dsl_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_fifo_mode_t *val); typedef enum @@ -2434,9 +2427,9 @@ typedef enum LSM6DSL_FIFO_6k66Hz = 10, LSM6DSL_FIFO_RATE_ND = 11, /* ERROR CODE */ } lsm6dsl_odr_fifo_t; -int32_t lsm6dsl_fifo_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsl_odr_fifo_t val); -int32_t lsm6dsl_fifo_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_fifo_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsl_odr_fifo_t *val); typedef enum @@ -2445,9 +2438,9 @@ typedef enum LSM6DSL_DEN_ACT_HIGH = 1, LSM6DSL_DEN_POL_ND = 2, /* ERROR CODE */ } lsm6dsl_den_lh_t; -int32_t lsm6dsl_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dsl_den_lh_t val); -int32_t lsm6dsl_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dsl_den_lh_t *val); typedef enum @@ -2459,9 +2452,9 @@ typedef enum LSM6DSL_EDGE_TRIGGER = 4, LSM6DSL_DEN_MODE_ND = 5, /* ERROR CODE */ } lsm6dsl_den_mode_t; -int32_t lsm6dsl_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_den_mode_set(const stmdev_ctx_t *ctx, lsm6dsl_den_mode_t val); -int32_t lsm6dsl_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_den_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_den_mode_t *val); typedef enum @@ -2471,28 +2464,28 @@ typedef enum LSM6DSL_STAMP_IN_GY_XL_DATA = 2, LSM6DSL_DEN_STAMP_ND = 3, /* ERROR CODE */ } lsm6dsl_den_xl_en_t; -int32_t lsm6dsl_den_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_den_enable_set(const stmdev_ctx_t *ctx, lsm6dsl_den_xl_en_t val); -int32_t lsm6dsl_den_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_den_enable_get(const stmdev_ctx_t *ctx, lsm6dsl_den_xl_en_t *val); -int32_t lsm6dsl_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_pedo_step_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_pedo_step_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_pedo_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_pedo_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2500,68 +2493,68 @@ typedef enum LSM6DSL_PEDO_AT_4g = 1, LSM6DSL_PEDO_FS_ND = 2, /* ERROR CODE */ } lsm6dsl_pedo_fs_t; -int32_t lsm6dsl_pedo_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_pedo_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsl_pedo_fs_t val); -int32_t lsm6dsl_pedo_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_pedo_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsl_pedo_fs_t *val); -int32_t lsm6dsl_pedo_debounce_steps_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_pedo_debounce_steps_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_pedo_timeout_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_pedo_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_pedo_steps_period_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_pedo_steps_period_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsl_pedo_steps_period_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_pedo_steps_period_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsl_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_motion_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_motion_threshold_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsl_motion_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_motion_threshold_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsl_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_wrist_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_wrist_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_wrist_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_wrist_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_tilt_latency_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsl_tilt_latency_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsl_tilt_latency_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsl_tilt_latency_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsl_tilt_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsl_tilt_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsl_tilt_threshold_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsl_tilt_threshold_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsl_tilt_src_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_tilt_src_set(const stmdev_ctx_t *ctx, lsm6dsl_a_wrist_tilt_mask_t *val); -int32_t lsm6dsl_tilt_src_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_tilt_src_get(const stmdev_ctx_t *ctx, lsm6dsl_a_wrist_tilt_mask_t *val); -int32_t lsm6dsl_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_mag_hard_iron_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_mag_hard_iron_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_mag_soft_iron_mat_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsl_mag_soft_iron_mat_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_mag_soft_iron_mat_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsl_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsl_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsl_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsl_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsl_func_en_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_func_en_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_sync_sens_frame_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_sync_sens_frame_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2572,16 +2565,16 @@ typedef enum LSM6DSL_RES_RATIO_2_14 = 3, LSM6DSL_RES_RATIO_ND = 4, /* ERROR CODE */ } lsm6dsl_rr_t; -int32_t lsm6dsl_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_sync_sens_ratio_set(const stmdev_ctx_t *ctx, lsm6dsl_rr_t val); -int32_t lsm6dsl_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_sync_sens_ratio_get(const stmdev_ctx_t *ctx, lsm6dsl_rr_t *val); -int32_t lsm6dsl_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2589,9 +2582,9 @@ typedef enum LSM6DSL_INTERNAL_PULL_UP = 1, LSM6DSL_SH_PIN_MODE = 2, /* ERROR CODE */ } lsm6dsl_pull_up_en_t; -int32_t lsm6dsl_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dsl_pull_up_en_t val); -int32_t lsm6dsl_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_pull_up_en_t *val); typedef enum @@ -2600,13 +2593,13 @@ typedef enum LSM6DSL_EXT_ON_INT2_PIN = 1, LSM6DSL_SH_SYNCRO_ND = 2, /* ERROR CODE */ } lsm6dsl_start_config_t; -int32_t lsm6dsl_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_syncro_mode_set(const stmdev_ctx_t *ctx, lsm6dsl_start_config_t val); -int32_t lsm6dsl_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_syncro_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_start_config_t *val); -int32_t lsm6dsl_sh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_sh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_sh_drdy_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_sh_drdy_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -2629,14 +2622,14 @@ typedef struct lsm6dsl_sensorhub17_reg_t sh_byte_17; lsm6dsl_sensorhub18_reg_t sh_byte_18; } lsm6dsl_emb_sh_read_t; -int32_t lsm6dsl_sh_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_read_data_raw_get(const stmdev_ctx_t *ctx, lsm6dsl_emb_sh_read_t *val); -int32_t lsm6dsl_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsl_sh_cmd_sens_sync_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_sh_cmd_sens_sync_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsl_sh_spi_sync_error_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsl_sh_spi_sync_error_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_spi_sync_error_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsl_sh_spi_sync_error_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2647,9 +2640,9 @@ typedef enum LSM6DSL_SLV_0_1_2_3 = 3, LSM6DSL_SLV_EN_ND = 4, /* ERROR CODE */ } lsm6dsl_aux_sens_on_t; -int32_t lsm6dsl_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_num_of_dev_connected_set(const stmdev_ctx_t *ctx, lsm6dsl_aux_sens_on_t val); -int32_t lsm6dsl_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_num_of_dev_connected_get(const stmdev_ctx_t *ctx, lsm6dsl_aux_sens_on_t *val); typedef struct @@ -2658,7 +2651,7 @@ typedef struct uint8_t slv0_subadd; uint8_t slv0_data; } lsm6dsl_sh_cfg_write_t; -int32_t lsm6dsl_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_cfg_write(const stmdev_ctx_t *ctx, lsm6dsl_sh_cfg_write_t *val); typedef struct @@ -2667,13 +2660,13 @@ typedef struct uint8_t slv_subadd; uint8_t slv_len; } lsm6dsl_sh_cfg_read_t; -int32_t lsm6dsl_sh_slv0_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, lsm6dsl_sh_cfg_read_t *val); -int32_t lsm6dsl_sh_slv1_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, lsm6dsl_sh_cfg_read_t *val); -int32_t lsm6dsl_sh_slv2_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, lsm6dsl_sh_cfg_read_t *val); -int32_t lsm6dsl_sh_slv3_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, lsm6dsl_sh_cfg_read_t *val); typedef enum @@ -2684,9 +2677,9 @@ typedef enum LSM6DSL_SL0_DEC_8 = 3, LSM6DSL_SL0_DEC_ND = 4, /* ERROR CODE */ } lsm6dsl_slave0_rate_t; -int32_t lsm6dsl_sh_slave_0_dec_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_slave_0_dec_set(const stmdev_ctx_t *ctx, lsm6dsl_slave0_rate_t val); -int32_t lsm6dsl_sh_slave_0_dec_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_slave_0_dec_get(const stmdev_ctx_t *ctx, lsm6dsl_slave0_rate_t *val); typedef enum @@ -2695,9 +2688,9 @@ typedef enum LSM6DSL_ONLY_FIRST_CYCLE = 1, LSM6DSL_SH_WR_MODE_ND = 2, /* ERROR CODE */ } lsm6dsl_write_once_t; -int32_t lsm6dsl_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_write_mode_set(const stmdev_ctx_t *ctx, lsm6dsl_write_once_t val); -int32_t lsm6dsl_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_write_mode_get(const stmdev_ctx_t *ctx, lsm6dsl_write_once_t *val); typedef enum @@ -2708,9 +2701,9 @@ typedef enum LSM6DSL_SL1_DEC_8 = 3, LSM6DSL_SL1_DEC_ND = 4, /* ERROR CODE */ } lsm6dsl_slave1_rate_t; -int32_t lsm6dsl_sh_slave_1_dec_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_slave_1_dec_set(const stmdev_ctx_t *ctx, lsm6dsl_slave1_rate_t val); -int32_t lsm6dsl_sh_slave_1_dec_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_slave_1_dec_get(const stmdev_ctx_t *ctx, lsm6dsl_slave1_rate_t *val); typedef enum @@ -2721,9 +2714,9 @@ typedef enum LSM6DSL_SL2_DEC_8 = 3, LSM6DSL_SL2_DEC_ND = 4, /* ERROR CODE */ } lsm6dsl_slave2_rate_t; -int32_t lsm6dsl_sh_slave_2_dec_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_slave_2_dec_set(const stmdev_ctx_t *ctx, lsm6dsl_slave2_rate_t val); -int32_t lsm6dsl_sh_slave_2_dec_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_slave_2_dec_get(const stmdev_ctx_t *ctx, lsm6dsl_slave2_rate_t *val); typedef enum @@ -2734,9 +2727,9 @@ typedef enum LSM6DSL_SL3_DEC_8 = 3, LSM6DSL_SL3_DEC_ND = 4, /* ERROR CODE */ } lsm6dsl_slave3_rate_t; -int32_t lsm6dsl_sh_slave_3_dec_set(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_slave_3_dec_set(const stmdev_ctx_t *ctx, lsm6dsl_slave3_rate_t val); -int32_t lsm6dsl_sh_slave_3_dec_get(stmdev_ctx_t *ctx, +int32_t lsm6dsl_sh_slave_3_dec_get(const stmdev_ctx_t *ctx, lsm6dsl_slave3_rate_t *val); /** diff --git a/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.c b/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.c index 1bfbe5f4..5f23d34f 100644 --- a/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.c +++ b/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm6dsm_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm6dsm_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lsm6dsm_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm6dsm_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm6dsm_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -162,7 +172,7 @@ float_t lsm6dsm_from_lsb_to_celsius(int16_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsm_fs_xl_t val) { lsm6dsm_ctrl1_xl_t ctrl1_xl; @@ -187,7 +197,7 @@ int32_t lsm6dsm_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsm_fs_xl_t *val) { lsm6dsm_ctrl1_xl_t ctrl1_xl; @@ -229,7 +239,7 @@ int32_t lsm6dsm_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsm_odr_xl_t val) { lsm6dsm_ctrl1_xl_t ctrl1_xl; @@ -254,7 +264,7 @@ int32_t lsm6dsm_xl_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsm_odr_xl_t *val) { lsm6dsm_ctrl1_xl_t ctrl1_xl; @@ -328,7 +338,7 @@ int32_t lsm6dsm_xl_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsm_fs_g_t val) { lsm6dsm_ctrl2_g_t ctrl2_g; @@ -353,7 +363,7 @@ int32_t lsm6dsm_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsm_fs_g_t *val) { lsm6dsm_ctrl2_g_t ctrl2_g; @@ -399,7 +409,7 @@ int32_t lsm6dsm_gy_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_gy_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsm_odr_g_t val) { lsm6dsm_ctrl2_g_t ctrl2_g; @@ -424,7 +434,7 @@ int32_t lsm6dsm_gy_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsm_odr_g_t *val) { lsm6dsm_ctrl2_g_t ctrl2_g; @@ -494,7 +504,7 @@ int32_t lsm6dsm_gy_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_ctrl3_c_t ctrl3_c; int32_t ret; @@ -518,7 +528,7 @@ int32_t lsm6dsm_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_ctrl3_c_t ctrl3_c; int32_t ret; @@ -538,7 +548,7 @@ int32_t lsm6dsm_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_offset_weight_set(const stmdev_ctx_t *ctx, lsm6dsm_usr_off_w_t val) { lsm6dsm_ctrl6_c_t ctrl6_c; @@ -564,7 +574,7 @@ int32_t lsm6dsm_xl_offset_weight_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_offset_weight_get(const stmdev_ctx_t *ctx, lsm6dsm_usr_off_w_t *val) { lsm6dsm_ctrl6_c_t ctrl6_c; @@ -598,7 +608,7 @@ int32_t lsm6dsm_xl_offset_weight_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_power_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_xl_hm_mode_t val) { lsm6dsm_ctrl6_c_t ctrl6_c; @@ -623,7 +633,7 @@ int32_t lsm6dsm_xl_power_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_power_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_xl_hm_mode_t *val) { lsm6dsm_ctrl6_c_t ctrl6_c; @@ -659,7 +669,7 @@ int32_t lsm6dsm_xl_power_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_rounding_on_status_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_rounding_on_status_set(const stmdev_ctx_t *ctx, lsm6dsm_rounding_status_t val) { lsm6dsm_ctrl7_g_t ctrl7_g; @@ -686,7 +696,7 @@ int32_t lsm6dsm_rounding_on_status_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_rounding_on_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_rounding_on_status_get(const stmdev_ctx_t *ctx, lsm6dsm_rounding_status_t *val) { lsm6dsm_ctrl7_g_t ctrl7_g; @@ -720,7 +730,7 @@ int32_t lsm6dsm_rounding_on_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_gy_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_gy_power_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_g_hm_mode_t val) { lsm6dsm_ctrl7_g_t ctrl7_g; @@ -745,7 +755,7 @@ int32_t lsm6dsm_gy_power_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_gy_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_gy_power_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_g_hm_mode_t *val) { lsm6dsm_ctrl7_g_t ctrl7_g; @@ -780,7 +790,7 @@ int32_t lsm6dsm_gy_power_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_all_sources_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_all_sources_get(const stmdev_ctx_t *ctx, lsm6dsm_all_sources_t *val) { int32_t ret; @@ -850,7 +860,7 @@ int32_t lsm6dsm_all_sources_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_status_reg_get(const stmdev_ctx_t *ctx, lsm6dsm_status_reg_t *val) { int32_t ret; @@ -868,7 +878,7 @@ int32_t lsm6dsm_status_reg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_status_reg_t status_reg; @@ -889,7 +899,7 @@ int32_t lsm6dsm_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_status_reg_t status_reg; @@ -910,7 +920,7 @@ int32_t lsm6dsm_gy_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_status_reg_t status_reg; @@ -933,7 +943,7 @@ int32_t lsm6dsm_temp_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsm_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -952,7 +962,7 @@ int32_t lsm6dsm_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsm_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -983,7 +993,7 @@ int32_t lsm6dsm_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_ctrl10_c_t ctrl10_c; int32_t ret; @@ -1013,7 +1023,7 @@ int32_t lsm6dsm_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_ctrl10_c_t ctrl10_c; int32_t ret; @@ -1037,7 +1047,7 @@ int32_t lsm6dsm_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_timestamp_res_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_timestamp_res_set(const stmdev_ctx_t *ctx, lsm6dsm_timer_hr_t val) { lsm6dsm_wake_up_dur_t wake_up_dur; @@ -1069,7 +1079,7 @@ int32_t lsm6dsm_timestamp_res_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_timestamp_res_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_timestamp_res_get(const stmdev_ctx_t *ctx, lsm6dsm_timer_hr_t *val) { lsm6dsm_wake_up_dur_t wake_up_dur; @@ -1117,7 +1127,7 @@ int32_t lsm6dsm_timestamp_res_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_rounding_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_rounding_t val) { lsm6dsm_ctrl5_c_t ctrl5_c; @@ -1143,7 +1153,7 @@ int32_t lsm6dsm_rounding_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_rounding_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_rounding_t *val) { lsm6dsm_ctrl5_c_t ctrl5_c; @@ -1202,7 +1212,7 @@ int32_t lsm6dsm_rounding_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsm_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1223,7 +1233,7 @@ int32_t lsm6dsm_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsm_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1248,7 +1258,7 @@ int32_t lsm6dsm_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsm_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1272,7 +1282,7 @@ int32_t lsm6dsm_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_mag_calibrated_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_mag_calibrated_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -1298,7 +1308,7 @@ int32_t lsm6dsm_mag_calibrated_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer, +int32_t lsm6dsm_fifo_raw_data_get(const stmdev_ctx_t *ctx, uint8_t *buffer, uint8_t len) { int32_t ret; @@ -1329,7 +1339,7 @@ int32_t lsm6dsm_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_mem_bank_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dsm_func_cfg_en_t val) { lsm6dsm_func_cfg_access_t func_cfg_access; @@ -1357,7 +1367,7 @@ int32_t lsm6dsm_mem_bank_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_mem_bank_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dsm_func_cfg_en_t *val) { lsm6dsm_func_cfg_access_t func_cfg_access; @@ -1392,7 +1402,7 @@ int32_t lsm6dsm_mem_bank_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_drdy_pulsed_g_t val) { lsm6dsm_drdy_pulse_cfg_t drdy_pulse_cfg; @@ -1419,7 +1429,7 @@ int32_t lsm6dsm_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_drdy_pulsed_g_t *val) { lsm6dsm_drdy_pulse_cfg_t drdy_pulse_cfg; @@ -1454,7 +1464,7 @@ int32_t lsm6dsm_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsm_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1471,7 +1481,7 @@ int32_t lsm6dsm_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1495,7 +1505,7 @@ int32_t lsm6dsm_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1514,7 +1524,7 @@ int32_t lsm6dsm_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_data_format_set(stmdev_ctx_t *ctx, lsm6dsm_ble_t val) +int32_t lsm6dsm_data_format_set(const stmdev_ctx_t *ctx, lsm6dsm_ble_t val) { lsm6dsm_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1538,7 +1548,7 @@ int32_t lsm6dsm_data_format_set(stmdev_ctx_t *ctx, lsm6dsm_ble_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_data_format_get(stmdev_ctx_t *ctx, lsm6dsm_ble_t *val) +int32_t lsm6dsm_data_format_get(const stmdev_ctx_t *ctx, lsm6dsm_ble_t *val) { lsm6dsm_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1572,7 +1582,7 @@ int32_t lsm6dsm_data_format_get(stmdev_ctx_t *ctx, lsm6dsm_ble_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1597,7 +1607,7 @@ int32_t lsm6dsm_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1616,7 +1626,7 @@ int32_t lsm6dsm_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1640,7 +1650,7 @@ int32_t lsm6dsm_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1659,7 +1669,7 @@ int32_t lsm6dsm_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dsm_st_xl_t val) { lsm6dsm_ctrl5_c_t ctrl5_c; @@ -1684,7 +1694,7 @@ int32_t lsm6dsm_xl_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dsm_st_xl_t *val) { lsm6dsm_ctrl5_c_t ctrl5_c; @@ -1722,7 +1732,7 @@ int32_t lsm6dsm_xl_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dsm_st_g_t val) { lsm6dsm_ctrl5_c_t ctrl5_c; @@ -1747,7 +1757,7 @@ int32_t lsm6dsm_gy_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dsm_st_g_t *val) { lsm6dsm_ctrl5_c_t ctrl5_c; @@ -1799,7 +1809,7 @@ int32_t lsm6dsm_gy_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_ctrl4_c_t ctrl4_c; @@ -1825,7 +1835,7 @@ int32_t lsm6dsm_filter_settling_mask_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_ctrl4_c_t ctrl4_c; @@ -1846,7 +1856,7 @@ int32_t lsm6dsm_filter_settling_mask_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dsm_slope_fds_t val) { lsm6dsm_tap_cfg_t tap_cfg; @@ -1872,7 +1882,7 @@ int32_t lsm6dsm_xl_hp_path_internal_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dsm_slope_fds_t *val) { lsm6dsm_tap_cfg_t tap_cfg; @@ -1920,7 +1930,7 @@ int32_t lsm6dsm_xl_hp_path_internal_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_filter_analog_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_filter_analog_set(const stmdev_ctx_t *ctx, lsm6dsm_bw0_xl_t val) { lsm6dsm_ctrl1_xl_t ctrl1_xl; @@ -1946,7 +1956,7 @@ int32_t lsm6dsm_xl_filter_analog_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_filter_analog_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_filter_analog_get(const stmdev_ctx_t *ctx, lsm6dsm_bw0_xl_t *val) { lsm6dsm_ctrl1_xl_t ctrl1_xl; @@ -1995,7 +2005,7 @@ int32_t lsm6dsm_xl_filter_analog_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsm_lpf1_bw_sel_t val) { lsm6dsm_ctrl1_xl_t ctrl1_xl; @@ -2034,7 +2044,7 @@ int32_t lsm6dsm_xl_lp1_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsm_lpf1_bw_sel_t *val) { lsm6dsm_ctrl1_xl_t ctrl1_xl; @@ -2083,7 +2093,7 @@ int32_t lsm6dsm_xl_lp1_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsm_input_composite_t val) { lsm6dsm_ctrl8_xl_t ctrl8_xl; @@ -2111,7 +2121,7 @@ int32_t lsm6dsm_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsm_input_composite_t *val) { lsm6dsm_ctrl8_xl_t ctrl8_xl; @@ -2181,7 +2191,7 @@ int32_t lsm6dsm_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_xl_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -2205,7 +2215,7 @@ int32_t lsm6dsm_xl_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_xl_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -2224,7 +2234,7 @@ int32_t lsm6dsm_xl_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_hp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsm_hpcf_xl_t val) { lsm6dsm_ctrl8_xl_t ctrl8_xl; @@ -2251,7 +2261,7 @@ int32_t lsm6dsm_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_hp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsm_hpcf_xl_t *val) { lsm6dsm_ctrl8_xl_t ctrl8_xl; @@ -2313,7 +2323,7 @@ int32_t lsm6dsm_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_ui_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_ui_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsm_ui_lpf1_bw_sel_t val) { lsm6dsm_ctrl1_xl_t ctrl1_xl; @@ -2351,7 +2361,7 @@ int32_t lsm6dsm_xl_ui_lp1_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_ui_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_ui_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsm_ui_lpf1_bw_sel_t *val) { lsm6dsm_ctrl1_xl_t ctrl1_xl; @@ -2399,7 +2409,7 @@ int32_t lsm6dsm_xl_ui_lp1_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_ui_slope_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_xl_ui_slope_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -2423,7 +2433,7 @@ int32_t lsm6dsm_xl_ui_slope_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_ui_slope_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_xl_ui_slope_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -2455,7 +2465,7 @@ int32_t lsm6dsm_xl_ui_slope_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_aux_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_aux_lp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsm_filter_xl_conf_ois_t val) { lsm6dsm_ctrl3_ois_t ctrl3_ois; @@ -2493,7 +2503,7 @@ int32_t lsm6dsm_xl_aux_lp_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_xl_aux_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_aux_lp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsm_filter_xl_conf_ois_t *val) { lsm6dsm_ctrl3_ois_t ctrl3_ois; @@ -2549,7 +2559,7 @@ int32_t lsm6dsm_xl_aux_lp_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_gy_band_pass_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_gy_band_pass_set(const stmdev_ctx_t *ctx, lsm6dsm_lpf1_sel_g_t val) { lsm6dsm_ctrl4_c_t ctrl4_c; @@ -2601,7 +2611,7 @@ int32_t lsm6dsm_gy_band_pass_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_gy_band_pass_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_gy_band_pass_get(const stmdev_ctx_t *ctx, lsm6dsm_lpf1_sel_g_t *val) { lsm6dsm_ctrl4_c_t ctrl4_c; @@ -2703,7 +2713,7 @@ int32_t lsm6dsm_gy_band_pass_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_gy_ui_high_pass_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_gy_ui_high_pass_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_ctrl7_g_t ctrl7_g; int32_t ret; @@ -2728,7 +2738,7 @@ int32_t lsm6dsm_gy_ui_high_pass_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_gy_ui_high_pass_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_gy_ui_high_pass_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_ctrl7_g_t ctrl7_g; int32_t ret; @@ -2750,7 +2760,7 @@ int32_t lsm6dsm_gy_ui_high_pass_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_gy_aux_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_gy_aux_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsm_hp_en_ois_t val) { lsm6dsm_ctrl7_g_t ctrl7_g; @@ -2791,7 +2801,7 @@ int32_t lsm6dsm_gy_aux_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_gy_aux_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_gy_aux_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsm_hp_en_ois_t *val) { lsm6dsm_ctrl2_ois_t ctrl2_ois; @@ -2863,7 +2873,7 @@ int32_t lsm6dsm_gy_aux_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_aux_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_status_reg_get(const stmdev_ctx_t *ctx, lsm6dsm_status_spiaux_t *val) { int32_t ret; @@ -2881,7 +2891,7 @@ int32_t lsm6dsm_aux_status_reg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_status_spiaux_t status_spiaux; @@ -2902,7 +2912,7 @@ int32_t lsm6dsm_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_status_spiaux_t status_spiaux; @@ -2923,7 +2933,7 @@ int32_t lsm6dsm_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_status_spiaux_t status_spiaux; @@ -2944,7 +2954,7 @@ int32_t lsm6dsm_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_aux_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_den_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_lvl_ois_t val) { lsm6dsm_int_ois_t int_ois; @@ -2981,7 +2991,7 @@ int32_t lsm6dsm_aux_den_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_aux_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_den_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_lvl_ois_t *val) { lsm6dsm_int_ois_t int_ois; @@ -3026,7 +3036,7 @@ int32_t lsm6dsm_aux_den_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_aux_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_int_ois_t int_ois; int32_t ret; @@ -3051,7 +3061,7 @@ int32_t lsm6dsm_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_int_ois_t int_ois; int32_t ret; @@ -3077,7 +3087,7 @@ int32_t lsm6dsm_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_aux_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_ois_en_spi2_t val) { lsm6dsm_ctrl1_ois_t ctrl1_ois; @@ -3110,7 +3120,7 @@ int32_t lsm6dsm_aux_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_aux_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_ois_en_spi2_t *val) { lsm6dsm_ctrl1_ois_t ctrl1_ois; @@ -3148,7 +3158,7 @@ int32_t lsm6dsm_aux_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_aux_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsm_fs_g_ois_t val) { lsm6dsm_ctrl1_ois_t ctrl1_ois; @@ -3173,7 +3183,7 @@ int32_t lsm6dsm_aux_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_aux_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsm_fs_g_ois_t *val) { lsm6dsm_ctrl1_ois_t ctrl1_ois; @@ -3219,7 +3229,7 @@ int32_t lsm6dsm_aux_gy_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_aux_spi_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_sim_ois_t val) { lsm6dsm_ctrl1_ois_t ctrl1_ois; @@ -3244,7 +3254,7 @@ int32_t lsm6dsm_aux_spi_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_aux_spi_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_sim_ois_t *val) { lsm6dsm_ctrl1_ois_t ctrl1_ois; @@ -3278,7 +3288,7 @@ int32_t lsm6dsm_aux_spi_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_aux_data_format_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_data_format_set(const stmdev_ctx_t *ctx, lsm6dsm_ble_ois_t val) { lsm6dsm_ctrl1_ois_t ctrl1_ois; @@ -3303,7 +3313,7 @@ int32_t lsm6dsm_aux_data_format_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_aux_data_format_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_data_format_get(const stmdev_ctx_t *ctx, lsm6dsm_ble_ois_t *val) { lsm6dsm_ctrl1_ois_t ctrl1_ois; @@ -3341,7 +3351,7 @@ int32_t lsm6dsm_aux_data_format_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_aux_gy_clamp_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_gy_clamp_set(const stmdev_ctx_t *ctx, lsm6dsm_st_ois_clampdis_t val) { lsm6dsm_ctrl3_ois_t ctrl3_ois; @@ -3370,7 +3380,7 @@ int32_t lsm6dsm_aux_gy_clamp_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_aux_gy_clamp_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_gy_clamp_get(const stmdev_ctx_t *ctx, lsm6dsm_st_ois_clampdis_t *val) { lsm6dsm_ctrl3_ois_t ctrl3_ois; @@ -3404,7 +3414,7 @@ int32_t lsm6dsm_aux_gy_clamp_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_aux_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dsm_st_ois_t val) { lsm6dsm_ctrl3_ois_t ctrl3_ois; @@ -3429,7 +3439,7 @@ int32_t lsm6dsm_aux_gy_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_aux_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dsm_st_ois_t *val) { lsm6dsm_ctrl3_ois_t ctrl3_ois; @@ -3467,7 +3477,7 @@ int32_t lsm6dsm_aux_gy_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_aux_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsm_fs_xl_ois_t val) { lsm6dsm_ctrl3_ois_t ctrl3_ois; @@ -3492,7 +3502,7 @@ int32_t lsm6dsm_aux_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_aux_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsm_fs_xl_ois_t *val) { lsm6dsm_ctrl3_ois_t ctrl3_ois; @@ -3534,7 +3544,7 @@ int32_t lsm6dsm_aux_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_aux_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dsm_den_lh_ois_t val) { lsm6dsm_ctrl3_ois_t ctrl3_ois; @@ -3559,7 +3569,7 @@ int32_t lsm6dsm_aux_den_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_aux_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dsm_den_lh_ois_t *val) { lsm6dsm_ctrl3_ois_t ctrl3_ois; @@ -3606,7 +3616,7 @@ int32_t lsm6dsm_aux_den_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsm_sim_t val) +int32_t lsm6dsm_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_sim_t val) { lsm6dsm_ctrl3_c_t ctrl3_c; int32_t ret; @@ -3630,7 +3640,7 @@ int32_t lsm6dsm_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsm_sim_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsm_sim_t *val) +int32_t lsm6dsm_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_sim_t *val) { lsm6dsm_ctrl3_c_t ctrl3_c; int32_t ret; @@ -3663,7 +3673,7 @@ int32_t lsm6dsm_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsm_sim_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_i2c_interface_set(const stmdev_ctx_t *ctx, lsm6dsm_i2c_disable_t val) { lsm6dsm_ctrl4_c_t ctrl4_c; @@ -3688,7 +3698,7 @@ int32_t lsm6dsm_i2c_interface_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_i2c_interface_get(const stmdev_ctx_t *ctx, lsm6dsm_i2c_disable_t *val) { lsm6dsm_ctrl4_c_t ctrl4_c; @@ -3736,7 +3746,7 @@ int32_t lsm6dsm_i2c_interface_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm6dsm_int1_route_t val) { lsm6dsm_master_config_t master_config; @@ -3852,7 +3862,7 @@ int32_t lsm6dsm_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm6dsm_int1_route_t *val) { lsm6dsm_master_config_t master_config; @@ -3908,7 +3918,7 @@ int32_t lsm6dsm_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm6dsm_int2_route_t val) { lsm6dsm_int2_ctrl_t int2_ctrl; @@ -4011,7 +4021,7 @@ int32_t lsm6dsm_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_pin_int2_route_get(const stmdev_ctx_t *ctx, lsm6dsm_int2_route_t *val) { lsm6dsm_int2_ctrl_t int2_ctrl; @@ -4060,7 +4070,7 @@ int32_t lsm6dsm_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsm_pp_od_t val) +int32_t lsm6dsm_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_pp_od_t val) { lsm6dsm_ctrl3_c_t ctrl3_c; int32_t ret; @@ -4084,7 +4094,7 @@ int32_t lsm6dsm_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsm_pp_od_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsm_pp_od_t *val) +int32_t lsm6dsm_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_pp_od_t *val) { lsm6dsm_ctrl3_c_t ctrl3_c; int32_t ret; @@ -4117,7 +4127,7 @@ int32_t lsm6dsm_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsm_pp_od_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_pin_polarity_set(const stmdev_ctx_t *ctx, lsm6dsm_h_lactive_t val) { lsm6dsm_ctrl3_c_t ctrl3_c; @@ -4142,7 +4152,7 @@ int32_t lsm6dsm_pin_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_pin_polarity_get(const stmdev_ctx_t *ctx, lsm6dsm_h_lactive_t *val) { lsm6dsm_ctrl3_c_t ctrl3_c; @@ -4176,7 +4186,7 @@ int32_t lsm6dsm_pin_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_ctrl4_c_t ctrl4_c; int32_t ret; @@ -4200,7 +4210,7 @@ int32_t lsm6dsm_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_ctrl4_c_t ctrl4_c; int32_t ret; @@ -4219,7 +4229,7 @@ int32_t lsm6dsm_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_int_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_int_notification_set(const stmdev_ctx_t *ctx, lsm6dsm_lir_t val) { lsm6dsm_tap_cfg_t tap_cfg; @@ -4244,7 +4254,7 @@ int32_t lsm6dsm_int_notification_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_int_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_int_notification_get(const stmdev_ctx_t *ctx, lsm6dsm_lir_t *val) { lsm6dsm_tap_cfg_t tap_cfg; @@ -4291,7 +4301,7 @@ int32_t lsm6dsm_int_notification_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_wake_up_ths_t wake_up_ths; int32_t ret; @@ -4317,7 +4327,7 @@ int32_t lsm6dsm_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_wake_up_ths_t wake_up_ths; int32_t ret; @@ -4337,7 +4347,7 @@ int32_t lsm6dsm_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_wake_up_dur_t wake_up_dur; int32_t ret; @@ -4363,7 +4373,7 @@ int32_t lsm6dsm_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_wake_up_dur_t wake_up_dur; int32_t ret; @@ -4396,7 +4406,7 @@ int32_t lsm6dsm_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_ctrl4_c_t ctrl4_c; int32_t ret; @@ -4420,7 +4430,7 @@ int32_t lsm6dsm_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_ctrl4_c_t ctrl4_c; int32_t ret; @@ -4439,7 +4449,7 @@ int32_t lsm6dsm_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_act_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_act_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_inact_en_t val) { lsm6dsm_tap_cfg_t tap_cfg; @@ -4464,7 +4474,7 @@ int32_t lsm6dsm_act_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_act_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_act_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_inact_en_t *val) { lsm6dsm_tap_cfg_t tap_cfg; @@ -4506,7 +4516,7 @@ int32_t lsm6dsm_act_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_wake_up_dur_t wake_up_dur; int32_t ret; @@ -4532,7 +4542,7 @@ int32_t lsm6dsm_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_wake_up_dur_t wake_up_dur; int32_t ret; @@ -4565,7 +4575,7 @@ int32_t lsm6dsm_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_tap_src_get(stmdev_ctx_t *ctx, lsm6dsm_tap_src_t *val) +int32_t lsm6dsm_tap_src_get(const stmdev_ctx_t *ctx, lsm6dsm_tap_src_t *val) { int32_t ret; @@ -4581,7 +4591,7 @@ int32_t lsm6dsm_tap_src_get(stmdev_ctx_t *ctx, lsm6dsm_tap_src_t *val) * @param val Change the values of tap_z_en in reg TAP_CFG * */ -int32_t lsm6dsm_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_tap_cfg_t tap_cfg; int32_t ret; @@ -4605,7 +4615,7 @@ int32_t lsm6dsm_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_tap_cfg_t tap_cfg; @@ -4625,7 +4635,7 @@ int32_t lsm6dsm_tap_detection_on_z_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_tap_cfg_t tap_cfg; int32_t ret; @@ -4649,7 +4659,7 @@ int32_t lsm6dsm_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_tap_cfg_t tap_cfg; @@ -4669,7 +4679,7 @@ int32_t lsm6dsm_tap_detection_on_y_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_tap_cfg_t tap_cfg; int32_t ret; @@ -4693,7 +4703,7 @@ int32_t lsm6dsm_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_tap_cfg_t tap_cfg; @@ -4713,7 +4723,7 @@ int32_t lsm6dsm_tap_detection_on_x_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -4739,7 +4749,7 @@ int32_t lsm6dsm_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -4764,7 +4774,7 @@ int32_t lsm6dsm_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_int_dur2_t int_dur2; int32_t ret; @@ -4793,7 +4803,7 @@ int32_t lsm6dsm_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_int_dur2_t int_dur2; int32_t ret; @@ -4817,7 +4827,7 @@ int32_t lsm6dsm_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_int_dur2_t int_dur2; int32_t ret; @@ -4846,7 +4856,7 @@ int32_t lsm6dsm_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_int_dur2_t int_dur2; int32_t ret; @@ -4871,7 +4881,7 @@ int32_t lsm6dsm_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_int_dur2_t int_dur2; int32_t ret; @@ -4901,7 +4911,7 @@ int32_t lsm6dsm_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_int_dur2_t int_dur2; int32_t ret; @@ -4921,7 +4931,7 @@ int32_t lsm6dsm_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_tap_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_single_double_tap_t val) { lsm6dsm_wake_up_ths_t wake_up_ths; @@ -4949,7 +4959,7 @@ int32_t lsm6dsm_tap_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_tap_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_single_double_tap_t *val) { lsm6dsm_wake_up_ths_t wake_up_ths; @@ -4998,7 +5008,7 @@ int32_t lsm6dsm_tap_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_6d_feed_data_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_6d_feed_data_set(const stmdev_ctx_t *ctx, lsm6dsm_low_pass_on_6d_t val) { lsm6dsm_ctrl8_xl_t ctrl8_xl; @@ -5023,7 +5033,7 @@ int32_t lsm6dsm_6d_feed_data_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_6d_feed_data_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_6d_feed_data_get(const stmdev_ctx_t *ctx, lsm6dsm_low_pass_on_6d_t *val) { lsm6dsm_ctrl8_xl_t ctrl8_xl; @@ -5057,7 +5067,7 @@ int32_t lsm6dsm_6d_feed_data_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_6d_threshold_set(const stmdev_ctx_t *ctx, lsm6dsm_sixd_ths_t val) { lsm6dsm_tap_ths_6d_t tap_ths_6d; @@ -5084,7 +5094,7 @@ int32_t lsm6dsm_6d_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_6d_threshold_get(const stmdev_ctx_t *ctx, lsm6dsm_sixd_ths_t *val) { lsm6dsm_tap_ths_6d_t tap_ths_6d; @@ -5127,7 +5137,7 @@ int32_t lsm6dsm_6d_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -5153,7 +5163,7 @@ int32_t lsm6dsm_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -5186,7 +5196,7 @@ int32_t lsm6dsm_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_wake_up_dur_t wake_up_dur; lsm6dsm_free_fall_t free_fall; @@ -5224,7 +5234,7 @@ int32_t lsm6dsm_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_wake_up_dur_t wake_up_dur; lsm6dsm_free_fall_t free_fall; @@ -5251,7 +5261,7 @@ int32_t lsm6dsm_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_ff_threshold_set(const stmdev_ctx_t *ctx, lsm6dsm_ff_ths_t val) { lsm6dsm_free_fall_t free_fall; @@ -5276,7 +5286,7 @@ int32_t lsm6dsm_ff_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_ff_threshold_get(const stmdev_ctx_t *ctx, lsm6dsm_ff_ths_t *val) { lsm6dsm_free_fall_t free_fall; @@ -5347,7 +5357,7 @@ int32_t lsm6dsm_ff_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsm_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val) { lsm6dsm_fifo_ctrl1_t fifo_ctrl1; lsm6dsm_fifo_ctrl2_t fifo_ctrl2; @@ -5381,7 +5391,7 @@ int32_t lsm6dsm_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsm_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dsm_fifo_ctrl1_t fifo_ctrl1; lsm6dsm_fifo_ctrl2_t fifo_ctrl2; @@ -5411,7 +5421,7 @@ int32_t lsm6dsm_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsm_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dsm_fifo_status1_t fifo_status1; lsm6dsm_fifo_status2_t fifo_status2; @@ -5439,7 +5449,7 @@ int32_t lsm6dsm_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_fifo_status2_t fifo_status2; int32_t ret; @@ -5459,7 +5469,7 @@ int32_t lsm6dsm_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_over_run_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_fifo_over_run_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_fifo_status2_t fifo_status2; int32_t ret; @@ -5480,7 +5490,7 @@ int32_t lsm6dsm_fifo_over_run_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsm_fifo_pattern_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dsm_fifo_status3_t fifo_status3; lsm6dsm_fifo_status4_t fifo_status4; @@ -5508,7 +5518,7 @@ int32_t lsm6dsm_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_fifo_temp_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -5534,7 +5544,7 @@ int32_t lsm6dsm_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_fifo_temp_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -5555,7 +5565,7 @@ int32_t lsm6dsm_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_write_trigger_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_write_trigger_set(const stmdev_ctx_t *ctx, lsm6dsm_trigger_fifo_t val) { lsm6dsm_fifo_ctrl2_t fifo_ctrl2; @@ -5597,7 +5607,7 @@ int32_t lsm6dsm_fifo_write_trigger_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_write_trigger_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_write_trigger_get(const stmdev_ctx_t *ctx, lsm6dsm_trigger_fifo_t *val) { lsm6dsm_fifo_ctrl2_t fifo_ctrl2; @@ -5612,8 +5622,8 @@ int32_t lsm6dsm_fifo_write_trigger_get(stmdev_ctx_t *ctx, ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG, (uint8_t *)&master_config, 1); - switch ((fifo_ctrl2.timer_pedo_fifo_drdy << 1) + - fifo_ctrl2. timer_pedo_fifo_drdy) + switch ((master_config.data_valid_sel_fifo << 1) + + fifo_ctrl2.timer_pedo_fifo_drdy) { case LSM6DSM_TRG_XL_GY_DRDY: *val = LSM6DSM_TRG_XL_GY_DRDY; @@ -5645,7 +5655,7 @@ int32_t lsm6dsm_fifo_write_trigger_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_pedo_and_timestamp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_pedo_and_timestamp_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_fifo_ctrl2_t fifo_ctrl2; @@ -5673,7 +5683,7 @@ int32_t lsm6dsm_fifo_pedo_and_timestamp_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_pedo_and_timestamp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_pedo_and_timestamp_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_fifo_ctrl2_t fifo_ctrl2; @@ -5695,7 +5705,7 @@ int32_t lsm6dsm_fifo_pedo_and_timestamp_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_xl_batch_set(const stmdev_ctx_t *ctx, lsm6dsm_dec_fifo_xl_t val) { lsm6dsm_fifo_ctrl3_t fifo_ctrl3; @@ -5723,7 +5733,7 @@ int32_t lsm6dsm_fifo_xl_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_xl_batch_get(const stmdev_ctx_t *ctx, lsm6dsm_dec_fifo_xl_t *val) { lsm6dsm_fifo_ctrl3_t fifo_ctrl3; @@ -5783,7 +5793,7 @@ int32_t lsm6dsm_fifo_xl_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_gy_batch_set(const stmdev_ctx_t *ctx, lsm6dsm_dec_fifo_gyro_t val) { lsm6dsm_fifo_ctrl3_t fifo_ctrl3; @@ -5811,7 +5821,7 @@ int32_t lsm6dsm_fifo_gy_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_gy_batch_get(const stmdev_ctx_t *ctx, lsm6dsm_dec_fifo_gyro_t *val) { lsm6dsm_fifo_ctrl3_t fifo_ctrl3; @@ -5871,7 +5881,7 @@ int32_t lsm6dsm_fifo_gy_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_dataset_3_batch_set(const stmdev_ctx_t *ctx, lsm6dsm_dec_ds3_fifo_t val) { lsm6dsm_fifo_ctrl4_t fifo_ctrl4; @@ -5899,7 +5909,7 @@ int32_t lsm6dsm_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_dataset_3_batch_get(const stmdev_ctx_t *ctx, lsm6dsm_dec_ds3_fifo_t *val) { lsm6dsm_fifo_ctrl4_t fifo_ctrl4; @@ -5959,7 +5969,7 @@ int32_t lsm6dsm_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_dataset_4_batch_set(const stmdev_ctx_t *ctx, lsm6dsm_dec_ds4_fifo_t val) { lsm6dsm_fifo_ctrl4_t fifo_ctrl4; @@ -5987,7 +5997,7 @@ int32_t lsm6dsm_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_dataset_4_batch_get(const stmdev_ctx_t *ctx, lsm6dsm_dec_ds4_fifo_t *val) { lsm6dsm_fifo_ctrl4_t fifo_ctrl4; @@ -6046,7 +6056,7 @@ int32_t lsm6dsm_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_xl_gy_8bit_format_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_fifo_ctrl4_t fifo_ctrl4; @@ -6073,7 +6083,7 @@ int32_t lsm6dsm_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_xl_gy_8bit_format_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_fifo_ctrl4_t fifo_ctrl4; @@ -6095,7 +6105,7 @@ int32_t lsm6dsm_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_fifo_ctrl4_t fifo_ctrl4; int32_t ret; @@ -6122,7 +6132,7 @@ int32_t lsm6dsm_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_fifo_ctrl4_t fifo_ctrl4; int32_t ret; @@ -6142,7 +6152,7 @@ int32_t lsm6dsm_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_fifo_mode_t val) { lsm6dsm_fifo_ctrl5_t fifo_ctrl5; @@ -6169,7 +6179,7 @@ int32_t lsm6dsm_fifo_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_fifo_mode_t *val) { lsm6dsm_fifo_ctrl5_t fifo_ctrl5; @@ -6216,7 +6226,7 @@ int32_t lsm6dsm_fifo_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsm_odr_fifo_t val) { lsm6dsm_fifo_ctrl5_t fifo_ctrl5; @@ -6243,7 +6253,7 @@ int32_t lsm6dsm_fifo_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_fifo_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsm_odr_fifo_t *val) { lsm6dsm_fifo_ctrl5_t fifo_ctrl5; @@ -6327,7 +6337,7 @@ int32_t lsm6dsm_fifo_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dsm_den_lh_t val) { lsm6dsm_ctrl5_c_t ctrl5_c; @@ -6352,7 +6362,7 @@ int32_t lsm6dsm_den_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dsm_den_lh_t *val) { lsm6dsm_ctrl5_c_t ctrl5_c; @@ -6386,7 +6396,7 @@ int32_t lsm6dsm_den_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_den_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_den_mode_t val) { lsm6dsm_ctrl6_c_t ctrl6_c; @@ -6411,7 +6421,7 @@ int32_t lsm6dsm_den_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_den_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_den_mode_t *val) { lsm6dsm_ctrl6_c_t ctrl6_c; @@ -6454,7 +6464,7 @@ int32_t lsm6dsm_den_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_den_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_den_enable_set(const stmdev_ctx_t *ctx, lsm6dsm_den_xl_en_t val) { lsm6dsm_ctrl4_c_t ctrl4_c; @@ -6492,7 +6502,7 @@ int32_t lsm6dsm_den_enable_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_den_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_den_enable_get(const stmdev_ctx_t *ctx, lsm6dsm_den_xl_en_t *val) { lsm6dsm_ctrl4_c_t ctrl4_c; @@ -6536,7 +6546,7 @@ int32_t lsm6dsm_den_enable_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -6560,7 +6570,7 @@ int32_t lsm6dsm_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -6579,7 +6589,7 @@ int32_t lsm6dsm_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -6603,7 +6613,7 @@ int32_t lsm6dsm_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -6622,7 +6632,7 @@ int32_t lsm6dsm_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -6646,7 +6656,7 @@ int32_t lsm6dsm_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -6677,7 +6687,7 @@ int32_t lsm6dsm_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_pedo_step_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_ctrl10_c_t ctrl10_c; int32_t ret; @@ -6701,7 +6711,7 @@ int32_t lsm6dsm_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_pedo_step_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_ctrl10_c_t ctrl10_c; int32_t ret; @@ -6720,7 +6730,7 @@ int32_t lsm6dsm_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_ctrl10_c_t ctrl10_c; int32_t ret; @@ -6750,7 +6760,7 @@ int32_t lsm6dsm_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_ctrl10_c_t ctrl10_c; int32_t ret; @@ -6770,7 +6780,7 @@ int32_t lsm6dsm_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_pedo_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_config_pedo_ths_min_t config_pedo_ths_min; int32_t ret; @@ -6806,7 +6816,7 @@ int32_t lsm6dsm_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_pedo_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_config_pedo_ths_min_t config_pedo_ths_min; int32_t ret; @@ -6837,7 +6847,7 @@ int32_t lsm6dsm_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_pedo_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_pedo_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsm_pedo_fs_t val) { lsm6dsm_config_pedo_ths_min_t config_pedo_ths_min; @@ -6875,7 +6885,7 @@ int32_t lsm6dsm_pedo_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_pedo_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_pedo_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsm_pedo_fs_t *val) { lsm6dsm_config_pedo_ths_min_t config_pedo_ths_min; @@ -6920,7 +6930,7 @@ int32_t lsm6dsm_pedo_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_pedo_debounce_steps_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_pedo_deb_reg_t pedo_deb_reg; @@ -6957,7 +6967,7 @@ int32_t lsm6dsm_pedo_debounce_steps_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_pedo_debounce_steps_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_pedo_deb_reg_t pedo_deb_reg; @@ -6990,7 +7000,7 @@ int32_t lsm6dsm_pedo_debounce_steps_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_pedo_timeout_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_pedo_deb_reg_t pedo_deb_reg; int32_t ret; @@ -7028,7 +7038,7 @@ int32_t lsm6dsm_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_pedo_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_pedo_deb_reg_t pedo_deb_reg; int32_t ret; @@ -7058,7 +7068,7 @@ int32_t lsm6dsm_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_pedo_steps_period_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_pedo_steps_period_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -7086,7 +7096,7 @@ int32_t lsm6dsm_pedo_steps_period_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_pedo_steps_period_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_pedo_steps_period_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -7127,7 +7137,7 @@ int32_t lsm6dsm_pedo_steps_period_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_ctrl10_c_t ctrl10_c; int32_t ret; @@ -7156,7 +7166,7 @@ int32_t lsm6dsm_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_ctrl10_c_t ctrl10_c; int32_t ret; @@ -7175,7 +7185,7 @@ int32_t lsm6dsm_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsm_motion_threshold_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -7202,7 +7212,7 @@ int32_t lsm6dsm_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsm_motion_threshold_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -7242,7 +7252,7 @@ int32_t lsm6dsm_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_ctrl10_c_t ctrl10_c; int32_t ret; @@ -7272,7 +7282,7 @@ int32_t lsm6dsm_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_ctrl10_c_t ctrl10_c; int32_t ret; @@ -7291,7 +7301,7 @@ int32_t lsm6dsm_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_wrist_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_wrist_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_ctrl10_c_t ctrl10_c; int32_t ret; @@ -7321,7 +7331,7 @@ int32_t lsm6dsm_wrist_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_wrist_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_wrist_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_ctrl10_c_t ctrl10_c; int32_t ret; @@ -7342,7 +7352,7 @@ int32_t lsm6dsm_wrist_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_tilt_latency_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsm_tilt_latency_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -7371,7 +7381,7 @@ int32_t lsm6dsm_tilt_latency_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_tilt_latency_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsm_tilt_latency_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -7400,7 +7410,7 @@ int32_t lsm6dsm_tilt_latency_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_tilt_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsm_tilt_threshold_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -7429,7 +7439,7 @@ int32_t lsm6dsm_tilt_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_tilt_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsm_tilt_threshold_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -7456,7 +7466,7 @@ int32_t lsm6dsm_tilt_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_tilt_src_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_tilt_src_set(const stmdev_ctx_t *ctx, lsm6dsm_a_wrist_tilt_mask_t *val) { int32_t ret; @@ -7485,7 +7495,7 @@ int32_t lsm6dsm_tilt_src_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_tilt_src_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_tilt_src_get(const stmdev_ctx_t *ctx, lsm6dsm_a_wrist_tilt_mask_t *val) { int32_t ret; @@ -7527,7 +7537,7 @@ int32_t lsm6dsm_tilt_src_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -7551,7 +7561,7 @@ int32_t lsm6dsm_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -7570,7 +7580,7 @@ int32_t lsm6dsm_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_mag_hard_iron_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_master_config_t master_config; lsm6dsm_ctrl10_c_t ctrl10_c; @@ -7613,7 +7623,7 @@ int32_t lsm6dsm_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_mag_hard_iron_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_master_config_t master_config; int32_t ret; @@ -7634,7 +7644,7 @@ int32_t lsm6dsm_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_mag_soft_iron_mat_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -7663,7 +7673,7 @@ int32_t lsm6dsm_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_mag_soft_iron_mat_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_mag_soft_iron_mat_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -7692,7 +7702,7 @@ int32_t lsm6dsm_mag_soft_iron_mat_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsm_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -7727,7 +7737,7 @@ int32_t lsm6dsm_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsm_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -7774,7 +7784,7 @@ int32_t lsm6dsm_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_func_en_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_func_en_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_ctrl10_c_t ctrl10_c; int32_t ret; @@ -7799,7 +7809,7 @@ int32_t lsm6dsm_func_en_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_sh_sync_sens_frame_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_sensor_sync_time_frame_t sensor_sync_time_frame; int32_t ret; @@ -7826,7 +7836,7 @@ int32_t lsm6dsm_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_sync_sens_frame_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_sensor_sync_time_frame_t sensor_sync_time_frame; @@ -7847,7 +7857,7 @@ int32_t lsm6dsm_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_sync_sens_ratio_set(const stmdev_ctx_t *ctx, lsm6dsm_rr_t val) { lsm6dsm_sensor_sync_res_ratio_t sensor_sync_res_ratio; @@ -7874,7 +7884,7 @@ int32_t lsm6dsm_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_sync_sens_ratio_get(const stmdev_ctx_t *ctx, lsm6dsm_rr_t *val) { lsm6dsm_sensor_sync_res_ratio_t sensor_sync_res_ratio; @@ -7917,7 +7927,7 @@ int32_t lsm6dsm_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_master_config_t master_config; int32_t ret; @@ -7943,7 +7953,7 @@ int32_t lsm6dsm_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_master_config_t master_config; int32_t ret; @@ -7963,7 +7973,7 @@ int32_t lsm6dsm_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_master_config_t master_config; int32_t ret; @@ -7989,7 +7999,7 @@ int32_t lsm6dsm_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_master_config_t master_config; int32_t ret; @@ -8009,7 +8019,7 @@ int32_t lsm6dsm_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_pull_up_en_t val) { lsm6dsm_master_config_t master_config; @@ -8036,7 +8046,7 @@ int32_t lsm6dsm_sh_pin_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_pull_up_en_t *val) { lsm6dsm_master_config_t master_config; @@ -8071,7 +8081,7 @@ int32_t lsm6dsm_sh_pin_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_syncro_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_start_config_t val) { lsm6dsm_master_config_t master_config; @@ -8098,7 +8108,7 @@ int32_t lsm6dsm_sh_syncro_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_syncro_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_start_config_t *val) { lsm6dsm_master_config_t master_config; @@ -8133,7 +8143,7 @@ int32_t lsm6dsm_sh_syncro_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_sh_drdy_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_master_config_t master_config; int32_t ret; @@ -8159,7 +8169,7 @@ int32_t lsm6dsm_sh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_sh_drdy_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_master_config_t master_config; int32_t ret; @@ -8179,7 +8189,7 @@ int32_t lsm6dsm_sh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_read_data_raw_get(const stmdev_ctx_t *ctx, lsm6dsm_emb_sh_read_t *val) { int32_t ret; @@ -8205,7 +8215,7 @@ int32_t lsm6dsm_sh_read_data_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_sh_cmd_sens_sync_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_master_cmd_code_t master_cmd_code; int32_t ret; @@ -8232,7 +8242,7 @@ int32_t lsm6dsm_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_sh_cmd_sens_sync_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_master_cmd_code_t master_cmd_code; int32_t ret; @@ -8253,7 +8263,7 @@ int32_t lsm6dsm_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_spi_sync_error_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsm_sh_spi_sync_error_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsm_sens_sync_spi_error_code_t sens_sync_spi_error_code; int32_t ret; @@ -8280,7 +8290,7 @@ int32_t lsm6dsm_sh_spi_sync_error_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_spi_sync_error_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsm_sh_spi_sync_error_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsm_sens_sync_spi_error_code_t sens_sync_spi_error_code; int32_t ret; @@ -8300,7 +8310,7 @@ int32_t lsm6dsm_sh_spi_sync_error_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_num_of_dev_connected_set(const stmdev_ctx_t *ctx, lsm6dsm_aux_sens_on_t val) { lsm6dsm_slave0_config_t slave0_config; @@ -8337,7 +8347,7 @@ int32_t lsm6dsm_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_num_of_dev_connected_get(const stmdev_ctx_t *ctx, lsm6dsm_aux_sens_on_t *val) { lsm6dsm_slave0_config_t slave0_config; @@ -8393,7 +8403,7 @@ int32_t lsm6dsm_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_cfg_write(const stmdev_ctx_t *ctx, lsm6dsm_sh_cfg_write_t *val) { lsm6dsm_slv0_add_t slv0_add; @@ -8439,7 +8449,7 @@ int32_t lsm6dsm_sh_cfg_write(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_slv0_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, lsm6dsm_sh_cfg_read_t *val) { lsm6dsm_slave0_config_t slave0_config; @@ -8493,7 +8503,7 @@ int32_t lsm6dsm_sh_slv0_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_slv1_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, lsm6dsm_sh_cfg_read_t *val) { lsm6dsm_slave1_config_t slave1_config; @@ -8547,7 +8557,7 @@ int32_t lsm6dsm_sh_slv1_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_slv2_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, lsm6dsm_sh_cfg_read_t *val) { lsm6dsm_slv2_add_t slv2_add; @@ -8601,7 +8611,7 @@ int32_t lsm6dsm_sh_slv2_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_slv3_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, lsm6dsm_sh_cfg_read_t *val) { lsm6dsm_slave3_config_t slave3_config; @@ -8653,7 +8663,7 @@ int32_t lsm6dsm_sh_slv3_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_slave_0_dec_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_slave_0_dec_set(const stmdev_ctx_t *ctx, lsm6dsm_slave0_rate_t val) { lsm6dsm_slave0_config_t slave0_config; @@ -8691,7 +8701,7 @@ int32_t lsm6dsm_sh_slave_0_dec_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_slave_0_dec_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_slave_0_dec_get(const stmdev_ctx_t *ctx, lsm6dsm_slave0_rate_t *val) { lsm6dsm_slave0_config_t slave0_config; @@ -8747,7 +8757,7 @@ int32_t lsm6dsm_sh_slave_0_dec_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_write_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_write_once_t val) { lsm6dsm_slave1_config_t slave1_config; @@ -8787,7 +8797,7 @@ int32_t lsm6dsm_sh_write_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_write_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_write_once_t *val) { lsm6dsm_slave1_config_t slave1_config; @@ -8833,7 +8843,7 @@ int32_t lsm6dsm_sh_write_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_slave_1_dec_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_slave_1_dec_set(const stmdev_ctx_t *ctx, lsm6dsm_slave1_rate_t val) { lsm6dsm_slave1_config_t slave1_config; @@ -8870,7 +8880,7 @@ int32_t lsm6dsm_sh_slave_1_dec_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_slave_1_dec_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_slave_1_dec_get(const stmdev_ctx_t *ctx, lsm6dsm_slave1_rate_t *val) { lsm6dsm_slave1_config_t slave1_config; @@ -8924,7 +8934,7 @@ int32_t lsm6dsm_sh_slave_1_dec_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_slave_2_dec_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_slave_2_dec_set(const stmdev_ctx_t *ctx, lsm6dsm_slave2_rate_t val) { lsm6dsm_slave2_config_t slave2_config; @@ -8962,7 +8972,7 @@ int32_t lsm6dsm_sh_slave_2_dec_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_slave_2_dec_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_slave_2_dec_get(const stmdev_ctx_t *ctx, lsm6dsm_slave2_rate_t *val) { lsm6dsm_slave2_config_t slave2_config; @@ -9016,7 +9026,7 @@ int32_t lsm6dsm_sh_slave_2_dec_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_slave_3_dec_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_slave_3_dec_set(const stmdev_ctx_t *ctx, lsm6dsm_slave3_rate_t val) { lsm6dsm_slave3_config_t slave3_config; @@ -9054,7 +9064,7 @@ int32_t lsm6dsm_sh_slave_3_dec_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsm_sh_slave_3_dec_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_slave_3_dec_get(const stmdev_ctx_t *ctx, lsm6dsm_slave3_rate_t *val) { lsm6dsm_slave3_config_t slave3_config; diff --git a/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.h b/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.h index 3ea21ee9..22aa1fa5 100644 --- a/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.h +++ b/sensor/stmemsc/lsm6dsm_STdC/driver/lsm6dsm_reg.h @@ -186,11 +186,9 @@ typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t not_used_01 : 5; -uint8_t func_cfg_en : - 3; /* func_cfg_en + func_cfg_en_b */ + uint8_t func_cfg_en : 3; /* func_cfg_en + func_cfg_en_b */ #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN -uint8_t func_cfg_en : - 3; /* func_cfg_en + func_cfg_en_b */ + uint8_t func_cfg_en : 3; /* func_cfg_en + func_cfg_en_b */ uint8_t not_used_01 : 5; #endif /* DRV_BYTE_ORDER */ } lsm6dsm_func_cfg_access_t; @@ -452,11 +450,9 @@ typedef struct uint8_t not_used_01 : 1; uint8_t usr_off_w : 1; uint8_t xl_hm_mode : 1; -uint8_t den_mode : - 3; /* trig_en + lvl_en + lvl2_en */ + uint8_t den_mode : 3; /* trig_en + lvl_en + lvl2_en */ #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN -uint8_t den_mode : - 3; /* trig_en + lvl_en + lvl2_en */ + uint8_t den_mode : 3; /* trig_en + lvl_en + lvl2_en */ uint8_t xl_hm_mode : 1; uint8_t usr_off_w : 1; uint8_t not_used_01 : 1; @@ -1009,21 +1005,18 @@ typedef struct #define LSM6DSM_FIFO_STATUS3 0x3CU typedef struct { -uint8_t fifo_pattern : - 8; /* + FIFO_STATUS4(fifo_pattern) */ + uint8_t fifo_pattern : 8; /* + FIFO_STATUS4(fifo_pattern) */ } lsm6dsm_fifo_status3_t; #define LSM6DSM_FIFO_STATUS4 0x3DU typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN -uint8_t fifo_pattern : - 2; /* + FIFO_STATUS3(fifo_pattern) */ + uint8_t fifo_pattern : 2; /* + FIFO_STATUS3(fifo_pattern) */ uint8_t not_used_01 : 6; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN uint8_t not_used_01 : 6; -uint8_t fifo_pattern : - 2; /* + FIFO_STATUS3(fifo_pattern) */ + uint8_t fifo_pattern : 2; /* + FIFO_STATUS3(fifo_pattern) */ #endif /* DRV_BYTE_ORDER */ } lsm6dsm_fifo_status4_t; @@ -1804,10 +1797,10 @@ typedef union * them with a custom implementation. */ -int32_t lsm6dsm_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm6dsm_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lsm6dsm_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm6dsm_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -1831,9 +1824,9 @@ typedef enum LSM6DSM_4g = 2, LSM6DSM_8g = 3, } lsm6dsm_fs_xl_t; -int32_t lsm6dsm_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsm_fs_xl_t val); -int32_t lsm6dsm_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsm_fs_xl_t *val); typedef enum @@ -1851,9 +1844,9 @@ typedef enum LSM6DSM_XL_ODR_6k66Hz = 10, LSM6DSM_XL_ODR_1Hz6 = 11, } lsm6dsm_odr_xl_t; -int32_t lsm6dsm_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsm_odr_xl_t val); -int32_t lsm6dsm_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsm_odr_xl_t *val); typedef enum @@ -1864,9 +1857,9 @@ typedef enum LSM6DSM_1000dps = 4, LSM6DSM_2000dps = 6, } lsm6dsm_fs_g_t; -int32_t lsm6dsm_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsm_fs_g_t val); -int32_t lsm6dsm_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsm_fs_g_t *val); typedef enum @@ -1883,13 +1876,13 @@ typedef enum LSM6DSM_GY_ODR_3k33Hz = 9, LSM6DSM_GY_ODR_6k66Hz = 10, } lsm6dsm_odr_g_t; -int32_t lsm6dsm_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_gy_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsm_odr_g_t val); -int32_t lsm6dsm_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsm_odr_g_t *val); -int32_t lsm6dsm_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -1897,9 +1890,9 @@ typedef enum LSM6DSM_LSb_1mg = 0, LSM6DSM_LSb_16mg = 1, } lsm6dsm_usr_off_w_t; -int32_t lsm6dsm_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_offset_weight_set(const stmdev_ctx_t *ctx, lsm6dsm_usr_off_w_t val); -int32_t lsm6dsm_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_offset_weight_get(const stmdev_ctx_t *ctx, lsm6dsm_usr_off_w_t *val); typedef enum @@ -1907,9 +1900,9 @@ typedef enum LSM6DSM_XL_HIGH_PERFORMANCE = 0, LSM6DSM_XL_NORMAL = 1, } lsm6dsm_xl_hm_mode_t; -int32_t lsm6dsm_xl_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_power_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_xl_hm_mode_t val); -int32_t lsm6dsm_xl_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_power_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_xl_hm_mode_t *val); typedef enum @@ -1917,9 +1910,9 @@ typedef enum LSM6DSM_STAT_RND_DISABLE = 0, LSM6DSM_STAT_RND_ENABLE = 1, } lsm6dsm_rounding_status_t; -int32_t lsm6dsm_rounding_on_status_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_rounding_on_status_set(const stmdev_ctx_t *ctx, lsm6dsm_rounding_status_t val); -int32_t lsm6dsm_rounding_on_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_rounding_on_status_get(const stmdev_ctx_t *ctx, lsm6dsm_rounding_status_t *val); typedef enum @@ -1927,9 +1920,9 @@ typedef enum LSM6DSM_GY_HIGH_PERFORMANCE = 0, LSM6DSM_GY_NORMAL = 1, } lsm6dsm_g_hm_mode_t; -int32_t lsm6dsm_gy_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_gy_power_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_g_hm_mode_t val); -int32_t lsm6dsm_gy_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_gy_power_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_g_hm_mode_t *val); typedef struct @@ -1943,34 +1936,34 @@ typedef struct lsm6dsm_wrist_tilt_ia_t wrist_tilt_ia; lsm6dsm_a_wrist_tilt_mask_t a_wrist_tilt_mask; } lsm6dsm_all_sources_t; -int32_t lsm6dsm_all_sources_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_all_sources_get(const stmdev_ctx_t *ctx, lsm6dsm_all_sources_t *val); -int32_t lsm6dsm_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_status_reg_get(const stmdev_ctx_t *ctx, lsm6dsm_status_reg_t *val); -int32_t lsm6dsm_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsm_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsm_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsm_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsm_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSM_LSB_6ms4 = 0, LSM6DSM_LSB_25us = 1, } lsm6dsm_timer_hr_t; -int32_t lsm6dsm_timestamp_res_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_timestamp_res_set(const stmdev_ctx_t *ctx, lsm6dsm_timer_hr_t val); -int32_t lsm6dsm_timestamp_res_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_timestamp_res_get(const stmdev_ctx_t *ctx, lsm6dsm_timer_hr_t *val); typedef enum @@ -1984,19 +1977,19 @@ typedef enum LSM6DSM_ROUND_GY_XL_SH1_TO_SH12 = 6, LSM6DSM_ROUND_GY_XL_SH1_TO_SH6 = 7, } lsm6dsm_rounding_t; -int32_t lsm6dsm_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_rounding_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_rounding_t val); -int32_t lsm6dsm_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_rounding_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_rounding_t *val); -int32_t lsm6dsm_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsm_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsm_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsm_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsm_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsm_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsm_mag_calibrated_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_mag_calibrated_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsm_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer, +int32_t lsm6dsm_fifo_raw_data_get(const stmdev_ctx_t *ctx, uint8_t *buffer, uint8_t len); typedef enum @@ -2005,9 +1998,9 @@ typedef enum LSM6DSM_BANK_A = 4, LSM6DSM_BANK_B = 5, } lsm6dsm_func_cfg_en_t; -int32_t lsm6dsm_mem_bank_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dsm_func_cfg_en_t val); -int32_t lsm6dsm_mem_bank_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dsm_func_cfg_en_t *val); typedef enum @@ -2015,29 +2008,29 @@ typedef enum LSM6DSM_DRDY_LATCHED = 0, LSM6DSM_DRDY_PULSED = 1, } lsm6dsm_drdy_pulsed_g_t; -int32_t lsm6dsm_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_drdy_pulsed_g_t val); -int32_t lsm6dsm_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_drdy_pulsed_g_t *val); -int32_t lsm6dsm_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsm_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsm_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSM_LSB_AT_LOW_ADD = 0, LSM6DSM_MSB_AT_LOW_ADD = 1, } lsm6dsm_ble_t; -int32_t lsm6dsm_data_format_set(stmdev_ctx_t *ctx, lsm6dsm_ble_t val); -int32_t lsm6dsm_data_format_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_data_format_set(const stmdev_ctx_t *ctx, lsm6dsm_ble_t val); +int32_t lsm6dsm_data_format_get(const stmdev_ctx_t *ctx, lsm6dsm_ble_t *val); -int32_t lsm6dsm_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2045,9 +2038,9 @@ typedef enum LSM6DSM_XL_ST_POSITIVE = 1, LSM6DSM_XL_ST_NEGATIVE = 2, } lsm6dsm_st_xl_t; -int32_t lsm6dsm_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dsm_st_xl_t val); -int32_t lsm6dsm_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dsm_st_xl_t *val); typedef enum @@ -2056,14 +2049,14 @@ typedef enum LSM6DSM_GY_ST_POSITIVE = 1, LSM6DSM_GY_ST_NEGATIVE = 3, } lsm6dsm_st_g_t; -int32_t lsm6dsm_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dsm_st_g_t val); -int32_t lsm6dsm_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dsm_st_g_t *val); -int32_t lsm6dsm_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2071,9 +2064,9 @@ typedef enum LSM6DSM_USE_SLOPE = 0, LSM6DSM_USE_HPF = 1, } lsm6dsm_slope_fds_t; -int32_t lsm6dsm_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dsm_slope_fds_t val); -int32_t lsm6dsm_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dsm_slope_fds_t *val); typedef enum @@ -2081,9 +2074,9 @@ typedef enum LSM6DSM_XL_ANA_BW_1k5Hz = 0, LSM6DSM_XL_ANA_BW_400Hz = 1, } lsm6dsm_bw0_xl_t; -int32_t lsm6dsm_xl_filter_analog_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_filter_analog_set(const stmdev_ctx_t *ctx, lsm6dsm_bw0_xl_t val); -int32_t lsm6dsm_xl_filter_analog_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_filter_analog_get(const stmdev_ctx_t *ctx, lsm6dsm_bw0_xl_t *val); typedef enum @@ -2092,9 +2085,9 @@ typedef enum LSM6DSM_XL_LP1_ODR_DIV_4 = 1, LSM6DSM_XL_LP1_NA = 2, /* ERROR CODE */ } lsm6dsm_lpf1_bw_sel_t; -int32_t lsm6dsm_xl_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsm_lpf1_bw_sel_t val); -int32_t lsm6dsm_xl_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsm_lpf1_bw_sel_t *val); typedef enum @@ -2109,13 +2102,13 @@ typedef enum LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_400 = 0x13, LSM6DSM_XL_LP_NA = 0x20, /* ERROR CODE */ } lsm6dsm_input_composite_t; -int32_t lsm6dsm_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsm_input_composite_t val); -int32_t lsm6dsm_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsm_input_composite_t *val); -int32_t lsm6dsm_xl_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_xl_reference_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_xl_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2126,9 +2119,9 @@ typedef enum LSM6DSM_XL_HP_ODR_DIV_400 = 0x03, LSM6DSM_XL_HP_NA = 0x10, /* ERROR CODE */ } lsm6dsm_hpcf_xl_t; -int32_t lsm6dsm_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_hp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsm_hpcf_xl_t val); -int32_t lsm6dsm_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_hp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsm_hpcf_xl_t *val); typedef enum @@ -2137,13 +2130,13 @@ typedef enum LSM6DSM_XL_UI_LP1_ODR_DIV_4 = 1, LSM6DSM_XL_UI_LP1_NA = 2, } lsm6dsm_ui_lpf1_bw_sel_t; -int32_t lsm6dsm_xl_ui_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_ui_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsm_ui_lpf1_bw_sel_t val); -int32_t lsm6dsm_xl_ui_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_ui_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsm_ui_lpf1_bw_sel_t *val); -int32_t lsm6dsm_xl_ui_slope_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_xl_ui_slope_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_xl_ui_slope_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_xl_ui_slope_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2152,9 +2145,9 @@ typedef enum LSM6DSM_AUX_LP_STRONG = 0, LSM6DSM_AUX_LP_AGGRESSIVE = 1, } lsm6dsm_filter_xl_conf_ois_t; -int32_t lsm6dsm_xl_aux_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_aux_lp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsm_filter_xl_conf_ois_t val); -int32_t lsm6dsm_xl_aux_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_xl_aux_lp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsm_filter_xl_conf_ois_t *val); typedef enum @@ -2176,13 +2169,13 @@ typedef enum LSM6DSM_HP_260mHz_LP1_STRONG = 0xA8, LSM6DSM_HP_1Hz04_LP1_AGGRESSIVE = 0xBB, } lsm6dsm_lpf1_sel_g_t; -int32_t lsm6dsm_gy_band_pass_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_gy_band_pass_set(const stmdev_ctx_t *ctx, lsm6dsm_lpf1_sel_g_t val); -int32_t lsm6dsm_gy_band_pass_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_gy_band_pass_get(const stmdev_ctx_t *ctx, lsm6dsm_lpf1_sel_g_t *val); -int32_t lsm6dsm_gy_ui_high_pass_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_gy_ui_high_pass_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_gy_ui_high_pass_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_gy_ui_high_pass_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2196,21 +2189,21 @@ typedef enum LSM6DSM_HP_260mHz_LP_351Hz = 0xA0, LSM6DSM_HP_1Hz04_LP_937Hz = 0xB3, } lsm6dsm_hp_en_ois_t; -int32_t lsm6dsm_gy_aux_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_gy_aux_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsm_hp_en_ois_t val); -int32_t lsm6dsm_gy_aux_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_gy_aux_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsm_hp_en_ois_t *val); -int32_t lsm6dsm_aux_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_status_reg_get(const stmdev_ctx_t *ctx, lsm6dsm_status_spiaux_t *val); -int32_t lsm6dsm_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2219,13 +2212,13 @@ typedef enum LSM6DSM_AUX_DEN_LEVEL_LATCH = 3, LSM6DSM_AUX_DEN_LEVEL_TRIG = 2, } lsm6dsm_lvl_ois_t; -int32_t lsm6dsm_aux_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_den_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_lvl_ois_t val); -int32_t lsm6dsm_aux_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_den_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_lvl_ois_t *val); -int32_t lsm6dsm_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_aux_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2233,9 +2226,9 @@ typedef enum LSM6DSM_MODE_3_GY = 1, LSM6DSM_MODE_4_GY_XL = 3, } lsm6dsm_ois_en_spi2_t; -int32_t lsm6dsm_aux_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_ois_en_spi2_t val); -int32_t lsm6dsm_aux_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_ois_en_spi2_t *val); typedef enum @@ -2246,9 +2239,9 @@ typedef enum LSM6DSM_1000dps_AUX = 4, LSM6DSM_2000dps_AUX = 6, } lsm6dsm_fs_g_ois_t; -int32_t lsm6dsm_aux_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsm_fs_g_ois_t val); -int32_t lsm6dsm_aux_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsm_fs_g_ois_t *val); typedef enum @@ -2256,9 +2249,9 @@ typedef enum LSM6DSM_AUX_SPI_4_WIRE = 0, LSM6DSM_AUX_SPI_3_WIRE = 1, } lsm6dsm_sim_ois_t; -int32_t lsm6dsm_aux_spi_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_sim_ois_t val); -int32_t lsm6dsm_aux_spi_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_sim_ois_t *val); typedef enum @@ -2266,9 +2259,9 @@ typedef enum LSM6DSM_AUX_LSB_AT_LOW_ADD = 0, LSM6DSM_AUX_MSB_AT_LOW_ADD = 1, } lsm6dsm_ble_ois_t; -int32_t lsm6dsm_aux_data_format_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_data_format_set(const stmdev_ctx_t *ctx, lsm6dsm_ble_ois_t val); -int32_t lsm6dsm_aux_data_format_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_data_format_get(const stmdev_ctx_t *ctx, lsm6dsm_ble_ois_t *val); typedef enum @@ -2276,9 +2269,9 @@ typedef enum LSM6DSM_ENABLE_CLAMP = 0, LSM6DSM_DISABLE_CLAMP = 1, } lsm6dsm_st_ois_clampdis_t; -int32_t lsm6dsm_aux_gy_clamp_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_gy_clamp_set(const stmdev_ctx_t *ctx, lsm6dsm_st_ois_clampdis_t val); -int32_t lsm6dsm_aux_gy_clamp_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_gy_clamp_get(const stmdev_ctx_t *ctx, lsm6dsm_st_ois_clampdis_t *val); typedef enum @@ -2287,9 +2280,9 @@ typedef enum LSM6DSM_AUX_GY_POS = 1, LSM6DSM_AUX_GY_NEG = 3, } lsm6dsm_st_ois_t; -int32_t lsm6dsm_aux_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dsm_st_ois_t val); -int32_t lsm6dsm_aux_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dsm_st_ois_t *val); typedef enum @@ -2299,9 +2292,9 @@ typedef enum LSM6DSM_AUX_4g = 2, LSM6DSM_AUX_8g = 3, } lsm6dsm_fs_xl_ois_t; -int32_t lsm6dsm_aux_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsm_fs_xl_ois_t val); -int32_t lsm6dsm_aux_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsm_fs_xl_ois_t *val); typedef enum @@ -2309,9 +2302,9 @@ typedef enum LSM6DSM_AUX_DEN_ACTIVE_LOW = 0, LSM6DSM_AUX_DEN_ACTIVE_HIGH = 1, } lsm6dsm_den_lh_ois_t; -int32_t lsm6dsm_aux_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dsm_den_lh_ois_t val); -int32_t lsm6dsm_aux_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_aux_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dsm_den_lh_ois_t *val); typedef enum @@ -2319,17 +2312,17 @@ typedef enum LSM6DSM_SPI_4_WIRE = 0, LSM6DSM_SPI_3_WIRE = 1, } lsm6dsm_sim_t; -int32_t lsm6dsm_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsm_sim_t val); -int32_t lsm6dsm_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsm_sim_t *val); +int32_t lsm6dsm_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_sim_t val); +int32_t lsm6dsm_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_sim_t *val); typedef enum { LSM6DSM_I2C_ENABLE = 0, LSM6DSM_I2C_DISABLE = 1, } lsm6dsm_i2c_disable_t; -int32_t lsm6dsm_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_i2c_interface_set(const stmdev_ctx_t *ctx, lsm6dsm_i2c_disable_t val); -int32_t lsm6dsm_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_i2c_interface_get(const stmdev_ctx_t *ctx, lsm6dsm_i2c_disable_t *val); typedef struct @@ -2353,9 +2346,9 @@ typedef struct uint8_t den_drdy_int1 : 1; uint8_t drdy_on_int1 : 1; } lsm6dsm_int1_route_t; -int32_t lsm6dsm_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm6dsm_int1_route_t val); -int32_t lsm6dsm_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm6dsm_int1_route_t *val); typedef struct @@ -2378,9 +2371,9 @@ typedef struct uint8_t int2_inact_state : 1; uint8_t int2_wrist_tilt : 1; } lsm6dsm_int2_route_t; -int32_t lsm6dsm_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm6dsm_int2_route_t val); -int32_t lsm6dsm_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_pin_int2_route_get(const stmdev_ctx_t *ctx, lsm6dsm_int2_route_t *val); typedef enum @@ -2388,40 +2381,40 @@ typedef enum LSM6DSM_PUSH_PULL = 0, LSM6DSM_OPEN_DRAIN = 1, } lsm6dsm_pp_od_t; -int32_t lsm6dsm_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsm_pp_od_t val); -int32_t lsm6dsm_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsm_pp_od_t *val); +int32_t lsm6dsm_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_pp_od_t val); +int32_t lsm6dsm_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_pp_od_t *val); typedef enum { LSM6DSM_ACTIVE_HIGH = 0, LSM6DSM_ACTIVE_LOW = 1, } lsm6dsm_h_lactive_t; -int32_t lsm6dsm_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_pin_polarity_set(const stmdev_ctx_t *ctx, lsm6dsm_h_lactive_t val); -int32_t lsm6dsm_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_pin_polarity_get(const stmdev_ctx_t *ctx, lsm6dsm_h_lactive_t *val); -int32_t lsm6dsm_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSM_INT_PULSED = 0, LSM6DSM_INT_LATCHED = 1, } lsm6dsm_lir_t; -int32_t lsm6dsm_int_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_int_notification_set(const stmdev_ctx_t *ctx, lsm6dsm_lir_t val); -int32_t lsm6dsm_int_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_int_notification_get(const stmdev_ctx_t *ctx, lsm6dsm_lir_t *val); -int32_t lsm6dsm_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2430,52 +2423,52 @@ typedef enum LSM6DSM_XL_12Hz5_GY_SLEEP = 2, LSM6DSM_XL_12Hz5_GY_PD = 3, } lsm6dsm_inact_en_t; -int32_t lsm6dsm_act_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_act_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_inact_en_t val); -int32_t lsm6dsm_act_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_act_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_inact_en_t *val); -int32_t lsm6dsm_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_tap_src_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_tap_src_get(const stmdev_ctx_t *ctx, lsm6dsm_tap_src_t *val); -int32_t lsm6dsm_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSM_ONLY_SINGLE = 0, LSM6DSM_BOTH_SINGLE_DOUBLE = 1, } lsm6dsm_single_double_tap_t; -int32_t lsm6dsm_tap_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_single_double_tap_t val); -int32_t lsm6dsm_tap_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_single_double_tap_t *val); typedef enum @@ -2483,9 +2476,9 @@ typedef enum LSM6DSM_ODR_DIV_2_FEED = 0, LSM6DSM_LPF2_FEED = 1, } lsm6dsm_low_pass_on_6d_t; -int32_t lsm6dsm_6d_feed_data_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_6d_feed_data_set(const stmdev_ctx_t *ctx, lsm6dsm_low_pass_on_6d_t val); -int32_t lsm6dsm_6d_feed_data_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_6d_feed_data_get(const stmdev_ctx_t *ctx, lsm6dsm_low_pass_on_6d_t *val); typedef enum @@ -2495,16 +2488,16 @@ typedef enum LSM6DSM_DEG_60 = 2, LSM6DSM_DEG_50 = 3, } lsm6dsm_sixd_ths_t; -int32_t lsm6dsm_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_6d_threshold_set(const stmdev_ctx_t *ctx, lsm6dsm_sixd_ths_t val); -int32_t lsm6dsm_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_6d_threshold_get(const stmdev_ctx_t *ctx, lsm6dsm_sixd_ths_t *val); -int32_t lsm6dsm_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2517,23 +2510,23 @@ typedef enum LSM6DSM_FF_TSH_469mg = 6, LSM6DSM_FF_TSH_500mg = 7, } lsm6dsm_ff_ths_t; -int32_t lsm6dsm_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_ff_threshold_set(const stmdev_ctx_t *ctx, lsm6dsm_ff_ths_t val); -int32_t lsm6dsm_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_ff_threshold_get(const stmdev_ctx_t *ctx, lsm6dsm_ff_ths_t *val); -int32_t lsm6dsm_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsm_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsm_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsm_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsm_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsm_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsm_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_fifo_over_run_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_fifo_over_run_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsm_fifo_pattern_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsm_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_fifo_temp_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_fifo_temp_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2541,14 +2534,14 @@ typedef enum LSM6DSM_TRG_STEP_DETECT = 1, LSM6DSM_TRG_SH_DRDY = 2, } lsm6dsm_trigger_fifo_t; -int32_t lsm6dsm_fifo_write_trigger_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_write_trigger_set(const stmdev_ctx_t *ctx, lsm6dsm_trigger_fifo_t val); -int32_t lsm6dsm_fifo_write_trigger_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_write_trigger_get(const stmdev_ctx_t *ctx, lsm6dsm_trigger_fifo_t *val); -int32_t lsm6dsm_fifo_pedo_and_timestamp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_pedo_and_timestamp_batch_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_fifo_pedo_and_timestamp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_pedo_and_timestamp_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2562,9 +2555,9 @@ typedef enum LSM6DSM_FIFO_XL_DEC_16 = 6, LSM6DSM_FIFO_XL_DEC_32 = 7, } lsm6dsm_dec_fifo_xl_t; -int32_t lsm6dsm_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_xl_batch_set(const stmdev_ctx_t *ctx, lsm6dsm_dec_fifo_xl_t val); -int32_t lsm6dsm_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_xl_batch_get(const stmdev_ctx_t *ctx, lsm6dsm_dec_fifo_xl_t *val); typedef enum @@ -2578,9 +2571,9 @@ typedef enum LSM6DSM_FIFO_GY_DEC_16 = 6, LSM6DSM_FIFO_GY_DEC_32 = 7, } lsm6dsm_dec_fifo_gyro_t; -int32_t lsm6dsm_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_gy_batch_set(const stmdev_ctx_t *ctx, lsm6dsm_dec_fifo_gyro_t val); -int32_t lsm6dsm_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_gy_batch_get(const stmdev_ctx_t *ctx, lsm6dsm_dec_fifo_gyro_t *val); typedef enum @@ -2594,9 +2587,9 @@ typedef enum LSM6DSM_FIFO_DS3_DEC_16 = 6, LSM6DSM_FIFO_DS3_DEC_32 = 7, } lsm6dsm_dec_ds3_fifo_t; -int32_t lsm6dsm_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_dataset_3_batch_set(const stmdev_ctx_t *ctx, lsm6dsm_dec_ds3_fifo_t val); -int32_t lsm6dsm_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_dataset_3_batch_get(const stmdev_ctx_t *ctx, lsm6dsm_dec_ds3_fifo_t *val); typedef enum @@ -2610,18 +2603,18 @@ typedef enum LSM6DSM_FIFO_DS4_DEC_16 = 6, LSM6DSM_FIFO_DS4_DEC_32 = 7, } lsm6dsm_dec_ds4_fifo_t; -int32_t lsm6dsm_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_dataset_4_batch_set(const stmdev_ctx_t *ctx, lsm6dsm_dec_ds4_fifo_t val); -int32_t lsm6dsm_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_dataset_4_batch_get(const stmdev_ctx_t *ctx, lsm6dsm_dec_ds4_fifo_t *val); -int32_t lsm6dsm_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_xl_gy_8bit_format_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_xl_gy_8bit_format_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2631,9 +2624,9 @@ typedef enum LSM6DSM_BYPASS_TO_STREAM_MODE = 4, LSM6DSM_STREAM_MODE = 6, } lsm6dsm_fifo_mode_t; -int32_t lsm6dsm_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_fifo_mode_t val); -int32_t lsm6dsm_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_fifo_mode_t *val); typedef enum @@ -2650,9 +2643,9 @@ typedef enum LSM6DSM_FIFO_3k33Hz = 9, LSM6DSM_FIFO_6k66Hz = 10, } lsm6dsm_odr_fifo_t; -int32_t lsm6dsm_fifo_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsm_odr_fifo_t val); -int32_t lsm6dsm_fifo_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_fifo_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsm_odr_fifo_t *val); typedef enum @@ -2660,9 +2653,9 @@ typedef enum LSM6DSM_DEN_ACT_LOW = 0, LSM6DSM_DEN_ACT_HIGH = 1, } lsm6dsm_den_lh_t; -int32_t lsm6dsm_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dsm_den_lh_t val); -int32_t lsm6dsm_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dsm_den_lh_t *val); typedef enum @@ -2673,9 +2666,9 @@ typedef enum LSM6DSM_LEVEL_TRIGGER = 2, LSM6DSM_EDGE_TRIGGER = 4, } lsm6dsm_den_mode_t; -int32_t lsm6dsm_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_den_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_den_mode_t val); -int32_t lsm6dsm_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_den_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_den_mode_t *val); typedef enum @@ -2684,96 +2677,96 @@ typedef enum LSM6DSM_STAMP_IN_XL_DATA = 1, LSM6DSM_STAMP_IN_GY_XL_DATA = 2, } lsm6dsm_den_xl_en_t; -int32_t lsm6dsm_den_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_den_enable_set(const stmdev_ctx_t *ctx, lsm6dsm_den_xl_en_t val); -int32_t lsm6dsm_den_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_den_enable_get(const stmdev_ctx_t *ctx, lsm6dsm_den_xl_en_t *val); -int32_t lsm6dsm_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_pedo_step_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_pedo_step_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_pedo_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_pedo_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSM_PEDO_AT_2g = 0, LSM6DSM_PEDO_AT_4g = 1, } lsm6dsm_pedo_fs_t; -int32_t lsm6dsm_pedo_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_pedo_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsm_pedo_fs_t val); -int32_t lsm6dsm_pedo_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_pedo_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsm_pedo_fs_t *val); -int32_t lsm6dsm_pedo_debounce_steps_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_pedo_debounce_steps_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_pedo_timeout_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_pedo_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_pedo_steps_period_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_pedo_steps_period_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsm_pedo_steps_period_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_pedo_steps_period_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsm_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_motion_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_motion_threshold_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsm_motion_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_motion_threshold_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsm_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_wrist_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_wrist_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_wrist_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_wrist_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_tilt_latency_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsm_tilt_latency_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsm_tilt_latency_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsm_tilt_latency_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsm_tilt_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsm_tilt_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsm_tilt_threshold_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsm_tilt_threshold_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsm_tilt_src_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_tilt_src_set(const stmdev_ctx_t *ctx, lsm6dsm_a_wrist_tilt_mask_t *val); -int32_t lsm6dsm_tilt_src_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_tilt_src_get(const stmdev_ctx_t *ctx, lsm6dsm_a_wrist_tilt_mask_t *val); -int32_t lsm6dsm_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_mag_hard_iron_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_mag_hard_iron_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_mag_soft_iron_mat_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsm_mag_soft_iron_mat_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_mag_soft_iron_mat_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsm_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsm_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsm_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsm_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsm_func_en_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_func_en_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_sync_sens_frame_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_sync_sens_frame_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2783,16 +2776,16 @@ typedef enum LSM6DSM_RES_RATIO_2_13 = 2, LSM6DSM_RES_RATIO_2_14 = 3, } lsm6dsm_rr_t; -int32_t lsm6dsm_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_sync_sens_ratio_set(const stmdev_ctx_t *ctx, lsm6dsm_rr_t val); -int32_t lsm6dsm_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_sync_sens_ratio_get(const stmdev_ctx_t *ctx, lsm6dsm_rr_t *val); -int32_t lsm6dsm_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2800,9 +2793,9 @@ typedef enum LSM6DSM_INTERNAL_PULL_UP = 1, LSM6DSM_SH_PIN_MODE = 2, } lsm6dsm_pull_up_en_t; -int32_t lsm6dsm_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_pull_up_en_t val); -int32_t lsm6dsm_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_pull_up_en_t *val); typedef enum @@ -2810,13 +2803,13 @@ typedef enum LSM6DSM_XL_GY_DRDY = 0, LSM6DSM_EXT_ON_INT2_PIN = 1, } lsm6dsm_start_config_t; -int32_t lsm6dsm_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_syncro_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_start_config_t val); -int32_t lsm6dsm_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_syncro_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_start_config_t *val); -int32_t lsm6dsm_sh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_sh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_sh_drdy_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_sh_drdy_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -2839,14 +2832,14 @@ typedef struct lsm6dsm_sensorhub17_reg_t sh_byte_17; lsm6dsm_sensorhub18_reg_t sh_byte_18; } lsm6dsm_emb_sh_read_t; -int32_t lsm6dsm_sh_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_read_data_raw_get(const stmdev_ctx_t *ctx, lsm6dsm_emb_sh_read_t *val); -int32_t lsm6dsm_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsm_sh_cmd_sens_sync_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_sh_cmd_sens_sync_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsm_sh_spi_sync_error_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsm_sh_spi_sync_error_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_spi_sync_error_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsm_sh_spi_sync_error_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2854,9 +2847,9 @@ typedef enum LSM6DSM_NORMAL_MODE_READ = 0, LSM6DSM_SRC_MODE_READ = 1, } lsm6dsm_src_mode_t; -int32_t lsm6dsm_sh_cfg_slave_0_rd_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_cfg_slave_0_rd_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_src_mode_t val); -int32_t lsm6dsm_sh_cfg_slave_0_rd_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_cfg_slave_0_rd_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_src_mode_t *val); typedef enum @@ -2866,9 +2859,9 @@ typedef enum LSM6DSM_SLV_0_1_2 = 2, LSM6DSM_SLV_0_1_2_3 = 3, } lsm6dsm_aux_sens_on_t; -int32_t lsm6dsm_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_num_of_dev_connected_set(const stmdev_ctx_t *ctx, lsm6dsm_aux_sens_on_t val); -int32_t lsm6dsm_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_num_of_dev_connected_get(const stmdev_ctx_t *ctx, lsm6dsm_aux_sens_on_t *val); typedef struct @@ -2877,7 +2870,7 @@ typedef struct uint8_t slv0_subadd; uint8_t slv0_data; } lsm6dsm_sh_cfg_write_t; -int32_t lsm6dsm_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_cfg_write(const stmdev_ctx_t *ctx, lsm6dsm_sh_cfg_write_t *val); typedef struct @@ -2886,13 +2879,13 @@ typedef struct uint8_t slv_subadd; uint8_t slv_len; } lsm6dsm_sh_cfg_read_t; -int32_t lsm6dsm_sh_slv0_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, lsm6dsm_sh_cfg_read_t *val); -int32_t lsm6dsm_sh_slv1_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, lsm6dsm_sh_cfg_read_t *val); -int32_t lsm6dsm_sh_slv2_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, lsm6dsm_sh_cfg_read_t *val); -int32_t lsm6dsm_sh_slv3_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, lsm6dsm_sh_cfg_read_t *val); typedef enum @@ -2902,9 +2895,9 @@ typedef enum LSM6DSM_SL0_DEC_4 = 2, LSM6DSM_SL0_DEC_8 = 3, } lsm6dsm_slave0_rate_t; -int32_t lsm6dsm_sh_slave_0_dec_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_slave_0_dec_set(const stmdev_ctx_t *ctx, lsm6dsm_slave0_rate_t val); -int32_t lsm6dsm_sh_slave_0_dec_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_slave_0_dec_get(const stmdev_ctx_t *ctx, lsm6dsm_slave0_rate_t *val); typedef enum @@ -2912,9 +2905,9 @@ typedef enum LSM6DSM_EACH_SH_CYCLE = 0, LSM6DSM_ONLY_FIRST_CYCLE = 1, } lsm6dsm_write_once_t; -int32_t lsm6dsm_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_write_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_write_once_t val); -int32_t lsm6dsm_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_write_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_write_once_t *val); typedef enum @@ -2924,9 +2917,9 @@ typedef enum LSM6DSM_SL1_DEC_4 = 2, LSM6DSM_SL1_DEC_8 = 3, } lsm6dsm_slave1_rate_t; -int32_t lsm6dsm_sh_slave_1_dec_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_slave_1_dec_set(const stmdev_ctx_t *ctx, lsm6dsm_slave1_rate_t val); -int32_t lsm6dsm_sh_slave_1_dec_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_slave_1_dec_get(const stmdev_ctx_t *ctx, lsm6dsm_slave1_rate_t *val); typedef enum @@ -2936,9 +2929,9 @@ typedef enum LSM6DSM_SL2_DEC_4 = 2, LSM6DSM_SL2_DEC_8 = 3, } lsm6dsm_slave2_rate_t; -int32_t lsm6dsm_sh_slave_2_dec_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_slave_2_dec_set(const stmdev_ctx_t *ctx, lsm6dsm_slave2_rate_t val); -int32_t lsm6dsm_sh_slave_2_dec_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_slave_2_dec_get(const stmdev_ctx_t *ctx, lsm6dsm_slave2_rate_t *val); typedef enum @@ -2948,9 +2941,9 @@ typedef enum LSM6DSM_SL3_DEC_4 = 2, LSM6DSM_SL3_DEC_8 = 3, } lsm6dsm_slave3_rate_t; -int32_t lsm6dsm_sh_slave_3_dec_set(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_slave_3_dec_set(const stmdev_ctx_t *ctx, lsm6dsm_slave3_rate_t val); -int32_t lsm6dsm_sh_slave_3_dec_get(stmdev_ctx_t *ctx, +int32_t lsm6dsm_sh_slave_3_dec_get(const stmdev_ctx_t *ctx, lsm6dsm_slave3_rate_t *val); /** diff --git a/sensor/stmemsc/lsm6dso16is_STdC/driver/lsm6dso16is_reg.c b/sensor/stmemsc/lsm6dso16is_STdC/driver/lsm6dso16is_reg.c index 85fb2705..9a784a11 100644 --- a/sensor/stmemsc/lsm6dso16is_STdC/driver/lsm6dso16is_reg.c +++ b/sensor/stmemsc/lsm6dso16is_STdC/driver/lsm6dso16is_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm6dso16is_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm6dso16is_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lsm6dso16is_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm6dso16is_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm6dso16is_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -157,7 +167,7 @@ float_t lsm6dso16is_from_lsb_to_celsius(int16_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso16is_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso16is_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso16is_internal_freq_fine_t internal_freq_fine; int32_t ret; @@ -185,7 +195,7 @@ int32_t lsm6dso16is_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso16is_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso16is_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso16is_internal_freq_fine_t internal_freq_fine; int32_t ret; @@ -205,7 +215,7 @@ int32_t lsm6dso16is_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_mem_bank_set(stmdev_ctx_t *ctx, lsm6dso16is_mem_bank_t val) +int32_t lsm6dso16is_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dso16is_mem_bank_t val) { lsm6dso16is_func_cfg_access_t func_cfg_access = {0x0}; int32_t ret; @@ -226,7 +236,7 @@ int32_t lsm6dso16is_mem_bank_set(stmdev_ctx_t *ctx, lsm6dso16is_mem_bank_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_mem_bank_get(stmdev_ctx_t *ctx, lsm6dso16is_mem_bank_t *val) +int32_t lsm6dso16is_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dso16is_mem_bank_t *val) { lsm6dso16is_func_cfg_access_t func_cfg_access; int32_t ret; @@ -257,7 +267,7 @@ int32_t lsm6dso16is_mem_bank_get(stmdev_ctx_t *ctx, lsm6dso16is_mem_bank_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm6dso16is_data_ready_mode_t val) { lsm6dso16is_drdy_pulsed_reg_t drdy_pulsed_reg; @@ -282,7 +292,7 @@ int32_t lsm6dso16is_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm6dso16is_data_ready_mode_t *val) { lsm6dso16is_drdy_pulsed_reg_t drdy_pulsed_reg; @@ -315,7 +325,7 @@ int32_t lsm6dso16is_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_device_id_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso16is_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -331,7 +341,7 @@ int32_t lsm6dso16is_device_id_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso16is_software_reset(stmdev_ctx_t *ctx) +int32_t lsm6dso16is_software_reset(const stmdev_ctx_t *ctx) { lsm6dso16is_ctrl3_c_t ctrl3_c; int32_t ret; @@ -346,7 +356,8 @@ int32_t lsm6dso16is_software_reset(stmdev_ctx_t *ctx) ctrl3_c.sw_reset = PROPERTY_ENABLE; ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); - do { + do + { ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_CTRL3_C, (uint8_t *)&ctrl3_c, 1); } while (ret == 0 && ctrl3_c.sw_reset == PROPERTY_ENABLE); } @@ -362,7 +373,7 @@ int32_t lsm6dso16is_software_reset(stmdev_ctx_t *ctx) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso16is_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso16is_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso16is_ctrl3_c_t ctrl3_c; int32_t ret; @@ -386,7 +397,7 @@ int32_t lsm6dso16is_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso16is_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso16is_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso16is_ctrl3_c_t ctrl3_c; int32_t ret; @@ -405,7 +416,7 @@ int32_t lsm6dso16is_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_xl_hm_mode_set(stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t val) +int32_t lsm6dso16is_xl_hm_mode_set(const stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t val) { lsm6dso16is_ctrl6_c_t ctrl6_c; int32_t ret; @@ -429,7 +440,7 @@ int32_t lsm6dso16is_xl_hm_mode_set(stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_xl_hm_mode_get(stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t *val) +int32_t lsm6dso16is_xl_hm_mode_get(const stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t *val) { lsm6dso16is_ctrl6_c_t ctrl6_c; int32_t ret; @@ -461,7 +472,7 @@ int32_t lsm6dso16is_xl_hm_mode_get(stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t *val * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dso16is_xl_full_scale_t val) { lsm6dso16is_ctrl1_xl_t ctrl1_xl; @@ -486,7 +497,7 @@ int32_t lsm6dso16is_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dso16is_xl_full_scale_t *val) { lsm6dso16is_ctrl1_xl_t ctrl1_xl; @@ -527,7 +538,7 @@ int32_t lsm6dso16is_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso16is_xl_data_rate_t val) { lsm6dso16is_ctrl1_xl_t ctrl1_xl; @@ -561,7 +572,7 @@ int32_t lsm6dso16is_xl_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso16is_xl_data_rate_t *val) { lsm6dso16is_ctrl1_xl_t ctrl1_xl; @@ -677,7 +688,7 @@ int32_t lsm6dso16is_xl_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_gy_hm_mode_set(stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t val) +int32_t lsm6dso16is_gy_hm_mode_set(const stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t val) { lsm6dso16is_ctrl7_g_t ctrl7_g; int32_t ret; @@ -701,7 +712,7 @@ int32_t lsm6dso16is_gy_hm_mode_set(stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_gy_hm_mode_get(stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t *val) +int32_t lsm6dso16is_gy_hm_mode_get(const stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t *val) { lsm6dso16is_ctrl7_g_t ctrl7_g; int32_t ret; @@ -733,7 +744,7 @@ int32_t lsm6dso16is_gy_hm_mode_get(stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t *val * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dso16is_gy_full_scale_t val) { lsm6dso16is_ctrl2_g_t ctrl2_g; @@ -759,7 +770,7 @@ int32_t lsm6dso16is_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dso16is_gy_full_scale_t *val) { lsm6dso16is_ctrl2_g_t ctrl2_g; @@ -804,7 +815,7 @@ int32_t lsm6dso16is_gy_full_scale_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_gy_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso16is_gy_data_rate_t val) { lsm6dso16is_ctrl2_g_t ctrl2_g; @@ -838,7 +849,7 @@ int32_t lsm6dso16is_gy_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso16is_gy_data_rate_t *val) { lsm6dso16is_ctrl2_g_t ctrl2_g; @@ -950,7 +961,7 @@ int32_t lsm6dso16is_gy_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso16is_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso16is_ctrl3_c_t ctrl3_c; int32_t ret; @@ -974,7 +985,7 @@ int32_t lsm6dso16is_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso16is_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso16is_ctrl3_c_t ctrl3_c; int32_t ret; @@ -994,7 +1005,7 @@ int32_t lsm6dso16is_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso16is_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso16is_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1018,7 +1029,7 @@ int32_t lsm6dso16is_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso16is_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso16is_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1038,7 +1049,7 @@ int32_t lsm6dso16is_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_sleep_set(stmdev_ctx_t *ctx, lsm6dso16is_sleep_t val) +int32_t lsm6dso16is_sleep_set(const stmdev_ctx_t *ctx, lsm6dso16is_sleep_t val) { lsm6dso16is_ctrl4_c_t ctrl4_c; int32_t ret; @@ -1062,7 +1073,7 @@ int32_t lsm6dso16is_sleep_set(stmdev_ctx_t *ctx, lsm6dso16is_sleep_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_sleep_get(stmdev_ctx_t *ctx, lsm6dso16is_sleep_t *val) +int32_t lsm6dso16is_sleep_get(const stmdev_ctx_t *ctx, lsm6dso16is_sleep_t *val) { lsm6dso16is_ctrl4_c_t ctrl4_c; int32_t ret; @@ -1094,7 +1105,7 @@ int32_t lsm6dso16is_sleep_get(stmdev_ctx_t *ctx, lsm6dso16is_sleep_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dso16is_xl_self_test_t val) { lsm6dso16is_ctrl5_c_t ctrl5_c; @@ -1119,7 +1130,7 @@ int32_t lsm6dso16is_xl_self_test_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dso16is_xl_self_test_t *val) { lsm6dso16is_ctrl5_c_t ctrl5_c; @@ -1156,7 +1167,7 @@ int32_t lsm6dso16is_xl_self_test_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dso16is_gy_self_test_t val) { lsm6dso16is_ctrl5_c_t ctrl5_c; @@ -1181,7 +1192,7 @@ int32_t lsm6dso16is_gy_self_test_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dso16is_gy_self_test_t *val) { lsm6dso16is_ctrl5_c_t ctrl5_c; @@ -1224,7 +1235,7 @@ int32_t lsm6dso16is_gy_self_test_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso16is_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso16is_pin_ctrl_t pin_ctrl; int32_t ret; @@ -1248,7 +1259,7 @@ int32_t lsm6dso16is_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso16is_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso16is_pin_ctrl_t pin_ctrl; int32_t ret; @@ -1268,7 +1279,7 @@ int32_t lsm6dso16is_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso16is_spi_mode_t val) +int32_t lsm6dso16is_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dso16is_spi_mode_t val) { lsm6dso16is_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1292,7 +1303,7 @@ int32_t lsm6dso16is_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso16is_spi_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_spi_mode_get(stmdev_ctx_t *ctx, lsm6dso16is_spi_mode_t *val) +int32_t lsm6dso16is_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dso16is_spi_mode_t *val) { lsm6dso16is_ctrl3_c_t ctrl3_c; int32_t ret; @@ -1324,7 +1335,7 @@ int32_t lsm6dso16is_spi_mode_get(stmdev_ctx_t *ctx, lsm6dso16is_spi_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ui_i2c_mode_set(stmdev_ctx_t *ctx, lsm6dso16is_ui_i2c_mode_t val) +int32_t lsm6dso16is_ui_i2c_mode_set(const stmdev_ctx_t *ctx, lsm6dso16is_ui_i2c_mode_t val) { lsm6dso16is_ctrl4_c_t ctrl4_c; int32_t ret; @@ -1348,7 +1359,7 @@ int32_t lsm6dso16is_ui_i2c_mode_set(stmdev_ctx_t *ctx, lsm6dso16is_ui_i2c_mode_t * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ui_i2c_mode_get(stmdev_ctx_t *ctx, lsm6dso16is_ui_i2c_mode_t *val) +int32_t lsm6dso16is_ui_i2c_mode_get(const stmdev_ctx_t *ctx, lsm6dso16is_ui_i2c_mode_t *val) { lsm6dso16is_ctrl4_c_t ctrl4_c; int32_t ret; @@ -1391,7 +1402,7 @@ int32_t lsm6dso16is_ui_i2c_mode_get(stmdev_ctx_t *ctx, lsm6dso16is_ui_i2c_mode_t * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso16is_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso16is_ctrl10_c_t ctrl10_c; int32_t ret; @@ -1415,7 +1426,7 @@ int32_t lsm6dso16is_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso16is_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso16is_ctrl10_c_t ctrl10_c; int32_t ret; @@ -1435,7 +1446,7 @@ int32_t lsm6dso16is_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t lsm6dso16is_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; @@ -1463,7 +1474,7 @@ int32_t lsm6dso16is_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_all_sources_get(stmdev_ctx_t *ctx, lsm6dso16is_all_sources_t *val) +int32_t lsm6dso16is_all_sources_get(const stmdev_ctx_t *ctx, lsm6dso16is_all_sources_t *val) { lsm6dso16is_status_reg_t status_reg; lsm6dso16is_status_master_mainpage_t status_sh; @@ -1471,14 +1482,20 @@ int32_t lsm6dso16is_all_sources_get(stmdev_ctx_t *ctx, lsm6dso16is_all_sources_t int32_t ret; ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_STATUS_REG, (uint8_t *)&status_reg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->drdy_xl = status_reg.xlda; val->drdy_gy = status_reg.gda; val->drdy_temp = status_reg.tda; ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_STATUS_MASTER_MAINPAGE, (uint8_t *)&status_sh, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->sh_endop = status_sh.sens_hub_endop; val->sh_slave0_nack = status_sh.sens_hub_endop; @@ -1488,7 +1505,10 @@ int32_t lsm6dso16is_all_sources_get(stmdev_ctx_t *ctx, lsm6dso16is_all_sources_t val->sh_wr_once = status_sh.sens_hub_endop; ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_INT_STATUS0_MAINPAGE, (uint8_t *)&status_ispu, 4); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->ispu = status_ispu; @@ -1503,7 +1523,7 @@ int32_t lsm6dso16is_all_sources_get(stmdev_ctx_t *ctx, lsm6dso16is_all_sources_t * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso16is_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_status_reg_get(const stmdev_ctx_t *ctx, lsm6dso16is_status_reg_t *val) { int32_t ret; @@ -1520,7 +1540,7 @@ int32_t lsm6dso16is_status_reg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso16is_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso16is_status_reg_t status_reg; @@ -1540,7 +1560,7 @@ int32_t lsm6dso16is_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso16is_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso16is_status_reg_t status_reg; @@ -1560,7 +1580,7 @@ int32_t lsm6dso16is_gy_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso16is_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso16is_status_reg_t status_reg; @@ -1580,7 +1600,7 @@ int32_t lsm6dso16is_temp_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dso16is_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1600,7 +1620,7 @@ int32_t lsm6dso16is_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dso16is_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1624,7 +1644,7 @@ int32_t lsm6dso16is_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dso16is_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1659,7 +1679,7 @@ int32_t lsm6dso16is_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm6dso16is_pin_int1_route_t val) { lsm6dso16is_int1_ctrl_t int1_ctrl; @@ -1668,7 +1688,10 @@ int32_t lsm6dso16is_pin_int1_route_set(stmdev_ctx_t *ctx, ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MD1_CFG, (uint8_t *)&md1_cfg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } int1_ctrl.int1_drdy_xl = val.drdy_xl; int1_ctrl.int1_drdy_g = val.drdy_gy; @@ -1691,7 +1714,7 @@ int32_t lsm6dso16is_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm6dso16is_pin_int1_route_t *val) { lsm6dso16is_int1_ctrl_t int1_ctrl; @@ -1700,7 +1723,10 @@ int32_t lsm6dso16is_pin_int1_route_get(stmdev_ctx_t *ctx, ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MD1_CFG, (uint8_t *)&md1_cfg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->drdy_xl = int1_ctrl.int1_drdy_xl; val->drdy_gy = int1_ctrl.int1_drdy_g; @@ -1719,7 +1745,7 @@ int32_t lsm6dso16is_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm6dso16is_pin_int2_route_t val) { lsm6dso16is_int2_ctrl_t int2_ctrl; @@ -1728,7 +1754,10 @@ int32_t lsm6dso16is_pin_int2_route_set(stmdev_ctx_t *ctx, ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MD2_CFG, (uint8_t *)&md2_cfg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } int2_ctrl.int2_drdy_xl = val.drdy_xl; int2_ctrl.int2_drdy_g = val.drdy_gy; @@ -1751,7 +1780,7 @@ int32_t lsm6dso16is_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_pin_int2_route_get(const stmdev_ctx_t *ctx, lsm6dso16is_pin_int2_route_t *val) { lsm6dso16is_int2_ctrl_t int2_ctrl; @@ -1760,7 +1789,10 @@ int32_t lsm6dso16is_pin_int2_route_get(stmdev_ctx_t *ctx, ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MD2_CFG, (uint8_t *)&md2_cfg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->drdy_xl = int2_ctrl.int2_drdy_xl; val->drdy_gy = int2_ctrl.int2_drdy_g; @@ -1780,7 +1812,7 @@ int32_t lsm6dso16is_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_int_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_int_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dso16is_int_pin_mode_t val) { lsm6dso16is_ctrl3_c_t ctrl3_c; @@ -1805,7 +1837,7 @@ int32_t lsm6dso16is_int_pin_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_int_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_int_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dso16is_int_pin_mode_t *val) { lsm6dso16is_ctrl3_c_t ctrl3_c; @@ -1838,7 +1870,7 @@ int32_t lsm6dso16is_int_pin_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_pin_polarity_set(const stmdev_ctx_t *ctx, lsm6dso16is_pin_polarity_t val) { lsm6dso16is_ctrl3_c_t ctrl3_c; @@ -1863,7 +1895,7 @@ int32_t lsm6dso16is_pin_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_pin_polarity_get(const stmdev_ctx_t *ctx, lsm6dso16is_pin_polarity_t *val) { lsm6dso16is_ctrl3_c_t ctrl3_c; @@ -1909,7 +1941,7 @@ int32_t lsm6dso16is_pin_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val, +int32_t lsm6dso16is_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, uint8_t len) { int32_t ret; @@ -1929,7 +1961,7 @@ int32_t lsm6dso16is_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_sh_slave_connected_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_sh_slave_connected_set(const stmdev_ctx_t *ctx, lsm6dso16is_sh_slave_connected_t val) { lsm6dso16is_master_config_t master_config; @@ -1937,7 +1969,10 @@ int32_t lsm6dso16is_sh_slave_connected_set(stmdev_ctx_t *ctx, ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } master_config.aux_sens_on = (uint8_t)val & 0x3U; ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); @@ -1956,7 +1991,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_sh_slave_connected_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_sh_slave_connected_get(const stmdev_ctx_t *ctx, lsm6dso16is_sh_slave_connected_t *val) { lsm6dso16is_master_config_t master_config; @@ -1965,7 +2000,10 @@ int32_t lsm6dso16is_sh_slave_connected_get(stmdev_ctx_t *ctx, ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (master_config.aux_sens_on) { @@ -2001,14 +2039,17 @@ int32_t lsm6dso16is_sh_slave_connected_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso16is_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso16is_master_config_t master_config; int32_t ret; ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } master_config.master_on = val; ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); @@ -2027,14 +2068,17 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso16is_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso16is_master_config_t master_config; int32_t ret; ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } *val = master_config.master_on; @@ -2051,14 +2095,17 @@ int32_t lsm6dso16is_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_sh_master_interface_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso16is_sh_master_interface_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso16is_master_config_t master_config; int32_t ret; ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } master_config.shub_pu_en = val; ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); @@ -2077,7 +2124,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_sh_master_interface_pull_up_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_sh_master_interface_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso16is_master_config_t master_config; @@ -2085,7 +2132,10 @@ int32_t lsm6dso16is_sh_master_interface_pull_up_get(stmdev_ctx_t *ctx, ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } *val = master_config.shub_pu_en; @@ -2102,14 +2152,17 @@ int32_t lsm6dso16is_sh_master_interface_pull_up_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso16is_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso16is_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso16is_master_config_t master_config; int32_t ret; ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } master_config.pass_through_mode = (uint8_t)val; ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); @@ -2128,7 +2181,7 @@ exit: * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso16is_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso16is_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso16is_master_config_t master_config; int32_t ret; @@ -2150,7 +2203,7 @@ int32_t lsm6dso16is_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_sh_syncro_mode_set(const stmdev_ctx_t *ctx, lsm6dso16is_sh_syncro_mode_t val) { lsm6dso16is_master_config_t master_config; @@ -2158,7 +2211,10 @@ int32_t lsm6dso16is_sh_syncro_mode_set(stmdev_ctx_t *ctx, ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } master_config.start_config = (uint8_t)val & 0x01U; ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); @@ -2177,7 +2233,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_sh_syncro_mode_get(const stmdev_ctx_t *ctx, lsm6dso16is_sh_syncro_mode_t *val) { lsm6dso16is_master_config_t master_config; @@ -2186,7 +2242,10 @@ int32_t lsm6dso16is_sh_syncro_mode_get(stmdev_ctx_t *ctx, ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (master_config.start_config) { @@ -2214,7 +2273,7 @@ int32_t lsm6dso16is_sh_syncro_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_sh_write_mode_set(const stmdev_ctx_t *ctx, lsm6dso16is_sh_write_mode_t val) { lsm6dso16is_master_config_t master_config; @@ -2222,7 +2281,10 @@ int32_t lsm6dso16is_sh_write_mode_set(stmdev_ctx_t *ctx, ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } master_config.write_once = (uint8_t)val & 0x01U; ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); @@ -2241,7 +2303,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_sh_write_mode_get(const stmdev_ctx_t *ctx, lsm6dso16is_sh_write_mode_t *val) { lsm6dso16is_master_config_t master_config; @@ -2250,7 +2312,10 @@ int32_t lsm6dso16is_sh_write_mode_get(stmdev_ctx_t *ctx, ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (master_config.write_once) { @@ -2278,14 +2343,17 @@ int32_t lsm6dso16is_sh_write_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_sh_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso16is_sh_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso16is_master_config_t master_config; int32_t ret; ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } master_config.rst_master_regs = val; ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); @@ -2304,14 +2372,17 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso16is_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso16is_master_config_t master_config; int32_t ret; ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } *val = master_config.rst_master_regs; @@ -2331,23 +2402,32 @@ int32_t lsm6dso16is_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_sh_cfg_write(const stmdev_ctx_t *ctx, lsm6dso16is_sh_cfg_write_t *val) { lsm6dso16is_slv0_add_t reg; int32_t ret; ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } reg.slave0_add = val->slv0_add; reg.rw_0 = 0; ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV0_ADD, (uint8_t *)®, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV0_SUBADD, &(val->slv0_subadd), 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_DATAWRITE_SLV0, &(val->slv0_data), 1); @@ -2366,7 +2446,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_sh_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_sh_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso16is_sh_data_rate_t val) { lsm6dso16is_slv0_config_t slv0_config; @@ -2374,7 +2454,10 @@ int32_t lsm6dso16is_sh_data_rate_set(stmdev_ctx_t *ctx, ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } slv0_config.shub_odr = (uint8_t)val & 0x07U; ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); @@ -2393,7 +2476,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_sh_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_sh_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso16is_sh_data_rate_t *val) { lsm6dso16is_slv0_config_t slv0_config; @@ -2402,7 +2485,10 @@ int32_t lsm6dso16is_sh_data_rate_get(stmdev_ctx_t *ctx, ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (slv0_config.shub_odr) { @@ -2441,7 +2527,7 @@ int32_t lsm6dso16is_sh_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_sh_slv_cfg_read(stmdev_ctx_t *ctx, uint8_t idx, +int32_t lsm6dso16is_sh_slv_cfg_read(const stmdev_ctx_t *ctx, uint8_t idx, lsm6dso16is_sh_cfg_read_t *val) { lsm6dso16is_slv0_add_t slv_add; @@ -2449,25 +2535,37 @@ int32_t lsm6dso16is_sh_slv_cfg_read(stmdev_ctx_t *ctx, uint8_t idx, int32_t ret; ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_SENSOR_HUB_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } slv_add.slave0_add = val->slv_add; slv_add.rw_0 = 1; - ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV0_ADD + idx*3U, - (uint8_t *)&slv_add, 1); - if (ret != 0) { goto exit; } + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV0_ADD + idx * 3U, + (uint8_t *)&slv_add, 1); + if (ret != 0) + { + goto exit; + } - ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV0_SUBADD + idx*3U, - &(val->slv_subadd), 1); - if (ret != 0) { goto exit; } + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV0_SUBADD + idx * 3U, + &(val->slv_subadd), 1); + if (ret != 0) + { + goto exit; + } - ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_SLV0_CONFIG + idx*3U, - (uint8_t *)&slv_config, 1); - if (ret != 0) { goto exit; } + ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_SLV0_CONFIG + idx * 3U, + (uint8_t *)&slv_config, 1); + if (ret != 0) + { + goto exit; + } slv_config.slave0_numop = val->slv_len; - ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV0_CONFIG + idx*3U, - (uint8_t *)&slv_config, 1); + ret = lsm6dso16is_write_reg(ctx, LSM6DSO16IS_SLV0_CONFIG + idx * 3U, + (uint8_t *)&slv_config, 1); exit: ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); @@ -2483,7 +2581,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_sh_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_sh_status_get(const stmdev_ctx_t *ctx, lsm6dso16is_status_master_t *val) { int32_t ret; @@ -2512,7 +2610,7 @@ int32_t lsm6dso16is_sh_status_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ispu_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso16is_ispu_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso16is_func_cfg_access_t func_cfg_access; int32_t ret; @@ -2536,7 +2634,7 @@ int32_t lsm6dso16is_ispu_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ispu_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso16is_ispu_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso16is_func_cfg_access_t func_cfg_access; int32_t ret; @@ -2549,7 +2647,7 @@ int32_t lsm6dso16is_ispu_reset_get(stmdev_ctx_t *ctx, uint8_t *val) return ret; } -int32_t lsm6dso16is_ispu_clock_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_ispu_clock_set(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_clock_sel_t val) { lsm6dso16is_ctrl10_c_t ctrl10_c; @@ -2566,7 +2664,7 @@ int32_t lsm6dso16is_ispu_clock_set(stmdev_ctx_t *ctx, return ret; } -int32_t lsm6dso16is_ispu_clock_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_ispu_clock_get(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_clock_sel_t *val) { lsm6dso16is_ctrl10_c_t ctrl10_c; @@ -2598,7 +2696,7 @@ int32_t lsm6dso16is_ispu_clock_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ispu_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_ispu_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_data_rate_t val) { lsm6dso16is_ctrl9_c_t ctrl9_c; @@ -2625,7 +2723,7 @@ int32_t lsm6dso16is_ispu_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ispu_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_ispu_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_data_rate_t *val) { lsm6dso16is_ctrl9_c_t ctrl9_c; @@ -2694,7 +2792,7 @@ int32_t lsm6dso16is_ispu_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ispu_bdu_set(stmdev_ctx_t *ctx, lsm6dso16is_ispu_bdu_t val) +int32_t lsm6dso16is_ispu_bdu_set(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_bdu_t val) { lsm6dso16is_ctrl9_c_t ctrl9_c; int32_t ret; @@ -2718,7 +2816,7 @@ int32_t lsm6dso16is_ispu_bdu_set(stmdev_ctx_t *ctx, lsm6dso16is_ispu_bdu_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ispu_bdu_get(stmdev_ctx_t *ctx, lsm6dso16is_ispu_bdu_t *val) +int32_t lsm6dso16is_ispu_bdu_get(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_bdu_t *val) { lsm6dso16is_ctrl9_c_t ctrl9_c; int32_t ret; @@ -2758,7 +2856,7 @@ int32_t lsm6dso16is_ispu_bdu_get(stmdev_ctx_t *ctx, lsm6dso16is_ispu_bdu_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ia_ispu_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t lsm6dso16is_ia_ispu_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; @@ -2783,7 +2881,7 @@ int32_t lsm6dso16is_ia_ispu_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ispu_write_dummy_cfg(stmdev_ctx_t *ctx, uint8_t offset, +int32_t lsm6dso16is_ispu_write_dummy_cfg(const stmdev_ctx_t *ctx, uint8_t offset, uint8_t *val, uint8_t len) { int32_t ret; @@ -2809,7 +2907,7 @@ int32_t lsm6dso16is_ispu_write_dummy_cfg(stmdev_ctx_t *ctx, uint8_t offset, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ispu_read_dummy_cfg(stmdev_ctx_t *ctx, uint8_t offset, +int32_t lsm6dso16is_ispu_read_dummy_cfg(const stmdev_ctx_t *ctx, uint8_t offset, uint8_t *val, uint8_t len) { int32_t ret; @@ -2833,17 +2931,23 @@ int32_t lsm6dso16is_ispu_read_dummy_cfg(stmdev_ctx_t *ctx, uint8_t offset, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ispu_boot_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_ispu_boot_set(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_boot_latched_t val) { lsm6dso16is_ispu_config_t ispu_config; int32_t ret; ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } ispu_config.ispu_rst_n = (uint8_t)val; ispu_config.clk_dis = (uint8_t)val; @@ -2863,17 +2967,23 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ispu_boot_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_ispu_boot_get(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_boot_latched_t *val) { lsm6dso16is_ispu_config_t ispu_config; int32_t ret; ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } *val = LSM6DSO16IS_ISPU_TURN_OFF; if (ispu_config.ispu_rst_n == 1U || ispu_config.clk_dis == 1U) @@ -2895,17 +3005,23 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ispu_int_latched_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_ispu_int_latched_set(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_int_latched_t val) { lsm6dso16is_ispu_config_t ispu_config; int32_t ret; ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } ispu_config.latched = ((uint8_t)val & 0x1U); ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1); @@ -2924,7 +3040,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ispu_int_latched_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_ispu_int_latched_get(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_int_latched_t *val) { lsm6dso16is_ispu_config_t ispu_config; @@ -2933,7 +3049,10 @@ int32_t lsm6dso16is_ispu_int_latched_get(stmdev_ctx_t *ctx, ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); ret += lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_CONFIG, (uint8_t *)&ispu_config, 1); ret += lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch ((ispu_config.latched)) { @@ -2961,14 +3080,17 @@ int32_t lsm6dso16is_ispu_int_latched_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ispu_get_boot_status(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_ispu_get_boot_status(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_boot_end_t *val) { lsm6dso16is_ispu_status_t ispu_boot_status; int32_t ret; ret = lsm6dso16is_mem_bank_set(ctx, LSM6DSO16IS_ISPU_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dso16is_read_reg(ctx, LSM6DSO16IS_ISPU_STATUS, (uint8_t *)&ispu_boot_status, 1); *val = (lsm6dso16is_ispu_boot_end_t)ispu_boot_status.boot_end; @@ -2977,7 +3099,7 @@ int32_t lsm6dso16is_ispu_get_boot_status(stmdev_ctx_t *ctx, return ret; } -static int32_t lsm6dso16is_ispu_sel_memory_addr(stmdev_ctx_t *ctx, uint16_t mem_addr) +static int32_t lsm6dso16is_ispu_sel_memory_addr(const stmdev_ctx_t *ctx, uint16_t mem_addr) { uint8_t mem_addr_l, mem_addr_h; int32_t ret = 0; @@ -2985,9 +3107,9 @@ static int32_t lsm6dso16is_ispu_sel_memory_addr(stmdev_ctx_t *ctx, uint16_t mem_ mem_addr_l = (uint8_t)(mem_addr & 0xFFU); mem_addr_h = (uint8_t)(mem_addr / 256U); ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_MEM_ADDR1, - (uint8_t *)&mem_addr_h, 1); + (uint8_t *)&mem_addr_h, 1); ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_MEM_ADDR0, - (uint8_t *)&mem_addr_l, 1); + (uint8_t *)&mem_addr_l, 1); return ret; } @@ -3003,7 +3125,7 @@ static int32_t lsm6dso16is_ispu_sel_memory_addr(stmdev_ctx_t *ctx, uint16_t mem_ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ispu_write_memory(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_ispu_write_memory(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_memory_type_t mem_sel, uint16_t mem_addr, uint8_t *mem_data, uint16_t len) { @@ -3054,9 +3176,11 @@ int32_t lsm6dso16is_ispu_write_memory(stmdev_ctx_t *ctx, { ret += lsm6dso16is_ispu_sel_memory_addr(ctx, addr_s[i]); ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_MEM_DATA, &mem_data[k], len_s[i]); - k+=len_s[i]; + k += len_s[i]; } - } else { + } + else + { /* select memory address */ ret += lsm6dso16is_ispu_sel_memory_addr(ctx, mem_addr); ret += lsm6dso16is_write_reg(ctx, LSM6DSO16IS_ISPU_MEM_DATA, &mem_data[0], len); @@ -3083,7 +3207,7 @@ int32_t lsm6dso16is_ispu_write_memory(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ispu_read_memory(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_ispu_read_memory(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_memory_type_t mem_sel, uint16_t mem_addr, uint8_t *mem_data, uint16_t len) { @@ -3132,7 +3256,7 @@ int32_t lsm6dso16is_ispu_read_memory(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ispu_write_flags(stmdev_ctx_t *ctx, uint16_t data) +int32_t lsm6dso16is_ispu_write_flags(const stmdev_ctx_t *ctx, uint16_t data) { lsm6dso16is_ispu_if2s_flag_l_t flag_l; lsm6dso16is_ispu_if2s_flag_h_t flag_h; @@ -3163,7 +3287,7 @@ int32_t lsm6dso16is_ispu_write_flags(stmdev_ctx_t *ctx, uint16_t data) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ispu_read_flags(stmdev_ctx_t *ctx, uint16_t *data) +int32_t lsm6dso16is_ispu_read_flags(const stmdev_ctx_t *ctx, uint16_t *data) { uint8_t buff[2]; int32_t ret; @@ -3189,7 +3313,7 @@ int32_t lsm6dso16is_ispu_read_flags(stmdev_ctx_t *ctx, uint16_t *data) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ispu_clear_flags(stmdev_ctx_t *ctx) +int32_t lsm6dso16is_ispu_clear_flags(const stmdev_ctx_t *ctx) { uint8_t data = 1; int32_t ret; @@ -3213,7 +3337,7 @@ int32_t lsm6dso16is_ispu_clear_flags(stmdev_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ispu_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_ispu_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, uint8_t len) { @@ -3239,7 +3363,7 @@ int32_t lsm6dso16is_ispu_read_data_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ispu_int1_ctrl_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t lsm6dso16is_ispu_int1_ctrl_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; @@ -3269,7 +3393,7 @@ int32_t lsm6dso16is_ispu_int1_ctrl_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ispu_int1_ctrl_set(stmdev_ctx_t *ctx, uint32_t val) +int32_t lsm6dso16is_ispu_int1_ctrl_set(const stmdev_ctx_t *ctx, uint32_t val) { lsm6dso16is_ispu_int1_ctrl0_t int1_ctrl0; lsm6dso16is_ispu_int1_ctrl1_t int1_ctrl1; @@ -3311,7 +3435,7 @@ int32_t lsm6dso16is_ispu_int1_ctrl_set(stmdev_ctx_t *ctx, uint32_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ispu_int2_ctrl_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t lsm6dso16is_ispu_int2_ctrl_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; @@ -3341,7 +3465,7 @@ int32_t lsm6dso16is_ispu_int2_ctrl_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ispu_int2_ctrl_set(stmdev_ctx_t *ctx, uint32_t val) +int32_t lsm6dso16is_ispu_int2_ctrl_set(const stmdev_ctx_t *ctx, uint32_t val) { lsm6dso16is_ispu_int2_ctrl0_t int2_ctrl0; lsm6dso16is_ispu_int2_ctrl1_t int2_ctrl1; @@ -3383,7 +3507,7 @@ int32_t lsm6dso16is_ispu_int2_ctrl_set(stmdev_ctx_t *ctx, uint32_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ispu_int_status_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t lsm6dso16is_ispu_int_status_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; @@ -3413,7 +3537,7 @@ int32_t lsm6dso16is_ispu_int_status_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ispu_algo_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t lsm6dso16is_ispu_algo_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; @@ -3443,7 +3567,7 @@ int32_t lsm6dso16is_ispu_algo_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso16is_ispu_algo_set(stmdev_ctx_t *ctx, uint32_t val) +int32_t lsm6dso16is_ispu_algo_set(const stmdev_ctx_t *ctx, uint32_t val) { lsm6dso16is_ispu_algo0_t algo0; lsm6dso16is_ispu_algo1_t algo1; diff --git a/sensor/stmemsc/lsm6dso16is_STdC/driver/lsm6dso16is_reg.h b/sensor/stmemsc/lsm6dso16is_STdC/driver/lsm6dso16is_reg.h index c9a00fb8..eee3406b 100644 --- a/sensor/stmemsc/lsm6dso16is_STdC/driver/lsm6dso16is_reg.h +++ b/sensor/stmemsc/lsm6dso16is_STdC/driver/lsm6dso16is_reg.h @@ -2315,10 +2315,10 @@ typedef union * them with a custom implementation. */ -int32_t lsm6dso16is_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm6dso16is_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lsm6dso16is_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm6dso16is_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -2341,36 +2341,36 @@ typedef enum LSM6DSO16IS_SENSOR_HUB_MEM_BANK = 0x2, LSM6DSO16IS_ISPU_MEM_BANK = 0x3, } lsm6dso16is_mem_bank_t; -int32_t lsm6dso16is_mem_bank_set(stmdev_ctx_t *ctx, lsm6dso16is_mem_bank_t val); -int32_t lsm6dso16is_mem_bank_get(stmdev_ctx_t *ctx, lsm6dso16is_mem_bank_t *val); +int32_t lsm6dso16is_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dso16is_mem_bank_t val); +int32_t lsm6dso16is_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dso16is_mem_bank_t *val); typedef enum { LSM6DSO16IS_DRDY_LATCHED = 0x0, LSM6DSO16IS_DRDY_PULSED = 0x1, } lsm6dso16is_data_ready_mode_t; -int32_t lsm6dso16is_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm6dso16is_data_ready_mode_t val); -int32_t lsm6dso16is_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm6dso16is_data_ready_mode_t *val); -int32_t lsm6dso16is_device_id_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso16is_device_id_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso16is_device_id_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso16is_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso16is_software_reset(stmdev_ctx_t *ctx); +int32_t lsm6dso16is_software_reset(const stmdev_ctx_t *ctx); -int32_t lsm6dso16is_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso16is_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso16is_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso16is_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSO16IS_HIGH_PERFOMANCE_MODE_ENABLED = 0x0, LSM6DSO16IS_HIGH_PERFOMANCE_MODE_DISABLED = 0x1, } lsm6dso16is_hm_mode_t; -int32_t lsm6dso16is_xl_hm_mode_set(stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t val); -int32_t lsm6dso16is_xl_hm_mode_get(stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t *val); -int32_t lsm6dso16is_gy_hm_mode_set(stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t val); -int32_t lsm6dso16is_gy_hm_mode_get(stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t *val); +int32_t lsm6dso16is_xl_hm_mode_set(const stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t val); +int32_t lsm6dso16is_xl_hm_mode_get(const stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t *val); +int32_t lsm6dso16is_gy_hm_mode_set(const stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t val); +int32_t lsm6dso16is_gy_hm_mode_get(const stmdev_ctx_t *ctx, lsm6dso16is_hm_mode_t *val); typedef enum { @@ -2379,9 +2379,9 @@ typedef enum LSM6DSO16IS_4g = 0x2, LSM6DSO16IS_8g = 0x3, } lsm6dso16is_xl_full_scale_t; -int32_t lsm6dso16is_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dso16is_xl_full_scale_t val); -int32_t lsm6dso16is_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dso16is_xl_full_scale_t *val); typedef enum @@ -2409,9 +2409,9 @@ typedef enum LSM6DSO16IS_XL_ODR_AT_6667Hz_LP = 0x1a, LSM6DSO16IS_XL_ODR_AT_1Hz6_LP = 0x1b, } lsm6dso16is_xl_data_rate_t; -int32_t lsm6dso16is_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso16is_xl_data_rate_t val); -int32_t lsm6dso16is_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso16is_xl_data_rate_t *val); typedef enum @@ -2422,9 +2422,9 @@ typedef enum LSM6DSO16IS_2000dps = 0x3, LSM6DSO16IS_125dps = 0x10, } lsm6dso16is_gy_full_scale_t; -int32_t lsm6dso16is_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dso16is_gy_full_scale_t val); -int32_t lsm6dso16is_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dso16is_gy_full_scale_t *val); typedef enum @@ -2451,24 +2451,24 @@ typedef enum LSM6DSO16IS_GY_ODR_AT_3333Hz_LP = 0x19, LSM6DSO16IS_GY_ODR_AT_6667Hz_LP = 0x1a, } lsm6dso16is_gy_data_rate_t; -int32_t lsm6dso16is_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_gy_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso16is_gy_data_rate_t val); -int32_t lsm6dso16is_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso16is_gy_data_rate_t *val); -int32_t lsm6dso16is_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso16is_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso16is_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso16is_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso16is_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso16is_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso16is_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso16is_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSO16IS_SLEEP_G_ENABLE = 0x0, LSM6DSO16IS_SLEEP_G_DISABLE = 0x1, } lsm6dso16is_sleep_t; -int32_t lsm6dso16is_sleep_set(stmdev_ctx_t *ctx, lsm6dso16is_sleep_t val); -int32_t lsm6dso16is_sleep_get(stmdev_ctx_t *ctx, lsm6dso16is_sleep_t *val); +int32_t lsm6dso16is_sleep_set(const stmdev_ctx_t *ctx, lsm6dso16is_sleep_t val); +int32_t lsm6dso16is_sleep_get(const stmdev_ctx_t *ctx, lsm6dso16is_sleep_t *val); typedef enum { @@ -2476,9 +2476,9 @@ typedef enum LSM6DSO16IS_XL_ST_POSITIVE = 0x1, LSM6DSO16IS_XL_ST_NEGATIVE = 0x2, } lsm6dso16is_xl_self_test_t; -int32_t lsm6dso16is_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dso16is_xl_self_test_t val); -int32_t lsm6dso16is_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dso16is_xl_self_test_t *val); typedef enum @@ -2487,36 +2487,36 @@ typedef enum LSM6DSO16IS_GY_ST_POSITIVE = 0x1, LSM6DSO16IS_GY_ST_NEGATIVE = 0x3, } lsm6dso16is_gy_self_test_t; -int32_t lsm6dso16is_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dso16is_gy_self_test_t val); -int32_t lsm6dso16is_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dso16is_gy_self_test_t *val); -int32_t lsm6dso16is_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso16is_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso16is_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso16is_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSO16IS_SPI_4_WIRE = 0x0, LSM6DSO16IS_SPI_3_WIRE = 0x1, } lsm6dso16is_spi_mode_t; -int32_t lsm6dso16is_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso16is_spi_mode_t val); -int32_t lsm6dso16is_spi_mode_get(stmdev_ctx_t *ctx, lsm6dso16is_spi_mode_t *val); +int32_t lsm6dso16is_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dso16is_spi_mode_t val); +int32_t lsm6dso16is_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dso16is_spi_mode_t *val); typedef enum { LSM6DSO16IS_I2C_ENABLE = 0x0, LSM6DSO16IS_I2C_DISABLE = 0x1, } lsm6dso16is_ui_i2c_mode_t; -int32_t lsm6dso16is_ui_i2c_mode_set(stmdev_ctx_t *ctx, lsm6dso16is_ui_i2c_mode_t val); -int32_t lsm6dso16is_ui_i2c_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_ui_i2c_mode_set(const stmdev_ctx_t *ctx, lsm6dso16is_ui_i2c_mode_t val); +int32_t lsm6dso16is_ui_i2c_mode_get(const stmdev_ctx_t *ctx, lsm6dso16is_ui_i2c_mode_t *val); -int32_t lsm6dso16is_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso16is_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso16is_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso16is_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso16is_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); +int32_t lsm6dso16is_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); typedef struct { @@ -2526,9 +2526,9 @@ typedef struct uint8_t sh_endop : 1; uint8_t ispu : 1; } lsm6dso16is_pin_int1_route_t; -int32_t lsm6dso16is_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm6dso16is_pin_int1_route_t val); -int32_t lsm6dso16is_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm6dso16is_pin_int1_route_t *val); typedef struct @@ -2540,9 +2540,9 @@ typedef struct uint8_t ispu_sleep : 1; uint8_t ispu : 1; } lsm6dso16is_pin_int2_route_t; -int32_t lsm6dso16is_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm6dso16is_pin_int2_route_t val); -int32_t lsm6dso16is_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_pin_int2_route_get(const stmdev_ctx_t *ctx, lsm6dso16is_pin_int2_route_t *val); typedef enum @@ -2550,9 +2550,9 @@ typedef enum LSM6DSO16IS_PUSH_PULL = 0x0, LSM6DSO16IS_OPEN_DRAIN = 0x1, } lsm6dso16is_int_pin_mode_t; -int32_t lsm6dso16is_int_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_int_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dso16is_int_pin_mode_t val); -int32_t lsm6dso16is_int_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_int_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dso16is_int_pin_mode_t *val); typedef enum @@ -2560,9 +2560,9 @@ typedef enum LSM6DSO16IS_ACTIVE_HIGH = 0x0, LSM6DSO16IS_ACTIVE_LOW = 0x1, } lsm6dso16is_pin_polarity_t; -int32_t lsm6dso16is_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_pin_polarity_set(const stmdev_ctx_t *ctx, lsm6dso16is_pin_polarity_t val); -int32_t lsm6dso16is_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_pin_polarity_get(const stmdev_ctx_t *ctx, lsm6dso16is_pin_polarity_t *val); typedef struct @@ -2578,31 +2578,31 @@ typedef struct uint8_t sh_wr_once : 1; uint32_t ispu : 30; } lsm6dso16is_all_sources_t; -int32_t lsm6dso16is_all_sources_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_all_sources_get(const stmdev_ctx_t *ctx, lsm6dso16is_all_sources_t *val); -int32_t lsm6dso16is_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_status_reg_get(const stmdev_ctx_t *ctx, lsm6dso16is_status_reg_t *val); -int32_t lsm6dso16is_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso16is_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso16is_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso16is_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dso16is_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dso16is_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dso16is_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dso16is_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dso16is_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dso16is_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso16is_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso16is_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso16is_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso16is_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val, +int32_t lsm6dso16is_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, uint8_t len); typedef enum @@ -2612,30 +2612,30 @@ typedef enum LSM6DSO16IS_SLV_0_1_2 = 0x2, LSM6DSO16IS_SLV_0_1_2_3 = 0x3, } lsm6dso16is_sh_slave_connected_t; -int32_t lsm6dso16is_sh_slave_connected_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_sh_slave_connected_set(const stmdev_ctx_t *ctx, lsm6dso16is_sh_slave_connected_t val); -int32_t lsm6dso16is_sh_slave_connected_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_sh_slave_connected_get(const stmdev_ctx_t *ctx, lsm6dso16is_sh_slave_connected_t *val); -int32_t lsm6dso16is_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso16is_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso16is_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso16is_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso16is_sh_master_interface_pull_up_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_sh_master_interface_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso16is_sh_master_interface_pull_up_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_sh_master_interface_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso16is_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso16is_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso16is_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso16is_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSO16IS_SH_TRG_XL_GY_DRDY = 0x0, LSM6DSO16IS_SH_TRIG_INT2 = 0x1, } lsm6dso16is_sh_syncro_mode_t; -int32_t lsm6dso16is_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_sh_syncro_mode_set(const stmdev_ctx_t *ctx, lsm6dso16is_sh_syncro_mode_t val); -int32_t lsm6dso16is_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_sh_syncro_mode_get(const stmdev_ctx_t *ctx, lsm6dso16is_sh_syncro_mode_t *val); typedef enum @@ -2643,13 +2643,13 @@ typedef enum LSM6DSO16IS_EACH_SH_CYCLE = 0x0, LSM6DSO16IS_ONLY_FIRST_CYCLE = 0x1, } lsm6dso16is_sh_write_mode_t; -int32_t lsm6dso16is_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_sh_write_mode_set(const stmdev_ctx_t *ctx, lsm6dso16is_sh_write_mode_t val); -int32_t lsm6dso16is_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_sh_write_mode_get(const stmdev_ctx_t *ctx, lsm6dso16is_sh_write_mode_t *val); -int32_t lsm6dso16is_sh_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso16is_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso16is_sh_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso16is_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -2657,7 +2657,7 @@ typedef struct uint8_t slv0_subadd; uint8_t slv0_data; } lsm6dso16is_sh_cfg_write_t; -int32_t lsm6dso16is_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_sh_cfg_write(const stmdev_ctx_t *ctx, lsm6dso16is_sh_cfg_write_t *val); typedef enum { @@ -2666,9 +2666,9 @@ typedef enum LSM6DSO16IS_SH_26Hz = 0x2, LSM6DSO16IS_SH_12_5Hz = 0x3, } lsm6dso16is_sh_data_rate_t; -int32_t lsm6dso16is_sh_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_sh_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso16is_sh_data_rate_t val); -int32_t lsm6dso16is_sh_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_sh_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso16is_sh_data_rate_t *val); typedef struct @@ -2677,23 +2677,23 @@ typedef struct uint8_t slv_subadd; uint8_t slv_len; } lsm6dso16is_sh_cfg_read_t; -int32_t lsm6dso16is_sh_slv_cfg_read(stmdev_ctx_t *ctx, uint8_t idx, +int32_t lsm6dso16is_sh_slv_cfg_read(const stmdev_ctx_t *ctx, uint8_t idx, lsm6dso16is_sh_cfg_read_t *val); -int32_t lsm6dso16is_sh_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_sh_status_get(const stmdev_ctx_t *ctx, lsm6dso16is_status_master_t *val); -int32_t lsm6dso16is_ispu_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso16is_ispu_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso16is_ispu_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso16is_ispu_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSO16IS_ISPU_CLK_5MHz = 0x0, LSM6DSO16IS_ISPU_CLK_10MHz = 0x1, } lsm6dso16is_ispu_clock_sel_t; -int32_t lsm6dso16is_ispu_clock_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_ispu_clock_set(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_clock_sel_t val); -int32_t lsm6dso16is_ispu_clock_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_ispu_clock_get(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_clock_sel_t *val); typedef enum @@ -2710,9 +2710,9 @@ typedef enum LSM6DSO16IS_ISPU_ODR_AT_3333Hz = 0x9, LSM6DSO16IS_ISPU_ODR_AT_6667Hz = 0xa, } lsm6dso16is_ispu_data_rate_t; -int32_t lsm6dso16is_ispu_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_ispu_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_data_rate_t val); -int32_t lsm6dso16is_ispu_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_ispu_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_data_rate_t *val); typedef enum @@ -2722,14 +2722,14 @@ typedef enum LSM6DSO16IS_ISPU_BDU_ON_2B_2B = 0x2, LSM6DSO16IS_ISPU_BDU_ON_4B_4B = 0x3, } lsm6dso16is_ispu_bdu_t; -int32_t lsm6dso16is_ispu_bdu_set(stmdev_ctx_t *ctx, lsm6dso16is_ispu_bdu_t val); -int32_t lsm6dso16is_ispu_bdu_get(stmdev_ctx_t *ctx, lsm6dso16is_ispu_bdu_t *val); +int32_t lsm6dso16is_ispu_bdu_set(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_bdu_t val); +int32_t lsm6dso16is_ispu_bdu_get(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_bdu_t *val); -int32_t lsm6dso16is_ia_ispu_get(stmdev_ctx_t *ctx, uint32_t *val); +int32_t lsm6dso16is_ia_ispu_get(const stmdev_ctx_t *ctx, uint32_t *val); -int32_t lsm6dso16is_ispu_write_dummy_cfg(stmdev_ctx_t *ctx, uint8_t offset, +int32_t lsm6dso16is_ispu_write_dummy_cfg(const stmdev_ctx_t *ctx, uint8_t offset, uint8_t *val, uint8_t len); -int32_t lsm6dso16is_ispu_read_dummy_cfg(stmdev_ctx_t *ctx, uint8_t offset, +int32_t lsm6dso16is_ispu_read_dummy_cfg(const stmdev_ctx_t *ctx, uint8_t offset, uint8_t *val, uint8_t len); typedef enum @@ -2737,9 +2737,9 @@ typedef enum LSM6DSO16IS_ISPU_TURN_ON = 0x0, LSM6DSO16IS_ISPU_TURN_OFF = 0x1, } lsm6dso16is_ispu_boot_latched_t; -int32_t lsm6dso16is_ispu_boot_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_ispu_boot_set(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_boot_latched_t val); -int32_t lsm6dso16is_ispu_boot_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_ispu_boot_get(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_boot_latched_t *val); typedef enum @@ -2747,9 +2747,9 @@ typedef enum LSM6DSO16IS_ISPU_INT_PULSED = 0x0, LSM6DSO16IS_ISPU_INT_LATCHED = 0x1, } lsm6dso16is_ispu_int_latched_t; -int32_t lsm6dso16is_ispu_int_latched_set(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_ispu_int_latched_set(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_int_latched_t val); -int32_t lsm6dso16is_ispu_int_latched_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_ispu_int_latched_get(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_int_latched_t *val); typedef enum @@ -2757,7 +2757,7 @@ typedef enum LSM6DSO16IS_ISPU_BOOT_IN_PROGRESS = 0x0, LSM6DSO16IS_ISPU_BOOT_ENDED = 0x1, } lsm6dso16is_ispu_boot_end_t; -int32_t lsm6dso16is_ispu_get_boot_status(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_ispu_get_boot_status(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_boot_end_t *val); typedef enum @@ -2765,34 +2765,34 @@ typedef enum LSM6DSO16IS_ISPU_DATA_RAM_MEMORY = 0x0, LSM6DSO16IS_ISPU_PROGRAM_RAM_MEMORY = 0x1, } lsm6dso16is_ispu_memory_type_t; -int32_t lsm6dso16is_ispu_read_memory_enable(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_ispu_read_memory_enable(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_memory_type_t val); -int32_t lsm6dso16is_ispu_read_memory_disable(stmdev_ctx_t *ctx); +int32_t lsm6dso16is_ispu_read_memory_disable(const stmdev_ctx_t *ctx); -int32_t lsm6dso16is_ispu_write_memory(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_ispu_write_memory(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_memory_type_t mem_sel, uint16_t mem_addr, uint8_t *mem_data, uint16_t len); -int32_t lsm6dso16is_ispu_read_memory(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_ispu_read_memory(const stmdev_ctx_t *ctx, lsm6dso16is_ispu_memory_type_t mem_sel, uint16_t mem_addr, uint8_t *mem_data, uint16_t len); -int32_t lsm6dso16is_ispu_write_flags(stmdev_ctx_t *ctx, uint16_t data); -int32_t lsm6dso16is_ispu_read_flags(stmdev_ctx_t *ctx, uint16_t *data); -int32_t lsm6dso16is_ispu_clear_flags(stmdev_ctx_t *ctx); +int32_t lsm6dso16is_ispu_write_flags(const stmdev_ctx_t *ctx, uint16_t data); +int32_t lsm6dso16is_ispu_read_flags(const stmdev_ctx_t *ctx, uint16_t *data); +int32_t lsm6dso16is_ispu_clear_flags(const stmdev_ctx_t *ctx); -int32_t lsm6dso16is_ispu_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dso16is_ispu_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, uint8_t len); -int32_t lsm6dso16is_ispu_int1_ctrl_get(stmdev_ctx_t *ctx, uint32_t *val); -int32_t lsm6dso16is_ispu_int1_ctrl_set(stmdev_ctx_t *ctx, uint32_t val); -int32_t lsm6dso16is_ispu_int2_ctrl_get(stmdev_ctx_t *ctx, uint32_t *val); -int32_t lsm6dso16is_ispu_int2_ctrl_set(stmdev_ctx_t *ctx, uint32_t val); +int32_t lsm6dso16is_ispu_int1_ctrl_get(const stmdev_ctx_t *ctx, uint32_t *val); +int32_t lsm6dso16is_ispu_int1_ctrl_set(const stmdev_ctx_t *ctx, uint32_t val); +int32_t lsm6dso16is_ispu_int2_ctrl_get(const stmdev_ctx_t *ctx, uint32_t *val); +int32_t lsm6dso16is_ispu_int2_ctrl_set(const stmdev_ctx_t *ctx, uint32_t val); -int32_t lsm6dso16is_ispu_int_status_get(stmdev_ctx_t *ctx, uint32_t *val); +int32_t lsm6dso16is_ispu_int_status_get(const stmdev_ctx_t *ctx, uint32_t *val); -int32_t lsm6dso16is_ispu_algo_get(stmdev_ctx_t *ctx, uint32_t *val); -int32_t lsm6dso16is_ispu_algo_set(stmdev_ctx_t *ctx, uint32_t val); +int32_t lsm6dso16is_ispu_algo_get(const stmdev_ctx_t *ctx, uint32_t *val); +int32_t lsm6dso16is_ispu_algo_set(const stmdev_ctx_t *ctx, uint32_t val); /** * @} * diff --git a/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.c b/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.c index e7d294f1..9404b17f 100644 --- a/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.c +++ b/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.c @@ -46,12 +46,14 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm6dso32_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm6dso32_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +69,14 @@ int32_t __weak lsm6dso32_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm6dso32_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm6dso32_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -164,7 +168,7 @@ float_t lsm6dso32_from_lsb_to_nsec(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dso32_fs_xl_t val) { lsm6dso32_ctrl1_xl_t ctrl1_xl; @@ -191,7 +195,7 @@ int32_t lsm6dso32_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dso32_fs_xl_t *val) { lsm6dso32_ctrl1_xl_t reg; @@ -234,7 +238,7 @@ int32_t lsm6dso32_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso32_odr_xl_t val) { lsm6dso32_ctrl1_xl_t ctrl1_xl; @@ -308,7 +312,7 @@ int32_t lsm6dso32_xl_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso32_odr_xl_t *val) { lsm6dso32_ctrl1_xl_t ctrl1_xl; @@ -343,8 +347,8 @@ int32_t lsm6dso32_xl_data_rate_get(stmdev_ctx_t *ctx, *val = LSM6DSO32_XL_ODR_OFF; break; - case LSM6DSO32_XL_ODR_6Hz5_LOW_PW: - *val = LSM6DSO32_XL_ODR_6Hz5_LOW_PW; + case LSM6DSO32_XL_ODR_1Hz6_LOW_PW: + *val = LSM6DSO32_XL_ODR_1Hz6_LOW_PW; break; case LSM6DSO32_XL_ODR_12Hz5_LOW_PW: @@ -407,8 +411,8 @@ int32_t lsm6dso32_xl_data_rate_get(stmdev_ctx_t *ctx, *val = LSM6DSO32_XL_ODR_6667Hz_HIGH_PERF; break; - case LSM6DSO32_XL_ODR_6Hz5_ULTRA_LOW_PW: - *val = LSM6DSO32_XL_ODR_6Hz5_ULTRA_LOW_PW; + case LSM6DSO32_XL_ODR_1Hz6_ULTRA_LOW_PW: + *val = LSM6DSO32_XL_ODR_1Hz6_ULTRA_LOW_PW; break; case LSM6DSO32_XL_ODR_12Hz5_ULTRA_LOW_PW: @@ -447,7 +451,7 @@ int32_t lsm6dso32_xl_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dso32_fs_g_t val) { lsm6dso32_ctrl2_g_t reg; @@ -472,7 +476,7 @@ int32_t lsm6dso32_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dso32_fs_g_t *val) { lsm6dso32_ctrl2_g_t reg; @@ -518,7 +522,7 @@ int32_t lsm6dso32_gy_full_scale_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_gy_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso32_odr_g_t val) { lsm6dso32_ctrl2_g_t ctrl2_g; @@ -566,7 +570,7 @@ int32_t lsm6dso32_gy_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso32_odr_g_t *val) { lsm6dso32_ctrl2_g_t ctrl2_g; @@ -662,7 +666,7 @@ int32_t lsm6dso32_gy_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_block_data_update_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_ctrl3_c_t reg; @@ -687,7 +691,7 @@ int32_t lsm6dso32_block_data_update_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_ctrl3_c_t reg; @@ -708,7 +712,7 @@ int32_t lsm6dso32_block_data_update_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_offset_weight_set(const stmdev_ctx_t *ctx, lsm6dso32_usr_off_w_t val) { lsm6dso32_ctrl6_c_t reg; @@ -734,7 +738,7 @@ int32_t lsm6dso32_xl_offset_weight_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_offset_weight_get(const stmdev_ctx_t *ctx, lsm6dso32_usr_off_w_t *val) { lsm6dso32_ctrl6_c_t reg; @@ -770,7 +774,7 @@ int32_t lsm6dso32_xl_offset_weight_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_all_sources_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_all_sources_get(const stmdev_ctx_t *ctx, lsm6dso32_all_sources_t *val) { int32_t ret; @@ -841,7 +845,7 @@ int32_t lsm6dso32_all_sources_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_status_reg_get(const stmdev_ctx_t *ctx, lsm6dso32_status_reg_t *val) { int32_t ret; @@ -859,7 +863,7 @@ int32_t lsm6dso32_status_reg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_status_reg_t reg; @@ -879,7 +883,7 @@ int32_t lsm6dso32_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_status_reg_t reg; @@ -899,7 +903,7 @@ int32_t lsm6dso32_gy_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_status_reg_t reg; @@ -921,7 +925,7 @@ int32_t lsm6dso32_temp_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_usr_offset_x_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -941,7 +945,7 @@ int32_t lsm6dso32_xl_usr_offset_x_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_usr_offset_x_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -961,7 +965,7 @@ int32_t lsm6dso32_xl_usr_offset_x_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_usr_offset_y_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -981,7 +985,7 @@ int32_t lsm6dso32_xl_usr_offset_y_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_usr_offset_y_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1001,7 +1005,7 @@ int32_t lsm6dso32_xl_usr_offset_y_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_usr_offset_z_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1021,7 +1025,7 @@ int32_t lsm6dso32_xl_usr_offset_z_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_usr_offset_z_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1039,7 +1043,7 @@ int32_t lsm6dso32_xl_usr_offset_z_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_ctrl7_g_t reg; int32_t ret; @@ -1063,7 +1067,7 @@ int32_t lsm6dso32_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_ctrl7_g_t reg; int32_t ret; @@ -1095,7 +1099,7 @@ int32_t lsm6dso32_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_ctrl10_c_t reg; int32_t ret; @@ -1119,7 +1123,7 @@ int32_t lsm6dso32_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_ctrl10_c_t reg; int32_t ret; @@ -1140,7 +1144,7 @@ int32_t lsm6dso32_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t lsm6dso32_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; @@ -1175,7 +1179,7 @@ int32_t lsm6dso32_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_rounding_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_rounding_t val) { lsm6dso32_ctrl5_c_t reg; @@ -1200,7 +1204,7 @@ int32_t lsm6dso32_rounding_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_rounding_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_rounding_t *val) { lsm6dso32_ctrl5_c_t reg; @@ -1244,7 +1248,7 @@ int32_t lsm6dso32_rounding_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dso32_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1265,7 +1269,7 @@ int32_t lsm6dso32_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_angular_rate_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -1291,7 +1295,7 @@ int32_t lsm6dso32_angular_rate_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -1316,7 +1320,7 @@ int32_t lsm6dso32_acceleration_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dso32_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1333,7 +1337,7 @@ int32_t lsm6dso32_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_number_of_steps_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_number_of_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -1363,7 +1367,7 @@ int32_t lsm6dso32_number_of_steps_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_steps_reset(stmdev_ctx_t *ctx) +int32_t lsm6dso32_steps_reset(const stmdev_ctx_t *ctx) { lsm6dso32_emb_func_src_t reg; int32_t ret; @@ -1413,7 +1417,7 @@ int32_t lsm6dso32_steps_reset(stmdev_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_internal_freq_fine_t reg; int32_t ret; @@ -1441,7 +1445,7 @@ int32_t lsm6dso32_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_internal_freq_fine_t reg; int32_t ret; @@ -1463,7 +1467,7 @@ int32_t lsm6dso32_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_mem_bank_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dso32_reg_access_t val) { lsm6dso32_func_cfg_access_t reg; @@ -1491,7 +1495,7 @@ int32_t lsm6dso32_mem_bank_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_mem_bank_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dso32_reg_access_t *val) { lsm6dso32_func_cfg_access_t reg; @@ -1531,73 +1535,9 @@ int32_t lsm6dso32_mem_bank_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_ln_pg_write_byte(stmdev_ctx_t *ctx, - uint16_t address, - uint8_t *val) +int32_t lsm6dso32_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val) { - lsm6dso32_page_rw_t page_rw; - lsm6dso32_page_sel_t page_sel; - lsm6dso32_page_address_t page_address; - int32_t ret; - - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK); - - if (ret == 0) - { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); - } - - if (ret == 0) - { - page_rw.page_rw = 0x02; /* page_write enable */ - ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, - (uint8_t *) &page_rw, 1); - } - - if (ret == 0) - { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL, - (uint8_t *) &page_sel, 1); - } - - if (ret == 0) - { - page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU); - page_sel.not_used_01 = 1; - ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL, - (uint8_t *) &page_sel, 1); - } - - if (ret == 0) - { - page_address.page_addr = (uint8_t)address & 0xFFU; - ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); - } - - if (ret == 0) - { - ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_VALUE, val, 1); - } - - if (ret == 0) - { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); - } - - if (ret == 0) - { - page_rw.page_rw = 0x00; /* page_write disable */ - ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, - (uint8_t *) &page_rw, 1); - } - - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } - - return ret; + return lsm6dso32_ln_pg_write(ctx, address, val, 1); } /** @@ -1610,99 +1550,75 @@ int32_t lsm6dso32_ln_pg_write_byte(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dso32_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len) { lsm6dso32_page_rw_t page_rw; lsm6dso32_page_sel_t page_sel; lsm6dso32_page_address_t page_address; + uint8_t msb; + uint8_t lsb; int32_t ret; - - uint8_t msb, lsb; uint8_t i ; + msb = ((uint8_t)(address >> 8) & 0x0FU); lsb = (uint8_t)address & 0xFFU; + ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK); + if (ret != 0) { return ret; } - if (ret == 0) - { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); - } + /* set page write */ + ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); + page_rw.page_rw = 0x02; /* page_write enable*/ + ret += lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); + if (ret != 0) { goto exit; } - if (ret == 0) - { - page_rw.page_rw = 0x02; /* page_write enable*/ - ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, - (uint8_t *) &page_rw, 1); - } + /* select page */ + ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *) &page_sel, 1); + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; + ret += lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *) &page_sel, 1); + if (ret != 0) { goto exit; } - if (ret == 0) - { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL, - (uint8_t *) &page_sel, 1); - } + /* set page addr */ + page_address.page_addr = lsb; + ret += lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) { goto exit; } - if (ret == 0) + for (i = 0; ((i < len) && (ret == 0)); i++) { - page_sel.page_sel = msb; - page_sel.not_used_01 = 1; - ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL, - (uint8_t *) &page_sel, 1); - } + ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_VALUE, &buf[i], 1); + if (ret != 0) { goto exit; } - if (ret == 0) - { - page_address.page_addr = lsb; - ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); - } + lsb++; - if (ret == 0) - { - for (i = 0; ((i < len) && (ret == 0)); i++) + /* Check if page wrap */ + if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) { - ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_VALUE, &buf[i], 1); - - /* Check if page wrap */ - if ((lsb == 0x00U) && (ret == 0)) - { - lsb++; - msb++; - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL, - (uint8_t *)&page_sel, 1); - - if (ret == 0) - { - page_sel.page_sel = msb; - page_sel.not_used_01 = 1; - ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL, - (uint8_t *)&page_sel, 1); - } - } + msb++; + ret += lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) { goto exit; } + + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; + ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) { goto exit; } } - - page_sel.page_sel = 0; - page_sel.not_used_01 = 1; - ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL, - (uint8_t *) &page_sel, 1); } - if (ret == 0) - { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); - } + page_sel.page_sel = 0; + page_sel.not_used_01 = 1; + ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *) &page_sel, 1); + if (ret != 0) { goto exit; } - if (ret == 0) - { - page_rw.page_rw = 0x00; /* page_write disable */ - ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, - (uint8_t *) &page_rw, 1); - } + /* unset page write */ + ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); + page_rw.page_rw = 0x00; /* page_write disable */ + ret += lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } +exit: + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -1716,70 +1632,80 @@ int32_t lsm6dso32_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t address, - uint8_t *val) +int32_t lsm6dso32_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val) +{ + return lsm6dso32_ln_pg_read(ctx, address, val, 1); +} + +int32_t lsm6dso32_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, + uint8_t len) { lsm6dso32_page_rw_t page_rw; lsm6dso32_page_sel_t page_sel; lsm6dso32_page_address_t page_address; + uint8_t msb; + uint8_t lsb; int32_t ret; + uint8_t i ; + + msb = ((uint8_t)(address >> 8) & 0x0FU); + lsb = (uint8_t)address & 0xFFU; ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK); + if (ret != 0) { return ret; } - if (ret == 0) - { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); - } + /* set page write */ + ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); + page_rw.page_rw = 0x01; /* page_read enable*/ + ret += lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); + if (ret != 0) { goto exit; } - if (ret == 0) - { - page_rw.page_rw = 0x01; /* page_read enable*/ - ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, - (uint8_t *) &page_rw, 1); - } + /* select page */ + ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *) &page_sel, 1); + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; + ret += lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *) &page_sel, 1); + if (ret != 0) { goto exit; } - if (ret == 0) + for (i = 0; ((i < len) && (ret == 0)); i++) { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL, - (uint8_t *) &page_sel, 1); - } + /* set page addr */ + page_address.page_addr = lsb; + ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) { goto exit; } - if (ret == 0) - { - page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU); - page_sel.not_used_01 = 1; - ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL, - (uint8_t *) &page_sel, 1); - } + ret += lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_VALUE, &buf[i], 1); + if (ret != 0) { goto exit; } - if (ret == 0) - { - page_address.page_addr = (uint8_t)address & 0x00FFU; - ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_ADDRESS, - (uint8_t *)&page_address, 1); - } + lsb++; - if (ret == 0) - { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_VALUE, val, 2); + /* Check if page wrap */ + if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) + { + msb++; + ret += lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) { goto exit; } + + page_sel.page_sel = msb; + page_sel.not_used_01 = 1; + ret += lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) { goto exit; } + } } - if (ret == 0) - { - ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); - } + page_sel.page_sel = 0; + page_sel.not_used_01 = 1; + ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL, (uint8_t *) &page_sel, 1); + if (ret != 0) { goto exit; } - if (ret == 0) - { - page_rw.page_rw = 0x00; /* page_read disable */ - ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, - (uint8_t *) &page_rw, 1); - } + /* unset page write */ + ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); + page_rw.page_rw = 0x00; /* page_write disable */ + ret += lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1); - if (ret == 0) - { - ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); - } +exit: + ret += lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK); return ret; } @@ -1793,7 +1719,7 @@ int32_t lsm6dso32_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t address, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_dataready_pulsed_t val) { lsm6dso32_counter_bdr_reg1_t reg; @@ -1822,7 +1748,7 @@ int32_t lsm6dso32_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_dataready_pulsed_t *val) { lsm6dso32_counter_bdr_reg1_t reg; @@ -1857,7 +1783,7 @@ int32_t lsm6dso32_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dso32_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1875,7 +1801,7 @@ int32_t lsm6dso32_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_ctrl3_c_t reg; int32_t ret; @@ -1899,7 +1825,7 @@ int32_t lsm6dso32_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_ctrl3_c_t reg; int32_t ret; @@ -1919,7 +1845,7 @@ int32_t lsm6dso32_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_ctrl3_c_t reg; int32_t ret; @@ -1944,7 +1870,7 @@ int32_t lsm6dso32_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_ctrl3_c_t reg; int32_t ret; @@ -1963,7 +1889,7 @@ int32_t lsm6dso32_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_ctrl3_c_t reg; int32_t ret; @@ -1987,7 +1913,7 @@ int32_t lsm6dso32_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_ctrl3_c_t reg; int32_t ret; @@ -2006,7 +1932,7 @@ int32_t lsm6dso32_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dso32_st_xl_t val) { lsm6dso32_ctrl5_c_t reg; @@ -2031,7 +1957,7 @@ int32_t lsm6dso32_xl_self_test_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dso32_st_xl_t *val) { lsm6dso32_ctrl5_c_t reg; @@ -2069,7 +1995,7 @@ int32_t lsm6dso32_xl_self_test_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dso32_st_g_t val) { lsm6dso32_ctrl5_c_t reg; @@ -2094,7 +2020,7 @@ int32_t lsm6dso32_gy_self_test_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dso32_st_g_t *val) { lsm6dso32_ctrl5_c_t reg; @@ -2145,7 +2071,7 @@ int32_t lsm6dso32_gy_self_test_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_ctrl1_xl_t reg; int32_t ret; @@ -2169,7 +2095,7 @@ int32_t lsm6dso32_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_ctrl1_xl_t reg; int32_t ret; @@ -2190,7 +2116,7 @@ int32_t lsm6dso32_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_ctrl4_c_t reg; int32_t ret; @@ -2216,7 +2142,7 @@ int32_t lsm6dso32_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_ctrl4_c_t reg; int32_t ret; @@ -2236,7 +2162,7 @@ int32_t lsm6dso32_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_ctrl4_c_t reg; @@ -2262,7 +2188,7 @@ int32_t lsm6dso32_filter_settling_mask_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_ctrl4_c_t reg; @@ -2282,7 +2208,7 @@ int32_t lsm6dso32_filter_settling_mask_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dso32_ftype_t val) { lsm6dso32_ctrl6_c_t reg; @@ -2307,7 +2233,7 @@ int32_t lsm6dso32_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dso32_ftype_t *val) { lsm6dso32_ctrl6_c_t reg; @@ -2365,7 +2291,7 @@ int32_t lsm6dso32_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_ctrl8_xl_t reg; int32_t ret; @@ -2389,7 +2315,7 @@ int32_t lsm6dso32_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_ctrl8_xl_t reg; int32_t ret; @@ -2410,7 +2336,7 @@ int32_t lsm6dso32_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, lsm6dso32_hp_slope_xl_en_t val) { lsm6dso32_ctrl8_xl_t reg; @@ -2438,7 +2364,7 @@ int32_t lsm6dso32_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, lsm6dso32_hp_slope_xl_en_t *val) { lsm6dso32_ctrl8_xl_t reg; @@ -2560,7 +2486,7 @@ int32_t lsm6dso32_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_ctrl8_xl_t reg; int32_t ret; @@ -2586,7 +2512,7 @@ int32_t lsm6dso32_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_fast_settling_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_ctrl8_xl_t reg; @@ -2607,7 +2533,7 @@ int32_t lsm6dso32_xl_fast_settling_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dso32_slope_fds_t val) { lsm6dso32_tap_cfg0_t reg; @@ -2633,7 +2559,7 @@ int32_t lsm6dso32_xl_hp_path_internal_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dso32_slope_fds_t *val) { lsm6dso32_tap_cfg0_t reg; @@ -2668,7 +2594,7 @@ int32_t lsm6dso32_xl_hp_path_internal_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_gy_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dso32_hpm_g_t val) { lsm6dso32_ctrl7_g_t reg; @@ -2695,7 +2621,7 @@ int32_t lsm6dso32_gy_hp_path_internal_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_gy_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dso32_hpm_g_t *val) { lsm6dso32_ctrl7_g_t reg; @@ -2755,7 +2681,7 @@ int32_t lsm6dso32_gy_hp_path_internal_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_sdo_pu_en_t val) { lsm6dso32_pin_ctrl_t reg; @@ -2780,7 +2706,7 @@ int32_t lsm6dso32_sdo_sa0_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_sdo_pu_en_t *val) { lsm6dso32_pin_ctrl_t reg; @@ -2814,7 +2740,7 @@ int32_t lsm6dso32_sdo_sa0_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso32_sim_t val) +int32_t lsm6dso32_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_sim_t val) { lsm6dso32_ctrl3_c_t reg; int32_t ret; @@ -2838,7 +2764,7 @@ int32_t lsm6dso32_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso32_sim_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_spi_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_sim_t *val) { lsm6dso32_ctrl3_c_t reg; @@ -2873,7 +2799,7 @@ int32_t lsm6dso32_spi_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_i2c_interface_set(const stmdev_ctx_t *ctx, lsm6dso32_i2c_disable_t val) { lsm6dso32_ctrl4_c_t reg; @@ -2899,7 +2825,7 @@ int32_t lsm6dso32_i2c_interface_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_i2c_interface_get(const stmdev_ctx_t *ctx, lsm6dso32_i2c_disable_t *val) { lsm6dso32_ctrl4_c_t reg; @@ -2933,7 +2859,7 @@ int32_t lsm6dso32_i2c_interface_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_i3c_disable_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_i3c_disable_set(const stmdev_ctx_t *ctx, lsm6dso32_i3c_disable_t val) { lsm6dso32_i3c_bus_avb_t i3c_bus_avb; @@ -2974,7 +2900,7 @@ int32_t lsm6dso32_i3c_disable_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_i3c_disable_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_i3c_disable_get(const stmdev_ctx_t *ctx, lsm6dso32_i3c_disable_t *val) { lsm6dso32_ctrl9_xl_t ctrl9_xl; @@ -3040,7 +2966,7 @@ int32_t lsm6dso32_i3c_disable_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_int1_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_int1_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_int1_pd_en_t val) { lsm6dso32_i3c_bus_avb_t reg; @@ -3065,7 +2991,7 @@ int32_t lsm6dso32_int1_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_int1_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_int1_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_int1_pd_en_t *val) { lsm6dso32_i3c_bus_avb_t reg; @@ -3101,7 +3027,7 @@ int32_t lsm6dso32_int1_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm6dso32_pin_int1_route_t *val) { lsm6dso32_pin_int2_route_t pin_int2_route; @@ -3239,7 +3165,7 @@ int32_t lsm6dso32_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm6dso32_pin_int1_route_t *val) { int32_t ret; @@ -3293,7 +3219,7 @@ int32_t lsm6dso32_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm6dso32_pin_int2_route_t *val) { lsm6dso32_pin_int1_route_t pin_int1_route; @@ -3431,7 +3357,7 @@ int32_t lsm6dso32_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pin_int2_route_get(const stmdev_ctx_t *ctx, lsm6dso32_pin_int2_route_t *val) { int32_t ret; @@ -3484,7 +3410,7 @@ int32_t lsm6dso32_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_pp_od_t val) { lsm6dso32_ctrl3_c_t reg; @@ -3509,7 +3435,7 @@ int32_t lsm6dso32_pin_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_pp_od_t *val) { lsm6dso32_ctrl3_c_t reg; @@ -3543,7 +3469,7 @@ int32_t lsm6dso32_pin_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pin_polarity_set(const stmdev_ctx_t *ctx, lsm6dso32_h_lactive_t val) { lsm6dso32_ctrl3_c_t reg; @@ -3568,7 +3494,7 @@ int32_t lsm6dso32_pin_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pin_polarity_get(const stmdev_ctx_t *ctx, lsm6dso32_h_lactive_t *val) { lsm6dso32_ctrl3_c_t reg; @@ -3602,7 +3528,7 @@ int32_t lsm6dso32_pin_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_ctrl4_c_t reg; int32_t ret; @@ -3626,7 +3552,7 @@ int32_t lsm6dso32_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_ctrl4_c_t reg; int32_t ret; @@ -3645,7 +3571,7 @@ int32_t lsm6dso32_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_int_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_int_notification_set(const stmdev_ctx_t *ctx, lsm6dso32_lir_t val) { lsm6dso32_tap_cfg0_t tap_cfg0; @@ -3696,7 +3622,7 @@ int32_t lsm6dso32_int_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_int_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_int_notification_get(const stmdev_ctx_t *ctx, lsm6dso32_lir_t *val) { lsm6dso32_tap_cfg0_t tap_cfg0; @@ -3786,7 +3712,7 @@ int32_t lsm6dso32_int_notification_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_wkup_ths_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_wkup_ths_weight_set(const stmdev_ctx_t *ctx, lsm6dso32_wake_ths_w_t val) { lsm6dso32_wake_up_dur_t reg; @@ -3814,7 +3740,7 @@ int32_t lsm6dso32_wkup_ths_weight_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_wkup_ths_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_wkup_ths_weight_get(const stmdev_ctx_t *ctx, lsm6dso32_wake_ths_w_t *val) { lsm6dso32_wake_up_dur_t reg; @@ -3849,7 +3775,7 @@ int32_t lsm6dso32_wkup_ths_weight_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_wake_up_ths_t reg; int32_t ret; @@ -3874,7 +3800,7 @@ int32_t lsm6dso32_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_wake_up_ths_t reg; int32_t ret; @@ -3894,7 +3820,7 @@ int32_t lsm6dso32_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_wake_up_ths_t reg; @@ -3920,7 +3846,7 @@ int32_t lsm6dso32_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_wake_up_ths_t reg; @@ -3941,7 +3867,7 @@ int32_t lsm6dso32_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_wake_up_dur_t reg; int32_t ret; @@ -3966,7 +3892,7 @@ int32_t lsm6dso32_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_wake_up_dur_t reg; int32_t ret; @@ -3998,7 +3924,7 @@ int32_t lsm6dso32_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_ctrl4_c_t reg; int32_t ret; @@ -4022,7 +3948,7 @@ int32_t lsm6dso32_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_ctrl4_c_t reg; int32_t ret; @@ -4044,7 +3970,7 @@ int32_t lsm6dso32_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_act_pin_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_act_pin_notification_set(const stmdev_ctx_t *ctx, lsm6dso32_sleep_status_on_int_t val) { lsm6dso32_tap_cfg0_t reg; @@ -4072,7 +3998,7 @@ int32_t lsm6dso32_act_pin_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_act_pin_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_act_pin_notification_get(const stmdev_ctx_t *ctx, lsm6dso32_sleep_status_on_int_t *val) { lsm6dso32_tap_cfg0_t reg; @@ -4106,7 +4032,7 @@ int32_t lsm6dso32_act_pin_notification_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_act_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_act_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_inact_en_t val) { lsm6dso32_tap_cfg2_t reg; @@ -4131,7 +4057,7 @@ int32_t lsm6dso32_act_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_act_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_act_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_inact_en_t *val) { lsm6dso32_tap_cfg2_t reg; @@ -4174,7 +4100,7 @@ int32_t lsm6dso32_act_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_wake_up_dur_t reg; int32_t ret; @@ -4199,7 +4125,7 @@ int32_t lsm6dso32_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_wake_up_dur_t reg; int32_t ret; @@ -4231,7 +4157,7 @@ int32_t lsm6dso32_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_tap_cfg0_t reg; @@ -4256,7 +4182,7 @@ int32_t lsm6dso32_tap_detection_on_z_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_tap_cfg0_t reg; @@ -4276,7 +4202,7 @@ int32_t lsm6dso32_tap_detection_on_z_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_tap_cfg0_t reg; @@ -4301,7 +4227,7 @@ int32_t lsm6dso32_tap_detection_on_y_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_tap_cfg0_t reg; @@ -4321,7 +4247,7 @@ int32_t lsm6dso32_tap_detection_on_y_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_tap_cfg0_t reg; @@ -4346,7 +4272,7 @@ int32_t lsm6dso32_tap_detection_on_x_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_tap_cfg0_t reg; @@ -4366,7 +4292,7 @@ int32_t lsm6dso32_tap_detection_on_x_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_tap_cfg1_t reg; int32_t ret; @@ -4390,7 +4316,7 @@ int32_t lsm6dso32_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_tap_cfg1_t reg; int32_t ret; @@ -4409,7 +4335,7 @@ int32_t lsm6dso32_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_tap_axis_priority_set(const stmdev_ctx_t *ctx, lsm6dso32_tap_priority_t val) { lsm6dso32_tap_cfg1_t reg; @@ -4434,7 +4360,7 @@ int32_t lsm6dso32_tap_axis_priority_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_tap_axis_priority_get(const stmdev_ctx_t *ctx, lsm6dso32_tap_priority_t *val) { lsm6dso32_tap_cfg1_t reg; @@ -4484,7 +4410,7 @@ int32_t lsm6dso32_tap_axis_priority_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_tap_cfg2_t reg; int32_t ret; @@ -4508,7 +4434,7 @@ int32_t lsm6dso32_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_tap_cfg2_t reg; int32_t ret; @@ -4527,7 +4453,7 @@ int32_t lsm6dso32_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_tap_ths_6d_t reg; int32_t ret; @@ -4551,7 +4477,7 @@ int32_t lsm6dso32_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_tap_ths_6d_t reg; int32_t ret; @@ -4575,7 +4501,7 @@ int32_t lsm6dso32_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_int_dur2_t reg; int32_t ret; @@ -4604,7 +4530,7 @@ int32_t lsm6dso32_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_int_dur2_t reg; int32_t ret; @@ -4629,7 +4555,7 @@ int32_t lsm6dso32_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_int_dur2_t reg; int32_t ret; @@ -4659,7 +4585,7 @@ int32_t lsm6dso32_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_int_dur2_t reg; int32_t ret; @@ -4685,7 +4611,7 @@ int32_t lsm6dso32_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_int_dur2_t reg; int32_t ret; @@ -4716,7 +4642,7 @@ int32_t lsm6dso32_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_int_dur2_t reg; int32_t ret; @@ -4735,7 +4661,7 @@ int32_t lsm6dso32_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_tap_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_single_double_tap_t val) { lsm6dso32_wake_up_ths_t reg; @@ -4760,7 +4686,7 @@ int32_t lsm6dso32_tap_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_tap_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_single_double_tap_t *val) { lsm6dso32_wake_up_ths_t reg; @@ -4807,7 +4733,7 @@ int32_t lsm6dso32_tap_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_6d_threshold_set(const stmdev_ctx_t *ctx, lsm6dso32_sixd_ths_t val) { lsm6dso32_tap_ths_6d_t reg; @@ -4832,7 +4758,7 @@ int32_t lsm6dso32_6d_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_6d_threshold_get(const stmdev_ctx_t *ctx, lsm6dso32_sixd_ths_t *val) { lsm6dso32_tap_ths_6d_t reg; @@ -4866,7 +4792,7 @@ int32_t lsm6dso32_6d_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_tap_ths_6d_t reg; int32_t ret; @@ -4890,7 +4816,7 @@ int32_t lsm6dso32_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_tap_ths_6d_t reg; int32_t ret; @@ -4922,7 +4848,7 @@ int32_t lsm6dso32_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_ff_threshold_set(const stmdev_ctx_t *ctx, lsm6dso32_ff_ths_t val) { lsm6dso32_free_fall_t reg; @@ -4947,7 +4873,7 @@ int32_t lsm6dso32_ff_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_ff_threshold_get(const stmdev_ctx_t *ctx, lsm6dso32_ff_ths_t *val) { lsm6dso32_free_fall_t reg; @@ -4986,7 +4912,7 @@ int32_t lsm6dso32_ff_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_wake_up_dur_t wake_up_dur; lsm6dso32_free_fall_t free_fall; @@ -5027,7 +4953,7 @@ int32_t lsm6dso32_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_wake_up_dur_t wake_up_dur; lsm6dso32_free_fall_t free_fall; @@ -5066,7 +4992,7 @@ int32_t lsm6dso32_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dso32_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val) { lsm6dso32_fifo_ctrl1_t fifo_ctrl1; lsm6dso32_fifo_ctrl2_t fifo_ctrl2; @@ -5100,7 +5026,7 @@ int32_t lsm6dso32_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dso32_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dso32_fifo_ctrl1_t fifo_ctrl1; lsm6dso32_fifo_ctrl2_t fifo_ctrl2; @@ -5128,7 +5054,7 @@ int32_t lsm6dso32_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_compression_algo_init_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_compression_algo_init_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_emb_func_init_b_t reg; @@ -5166,7 +5092,7 @@ int32_t lsm6dso32_compression_algo_init_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_compression_algo_init_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_compression_algo_init_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_emb_func_init_b_t reg; @@ -5198,7 +5124,7 @@ int32_t lsm6dso32_compression_algo_init_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_compression_algo_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_compression_algo_set(const stmdev_ctx_t *ctx, lsm6dso32_uncoptr_rate_t val) { lsm6dso32_emb_func_en_b_t emb_func_en_b; @@ -5251,7 +5177,7 @@ int32_t lsm6dso32_compression_algo_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_compression_algo_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_compression_algo_get(const stmdev_ctx_t *ctx, lsm6dso32_uncoptr_rate_t *val) { lsm6dso32_fifo_ctrl2_t reg; @@ -5297,7 +5223,7 @@ int32_t lsm6dso32_compression_algo_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_fifo_ctrl2_t reg; @@ -5322,7 +5248,7 @@ int32_t lsm6dso32_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_fifo_ctrl2_t reg; @@ -5343,7 +5269,7 @@ int32_t lsm6dso32_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_compression_algo_real_time_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_compression_algo_real_time_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_fifo_ctrl2_t reg; @@ -5368,7 +5294,7 @@ int32_t lsm6dso32_compression_algo_real_time_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_compression_algo_real_time_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_compression_algo_real_time_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_fifo_ctrl2_t reg; @@ -5389,7 +5315,7 @@ int32_t lsm6dso32_compression_algo_real_time_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_fifo_ctrl2_t reg; int32_t ret; @@ -5414,7 +5340,7 @@ int32_t lsm6dso32_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_fifo_ctrl2_t reg; @@ -5435,7 +5361,7 @@ int32_t lsm6dso32_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_xl_batch_set(const stmdev_ctx_t *ctx, lsm6dso32_bdr_xl_t val) { lsm6dso32_fifo_ctrl3_t reg; @@ -5461,7 +5387,7 @@ int32_t lsm6dso32_fifo_xl_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_xl_batch_get(const stmdev_ctx_t *ctx, lsm6dso32_bdr_xl_t *val) { lsm6dso32_fifo_ctrl3_t reg; @@ -5536,7 +5462,7 @@ int32_t lsm6dso32_fifo_xl_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_gy_batch_set(const stmdev_ctx_t *ctx, lsm6dso32_bdr_gy_t val) { lsm6dso32_fifo_ctrl3_t reg; @@ -5562,7 +5488,7 @@ int32_t lsm6dso32_fifo_gy_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_gy_batch_get(const stmdev_ctx_t *ctx, lsm6dso32_bdr_gy_t *val) { lsm6dso32_fifo_ctrl3_t reg; @@ -5636,7 +5562,7 @@ int32_t lsm6dso32_fifo_gy_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_fifo_mode_t val) { lsm6dso32_fifo_ctrl4_t reg; @@ -5661,7 +5587,7 @@ int32_t lsm6dso32_fifo_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_fifo_mode_t *val) { lsm6dso32_fifo_ctrl4_t reg; @@ -5712,7 +5638,7 @@ int32_t lsm6dso32_fifo_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_temp_batch_set(const stmdev_ctx_t *ctx, lsm6dso32_odr_t_batch_t val) { lsm6dso32_fifo_ctrl4_t reg; @@ -5738,7 +5664,7 @@ int32_t lsm6dso32_fifo_temp_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_temp_batch_get(const stmdev_ctx_t *ctx, lsm6dso32_odr_t_batch_t *val) { lsm6dso32_fifo_ctrl4_t reg; @@ -5782,7 +5708,7 @@ int32_t lsm6dso32_fifo_temp_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, lsm6dso32_odr_ts_batch_t val) { lsm6dso32_fifo_ctrl4_t reg; @@ -5809,7 +5735,7 @@ int32_t lsm6dso32_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, lsm6dso32_odr_ts_batch_t *val) { lsm6dso32_fifo_ctrl4_t reg; @@ -5853,7 +5779,7 @@ int32_t lsm6dso32_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, lsm6dso32_trig_counter_bdr_t val) { lsm6dso32_counter_bdr_reg1_t reg; @@ -5882,7 +5808,7 @@ int32_t lsm6dso32_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, lsm6dso32_trig_counter_bdr_t *val) { lsm6dso32_counter_bdr_reg1_t reg; @@ -5919,7 +5845,7 @@ int32_t lsm6dso32_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_rst_batch_counter_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_counter_bdr_reg1_t reg; @@ -5948,7 +5874,7 @@ int32_t lsm6dso32_rst_batch_counter_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_rst_batch_counter_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_counter_bdr_reg1_t reg; @@ -5970,7 +5896,7 @@ int32_t lsm6dso32_rst_batch_counter_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_batch_counter_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { lsm6dso32_counter_bdr_reg1_t counter_bdr_reg1; @@ -6006,7 +5932,7 @@ int32_t lsm6dso32_batch_counter_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dso32_counter_bdr_reg1_t counter_bdr_reg1; @@ -6035,7 +5961,7 @@ int32_t lsm6dso32_batch_counter_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fifo_data_level_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dso32_fifo_status1_t fifo_status1; @@ -6064,7 +5990,7 @@ int32_t lsm6dso32_fifo_data_level_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_status_get(const stmdev_ctx_t *ctx, lsm6dso32_fifo_status2_t *val) { int32_t ret; @@ -6082,7 +6008,7 @@ int32_t lsm6dso32_fifo_status_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_fifo_status2_t reg; int32_t ret; @@ -6102,7 +6028,7 @@ int32_t lsm6dso32_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_fifo_status2_t reg; int32_t ret; @@ -6121,7 +6047,7 @@ int32_t lsm6dso32_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_fifo_status2_t reg; int32_t ret; @@ -6140,7 +6066,7 @@ int32_t lsm6dso32_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fifo_sensor_tag_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, lsm6dso32_fifo_tag_t *val) { lsm6dso32_fifo_data_out_tag_t reg; @@ -6245,7 +6171,7 @@ int32_t lsm6dso32_fifo_sensor_tag_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_emb_func_fifo_cfg_t reg; int32_t ret; @@ -6282,7 +6208,7 @@ int32_t lsm6dso32_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_emb_func_fifo_cfg_t reg; int32_t ret; @@ -6313,7 +6239,7 @@ int32_t lsm6dso32_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_slv0_config_t reg; int32_t ret; @@ -6348,7 +6274,7 @@ int32_t lsm6dso32_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_batch_slave_0_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_slv0_config_t reg; @@ -6379,7 +6305,7 @@ int32_t lsm6dso32_sh_batch_slave_0_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_slv1_config_t reg; int32_t ret; @@ -6414,7 +6340,7 @@ int32_t lsm6dso32_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_batch_slave_1_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_slv1_config_t reg; @@ -6445,7 +6371,7 @@ int32_t lsm6dso32_sh_batch_slave_1_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_slv2_config_t reg; int32_t ret; @@ -6480,7 +6406,7 @@ int32_t lsm6dso32_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_batch_slave_2_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_slv2_config_t reg; @@ -6511,7 +6437,7 @@ int32_t lsm6dso32_sh_batch_slave_2_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_slv3_config_t reg; int32_t ret; @@ -6546,7 +6472,7 @@ int32_t lsm6dso32_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_batch_slave_3_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_slv3_config_t reg; @@ -6589,7 +6515,7 @@ int32_t lsm6dso32_sh_batch_slave_3_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_den_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_den_mode_t val) { lsm6dso32_ctrl6_c_t reg; @@ -6614,7 +6540,7 @@ int32_t lsm6dso32_den_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_den_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_den_mode_t *val) { lsm6dso32_ctrl6_c_t reg; @@ -6660,7 +6586,7 @@ int32_t lsm6dso32_den_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dso32_den_lh_t val) { lsm6dso32_ctrl9_xl_t reg; @@ -6685,7 +6611,7 @@ int32_t lsm6dso32_den_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dso32_den_lh_t *val) { lsm6dso32_ctrl9_xl_t reg; @@ -6719,7 +6645,7 @@ int32_t lsm6dso32_den_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_den_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_den_enable_set(const stmdev_ctx_t *ctx, lsm6dso32_den_xl_g_t val) { lsm6dso32_ctrl9_xl_t reg; @@ -6744,7 +6670,7 @@ int32_t lsm6dso32_den_enable_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_den_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_den_enable_get(const stmdev_ctx_t *ctx, lsm6dso32_den_xl_g_t *val) { lsm6dso32_ctrl9_xl_t reg; @@ -6782,7 +6708,7 @@ int32_t lsm6dso32_den_enable_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_ctrl9_xl_t reg; int32_t ret; @@ -6806,7 +6732,7 @@ int32_t lsm6dso32_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_ctrl9_xl_t reg; int32_t ret; @@ -6825,7 +6751,7 @@ int32_t lsm6dso32_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_ctrl9_xl_t reg; int32_t ret; @@ -6849,7 +6775,7 @@ int32_t lsm6dso32_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_ctrl9_xl_t reg; int32_t ret; @@ -6868,7 +6794,7 @@ int32_t lsm6dso32_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_ctrl9_xl_t reg; int32_t ret; @@ -6892,7 +6818,7 @@ int32_t lsm6dso32_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_ctrl9_xl_t reg; int32_t ret; @@ -6923,7 +6849,7 @@ int32_t lsm6dso32_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_pedo_sens_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pedo_sens_set(const stmdev_ctx_t *ctx, lsm6dso32_pedo_md_t val) { lsm6dso32_emb_func_en_a_t emb_func_en_a; @@ -6989,7 +6915,7 @@ int32_t lsm6dso32_pedo_sens_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_pedo_sens_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pedo_sens_get(const stmdev_ctx_t *ctx, lsm6dso32_pedo_md_t *val) { lsm6dso32_emb_func_en_a_t emb_func_en_a; @@ -7062,7 +6988,7 @@ int32_t lsm6dso32_pedo_sens_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_pedo_step_detect_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pedo_step_detect_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_emb_func_status_t reg; @@ -7093,7 +7019,7 @@ int32_t lsm6dso32_pedo_step_detect_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_pedo_debounce_steps_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -7112,7 +7038,7 @@ int32_t lsm6dso32_pedo_debounce_steps_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_pedo_debounce_steps_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -7131,7 +7057,7 @@ int32_t lsm6dso32_pedo_debounce_steps_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_pedo_steps_period_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pedo_steps_period_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; @@ -7159,7 +7085,7 @@ int32_t lsm6dso32_pedo_steps_period_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_pedo_steps_period_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pedo_steps_period_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -7188,7 +7114,7 @@ int32_t lsm6dso32_pedo_steps_period_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_pedo_int_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pedo_int_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_carry_count_en_t val) { lsm6dso32_pedo_cmd_reg_t reg; @@ -7216,7 +7142,7 @@ int32_t lsm6dso32_pedo_int_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_pedo_int_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pedo_int_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_carry_count_en_t *val) { lsm6dso32_pedo_cmd_reg_t reg; @@ -7264,7 +7190,7 @@ int32_t lsm6dso32_pedo_int_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_emb_func_en_a_t reg; int32_t ret; @@ -7300,7 +7226,7 @@ int32_t lsm6dso32_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_emb_func_en_a_t reg; int32_t ret; @@ -7330,7 +7256,7 @@ int32_t lsm6dso32_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_motion_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_motion_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_emb_func_status_t reg; @@ -7374,7 +7300,7 @@ int32_t lsm6dso32_motion_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_emb_func_en_a_t reg; int32_t ret; @@ -7410,7 +7336,7 @@ int32_t lsm6dso32_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_emb_func_en_a_t reg; int32_t ret; @@ -7440,7 +7366,7 @@ int32_t lsm6dso32_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_emb_func_status_t reg; @@ -7484,7 +7410,7 @@ int32_t lsm6dso32_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dso32_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -7511,7 +7437,7 @@ int32_t lsm6dso32_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_mag_sensitivity_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -7539,7 +7465,7 @@ int32_t lsm6dso32_mag_sensitivity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dso32_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -7594,7 +7520,7 @@ int32_t lsm6dso32_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dso32_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -7655,7 +7581,7 @@ int32_t lsm6dso32_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_mag_soft_iron_set(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dso32_mag_soft_iron_set(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[12]; int32_t ret; @@ -7772,7 +7698,7 @@ int32_t lsm6dso32_mag_soft_iron_set(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_mag_soft_iron_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dso32_mag_soft_iron_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[12]; int32_t ret; @@ -7886,7 +7812,7 @@ int32_t lsm6dso32_mag_soft_iron_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_mag_z_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_mag_z_orient_set(const stmdev_ctx_t *ctx, lsm6dso32_mag_z_axis_t val) { lsm6dso32_mag_cfg_a_t reg; @@ -7916,7 +7842,7 @@ int32_t lsm6dso32_mag_z_orient_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_mag_z_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_mag_z_orient_get(const stmdev_ctx_t *ctx, lsm6dso32_mag_z_axis_t *val) { lsm6dso32_mag_cfg_a_t reg; @@ -7970,7 +7896,7 @@ int32_t lsm6dso32_mag_z_orient_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_mag_y_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_mag_y_orient_set(const stmdev_ctx_t *ctx, lsm6dso32_mag_y_axis_t val) { lsm6dso32_mag_cfg_a_t reg; @@ -8000,7 +7926,7 @@ int32_t lsm6dso32_mag_y_orient_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_mag_y_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_mag_y_orient_get(const stmdev_ctx_t *ctx, lsm6dso32_mag_y_axis_t *val) { lsm6dso32_mag_cfg_a_t reg; @@ -8054,7 +7980,7 @@ int32_t lsm6dso32_mag_y_orient_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_mag_x_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_mag_x_orient_set(const stmdev_ctx_t *ctx, lsm6dso32_mag_x_axis_t val) { lsm6dso32_mag_cfg_b_t reg; @@ -8084,7 +8010,7 @@ int32_t lsm6dso32_mag_x_orient_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_mag_x_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_mag_x_orient_get(const stmdev_ctx_t *ctx, lsm6dso32_mag_x_axis_t *val) { lsm6dso32_mag_cfg_b_t reg; @@ -8149,7 +8075,7 @@ int32_t lsm6dso32_mag_x_orient_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_emb_func_status_t reg; @@ -8180,7 +8106,7 @@ int32_t lsm6dso32_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; @@ -8216,7 +8142,7 @@ int32_t lsm6dso32_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -8252,7 +8178,7 @@ int32_t lsm6dso32_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fsm_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fsm_enable_set(const stmdev_ctx_t *ctx, lsm6dso32_emb_fsm_enable_t *val) { int32_t ret; @@ -8326,7 +8252,7 @@ int32_t lsm6dso32_fsm_enable_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fsm_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fsm_enable_get(const stmdev_ctx_t *ctx, lsm6dso32_emb_fsm_enable_t *val) { int32_t ret; @@ -8356,7 +8282,7 @@ int32_t lsm6dso32_fsm_enable_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dso32_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -8387,7 +8313,7 @@ int32_t lsm6dso32_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dso32_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -8418,7 +8344,7 @@ int32_t lsm6dso32_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_long_clr_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_long_clr_set(const stmdev_ctx_t *ctx, lsm6dso32_fsm_lc_clr_t val) { lsm6dso32_fsm_long_counter_clear_t reg; @@ -8456,7 +8382,7 @@ int32_t lsm6dso32_long_clr_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_long_clr_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_long_clr_get(const stmdev_ctx_t *ctx, lsm6dso32_fsm_lc_clr_t *val) { lsm6dso32_fsm_long_counter_clear_t reg; @@ -8508,7 +8434,7 @@ int32_t lsm6dso32_long_clr_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fsm_out_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dso32_fsm_out_t *val) { int32_t ret; @@ -8537,7 +8463,7 @@ int32_t lsm6dso32_fsm_out_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fsm_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fsm_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso32_fsm_odr_t val) { lsm6dso32_emb_func_odr_cfg_b_t reg; @@ -8576,7 +8502,7 @@ int32_t lsm6dso32_fsm_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fsm_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fsm_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso32_fsm_odr_t *val) { lsm6dso32_emb_func_odr_cfg_b_t reg; @@ -8629,7 +8555,7 @@ int32_t lsm6dso32_fsm_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_emb_func_init_b_t reg; int32_t ret; @@ -8665,7 +8591,7 @@ int32_t lsm6dso32_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_emb_func_init_b_t reg; int32_t ret; @@ -8698,7 +8624,7 @@ int32_t lsm6dso32_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_long_cnt_int_value_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; @@ -8729,7 +8655,7 @@ int32_t lsm6dso32_long_cnt_int_value_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_long_cnt_int_value_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -8757,7 +8683,7 @@ int32_t lsm6dso32_long_cnt_int_value_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fsm_number_of_programs_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -8775,7 +8701,7 @@ int32_t lsm6dso32_fsm_number_of_programs_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fsm_number_of_programs_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -8794,7 +8720,7 @@ int32_t lsm6dso32_fsm_number_of_programs_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fsm_start_address_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; @@ -8824,7 +8750,7 @@ int32_t lsm6dso32_fsm_start_address_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_fsm_start_address_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -8865,7 +8791,7 @@ int32_t lsm6dso32_fsm_start_address_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_read_data_raw_get(const stmdev_ctx_t *ctx, lsm6dso32_emb_sh_read_t *val) { int32_t ret; @@ -8894,7 +8820,7 @@ int32_t lsm6dso32_sh_read_data_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_slave_connected_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_slave_connected_set(const stmdev_ctx_t *ctx, lsm6dso32_aux_sens_on_t val) { lsm6dso32_master_config_t reg; @@ -8931,7 +8857,7 @@ int32_t lsm6dso32_sh_slave_connected_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_slave_connected_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_slave_connected_get(const stmdev_ctx_t *ctx, lsm6dso32_aux_sens_on_t *val) { lsm6dso32_master_config_t reg; @@ -8984,7 +8910,7 @@ int32_t lsm6dso32_sh_slave_connected_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_master_config_t reg; int32_t ret; @@ -9020,7 +8946,7 @@ int32_t lsm6dso32_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_master_config_t reg; int32_t ret; @@ -9050,7 +8976,7 @@ int32_t lsm6dso32_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_shub_pu_en_t val) { lsm6dso32_master_config_t reg; @@ -9087,7 +9013,7 @@ int32_t lsm6dso32_sh_pin_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_shub_pu_en_t *val) { lsm6dso32_master_config_t reg; @@ -9133,7 +9059,7 @@ int32_t lsm6dso32_sh_pin_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32_master_config_t reg; int32_t ret; @@ -9170,7 +9096,7 @@ int32_t lsm6dso32_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_master_config_t reg; int32_t ret; @@ -9200,7 +9126,7 @@ int32_t lsm6dso32_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_syncro_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_start_config_t val) { lsm6dso32_master_config_t reg; @@ -9237,7 +9163,7 @@ int32_t lsm6dso32_sh_syncro_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_syncro_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_start_config_t *val) { lsm6dso32_master_config_t reg; @@ -9283,7 +9209,7 @@ int32_t lsm6dso32_sh_syncro_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_write_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_write_once_t val) { lsm6dso32_master_config_t reg; @@ -9321,7 +9247,7 @@ int32_t lsm6dso32_sh_write_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_write_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_write_once_t *val) { lsm6dso32_master_config_t reg; @@ -9365,7 +9291,7 @@ int32_t lsm6dso32_sh_write_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_reset_set(stmdev_ctx_t *ctx) +int32_t lsm6dso32_sh_reset_set(const stmdev_ctx_t *ctx) { lsm6dso32_master_config_t reg; int32_t ret; @@ -9408,7 +9334,7 @@ int32_t lsm6dso32_sh_reset_set(stmdev_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32_master_config_t reg; int32_t ret; @@ -9438,7 +9364,7 @@ int32_t lsm6dso32_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso32_shub_odr_t val) { lsm6dso32_slv0_config_t reg; @@ -9473,7 +9399,7 @@ int32_t lsm6dso32_sh_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso32_shub_odr_t *val) { lsm6dso32_slv0_config_t reg; @@ -9528,7 +9454,7 @@ int32_t lsm6dso32_sh_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_cfg_write(const stmdev_ctx_t *ctx, lsm6dso32_sh_cfg_write_t *val) { lsm6dso32_slv0_add_t reg; @@ -9574,7 +9500,7 @@ int32_t lsm6dso32_sh_cfg_write(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_slv0_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, lsm6dso32_sh_cfg_read_t *val) { lsm6dso32_slv0_add_t slv0_add; @@ -9629,7 +9555,7 @@ int32_t lsm6dso32_sh_slv0_cfg_read(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_slv1_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, lsm6dso32_sh_cfg_read_t *val) { lsm6dso32_slv1_add_t slv1_add; @@ -9684,7 +9610,7 @@ int32_t lsm6dso32_sh_slv1_cfg_read(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_slv2_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, lsm6dso32_sh_cfg_read_t *val) { lsm6dso32_slv2_add_t slv2_add; @@ -9739,7 +9665,7 @@ int32_t lsm6dso32_sh_slv2_cfg_read(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_slv3_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, lsm6dso32_sh_cfg_read_t *val) { lsm6dso32_slv3_add_t slv3_add; @@ -9791,7 +9717,7 @@ int32_t lsm6dso32_sh_slv3_cfg_read(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso32_sh_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_status_get(const stmdev_ctx_t *ctx, lsm6dso32_status_master_t *val) { int32_t ret; diff --git a/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.h b/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.h index f878a9da..80e314de 100644 --- a/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.h +++ b/sensor/stmemsc/lsm6dso32_STdC/driver/lsm6dso32_reg.h @@ -2638,10 +2638,10 @@ typedef union * them with a custom implementation. */ -int32_t lsm6dso32_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm6dso32_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lsm6dso32_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm6dso32_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -2667,9 +2667,9 @@ typedef enum LSM6DSO32_16g = 0x03, LSM6DSO32_32g = 0x01, } lsm6dso32_fs_xl_t; -int32_t lsm6dso32_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dso32_fs_xl_t val); -int32_t lsm6dso32_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dso32_fs_xl_t *val); typedef enum @@ -2677,7 +2677,7 @@ typedef enum /* Accelerometer power off */ LSM6DSO32_XL_ODR_OFF = 0x00, /* Accelerometer low power mode */ - LSM6DSO32_XL_ODR_6Hz5_LOW_PW = 0x1B, + LSM6DSO32_XL_ODR_1Hz6_LOW_PW = 0x1B, LSM6DSO32_XL_ODR_12Hz5_LOW_PW = 0x11, LSM6DSO32_XL_ODR_26Hz_LOW_PW = 0x12, LSM6DSO32_XL_ODR_52Hz_LOW_PW = 0x13, @@ -2699,16 +2699,16 @@ typedef enum * WARNING: Gyroscope must be in Power-Down mode when * accelerometer is in ultra low power mode. */ - LSM6DSO32_XL_ODR_6Hz5_ULTRA_LOW_PW = 0x2B, + LSM6DSO32_XL_ODR_1Hz6_ULTRA_LOW_PW = 0x2B, LSM6DSO32_XL_ODR_12Hz5_ULTRA_LOW_PW = 0x21, LSM6DSO32_XL_ODR_26Hz_ULTRA_LOW_PW = 0x22, LSM6DSO32_XL_ODR_52Hz_ULTRA_LOW_PW = 0x23, LSM6DSO32_XL_ODR_104Hz_ULTRA_LOW_PW = 0x24, LSM6DSO32_XL_ODR_208Hz_ULTRA_LOW_PW = 0x25, } lsm6dso32_odr_xl_t; -int32_t lsm6dso32_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso32_odr_xl_t val); -int32_t lsm6dso32_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso32_odr_xl_t *val); typedef enum @@ -2719,9 +2719,9 @@ typedef enum LSM6DSO32_1000dps = 4, LSM6DSO32_2000dps = 6, } lsm6dso32_fs_g_t; -int32_t lsm6dso32_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dso32_fs_g_t val); -int32_t lsm6dso32_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dso32_fs_g_t *val); typedef enum @@ -2747,14 +2747,14 @@ typedef enum LSM6DSO32_GY_ODR_26Hz_LOW_PW = 0x12, LSM6DSO32_GY_ODR_52Hz_LOW_PW = 0x13, } lsm6dso32_odr_g_t; -int32_t lsm6dso32_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_gy_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso32_odr_g_t val); -int32_t lsm6dso32_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso32_odr_g_t *val); -int32_t lsm6dso32_block_data_update_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2762,9 +2762,9 @@ typedef enum LSM6DSO32_LSb_1mg = 0, LSM6DSO32_LSb_16mg = 1, } lsm6dso32_usr_off_w_t; -int32_t lsm6dso32_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_offset_weight_set(const stmdev_ctx_t *ctx, lsm6dso32_usr_off_w_t val); -int32_t lsm6dso32_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_offset_weight_get(const stmdev_ctx_t *ctx, lsm6dso32_usr_off_w_t *val); typedef struct @@ -2778,43 +2778,43 @@ typedef struct lsm6dso32_fsm_status_a_t fsm_status_a; lsm6dso32_fsm_status_b_t fsm_status_b; } lsm6dso32_all_sources_t; -int32_t lsm6dso32_all_sources_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_all_sources_get(const stmdev_ctx_t *ctx, lsm6dso32_all_sources_t *val); -int32_t lsm6dso32_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_status_reg_get(const stmdev_ctx_t *ctx, lsm6dso32_status_reg_t *val); -int32_t lsm6dso32_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_xl_usr_offset_x_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso32_xl_usr_offset_x_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso32_xl_usr_offset_y_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso32_xl_usr_offset_y_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso32_xl_usr_offset_z_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso32_xl_usr_offset_z_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso32_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); +int32_t lsm6dso32_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); typedef enum { @@ -2823,29 +2823,29 @@ typedef enum LSM6DSO32_ROUND_GY = 2, LSM6DSO32_ROUND_GY_XL = 3, } lsm6dso32_rounding_t; -int32_t lsm6dso32_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_rounding_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_rounding_t val); -int32_t lsm6dso32_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_rounding_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_rounding_t *val); -int32_t lsm6dso32_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dso32_angular_rate_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dso32_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dso32_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dso32_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso32_number_of_steps_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_number_of_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dso32_steps_reset(stmdev_ctx_t *ctx); +int32_t lsm6dso32_steps_reset(const stmdev_ctx_t *ctx); -int32_t lsm6dso32_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2853,41 +2853,40 @@ typedef enum LSM6DSO32_SENSOR_HUB_BANK = 1, LSM6DSO32_EMBEDDED_FUNC_BANK = 2, } lsm6dso32_reg_access_t; -int32_t lsm6dso32_mem_bank_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dso32_reg_access_t val); -int32_t lsm6dso32_mem_bank_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dso32_reg_access_t *val); -int32_t lsm6dso32_ln_pg_write_byte(stmdev_ctx_t *ctx, - uint16_t address, +int32_t lsm6dso32_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val); -int32_t lsm6dso32_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dso32_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val); -int32_t lsm6dso32_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dso32_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); -int32_t lsm6dso32_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, - uint8_t *val); +int32_t lsm6dso32_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, + uint8_t len); typedef enum { LSM6DSO32_DRDY_LATCHED = 0, LSM6DSO32_DRDY_PULSED = 1, } lsm6dso32_dataready_pulsed_t; -int32_t lsm6dso32_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_dataready_pulsed_t val); -int32_t lsm6dso32_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_dataready_pulsed_t *val); -int32_t lsm6dso32_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dso32_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso32_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2895,9 +2894,9 @@ typedef enum LSM6DSO32_XL_ST_POSITIVE = 1, LSM6DSO32_XL_ST_NEGATIVE = 2, } lsm6dso32_st_xl_t; -int32_t lsm6dso32_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dso32_st_xl_t val); -int32_t lsm6dso32_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dso32_st_xl_t *val); typedef enum @@ -2906,20 +2905,20 @@ typedef enum LSM6DSO32_GY_ST_POSITIVE = 1, LSM6DSO32_GY_ST_NEGATIVE = 3, } lsm6dso32_st_g_t; -int32_t lsm6dso32_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dso32_st_g_t val); -int32_t lsm6dso32_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dso32_st_g_t *val); -int32_t lsm6dso32_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2933,13 +2932,13 @@ typedef enum LSM6DSO32_AGGRESSIVE = 6, /* not available for data rate > 1k670Hz */ LSM6DSO32_XTREME = 7, /* not available for data rate > 1k670Hz */ } lsm6dso32_ftype_t; -int32_t lsm6dso32_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dso32_ftype_t val); -int32_t lsm6dso32_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dso32_ftype_t *val); -int32_t lsm6dso32_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2967,14 +2966,14 @@ typedef enum LSM6DSO32_LP_ODR_DIV_400 = 0x06, LSM6DSO32_LP_ODR_DIV_800 = 0x07, } lsm6dso32_hp_slope_xl_en_t; -int32_t lsm6dso32_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, lsm6dso32_hp_slope_xl_en_t val); -int32_t lsm6dso32_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, lsm6dso32_hp_slope_xl_en_t *val); -int32_t lsm6dso32_xl_fast_settling_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_xl_fast_settling_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2982,9 +2981,9 @@ typedef enum LSM6DSO32_USE_SLOPE = 0, LSM6DSO32_USE_HPF = 1, } lsm6dso32_slope_fds_t; -int32_t lsm6dso32_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dso32_slope_fds_t val); -int32_t lsm6dso32_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dso32_slope_fds_t *val); typedef enum @@ -2995,9 +2994,9 @@ typedef enum LSM6DSO32_HP_FILTER_260mHz = 0x82, LSM6DSO32_HP_FILTER_1Hz04 = 0x83, } lsm6dso32_hpm_g_t; -int32_t lsm6dso32_gy_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dso32_hpm_g_t val); -int32_t lsm6dso32_gy_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dso32_hpm_g_t *val); typedef enum @@ -3005,9 +3004,9 @@ typedef enum LSM6DSO32_PULL_UP_DISC = 0, LSM6DSO32_PULL_UP_CONNECT = 1, } lsm6dso32_sdo_pu_en_t; -int32_t lsm6dso32_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_sdo_pu_en_t val); -int32_t lsm6dso32_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_sdo_pu_en_t *val); typedef enum @@ -3015,9 +3014,9 @@ typedef enum LSM6DSO32_SPI_4_WIRE = 0, LSM6DSO32_SPI_3_WIRE = 1, } lsm6dso32_sim_t; -int32_t lsm6dso32_spi_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_sim_t val); -int32_t lsm6dso32_spi_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_sim_t *val); typedef enum @@ -3025,9 +3024,9 @@ typedef enum LSM6DSO32_I2C_ENABLE = 0, LSM6DSO32_I2C_DISABLE = 1, } lsm6dso32_i2c_disable_t; -int32_t lsm6dso32_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_i2c_interface_set(const stmdev_ctx_t *ctx, lsm6dso32_i2c_disable_t val); -int32_t lsm6dso32_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_i2c_interface_get(const stmdev_ctx_t *ctx, lsm6dso32_i2c_disable_t *val); typedef enum @@ -3038,9 +3037,9 @@ typedef enum LSM6DSO32_I3C_ENABLE_T_1ms = 0x02, LSM6DSO32_I3C_ENABLE_T_25ms = 0x03, } lsm6dso32_i3c_disable_t; -int32_t lsm6dso32_i3c_disable_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_i3c_disable_set(const stmdev_ctx_t *ctx, lsm6dso32_i3c_disable_t val); -int32_t lsm6dso32_i3c_disable_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_i3c_disable_get(const stmdev_ctx_t *ctx, lsm6dso32_i3c_disable_t *val); typedef enum @@ -3048,9 +3047,9 @@ typedef enum LSM6DSO32_PULL_DOWN_DISC = 0, LSM6DSO32_PULL_DOWN_CONNECT = 1, } lsm6dso32_int1_pd_en_t; -int32_t lsm6dso32_int1_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_int1_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_int1_pd_en_t val); -int32_t lsm6dso32_int1_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_int1_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_int1_pd_en_t *val); typedef struct @@ -3061,9 +3060,9 @@ typedef struct lsm6dso32_fsm_int1_a_t fsm_int1_a; lsm6dso32_fsm_int1_b_t fsm_int1_b; } lsm6dso32_pin_int1_route_t; -int32_t lsm6dso32_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm6dso32_pin_int1_route_t *val); -int32_t lsm6dso32_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm6dso32_pin_int1_route_t *val); typedef struct @@ -3074,9 +3073,9 @@ typedef struct lsm6dso32_fsm_int2_a_t fsm_int2_a; lsm6dso32_fsm_int2_b_t fsm_int2_b; } lsm6dso32_pin_int2_route_t; -int32_t lsm6dso32_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm6dso32_pin_int2_route_t *val); -int32_t lsm6dso32_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pin_int2_route_get(const stmdev_ctx_t *ctx, lsm6dso32_pin_int2_route_t *val); typedef enum @@ -3084,9 +3083,9 @@ typedef enum LSM6DSO32_PUSH_PULL = 0, LSM6DSO32_OPEN_DRAIN = 1, } lsm6dso32_pp_od_t; -int32_t lsm6dso32_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_pp_od_t val); -int32_t lsm6dso32_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_pp_od_t *val); typedef enum @@ -3094,13 +3093,13 @@ typedef enum LSM6DSO32_ACTIVE_HIGH = 0, LSM6DSO32_ACTIVE_LOW = 1, } lsm6dso32_h_lactive_t; -int32_t lsm6dso32_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pin_polarity_set(const stmdev_ctx_t *ctx, lsm6dso32_h_lactive_t val); -int32_t lsm6dso32_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pin_polarity_get(const stmdev_ctx_t *ctx, lsm6dso32_h_lactive_t *val); -int32_t lsm6dso32_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3109,9 +3108,9 @@ typedef enum LSM6DSO32_BASE_PULSED_EMB_LATCHED = 2, LSM6DSO32_ALL_INT_LATCHED = 3, } lsm6dso32_lir_t; -int32_t lsm6dso32_int_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_int_notification_set(const stmdev_ctx_t *ctx, lsm6dso32_lir_t val); -int32_t lsm6dso32_int_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_int_notification_get(const stmdev_ctx_t *ctx, lsm6dso32_lir_t *val); typedef enum @@ -3119,33 +3118,33 @@ typedef enum LSM6DSO32_LSb_FS_DIV_64 = 0, LSM6DSO32_LSb_FS_DIV_256 = 1, } lsm6dso32_wake_ths_w_t; -int32_t lsm6dso32_wkup_ths_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_wkup_ths_weight_set(const stmdev_ctx_t *ctx, lsm6dso32_wake_ths_w_t val); -int32_t lsm6dso32_wkup_ths_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_wkup_ths_weight_get(const stmdev_ctx_t *ctx, lsm6dso32_wake_ths_w_t *val); -int32_t lsm6dso32_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSO32_DRIVE_SLEEP_CHG_EVENT = 0, LSM6DSO32_DRIVE_SLEEP_STATUS = 1, } lsm6dso32_sleep_status_on_int_t; -int32_t lsm6dso32_act_pin_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_act_pin_notification_set(const stmdev_ctx_t *ctx, lsm6dso32_sleep_status_on_int_t val); -int32_t lsm6dso32_act_pin_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_act_pin_notification_get(const stmdev_ctx_t *ctx, lsm6dso32_sleep_status_on_int_t *val); typedef enum @@ -3155,31 +3154,31 @@ typedef enum LSM6DSO32_XL_12Hz5_GY_SLEEP = 2, LSM6DSO32_XL_12Hz5_GY_PD = 3, } lsm6dso32_inact_en_t; -int32_t lsm6dso32_act_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_act_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_inact_en_t val); -int32_t lsm6dso32_act_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_act_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_inact_en_t *val); -int32_t lsm6dso32_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_tap_threshold_x_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3191,36 +3190,36 @@ typedef enum LSM6DSO32_YZX = 5, LSM6DSO32_ZXY = 6, } lsm6dso32_tap_priority_t; -int32_t lsm6dso32_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_tap_axis_priority_set(const stmdev_ctx_t *ctx, lsm6dso32_tap_priority_t val); -int32_t lsm6dso32_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_tap_axis_priority_get(const stmdev_ctx_t *ctx, lsm6dso32_tap_priority_t *val); -int32_t lsm6dso32_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_tap_threshold_y_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_tap_threshold_z_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSO32_ONLY_SINGLE = 0, LSM6DSO32_BOTH_SINGLE_DOUBLE = 1, } lsm6dso32_single_double_tap_t; -int32_t lsm6dso32_tap_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_single_double_tap_t val); -int32_t lsm6dso32_tap_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_single_double_tap_t *val); typedef enum @@ -3228,13 +3227,13 @@ typedef enum LSM6DSO32_DEG_68 = 0, LSM6DSO32_DEG_47 = 1, } lsm6dso32_sixd_ths_t; -int32_t lsm6dso32_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_6d_threshold_set(const stmdev_ctx_t *ctx, lsm6dso32_sixd_ths_t val); -int32_t lsm6dso32_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_6d_threshold_get(const stmdev_ctx_t *ctx, lsm6dso32_sixd_ths_t *val); -int32_t lsm6dso32_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3242,21 +3241,21 @@ typedef enum LSM6DSO32_FF_TSH_438mg = 1, LSM6DSO32_FF_TSH_500mg = 2, } lsm6dso32_ff_ths_t; -int32_t lsm6dso32_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_ff_threshold_set(const stmdev_ctx_t *ctx, lsm6dso32_ff_ths_t val); -int32_t lsm6dso32_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_ff_threshold_get(const stmdev_ctx_t *ctx, lsm6dso32_ff_ths_t *val); -int32_t lsm6dso32_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dso32_fifo_watermark_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dso32_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dso32_compression_algo_init_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_compression_algo_init_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_compression_algo_init_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_compression_algo_init_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3267,24 +3266,24 @@ typedef enum LSM6DSO32_CMP_16_TO_1 = 0x06, LSM6DSO32_CMP_32_TO_1 = 0x07, } lsm6dso32_uncoptr_rate_t; -int32_t lsm6dso32_compression_algo_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_compression_algo_set(const stmdev_ctx_t *ctx, lsm6dso32_uncoptr_rate_t val); -int32_t lsm6dso32_compression_algo_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_compression_algo_get(const stmdev_ctx_t *ctx, lsm6dso32_uncoptr_rate_t *val); -int32_t lsm6dso32_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_compression_algo_real_time_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_compression_algo_real_time_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_compression_algo_real_time_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_compression_algo_real_time_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3302,9 +3301,9 @@ typedef enum LSM6DSO32_XL_BATCHED_AT_6667Hz = 10, LSM6DSO32_XL_BATCHED_AT_6Hz5 = 11, } lsm6dso32_bdr_xl_t; -int32_t lsm6dso32_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_xl_batch_set(const stmdev_ctx_t *ctx, lsm6dso32_bdr_xl_t val); -int32_t lsm6dso32_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_xl_batch_get(const stmdev_ctx_t *ctx, lsm6dso32_bdr_xl_t *val); typedef enum @@ -3322,9 +3321,9 @@ typedef enum LSM6DSO32_GY_BATCHED_AT_6667Hz = 10, LSM6DSO32_GY_BATCHED_AT_6Hz5 = 11, } lsm6dso32_bdr_gy_t; -int32_t lsm6dso32_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_gy_batch_set(const stmdev_ctx_t *ctx, lsm6dso32_bdr_gy_t val); -int32_t lsm6dso32_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_gy_batch_get(const stmdev_ctx_t *ctx, lsm6dso32_bdr_gy_t *val); typedef enum @@ -3336,9 +3335,9 @@ typedef enum LSM6DSO32_STREAM_MODE = 6, LSM6DSO32_BYPASS_TO_FIFO_MODE = 7, } lsm6dso32_fifo_mode_t; -int32_t lsm6dso32_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_fifo_mode_t val); -int32_t lsm6dso32_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_fifo_mode_t *val); typedef enum @@ -3348,9 +3347,9 @@ typedef enum LSM6DSO32_TEMP_BATCHED_AT_12Hz5 = 2, LSM6DSO32_TEMP_BATCHED_AT_52Hz = 3, } lsm6dso32_odr_t_batch_t; -int32_t lsm6dso32_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_temp_batch_set(const stmdev_ctx_t *ctx, lsm6dso32_odr_t_batch_t val); -int32_t lsm6dso32_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_temp_batch_get(const stmdev_ctx_t *ctx, lsm6dso32_odr_t_batch_t *val); typedef enum @@ -3360,9 +3359,9 @@ typedef enum LSM6DSO32_DEC_8 = 2, LSM6DSO32_DEC_32 = 3, } lsm6dso32_odr_ts_batch_t; -int32_t lsm6dso32_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, lsm6dso32_odr_ts_batch_t val); -int32_t lsm6dso32_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, lsm6dso32_odr_ts_batch_t *val); typedef enum @@ -3393,58 +3392,58 @@ typedef enum LSM6DSO32_STEP_COUNTER_TAG, LSM6DSO32_SENSORHUB_NACK_TAG = 0x19, } lsm6dso32_fifo_tag_t; -int32_t lsm6dso32_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, lsm6dso32_trig_counter_bdr_t val); -int32_t lsm6dso32_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, lsm6dso32_trig_counter_bdr_t *val); -int32_t lsm6dso32_rst_batch_counter_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_rst_batch_counter_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_batch_counter_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dso32_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dso32_fifo_data_level_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dso32_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_status_get(const stmdev_ctx_t *ctx, lsm6dso32_fifo_status2_t *val); -int32_t lsm6dso32_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_fifo_sensor_tag_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, lsm6dso32_fifo_tag_t *val); -int32_t lsm6dso32_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_fifo_pedo_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_sh_batch_slave_0_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_sh_batch_slave_0_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_sh_batch_slave_1_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_sh_batch_slave_1_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_sh_batch_slave_2_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_sh_batch_slave_2_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_sh_batch_slave_3_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_sh_batch_slave_3_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3455,9 +3454,9 @@ typedef enum LSM6DSO32_LEVEL_TRIGGER = 2, LSM6DSO32_EDGE_TRIGGER = 4, } lsm6dso32_den_mode_t; -int32_t lsm6dso32_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_den_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_den_mode_t val); -int32_t lsm6dso32_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_den_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_den_mode_t *val); typedef enum @@ -3465,9 +3464,9 @@ typedef enum LSM6DSO32_DEN_ACT_LOW = 0, LSM6DSO32_DEN_ACT_HIGH = 1, } lsm6dso32_den_lh_t; -int32_t lsm6dso32_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dso32_den_lh_t val); -int32_t lsm6dso32_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dso32_den_lh_t *val); typedef enum @@ -3476,21 +3475,21 @@ typedef enum LSM6DSO32_STAMP_IN_XL_DATA = 1, LSM6DSO32_STAMP_IN_GY_XL_DATA = 2, } lsm6dso32_den_xl_g_t; -int32_t lsm6dso32_den_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_den_enable_set(const stmdev_ctx_t *ctx, lsm6dso32_den_xl_g_t val); -int32_t lsm6dso32_den_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_den_enable_get(const stmdev_ctx_t *ctx, lsm6dso32_den_xl_g_t *val); -int32_t lsm6dso32_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_den_mark_axis_x_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_den_mark_axis_y_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_den_mark_axis_z_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3501,22 +3500,22 @@ typedef enum LSM6DSO32_FALSE_STEP_REJ = 0x13, LSM6DSO32_FALSE_STEP_REJ_ADV_MODE = 0x33, } lsm6dso32_pedo_md_t; -int32_t lsm6dso32_pedo_sens_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pedo_sens_set(const stmdev_ctx_t *ctx, lsm6dso32_pedo_md_t val); -int32_t lsm6dso32_pedo_sens_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pedo_sens_get(const stmdev_ctx_t *ctx, lsm6dso32_pedo_md_t *val); -int32_t lsm6dso32_pedo_step_detect_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pedo_step_detect_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_pedo_debounce_steps_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso32_pedo_debounce_steps_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso32_pedo_steps_period_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pedo_steps_period_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dso32_pedo_steps_period_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pedo_steps_period_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum @@ -3524,33 +3523,33 @@ typedef enum LSM6DSO32_EVERY_STEP = 0, LSM6DSO32_COUNT_OVERFLOW = 1, } lsm6dso32_carry_count_en_t; -int32_t lsm6dso32_pedo_int_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pedo_int_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_carry_count_en_t val); -int32_t lsm6dso32_pedo_int_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_pedo_int_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_carry_count_en_t *val); -int32_t lsm6dso32_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_motion_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_motion_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_mag_sensitivity_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dso32_mag_sensitivity_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dso32_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dso32_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dso32_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dso32_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dso32_mag_soft_iron_set(stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dso32_mag_soft_iron_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dso32_mag_soft_iron_set(const stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dso32_mag_soft_iron_get(const stmdev_ctx_t *ctx, int16_t *val); typedef enum { @@ -3561,9 +3560,9 @@ typedef enum LSM6DSO32_Z_EQ_MIN_Z = 4, LSM6DSO32_Z_EQ_Z = 5, } lsm6dso32_mag_z_axis_t; -int32_t lsm6dso32_mag_z_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_mag_z_orient_set(const stmdev_ctx_t *ctx, lsm6dso32_mag_z_axis_t val); -int32_t lsm6dso32_mag_z_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_mag_z_orient_get(const stmdev_ctx_t *ctx, lsm6dso32_mag_z_axis_t *val); typedef enum @@ -3575,9 +3574,9 @@ typedef enum LSM6DSO32_Y_EQ_MIN_Z = 4, LSM6DSO32_Y_EQ_Z = 5, } lsm6dso32_mag_y_axis_t; -int32_t lsm6dso32_mag_y_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_mag_y_orient_set(const stmdev_ctx_t *ctx, lsm6dso32_mag_y_axis_t val); -int32_t lsm6dso32_mag_y_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_mag_y_orient_get(const stmdev_ctx_t *ctx, lsm6dso32_mag_y_axis_t *val); typedef enum @@ -3589,29 +3588,29 @@ typedef enum LSM6DSO32_X_EQ_MIN_Z = 4, LSM6DSO32_X_EQ_Z = 5, } lsm6dso32_mag_x_axis_t; -int32_t lsm6dso32_mag_x_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_mag_x_orient_set(const stmdev_ctx_t *ctx, lsm6dso32_mag_x_axis_t val); -int32_t lsm6dso32_mag_x_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_mag_x_orient_get(const stmdev_ctx_t *ctx, lsm6dso32_mag_x_axis_t *val); -int32_t lsm6dso32_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { lsm6dso32_fsm_enable_a_t fsm_enable_a; lsm6dso32_fsm_enable_b_t fsm_enable_b; } lsm6dso32_emb_fsm_enable_t; -int32_t lsm6dso32_fsm_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fsm_enable_set(const stmdev_ctx_t *ctx, lsm6dso32_emb_fsm_enable_t *val); -int32_t lsm6dso32_fsm_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fsm_enable_get(const stmdev_ctx_t *ctx, lsm6dso32_emb_fsm_enable_t *val); -int32_t lsm6dso32_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dso32_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dso32_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dso32_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum { @@ -3619,9 +3618,9 @@ typedef enum LSM6DSO32_LC_CLEAR = 1, LSM6DSO32_LC_CLEAR_DONE = 2, } lsm6dso32_fsm_lc_clr_t; -int32_t lsm6dso32_long_clr_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_long_clr_set(const stmdev_ctx_t *ctx, lsm6dso32_fsm_lc_clr_t val); -int32_t lsm6dso32_long_clr_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_long_clr_get(const stmdev_ctx_t *ctx, lsm6dso32_fsm_lc_clr_t *val); typedef struct @@ -3643,7 +3642,7 @@ typedef struct lsm6dso32_fsm_outs7_t fsm_outs15; lsm6dso32_fsm_outs8_t fsm_outs16; } lsm6dso32_fsm_out_t; -int32_t lsm6dso32_fsm_out_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dso32_fsm_out_t *val); typedef enum @@ -3653,27 +3652,27 @@ typedef enum LSM6DSO32_ODR_FSM_52Hz = 2, LSM6DSO32_ODR_FSM_104Hz = 3, } lsm6dso32_fsm_odr_t; -int32_t lsm6dso32_fsm_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fsm_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso32_fsm_odr_t val); -int32_t lsm6dso32_fsm_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fsm_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso32_fsm_odr_t *val); -int32_t lsm6dso32_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32_long_cnt_int_value_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dso32_long_cnt_int_value_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dso32_fsm_number_of_programs_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso32_fsm_number_of_programs_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso32_fsm_start_address_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dso32_fsm_start_address_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef struct @@ -3697,7 +3696,7 @@ typedef struct lsm6dso32_sensor_hub_17_t sh_byte_17; lsm6dso32_sensor_hub_18_t sh_byte_18; } lsm6dso32_emb_sh_read_t; -int32_t lsm6dso32_sh_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_read_data_raw_get(const stmdev_ctx_t *ctx, lsm6dso32_emb_sh_read_t *val); typedef enum @@ -3707,26 +3706,26 @@ typedef enum LSM6DSO32_SLV_0_1_2 = 2, LSM6DSO32_SLV_0_1_2_3 = 3, } lsm6dso32_aux_sens_on_t; -int32_t lsm6dso32_sh_slave_connected_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_slave_connected_set(const stmdev_ctx_t *ctx, lsm6dso32_aux_sens_on_t val); -int32_t lsm6dso32_sh_slave_connected_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_slave_connected_get(const stmdev_ctx_t *ctx, lsm6dso32_aux_sens_on_t *val); -int32_t lsm6dso32_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSO32_EXT_PULL_UP = 0, LSM6DSO32_INTERNAL_PULL_UP = 1, } lsm6dso32_shub_pu_en_t; -int32_t lsm6dso32_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_shub_pu_en_t val); -int32_t lsm6dso32_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_shub_pu_en_t *val); -int32_t lsm6dso32_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32_sh_pass_through_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3734,9 +3733,9 @@ typedef enum LSM6DSO32_EXT_ON_INT2_PIN = 1, LSM6DSO32_XL_GY_DRDY = 0, } lsm6dso32_start_config_t; -int32_t lsm6dso32_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_syncro_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_start_config_t val); -int32_t lsm6dso32_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_syncro_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_start_config_t *val); typedef enum @@ -3744,13 +3743,13 @@ typedef enum LSM6DSO32_EACH_SH_CYCLE = 0, LSM6DSO32_ONLY_FIRST_CYCLE = 1, } lsm6dso32_write_once_t; -int32_t lsm6dso32_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_write_mode_set(const stmdev_ctx_t *ctx, lsm6dso32_write_once_t val); -int32_t lsm6dso32_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_write_mode_get(const stmdev_ctx_t *ctx, lsm6dso32_write_once_t *val); -int32_t lsm6dso32_sh_reset_set(stmdev_ctx_t *ctx); -int32_t lsm6dso32_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32_sh_reset_set(const stmdev_ctx_t *ctx); +int32_t lsm6dso32_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3759,9 +3758,9 @@ typedef enum LSM6DSO32_SH_ODR_26Hz = 2, LSM6DSO32_SH_ODR_13Hz = 3, } lsm6dso32_shub_odr_t; -int32_t lsm6dso32_sh_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso32_shub_odr_t val); -int32_t lsm6dso32_sh_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso32_shub_odr_t *val); typedef struct @@ -3770,7 +3769,7 @@ typedef struct uint8_t slv0_subadd; uint8_t slv0_data; } lsm6dso32_sh_cfg_write_t; -int32_t lsm6dso32_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_cfg_write(const stmdev_ctx_t *ctx, lsm6dso32_sh_cfg_write_t *val); typedef struct @@ -3779,16 +3778,16 @@ typedef struct uint8_t slv_subadd; uint8_t slv_len; } lsm6dso32_sh_cfg_read_t; -int32_t lsm6dso32_sh_slv0_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, lsm6dso32_sh_cfg_read_t *val); -int32_t lsm6dso32_sh_slv1_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, lsm6dso32_sh_cfg_read_t *val); -int32_t lsm6dso32_sh_slv2_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, lsm6dso32_sh_cfg_read_t *val); -int32_t lsm6dso32_sh_slv3_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, lsm6dso32_sh_cfg_read_t *val); -int32_t lsm6dso32_sh_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32_sh_status_get(const stmdev_ctx_t *ctx, lsm6dso32_status_master_t *val); /** diff --git a/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.c b/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.c index 2f586b4d..95fa7768 100644 --- a/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.c +++ b/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t __weak lsm6dso32x_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm6dso32x_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lsm6dso32x_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t __weak lsm6dso32x_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm6dso32x_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -184,7 +194,7 @@ float_t lsm6dso32x_from_lsb_to_nsec(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_full_scale_set(stmdev_ctx_t *ctx, lsm6dso32x_fs_xl_t val) +int32_t lsm6dso32x_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dso32x_fs_xl_t val) { lsm6dso32x_ctrl1_xl_t reg; int32_t ret; @@ -208,7 +218,7 @@ int32_t lsm6dso32x_xl_full_scale_set(stmdev_ctx_t *ctx, lsm6dso32x_fs_xl_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dso32x_fs_xl_t *val) { lsm6dso32x_ctrl1_xl_t reg; @@ -250,7 +260,7 @@ int32_t lsm6dso32x_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6dso32x_odr_xl_t val) +int32_t lsm6dso32x_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso32x_odr_xl_t val) { lsm6dso32x_odr_xl_t odr_xl = val; lsm6dso32x_emb_fsm_enable_t fsm_enable; @@ -505,7 +515,7 @@ int32_t lsm6dso32x_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6dso32x_odr_xl_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6dso32x_odr_xl_t *val) +int32_t lsm6dso32x_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso32x_odr_xl_t *val) { lsm6dso32x_ctrl1_xl_t reg; int32_t ret; @@ -578,7 +588,7 @@ int32_t lsm6dso32x_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6dso32x_odr_xl_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6dso32x_fs_g_t val) +int32_t lsm6dso32x_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dso32x_fs_g_t val) { lsm6dso32x_ctrl2_g_t reg; int32_t ret; @@ -602,7 +612,7 @@ int32_t lsm6dso32x_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6dso32x_fs_g_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6dso32x_fs_g_t *val) +int32_t lsm6dso32x_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dso32x_fs_g_t *val) { lsm6dso32x_ctrl2_g_t reg; int32_t ret; @@ -647,7 +657,7 @@ int32_t lsm6dso32x_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6dso32x_fs_g_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6dso32x_odr_g_t val) +int32_t lsm6dso32x_gy_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso32x_odr_g_t val) { lsm6dso32x_odr_g_t odr_gy = val; lsm6dso32x_emb_fsm_enable_t fsm_enable; @@ -902,7 +912,7 @@ int32_t lsm6dso32x_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6dso32x_odr_g_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_gy_data_rate_get(stmdev_ctx_t *ctx, lsm6dso32x_odr_g_t *val) +int32_t lsm6dso32x_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso32x_odr_g_t *val) { lsm6dso32x_ctrl2_g_t reg; int32_t ret; @@ -971,7 +981,7 @@ int32_t lsm6dso32x_gy_data_rate_get(stmdev_ctx_t *ctx, lsm6dso32x_odr_g_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_ctrl3_c_t reg; int32_t ret; @@ -995,7 +1005,7 @@ int32_t lsm6dso32x_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_ctrl3_c_t reg; int32_t ret; @@ -1015,7 +1025,7 @@ int32_t lsm6dso32x_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_offset_weight_set(const stmdev_ctx_t *ctx, lsm6dso32x_usr_off_w_t val) { lsm6dso32x_ctrl6_c_t reg; @@ -1041,7 +1051,7 @@ int32_t lsm6dso32x_xl_offset_weight_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_offset_weight_get(const stmdev_ctx_t *ctx, lsm6dso32x_usr_off_w_t *val) { lsm6dso32x_ctrl6_c_t reg; @@ -1076,7 +1086,7 @@ int32_t lsm6dso32x_xl_offset_weight_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_power_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_xl_hm_mode_t val) { lsm6dso32x_ctrl5_c_t ctrl5_c; @@ -1117,7 +1127,7 @@ int32_t lsm6dso32x_xl_power_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_power_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_xl_hm_mode_t *val) { lsm6dso32x_ctrl5_c_t ctrl5_c; @@ -1163,7 +1173,7 @@ int32_t lsm6dso32x_xl_power_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_gy_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_gy_power_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_g_hm_mode_t val) { lsm6dso32x_ctrl7_g_t reg; @@ -1188,7 +1198,7 @@ int32_t lsm6dso32x_gy_power_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_gy_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_gy_power_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_g_hm_mode_t *val) { lsm6dso32x_ctrl7_g_t reg; @@ -1222,7 +1232,7 @@ int32_t lsm6dso32x_gy_power_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_status_reg_get(const stmdev_ctx_t *ctx, lsm6dso32x_status_reg_t *val) { int32_t ret; @@ -1240,7 +1250,7 @@ int32_t lsm6dso32x_status_reg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_status_reg_t reg; int32_t ret; @@ -1259,7 +1269,7 @@ int32_t lsm6dso32x_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_status_reg_t reg; int32_t ret; @@ -1278,7 +1288,7 @@ int32_t lsm6dso32x_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_status_reg_t reg; int32_t ret; @@ -1299,7 +1309,7 @@ int32_t lsm6dso32x_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dso32x_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1318,7 +1328,7 @@ int32_t lsm6dso32x_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dso32x_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1337,7 +1347,7 @@ int32_t lsm6dso32x_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dso32x_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1356,7 +1366,7 @@ int32_t lsm6dso32x_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dso32x_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1375,7 +1385,7 @@ int32_t lsm6dso32x_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dso32x_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1394,7 +1404,7 @@ int32_t lsm6dso32x_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dso32x_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1411,7 +1421,7 @@ int32_t lsm6dso32x_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_ctrl7_g_t reg; int32_t ret; @@ -1435,7 +1445,7 @@ int32_t lsm6dso32x_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_ctrl7_g_t reg; int32_t ret; @@ -1467,7 +1477,7 @@ int32_t lsm6dso32x_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_timestamp_rst(stmdev_ctx_t *ctx) +int32_t lsm6dso32x_timestamp_rst(const stmdev_ctx_t *ctx) { uint8_t rst_val = 0xAA; return lsm6dso32x_write_reg(ctx, LSM6DSO32X_TIMESTAMP2, &rst_val, 1); @@ -1481,7 +1491,7 @@ int32_t lsm6dso32x_timestamp_rst(stmdev_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_ctrl10_c_t reg; int32_t ret; @@ -1505,7 +1515,7 @@ int32_t lsm6dso32x_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_ctrl10_c_t reg; int32_t ret; @@ -1526,7 +1536,7 @@ int32_t lsm6dso32x_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t lsm6dso32x_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; @@ -1561,7 +1571,7 @@ int32_t lsm6dso32x_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_rounding_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_rounding_t val) { lsm6dso32x_ctrl5_c_t reg; @@ -1586,7 +1596,7 @@ int32_t lsm6dso32x_rounding_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_rounding_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_rounding_t *val) { lsm6dso32x_ctrl5_c_t reg; @@ -1630,7 +1640,7 @@ int32_t lsm6dso32x_rounding_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; @@ -1652,7 +1662,7 @@ int32_t lsm6dso32x_temperature_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_angular_rate_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -1678,7 +1688,7 @@ int32_t lsm6dso32x_angular_rate_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -1703,7 +1713,7 @@ int32_t lsm6dso32x_acceleration_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dso32x_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1720,7 +1730,7 @@ int32_t lsm6dso32x_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_number_of_steps_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_number_of_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -1750,7 +1760,7 @@ int32_t lsm6dso32x_number_of_steps_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_steps_reset(stmdev_ctx_t *ctx) +int32_t lsm6dso32x_steps_reset(const stmdev_ctx_t *ctx) { lsm6dso32x_emb_func_src_t reg; int32_t ret; @@ -1786,7 +1796,7 @@ int32_t lsm6dso32x_steps_reset(stmdev_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dso32x_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1828,7 +1838,7 @@ int32_t lsm6dso32x_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_internal_freq_fine_t reg; int32_t ret; @@ -1856,7 +1866,7 @@ int32_t lsm6dso32x_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_internal_freq_fine_t reg; int32_t ret; @@ -1879,7 +1889,7 @@ int32_t lsm6dso32x_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_mem_bank_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dso32x_reg_access_t val) { lsm6dso32x_func_cfg_access_t reg; @@ -1908,7 +1918,7 @@ int32_t lsm6dso32x_mem_bank_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_mem_bank_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dso32x_reg_access_t *val) { lsm6dso32x_func_cfg_access_t reg; @@ -1948,7 +1958,7 @@ int32_t lsm6dso32x_mem_bank_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_ln_pg_write_byte(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val) { @@ -2029,7 +2039,7 @@ int32_t lsm6dso32x_ln_pg_write_byte(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dso32x_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len) { lsm6dso32x_page_rw_t page_rw; @@ -2137,7 +2147,7 @@ int32_t lsm6dso32x_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_ln_pg_read_byte(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val) { @@ -2218,7 +2228,7 @@ int32_t lsm6dso32x_ln_pg_read_byte(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_dataready_pulsed_t val) { lsm6dso32x_counter_bdr_reg1_t reg; @@ -2247,7 +2257,7 @@ int32_t lsm6dso32x_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_dataready_pulsed_t *val) { lsm6dso32x_counter_bdr_reg1_t reg; @@ -2282,7 +2292,7 @@ int32_t lsm6dso32x_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dso32x_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -2300,7 +2310,7 @@ int32_t lsm6dso32x_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_ctrl3_c_t reg; int32_t ret; @@ -2324,7 +2334,7 @@ int32_t lsm6dso32x_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_ctrl3_c_t reg; int32_t ret; @@ -2344,7 +2354,7 @@ int32_t lsm6dso32x_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_ctrl3_c_t reg; int32_t ret; @@ -2369,7 +2379,7 @@ int32_t lsm6dso32x_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_ctrl3_c_t reg; int32_t ret; @@ -2388,7 +2398,7 @@ int32_t lsm6dso32x_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_ctrl3_c_t reg; int32_t ret; @@ -2412,7 +2422,7 @@ int32_t lsm6dso32x_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_ctrl3_c_t reg; int32_t ret; @@ -2431,7 +2441,7 @@ int32_t lsm6dso32x_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dso32x_st_xl_t val) { lsm6dso32x_ctrl5_c_t reg; @@ -2456,7 +2466,7 @@ int32_t lsm6dso32x_xl_self_test_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dso32x_st_xl_t *val) { lsm6dso32x_ctrl5_c_t reg; @@ -2494,7 +2504,7 @@ int32_t lsm6dso32x_xl_self_test_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dso32x_st_g_t val) { lsm6dso32x_ctrl5_c_t reg; @@ -2519,7 +2529,7 @@ int32_t lsm6dso32x_gy_self_test_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dso32x_st_g_t *val) { lsm6dso32x_ctrl5_c_t reg; @@ -2570,7 +2580,7 @@ int32_t lsm6dso32x_gy_self_test_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_ctrl1_xl_t reg; int32_t ret; @@ -2594,7 +2604,7 @@ int32_t lsm6dso32x_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_ctrl1_xl_t reg; int32_t ret; @@ -2615,7 +2625,7 @@ int32_t lsm6dso32x_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_ctrl4_c_t reg; int32_t ret; @@ -2641,7 +2651,7 @@ int32_t lsm6dso32x_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_ctrl4_c_t reg; int32_t ret; @@ -2661,7 +2671,7 @@ int32_t lsm6dso32x_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_ctrl4_c_t reg; @@ -2687,7 +2697,7 @@ int32_t lsm6dso32x_filter_settling_mask_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_ctrl4_c_t reg; @@ -2707,7 +2717,7 @@ int32_t lsm6dso32x_filter_settling_mask_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dso32x_ftype_t val) { lsm6dso32x_ctrl6_c_t reg; @@ -2732,7 +2742,7 @@ int32_t lsm6dso32x_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dso32x_ftype_t *val) { lsm6dso32x_ctrl6_c_t reg; @@ -2790,7 +2800,7 @@ int32_t lsm6dso32x_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_ctrl8_xl_t reg; int32_t ret; @@ -2814,7 +2824,7 @@ int32_t lsm6dso32x_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_ctrl8_xl_t reg; int32_t ret; @@ -2835,7 +2845,7 @@ int32_t lsm6dso32x_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, lsm6dso32x_hp_slope_xl_en_t val) { lsm6dso32x_ctrl8_xl_t reg; @@ -2864,7 +2874,7 @@ int32_t lsm6dso32x_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, lsm6dso32x_hp_slope_xl_en_t *val) { lsm6dso32x_ctrl8_xl_t reg; @@ -2986,7 +2996,7 @@ int32_t lsm6dso32x_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_fast_settling_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_ctrl8_xl_t reg; @@ -3013,7 +3023,7 @@ int32_t lsm6dso32x_xl_fast_settling_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_fast_settling_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_ctrl8_xl_t reg; @@ -3034,7 +3044,7 @@ int32_t lsm6dso32x_xl_fast_settling_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dso32x_slope_fds_t val) { lsm6dso32x_tap_cfg0_t reg; @@ -3060,7 +3070,7 @@ int32_t lsm6dso32x_xl_hp_path_internal_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dso32x_slope_fds_t *val) { lsm6dso32x_tap_cfg0_t reg; @@ -3096,7 +3106,7 @@ int32_t lsm6dso32x_xl_hp_path_internal_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_gy_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dso32x_hpm_g_t val) { lsm6dso32x_ctrl7_g_t reg; @@ -3124,7 +3134,7 @@ int32_t lsm6dso32x_gy_hp_path_internal_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_gy_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dso32x_hpm_g_t *val) { lsm6dso32x_ctrl7_g_t reg; @@ -3184,7 +3194,7 @@ int32_t lsm6dso32x_gy_hp_path_internal_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_sdo_pu_en_t val) { lsm6dso32x_pin_ctrl_t reg; @@ -3209,7 +3219,7 @@ int32_t lsm6dso32x_sdo_sa0_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_sdo_pu_en_t *val) { lsm6dso32x_pin_ctrl_t reg; @@ -3243,7 +3253,7 @@ int32_t lsm6dso32x_sdo_sa0_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_spi_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_sim_t val) { lsm6dso32x_ctrl3_c_t reg; @@ -3268,7 +3278,7 @@ int32_t lsm6dso32x_spi_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_spi_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_sim_t *val) { lsm6dso32x_ctrl3_c_t reg; @@ -3303,7 +3313,7 @@ int32_t lsm6dso32x_spi_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_i2c_interface_set(const stmdev_ctx_t *ctx, lsm6dso32x_i2c_disable_t val) { lsm6dso32x_ctrl4_c_t reg; @@ -3329,7 +3339,7 @@ int32_t lsm6dso32x_i2c_interface_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_i2c_interface_get(const stmdev_ctx_t *ctx, lsm6dso32x_i2c_disable_t *val) { lsm6dso32x_ctrl4_c_t reg; @@ -3364,7 +3374,7 @@ int32_t lsm6dso32x_i2c_interface_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_i3c_disable_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_i3c_disable_set(const stmdev_ctx_t *ctx, lsm6dso32x_i3c_disable_t val) { lsm6dso32x_i3c_bus_avb_t i3c_bus_avb; @@ -3406,7 +3416,7 @@ int32_t lsm6dso32x_i3c_disable_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_i3c_disable_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_i3c_disable_get(const stmdev_ctx_t *ctx, lsm6dso32x_i3c_disable_t *val) { lsm6dso32x_ctrl9_xl_t ctrl9_xl; @@ -3472,7 +3482,7 @@ int32_t lsm6dso32x_i3c_disable_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_pp_od_t val) { lsm6dso32x_i3c_bus_avb_t i3c_bus_avb; @@ -3513,7 +3523,7 @@ int32_t lsm6dso32x_pin_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_pp_od_t *val) { lsm6dso32x_i3c_bus_avb_t i3c_bus_avb; @@ -3563,7 +3573,7 @@ int32_t lsm6dso32x_pin_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pin_polarity_set(const stmdev_ctx_t *ctx, lsm6dso32x_h_lactive_t val) { lsm6dso32x_ctrl3_c_t reg; @@ -3588,7 +3598,7 @@ int32_t lsm6dso32x_pin_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pin_polarity_get(const stmdev_ctx_t *ctx, lsm6dso32x_h_lactive_t *val) { lsm6dso32x_ctrl3_c_t reg; @@ -3622,7 +3632,7 @@ int32_t lsm6dso32x_pin_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_ctrl4_c_t reg; int32_t ret; @@ -3646,7 +3656,7 @@ int32_t lsm6dso32x_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_ctrl4_c_t reg; int32_t ret; @@ -3665,7 +3675,7 @@ int32_t lsm6dso32x_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_int_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_int_notification_set(const stmdev_ctx_t *ctx, lsm6dso32x_lir_t val) { lsm6dso32x_tap_cfg0_t tap_cfg0; @@ -3717,7 +3727,7 @@ int32_t lsm6dso32x_int_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_int_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_int_notification_get(const stmdev_ctx_t *ctx, lsm6dso32x_lir_t *val) { lsm6dso32x_tap_cfg0_t tap_cfg0; @@ -3809,7 +3819,7 @@ int32_t lsm6dso32x_int_notification_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_wkup_ths_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_wkup_ths_weight_set(const stmdev_ctx_t *ctx, lsm6dso32x_wake_ths_w_t val) { lsm6dso32x_wake_up_dur_t reg; @@ -3839,7 +3849,7 @@ int32_t lsm6dso32x_wkup_ths_weight_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_wkup_ths_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_wkup_ths_weight_get(const stmdev_ctx_t *ctx, lsm6dso32x_wake_ths_w_t *val) { lsm6dso32x_wake_up_dur_t reg; @@ -3875,7 +3885,7 @@ int32_t lsm6dso32x_wkup_ths_weight_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_wake_up_ths_t reg; int32_t ret; @@ -3902,7 +3912,7 @@ int32_t lsm6dso32x_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_wake_up_ths_t reg; int32_t ret; @@ -3923,7 +3933,7 @@ int32_t lsm6dso32x_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_wake_up_ths_t reg; @@ -3951,7 +3961,7 @@ int32_t lsm6dso32x_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_wake_up_ths_t reg; @@ -3973,7 +3983,7 @@ int32_t lsm6dso32x_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_wake_up_dur_t reg; int32_t ret; @@ -4000,7 +4010,7 @@ int32_t lsm6dso32x_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_wake_up_dur_t reg; int32_t ret; @@ -4033,7 +4043,7 @@ int32_t lsm6dso32x_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_ctrl4_c_t reg; int32_t ret; @@ -4057,7 +4067,7 @@ int32_t lsm6dso32x_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_ctrl4_c_t reg; int32_t ret; @@ -4079,7 +4089,7 @@ int32_t lsm6dso32x_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_act_pin_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_act_pin_notification_set(const stmdev_ctx_t *ctx, lsm6dso32x_sleep_status_on_int_t val) { lsm6dso32x_tap_cfg0_t reg; @@ -4107,7 +4117,7 @@ int32_t lsm6dso32x_act_pin_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_act_pin_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_act_pin_notification_get(const stmdev_ctx_t *ctx, lsm6dso32x_sleep_status_on_int_t *val) { lsm6dso32x_tap_cfg0_t reg; @@ -4141,7 +4151,7 @@ int32_t lsm6dso32x_act_pin_notification_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_act_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_act_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_inact_en_t val) { lsm6dso32x_tap_cfg2_t reg; @@ -4166,7 +4176,7 @@ int32_t lsm6dso32x_act_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_act_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_act_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_inact_en_t *val) { lsm6dso32x_tap_cfg2_t reg; @@ -4209,7 +4219,7 @@ int32_t lsm6dso32x_act_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_wake_up_dur_t reg; int32_t ret; @@ -4236,7 +4246,7 @@ int32_t lsm6dso32x_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_wake_up_dur_t reg; int32_t ret; @@ -4269,7 +4279,7 @@ int32_t lsm6dso32x_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_tap_cfg0_t reg; @@ -4294,7 +4304,7 @@ int32_t lsm6dso32x_tap_detection_on_z_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_tap_cfg0_t reg; @@ -4314,7 +4324,7 @@ int32_t lsm6dso32x_tap_detection_on_z_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_tap_cfg0_t reg; @@ -4339,7 +4349,7 @@ int32_t lsm6dso32x_tap_detection_on_y_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_tap_cfg0_t reg; @@ -4359,7 +4369,7 @@ int32_t lsm6dso32x_tap_detection_on_y_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_tap_cfg0_t reg; @@ -4384,7 +4394,7 @@ int32_t lsm6dso32x_tap_detection_on_x_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_tap_cfg0_t reg; @@ -4404,7 +4414,7 @@ int32_t lsm6dso32x_tap_detection_on_x_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_tap_cfg1_t reg; int32_t ret; @@ -4428,7 +4438,7 @@ int32_t lsm6dso32x_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_tap_threshold_x_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_tap_cfg1_t reg; @@ -4449,7 +4459,7 @@ int32_t lsm6dso32x_tap_threshold_x_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_axis_priority_set(const stmdev_ctx_t *ctx, lsm6dso32x_tap_priority_t val) { lsm6dso32x_tap_cfg1_t reg; @@ -4475,7 +4485,7 @@ int32_t lsm6dso32x_tap_axis_priority_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_axis_priority_get(const stmdev_ctx_t *ctx, lsm6dso32x_tap_priority_t *val) { lsm6dso32x_tap_cfg1_t reg; @@ -4525,7 +4535,7 @@ int32_t lsm6dso32x_tap_axis_priority_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_tap_cfg2_t reg; int32_t ret; @@ -4549,7 +4559,7 @@ int32_t lsm6dso32x_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_tap_threshold_y_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_tap_cfg2_t reg; @@ -4569,7 +4579,7 @@ int32_t lsm6dso32x_tap_threshold_y_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_tap_ths_6d_t reg; int32_t ret; @@ -4594,7 +4604,7 @@ int32_t lsm6dso32x_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_tap_threshold_z_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_tap_ths_6d_t reg; @@ -4619,7 +4629,7 @@ int32_t lsm6dso32x_tap_threshold_z_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_int_dur2_t reg; int32_t ret; @@ -4648,7 +4658,7 @@ int32_t lsm6dso32x_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_int_dur2_t reg; int32_t ret; @@ -4673,7 +4683,7 @@ int32_t lsm6dso32x_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_int_dur2_t reg; int32_t ret; @@ -4703,7 +4713,7 @@ int32_t lsm6dso32x_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_int_dur2_t reg; int32_t ret; @@ -4729,7 +4739,7 @@ int32_t lsm6dso32x_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_int_dur2_t reg; int32_t ret; @@ -4760,7 +4770,7 @@ int32_t lsm6dso32x_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_int_dur2_t reg; int32_t ret; @@ -4779,7 +4789,7 @@ int32_t lsm6dso32x_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_tap_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_single_double_tap_t val) { lsm6dso32x_wake_up_ths_t reg; @@ -4806,7 +4816,7 @@ int32_t lsm6dso32x_tap_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_tap_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_single_double_tap_t *val) { lsm6dso32x_wake_up_ths_t reg; @@ -4854,7 +4864,7 @@ int32_t lsm6dso32x_tap_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_6d_threshold_set(const stmdev_ctx_t *ctx, lsm6dso32x_sixd_ths_t val) { lsm6dso32x_tap_ths_6d_t reg; @@ -4880,7 +4890,7 @@ int32_t lsm6dso32x_6d_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_6d_threshold_get(const stmdev_ctx_t *ctx, lsm6dso32x_sixd_ths_t *val) { lsm6dso32x_tap_ths_6d_t reg; @@ -4922,7 +4932,7 @@ int32_t lsm6dso32x_6d_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_tap_ths_6d_t reg; int32_t ret; @@ -4947,7 +4957,7 @@ int32_t lsm6dso32x_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_tap_ths_6d_t reg; int32_t ret; @@ -4978,7 +4988,7 @@ int32_t lsm6dso32x_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_ff_threshold_set(const stmdev_ctx_t *ctx, lsm6dso32x_ff_ths_t val) { lsm6dso32x_free_fall_t reg; @@ -5003,7 +5013,7 @@ int32_t lsm6dso32x_ff_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_ff_threshold_get(const stmdev_ctx_t *ctx, lsm6dso32x_ff_ths_t *val) { lsm6dso32x_free_fall_t reg; @@ -5042,7 +5052,7 @@ int32_t lsm6dso32x_ff_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_wake_up_dur_t wake_up_dur; lsm6dso32x_free_fall_t free_fall; @@ -5083,7 +5093,7 @@ int32_t lsm6dso32x_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_wake_up_dur_t wake_up_dur; lsm6dso32x_free_fall_t free_fall; @@ -5122,7 +5132,7 @@ int32_t lsm6dso32x_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dso32x_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val) { lsm6dso32x_fifo_ctrl1_t fifo_ctrl1; lsm6dso32x_fifo_ctrl2_t fifo_ctrl2; @@ -5156,7 +5166,7 @@ int32_t lsm6dso32x_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fifo_watermark_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dso32x_fifo_ctrl1_t fifo_ctrl1; @@ -5185,7 +5195,7 @@ int32_t lsm6dso32x_fifo_watermark_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_compression_algo_init_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_compression_algo_init_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_emb_func_init_b_t reg; @@ -5223,7 +5233,7 @@ int32_t lsm6dso32x_compression_algo_init_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_compression_algo_init_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_compression_algo_init_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_emb_func_init_b_t reg; @@ -5255,7 +5265,7 @@ int32_t lsm6dso32x_compression_algo_init_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_compression_algo_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_compression_algo_set(const stmdev_ctx_t *ctx, lsm6dso32x_uncoptr_rate_t val) { lsm6dso32x_fifo_ctrl2_t fifo_ctrl2; @@ -5284,7 +5294,7 @@ int32_t lsm6dso32x_compression_algo_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_compression_algo_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_compression_algo_get(const stmdev_ctx_t *ctx, lsm6dso32x_uncoptr_rate_t *val) { lsm6dso32x_fifo_ctrl2_t reg; @@ -5330,7 +5340,7 @@ int32_t lsm6dso32x_compression_algo_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_fifo_ctrl2_t reg; @@ -5356,7 +5366,7 @@ int32_t lsm6dso32x_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_fifo_ctrl2_t reg; @@ -5377,7 +5387,7 @@ int32_t lsm6dso32x_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_compression_algo_real_time_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_compression_algo_real_time_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_fifo_ctrl2_t reg; @@ -5403,7 +5413,7 @@ int32_t lsm6dso32x_compression_algo_real_time_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_compression_algo_real_time_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_compression_algo_real_time_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_fifo_ctrl2_t reg; @@ -5424,7 +5434,7 @@ int32_t lsm6dso32x_compression_algo_real_time_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_fifo_ctrl2_t reg; @@ -5451,7 +5461,7 @@ int32_t lsm6dso32x_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_fifo_ctrl2_t reg; @@ -5472,7 +5482,7 @@ int32_t lsm6dso32x_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_xl_batch_set(const stmdev_ctx_t *ctx, lsm6dso32x_bdr_xl_t val) { lsm6dso32x_fifo_ctrl3_t reg; @@ -5499,7 +5509,7 @@ int32_t lsm6dso32x_fifo_xl_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_xl_batch_get(const stmdev_ctx_t *ctx, lsm6dso32x_bdr_xl_t *val) { lsm6dso32x_fifo_ctrl3_t reg; @@ -5574,7 +5584,7 @@ int32_t lsm6dso32x_fifo_xl_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_gy_batch_set(const stmdev_ctx_t *ctx, lsm6dso32x_bdr_gy_t val) { lsm6dso32x_fifo_ctrl3_t reg; @@ -5601,7 +5611,7 @@ int32_t lsm6dso32x_fifo_gy_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_gy_batch_get(const stmdev_ctx_t *ctx, lsm6dso32x_bdr_gy_t *val) { lsm6dso32x_fifo_ctrl3_t reg; @@ -5675,7 +5685,7 @@ int32_t lsm6dso32x_fifo_gy_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_fifo_mode_t val) { lsm6dso32x_fifo_ctrl4_t reg; @@ -5701,7 +5711,7 @@ int32_t lsm6dso32x_fifo_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_fifo_mode_t *val) { lsm6dso32x_fifo_ctrl4_t reg; @@ -5752,7 +5762,7 @@ int32_t lsm6dso32x_fifo_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_temp_batch_set(const stmdev_ctx_t *ctx, lsm6dso32x_odr_t_batch_t val) { lsm6dso32x_fifo_ctrl4_t reg; @@ -5779,7 +5789,7 @@ int32_t lsm6dso32x_fifo_temp_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_temp_batch_get(const stmdev_ctx_t *ctx, lsm6dso32x_odr_t_batch_t *val) { lsm6dso32x_fifo_ctrl4_t reg; @@ -5823,7 +5833,7 @@ int32_t lsm6dso32x_fifo_temp_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, lsm6dso32x_odr_ts_batch_t val) { lsm6dso32x_fifo_ctrl4_t reg; @@ -5851,7 +5861,7 @@ int32_t lsm6dso32x_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, lsm6dso32x_odr_ts_batch_t *val) { lsm6dso32x_fifo_ctrl4_t reg; @@ -5895,7 +5905,7 @@ int32_t lsm6dso32x_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, lsm6dso32x_trig_counter_bdr_t val) { lsm6dso32x_counter_bdr_reg1_t reg; @@ -5924,7 +5934,7 @@ int32_t lsm6dso32x_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, lsm6dso32x_trig_counter_bdr_t *val) { lsm6dso32x_counter_bdr_reg1_t reg; @@ -5961,7 +5971,7 @@ int32_t lsm6dso32x_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_rst_batch_counter_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_counter_bdr_reg1_t reg; @@ -5990,7 +6000,7 @@ int32_t lsm6dso32x_rst_batch_counter_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_rst_batch_counter_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_counter_bdr_reg1_t reg; @@ -6012,7 +6022,7 @@ int32_t lsm6dso32x_rst_batch_counter_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_batch_counter_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { lsm6dso32x_counter_bdr_reg1_t counter_bdr_reg1; @@ -6048,7 +6058,7 @@ int32_t lsm6dso32x_batch_counter_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dso32x_counter_bdr_reg1_t counter_bdr_reg1; @@ -6077,7 +6087,7 @@ int32_t lsm6dso32x_batch_counter_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fifo_data_level_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dso32x_fifo_status1_t fifo_status1; @@ -6106,7 +6116,7 @@ int32_t lsm6dso32x_fifo_data_level_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_status_get(const stmdev_ctx_t *ctx, lsm6dso32x_fifo_status2_t *val) { int32_t ret; @@ -6125,7 +6135,7 @@ int32_t lsm6dso32x_fifo_status_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_fifo_status2_t reg; int32_t ret; @@ -6146,7 +6156,7 @@ int32_t lsm6dso32x_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_fifo_status2_t reg; int32_t ret; @@ -6166,7 +6176,7 @@ int32_t lsm6dso32x_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_fifo_status2_t reg; int32_t ret; @@ -6186,7 +6196,7 @@ int32_t lsm6dso32x_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fifo_sensor_tag_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, lsm6dso32x_fifo_tag_t *val) { lsm6dso32x_fifo_data_out_tag_t reg; @@ -6303,7 +6313,7 @@ int32_t lsm6dso32x_fifo_sensor_tag_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_emb_func_fifo_cfg_t reg; int32_t ret; @@ -6340,7 +6350,7 @@ int32_t lsm6dso32x_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fifo_pedo_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_emb_func_fifo_cfg_t reg; @@ -6372,7 +6382,7 @@ int32_t lsm6dso32x_fifo_pedo_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_batch_slave_0_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_slv0_config_t reg; @@ -6410,7 +6420,7 @@ int32_t lsm6dso32x_sh_batch_slave_0_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_batch_slave_0_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_slv0_config_t reg; @@ -6442,7 +6452,7 @@ int32_t lsm6dso32x_sh_batch_slave_0_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_batch_slave_1_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_slv1_config_t reg; @@ -6480,7 +6490,7 @@ int32_t lsm6dso32x_sh_batch_slave_1_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_batch_slave_1_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_slv1_config_t reg; @@ -6512,7 +6522,7 @@ int32_t lsm6dso32x_sh_batch_slave_1_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_batch_slave_2_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_slv2_config_t reg; @@ -6550,7 +6560,7 @@ int32_t lsm6dso32x_sh_batch_slave_2_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_batch_slave_2_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_slv2_config_t reg; @@ -6582,7 +6592,7 @@ int32_t lsm6dso32x_sh_batch_slave_2_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_batch_slave_3_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_slv3_config_t reg; @@ -6620,7 +6630,7 @@ int32_t lsm6dso32x_sh_batch_slave_3_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_batch_slave_3_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_slv3_config_t reg; @@ -6664,7 +6674,7 @@ int32_t lsm6dso32x_sh_batch_slave_3_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_den_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_den_mode_t val) { lsm6dso32x_ctrl6_c_t reg; @@ -6689,7 +6699,7 @@ int32_t lsm6dso32x_den_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_den_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_den_mode_t *val) { lsm6dso32x_ctrl6_c_t reg; @@ -6735,7 +6745,7 @@ int32_t lsm6dso32x_den_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dso32x_den_lh_t val) { lsm6dso32x_ctrl9_xl_t reg; @@ -6760,7 +6770,7 @@ int32_t lsm6dso32x_den_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dso32x_den_lh_t *val) { lsm6dso32x_ctrl9_xl_t reg; @@ -6794,7 +6804,7 @@ int32_t lsm6dso32x_den_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_den_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_den_enable_set(const stmdev_ctx_t *ctx, lsm6dso32x_den_xl_g_t val) { lsm6dso32x_ctrl9_xl_t reg; @@ -6819,7 +6829,7 @@ int32_t lsm6dso32x_den_enable_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_den_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_den_enable_get(const stmdev_ctx_t *ctx, lsm6dso32x_den_xl_g_t *val) { lsm6dso32x_ctrl9_xl_t reg; @@ -6857,7 +6867,7 @@ int32_t lsm6dso32x_den_enable_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_ctrl9_xl_t reg; int32_t ret; @@ -6881,7 +6891,7 @@ int32_t lsm6dso32x_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_den_mark_axis_x_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_ctrl9_xl_t reg; @@ -6901,7 +6911,7 @@ int32_t lsm6dso32x_den_mark_axis_x_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_ctrl9_xl_t reg; int32_t ret; @@ -6925,7 +6935,7 @@ int32_t lsm6dso32x_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_den_mark_axis_y_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_ctrl9_xl_t reg; @@ -6945,7 +6955,7 @@ int32_t lsm6dso32x_den_mark_axis_y_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_ctrl9_xl_t reg; int32_t ret; @@ -6969,7 +6979,7 @@ int32_t lsm6dso32x_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_den_mark_axis_z_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_ctrl9_xl_t reg; @@ -7001,7 +7011,7 @@ int32_t lsm6dso32x_den_mark_axis_z_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_pedo_sens_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pedo_sens_set(const stmdev_ctx_t *ctx, lsm6dso32x_pedo_md_t val) { lsm6dso32x_pedo_cmd_reg_t pedo_cmd_reg; @@ -7029,7 +7039,7 @@ int32_t lsm6dso32x_pedo_sens_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_pedo_sens_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pedo_sens_get(const stmdev_ctx_t *ctx, lsm6dso32x_pedo_md_t *val) { lsm6dso32x_pedo_cmd_reg_t pedo_cmd_reg; @@ -7069,7 +7079,7 @@ int32_t lsm6dso32x_pedo_sens_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_pedo_step_detect_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pedo_step_detect_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_emb_func_status_t reg; @@ -7100,7 +7110,7 @@ int32_t lsm6dso32x_pedo_step_detect_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_pedo_debounce_steps_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -7119,7 +7129,7 @@ int32_t lsm6dso32x_pedo_debounce_steps_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_pedo_debounce_steps_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -7138,7 +7148,7 @@ int32_t lsm6dso32x_pedo_debounce_steps_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_pedo_steps_period_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pedo_steps_period_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; @@ -7166,7 +7176,7 @@ int32_t lsm6dso32x_pedo_steps_period_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_pedo_steps_period_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pedo_steps_period_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -7195,7 +7205,7 @@ int32_t lsm6dso32x_pedo_steps_period_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_pedo_int_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pedo_int_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_carry_count_en_t val) { lsm6dso32x_pedo_cmd_reg_t reg; @@ -7223,7 +7233,7 @@ int32_t lsm6dso32x_pedo_int_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_pedo_int_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pedo_int_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_carry_count_en_t *val) { lsm6dso32x_pedo_cmd_reg_t reg; @@ -7271,7 +7281,7 @@ int32_t lsm6dso32x_pedo_int_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_motion_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_motion_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_emb_func_status_t reg; @@ -7315,7 +7325,7 @@ int32_t lsm6dso32x_motion_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_emb_func_status_t reg; @@ -7360,7 +7370,7 @@ int32_t lsm6dso32x_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_mag_sensitivity_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; @@ -7389,7 +7399,7 @@ int32_t lsm6dso32x_sh_mag_sensitivity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_mag_sensitivity_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -7418,7 +7428,7 @@ int32_t lsm6dso32x_sh_mag_sensitivity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mlc_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; @@ -7449,7 +7459,7 @@ int32_t lsm6dso32x_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -7480,7 +7490,7 @@ int32_t lsm6dso32x_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dso32x_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -7542,7 +7552,7 @@ int32_t lsm6dso32x_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dso32x_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -7611,7 +7621,7 @@ int32_t lsm6dso32x_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_mag_soft_iron_set(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dso32x_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[12]; uint8_t index; @@ -7728,7 +7738,7 @@ int32_t lsm6dso32x_mag_soft_iron_set(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dso32x_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[12]; uint8_t index; @@ -7842,7 +7852,7 @@ int32_t lsm6dso32x_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_mag_z_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mag_z_orient_set(const stmdev_ctx_t *ctx, lsm6dso32x_mag_z_axis_t val) { lsm6dso32x_mag_cfg_a_t reg; @@ -7872,7 +7882,7 @@ int32_t lsm6dso32x_mag_z_orient_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_mag_z_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mag_z_orient_get(const stmdev_ctx_t *ctx, lsm6dso32x_mag_z_axis_t *val) { lsm6dso32x_mag_cfg_a_t reg; @@ -7926,7 +7936,7 @@ int32_t lsm6dso32x_mag_z_orient_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_mag_y_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mag_y_orient_set(const stmdev_ctx_t *ctx, lsm6dso32x_mag_y_axis_t val) { lsm6dso32x_mag_cfg_a_t reg; @@ -7956,7 +7966,7 @@ int32_t lsm6dso32x_mag_y_orient_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_mag_y_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mag_y_orient_get(const stmdev_ctx_t *ctx, lsm6dso32x_mag_y_axis_t *val) { lsm6dso32x_mag_cfg_a_t reg; @@ -8010,7 +8020,7 @@ int32_t lsm6dso32x_mag_y_orient_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_mag_x_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mag_x_orient_set(const stmdev_ctx_t *ctx, lsm6dso32x_mag_x_axis_t val) { lsm6dso32x_mag_cfg_b_t reg; @@ -8040,7 +8050,7 @@ int32_t lsm6dso32x_mag_x_orient_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_mag_x_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mag_x_orient_get(const stmdev_ctx_t *ctx, lsm6dso32x_mag_x_axis_t *val) { lsm6dso32x_mag_cfg_b_t reg; @@ -8105,7 +8115,7 @@ int32_t lsm6dso32x_mag_x_orient_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_emb_func_status_t reg; @@ -8136,7 +8146,7 @@ int32_t lsm6dso32x_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fsm_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fsm_enable_set(const stmdev_ctx_t *ctx, lsm6dso32x_emb_fsm_enable_t *val) { int32_t ret; @@ -8171,7 +8181,7 @@ int32_t lsm6dso32x_fsm_enable_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fsm_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fsm_enable_get(const stmdev_ctx_t *ctx, lsm6dso32x_emb_fsm_enable_t *val) { int32_t ret; @@ -8202,7 +8212,7 @@ int32_t lsm6dso32x_fsm_enable_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dso32x_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -8234,7 +8244,7 @@ int32_t lsm6dso32x_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dso32x_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -8266,7 +8276,7 @@ int32_t lsm6dso32x_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_long_clr_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_long_clr_set(const stmdev_ctx_t *ctx, lsm6dso32x_fsm_lc_clr_t val) { lsm6dso32x_fsm_long_counter_clear_t reg; @@ -8304,7 +8314,7 @@ int32_t lsm6dso32x_long_clr_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_long_clr_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_long_clr_get(const stmdev_ctx_t *ctx, lsm6dso32x_fsm_lc_clr_t *val) { lsm6dso32x_fsm_long_counter_clear_t reg; @@ -8356,7 +8366,7 @@ int32_t lsm6dso32x_long_clr_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fsm_out_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dso32x_fsm_out_t *val) { int32_t ret; @@ -8385,7 +8395,7 @@ int32_t lsm6dso32x_fsm_out_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fsm_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fsm_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso32x_fsm_odr_t val) { lsm6dso32x_emb_func_odr_cfg_b_t reg; @@ -8424,7 +8434,7 @@ int32_t lsm6dso32x_fsm_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fsm_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fsm_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso32x_fsm_odr_t *val) { lsm6dso32x_emb_func_odr_cfg_b_t reg; @@ -8477,7 +8487,7 @@ int32_t lsm6dso32x_fsm_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_emb_func_init_b_t reg; int32_t ret; @@ -8513,7 +8523,7 @@ int32_t lsm6dso32x_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_emb_func_init_b_t reg; int32_t ret; @@ -8546,7 +8556,7 @@ int32_t lsm6dso32x_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_long_cnt_int_value_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val) { int32_t ret; @@ -8578,7 +8588,7 @@ int32_t lsm6dso32x_long_cnt_int_value_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_long_cnt_int_value_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val) { int32_t ret; @@ -8608,7 +8618,7 @@ int32_t lsm6dso32x_long_cnt_int_value_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fsm_number_of_programs_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; @@ -8626,7 +8636,7 @@ int32_t lsm6dso32x_fsm_number_of_programs_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fsm_number_of_programs_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -8645,7 +8655,7 @@ int32_t lsm6dso32x_fsm_number_of_programs_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fsm_start_address_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val) { int32_t ret; @@ -8675,7 +8685,7 @@ int32_t lsm6dso32x_fsm_start_address_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_fsm_start_address_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val) { int32_t ret; @@ -8718,7 +8728,7 @@ int32_t lsm6dso32x_fsm_start_address_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_mlc_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mlc_status_get(const stmdev_ctx_t *ctx, lsm6dso32x_mlc_status_mainpage_t *val) { return lsm6dso32x_read_reg(ctx, LSM6DSO32X_MLC_STATUS_MAINPAGE, @@ -8734,7 +8744,7 @@ int32_t lsm6dso32x_mlc_status_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_mlc_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mlc_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso32x_mlc_odr_t val) { lsm6dso32x_emb_func_odr_cfg_c_t reg; @@ -8772,7 +8782,7 @@ int32_t lsm6dso32x_mlc_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_mlc_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mlc_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso32x_mlc_odr_t *val) { lsm6dso32x_emb_func_odr_cfg_c_t reg; @@ -8837,7 +8847,7 @@ int32_t lsm6dso32x_mlc_data_rate_get(stmdev_ctx_t *ctx, * @param val union of registers from SENSOR_HUB_1 to SENSOR_HUB_18 * */ -int32_t lsm6dso32x_sh_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_read_data_raw_get(const stmdev_ctx_t *ctx, lsm6dso32x_emb_sh_read_t *val, uint8_t len) { @@ -8868,7 +8878,7 @@ int32_t lsm6dso32x_sh_read_data_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_slave_connected_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_slave_connected_set(const stmdev_ctx_t *ctx, lsm6dso32x_aux_sens_on_t val) { lsm6dso32x_master_config_t reg; @@ -8905,7 +8915,7 @@ int32_t lsm6dso32x_sh_slave_connected_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_slave_connected_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_slave_connected_get(const stmdev_ctx_t *ctx, lsm6dso32x_aux_sens_on_t *val) { lsm6dso32x_master_config_t reg; @@ -8958,7 +8968,7 @@ int32_t lsm6dso32x_sh_slave_connected_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_master_config_t reg; int32_t ret; @@ -8994,7 +9004,7 @@ int32_t lsm6dso32x_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_master_config_t reg; int32_t ret; @@ -9024,7 +9034,7 @@ int32_t lsm6dso32x_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_shub_pu_en_t val) { lsm6dso32x_master_config_t reg; @@ -9061,7 +9071,7 @@ int32_t lsm6dso32x_sh_pin_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_shub_pu_en_t *val) { lsm6dso32x_master_config_t reg; @@ -9107,7 +9117,7 @@ int32_t lsm6dso32x_sh_pin_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso32x_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso32x_master_config_t reg; int32_t ret; @@ -9144,7 +9154,7 @@ int32_t lsm6dso32x_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_pass_through_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_master_config_t reg; @@ -9175,7 +9185,7 @@ int32_t lsm6dso32x_sh_pass_through_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_syncro_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_start_config_t val) { lsm6dso32x_master_config_t reg; @@ -9212,7 +9222,7 @@ int32_t lsm6dso32x_sh_syncro_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_syncro_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_start_config_t *val) { lsm6dso32x_master_config_t reg; @@ -9258,7 +9268,7 @@ int32_t lsm6dso32x_sh_syncro_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_write_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_write_once_t val) { lsm6dso32x_master_config_t reg; @@ -9296,7 +9306,7 @@ int32_t lsm6dso32x_sh_write_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_write_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_write_once_t *val) { lsm6dso32x_master_config_t reg; @@ -9340,7 +9350,7 @@ int32_t lsm6dso32x_sh_write_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_reset_set(stmdev_ctx_t *ctx) +int32_t lsm6dso32x_sh_reset_set(const stmdev_ctx_t *ctx) { lsm6dso32x_master_config_t reg; int32_t ret; @@ -9383,7 +9393,7 @@ int32_t lsm6dso32x_sh_reset_set(stmdev_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso32x_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso32x_master_config_t reg; int32_t ret; @@ -9413,7 +9423,7 @@ int32_t lsm6dso32x_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso32x_shub_odr_t val) { lsm6dso32x_slv0_config_t reg; @@ -9450,7 +9460,7 @@ int32_t lsm6dso32x_sh_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso32x_shub_odr_t *val) { lsm6dso32x_slv0_config_t reg; @@ -9506,7 +9516,7 @@ int32_t lsm6dso32x_sh_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_cfg_write(const stmdev_ctx_t *ctx, lsm6dso32x_sh_cfg_write_t *val) { lsm6dso32x_slv0_add_t reg; @@ -9552,7 +9562,7 @@ int32_t lsm6dso32x_sh_cfg_write(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_slv0_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, lsm6dso32x_sh_cfg_read_t *val) { lsm6dso32x_slv0_add_t slv0_add; @@ -9607,7 +9617,7 @@ int32_t lsm6dso32x_sh_slv0_cfg_read(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_slv1_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, lsm6dso32x_sh_cfg_read_t *val) { lsm6dso32x_slv1_add_t slv1_add; @@ -9662,7 +9672,7 @@ int32_t lsm6dso32x_sh_slv1_cfg_read(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_slv2_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, lsm6dso32x_sh_cfg_read_t *val) { lsm6dso32x_slv2_add_t slv2_add; @@ -9717,7 +9727,7 @@ int32_t lsm6dso32x_sh_slv2_cfg_read(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_slv3_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, lsm6dso32x_sh_cfg_read_t *val) { lsm6dso32x_slv3_add_t slv3_add; @@ -9769,7 +9779,7 @@ int32_t lsm6dso32x_sh_slv3_cfg_read(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_sh_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_status_get(const stmdev_ctx_t *ctx, lsm6dso32x_status_master_t *val) { int32_t ret; @@ -9813,7 +9823,7 @@ int32_t lsm6dso32x_sh_status_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_id_get(stmdev_ctx_t *ctx, lsm6dso32x_id_t *val) +int32_t lsm6dso32x_id_get(const stmdev_ctx_t *ctx, lsm6dso32x_id_t *val) { int32_t ret = 0; @@ -9837,7 +9847,7 @@ int32_t lsm6dso32x_id_get(stmdev_ctx_t *ctx, lsm6dso32x_id_t *val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_init_set(stmdev_ctx_t *ctx, lsm6dso32x_init_t val) +int32_t lsm6dso32x_init_set(const stmdev_ctx_t *ctx, lsm6dso32x_init_t val) { lsm6dso32x_emb_func_init_a_t emb_func_init_a; lsm6dso32x_emb_func_init_b_t emb_func_init_b; @@ -9925,7 +9935,7 @@ int32_t lsm6dso32x_init_set(stmdev_ctx_t *ctx, lsm6dso32x_init_t val) * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_bus_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_bus_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_bus_mode_t val) { lsm6dso32x_i3c_bus_avb_t i3c_bus_avb; @@ -10010,7 +10020,7 @@ int32_t lsm6dso32x_bus_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_bus_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_bus_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_bus_mode_t *val) { lsm6dso32x_i3c_bus_avb_t i3c_bus_avb; @@ -10096,7 +10106,7 @@ int32_t lsm6dso32x_bus_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_status_get(const stmdev_ctx_t *ctx, lsm6dso32x_status_t *val) { lsm6dso32x_status_reg_t status_reg; @@ -10134,7 +10144,7 @@ int32_t lsm6dso32x_status_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_pin_conf_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pin_conf_set(const stmdev_ctx_t *ctx, lsm6dso32x_pin_conf_t val) { lsm6dso32x_i3c_bus_avb_t i3c_bus_avb; @@ -10190,7 +10200,7 @@ int32_t lsm6dso32x_pin_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_pin_conf_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pin_conf_get(const stmdev_ctx_t *ctx, lsm6dso32x_pin_conf_t *val) { lsm6dso32x_i3c_bus_avb_t i3c_bus_avb; @@ -10231,7 +10241,7 @@ int32_t lsm6dso32x_pin_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_interrupt_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_interrupt_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_int_mode_t val) { lsm6dso32x_tap_cfg0_t tap_cfg0; @@ -10297,7 +10307,7 @@ int32_t lsm6dso32x_interrupt_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_interrupt_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_interrupt_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_int_mode_t *val) { lsm6dso32x_tap_cfg0_t tap_cfg0; @@ -10351,7 +10361,7 @@ int32_t lsm6dso32x_interrupt_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm6dso32x_pin_int1_route_t val) { lsm6dso32x_pin_int2_route_t pin_int2_route; @@ -10603,7 +10613,7 @@ int32_t lsm6dso32x_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm6dso32x_pin_int1_route_t *val) { lsm6dso32x_emb_func_int1_t emb_func_int1; @@ -10744,7 +10754,7 @@ int32_t lsm6dso32x_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm6dso32x_pin_int2_route_t val) { lsm6dso32x_pin_int1_route_t pin_int1_route; @@ -10970,7 +10980,7 @@ int32_t lsm6dso32x_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pin_int2_route_get(const stmdev_ctx_t *ctx, lsm6dso32x_pin_int2_route_t *val) { lsm6dso32x_emb_func_int2_t emb_func_int2; @@ -11111,7 +11121,7 @@ int32_t lsm6dso32x_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_all_sources_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_all_sources_get(const stmdev_ctx_t *ctx, lsm6dso32x_all_sources_t *val) { lsm6dso32x_emb_func_status_mainpage_t emb_func_status_mainpage; @@ -11242,7 +11252,7 @@ int32_t lsm6dso32x_all_sources_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_md_t *val) { lsm6dso32x_func_cfg_access_t func_cfg_access; @@ -11306,7 +11316,7 @@ int32_t lsm6dso32x_mode_set(stmdev_ctx_t *ctx, { switch (val->fsm.odr) { - case LSM6DSO32X_FSM_12Hz5: + case LSM6DSO32X_ODR_FSM_12Hz5: if ((val->fsm.sens != LSM6DSO32X_FSM_GY) && (odr_xl == 0x00U)) { odr_xl = 0x01U; @@ -11320,7 +11330,7 @@ int32_t lsm6dso32x_mode_set(stmdev_ctx_t *ctx, break; - case LSM6DSO32X_FSM_26Hz: + case LSM6DSO32X_ODR_FSM_26Hz: if ((val->fsm.sens != LSM6DSO32X_FSM_GY) && (odr_xl < 0x02U)) { odr_xl = 0x02U; @@ -11334,7 +11344,7 @@ int32_t lsm6dso32x_mode_set(stmdev_ctx_t *ctx, break; - case LSM6DSO32X_FSM_52Hz: + case LSM6DSO32X_ODR_FSM_52Hz: if ((val->fsm.sens != LSM6DSO32X_FSM_GY) && (odr_xl < 0x03U)) { odr_xl = 0x03U; @@ -11348,7 +11358,7 @@ int32_t lsm6dso32x_mode_set(stmdev_ctx_t *ctx, break; - case LSM6DSO32X_FSM_104Hz: + case LSM6DSO32X_ODR_FSM_104Hz: if ((val->fsm.sens != LSM6DSO32X_FSM_GY) && (odr_xl < 0x04U)) { odr_xl = 0x04U; @@ -11374,7 +11384,7 @@ int32_t lsm6dso32x_mode_set(stmdev_ctx_t *ctx, { switch (val->mlc.odr) { - case LSM6DSO32X_MLC_12Hz5: + case LSM6DSO32X_ODR_PRGS_12Hz5: if (odr_xl == 0x00U) { odr_xl = 0x01U; @@ -11388,7 +11398,7 @@ int32_t lsm6dso32x_mode_set(stmdev_ctx_t *ctx, break; - case LSM6DSO32X_MLC_26Hz: + case LSM6DSO32X_ODR_PRGS_26Hz: if (odr_xl < 0x02U) { odr_xl = 0x02U; @@ -11402,7 +11412,7 @@ int32_t lsm6dso32x_mode_set(stmdev_ctx_t *ctx, break; - case LSM6DSO32X_MLC_52Hz: + case LSM6DSO32X_ODR_PRGS_52Hz: if (odr_xl < 0x03U) { odr_xl = 0x03U; @@ -11416,7 +11426,7 @@ int32_t lsm6dso32x_mode_set(stmdev_ctx_t *ctx, break; - case LSM6DSO32X_MLC_104Hz: + case LSM6DSO32X_ODR_PRGS_104Hz: if (odr_xl < 0x04U) { odr_xl = 0x04U; @@ -11657,7 +11667,7 @@ int32_t lsm6dso32x_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_md_t *val) { lsm6dso32x_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; @@ -11964,24 +11974,24 @@ int32_t lsm6dso32x_mode_get(stmdev_ctx_t *ctx, { switch (emb_func_odr_cfg_b.fsm_odr) { - case LSM6DSO32X_FSM_12Hz5: - val->fsm.odr = LSM6DSO32X_FSM_12Hz5; + case LSM6DSO32X_ODR_FSM_12Hz5: + val->fsm.odr = LSM6DSO32X_ODR_FSM_12Hz5; break; - case LSM6DSO32X_FSM_26Hz: - val->fsm.odr = LSM6DSO32X_FSM_26Hz; + case LSM6DSO32X_ODR_FSM_26Hz: + val->fsm.odr = LSM6DSO32X_ODR_FSM_26Hz; break; - case LSM6DSO32X_FSM_52Hz: - val->fsm.odr = LSM6DSO32X_FSM_52Hz; + case LSM6DSO32X_ODR_FSM_52Hz: + val->fsm.odr = LSM6DSO32X_ODR_FSM_52Hz; break; - case LSM6DSO32X_FSM_104Hz: - val->fsm.odr = LSM6DSO32X_FSM_104Hz; + case LSM6DSO32X_ODR_FSM_104Hz: + val->fsm.odr = LSM6DSO32X_ODR_FSM_104Hz; break; default: - val->fsm.odr = LSM6DSO32X_FSM_12Hz5; + val->fsm.odr = LSM6DSO32X_ODR_FSM_12Hz5; break; } @@ -12008,24 +12018,24 @@ int32_t lsm6dso32x_mode_get(stmdev_ctx_t *ctx, { switch (emb_func_odr_cfg_c.mlc_odr) { - case LSM6DSO32X_MLC_12Hz5: - val->mlc.odr = LSM6DSO32X_MLC_12Hz5; + case LSM6DSO32X_ODR_PRGS_12Hz5: + val->mlc.odr = LSM6DSO32X_ODR_PRGS_12Hz5; break; - case LSM6DSO32X_MLC_26Hz: - val->mlc.odr = LSM6DSO32X_MLC_26Hz; + case LSM6DSO32X_ODR_PRGS_26Hz: + val->mlc.odr = LSM6DSO32X_ODR_PRGS_26Hz; break; - case LSM6DSO32X_MLC_52Hz: - val->mlc.odr = LSM6DSO32X_MLC_52Hz; + case LSM6DSO32X_ODR_PRGS_52Hz: + val->mlc.odr = LSM6DSO32X_ODR_PRGS_52Hz; break; - case LSM6DSO32X_MLC_104Hz: - val->mlc.odr = LSM6DSO32X_MLC_104Hz; + case LSM6DSO32X_ODR_PRGS_104Hz: + val->mlc.odr = LSM6DSO32X_ODR_PRGS_104Hz; break; default: - val->mlc.odr = LSM6DSO32X_MLC_12Hz5; + val->mlc.odr = LSM6DSO32X_ODR_PRGS_12Hz5; break; } @@ -12058,7 +12068,7 @@ int32_t lsm6dso32x_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_data_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_data_get(const stmdev_ctx_t *ctx, lsm6dso32x_md_t *md, lsm6dso32x_data_t *data) { @@ -12167,7 +12177,7 @@ int32_t lsm6dso32x_data_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_embedded_sens_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_embedded_sens_set(const stmdev_ctx_t *ctx, lsm6dso32x_emb_sens_t *val) { lsm6dso32x_emb_func_en_a_t emb_func_en_a; @@ -12223,7 +12233,7 @@ int32_t lsm6dso32x_embedded_sens_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_embedded_sens_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_embedded_sens_get(const stmdev_ctx_t *ctx, lsm6dso32x_emb_sens_t *emb_sens) { lsm6dso32x_emb_func_en_a_t emb_func_en_a; @@ -12267,7 +12277,7 @@ int32_t lsm6dso32x_embedded_sens_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dso32x_embedded_sens_off(stmdev_ctx_t *ctx) +int32_t lsm6dso32x_embedded_sens_off(const stmdev_ctx_t *ctx) { lsm6dso32x_emb_func_en_a_t emb_func_en_a; lsm6dso32x_emb_func_en_b_t emb_func_en_b; diff --git a/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.h b/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.h index 5fec672d..67eb97ff 100644 --- a/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.h +++ b/sensor/stmemsc/lsm6dso32x_STdC/driver/lsm6dso32x_reg.h @@ -185,11 +185,9 @@ typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t not_used_01 : 6; -uint8_t reg_access : - 2; /* shub_reg_access + func_cfg_access */ + uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */ #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN -uint8_t reg_access : - 2; /* shub_reg_access + func_cfg_access */ + uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */ uint8_t not_used_01 : 6; #endif /* DRV_BYTE_ORDER */ } lsm6dso32x_func_cfg_access_t; @@ -440,11 +438,9 @@ typedef struct uint8_t ftype : 3; uint8_t usr_off_w : 1; uint8_t xl_hm_mode : 1; -uint8_t den_mode : - 3; /* trig_en + lvl1_en + lvl2_en */ + uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN -uint8_t den_mode : - 3; /* trig_en + lvl1_en + lvl2_en */ + uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ uint8_t xl_hm_mode : 1; uint8_t usr_off_w : 1; uint8_t ftype : 3; @@ -1422,13 +1418,11 @@ typedef struct typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN -uint8_t fsm_lc_clr : - 2; /* fsm_lc_cleared + fsm_lc_clear */ + uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ uint8_t not_used_01 : 6; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN uint8_t not_used_01 : 6; -uint8_t fsm_lc_clr : - 2; /* fsm_lc_cleared + fsm_lc_clear */ + uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ #endif /* DRV_BYTE_ORDER */ } lsm6dso32x_fsm_long_counter_clear_t; @@ -2756,9 +2750,9 @@ typedef union * them with a custom implementation. */ -int32_t lsm6dso32x_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, +int32_t lsm6dso32x_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lsm6dso32x_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, +int32_t lsm6dso32x_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); float_t lsm6dso32x_from_fs4_to_mg(int16_t lsb); @@ -2780,8 +2774,8 @@ typedef enum LSM6DSO32X_8g = 2, LSM6DSO32X_16g = 3, } lsm6dso32x_fs_xl_t; -int32_t lsm6dso32x_xl_full_scale_set(stmdev_ctx_t *ctx, lsm6dso32x_fs_xl_t val); -int32_t lsm6dso32x_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dso32x_fs_xl_t val); +int32_t lsm6dso32x_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dso32x_fs_xl_t *val); typedef enum @@ -2799,8 +2793,8 @@ typedef enum LSM6DSO32X_XL_ODR_6667Hz = 10, LSM6DSO32X_XL_ODR_1Hz6 = 11, /* (low power only) */ } lsm6dso32x_odr_xl_t; -int32_t lsm6dso32x_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6dso32x_odr_xl_t val); -int32_t lsm6dso32x_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso32x_odr_xl_t val); +int32_t lsm6dso32x_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso32x_odr_xl_t *val); typedef enum @@ -2811,8 +2805,8 @@ typedef enum LSM6DSO32X_1000dps = 4, LSM6DSO32X_2000dps = 6, } lsm6dso32x_fs_g_t; -int32_t lsm6dso32x_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6dso32x_fs_g_t val); -int32_t lsm6dso32x_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6dso32x_fs_g_t *val); +int32_t lsm6dso32x_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dso32x_fs_g_t val); +int32_t lsm6dso32x_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dso32x_fs_g_t *val); typedef enum { @@ -2828,14 +2822,14 @@ typedef enum LSM6DSO32X_GY_ODR_3333Hz = 9, LSM6DSO32X_GY_ODR_6667Hz = 10, } lsm6dso32x_odr_g_t; -int32_t lsm6dso32x_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_gy_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso32x_odr_g_t val); -int32_t lsm6dso32x_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso32x_odr_g_t *val); -int32_t lsm6dso32x_block_data_update_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2843,9 +2837,9 @@ typedef enum LSM6DSO32X_LSb_1mg = 0, LSM6DSO32X_LSb_16mg = 1, } lsm6dso32x_usr_off_w_t; -int32_t lsm6dso32x_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_offset_weight_set(const stmdev_ctx_t *ctx, lsm6dso32x_usr_off_w_t val); -int32_t lsm6dso32x_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_offset_weight_get(const stmdev_ctx_t *ctx, lsm6dso32x_usr_off_w_t *val); typedef enum @@ -2854,9 +2848,9 @@ typedef enum LSM6DSO32X_LOW_NORMAL_POWER_MD = 1, LSM6DSO32X_ULTRA_LOW_POWER_MD = 2, } lsm6dso32x_xl_hm_mode_t; -int32_t lsm6dso32x_xl_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_power_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_xl_hm_mode_t val); -int32_t lsm6dso32x_xl_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_power_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_xl_hm_mode_t *val); typedef enum @@ -2864,47 +2858,47 @@ typedef enum LSM6DSO32X_GY_HIGH_PERFORMANCE = 0, LSM6DSO32X_GY_NORMAL = 1, } lsm6dso32x_g_hm_mode_t; -int32_t lsm6dso32x_gy_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_gy_power_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_g_hm_mode_t val); -int32_t lsm6dso32x_gy_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_gy_power_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_g_hm_mode_t *val); -int32_t lsm6dso32x_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_status_reg_get(const stmdev_ctx_t *ctx, lsm6dso32x_status_reg_t *val); -int32_t lsm6dso32x_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_xl_usr_offset_x_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso32x_xl_usr_offset_x_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso32x_xl_usr_offset_y_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso32x_xl_usr_offset_y_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso32x_xl_usr_offset_z_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso32x_xl_usr_offset_z_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso32x_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32x_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32x_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_timestamp_rst(stmdev_ctx_t *ctx); +int32_t lsm6dso32x_timestamp_rst(const stmdev_ctx_t *ctx); -int32_t lsm6dso32x_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32x_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32x_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_timestamp_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); typedef enum @@ -2914,31 +2908,31 @@ typedef enum LSM6DSO32X_ROUND_GY = 2, LSM6DSO32X_ROUND_GY_XL = 3, } lsm6dso32x_rounding_t; -int32_t lsm6dso32x_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_rounding_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_rounding_t val); -int32_t lsm6dso32x_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_rounding_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_rounding_t *val); -int32_t lsm6dso32x_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dso32x_angular_rate_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dso32x_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dso32x_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dso32x_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso32x_number_of_steps_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_number_of_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dso32x_steps_reset(stmdev_ctx_t *ctx); +int32_t lsm6dso32x_steps_reset(const stmdev_ctx_t *ctx); -int32_t lsm6dso32x_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dso32x_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso32x_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32x_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32x_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2946,21 +2940,21 @@ typedef enum LSM6DSO32X_SENSOR_HUB_BANK = 1, LSM6DSO32X_EMBEDDED_FUNC_BANK = 2, } lsm6dso32x_reg_access_t; -int32_t lsm6dso32x_mem_bank_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dso32x_reg_access_t val); -int32_t lsm6dso32x_mem_bank_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dso32x_reg_access_t *val); -int32_t lsm6dso32x_ln_pg_write_byte(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val); -int32_t lsm6dso32x_ln_pg_read_byte(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val); -int32_t lsm6dso32x_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dso32x_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); -int32_t lsm6dso32x_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dso32x_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val); typedef enum @@ -2968,22 +2962,22 @@ typedef enum LSM6DSO32X_DRDY_LATCHED = 0, LSM6DSO32X_DRDY_PULSED = 1, } lsm6dso32x_dataready_pulsed_t; -int32_t lsm6dso32x_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_dataready_pulsed_t val); -int32_t lsm6dso32x_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_dataready_pulsed_t *val); -int32_t lsm6dso32x_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dso32x_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso32x_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32x_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32x_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_auto_increment_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32x_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32x_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32x_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2991,9 +2985,9 @@ typedef enum LSM6DSO32X_XL_ST_POSITIVE = 1, LSM6DSO32X_XL_ST_NEGATIVE = 2, } lsm6dso32x_st_xl_t; -int32_t lsm6dso32x_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dso32x_st_xl_t val); -int32_t lsm6dso32x_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dso32x_st_xl_t *val); typedef enum @@ -3002,20 +2996,20 @@ typedef enum LSM6DSO32X_GY_ST_POSITIVE = 1, LSM6DSO32X_GY_ST_NEGATIVE = 3, } lsm6dso32x_st_g_t; -int32_t lsm6dso32x_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dso32x_st_g_t val); -int32_t lsm6dso32x_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dso32x_st_g_t *val); -int32_t lsm6dso32x_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32x_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32x_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32x_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32x_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3029,13 +3023,13 @@ typedef enum LSM6DSO32X_AGGRESSIVE = 6, LSM6DSO32X_XTREME = 7, } lsm6dso32x_ftype_t; -int32_t lsm6dso32x_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dso32x_ftype_t val); -int32_t lsm6dso32x_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dso32x_ftype_t *val); -int32_t lsm6dso32x_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32x_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32x_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3063,14 +3057,14 @@ typedef enum LSM6DSO32X_LP_ODR_DIV_400 = 0x06, LSM6DSO32X_LP_ODR_DIV_800 = 0x07, } lsm6dso32x_hp_slope_xl_en_t; -int32_t lsm6dso32x_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, lsm6dso32x_hp_slope_xl_en_t val); -int32_t lsm6dso32x_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, lsm6dso32x_hp_slope_xl_en_t *val); -int32_t lsm6dso32x_xl_fast_settling_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_xl_fast_settling_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3078,9 +3072,9 @@ typedef enum LSM6DSO32X_USE_SLOPE = 0, LSM6DSO32X_USE_HPF = 1, } lsm6dso32x_slope_fds_t; -int32_t lsm6dso32x_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dso32x_slope_fds_t val); -int32_t lsm6dso32x_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dso32x_slope_fds_t *val); typedef enum @@ -3091,9 +3085,9 @@ typedef enum LSM6DSO32X_HP_FILTER_260mHz = 0x82, LSM6DSO32X_HP_FILTER_1Hz04 = 0x83, } lsm6dso32x_hpm_g_t; -int32_t lsm6dso32x_gy_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dso32x_hpm_g_t val); -int32_t lsm6dso32x_gy_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dso32x_hpm_g_t *val); typedef enum @@ -3101,9 +3095,9 @@ typedef enum LSM6DSO32X_PULL_UP_DISC = 0, LSM6DSO32X_PULL_UP_CONNECT = 1, } lsm6dso32x_sdo_pu_en_t; -int32_t lsm6dso32x_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_sdo_pu_en_t val); -int32_t lsm6dso32x_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_sdo_pu_en_t *val); typedef enum @@ -3111,9 +3105,9 @@ typedef enum LSM6DSO32X_SPI_4_WIRE = 0, LSM6DSO32X_SPI_3_WIRE = 1, } lsm6dso32x_sim_t; -int32_t lsm6dso32x_spi_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_sim_t val); -int32_t lsm6dso32x_spi_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_sim_t *val); typedef enum @@ -3121,9 +3115,9 @@ typedef enum LSM6DSO32X_I2C_ENABLE = 0, LSM6DSO32X_I2C_DISABLE = 1, } lsm6dso32x_i2c_disable_t; -int32_t lsm6dso32x_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_i2c_interface_set(const stmdev_ctx_t *ctx, lsm6dso32x_i2c_disable_t val); -int32_t lsm6dso32x_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_i2c_interface_get(const stmdev_ctx_t *ctx, lsm6dso32x_i2c_disable_t *val); typedef enum @@ -3134,9 +3128,9 @@ typedef enum LSM6DSO32X_I3C_ENABLE_T_1ms = 0x02, LSM6DSO32X_I3C_ENABLE_T_25ms = 0x03, } lsm6dso32x_i3c_disable_t; -int32_t lsm6dso32x_i3c_disable_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_i3c_disable_set(const stmdev_ctx_t *ctx, lsm6dso32x_i3c_disable_t val); -int32_t lsm6dso32x_i3c_disable_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_i3c_disable_get(const stmdev_ctx_t *ctx, lsm6dso32x_i3c_disable_t *val); typedef enum @@ -3146,9 +3140,9 @@ typedef enum LSM6DSO32X_INT1_NOPULL_DOWN_INT2_PUSH_PULL = 0x02, LSM6DSO32X_INT1_NOPULL_DOWN_INT2_OPEN_DRAIN = 0x03, } lsm6dso32x_pp_od_t; -int32_t lsm6dso32x_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_pp_od_t val); -int32_t lsm6dso32x_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_pp_od_t *val); typedef enum @@ -3156,13 +3150,13 @@ typedef enum LSM6DSO32X_ACTIVE_HIGH = 0, LSM6DSO32X_ACTIVE_LOW = 1, } lsm6dso32x_h_lactive_t; -int32_t lsm6dso32x_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pin_polarity_set(const stmdev_ctx_t *ctx, lsm6dso32x_h_lactive_t val); -int32_t lsm6dso32x_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pin_polarity_get(const stmdev_ctx_t *ctx, lsm6dso32x_h_lactive_t *val); -int32_t lsm6dso32x_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32x_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32x_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3171,9 +3165,9 @@ typedef enum LSM6DSO32X_BASE_PULSED_EMB_LATCHED = 2, LSM6DSO32X_ALL_INT_LATCHED = 3, } lsm6dso32x_lir_t; -int32_t lsm6dso32x_int_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_int_notification_set(const stmdev_ctx_t *ctx, lsm6dso32x_lir_t val); -int32_t lsm6dso32x_int_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_int_notification_get(const stmdev_ctx_t *ctx, lsm6dso32x_lir_t *val); typedef enum @@ -3181,34 +3175,34 @@ typedef enum LSM6DSO32X_LSb_FS_DIV_64 = 0, LSM6DSO32X_LSb_FS_DIV_256 = 1, } lsm6dso32x_wake_ths_w_t; -int32_t lsm6dso32x_wkup_ths_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_wkup_ths_weight_set(const stmdev_ctx_t *ctx, lsm6dso32x_wake_ths_w_t val); -int32_t lsm6dso32x_wkup_ths_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_wkup_ths_weight_get(const stmdev_ctx_t *ctx, lsm6dso32x_wake_ths_w_t *val); -int32_t lsm6dso32x_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_wkup_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32x_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32x_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32x_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32x_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32x_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSO32X_DRIVE_SLEEP_CHG_EVENT = 0, LSM6DSO32X_DRIVE_SLEEP_STATUS = 1, } lsm6dso32x_sleep_status_on_int_t; -int32_t lsm6dso32x_act_pin_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_act_pin_notification_set(const stmdev_ctx_t *ctx, lsm6dso32x_sleep_status_on_int_t val); -int32_t lsm6dso32x_act_pin_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_act_pin_notification_get(const stmdev_ctx_t *ctx, lsm6dso32x_sleep_status_on_int_t *val); typedef enum @@ -3218,32 +3212,32 @@ typedef enum LSM6DSO32X_XL_12Hz5_GY_SLEEP = 2, LSM6DSO32X_XL_12Hz5_GY_PD = 3, } lsm6dso32x_inact_en_t; -int32_t lsm6dso32x_act_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_act_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_inact_en_t val); -int32_t lsm6dso32x_act_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_act_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_inact_en_t *val); -int32_t lsm6dso32x_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32x_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32x_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_tap_threshold_x_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_tap_threshold_x_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3255,38 +3249,38 @@ typedef enum LSM6DSO32X_YZX = 5, LSM6DSO32X_ZXY = 6, } lsm6dso32x_tap_priority_t; -int32_t lsm6dso32x_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_axis_priority_set(const stmdev_ctx_t *ctx, lsm6dso32x_tap_priority_t val); -int32_t lsm6dso32x_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_axis_priority_get(const stmdev_ctx_t *ctx, lsm6dso32x_tap_priority_t *val); -int32_t lsm6dso32x_tap_threshold_y_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_tap_threshold_y_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_tap_threshold_z_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_tap_threshold_z_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32x_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32x_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32x_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32x_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32x_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32x_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSO32X_ONLY_SINGLE = 0, LSM6DSO32X_BOTH_SINGLE_DOUBLE = 1, } lsm6dso32x_single_double_tap_t; -int32_t lsm6dso32x_tap_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_single_double_tap_t val); -int32_t lsm6dso32x_tap_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_single_double_tap_t *val); typedef enum @@ -3296,13 +3290,13 @@ typedef enum LSM6DSO32X_DEG_60 = 2, LSM6DSO32X_DEG_50 = 3, } lsm6dso32x_sixd_ths_t; -int32_t lsm6dso32x_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_6d_threshold_set(const stmdev_ctx_t *ctx, lsm6dso32x_sixd_ths_t val); -int32_t lsm6dso32x_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_6d_threshold_get(const stmdev_ctx_t *ctx, lsm6dso32x_sixd_ths_t *val); -int32_t lsm6dso32x_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32x_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32x_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3310,22 +3304,22 @@ typedef enum LSM6DSO32X_FF_TSH_438mg = 1, LSM6DSO32X_FF_TSH_500mg = 2, } lsm6dso32x_ff_ths_t; -int32_t lsm6dso32x_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_ff_threshold_set(const stmdev_ctx_t *ctx, lsm6dso32x_ff_ths_t val); -int32_t lsm6dso32x_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_ff_threshold_get(const stmdev_ctx_t *ctx, lsm6dso32x_ff_ths_t *val); -int32_t lsm6dso32x_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32x_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32x_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_fifo_watermark_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dso32x_fifo_watermark_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dso32x_compression_algo_init_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_compression_algo_init_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_compression_algo_init_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_compression_algo_init_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3336,24 +3330,24 @@ typedef enum LSM6DSO32X_CMP_16_TO_1 = 0x06, LSM6DSO32X_CMP_32_TO_1 = 0x07, } lsm6dso32x_uncoptr_rate_t; -int32_t lsm6dso32x_compression_algo_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_compression_algo_set(const stmdev_ctx_t *ctx, lsm6dso32x_uncoptr_rate_t val); -int32_t lsm6dso32x_compression_algo_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_compression_algo_get(const stmdev_ctx_t *ctx, lsm6dso32x_uncoptr_rate_t *val); -int32_t lsm6dso32x_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_compression_algo_real_time_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_compression_algo_real_time_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_compression_algo_real_time_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_compression_algo_real_time_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3371,9 +3365,9 @@ typedef enum LSM6DSO32X_XL_BATCHED_AT_6667Hz = 10, LSM6DSO32X_XL_BATCHED_AT_6Hz5 = 11, } lsm6dso32x_bdr_xl_t; -int32_t lsm6dso32x_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_xl_batch_set(const stmdev_ctx_t *ctx, lsm6dso32x_bdr_xl_t val); -int32_t lsm6dso32x_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_xl_batch_get(const stmdev_ctx_t *ctx, lsm6dso32x_bdr_xl_t *val); typedef enum @@ -3391,9 +3385,9 @@ typedef enum LSM6DSO32X_GY_BATCHED_AT_6667Hz = 10, LSM6DSO32X_GY_BATCHED_AT_6Hz5 = 11, } lsm6dso32x_bdr_gy_t; -int32_t lsm6dso32x_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_gy_batch_set(const stmdev_ctx_t *ctx, lsm6dso32x_bdr_gy_t val); -int32_t lsm6dso32x_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_gy_batch_get(const stmdev_ctx_t *ctx, lsm6dso32x_bdr_gy_t *val); typedef enum @@ -3405,9 +3399,9 @@ typedef enum LSM6DSO32X_STREAM_MODE = 6, LSM6DSO32X_BYPASS_TO_FIFO_MODE = 7, } lsm6dso32x_fifo_mode_t; -int32_t lsm6dso32x_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_fifo_mode_t val); -int32_t lsm6dso32x_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_fifo_mode_t *val); typedef enum @@ -3417,9 +3411,9 @@ typedef enum LSM6DSO32X_TEMP_BATCHED_AT_12Hz5 = 2, LSM6DSO32X_TEMP_BATCHED_AT_52Hz = 3, } lsm6dso32x_odr_t_batch_t; -int32_t lsm6dso32x_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_temp_batch_set(const stmdev_ctx_t *ctx, lsm6dso32x_odr_t_batch_t val); -int32_t lsm6dso32x_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_temp_batch_get(const stmdev_ctx_t *ctx, lsm6dso32x_odr_t_batch_t *val); typedef enum @@ -3429,9 +3423,9 @@ typedef enum LSM6DSO32X_DEC_8 = 2, LSM6DSO32X_DEC_32 = 3, } lsm6dso32x_odr_ts_batch_t; -int32_t lsm6dso32x_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, lsm6dso32x_odr_ts_batch_t val); -int32_t lsm6dso32x_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, lsm6dso32x_odr_ts_batch_t *val); typedef enum @@ -3465,60 +3459,60 @@ typedef enum LSM6DSO32X_ROTATION_TAG, LSM6DSO32X_SENSORHUB_NACK_TAG = 0x19, } lsm6dso32x_fifo_tag_t; -int32_t lsm6dso32x_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, lsm6dso32x_trig_counter_bdr_t val); -int32_t lsm6dso32x_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, lsm6dso32x_trig_counter_bdr_t *val); -int32_t lsm6dso32x_rst_batch_counter_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_rst_batch_counter_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_batch_counter_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dso32x_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dso32x_fifo_data_level_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dso32x_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_status_get(const stmdev_ctx_t *ctx, lsm6dso32x_fifo_status2_t *val); -int32_t lsm6dso32x_fifo_full_flag_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32x_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32x_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_fifo_sensor_tag_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, lsm6dso32x_fifo_tag_t *val); -int32_t lsm6dso32x_fifo_pedo_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_fifo_pedo_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_sh_batch_slave_0_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_sh_batch_slave_0_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_sh_batch_slave_1_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_sh_batch_slave_1_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_sh_batch_slave_2_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_sh_batch_slave_2_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_sh_batch_slave_3_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_sh_batch_slave_3_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3529,9 +3523,9 @@ typedef enum LSM6DSO32X_LEVEL_TRIGGER = 2, LSM6DSO32X_EDGE_TRIGGER = 4, } lsm6dso32x_den_mode_t; -int32_t lsm6dso32x_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_den_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_den_mode_t val); -int32_t lsm6dso32x_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_den_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_den_mode_t *val); typedef enum @@ -3539,9 +3533,9 @@ typedef enum LSM6DSO32X_DEN_ACT_LOW = 0, LSM6DSO32X_DEN_ACT_HIGH = 1, } lsm6dso32x_den_lh_t; -int32_t lsm6dso32x_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dso32x_den_lh_t val); -int32_t lsm6dso32x_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dso32x_den_lh_t *val); typedef enum @@ -3550,24 +3544,24 @@ typedef enum LSM6DSO32X_STAMP_IN_XL_DATA = 1, LSM6DSO32X_STAMP_IN_GY_XL_DATA = 2, } lsm6dso32x_den_xl_g_t; -int32_t lsm6dso32x_den_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_den_enable_set(const stmdev_ctx_t *ctx, lsm6dso32x_den_xl_g_t val); -int32_t lsm6dso32x_den_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_den_enable_get(const stmdev_ctx_t *ctx, lsm6dso32x_den_xl_g_t *val); -int32_t lsm6dso32x_den_mark_axis_x_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_den_mark_axis_x_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_den_mark_axis_y_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_den_mark_axis_y_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_den_mark_axis_z_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_den_mark_axis_z_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3576,32 +3570,32 @@ typedef enum LSM6DSO32X_FALSE_STEP_REJ = 0x10, LSM6DSO32X_FALSE_STEP_REJ_ADV_MODE = 0x30, } lsm6dso32x_pedo_md_t; -int32_t lsm6dso32x_pedo_sens_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pedo_sens_set(const stmdev_ctx_t *ctx, lsm6dso32x_pedo_md_t val); -int32_t lsm6dso32x_pedo_sens_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pedo_sens_get(const stmdev_ctx_t *ctx, lsm6dso32x_pedo_md_t *val); -int32_t lsm6dso32x_pedo_step_detect_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pedo_step_detect_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_pedo_debounce_steps_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso32x_pedo_debounce_steps_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso32x_pedo_steps_period_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pedo_steps_period_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dso32x_pedo_steps_period_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pedo_steps_period_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dso32x_pedo_adv_detection_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pedo_adv_detection_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_pedo_adv_detection_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pedo_adv_detection_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_pedo_false_step_rejection_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pedo_false_step_rejection_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_pedo_false_step_rejection_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pedo_false_step_rejection_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3609,33 +3603,33 @@ typedef enum LSM6DSO32X_EVERY_STEP = 0, LSM6DSO32X_COUNT_OVERFLOW = 1, } lsm6dso32x_carry_count_en_t; -int32_t lsm6dso32x_pedo_int_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pedo_int_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_carry_count_en_t val); -int32_t lsm6dso32x_pedo_int_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pedo_int_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_carry_count_en_t *val); -int32_t lsm6dso32x_motion_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_motion_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_sh_mag_sensitivity_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dso32x_sh_mag_sensitivity_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dso32x_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mlc_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dso32x_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dso32x_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dso32x_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dso32x_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dso32x_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dso32x_mag_soft_iron_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dso32x_mag_soft_iron_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum @@ -3647,9 +3641,9 @@ typedef enum LSM6DSO32X_Z_EQ_MIN_Z = 4, LSM6DSO32X_Z_EQ_Z = 5, } lsm6dso32x_mag_z_axis_t; -int32_t lsm6dso32x_mag_z_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mag_z_orient_set(const stmdev_ctx_t *ctx, lsm6dso32x_mag_z_axis_t val); -int32_t lsm6dso32x_mag_z_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mag_z_orient_get(const stmdev_ctx_t *ctx, lsm6dso32x_mag_z_axis_t *val); typedef enum @@ -3661,9 +3655,9 @@ typedef enum LSM6DSO32X_Y_EQ_MIN_Z = 4, LSM6DSO32X_Y_EQ_Z = 5, } lsm6dso32x_mag_y_axis_t; -int32_t lsm6dso32x_mag_y_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mag_y_orient_set(const stmdev_ctx_t *ctx, lsm6dso32x_mag_y_axis_t val); -int32_t lsm6dso32x_mag_y_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mag_y_orient_get(const stmdev_ctx_t *ctx, lsm6dso32x_mag_y_axis_t *val); typedef enum @@ -3675,12 +3669,12 @@ typedef enum LSM6DSO32X_X_EQ_MIN_Z = 4, LSM6DSO32X_X_EQ_Z = 5, } lsm6dso32x_mag_x_axis_t; -int32_t lsm6dso32x_mag_x_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mag_x_orient_set(const stmdev_ctx_t *ctx, lsm6dso32x_mag_x_axis_t val); -int32_t lsm6dso32x_mag_x_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mag_x_orient_get(const stmdev_ctx_t *ctx, lsm6dso32x_mag_x_axis_t *val); -int32_t lsm6dso32x_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct @@ -3688,13 +3682,13 @@ typedef struct lsm6dso32x_fsm_enable_a_t fsm_enable_a; lsm6dso32x_fsm_enable_b_t fsm_enable_b; } lsm6dso32x_emb_fsm_enable_t; -int32_t lsm6dso32x_fsm_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fsm_enable_set(const stmdev_ctx_t *ctx, lsm6dso32x_emb_fsm_enable_t *val); -int32_t lsm6dso32x_fsm_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fsm_enable_get(const stmdev_ctx_t *ctx, lsm6dso32x_emb_fsm_enable_t *val); -int32_t lsm6dso32x_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dso32x_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dso32x_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dso32x_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum { @@ -3702,9 +3696,9 @@ typedef enum LSM6DSO32X_LC_CLEAR = 1, LSM6DSO32X_LC_CLEAR_DONE = 2, } lsm6dso32x_fsm_lc_clr_t; -int32_t lsm6dso32x_long_clr_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_long_clr_set(const stmdev_ctx_t *ctx, lsm6dso32x_fsm_lc_clr_t val); -int32_t lsm6dso32x_long_clr_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_long_clr_get(const stmdev_ctx_t *ctx, lsm6dso32x_fsm_lc_clr_t *val); typedef struct @@ -3726,7 +3720,7 @@ typedef struct lsm6dso32x_fsm_outs7_t fsm_outs15; lsm6dso32x_fsm_outs8_t fsm_outs16; } lsm6dso32x_fsm_out_t; -int32_t lsm6dso32x_fsm_out_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dso32x_fsm_out_t *val); typedef enum @@ -3736,30 +3730,30 @@ typedef enum LSM6DSO32X_ODR_FSM_52Hz = 2, LSM6DSO32X_ODR_FSM_104Hz = 3, } lsm6dso32x_fsm_odr_t; -int32_t lsm6dso32x_fsm_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fsm_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso32x_fsm_odr_t val); -int32_t lsm6dso32x_fsm_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fsm_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso32x_fsm_odr_t *val); -int32_t lsm6dso32x_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32x_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32x_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_long_cnt_int_value_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dso32x_long_cnt_int_value_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dso32x_fsm_number_of_programs_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_fsm_number_of_programs_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso32x_fsm_start_address_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dso32x_fsm_start_address_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dso32x_mlc_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mlc_status_get(const stmdev_ctx_t *ctx, lsm6dso32x_mlc_status_mainpage_t *val); typedef enum @@ -3769,9 +3763,9 @@ typedef enum LSM6DSO32X_ODR_PRGS_52Hz = 2, LSM6DSO32X_ODR_PRGS_104Hz = 3, } lsm6dso32x_mlc_odr_t; -int32_t lsm6dso32x_mlc_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mlc_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso32x_mlc_odr_t val); -int32_t lsm6dso32x_mlc_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mlc_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso32x_mlc_odr_t *val); typedef struct @@ -3795,7 +3789,7 @@ typedef struct lsm6dso32x_sensor_hub_17_t sh_byte_17; lsm6dso32x_sensor_hub_18_t sh_byte_18; } lsm6dso32x_emb_sh_read_t; -int32_t lsm6dso32x_sh_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_read_data_raw_get(const stmdev_ctx_t *ctx, lsm6dso32x_emb_sh_read_t *val, uint8_t len); @@ -3806,27 +3800,27 @@ typedef enum LSM6DSO32X_SLV_0_1_2 = 2, LSM6DSO32X_SLV_0_1_2_3 = 3, } lsm6dso32x_aux_sens_on_t; -int32_t lsm6dso32x_sh_slave_connected_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_slave_connected_set(const stmdev_ctx_t *ctx, lsm6dso32x_aux_sens_on_t val); -int32_t lsm6dso32x_sh_slave_connected_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_slave_connected_get(const stmdev_ctx_t *ctx, lsm6dso32x_aux_sens_on_t *val); -int32_t lsm6dso32x_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32x_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso32x_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSO32X_EXT_PULL_UP = 0, LSM6DSO32X_INTERNAL_PULL_UP = 1, } lsm6dso32x_shub_pu_en_t; -int32_t lsm6dso32x_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_shub_pu_en_t val); -int32_t lsm6dso32x_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_shub_pu_en_t *val); -int32_t lsm6dso32x_sh_pass_through_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso32x_sh_pass_through_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3834,9 +3828,9 @@ typedef enum LSM6DSO32X_EXT_ON_INT2_PIN = 1, LSM6DSO32X_XL_GY_DRDY = 0, } lsm6dso32x_start_config_t; -int32_t lsm6dso32x_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_syncro_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_start_config_t val); -int32_t lsm6dso32x_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_syncro_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_start_config_t *val); typedef enum @@ -3844,13 +3838,13 @@ typedef enum LSM6DSO32X_EACH_SH_CYCLE = 0, LSM6DSO32X_ONLY_FIRST_CYCLE = 1, } lsm6dso32x_write_once_t; -int32_t lsm6dso32x_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_write_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_write_once_t val); -int32_t lsm6dso32x_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_write_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_write_once_t *val); -int32_t lsm6dso32x_sh_reset_set(stmdev_ctx_t *ctx); -int32_t lsm6dso32x_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso32x_sh_reset_set(const stmdev_ctx_t *ctx); +int32_t lsm6dso32x_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3859,9 +3853,9 @@ typedef enum LSM6DSO32X_SH_ODR_26Hz = 2, LSM6DSO32X_SH_ODR_13Hz = 3, } lsm6dso32x_shub_odr_t; -int32_t lsm6dso32x_sh_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso32x_shub_odr_t val); -int32_t lsm6dso32x_sh_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso32x_shub_odr_t *val); typedef struct @@ -3870,7 +3864,7 @@ typedef struct uint8_t slv0_subadd; uint8_t slv0_data; } lsm6dso32x_sh_cfg_write_t; -int32_t lsm6dso32x_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_cfg_write(const stmdev_ctx_t *ctx, lsm6dso32x_sh_cfg_write_t *val); typedef struct @@ -3879,47 +3873,51 @@ typedef struct uint8_t slv_subadd; uint8_t slv_len; } lsm6dso32x_sh_cfg_read_t; -int32_t lsm6dso32x_sh_slv0_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, lsm6dso32x_sh_cfg_read_t *val); -int32_t lsm6dso32x_sh_slv1_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, lsm6dso32x_sh_cfg_read_t *val); -int32_t lsm6dso32x_sh_slv2_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, lsm6dso32x_sh_cfg_read_t *val); -int32_t lsm6dso32x_sh_slv3_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, lsm6dso32x_sh_cfg_read_t *val); -int32_t lsm6dso32x_sh_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_sh_status_get(const stmdev_ctx_t *ctx, lsm6dso32x_status_master_t *val); typedef struct { uint8_t ui; uint8_t aux; } lsm6dso32x_id_t; -int32_t lsm6dso32x_id_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_id_get(const stmdev_ctx_t *ctx, lsm6dso32x_id_t *val); +typedef enum +{ + LSM6DSO32X_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */ + LSM6DSO32X_SPI_4W = 0x06, /* Only SPI: SDO / SDI separated pins */ + LSM6DSO32X_SPI_3W = 0x07, /* Only SPI: SDO / SDI share the same pin */ + LSM6DSO32X_I2C = 0x04, /* Only I2C */ + LSM6DSO32X_I3C_T_50us = 0x02, /* I3C: available time equal to 50 μs */ + LSM6DSO32X_I3C_T_2us = 0x12, /* I3C: available time equal to 2 μs */ + LSM6DSO32X_I3C_T_1ms = 0x22, /* I3C: available time equal to 1 ms */ + LSM6DSO32X_I3C_T_25ms = 0x32, /* I3C: available time equal to 25 ms */ +} lsm6dso32x_ui_bus_md_t; + +typedef enum +{ + LSM6DSO32X_SPI_4W_AUX = 0x00, + LSM6DSO32X_SPI_3W_AUX = 0x01, +} lsm6dso32x_aux_bus_md_t; + typedef struct { - enum - { - LSM6DSO32X_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */ - LSM6DSO32X_SPI_4W = 0x06, /* Only SPI: SDO / SDI separated pins */ - LSM6DSO32X_SPI_3W = 0x07, /* Only SPI: SDO / SDI share the same pin */ - LSM6DSO32X_I2C = 0x04, /* Only I2C */ - LSM6DSO32X_I3C_T_50us = 0x02, /* I3C: available time equal to 50 μs */ - LSM6DSO32X_I3C_T_2us = 0x12, /* I3C: available time equal to 2 μs */ - LSM6DSO32X_I3C_T_1ms = 0x22, /* I3C: available time equal to 1 ms */ - LSM6DSO32X_I3C_T_25ms = 0x32, /* I3C: available time equal to 25 ms */ - } ui_bus_md; - enum - { - LSM6DSO32X_SPI_4W_AUX = 0x00, - LSM6DSO32X_SPI_3W_AUX = 0x01, - } aux_bus_md; + lsm6dso32x_ui_bus_md_t ui_bus_md; + lsm6dso32x_aux_bus_md_t aux_bus_md; } lsm6dso32x_bus_mode_t; -int32_t lsm6dso32x_bus_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_bus_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_bus_mode_t val); -int32_t lsm6dso32x_bus_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_bus_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_bus_mode_t *val); typedef enum @@ -3934,75 +3932,65 @@ typedef enum LSM6DSO32X_TILT = 0x40, /* Tilt algo initialization request */ LSM6DSO32X_SMOTION = 0x80, /* Significant Motion initialization request */ } lsm6dso32x_init_t; -int32_t lsm6dso32x_init_set(stmdev_ctx_t *ctx, lsm6dso32x_init_t val); +int32_t lsm6dso32x_init_set(const stmdev_ctx_t *ctx, lsm6dso32x_init_t val); typedef struct { -uint8_t sw_reset : - 1; /* Restoring configuration registers */ + uint8_t sw_reset : 1; /* Restoring configuration registers */ uint8_t boot : 1; /* Restoring calibration parameters */ uint8_t drdy_xl : 1; /* Accelerometer data ready */ uint8_t drdy_g : 1; /* Gyroscope data ready */ uint8_t drdy_temp : 1; /* Temperature data ready */ } lsm6dso32x_status_t; -int32_t lsm6dso32x_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_status_get(const stmdev_ctx_t *ctx, lsm6dso32x_status_t *val); typedef struct { uint8_t sdo_sa0_pull_up : 1; /* 1 = pull-up on SDO/SA0 pin */ -uint8_t aux_sdo_ocs_pull_up : - 1; /* 1 = pull-up on OCS_Aux/SDO_Aux pins */ + uint8_t aux_sdo_ocs_pull_up : 1; /* 1 = pull-up on OCS_Aux/SDO_Aux pins */ uint8_t int1_int2_push_pull : 1; /* 1 = push-pull / 0 = open-drain*/ -uint8_t int1_pull_down : - 1; /* 1 = pull-down always disabled (0=auto) */ + uint8_t int1_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */ } lsm6dso32x_pin_conf_t; -int32_t lsm6dso32x_pin_conf_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pin_conf_set(const stmdev_ctx_t *ctx, lsm6dso32x_pin_conf_t val); -int32_t lsm6dso32x_pin_conf_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pin_conf_get(const stmdev_ctx_t *ctx, lsm6dso32x_pin_conf_t *val); typedef struct { uint8_t active_low : 1; /* 1 = active low / 0 = active high */ -uint8_t base_latched : - 1; /* base functions are: FF, WU, 6D, Tap, Act/Inac */ -uint8_t emb_latched : - 1; /* emb functions are: Pedo, Tilt, SMot, Timestamp */ + uint8_t base_latched : 1; /* base functions are: FF, WU, 6D, Tap, Act/Inac */ + uint8_t emb_latched : 1; /* emb functions are: Pedo, Tilt, SMot, Timestamp */ } lsm6dso32x_int_mode_t; -int32_t lsm6dso32x_interrupt_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_interrupt_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_int_mode_t val); -int32_t lsm6dso32x_interrupt_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_interrupt_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_int_mode_t *val); typedef struct { uint8_t drdy_xl : 1; /* Accelerometer data ready */ uint8_t drdy_g : 1; /* Gyroscope data ready */ -uint8_t drdy_temp : - 1; /* Temperature data ready (1 = int2 pin disable) */ + uint8_t drdy_temp : 1; /* Temperature data ready (1 = int2 pin disable) */ uint8_t boot : 1; /* Restoring calibration parameters */ uint8_t fifo_th : 1; /* FIFO threshold reached */ uint8_t fifo_ovr : 1; /* FIFO overrun */ uint8_t fifo_full : 1; /* FIFO full */ uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */ -uint8_t den_flag : - 1; /* external trigger level recognition (DEN) */ + uint8_t den_flag : 1; /* external trigger level recognition (DEN) */ uint8_t sh_endop : 1; /* sensor hub end operation */ -uint8_t timestamp : - 1; /* timestamp overflow (1 = int2 pin disable) */ + uint8_t timestamp : 1; /* timestamp overflow (1 = int2 pin disable) */ uint8_t six_d : 1; /* orientation change (6D/4D detection) */ uint8_t double_tap : 1; /* double-tap event */ uint8_t free_fall : 1; /* free fall event */ uint8_t wake_up : 1; /* wake up event */ uint8_t single_tap : 1; /* single-tap event */ -uint8_t sleep_change : - 1; /* Act/Inact (or Vice-versa) status changed */ + uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ uint8_t step_detector : 1; /* Step detected */ uint8_t tilt : 1; /* Relative tilt event detected */ uint8_t sig_mot : 1; /* "significant motion" event detected */ -uint8_t fsm_lc : - 1; /* fsm long counter timeout interrupt event */ + uint8_t fsm_lc : 1; /* fsm long counter timeout interrupt event */ uint8_t fsm1 : 1; /* fsm 1 interrupt event */ uint8_t fsm2 : 1; /* fsm 2 interrupt event */ uint8_t fsm3 : 1; /* fsm 3 interrupt event */ @@ -4029,9 +4017,9 @@ uint8_t fsm_lc : uint8_t mlc8 : 1; /* mlc 8 interrupt event */ } lsm6dso32x_pin_int1_route_t; -int32_t lsm6dso32x_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm6dso32x_pin_int1_route_t val); -int32_t lsm6dso32x_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm6dso32x_pin_int1_route_t *val); typedef struct @@ -4049,13 +4037,11 @@ typedef struct uint8_t free_fall : 1; /* free fall event */ uint8_t wake_up : 1; /* wake up event */ uint8_t single_tap : 1; /* single-tap event */ -uint8_t sleep_change : - 1; /* Act/Inact (or Vice-versa) status changed */ + uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ uint8_t step_detector : 1; /* Step detected */ uint8_t tilt : 1; /* Relative tilt event detected */ uint8_t sig_mot : 1; /* "significant motion" event detected */ -uint8_t fsm_lc : - 1; /* fsm long counter timeout interrupt event */ + uint8_t fsm_lc : 1; /* fsm long counter timeout interrupt event */ uint8_t fsm1 : 1; /* fsm 1 interrupt event */ uint8_t fsm2 : 1; /* fsm 2 interrupt event */ uint8_t fsm3 : 1; /* fsm 3 interrupt event */ @@ -4082,9 +4068,9 @@ uint8_t fsm_lc : uint8_t mlc8 : 1; /* mlc 8 interrupt event */ } lsm6dso32x_pin_int2_route_t; -int32_t lsm6dso32x_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm6dso32x_pin_int2_route_t val); -int32_t lsm6dso32x_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_pin_int2_route_get(const stmdev_ctx_t *ctx, lsm6dso32x_pin_int2_route_t *val); typedef struct @@ -4092,10 +4078,8 @@ typedef struct uint8_t drdy_xl : 1; /* Accelerometer data ready */ uint8_t drdy_g : 1; /* Gyroscope data ready */ uint8_t drdy_temp : 1; /* Temperature data ready */ -uint8_t den_flag : - 1; /* external trigger level recognition (DEN) */ -uint8_t timestamp : - 1; /* timestamp overflow (1 = int2 pin disable) */ + uint8_t den_flag : 1; /* external trigger level recognition (DEN) */ + uint8_t timestamp : 1; /* timestamp overflow (1 = int2 pin disable) */ uint8_t free_fall : 1; /* free fall event */ uint8_t wake_up : 1; /* wake up event */ uint8_t wake_up_z : 1; /* wake up on Z axis event */ @@ -4107,30 +4091,19 @@ uint8_t timestamp : uint8_t tap_y : 1; /* single-tap on Y axis event */ uint8_t tap_x : 1; /* single-tap on X axis event */ uint8_t tap_sign : 1; /* sign of tap event (0-pos / 1-neg) */ -uint8_t six_d : - 1; /* orientation change (6D/4D detection) */ -uint8_t six_d_xl : - 1; /* X-axis low 6D/4D event (under threshold) */ -uint8_t six_d_xh : - 1; /* X-axis high 6D/4D event (over threshold) */ -uint8_t six_d_yl : - 1; /* Y-axis low 6D/4D event (under threshold) */ -uint8_t six_d_yh : - 1; /* Y-axis high 6D/4D event (over threshold) */ -uint8_t six_d_zl : - 1; /* Z-axis low 6D/4D event (under threshold) */ -uint8_t six_d_zh : - 1; /* Z-axis high 6D/4D event (over threshold) */ -uint8_t sleep_change : - 1; /* Act/Inact (or Vice-versa) status changed */ -uint8_t sleep_state : - 1; /* Act/Inact status flag (0-Act / 1-Inact) */ + uint8_t six_d : 1; /* orientation change (6D/4D detection) */ + uint8_t six_d_xl : 1; /* X-axis low 6D/4D event (under threshold) */ + uint8_t six_d_xh : 1; /* X-axis high 6D/4D event (over threshold) */ + uint8_t six_d_yl : 1; /* Y-axis low 6D/4D event (under threshold) */ + uint8_t six_d_yh : 1; /* Y-axis high 6D/4D event (over threshold) */ + uint8_t six_d_zl : 1; /* Z-axis low 6D/4D event (under threshold) */ + uint8_t six_d_zh : 1; /* Z-axis high 6D/4D event (over threshold) */ + uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ + uint8_t sleep_state : 1; /* Act/Inact status flag (0-Act / 1-Inact) */ uint8_t step_detector : 1; /* Step detected */ uint8_t tilt : 1; /* Relative tilt event detected */ -uint8_t sig_mot : - 1; /* "significant motion" event detected */ -uint8_t fsm_lc : - 1; /* fsm long counter timeout interrupt event */ + uint8_t sig_mot : 1; /* "significant motion" event detected */ + uint8_t fsm_lc : 1; /* fsm long counter timeout interrupt event */ uint8_t fsm1 : 1; /* fsm 1 interrupt event */ uint8_t fsm2 : 1; /* fsm 2 interrupt event */ uint8_t fsm3 : 1; /* fsm 3 interrupt event */ @@ -4156,143 +4129,136 @@ uint8_t fsm_lc : uint8_t mlc7 : 1; /* mlc 7 interrupt event */ uint8_t mlc8 : 1; /* mlc 8 interrupt event */ uint8_t sh_endop : 1; /* sensor hub end operation */ -uint8_t sh_slave0_nack : - 1; /* Not acknowledge on sensor hub slave 0 */ -uint8_t sh_slave1_nack : - 1; /* Not acknowledge on sensor hub slave 1 */ -uint8_t sh_slave2_nack : - 1; /* Not acknowledge on sensor hub slave 2 */ -uint8_t sh_slave3_nack : - 1; /* Not acknowledge on sensor hub slave 3 */ -uint8_t sh_wr_once : - 1; /* "WRITE_ONCE" end on sensor hub slave 0 */ -uint16_t fifo_diff : - 10; /* Number of unread sensor data in FIFO*/ + uint8_t sh_slave0_nack : 1; /* Not acknowledge on sensor hub slave 0 */ + uint8_t sh_slave1_nack : 1; /* Not acknowledge on sensor hub slave 1 */ + uint8_t sh_slave2_nack : 1; /* Not acknowledge on sensor hub slave 2 */ + uint8_t sh_slave3_nack : 1; /* Not acknowledge on sensor hub slave 3 */ + uint8_t sh_wr_once : 1; /* "WRITE_ONCE" end on sensor hub slave 0 */ + uint16_t fifo_diff : 10; /* Number of unread sensor data in FIFO*/ uint8_t fifo_ovr_latched : 1; /* Latched FIFO overrun status */ -uint8_t fifo_bdr : - 1; /* FIFO Batch counter threshold reached */ + uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */ uint8_t fifo_full : 1; /* FIFO full */ uint8_t fifo_ovr : 1; /* FIFO overrun */ uint8_t fifo_th : 1; /* FIFO threshold reached */ } lsm6dso32x_all_sources_t; -int32_t lsm6dso32x_all_sources_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_all_sources_get(const stmdev_ctx_t *ctx, lsm6dso32x_all_sources_t *val); typedef struct { uint8_t odr_fine_tune; } lsm6dso32x_dev_cal_t; -int32_t lsm6dso32x_calibration_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_calibration_get(const stmdev_ctx_t *ctx, lsm6dso32x_dev_cal_t *val); +typedef enum +{ + LSM6DSO32X_XL_UI_OFF = 0x00, /* in power down */ + LSM6DSO32X_XL_UI_1Hz6_LP = 0x1B, /* @1Hz6 (low power) */ + LSM6DSO32X_XL_UI_1Hz6_ULP = 0x2B, /* @1Hz6 (ultra low/Gy) */ + LSM6DSO32X_XL_UI_12Hz5_HP = 0x01, /* @12Hz5 (high performance) */ + LSM6DSO32X_XL_UI_12Hz5_LP = 0x11, /* @12Hz5 (low power) */ + LSM6DSO32X_XL_UI_12Hz5_ULP = 0x21, /* @12Hz5 (ultra low/Gy) */ + LSM6DSO32X_XL_UI_26Hz_HP = 0x02, /* @26Hz (high performance) */ + LSM6DSO32X_XL_UI_26Hz_LP = 0x12, /* @26Hz (low power) */ + LSM6DSO32X_XL_UI_26Hz_ULP = 0x22, /* @26Hz (ultra low/Gy) */ + LSM6DSO32X_XL_UI_52Hz_HP = 0x03, /* @52Hz (high performance) */ + LSM6DSO32X_XL_UI_52Hz_LP = 0x13, /* @52Hz (low power) */ + LSM6DSO32X_XL_UI_52Hz_ULP = 0x23, /* @52Hz (ultra low/Gy) */ + LSM6DSO32X_XL_UI_104Hz_HP = 0x04, /* @104Hz (high performance) */ + LSM6DSO32X_XL_UI_104Hz_NM = 0x14, /* @104Hz (normal mode) */ + LSM6DSO32X_XL_UI_104Hz_ULP = 0x24, /* @104Hz (ultra low/Gy) */ + LSM6DSO32X_XL_UI_208Hz_HP = 0x05, /* @208Hz (high performance) */ + LSM6DSO32X_XL_UI_208Hz_NM = 0x15, /* @208Hz (normal mode) */ + LSM6DSO32X_XL_UI_208Hz_ULP = 0x25, /* @208Hz (ultra low/Gy) */ + LSM6DSO32X_XL_UI_416Hz_HP = 0x06, /* @416Hz (high performance) */ + LSM6DSO32X_XL_UI_833Hz_HP = 0x07, /* @833Hz (high performance) */ + LSM6DSO32X_XL_UI_1667Hz_HP = 0x08, /* @1kHz66 (high performance) */ + LSM6DSO32X_XL_UI_3333Hz_HP = 0x09, /* @3kHz33 (high performance) */ + LSM6DSO32X_XL_UI_6667Hz_HP = 0x0A, /* @6kHz66 (high performance) */ +} lsm6dso32x_ui_xl_odr_t; + +typedef enum +{ + LSM6DSO32X_XL_UI_4g = 0, + LSM6DSO32X_XL_UI_32g = 1, + LSM6DSO32X_XL_UI_8g = 2, + LSM6DSO32X_XL_UI_16g = 3, +} lsm6dso32x_ui_xl_fs_t; + +typedef enum +{ + LSM6DSO32X_GY_UI_OFF = 0x00, /* gy in power down */ + LSM6DSO32X_GY_UI_12Hz5_LP = 0x11, /* gy @12Hz5 (low power) */ + LSM6DSO32X_GY_UI_12Hz5_HP = 0x01, /* gy @12Hz5 (high performance) */ + LSM6DSO32X_GY_UI_26Hz_LP = 0x12, /* gy @26Hz (low power) */ + LSM6DSO32X_GY_UI_26Hz_HP = 0x02, /* gy @26Hz (high performance) */ + LSM6DSO32X_GY_UI_52Hz_LP = 0x13, /* gy @52Hz (low power) */ + LSM6DSO32X_GY_UI_52Hz_HP = 0x03, /* gy @52Hz (high performance) */ + LSM6DSO32X_GY_UI_104Hz_NM = 0x14, /* gy @104Hz (low power) */ + LSM6DSO32X_GY_UI_104Hz_HP = 0x04, /* gy @104Hz (high performance) */ + LSM6DSO32X_GY_UI_208Hz_NM = 0x15, /* gy @208Hz (low power) */ + LSM6DSO32X_GY_UI_208Hz_HP = 0x05, /* gy @208Hz (high performance) */ + LSM6DSO32X_GY_UI_416Hz_HP = 0x06, /* gy @416Hz (high performance) */ + LSM6DSO32X_GY_UI_833Hz_HP = 0x07, /* gy @833Hz (high performance) */ + LSM6DSO32X_GY_UI_1667Hz_HP = 0x08, /* gy @1kHz66 (high performance) */ + LSM6DSO32X_GY_UI_3333Hz_HP = 0x09, /* gy @3kHz33 (high performance) */ + LSM6DSO32X_GY_UI_6667Hz_HP = 0x0A, /* gy @6kHz66 (high performance) */ +} lsm6dso32x_ui_gy_odr_t; + +typedef enum +{ + LSM6DSO32X_GY_UI_250dps = 0, + LSM6DSO32X_GY_UI_125dps = 1, + LSM6DSO32X_GY_UI_500dps = 2, + LSM6DSO32X_GY_UI_1000dps = 4, + LSM6DSO32X_GY_UI_2000dps = 6, +} lsm6dso32x_ui_gy_fs_t; + +typedef enum +{ + LSM6DSO32X_FSM_DISABLE = 0x00, + LSM6DSO32X_FSM_XL = 0x01, + LSM6DSO32X_FSM_GY = 0x02, + LSM6DSO32X_FSM_XL_GY = 0x03, +} lsm6dso32x_fsm_sens_t; + +typedef enum +{ + LSM6DSO32X_MLC_DISABLE = 0x00, + LSM6DSO32X_MLC_XL = 0x01, + LSM6DSO32X_MLC_XL_GY = 0x03, +} lsm6dso32x_mlc_sens_t; + typedef struct { struct { struct { - enum - { - LSM6DSO32X_XL_UI_OFF = 0x00, /* in power down */ - LSM6DSO32X_XL_UI_1Hz6_LP = 0x1B, /* @1Hz6 (low power) */ - LSM6DSO32X_XL_UI_1Hz6_ULP = 0x2B, /* @1Hz6 (ultra low/Gy) */ - LSM6DSO32X_XL_UI_12Hz5_HP = 0x01, /* @12Hz5 (high performance) */ - LSM6DSO32X_XL_UI_12Hz5_LP = 0x11, /* @12Hz5 (low power) */ - LSM6DSO32X_XL_UI_12Hz5_ULP = 0x21, /* @12Hz5 (ultra low/Gy) */ - LSM6DSO32X_XL_UI_26Hz_HP = 0x02, /* @26Hz (high performance) */ - LSM6DSO32X_XL_UI_26Hz_LP = 0x12, /* @26Hz (low power) */ - LSM6DSO32X_XL_UI_26Hz_ULP = 0x22, /* @26Hz (ultra low/Gy) */ - LSM6DSO32X_XL_UI_52Hz_HP = 0x03, /* @52Hz (high performance) */ - LSM6DSO32X_XL_UI_52Hz_LP = 0x13, /* @52Hz (low power) */ - LSM6DSO32X_XL_UI_52Hz_ULP = 0x23, /* @52Hz (ultra low/Gy) */ - LSM6DSO32X_XL_UI_104Hz_HP = 0x04, /* @104Hz (high performance) */ - LSM6DSO32X_XL_UI_104Hz_NM = 0x14, /* @104Hz (normal mode) */ - LSM6DSO32X_XL_UI_104Hz_ULP = 0x24, /* @104Hz (ultra low/Gy) */ - LSM6DSO32X_XL_UI_208Hz_HP = 0x05, /* @208Hz (high performance) */ - LSM6DSO32X_XL_UI_208Hz_NM = 0x15, /* @208Hz (normal mode) */ - LSM6DSO32X_XL_UI_208Hz_ULP = 0x25, /* @208Hz (ultra low/Gy) */ - LSM6DSO32X_XL_UI_416Hz_HP = 0x06, /* @416Hz (high performance) */ - LSM6DSO32X_XL_UI_833Hz_HP = 0x07, /* @833Hz (high performance) */ - LSM6DSO32X_XL_UI_1667Hz_HP = 0x08, /* @1kHz66 (high performance) */ - LSM6DSO32X_XL_UI_3333Hz_HP = 0x09, /* @3kHz33 (high performance) */ - LSM6DSO32X_XL_UI_6667Hz_HP = 0x0A, /* @6kHz66 (high performance) */ - } odr; - enum - { - LSM6DSO32X_XL_UI_4g = 0, - LSM6DSO32X_XL_UI_32g = 1, - LSM6DSO32X_XL_UI_8g = 2, - LSM6DSO32X_XL_UI_16g = 3, - } fs; + lsm6dso32x_ui_xl_odr_t odr; + lsm6dso32x_ui_xl_fs_t fs; } xl; struct { - enum - { - LSM6DSO32X_GY_UI_OFF = 0x00, /* gy in power down */ - LSM6DSO32X_GY_UI_12Hz5_LP = 0x11, /* gy @12Hz5 (low power) */ - LSM6DSO32X_GY_UI_12Hz5_HP = 0x01, /* gy @12Hz5 (high performance) */ - LSM6DSO32X_GY_UI_26Hz_LP = 0x12, /* gy @26Hz (low power) */ - LSM6DSO32X_GY_UI_26Hz_HP = 0x02, /* gy @26Hz (high performance) */ - LSM6DSO32X_GY_UI_52Hz_LP = 0x13, /* gy @52Hz (low power) */ - LSM6DSO32X_GY_UI_52Hz_HP = 0x03, /* gy @52Hz (high performance) */ - LSM6DSO32X_GY_UI_104Hz_NM = 0x14, /* gy @104Hz (low power) */ - LSM6DSO32X_GY_UI_104Hz_HP = 0x04, /* gy @104Hz (high performance) */ - LSM6DSO32X_GY_UI_208Hz_NM = 0x15, /* gy @208Hz (low power) */ - LSM6DSO32X_GY_UI_208Hz_HP = 0x05, /* gy @208Hz (high performance) */ - LSM6DSO32X_GY_UI_416Hz_HP = 0x06, /* gy @416Hz (high performance) */ - LSM6DSO32X_GY_UI_833Hz_HP = 0x07, /* gy @833Hz (high performance) */ - LSM6DSO32X_GY_UI_1667Hz_HP = 0x08, /* gy @1kHz66 (high performance) */ - LSM6DSO32X_GY_UI_3333Hz_HP = 0x09, /* gy @3kHz33 (high performance) */ - LSM6DSO32X_GY_UI_6667Hz_HP = 0x0A, /* gy @6kHz66 (high performance) */ - } odr; - enum - { - LSM6DSO32X_GY_UI_250dps = 0, - LSM6DSO32X_GY_UI_125dps = 1, - LSM6DSO32X_GY_UI_500dps = 2, - LSM6DSO32X_GY_UI_1000dps = 4, - LSM6DSO32X_GY_UI_2000dps = 6, - } fs; + lsm6dso32x_ui_gy_odr_t odr; + lsm6dso32x_ui_gy_fs_t fs; } gy; } ui; struct { - enum - { - LSM6DSO32X_FSM_DISABLE = 0x00, - LSM6DSO32X_FSM_XL = 0x01, - LSM6DSO32X_FSM_GY = 0x02, - LSM6DSO32X_FSM_XL_GY = 0x03, - } sens; - enum - { - LSM6DSO32X_FSM_12Hz5 = 0x00, - LSM6DSO32X_FSM_26Hz = 0x01, - LSM6DSO32X_FSM_52Hz = 0x02, - LSM6DSO32X_FSM_104Hz = 0x03, - } odr; + lsm6dso32x_fsm_sens_t sens; + lsm6dso32x_fsm_odr_t odr; } fsm; struct { - enum - { - LSM6DSO32X_MLC_DISABLE = 0x00, - LSM6DSO32X_MLC_XL = 0x01, - LSM6DSO32X_MLC_XL_GY = 0x03, - } sens; - enum - { - LSM6DSO32X_MLC_12Hz5 = 0x00, - LSM6DSO32X_MLC_26Hz = 0x01, - LSM6DSO32X_MLC_52Hz = 0x02, - LSM6DSO32X_MLC_104Hz = 0x03, - } odr; + lsm6dso32x_mlc_sens_t sens; + lsm6dso32x_mlc_odr_t odr; } mlc; } lsm6dso32x_md_t; -int32_t lsm6dso32x_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mode_set(const stmdev_ctx_t *ctx, lsm6dso32x_md_t *val); -int32_t lsm6dso32x_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_mode_get(const stmdev_ctx_t *ctx, lsm6dso32x_md_t *val); typedef struct @@ -4316,7 +4282,7 @@ typedef struct } heat; } ui; } lsm6dso32x_data_t; -int32_t lsm6dso32x_data_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_data_get(const stmdev_ctx_t *ctx, lsm6dso32x_md_t *md, lsm6dso32x_data_t *data); @@ -4329,11 +4295,11 @@ typedef struct uint8_t fsm : 1; /* finite state machine */ uint8_t fifo_compr : 1; /* mlc 8 interrupt event */ } lsm6dso32x_emb_sens_t; -int32_t lsm6dso32x_embedded_sens_set(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_embedded_sens_set(const stmdev_ctx_t *ctx, lsm6dso32x_emb_sens_t *emb_sens); -int32_t lsm6dso32x_embedded_sens_get(stmdev_ctx_t *ctx, +int32_t lsm6dso32x_embedded_sens_get(const stmdev_ctx_t *ctx, lsm6dso32x_emb_sens_t *emb_sens); -int32_t lsm6dso32x_embedded_sens_off(stmdev_ctx_t *ctx); +int32_t lsm6dso32x_embedded_sens_off(const stmdev_ctx_t *ctx); /** * @} diff --git a/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.c b/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.c index fe751a1f..4ca7b0be 100644 --- a/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.c +++ b/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.c @@ -47,12 +47,14 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm6dso_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm6dso_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -68,12 +70,14 @@ int32_t __weak lsm6dso_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm6dso_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm6dso_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -180,7 +184,7 @@ float_t lsm6dso_from_lsb_to_nsec(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dso_fs_xl_t val) { lsm6dso_ctrl1_xl_t reg; @@ -205,7 +209,7 @@ int32_t lsm6dso_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dso_fs_xl_t *val) { lsm6dso_ctrl1_xl_t reg; @@ -247,7 +251,7 @@ int32_t lsm6dso_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso_odr_xl_t val) { lsm6dso_odr_xl_t odr_xl = val; @@ -375,7 +379,7 @@ int32_t lsm6dso_xl_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso_odr_xl_t *val) { lsm6dso_ctrl1_xl_t reg; @@ -449,7 +453,7 @@ int32_t lsm6dso_xl_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dso_fs_g_t val) { lsm6dso_ctrl2_g_t reg; @@ -474,7 +478,7 @@ int32_t lsm6dso_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dso_fs_g_t *val) { lsm6dso_ctrl2_g_t reg; @@ -520,7 +524,7 @@ int32_t lsm6dso_gy_full_scale_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_gy_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso_odr_g_t val) { lsm6dso_odr_g_t odr_gy = val; @@ -648,7 +652,7 @@ int32_t lsm6dso_gy_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso_odr_g_t *val) { lsm6dso_ctrl2_g_t reg; @@ -718,7 +722,7 @@ int32_t lsm6dso_gy_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_ctrl3_c_t reg; int32_t ret; @@ -742,7 +746,7 @@ int32_t lsm6dso_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_ctrl3_c_t reg; int32_t ret; @@ -762,7 +766,7 @@ int32_t lsm6dso_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_offset_weight_set(const stmdev_ctx_t *ctx, lsm6dso_usr_off_w_t val) { lsm6dso_ctrl6_c_t reg; @@ -788,7 +792,7 @@ int32_t lsm6dso_xl_offset_weight_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_offset_weight_get(const stmdev_ctx_t *ctx, lsm6dso_usr_off_w_t *val) { lsm6dso_ctrl6_c_t reg; @@ -823,7 +827,7 @@ int32_t lsm6dso_xl_offset_weight_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_power_mode_set(const stmdev_ctx_t *ctx, lsm6dso_xl_hm_mode_t val) { lsm6dso_ctrl5_c_t ctrl5_c; @@ -854,7 +858,7 @@ int32_t lsm6dso_xl_power_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_power_mode_get(const stmdev_ctx_t *ctx, lsm6dso_xl_hm_mode_t *val) { lsm6dso_ctrl5_c_t ctrl5_c; @@ -898,7 +902,7 @@ int32_t lsm6dso_xl_power_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_gy_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_gy_power_mode_set(const stmdev_ctx_t *ctx, lsm6dso_g_hm_mode_t val) { lsm6dso_ctrl7_g_t reg; @@ -923,7 +927,7 @@ int32_t lsm6dso_gy_power_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_gy_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_gy_power_mode_get(const stmdev_ctx_t *ctx, lsm6dso_g_hm_mode_t *val) { lsm6dso_ctrl7_g_t reg; @@ -957,7 +961,7 @@ int32_t lsm6dso_gy_power_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_status_reg_get(const stmdev_ctx_t *ctx, lsm6dso_status_reg_t *val) { int32_t ret; @@ -975,7 +979,7 @@ int32_t lsm6dso_status_reg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_status_reg_t reg; @@ -995,7 +999,7 @@ int32_t lsm6dso_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_status_reg_t reg; @@ -1015,7 +1019,7 @@ int32_t lsm6dso_gy_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_status_reg_t reg; @@ -1037,7 +1041,7 @@ int32_t lsm6dso_temp_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dso_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1056,7 +1060,7 @@ int32_t lsm6dso_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dso_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1075,7 +1079,7 @@ int32_t lsm6dso_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dso_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1094,7 +1098,7 @@ int32_t lsm6dso_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dso_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1113,7 +1117,7 @@ int32_t lsm6dso_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dso_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1132,7 +1136,7 @@ int32_t lsm6dso_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dso_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1149,7 +1153,7 @@ int32_t lsm6dso_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_ctrl7_g_t reg; int32_t ret; @@ -1173,7 +1177,7 @@ int32_t lsm6dso_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_ctrl7_g_t reg; int32_t ret; @@ -1204,7 +1208,7 @@ int32_t lsm6dso_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_timestamp_rst(stmdev_ctx_t *ctx) +int32_t lsm6dso_timestamp_rst(const stmdev_ctx_t *ctx) { uint8_t rst_val = 0xAA; return lsm6dso_write_reg(ctx, LSM6DSO_TIMESTAMP2, &rst_val, 1); @@ -1218,7 +1222,7 @@ int32_t lsm6dso_timestamp_rst(stmdev_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_ctrl10_c_t reg; int32_t ret; @@ -1242,7 +1246,7 @@ int32_t lsm6dso_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_ctrl10_c_t reg; int32_t ret; @@ -1263,7 +1267,7 @@ int32_t lsm6dso_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t lsm6dso_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; @@ -1298,7 +1302,7 @@ int32_t lsm6dso_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_rounding_mode_set(const stmdev_ctx_t *ctx, lsm6dso_rounding_t val) { lsm6dso_ctrl5_c_t reg; @@ -1323,7 +1327,7 @@ int32_t lsm6dso_rounding_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_rounding_mode_get(const stmdev_ctx_t *ctx, lsm6dso_rounding_t *val) { lsm6dso_ctrl5_c_t reg; @@ -1367,7 +1371,7 @@ int32_t lsm6dso_rounding_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dso_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1388,7 +1392,7 @@ int32_t lsm6dso_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dso_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1413,7 +1417,7 @@ int32_t lsm6dso_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dso_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1437,7 +1441,7 @@ int32_t lsm6dso_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dso_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1454,7 +1458,7 @@ int32_t lsm6dso_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dso_number_of_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1481,7 +1485,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_steps_reset(stmdev_ctx_t *ctx) +int32_t lsm6dso_steps_reset(const stmdev_ctx_t *ctx) { lsm6dso_emb_func_src_t reg; int32_t ret; @@ -1524,7 +1528,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_internal_freq_fine_t reg; int32_t ret; @@ -1552,7 +1556,7 @@ int32_t lsm6dso_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_internal_freq_fine_t reg; int32_t ret; @@ -1574,7 +1578,7 @@ int32_t lsm6dso_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_mem_bank_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dso_reg_access_t val) { lsm6dso_func_cfg_access_t reg = {0}; @@ -1596,7 +1600,7 @@ int32_t lsm6dso_mem_bank_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_mem_bank_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dso_reg_access_t *val) { lsm6dso_func_cfg_access_t reg; @@ -1635,7 +1639,7 @@ int32_t lsm6dso_mem_bank_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address, uint8_t *val) +int32_t lsm6dso_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val) { return lsm6dso_ln_pg_write(ctx, address, val, 1); } @@ -1650,7 +1654,7 @@ int32_t lsm6dso_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address, uint8_t *v * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dso_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len) { lsm6dso_page_rw_t page_rw; @@ -1732,12 +1736,12 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t address, uint8_t *val) +int32_t lsm6dso_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val) { return lsm6dso_ln_pg_read(ctx, address, val, 1); } -int32_t lsm6dso_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, +int32_t lsm6dso_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len) { lsm6dso_page_rw_t page_rw; @@ -1820,7 +1824,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm6dso_dataready_pulsed_t val) { lsm6dso_counter_bdr_reg1_t reg; @@ -1848,7 +1852,7 @@ int32_t lsm6dso_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm6dso_dataready_pulsed_t *val) { lsm6dso_counter_bdr_reg1_t reg; @@ -1882,7 +1886,7 @@ int32_t lsm6dso_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dso_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1900,7 +1904,7 @@ int32_t lsm6dso_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_ctrl3_c_t reg; int32_t ret; @@ -1924,7 +1928,7 @@ int32_t lsm6dso_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_ctrl3_c_t reg; int32_t ret; @@ -1944,7 +1948,7 @@ int32_t lsm6dso_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_ctrl3_c_t reg; int32_t ret; @@ -1969,7 +1973,7 @@ int32_t lsm6dso_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_ctrl3_c_t reg; int32_t ret; @@ -1988,7 +1992,7 @@ int32_t lsm6dso_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_ctrl3_c_t reg; int32_t ret; @@ -2012,7 +2016,7 @@ int32_t lsm6dso_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_ctrl3_c_t reg; int32_t ret; @@ -2031,7 +2035,7 @@ int32_t lsm6dso_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dso_st_xl_t val) { lsm6dso_ctrl5_c_t reg; @@ -2056,7 +2060,7 @@ int32_t lsm6dso_xl_self_test_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dso_st_xl_t *val) { lsm6dso_ctrl5_c_t reg; @@ -2094,7 +2098,7 @@ int32_t lsm6dso_xl_self_test_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dso_st_g_t val) { lsm6dso_ctrl5_c_t reg; @@ -2119,7 +2123,7 @@ int32_t lsm6dso_gy_self_test_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dso_st_g_t *val) { lsm6dso_ctrl5_c_t reg; @@ -2170,7 +2174,7 @@ int32_t lsm6dso_gy_self_test_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_ctrl1_xl_t reg; int32_t ret; @@ -2194,7 +2198,7 @@ int32_t lsm6dso_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_ctrl1_xl_t reg; int32_t ret; @@ -2215,7 +2219,7 @@ int32_t lsm6dso_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_ctrl4_c_t reg; int32_t ret; @@ -2241,7 +2245,7 @@ int32_t lsm6dso_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_ctrl4_c_t reg; int32_t ret; @@ -2261,7 +2265,7 @@ int32_t lsm6dso_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_ctrl4_c_t reg; @@ -2287,7 +2291,7 @@ int32_t lsm6dso_filter_settling_mask_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_ctrl4_c_t reg; @@ -2307,7 +2311,7 @@ int32_t lsm6dso_filter_settling_mask_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dso_ftype_t val) { lsm6dso_ctrl6_c_t reg; @@ -2332,7 +2336,7 @@ int32_t lsm6dso_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dso_ftype_t *val) { lsm6dso_ctrl6_c_t reg; @@ -2390,7 +2394,7 @@ int32_t lsm6dso_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_ctrl8_xl_t reg; int32_t ret; @@ -2414,7 +2418,7 @@ int32_t lsm6dso_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_ctrl8_xl_t reg; int32_t ret; @@ -2435,7 +2439,7 @@ int32_t lsm6dso_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, lsm6dso_hp_slope_xl_en_t val) { lsm6dso_ctrl8_xl_t reg; @@ -2464,7 +2468,7 @@ int32_t lsm6dso_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, lsm6dso_hp_slope_xl_en_t *val) { lsm6dso_ctrl8_xl_t reg; @@ -2586,7 +2590,7 @@ int32_t lsm6dso_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_ctrl8_xl_t reg; int32_t ret; @@ -2612,7 +2616,7 @@ int32_t lsm6dso_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_ctrl8_xl_t reg; int32_t ret; @@ -2632,7 +2636,7 @@ int32_t lsm6dso_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dso_slope_fds_t val) { lsm6dso_tap_cfg0_t reg; @@ -2658,7 +2662,7 @@ int32_t lsm6dso_xl_hp_path_internal_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dso_slope_fds_t *val) { lsm6dso_tap_cfg0_t reg; @@ -2694,7 +2698,7 @@ int32_t lsm6dso_xl_hp_path_internal_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_gy_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dso_hpm_g_t val) { lsm6dso_ctrl7_g_t reg; @@ -2722,7 +2726,7 @@ int32_t lsm6dso_gy_hp_path_internal_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_gy_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dso_hpm_g_t *val) { lsm6dso_ctrl7_g_t reg; @@ -2783,7 +2787,7 @@ int32_t lsm6dso_gy_hp_path_internal_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_sdo_ocs_mode_set(const stmdev_ctx_t *ctx, lsm6dso_ois_pu_dis_t val) { lsm6dso_pin_ctrl_t reg; @@ -2809,7 +2813,7 @@ int32_t lsm6dso_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_sdo_ocs_mode_get(const stmdev_ctx_t *ctx, lsm6dso_ois_pu_dis_t *val) { lsm6dso_pin_ctrl_t reg; @@ -2843,7 +2847,7 @@ int32_t lsm6dso_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_pw_on_ctrl_set(const stmdev_ctx_t *ctx, lsm6dso_ois_on_t val) { lsm6dso_ctrl7_g_t reg; @@ -2869,7 +2873,7 @@ int32_t lsm6dso_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_pw_on_ctrl_get(const stmdev_ctx_t *ctx, lsm6dso_ois_on_t *val) { lsm6dso_ctrl7_g_t reg; @@ -2909,7 +2913,7 @@ int32_t lsm6dso_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_xl_fs_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_xl_fs_mode_set(const stmdev_ctx_t *ctx, lsm6dso_xl_fs_mode_t val) { lsm6dso_ctrl8_xl_t reg; @@ -2939,7 +2943,7 @@ int32_t lsm6dso_aux_xl_fs_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_xl_fs_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_xl_fs_mode_get(const stmdev_ctx_t *ctx, lsm6dso_xl_fs_mode_t *val) { lsm6dso_ctrl8_xl_t reg; @@ -2973,7 +2977,7 @@ int32_t lsm6dso_aux_xl_fs_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_status_reg_get(const stmdev_ctx_t *ctx, lsm6dso_status_spiaux_t *val) { int32_t ret; @@ -2991,7 +2995,7 @@ int32_t lsm6dso_aux_status_reg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_status_spiaux_t reg; @@ -3011,7 +3015,7 @@ int32_t lsm6dso_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_status_spiaux_t reg; @@ -3031,7 +3035,7 @@ int32_t lsm6dso_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_status_spiaux_t reg; @@ -3052,7 +3056,7 @@ int32_t lsm6dso_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dso_st_xl_ois_t val) { lsm6dso_int_ois_t reg; @@ -3078,7 +3082,7 @@ int32_t lsm6dso_aux_xl_self_test_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dso_st_xl_ois_t *val) { lsm6dso_int_ois_t reg; @@ -3117,7 +3121,7 @@ int32_t lsm6dso_aux_xl_self_test_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dso_den_lh_ois_t val) { lsm6dso_int_ois_t reg; @@ -3142,7 +3146,7 @@ int32_t lsm6dso_aux_den_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dso_den_lh_ois_t *val) { lsm6dso_int_ois_t reg; @@ -3176,7 +3180,7 @@ int32_t lsm6dso_aux_den_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_den_mode_set(const stmdev_ctx_t *ctx, lsm6dso_lvl2_ois_t val) { lsm6dso_ctrl1_ois_t ctrl1_ois; @@ -3204,7 +3208,7 @@ int32_t lsm6dso_aux_den_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_den_mode_get(const stmdev_ctx_t *ctx, lsm6dso_lvl2_ois_t *val) { lsm6dso_ctrl1_ois_t ctrl1_ois; @@ -3248,7 +3252,7 @@ int32_t lsm6dso_aux_den_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_aux_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_int_ois_t reg; int32_t ret; @@ -3273,7 +3277,7 @@ int32_t lsm6dso_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_int_ois_t reg; int32_t ret; @@ -3298,7 +3302,7 @@ int32_t lsm6dso_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_mode_set(const stmdev_ctx_t *ctx, lsm6dso_ois_en_spi2_t val) { lsm6dso_ctrl1_ois_t reg; @@ -3330,7 +3334,7 @@ int32_t lsm6dso_aux_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_mode_get(const stmdev_ctx_t *ctx, lsm6dso_ois_en_spi2_t *val) { lsm6dso_ctrl1_ois_t reg; @@ -3368,7 +3372,7 @@ int32_t lsm6dso_aux_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dso_fs_g_ois_t val) { lsm6dso_ctrl1_ois_t reg; @@ -3393,7 +3397,7 @@ int32_t lsm6dso_aux_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dso_fs_g_ois_t *val) { lsm6dso_ctrl1_ois_t reg; @@ -3439,7 +3443,7 @@ int32_t lsm6dso_aux_gy_full_scale_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_spi_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dso_sim_ois_t val) { lsm6dso_ctrl1_ois_t reg; @@ -3464,7 +3468,7 @@ int32_t lsm6dso_aux_spi_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_spi_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dso_sim_ois_t *val) { lsm6dso_ctrl1_ois_t reg; @@ -3499,7 +3503,7 @@ int32_t lsm6dso_aux_spi_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dso_ftype_ois_t val) { lsm6dso_ctrl2_ois_t reg; @@ -3524,7 +3528,7 @@ int32_t lsm6dso_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dso_ftype_ois_t *val) { lsm6dso_ctrl2_ois_t reg; @@ -3566,7 +3570,7 @@ int32_t lsm6dso_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_gy_hp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dso_hpm_ois_t val) { lsm6dso_ctrl2_ois_t reg; @@ -3592,7 +3596,7 @@ int32_t lsm6dso_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_gy_hp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dso_hpm_ois_t *val) { lsm6dso_ctrl2_ois_t reg; @@ -3643,7 +3647,7 @@ int32_t lsm6dso_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_gy_clamp_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_gy_clamp_set(const stmdev_ctx_t *ctx, lsm6dso_st_ois_clampdis_t val) { lsm6dso_ctrl3_ois_t reg; @@ -3673,7 +3677,7 @@ int32_t lsm6dso_aux_gy_clamp_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_gy_clamp_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_gy_clamp_get(const stmdev_ctx_t *ctx, lsm6dso_st_ois_clampdis_t *val) { lsm6dso_ctrl3_ois_t reg; @@ -3707,7 +3711,7 @@ int32_t lsm6dso_aux_gy_clamp_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dso_st_ois_t val) { lsm6dso_ctrl3_ois_t reg; @@ -3732,7 +3736,7 @@ int32_t lsm6dso_aux_gy_self_test_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dso_st_ois_t *val) { lsm6dso_ctrl3_ois_t reg; @@ -3771,7 +3775,7 @@ int32_t lsm6dso_aux_gy_self_test_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_xl_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_xl_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dso_filter_xl_conf_ois_t val) { lsm6dso_ctrl3_ois_t reg; @@ -3797,7 +3801,7 @@ int32_t lsm6dso_aux_xl_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_xl_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_xl_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dso_filter_xl_conf_ois_t *val) { lsm6dso_ctrl3_ois_t reg; @@ -3856,7 +3860,7 @@ int32_t lsm6dso_aux_xl_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dso_fs_xl_ois_t val) { lsm6dso_ctrl3_ois_t reg; @@ -3881,7 +3885,7 @@ int32_t lsm6dso_aux_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_aux_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dso_fs_xl_ois_t *val) { lsm6dso_ctrl3_ois_t reg; @@ -3937,7 +3941,7 @@ int32_t lsm6dso_aux_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, lsm6dso_sdo_pu_en_t val) { lsm6dso_pin_ctrl_t reg; @@ -3962,7 +3966,7 @@ int32_t lsm6dso_sdo_sa0_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, lsm6dso_sdo_pu_en_t *val) { lsm6dso_pin_ctrl_t reg; @@ -3996,7 +4000,7 @@ int32_t lsm6dso_sdo_sa0_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso_sim_t val) +int32_t lsm6dso_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dso_sim_t val) { lsm6dso_ctrl3_c_t reg; int32_t ret; @@ -4020,7 +4024,7 @@ int32_t lsm6dso_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso_sim_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_spi_mode_get(stmdev_ctx_t *ctx, lsm6dso_sim_t *val) +int32_t lsm6dso_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dso_sim_t *val) { lsm6dso_ctrl3_c_t reg; int32_t ret; @@ -4054,7 +4058,7 @@ int32_t lsm6dso_spi_mode_get(stmdev_ctx_t *ctx, lsm6dso_sim_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_i2c_interface_set(const stmdev_ctx_t *ctx, lsm6dso_i2c_disable_t val) { lsm6dso_ctrl4_c_t reg; @@ -4080,7 +4084,7 @@ int32_t lsm6dso_i2c_interface_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_i2c_interface_get(const stmdev_ctx_t *ctx, lsm6dso_i2c_disable_t *val) { lsm6dso_ctrl4_c_t reg; @@ -4115,7 +4119,7 @@ int32_t lsm6dso_i2c_interface_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_i3c_disable_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_i3c_disable_set(const stmdev_ctx_t *ctx, lsm6dso_i3c_disable_t val) { lsm6dso_i3c_bus_avb_t i3c_bus_avb; @@ -4143,7 +4147,7 @@ int32_t lsm6dso_i3c_disable_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_i3c_disable_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_i3c_disable_get(const stmdev_ctx_t *ctx, lsm6dso_i3c_disable_t *val) { lsm6dso_ctrl9_xl_t ctrl9_xl; @@ -4204,7 +4208,7 @@ int32_t lsm6dso_i3c_disable_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_int1_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_int1_mode_set(const stmdev_ctx_t *ctx, lsm6dso_int1_pd_en_t val) { lsm6dso_i3c_bus_avb_t reg; @@ -4229,7 +4233,7 @@ int32_t lsm6dso_int1_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_int1_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_int1_mode_get(const stmdev_ctx_t *ctx, lsm6dso_int1_pd_en_t *val) { lsm6dso_i3c_bus_avb_t reg; @@ -4263,7 +4267,7 @@ int32_t lsm6dso_int1_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_pin_mode_set(stmdev_ctx_t *ctx, lsm6dso_pp_od_t val) +int32_t lsm6dso_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dso_pp_od_t val) { lsm6dso_ctrl3_c_t reg; int32_t ret; @@ -4287,7 +4291,7 @@ int32_t lsm6dso_pin_mode_set(stmdev_ctx_t *ctx, lsm6dso_pp_od_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_pin_mode_get(stmdev_ctx_t *ctx, lsm6dso_pp_od_t *val) +int32_t lsm6dso_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dso_pp_od_t *val) { lsm6dso_ctrl3_c_t reg; int32_t ret; @@ -4320,7 +4324,7 @@ int32_t lsm6dso_pin_mode_get(stmdev_ctx_t *ctx, lsm6dso_pp_od_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_pin_polarity_set(const stmdev_ctx_t *ctx, lsm6dso_h_lactive_t val) { lsm6dso_ctrl3_c_t reg; @@ -4345,7 +4349,7 @@ int32_t lsm6dso_pin_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_pin_polarity_get(const stmdev_ctx_t *ctx, lsm6dso_h_lactive_t *val) { lsm6dso_ctrl3_c_t reg; @@ -4379,7 +4383,7 @@ int32_t lsm6dso_pin_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_ctrl4_c_t reg; int32_t ret; @@ -4403,7 +4407,7 @@ int32_t lsm6dso_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_ctrl4_c_t reg; int32_t ret; @@ -4422,7 +4426,7 @@ int32_t lsm6dso_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_int_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_int_notification_set(const stmdev_ctx_t *ctx, lsm6dso_lir_t val) { lsm6dso_tap_cfg0_t tap_cfg0; @@ -4455,7 +4459,7 @@ int32_t lsm6dso_int_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_int_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_int_notification_get(const stmdev_ctx_t *ctx, lsm6dso_lir_t *val) { lsm6dso_tap_cfg0_t tap_cfg0; @@ -4524,7 +4528,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_wkup_ths_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_wkup_ths_weight_set(const stmdev_ctx_t *ctx, lsm6dso_wake_ths_w_t val) { lsm6dso_wake_up_dur_t reg; @@ -4552,7 +4556,7 @@ int32_t lsm6dso_wkup_ths_weight_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_wkup_ths_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_wkup_ths_weight_get(const stmdev_ctx_t *ctx, lsm6dso_wake_ths_w_t *val) { lsm6dso_wake_up_dur_t reg; @@ -4587,7 +4591,7 @@ int32_t lsm6dso_wkup_ths_weight_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_wake_up_ths_t reg; int32_t ret; @@ -4612,7 +4616,7 @@ int32_t lsm6dso_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_wake_up_ths_t reg; int32_t ret; @@ -4632,7 +4636,7 @@ int32_t lsm6dso_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_wake_up_ths_t reg; @@ -4658,7 +4662,7 @@ int32_t lsm6dso_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_wake_up_ths_t reg; @@ -4679,7 +4683,7 @@ int32_t lsm6dso_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_wake_up_dur_t reg; int32_t ret; @@ -4704,7 +4708,7 @@ int32_t lsm6dso_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_wake_up_dur_t reg; int32_t ret; @@ -4736,7 +4740,7 @@ int32_t lsm6dso_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_ctrl4_c_t reg; int32_t ret; @@ -4760,7 +4764,7 @@ int32_t lsm6dso_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_ctrl4_c_t reg; int32_t ret; @@ -4782,7 +4786,7 @@ int32_t lsm6dso_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_act_pin_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_act_pin_notification_set(const stmdev_ctx_t *ctx, lsm6dso_sleep_status_on_int_t val) { lsm6dso_tap_cfg0_t reg; @@ -4810,7 +4814,7 @@ int32_t lsm6dso_act_pin_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_act_pin_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_act_pin_notification_get(const stmdev_ctx_t *ctx, lsm6dso_sleep_status_on_int_t *val) { lsm6dso_tap_cfg0_t reg; @@ -4844,7 +4848,7 @@ int32_t lsm6dso_act_pin_notification_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_act_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_act_mode_set(const stmdev_ctx_t *ctx, lsm6dso_inact_en_t val) { lsm6dso_tap_cfg2_t reg; @@ -4869,7 +4873,7 @@ int32_t lsm6dso_act_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_act_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_act_mode_get(const stmdev_ctx_t *ctx, lsm6dso_inact_en_t *val) { lsm6dso_tap_cfg2_t reg; @@ -4912,7 +4916,7 @@ int32_t lsm6dso_act_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_wake_up_dur_t reg; int32_t ret; @@ -4937,7 +4941,7 @@ int32_t lsm6dso_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_wake_up_dur_t reg; int32_t ret; @@ -4969,7 +4973,7 @@ int32_t lsm6dso_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_tap_cfg0_t reg; int32_t ret; @@ -4993,7 +4997,7 @@ int32_t lsm6dso_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_tap_cfg0_t reg; @@ -5013,7 +5017,7 @@ int32_t lsm6dso_tap_detection_on_z_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_tap_cfg0_t reg; int32_t ret; @@ -5037,7 +5041,7 @@ int32_t lsm6dso_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_tap_cfg0_t reg; @@ -5057,7 +5061,7 @@ int32_t lsm6dso_tap_detection_on_y_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_tap_cfg0_t reg; int32_t ret; @@ -5081,7 +5085,7 @@ int32_t lsm6dso_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_tap_cfg0_t reg; @@ -5101,7 +5105,7 @@ int32_t lsm6dso_tap_detection_on_x_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_tap_cfg1_t reg; int32_t ret; @@ -5125,7 +5129,7 @@ int32_t lsm6dso_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_tap_cfg1_t reg; int32_t ret; @@ -5145,7 +5149,7 @@ int32_t lsm6dso_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_tap_axis_priority_set(const stmdev_ctx_t *ctx, lsm6dso_tap_priority_t val) { lsm6dso_tap_cfg1_t reg; @@ -5171,7 +5175,7 @@ int32_t lsm6dso_tap_axis_priority_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_tap_axis_priority_get(const stmdev_ctx_t *ctx, lsm6dso_tap_priority_t *val) { lsm6dso_tap_cfg1_t reg; @@ -5221,7 +5225,7 @@ int32_t lsm6dso_tap_axis_priority_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_tap_cfg2_t reg; int32_t ret; @@ -5245,7 +5249,7 @@ int32_t lsm6dso_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_tap_cfg2_t reg; int32_t ret; @@ -5264,7 +5268,7 @@ int32_t lsm6dso_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_tap_ths_6d_t reg; int32_t ret; @@ -5288,7 +5292,7 @@ int32_t lsm6dso_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_tap_ths_6d_t reg; int32_t ret; @@ -5312,7 +5316,7 @@ int32_t lsm6dso_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_int_dur2_t reg; int32_t ret; @@ -5341,7 +5345,7 @@ int32_t lsm6dso_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_int_dur2_t reg; int32_t ret; @@ -5366,7 +5370,7 @@ int32_t lsm6dso_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_int_dur2_t reg; int32_t ret; @@ -5396,7 +5400,7 @@ int32_t lsm6dso_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_int_dur2_t reg; int32_t ret; @@ -5422,7 +5426,7 @@ int32_t lsm6dso_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_int_dur2_t reg; int32_t ret; @@ -5453,7 +5457,7 @@ int32_t lsm6dso_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_int_dur2_t reg; int32_t ret; @@ -5472,7 +5476,7 @@ int32_t lsm6dso_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_tap_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dso_single_double_tap_t val) { lsm6dso_wake_up_ths_t reg; @@ -5497,7 +5501,7 @@ int32_t lsm6dso_tap_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_tap_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dso_single_double_tap_t *val) { lsm6dso_wake_up_ths_t reg; @@ -5544,7 +5548,7 @@ int32_t lsm6dso_tap_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_6d_threshold_set(const stmdev_ctx_t *ctx, lsm6dso_sixd_ths_t val) { lsm6dso_tap_ths_6d_t reg; @@ -5569,7 +5573,7 @@ int32_t lsm6dso_6d_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_6d_threshold_get(const stmdev_ctx_t *ctx, lsm6dso_sixd_ths_t *val) { lsm6dso_tap_ths_6d_t reg; @@ -5611,7 +5615,7 @@ int32_t lsm6dso_6d_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_tap_ths_6d_t reg; int32_t ret; @@ -5635,7 +5639,7 @@ int32_t lsm6dso_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_tap_ths_6d_t reg; int32_t ret; @@ -5666,7 +5670,7 @@ int32_t lsm6dso_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_ff_threshold_set(const stmdev_ctx_t *ctx, lsm6dso_ff_ths_t val) { lsm6dso_free_fall_t reg; @@ -5691,7 +5695,7 @@ int32_t lsm6dso_ff_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_ff_threshold_get(const stmdev_ctx_t *ctx, lsm6dso_ff_ths_t *val) { lsm6dso_free_fall_t reg; @@ -5750,7 +5754,7 @@ int32_t lsm6dso_ff_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_wake_up_dur_t wake_up_dur; lsm6dso_free_fall_t free_fall; @@ -5778,7 +5782,7 @@ int32_t lsm6dso_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_wake_up_dur_t wake_up_dur; lsm6dso_free_fall_t free_fall; @@ -5816,7 +5820,7 @@ int32_t lsm6dso_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dso_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val) { lsm6dso_fifo_ctrl1_t fifo_ctrl1; lsm6dso_fifo_ctrl2_t fifo_ctrl2; @@ -5842,7 +5846,7 @@ int32_t lsm6dso_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dso_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dso_fifo_ctrl1_t fifo_ctrl1; lsm6dso_fifo_ctrl2_t fifo_ctrl2; @@ -5868,7 +5872,7 @@ int32_t lsm6dso_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_compression_algo_init_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_compression_algo_init_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_emb_func_init_b_t reg; @@ -5895,7 +5899,7 @@ int32_t lsm6dso_compression_algo_init_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_compression_algo_init_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_compression_algo_init_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_emb_func_init_b_t reg; @@ -5919,7 +5923,7 @@ int32_t lsm6dso_compression_algo_init_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_compression_algo_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_compression_algo_set(const stmdev_ctx_t *ctx, lsm6dso_uncoptr_rate_t val) { lsm6dso_fifo_ctrl2_t fifo_ctrl2; @@ -5948,7 +5952,7 @@ int32_t lsm6dso_compression_algo_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_compression_algo_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_compression_algo_get(const stmdev_ctx_t *ctx, lsm6dso_uncoptr_rate_t *val) { lsm6dso_fifo_ctrl2_t reg; @@ -5994,7 +5998,7 @@ int32_t lsm6dso_compression_algo_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_fifo_ctrl2_t reg; @@ -6019,7 +6023,7 @@ int32_t lsm6dso_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_fifo_ctrl2_t reg; @@ -6040,7 +6044,7 @@ int32_t lsm6dso_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_compression_algo_real_time_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_compression_algo_real_time_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_fifo_ctrl2_t reg; @@ -6065,7 +6069,7 @@ int32_t lsm6dso_compression_algo_real_time_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_compression_algo_real_time_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_compression_algo_real_time_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_fifo_ctrl2_t reg; @@ -6086,7 +6090,7 @@ int32_t lsm6dso_compression_algo_real_time_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_fifo_ctrl2_t reg; int32_t ret; @@ -6111,7 +6115,7 @@ int32_t lsm6dso_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_fifo_ctrl2_t reg; int32_t ret; @@ -6131,7 +6135,7 @@ int32_t lsm6dso_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_xl_batch_set(const stmdev_ctx_t *ctx, lsm6dso_bdr_xl_t val) { lsm6dso_fifo_ctrl3_t reg; @@ -6157,7 +6161,7 @@ int32_t lsm6dso_fifo_xl_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_xl_batch_get(const stmdev_ctx_t *ctx, lsm6dso_bdr_xl_t *val) { lsm6dso_fifo_ctrl3_t reg; @@ -6232,7 +6236,7 @@ int32_t lsm6dso_fifo_xl_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_gy_batch_set(const stmdev_ctx_t *ctx, lsm6dso_bdr_gy_t val) { lsm6dso_fifo_ctrl3_t reg; @@ -6258,7 +6262,7 @@ int32_t lsm6dso_fifo_gy_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_gy_batch_get(const stmdev_ctx_t *ctx, lsm6dso_bdr_gy_t *val) { lsm6dso_fifo_ctrl3_t reg; @@ -6332,7 +6336,7 @@ int32_t lsm6dso_fifo_gy_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dso_fifo_mode_t val) { lsm6dso_fifo_ctrl4_t reg; @@ -6357,7 +6361,7 @@ int32_t lsm6dso_fifo_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6dso_fifo_mode_t *val) { lsm6dso_fifo_ctrl4_t reg; @@ -6408,7 +6412,7 @@ int32_t lsm6dso_fifo_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_temp_batch_set(const stmdev_ctx_t *ctx, lsm6dso_odr_t_batch_t val) { lsm6dso_fifo_ctrl4_t reg; @@ -6434,7 +6438,7 @@ int32_t lsm6dso_fifo_temp_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_temp_batch_get(const stmdev_ctx_t *ctx, lsm6dso_odr_t_batch_t *val) { lsm6dso_fifo_ctrl4_t reg; @@ -6478,7 +6482,7 @@ int32_t lsm6dso_fifo_temp_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, lsm6dso_odr_ts_batch_t val) { lsm6dso_fifo_ctrl4_t reg; @@ -6505,7 +6509,7 @@ int32_t lsm6dso_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, lsm6dso_odr_ts_batch_t *val) { lsm6dso_fifo_ctrl4_t reg; @@ -6549,7 +6553,7 @@ int32_t lsm6dso_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, lsm6dso_trig_counter_bdr_t val) { lsm6dso_counter_bdr_reg1_t reg; @@ -6577,7 +6581,7 @@ int32_t lsm6dso_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, lsm6dso_trig_counter_bdr_t *val) { lsm6dso_counter_bdr_reg1_t reg; @@ -6613,7 +6617,7 @@ int32_t lsm6dso_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_counter_bdr_reg1_t reg; int32_t ret; @@ -6640,7 +6644,7 @@ int32_t lsm6dso_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_counter_bdr_reg1_t reg; int32_t ret; @@ -6660,7 +6664,7 @@ int32_t lsm6dso_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_batch_counter_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { lsm6dso_counter_bdr_reg1_t counter_bdr_reg1; @@ -6688,7 +6692,7 @@ int32_t lsm6dso_batch_counter_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dso_counter_bdr_reg1_t counter_bdr_reg1; @@ -6717,7 +6721,7 @@ int32_t lsm6dso_batch_counter_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dso_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dso_fifo_status1_t fifo_status1; lsm6dso_fifo_status2_t fifo_status2; @@ -6745,7 +6749,7 @@ int32_t lsm6dso_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_status_get(const stmdev_ctx_t *ctx, lsm6dso_fifo_status2_t *val) { int32_t ret; @@ -6763,7 +6767,7 @@ int32_t lsm6dso_fifo_status_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_fifo_status2_t reg; int32_t ret; @@ -6783,7 +6787,7 @@ int32_t lsm6dso_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_fifo_status2_t reg; int32_t ret; @@ -6802,7 +6806,7 @@ int32_t lsm6dso_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_fifo_status2_t reg; int32_t ret; @@ -6821,7 +6825,7 @@ int32_t lsm6dso_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fifo_sensor_tag_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, lsm6dso_fifo_tag_t *val) { lsm6dso_fifo_data_out_tag_t reg; @@ -6938,7 +6942,7 @@ int32_t lsm6dso_fifo_sensor_tag_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_emb_func_fifo_cfg_t reg; int32_t ret; @@ -6964,7 +6968,7 @@ int32_t lsm6dso_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_emb_func_fifo_cfg_t reg; int32_t ret; @@ -6988,7 +6992,7 @@ int32_t lsm6dso_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_sh_batch_slave_set(stmdev_ctx_t *ctx, uint8_t idx, uint8_t val) +int32_t lsm6dso_sh_batch_slave_set(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t val) { lsm6dso_slv0_config_t reg; int32_t ret; @@ -7013,7 +7017,7 @@ int32_t lsm6dso_sh_batch_slave_set(stmdev_ctx_t *ctx, uint8_t idx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_sh_batch_slave_get(stmdev_ctx_t *ctx, uint8_t idx, uint8_t *val) +int32_t lsm6dso_sh_batch_slave_get(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t *val) { lsm6dso_slv0_config_t reg; int32_t ret; @@ -7050,7 +7054,7 @@ int32_t lsm6dso_sh_batch_slave_get(stmdev_ctx_t *ctx, uint8_t idx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_den_mode_set(const stmdev_ctx_t *ctx, lsm6dso_den_mode_t val) { lsm6dso_ctrl6_c_t reg; @@ -7075,7 +7079,7 @@ int32_t lsm6dso_den_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_den_mode_get(const stmdev_ctx_t *ctx, lsm6dso_den_mode_t *val) { lsm6dso_ctrl6_c_t reg; @@ -7121,7 +7125,7 @@ int32_t lsm6dso_den_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dso_den_lh_t val) { lsm6dso_ctrl9_xl_t reg; @@ -7146,7 +7150,7 @@ int32_t lsm6dso_den_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dso_den_lh_t *val) { lsm6dso_ctrl9_xl_t reg; @@ -7180,7 +7184,7 @@ int32_t lsm6dso_den_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_den_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_den_enable_set(const stmdev_ctx_t *ctx, lsm6dso_den_xl_g_t val) { lsm6dso_ctrl9_xl_t reg; @@ -7205,7 +7209,7 @@ int32_t lsm6dso_den_enable_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_den_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_den_enable_get(const stmdev_ctx_t *ctx, lsm6dso_den_xl_g_t *val) { lsm6dso_ctrl9_xl_t reg; @@ -7243,7 +7247,7 @@ int32_t lsm6dso_den_enable_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_ctrl9_xl_t reg; int32_t ret; @@ -7267,7 +7271,7 @@ int32_t lsm6dso_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_ctrl9_xl_t reg; int32_t ret; @@ -7286,7 +7290,7 @@ int32_t lsm6dso_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_ctrl9_xl_t reg; int32_t ret; @@ -7310,7 +7314,7 @@ int32_t lsm6dso_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_ctrl9_xl_t reg; int32_t ret; @@ -7329,7 +7333,7 @@ int32_t lsm6dso_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_ctrl9_xl_t reg; int32_t ret; @@ -7353,7 +7357,7 @@ int32_t lsm6dso_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_ctrl9_xl_t reg; int32_t ret; @@ -7384,7 +7388,7 @@ int32_t lsm6dso_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_pedo_sens_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_pedo_sens_set(const stmdev_ctx_t *ctx, lsm6dso_pedo_md_t val) { lsm6dso_pedo_cmd_reg_t pedo_cmd_reg; @@ -7412,7 +7416,7 @@ int32_t lsm6dso_pedo_sens_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_pedo_sens_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_pedo_sens_get(const stmdev_ctx_t *ctx, lsm6dso_pedo_md_t *val) { lsm6dso_pedo_cmd_reg_t pedo_cmd_reg; @@ -7452,7 +7456,7 @@ int32_t lsm6dso_pedo_sens_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_pedo_step_detect_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_emb_func_status_t reg; int32_t ret; @@ -7476,7 +7480,7 @@ int32_t lsm6dso_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_pedo_debounce_steps_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -7495,7 +7499,7 @@ int32_t lsm6dso_pedo_debounce_steps_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_pedo_debounce_steps_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -7513,7 +7517,7 @@ int32_t lsm6dso_pedo_debounce_steps_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_pedo_steps_period_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dso_pedo_steps_period_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -7534,7 +7538,7 @@ int32_t lsm6dso_pedo_steps_period_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_pedo_steps_period_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_pedo_steps_period_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -7558,7 +7562,7 @@ int32_t lsm6dso_pedo_steps_period_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_pedo_int_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_pedo_int_mode_set(const stmdev_ctx_t *ctx, lsm6dso_carry_count_en_t val) { lsm6dso_pedo_cmd_reg_t reg; @@ -7586,7 +7590,7 @@ int32_t lsm6dso_pedo_int_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_pedo_int_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_pedo_int_mode_get(const stmdev_ctx_t *ctx, lsm6dso_carry_count_en_t *val) { lsm6dso_pedo_cmd_reg_t reg; @@ -7634,7 +7638,7 @@ int32_t lsm6dso_pedo_int_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_motion_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_motion_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_emb_func_status_t reg; @@ -7672,7 +7676,7 @@ int32_t lsm6dso_motion_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_emb_func_status_t reg; @@ -7710,7 +7714,7 @@ int32_t lsm6dso_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dso_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -7732,7 +7736,7 @@ int32_t lsm6dso_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dso_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -7754,7 +7758,7 @@ int32_t lsm6dso_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dso_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -7776,7 +7780,7 @@ int32_t lsm6dso_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dso_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -7807,7 +7811,7 @@ int32_t lsm6dso_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_mag_soft_iron_set(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dso_mag_soft_iron_set(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[12]; @@ -7842,7 +7846,7 @@ int32_t lsm6dso_mag_soft_iron_set(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_mag_soft_iron_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dso_mag_soft_iron_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[12]; int32_t ret; @@ -7876,7 +7880,7 @@ int32_t lsm6dso_mag_soft_iron_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_mag_z_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_mag_z_orient_set(const stmdev_ctx_t *ctx, lsm6dso_mag_z_axis_t val) { lsm6dso_mag_cfg_a_t reg; @@ -7904,7 +7908,7 @@ int32_t lsm6dso_mag_z_orient_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_mag_z_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_mag_z_orient_get(const stmdev_ctx_t *ctx, lsm6dso_mag_z_axis_t *val) { lsm6dso_mag_cfg_a_t reg; @@ -7958,7 +7962,7 @@ int32_t lsm6dso_mag_z_orient_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_mag_y_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_mag_y_orient_set(const stmdev_ctx_t *ctx, lsm6dso_mag_y_axis_t val) { lsm6dso_mag_cfg_a_t reg; @@ -7986,7 +7990,7 @@ int32_t lsm6dso_mag_y_orient_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_mag_y_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_mag_y_orient_get(const stmdev_ctx_t *ctx, lsm6dso_mag_y_axis_t *val) { lsm6dso_mag_cfg_a_t reg; @@ -8040,7 +8044,7 @@ int32_t lsm6dso_mag_y_orient_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_mag_x_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_mag_x_orient_set(const stmdev_ctx_t *ctx, lsm6dso_mag_x_axis_t val) { lsm6dso_mag_cfg_b_t reg; @@ -8068,7 +8072,7 @@ int32_t lsm6dso_mag_x_orient_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_mag_x_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_mag_x_orient_get(const stmdev_ctx_t *ctx, lsm6dso_mag_x_axis_t *val) { lsm6dso_mag_cfg_b_t reg; @@ -8133,7 +8137,7 @@ int32_t lsm6dso_mag_x_orient_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_emb_func_status_t reg; @@ -8158,7 +8162,7 @@ int32_t lsm6dso_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fsm_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_fsm_enable_set(const stmdev_ctx_t *ctx, lsm6dso_emb_fsm_enable_t *val) { int32_t ret; @@ -8182,7 +8186,7 @@ int32_t lsm6dso_fsm_enable_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fsm_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_fsm_enable_get(const stmdev_ctx_t *ctx, lsm6dso_emb_fsm_enable_t *val) { int32_t ret; @@ -8203,7 +8207,7 @@ int32_t lsm6dso_fsm_enable_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dso_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -8227,7 +8231,7 @@ int32_t lsm6dso_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dso_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -8251,7 +8255,7 @@ int32_t lsm6dso_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_long_clr_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_long_clr_set(const stmdev_ctx_t *ctx, lsm6dso_fsm_lc_clr_t val) { lsm6dso_fsm_long_counter_clear_t reg; @@ -8278,7 +8282,7 @@ int32_t lsm6dso_long_clr_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_long_clr_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_long_clr_get(const stmdev_ctx_t *ctx, lsm6dso_fsm_lc_clr_t *val) { lsm6dso_fsm_long_counter_clear_t reg; @@ -8323,7 +8327,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fsm_out_get(stmdev_ctx_t *ctx, lsm6dso_fsm_out_t *val) +int32_t lsm6dso_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dso_fsm_out_t *val) { int32_t ret; @@ -8342,7 +8346,7 @@ int32_t lsm6dso_fsm_out_get(stmdev_ctx_t *ctx, lsm6dso_fsm_out_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fsm_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_fsm_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso_fsm_odr_t val) { lsm6dso_emb_func_odr_cfg_b_t reg; @@ -8373,7 +8377,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fsm_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_fsm_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso_fsm_odr_t *val) { lsm6dso_emb_func_odr_cfg_b_t reg; @@ -8422,7 +8426,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_emb_func_init_b_t reg; int32_t ret; @@ -8450,7 +8454,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_emb_func_init_b_t reg; int32_t ret; @@ -8477,7 +8481,7 @@ int32_t lsm6dso_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_long_cnt_int_value_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; @@ -8503,7 +8507,7 @@ int32_t lsm6dso_long_cnt_int_value_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_long_cnt_int_value_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -8526,7 +8530,7 @@ int32_t lsm6dso_long_cnt_int_value_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fsm_number_of_programs_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; @@ -8544,7 +8548,7 @@ int32_t lsm6dso_fsm_number_of_programs_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fsm_number_of_programs_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -8563,7 +8567,7 @@ int32_t lsm6dso_fsm_number_of_programs_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dso_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -8586,7 +8590,7 @@ int32_t lsm6dso_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_fsm_start_address_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -8623,7 +8627,7 @@ int32_t lsm6dso_fsm_start_address_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val, +int32_t lsm6dso_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, uint8_t len) { int32_t ret; @@ -8643,7 +8647,7 @@ int32_t lsm6dso_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_sh_slave_connected_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_sh_slave_connected_set(const stmdev_ctx_t *ctx, lsm6dso_aux_sens_on_t val) { lsm6dso_master_config_t reg; @@ -8669,7 +8673,7 @@ int32_t lsm6dso_sh_slave_connected_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_sh_slave_connected_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_sh_slave_connected_get(const stmdev_ctx_t *ctx, lsm6dso_aux_sens_on_t *val) { lsm6dso_master_config_t reg; @@ -8716,7 +8720,7 @@ int32_t lsm6dso_sh_slave_connected_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_master_config_t reg; int32_t ret; @@ -8741,7 +8745,7 @@ int32_t lsm6dso_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_master_config_t reg; int32_t ret; @@ -8764,7 +8768,7 @@ int32_t lsm6dso_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_sh_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dso_shub_pu_en_t val) { lsm6dso_master_config_t reg; @@ -8790,7 +8794,7 @@ int32_t lsm6dso_sh_pin_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_sh_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dso_shub_pu_en_t *val) { lsm6dso_master_config_t reg; @@ -8830,7 +8834,7 @@ int32_t lsm6dso_sh_pin_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dso_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dso_master_config_t reg; int32_t ret; @@ -8856,7 +8860,7 @@ int32_t lsm6dso_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_master_config_t reg; int32_t ret; @@ -8880,7 +8884,7 @@ int32_t lsm6dso_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_sh_syncro_mode_set(const stmdev_ctx_t *ctx, lsm6dso_start_config_t val) { lsm6dso_master_config_t reg; @@ -8906,7 +8910,7 @@ int32_t lsm6dso_sh_syncro_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_sh_syncro_mode_get(const stmdev_ctx_t *ctx, lsm6dso_start_config_t *val) { lsm6dso_master_config_t reg; @@ -8946,7 +8950,7 @@ int32_t lsm6dso_sh_syncro_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_sh_write_mode_set(const stmdev_ctx_t *ctx, lsm6dso_write_once_t val) { lsm6dso_master_config_t reg; @@ -8973,7 +8977,7 @@ int32_t lsm6dso_sh_write_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_sh_write_mode_get(const stmdev_ctx_t *ctx, lsm6dso_write_once_t *val) { lsm6dso_master_config_t reg; @@ -9011,7 +9015,7 @@ int32_t lsm6dso_sh_write_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_sh_reset_set(stmdev_ctx_t *ctx) +int32_t lsm6dso_sh_reset_set(const stmdev_ctx_t *ctx) { lsm6dso_master_config_t reg; int32_t ret; @@ -9040,7 +9044,7 @@ int32_t lsm6dso_sh_reset_set(stmdev_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dso_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dso_master_config_t reg; int32_t ret; @@ -9064,7 +9068,7 @@ int32_t lsm6dso_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_sh_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_sh_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso_shub_odr_t val) { lsm6dso_slv0_config_t reg; @@ -9090,7 +9094,7 @@ int32_t lsm6dso_sh_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_sh_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_sh_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso_shub_odr_t *val) { lsm6dso_slv0_config_t reg; @@ -9140,7 +9144,7 @@ int32_t lsm6dso_sh_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t lsm6dso_sh_cfg_write(const stmdev_ctx_t *ctx, lsm6dso_sh_cfg_write_t *val) { lsm6dso_slv0_add_t reg; @@ -9176,7 +9180,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_sh_slv_cfg_read(stmdev_ctx_t *ctx, uint8_t idx, +int32_t lsm6dso_sh_slv_cfg_read(const stmdev_ctx_t *ctx, uint8_t idx, lsm6dso_sh_cfg_read_t *val) { lsm6dso_slv0_add_t slv0_add; @@ -9212,7 +9216,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_sh_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_sh_status_get(const stmdev_ctx_t *ctx, lsm6dso_status_master_t *val) { int32_t ret; @@ -9247,7 +9251,7 @@ int32_t lsm6dso_sh_status_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_id_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, +int32_t lsm6dso_id_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dso_id_t *val) { int32_t ret = 0; @@ -9271,12 +9275,12 @@ int32_t lsm6dso_id_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, * @param ctx communication interface handler.(ptr) * @param val re-initialization mode. Refer to datasheet * and application note for more information - * about differencies between boot and sw_reset + * about differences between boot and sw_reset * procedure. * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_init_set(stmdev_ctx_t *ctx, lsm6dso_init_t val) +int32_t lsm6dso_init_set(const stmdev_ctx_t *ctx, lsm6dso_init_t val) { lsm6dso_emb_func_init_a_t emb_func_init_a; lsm6dso_emb_func_init_b_t emb_func_init_b; @@ -9333,7 +9337,7 @@ int32_t lsm6dso_init_set(stmdev_ctx_t *ctx, lsm6dso_init_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_bus_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, +int32_t lsm6dso_bus_mode_set(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dso_bus_mode_t val) { lsm6dso_ctrl1_ois_t ctrl1_ois; @@ -9438,7 +9442,7 @@ int32_t lsm6dso_bus_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_bus_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, +int32_t lsm6dso_bus_mode_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dso_bus_mode_t *val) { lsm6dso_ctrl1_ois_t ctrl1_ois; @@ -9551,7 +9555,7 @@ int32_t lsm6dso_bus_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_status_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, +int32_t lsm6dso_status_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dso_status_t *val) { lsm6dso_status_spiaux_t status_spiaux; @@ -9598,7 +9602,7 @@ int32_t lsm6dso_status_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_pin_conf_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_pin_conf_set(const stmdev_ctx_t *ctx, lsm6dso_pin_conf_t val) { lsm6dso_i3c_bus_avb_t i3c_bus_avb; @@ -9633,7 +9637,7 @@ int32_t lsm6dso_pin_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_pin_conf_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_pin_conf_get(const stmdev_ctx_t *ctx, lsm6dso_pin_conf_t *val) { lsm6dso_i3c_bus_avb_t i3c_bus_avb; @@ -9666,7 +9670,7 @@ int32_t lsm6dso_pin_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_interrupt_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_interrupt_mode_set(const stmdev_ctx_t *ctx, lsm6dso_int_mode_t val) { lsm6dso_tap_cfg0_t tap_cfg0; @@ -9705,7 +9709,7 @@ int32_t lsm6dso_interrupt_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_interrupt_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_interrupt_mode_get(const stmdev_ctx_t *ctx, lsm6dso_int_mode_t *val) { lsm6dso_tap_cfg0_t tap_cfg0; @@ -9742,7 +9746,7 @@ int32_t lsm6dso_interrupt_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm6dso_pin_int1_route_t val) { lsm6dso_pin_int2_route_t pin_int2_route; @@ -9923,7 +9927,7 @@ int32_t lsm6dso_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm6dso_pin_int1_route_t *val) { lsm6dso_emb_func_int1_t emb_func_int1; @@ -10020,7 +10024,7 @@ int32_t lsm6dso_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_pin_int2_route_set(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dso_pin_int2_route_t val) { @@ -10192,7 +10196,7 @@ int32_t lsm6dso_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_pin_int2_route_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dso_pin_int2_route_t *val) { @@ -10328,7 +10332,7 @@ int32_t lsm6dso_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_all_sources_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_all_sources_get(const stmdev_ctx_t *ctx, lsm6dso_all_sources_t *val) { lsm6dso_emb_func_status_mainpage_t emb_func_status_mainpage; @@ -10441,7 +10445,7 @@ int32_t lsm6dso_all_sources_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, +int32_t lsm6dso_mode_set(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dso_md_t *val) { lsm6dso_func_cfg_access_t func_cfg_access; @@ -10880,7 +10884,7 @@ int32_t lsm6dso_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, +int32_t lsm6dso_mode_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dso_md_t *val) { lsm6dso_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; @@ -11420,7 +11424,7 @@ int32_t lsm6dso_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_data_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, +int32_t lsm6dso_data_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dso_md_t *md, lsm6dso_data_t *data) { uint8_t buff[14]; @@ -11598,7 +11602,7 @@ int32_t lsm6dso_data_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_embedded_sens_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_embedded_sens_set(const stmdev_ctx_t *ctx, lsm6dso_emb_sens_t *val) { lsm6dso_emb_func_en_a_t emb_func_en_a; @@ -11637,7 +11641,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_embedded_sens_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_embedded_sens_get(const stmdev_ctx_t *ctx, lsm6dso_emb_sens_t *emb_sens) { lsm6dso_emb_func_en_a_t emb_func_en_a; @@ -11671,7 +11675,7 @@ int32_t lsm6dso_embedded_sens_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dso_embedded_sens_off(stmdev_ctx_t *ctx) +int32_t lsm6dso_embedded_sens_off(const stmdev_ctx_t *ctx) { lsm6dso_emb_func_en_a_t emb_func_en_a; lsm6dso_emb_func_en_b_t emb_func_en_b; diff --git a/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.h b/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.h index 267f2a0c..de7d1d01 100644 --- a/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.h +++ b/sensor/stmemsc/lsm6dso_STdC/driver/lsm6dso_reg.h @@ -136,10 +136,10 @@ typedef struct * The __weak directive allows the final application to overwrite * them with a custom implementation. */ -int32_t lsm6dso_read_reg(stmdev_ctx_t* ctx, uint8_t reg, +int32_t lsm6dso_read_reg(const stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data, uint16_t len); -int32_t lsm6dso_write_reg(stmdev_ctx_t* ctx, uint8_t reg, +int32_t lsm6dso_write_reg(const stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data, uint16_t len); @@ -2762,9 +2762,9 @@ typedef enum LSM6DSO_4g = 2, LSM6DSO_8g = 3, } lsm6dso_fs_xl_t; -int32_t lsm6dso_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dso_fs_xl_t val); -int32_t lsm6dso_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dso_fs_xl_t *val); typedef enum @@ -2782,9 +2782,9 @@ typedef enum LSM6DSO_XL_ODR_6667Hz = 10, LSM6DSO_XL_ODR_1Hz6 = 11, /* (low power only) */ } lsm6dso_odr_xl_t; -int32_t lsm6dso_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso_odr_xl_t val); -int32_t lsm6dso_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso_odr_xl_t *val); typedef enum @@ -2795,9 +2795,9 @@ typedef enum LSM6DSO_1000dps = 4, LSM6DSO_2000dps = 6, } lsm6dso_fs_g_t; -int32_t lsm6dso_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dso_fs_g_t val); -int32_t lsm6dso_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dso_fs_g_t *val); typedef enum @@ -2814,13 +2814,13 @@ typedef enum LSM6DSO_GY_ODR_3333Hz = 9, LSM6DSO_GY_ODR_6667Hz = 10, } lsm6dso_odr_g_t; -int32_t lsm6dso_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_gy_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso_odr_g_t val); -int32_t lsm6dso_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso_odr_g_t *val); -int32_t lsm6dso_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2828,9 +2828,9 @@ typedef enum LSM6DSO_LSb_1mg = 0, LSM6DSO_LSb_16mg = 1, } lsm6dso_usr_off_w_t; -int32_t lsm6dso_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_offset_weight_set(const stmdev_ctx_t *ctx, lsm6dso_usr_off_w_t val); -int32_t lsm6dso_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_offset_weight_get(const stmdev_ctx_t *ctx, lsm6dso_usr_off_w_t *val); typedef enum @@ -2839,9 +2839,9 @@ typedef enum LSM6DSO_LOW_NORMAL_POWER_MD = 1, LSM6DSO_ULTRA_LOW_POWER_MD = 2, } lsm6dso_xl_hm_mode_t; -int32_t lsm6dso_xl_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_power_mode_set(const stmdev_ctx_t *ctx, lsm6dso_xl_hm_mode_t val); -int32_t lsm6dso_xl_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_power_mode_get(const stmdev_ctx_t *ctx, lsm6dso_xl_hm_mode_t *val); typedef enum @@ -2849,41 +2849,41 @@ typedef enum LSM6DSO_GY_HIGH_PERFORMANCE = 0, LSM6DSO_GY_NORMAL = 1, } lsm6dso_g_hm_mode_t; -int32_t lsm6dso_gy_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_gy_power_mode_set(const stmdev_ctx_t *ctx, lsm6dso_g_hm_mode_t val); -int32_t lsm6dso_gy_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_gy_power_mode_get(const stmdev_ctx_t *ctx, lsm6dso_g_hm_mode_t *val); -int32_t lsm6dso_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_status_reg_get(const stmdev_ctx_t *ctx, lsm6dso_status_reg_t *val); -int32_t lsm6dso_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dso_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dso_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dso_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dso_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dso_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dso_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_timestamp_rst(stmdev_ctx_t *ctx); +int32_t lsm6dso_timestamp_rst(const stmdev_ctx_t *ctx); -int32_t lsm6dso_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); +int32_t lsm6dso_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); typedef enum { @@ -2892,27 +2892,27 @@ typedef enum LSM6DSO_ROUND_GY = 2, LSM6DSO_ROUND_GY_XL = 3, } lsm6dso_rounding_t; -int32_t lsm6dso_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_rounding_mode_set(const stmdev_ctx_t *ctx, lsm6dso_rounding_t val); -int32_t lsm6dso_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_rounding_mode_get(const stmdev_ctx_t *ctx, lsm6dso_rounding_t *val); -int32_t lsm6dso_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dso_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dso_angular_rate_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dso_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dso_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dso_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dso_number_of_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dso_steps_reset(stmdev_ctx_t *ctx); +int32_t lsm6dso_steps_reset(const stmdev_ctx_t *ctx); -int32_t lsm6dso_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2920,18 +2920,18 @@ typedef enum LSM6DSO_SENSOR_HUB_BANK = 1, LSM6DSO_EMBEDDED_FUNC_BANK = 2, } lsm6dso_reg_access_t; -int32_t lsm6dso_mem_bank_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dso_reg_access_t val); -int32_t lsm6dso_mem_bank_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dso_reg_access_t *val); -int32_t lsm6dso_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dso_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val); -int32_t lsm6dso_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dso_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val); -int32_t lsm6dso_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dso_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); -int32_t lsm6dso_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, +int32_t lsm6dso_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); typedef enum @@ -2939,21 +2939,21 @@ typedef enum LSM6DSO_DRDY_LATCHED = 0, LSM6DSO_DRDY_PULSED = 1, } lsm6dso_dataready_pulsed_t; -int32_t lsm6dso_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm6dso_dataready_pulsed_t val); -int32_t lsm6dso_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm6dso_dataready_pulsed_t *val); -int32_t lsm6dso_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dso_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2961,9 +2961,9 @@ typedef enum LSM6DSO_XL_ST_POSITIVE = 1, LSM6DSO_XL_ST_NEGATIVE = 2, } lsm6dso_st_xl_t; -int32_t lsm6dso_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dso_st_xl_t val); -int32_t lsm6dso_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dso_st_xl_t *val); typedef enum @@ -2972,20 +2972,20 @@ typedef enum LSM6DSO_GY_ST_POSITIVE = 1, LSM6DSO_GY_ST_NEGATIVE = 3, } lsm6dso_st_g_t; -int32_t lsm6dso_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dso_st_g_t val); -int32_t lsm6dso_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dso_st_g_t *val); -int32_t lsm6dso_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2999,13 +2999,13 @@ typedef enum LSM6DSO_AGGRESSIVE = 6, /* not available for data rate > 1k670Hz */ LSM6DSO_XTREME = 7, /* not available for data rate > 1k670Hz */ } lsm6dso_ftype_t; -int32_t lsm6dso_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dso_ftype_t val); -int32_t lsm6dso_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dso_ftype_t *val); -int32_t lsm6dso_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3033,22 +3033,22 @@ typedef enum LSM6DSO_LP_ODR_DIV_400 = 0x06, LSM6DSO_LP_ODR_DIV_800 = 0x07, } lsm6dso_hp_slope_xl_en_t; -int32_t lsm6dso_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, lsm6dso_hp_slope_xl_en_t val); -int32_t lsm6dso_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, lsm6dso_hp_slope_xl_en_t *val); -int32_t lsm6dso_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSO_USE_SLOPE = 0, LSM6DSO_USE_HPF = 1, } lsm6dso_slope_fds_t; -int32_t lsm6dso_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dso_slope_fds_t val); -int32_t lsm6dso_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dso_slope_fds_t *val); typedef enum @@ -3059,9 +3059,9 @@ typedef enum LSM6DSO_HP_FILTER_260mHz = 0x82, LSM6DSO_HP_FILTER_1Hz04 = 0x83, } lsm6dso_hpm_g_t; -int32_t lsm6dso_gy_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dso_hpm_g_t val); -int32_t lsm6dso_gy_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dso_hpm_g_t *val); typedef enum @@ -3069,9 +3069,9 @@ typedef enum LSM6DSO_AUX_PULL_UP_DISC = 0, LSM6DSO_AUX_PULL_UP_CONNECT = 1, } lsm6dso_ois_pu_dis_t; -int32_t lsm6dso_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_sdo_ocs_mode_set(const stmdev_ctx_t *ctx, lsm6dso_ois_pu_dis_t val); -int32_t lsm6dso_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_sdo_ocs_mode_get(const stmdev_ctx_t *ctx, lsm6dso_ois_pu_dis_t *val); typedef enum @@ -3079,9 +3079,9 @@ typedef enum LSM6DSO_AUX_ON = 1, LSM6DSO_AUX_ON_BY_AUX_INTERFACE = 0, } lsm6dso_ois_on_t; -int32_t lsm6dso_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_pw_on_ctrl_set(const stmdev_ctx_t *ctx, lsm6dso_ois_on_t val); -int32_t lsm6dso_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_pw_on_ctrl_get(const stmdev_ctx_t *ctx, lsm6dso_ois_on_t *val); typedef enum @@ -3089,21 +3089,21 @@ typedef enum LSM6DSO_USE_SAME_XL_FS = 0, LSM6DSO_USE_DIFFERENT_XL_FS = 1, } lsm6dso_xl_fs_mode_t; -int32_t lsm6dso_aux_xl_fs_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_xl_fs_mode_set(const stmdev_ctx_t *ctx, lsm6dso_xl_fs_mode_t val); -int32_t lsm6dso_aux_xl_fs_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_xl_fs_mode_get(const stmdev_ctx_t *ctx, lsm6dso_xl_fs_mode_t *val); -int32_t lsm6dso_aux_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_status_reg_get(const stmdev_ctx_t *ctx, lsm6dso_status_spiaux_t *val); -int32_t lsm6dso_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3112,9 +3112,9 @@ typedef enum LSM6DSO_AUX_XL_POS = 1, LSM6DSO_AUX_XL_NEG = 2, } lsm6dso_st_xl_ois_t; -int32_t lsm6dso_aux_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dso_st_xl_ois_t val); -int32_t lsm6dso_aux_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dso_st_xl_ois_t *val); typedef enum @@ -3122,9 +3122,9 @@ typedef enum LSM6DSO_AUX_DEN_ACTIVE_LOW = 0, LSM6DSO_AUX_DEN_ACTIVE_HIGH = 1, } lsm6dso_den_lh_ois_t; -int32_t lsm6dso_aux_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dso_den_lh_ois_t val); -int32_t lsm6dso_aux_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dso_den_lh_ois_t *val); typedef enum @@ -3133,13 +3133,13 @@ typedef enum LSM6DSO_AUX_DEN_LEVEL_LATCH = 3, LSM6DSO_AUX_DEN_LEVEL_TRIG = 2, } lsm6dso_lvl2_ois_t; -int32_t lsm6dso_aux_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_den_mode_set(const stmdev_ctx_t *ctx, lsm6dso_lvl2_ois_t val); -int32_t lsm6dso_aux_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_den_mode_get(const stmdev_ctx_t *ctx, lsm6dso_lvl2_ois_t *val); -int32_t lsm6dso_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_aux_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3147,9 +3147,9 @@ typedef enum LSM6DSO_MODE_3_GY = 1, LSM6DSO_MODE_4_GY_XL = 3, } lsm6dso_ois_en_spi2_t; -int32_t lsm6dso_aux_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_mode_set(const stmdev_ctx_t *ctx, lsm6dso_ois_en_spi2_t val); -int32_t lsm6dso_aux_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_mode_get(const stmdev_ctx_t *ctx, lsm6dso_ois_en_spi2_t *val); typedef enum @@ -3160,9 +3160,9 @@ typedef enum LSM6DSO_1000dps_AUX = 4, LSM6DSO_2000dps_AUX = 6, } lsm6dso_fs_g_ois_t; -int32_t lsm6dso_aux_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dso_fs_g_ois_t val); -int32_t lsm6dso_aux_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dso_fs_g_ois_t *val); typedef enum @@ -3170,9 +3170,9 @@ typedef enum LSM6DSO_AUX_SPI_4_WIRE = 0, LSM6DSO_AUX_SPI_3_WIRE = 1, } lsm6dso_sim_ois_t; -int32_t lsm6dso_aux_spi_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dso_sim_ois_t val); -int32_t lsm6dso_aux_spi_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dso_sim_ois_t *val); typedef enum @@ -3182,9 +3182,9 @@ typedef enum LSM6DSO_172Hz70 = 2, LSM6DSO_937Hz91 = 3, } lsm6dso_ftype_ois_t; -int32_t lsm6dso_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dso_ftype_ois_t val); -int32_t lsm6dso_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dso_ftype_ois_t *val); typedef enum @@ -3195,9 +3195,9 @@ typedef enum LSM6DSO_AUX_HP_Hz260 = 0x12, LSM6DSO_AUX_HP_1Hz040 = 0x13, } lsm6dso_hpm_ois_t; -int32_t lsm6dso_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_gy_hp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dso_hpm_ois_t val); -int32_t lsm6dso_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_gy_hp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dso_hpm_ois_t *val); typedef enum @@ -3205,9 +3205,9 @@ typedef enum LSM6DSO_ENABLE_CLAMP = 0, LSM6DSO_DISABLE_CLAMP = 1, } lsm6dso_st_ois_clampdis_t; -int32_t lsm6dso_aux_gy_clamp_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_gy_clamp_set(const stmdev_ctx_t *ctx, lsm6dso_st_ois_clampdis_t val); -int32_t lsm6dso_aux_gy_clamp_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_gy_clamp_get(const stmdev_ctx_t *ctx, lsm6dso_st_ois_clampdis_t *val); typedef enum @@ -3216,9 +3216,9 @@ typedef enum LSM6DSO_AUX_GY_POS = 1, LSM6DSO_AUX_GY_NEG = 3, } lsm6dso_st_ois_t; -int32_t lsm6dso_aux_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dso_st_ois_t val); -int32_t lsm6dso_aux_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dso_st_ois_t *val); typedef enum @@ -3232,9 +3232,9 @@ typedef enum LSM6DSO_8Hz30 = 6, LSM6DSO_4Hz15 = 7, } lsm6dso_filter_xl_conf_ois_t; -int32_t lsm6dso_aux_xl_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_xl_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dso_filter_xl_conf_ois_t val); -int32_t lsm6dso_aux_xl_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_xl_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dso_filter_xl_conf_ois_t *val); typedef enum @@ -3244,9 +3244,9 @@ typedef enum LSM6DSO_AUX_4g = 2, LSM6DSO_AUX_8g = 3, } lsm6dso_fs_xl_ois_t; -int32_t lsm6dso_aux_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dso_fs_xl_ois_t val); -int32_t lsm6dso_aux_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_aux_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dso_fs_xl_ois_t *val); typedef enum @@ -3254,9 +3254,9 @@ typedef enum LSM6DSO_PULL_UP_DISC = 0, LSM6DSO_PULL_UP_CONNECT = 1, } lsm6dso_sdo_pu_en_t; -int32_t lsm6dso_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, lsm6dso_sdo_pu_en_t val); -int32_t lsm6dso_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, lsm6dso_sdo_pu_en_t *val); typedef enum @@ -3264,17 +3264,17 @@ typedef enum LSM6DSO_SPI_4_WIRE = 0, LSM6DSO_SPI_3_WIRE = 1, } lsm6dso_sim_t; -int32_t lsm6dso_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso_sim_t val); -int32_t lsm6dso_spi_mode_get(stmdev_ctx_t *ctx, lsm6dso_sim_t *val); +int32_t lsm6dso_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dso_sim_t val); +int32_t lsm6dso_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dso_sim_t *val); typedef enum { LSM6DSO_I2C_ENABLE = 0, LSM6DSO_I2C_DISABLE = 1, } lsm6dso_i2c_disable_t; -int32_t lsm6dso_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_i2c_interface_set(const stmdev_ctx_t *ctx, lsm6dso_i2c_disable_t val); -int32_t lsm6dso_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_i2c_interface_get(const stmdev_ctx_t *ctx, lsm6dso_i2c_disable_t *val); typedef enum @@ -3285,9 +3285,9 @@ typedef enum LSM6DSO_I3C_ENABLE_T_1ms = 0x02, LSM6DSO_I3C_ENABLE_T_25ms = 0x03, } lsm6dso_i3c_disable_t; -int32_t lsm6dso_i3c_disable_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_i3c_disable_set(const stmdev_ctx_t *ctx, lsm6dso_i3c_disable_t val); -int32_t lsm6dso_i3c_disable_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_i3c_disable_get(const stmdev_ctx_t *ctx, lsm6dso_i3c_disable_t *val); typedef enum @@ -3295,9 +3295,9 @@ typedef enum LSM6DSO_PULL_DOWN_DISC = 0, LSM6DSO_PULL_DOWN_CONNECT = 1, } lsm6dso_int1_pd_en_t; -int32_t lsm6dso_int1_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_int1_mode_set(const stmdev_ctx_t *ctx, lsm6dso_int1_pd_en_t val); -int32_t lsm6dso_int1_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_int1_mode_get(const stmdev_ctx_t *ctx, lsm6dso_int1_pd_en_t *val); typedef enum @@ -3305,21 +3305,21 @@ typedef enum LSM6DSO_PUSH_PULL = 0, LSM6DSO_OPEN_DRAIN = 1, } lsm6dso_pp_od_t; -int32_t lsm6dso_pin_mode_set(stmdev_ctx_t *ctx, lsm6dso_pp_od_t val); -int32_t lsm6dso_pin_mode_get(stmdev_ctx_t *ctx, lsm6dso_pp_od_t *val); +int32_t lsm6dso_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dso_pp_od_t val); +int32_t lsm6dso_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dso_pp_od_t *val); typedef enum { LSM6DSO_ACTIVE_HIGH = 0, LSM6DSO_ACTIVE_LOW = 1, } lsm6dso_h_lactive_t; -int32_t lsm6dso_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_pin_polarity_set(const stmdev_ctx_t *ctx, lsm6dso_h_lactive_t val); -int32_t lsm6dso_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_pin_polarity_get(const stmdev_ctx_t *ctx, lsm6dso_h_lactive_t *val); -int32_t lsm6dso_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3328,9 +3328,9 @@ typedef enum LSM6DSO_BASE_PULSED_EMB_LATCHED = 2, LSM6DSO_ALL_INT_LATCHED = 3, } lsm6dso_lir_t; -int32_t lsm6dso_int_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_int_notification_set(const stmdev_ctx_t *ctx, lsm6dso_lir_t val); -int32_t lsm6dso_int_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_int_notification_get(const stmdev_ctx_t *ctx, lsm6dso_lir_t *val); typedef enum @@ -3338,33 +3338,33 @@ typedef enum LSM6DSO_LSb_FS_DIV_64 = 0, LSM6DSO_LSb_FS_DIV_256 = 1, } lsm6dso_wake_ths_w_t; -int32_t lsm6dso_wkup_ths_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_wkup_ths_weight_set(const stmdev_ctx_t *ctx, lsm6dso_wake_ths_w_t val); -int32_t lsm6dso_wkup_ths_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_wkup_ths_weight_get(const stmdev_ctx_t *ctx, lsm6dso_wake_ths_w_t *val); -int32_t lsm6dso_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSO_DRIVE_SLEEP_CHG_EVENT = 0, LSM6DSO_DRIVE_SLEEP_STATUS = 1, } lsm6dso_sleep_status_on_int_t; -int32_t lsm6dso_act_pin_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_act_pin_notification_set(const stmdev_ctx_t *ctx, lsm6dso_sleep_status_on_int_t val); -int32_t lsm6dso_act_pin_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_act_pin_notification_get(const stmdev_ctx_t *ctx, lsm6dso_sleep_status_on_int_t *val); typedef enum @@ -3374,31 +3374,31 @@ typedef enum LSM6DSO_XL_12Hz5_GY_SLEEP = 2, LSM6DSO_XL_12Hz5_GY_PD = 3, } lsm6dso_inact_en_t; -int32_t lsm6dso_act_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_act_mode_set(const stmdev_ctx_t *ctx, lsm6dso_inact_en_t val); -int32_t lsm6dso_act_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_act_mode_get(const stmdev_ctx_t *ctx, lsm6dso_inact_en_t *val); -int32_t lsm6dso_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3409,34 +3409,34 @@ typedef enum LSM6DSO_YZX = 5, LSM6DSO_ZXY = 6, } lsm6dso_tap_priority_t; -int32_t lsm6dso_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_tap_axis_priority_set(const stmdev_ctx_t *ctx, lsm6dso_tap_priority_t val); -int32_t lsm6dso_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_tap_axis_priority_get(const stmdev_ctx_t *ctx, lsm6dso_tap_priority_t *val); -int32_t lsm6dso_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSO_ONLY_SINGLE = 0, LSM6DSO_BOTH_SINGLE_DOUBLE = 1, } lsm6dso_single_double_tap_t; -int32_t lsm6dso_tap_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dso_single_double_tap_t val); -int32_t lsm6dso_tap_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dso_single_double_tap_t *val); typedef enum @@ -3446,13 +3446,13 @@ typedef enum LSM6DSO_DEG_60 = 2, LSM6DSO_DEG_50 = 3, } lsm6dso_sixd_ths_t; -int32_t lsm6dso_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_6d_threshold_set(const stmdev_ctx_t *ctx, lsm6dso_sixd_ths_t val); -int32_t lsm6dso_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_6d_threshold_get(const stmdev_ctx_t *ctx, lsm6dso_sixd_ths_t *val); -int32_t lsm6dso_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3465,20 +3465,20 @@ typedef enum LSM6DSO_FF_TSH_469mg = 6, LSM6DSO_FF_TSH_500mg = 7, } lsm6dso_ff_ths_t; -int32_t lsm6dso_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_ff_threshold_set(const stmdev_ctx_t *ctx, lsm6dso_ff_ths_t val); -int32_t lsm6dso_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_ff_threshold_get(const stmdev_ctx_t *ctx, lsm6dso_ff_ths_t *val); -int32_t lsm6dso_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dso_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dso_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dso_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dso_compression_algo_init_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_compression_algo_init_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_compression_algo_init_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_compression_algo_init_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3489,23 +3489,23 @@ typedef enum LSM6DSO_CMP_16_TO_1 = 0x06, LSM6DSO_CMP_32_TO_1 = 0x07, } lsm6dso_uncoptr_rate_t; -int32_t lsm6dso_compression_algo_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_compression_algo_set(const stmdev_ctx_t *ctx, lsm6dso_uncoptr_rate_t val); -int32_t lsm6dso_compression_algo_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_compression_algo_get(const stmdev_ctx_t *ctx, lsm6dso_uncoptr_rate_t *val); -int32_t lsm6dso_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_compression_algo_real_time_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_compression_algo_real_time_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_compression_algo_real_time_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_compression_algo_real_time_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3522,9 +3522,9 @@ typedef enum LSM6DSO_XL_BATCHED_AT_6667Hz = 10, LSM6DSO_XL_BATCHED_AT_6Hz5 = 11, } lsm6dso_bdr_xl_t; -int32_t lsm6dso_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_xl_batch_set(const stmdev_ctx_t *ctx, lsm6dso_bdr_xl_t val); -int32_t lsm6dso_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_xl_batch_get(const stmdev_ctx_t *ctx, lsm6dso_bdr_xl_t *val); typedef enum @@ -3542,9 +3542,9 @@ typedef enum LSM6DSO_GY_BATCHED_AT_6667Hz = 10, LSM6DSO_GY_BATCHED_AT_6Hz5 = 11, } lsm6dso_bdr_gy_t; -int32_t lsm6dso_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_gy_batch_set(const stmdev_ctx_t *ctx, lsm6dso_bdr_gy_t val); -int32_t lsm6dso_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_gy_batch_get(const stmdev_ctx_t *ctx, lsm6dso_bdr_gy_t *val); typedef enum @@ -3556,9 +3556,9 @@ typedef enum LSM6DSO_STREAM_MODE = 6, LSM6DSO_BYPASS_TO_FIFO_MODE = 7, } lsm6dso_fifo_mode_t; -int32_t lsm6dso_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dso_fifo_mode_t val); -int32_t lsm6dso_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6dso_fifo_mode_t *val); typedef enum @@ -3568,9 +3568,9 @@ typedef enum LSM6DSO_TEMP_BATCHED_AT_12Hz5 = 2, LSM6DSO_TEMP_BATCHED_AT_52Hz = 3, } lsm6dso_odr_t_batch_t; -int32_t lsm6dso_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_temp_batch_set(const stmdev_ctx_t *ctx, lsm6dso_odr_t_batch_t val); -int32_t lsm6dso_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_temp_batch_get(const stmdev_ctx_t *ctx, lsm6dso_odr_t_batch_t *val); typedef enum @@ -3580,9 +3580,9 @@ typedef enum LSM6DSO_DEC_8 = 2, LSM6DSO_DEC_32 = 3, } lsm6dso_odr_ts_batch_t; -int32_t lsm6dso_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, lsm6dso_odr_ts_batch_t val); -int32_t lsm6dso_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, lsm6dso_odr_ts_batch_t *val); typedef enum @@ -3616,39 +3616,39 @@ typedef enum LSM6DSO_ROTATION_TAG, LSM6DSO_SENSORHUB_NACK_TAG = 0x19, } lsm6dso_fifo_tag_t; -int32_t lsm6dso_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, lsm6dso_trig_counter_bdr_t val); -int32_t lsm6dso_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, lsm6dso_trig_counter_bdr_t *val); -int32_t lsm6dso_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_rst_batch_counter_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_batch_counter_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dso_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dso_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dso_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dso_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_status_get(const stmdev_ctx_t *ctx, lsm6dso_fifo_status2_t *val); -int32_t lsm6dso_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_fifo_sensor_tag_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, lsm6dso_fifo_tag_t *val); -int32_t lsm6dso_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_sh_batch_slave_set(stmdev_ctx_t *ctx, uint8_t idx, uint8_t val); -int32_t lsm6dso_sh_batch_slave_get(stmdev_ctx_t *ctx, uint8_t idx, uint8_t *val); +int32_t lsm6dso_sh_batch_slave_set(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t val); +int32_t lsm6dso_sh_batch_slave_get(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t *val); typedef enum { @@ -3658,9 +3658,9 @@ typedef enum LSM6DSO_LEVEL_TRIGGER = 2, LSM6DSO_EDGE_TRIGGER = 4, } lsm6dso_den_mode_t; -int32_t lsm6dso_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_den_mode_set(const stmdev_ctx_t *ctx, lsm6dso_den_mode_t val); -int32_t lsm6dso_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_den_mode_get(const stmdev_ctx_t *ctx, lsm6dso_den_mode_t *val); typedef enum @@ -3668,9 +3668,9 @@ typedef enum LSM6DSO_DEN_ACT_LOW = 0, LSM6DSO_DEN_ACT_HIGH = 1, } lsm6dso_den_lh_t; -int32_t lsm6dso_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dso_den_lh_t val); -int32_t lsm6dso_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dso_den_lh_t *val); typedef enum @@ -3679,19 +3679,19 @@ typedef enum LSM6DSO_STAMP_IN_XL_DATA = 1, LSM6DSO_STAMP_IN_GY_XL_DATA = 2, } lsm6dso_den_xl_g_t; -int32_t lsm6dso_den_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_den_enable_set(const stmdev_ctx_t *ctx, lsm6dso_den_xl_g_t val); -int32_t lsm6dso_den_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_den_enable_get(const stmdev_ctx_t *ctx, lsm6dso_den_xl_g_t *val); -int32_t lsm6dso_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3699,21 +3699,21 @@ typedef enum LSM6DSO_FALSE_STEP_REJ = 0x10, LSM6DSO_FALSE_STEP_REJ_ADV_MODE = 0x30, } lsm6dso_pedo_md_t; -int32_t lsm6dso_pedo_sens_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_pedo_sens_set(const stmdev_ctx_t *ctx, lsm6dso_pedo_md_t val); -int32_t lsm6dso_pedo_sens_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_pedo_sens_get(const stmdev_ctx_t *ctx, lsm6dso_pedo_md_t *val); -int32_t lsm6dso_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_pedo_step_detect_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_pedo_debounce_steps_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso_pedo_debounce_steps_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dso_pedo_steps_period_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_pedo_steps_period_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dso_pedo_steps_period_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_pedo_steps_period_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum @@ -3721,25 +3721,25 @@ typedef enum LSM6DSO_EVERY_STEP = 0, LSM6DSO_COUNT_OVERFLOW = 1, } lsm6dso_carry_count_en_t; -int32_t lsm6dso_pedo_int_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_pedo_int_mode_set(const stmdev_ctx_t *ctx, lsm6dso_carry_count_en_t val); -int32_t lsm6dso_pedo_int_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_pedo_int_mode_get(const stmdev_ctx_t *ctx, lsm6dso_carry_count_en_t *val); -int32_t lsm6dso_motion_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_motion_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dso_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dso_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dso_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dso_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dso_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dso_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dso_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dso_mag_soft_iron_set(stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dso_mag_soft_iron_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dso_mag_soft_iron_set(const stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dso_mag_soft_iron_get(const stmdev_ctx_t *ctx, int16_t *val); typedef enum { @@ -3750,9 +3750,9 @@ typedef enum LSM6DSO_Z_EQ_MIN_Z = 4, LSM6DSO_Z_EQ_Z = 5, } lsm6dso_mag_z_axis_t; -int32_t lsm6dso_mag_z_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_mag_z_orient_set(const stmdev_ctx_t *ctx, lsm6dso_mag_z_axis_t val); -int32_t lsm6dso_mag_z_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_mag_z_orient_get(const stmdev_ctx_t *ctx, lsm6dso_mag_z_axis_t *val); typedef enum @@ -3764,9 +3764,9 @@ typedef enum LSM6DSO_Y_EQ_MIN_Z = 4, LSM6DSO_Y_EQ_Z = 5, } lsm6dso_mag_y_axis_t; -int32_t lsm6dso_mag_y_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_mag_y_orient_set(const stmdev_ctx_t *ctx, lsm6dso_mag_y_axis_t val); -int32_t lsm6dso_mag_y_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_mag_y_orient_get(const stmdev_ctx_t *ctx, lsm6dso_mag_y_axis_t *val); typedef enum @@ -3778,12 +3778,12 @@ typedef enum LSM6DSO_X_EQ_MIN_Z = 4, LSM6DSO_X_EQ_Z = 5, } lsm6dso_mag_x_axis_t; -int32_t lsm6dso_mag_x_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_mag_x_orient_set(const stmdev_ctx_t *ctx, lsm6dso_mag_x_axis_t val); -int32_t lsm6dso_mag_x_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_mag_x_orient_get(const stmdev_ctx_t *ctx, lsm6dso_mag_x_axis_t *val); -int32_t lsm6dso_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct @@ -3791,13 +3791,13 @@ typedef struct lsm6dso_fsm_enable_a_t fsm_enable_a; lsm6dso_fsm_enable_b_t fsm_enable_b; } lsm6dso_emb_fsm_enable_t; -int32_t lsm6dso_fsm_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_fsm_enable_set(const stmdev_ctx_t *ctx, lsm6dso_emb_fsm_enable_t *val); -int32_t lsm6dso_fsm_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_fsm_enable_get(const stmdev_ctx_t *ctx, lsm6dso_emb_fsm_enable_t *val); -int32_t lsm6dso_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dso_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dso_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dso_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum { @@ -3805,9 +3805,9 @@ typedef enum LSM6DSO_LC_CLEAR = 1, LSM6DSO_LC_CLEAR_DONE = 2, } lsm6dso_fsm_lc_clr_t; -int32_t lsm6dso_long_clr_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_long_clr_set(const stmdev_ctx_t *ctx, lsm6dso_fsm_lc_clr_t val); -int32_t lsm6dso_long_clr_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_long_clr_get(const stmdev_ctx_t *ctx, lsm6dso_fsm_lc_clr_t *val); typedef struct @@ -3829,7 +3829,7 @@ typedef struct lsm6dso_fsm_outs15_t fsm_outs15; lsm6dso_fsm_outs16_t fsm_outs16; } lsm6dso_fsm_out_t; -int32_t lsm6dso_fsm_out_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dso_fsm_out_t *val); typedef enum @@ -3839,30 +3839,30 @@ typedef enum LSM6DSO_ODR_FSM_52Hz = 2, LSM6DSO_ODR_FSM_104Hz = 3, } lsm6dso_fsm_odr_t; -int32_t lsm6dso_fsm_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_fsm_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso_fsm_odr_t val); -int32_t lsm6dso_fsm_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_fsm_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso_fsm_odr_t *val); -int32_t lsm6dso_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_long_cnt_int_value_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dso_long_cnt_int_value_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dso_fsm_number_of_programs_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_fsm_number_of_programs_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dso_fsm_start_address_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dso_fsm_start_address_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dso_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val, +int32_t lsm6dso_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, uint8_t len); typedef enum @@ -3872,35 +3872,35 @@ typedef enum LSM6DSO_SLV_0_1_2 = 2, LSM6DSO_SLV_0_1_2_3 = 3, } lsm6dso_aux_sens_on_t; -int32_t lsm6dso_sh_slave_connected_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_sh_slave_connected_set(const stmdev_ctx_t *ctx, lsm6dso_aux_sens_on_t val); -int32_t lsm6dso_sh_slave_connected_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_sh_slave_connected_get(const stmdev_ctx_t *ctx, lsm6dso_aux_sens_on_t *val); -int32_t lsm6dso_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSO_EXT_PULL_UP = 0, LSM6DSO_INTERNAL_PULL_UP = 1, } lsm6dso_shub_pu_en_t; -int32_t lsm6dso_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_sh_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dso_shub_pu_en_t val); -int32_t lsm6dso_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_sh_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dso_shub_pu_en_t *val); -int32_t lsm6dso_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dso_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dso_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSO_EXT_ON_INT2_PIN = 1, LSM6DSO_XL_GY_DRDY = 0, } lsm6dso_start_config_t; -int32_t lsm6dso_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_sh_syncro_mode_set(const stmdev_ctx_t *ctx, lsm6dso_start_config_t val); -int32_t lsm6dso_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_sh_syncro_mode_get(const stmdev_ctx_t *ctx, lsm6dso_start_config_t *val); typedef enum @@ -3908,13 +3908,13 @@ typedef enum LSM6DSO_EACH_SH_CYCLE = 0, LSM6DSO_ONLY_FIRST_CYCLE = 1, } lsm6dso_write_once_t; -int32_t lsm6dso_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_sh_write_mode_set(const stmdev_ctx_t *ctx, lsm6dso_write_once_t val); -int32_t lsm6dso_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_sh_write_mode_get(const stmdev_ctx_t *ctx, lsm6dso_write_once_t *val); -int32_t lsm6dso_sh_reset_set(stmdev_ctx_t *ctx); -int32_t lsm6dso_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dso_sh_reset_set(const stmdev_ctx_t *ctx); +int32_t lsm6dso_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3923,9 +3923,9 @@ typedef enum LSM6DSO_SH_ODR_26Hz = 2, LSM6DSO_SH_ODR_13Hz = 3, } lsm6dso_shub_odr_t; -int32_t lsm6dso_sh_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_sh_data_rate_set(const stmdev_ctx_t *ctx, lsm6dso_shub_odr_t val); -int32_t lsm6dso_sh_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_sh_data_rate_get(const stmdev_ctx_t *ctx, lsm6dso_shub_odr_t *val); typedef struct @@ -3934,7 +3934,7 @@ typedef struct uint8_t slv0_subadd; uint8_t slv0_data; } lsm6dso_sh_cfg_write_t; -int32_t lsm6dso_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t lsm6dso_sh_cfg_write(const stmdev_ctx_t *ctx, lsm6dso_sh_cfg_write_t *val); typedef struct @@ -3943,10 +3943,10 @@ typedef struct uint8_t slv_subadd; uint8_t slv_len; } lsm6dso_sh_cfg_read_t; -int32_t lsm6dso_sh_slv_cfg_read(stmdev_ctx_t *ctx, uint8_t idx, +int32_t lsm6dso_sh_slv_cfg_read(const stmdev_ctx_t *ctx, uint8_t idx, lsm6dso_sh_cfg_read_t *val); -int32_t lsm6dso_sh_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_sh_status_get(const stmdev_ctx_t *ctx, lsm6dso_status_master_t *val); @@ -3955,7 +3955,7 @@ typedef struct uint8_t ui; uint8_t aux; } lsm6dso_id_t; -int32_t lsm6dso_id_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, +int32_t lsm6dso_id_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dso_id_t *val); typedef enum @@ -3981,9 +3981,9 @@ typedef struct lsm6dso_ui_bus_md_t ui_bus_md; lsm6dso_aux_bus_md_t aux_bus_md; } lsm6dso_bus_mode_t; -int32_t lsm6dso_bus_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, +int32_t lsm6dso_bus_mode_set(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dso_bus_mode_t val); -int32_t lsm6dso_bus_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, +int32_t lsm6dso_bus_mode_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dso_bus_mode_t *val); typedef enum @@ -3997,7 +3997,7 @@ typedef enum LSM6DSO_TILT = 0x40, /* Tilt algo initialization request */ LSM6DSO_SMOTION = 0x80, /* Significant Motion initialization request */ } lsm6dso_init_t; -int32_t lsm6dso_init_set(stmdev_ctx_t *ctx, lsm6dso_init_t val); +int32_t lsm6dso_init_set(const stmdev_ctx_t *ctx, lsm6dso_init_t val); typedef struct { @@ -4012,7 +4012,7 @@ uint8_t sw_reset : uint8_t ois_gyro_settling : 1; /* Gyroscope is in the settling phase */ } lsm6dso_status_t; -int32_t lsm6dso_status_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, +int32_t lsm6dso_status_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dso_status_t *val); typedef struct @@ -4024,9 +4024,9 @@ uint8_t aux_sdo_ocs_pull_up : uint8_t int1_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */ } lsm6dso_pin_conf_t; -int32_t lsm6dso_pin_conf_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_pin_conf_set(const stmdev_ctx_t *ctx, lsm6dso_pin_conf_t val); -int32_t lsm6dso_pin_conf_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_pin_conf_get(const stmdev_ctx_t *ctx, lsm6dso_pin_conf_t *val); typedef struct @@ -4037,9 +4037,9 @@ uint8_t base_latched : uint8_t emb_latched : 1; /* emb functions are: Pedo, Tilt, SMot, Timestamp */ } lsm6dso_int_mode_t; -int32_t lsm6dso_interrupt_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_interrupt_mode_set(const stmdev_ctx_t *ctx, lsm6dso_int_mode_t val); -int32_t lsm6dso_interrupt_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_interrupt_mode_get(const stmdev_ctx_t *ctx, lsm6dso_int_mode_t *val); typedef struct @@ -4096,9 +4096,9 @@ uint8_t fsm_lc : uint8_t mlc8 : 1; /* mlc 8 interrupt event */ } lsm6dso_pin_int1_route_t; -int32_t lsm6dso_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm6dso_pin_int1_route_t val); -int32_t lsm6dso_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm6dso_pin_int1_route_t *val); typedef struct @@ -4150,10 +4150,10 @@ uint8_t fsm_lc : uint8_t mlc8 : 1; /* mlc 8 interrupt event */ } lsm6dso_pin_int2_route_t; -int32_t lsm6dso_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_pin_int2_route_set(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dso_pin_int2_route_t val); -int32_t lsm6dso_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_pin_int2_route_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dso_pin_int2_route_t *val); @@ -4245,14 +4245,14 @@ uint8_t fifo_bdr : uint8_t fifo_ovr : 1; /* FIFO overrun */ uint8_t fifo_th : 1; /* FIFO threshold reached */ } lsm6dso_all_sources_t; -int32_t lsm6dso_all_sources_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_all_sources_get(const stmdev_ctx_t *ctx, lsm6dso_all_sources_t *val); typedef struct { uint8_t odr_fine_tune; } dev_cal_t; -int32_t lsm6dso_calibration_get(stmdev_ctx_t *ctx, dev_cal_t *val); +int32_t lsm6dso_calibration_get(const stmdev_ctx_t *ctx, dev_cal_t *val); typedef enum { @@ -4404,9 +4404,9 @@ typedef struct lsm6dso_odr_fsm_t odr; } fsm; } lsm6dso_md_t; -int32_t lsm6dso_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, +int32_t lsm6dso_mode_set(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dso_md_t *val); -int32_t lsm6dso_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, +int32_t lsm6dso_mode_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dso_md_t *val); typedef struct { @@ -4442,7 +4442,7 @@ typedef struct } gy; } ois; } lsm6dso_data_t; -int32_t lsm6dso_data_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, +int32_t lsm6dso_data_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dso_md_t *md, lsm6dso_data_t *data); typedef struct @@ -4454,11 +4454,11 @@ typedef struct uint8_t fsm : 1; /* finite state machine */ uint8_t fifo_compr : 1; /* FIFO compression */ } lsm6dso_emb_sens_t; -int32_t lsm6dso_embedded_sens_set(stmdev_ctx_t *ctx, +int32_t lsm6dso_embedded_sens_set(const stmdev_ctx_t *ctx, lsm6dso_emb_sens_t *emb_sens); -int32_t lsm6dso_embedded_sens_get(stmdev_ctx_t *ctx, +int32_t lsm6dso_embedded_sens_get(const stmdev_ctx_t *ctx, lsm6dso_emb_sens_t *emb_sens); -int32_t lsm6dso_embedded_sens_off(stmdev_ctx_t *ctx); +int32_t lsm6dso_embedded_sens_off(const stmdev_ctx_t *ctx); /** * @} diff --git a/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.c b/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.c index d4435633..a700f805 100644 --- a/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.c +++ b/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm6dsox_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm6dsox_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lsm6dsox_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm6dsox_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm6dsox_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -184,7 +194,7 @@ float_t lsm6dsox_from_lsb_to_nsec(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsox_fs_xl_t val) { lsm6dsox_ctrl1_xl_t reg; @@ -209,7 +219,7 @@ int32_t lsm6dsox_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsox_fs_xl_t *val) { lsm6dsox_ctrl1_xl_t reg; @@ -251,7 +261,7 @@ int32_t lsm6dsox_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsox_odr_xl_t val) { lsm6dsox_odr_xl_t odr_xl = val; @@ -507,7 +517,7 @@ int32_t lsm6dsox_xl_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsox_odr_xl_t *val) { lsm6dsox_ctrl1_xl_t reg; @@ -581,7 +591,7 @@ int32_t lsm6dsox_xl_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsox_fs_g_t val) { lsm6dsox_ctrl2_g_t reg; @@ -606,7 +616,7 @@ int32_t lsm6dsox_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsox_fs_g_t *val) { lsm6dsox_ctrl2_g_t reg; @@ -652,7 +662,7 @@ int32_t lsm6dsox_gy_full_scale_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_gy_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsox_odr_g_t val) { lsm6dsox_odr_g_t odr_gy = val; @@ -908,7 +918,7 @@ int32_t lsm6dsox_gy_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsox_odr_g_t *val) { lsm6dsox_ctrl2_g_t reg; @@ -978,7 +988,7 @@ int32_t lsm6dsox_gy_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_ctrl3_c_t reg; int32_t ret; @@ -1002,7 +1012,7 @@ int32_t lsm6dsox_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_ctrl3_c_t reg; @@ -1023,7 +1033,7 @@ int32_t lsm6dsox_block_data_update_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_offset_weight_set(const stmdev_ctx_t *ctx, lsm6dsox_usr_off_w_t val) { lsm6dsox_ctrl6_c_t reg; @@ -1049,7 +1059,7 @@ int32_t lsm6dsox_xl_offset_weight_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_offset_weight_get(const stmdev_ctx_t *ctx, lsm6dsox_usr_off_w_t *val) { lsm6dsox_ctrl6_c_t reg; @@ -1084,7 +1094,7 @@ int32_t lsm6dsox_xl_offset_weight_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_power_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_xl_hm_mode_t val) { lsm6dsox_ctrl5_c_t ctrl5_c; @@ -1121,7 +1131,7 @@ int32_t lsm6dsox_xl_power_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_power_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_xl_hm_mode_t *val) { lsm6dsox_ctrl5_c_t ctrl5_c; @@ -1165,7 +1175,7 @@ int32_t lsm6dsox_xl_power_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_gy_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_gy_power_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_g_hm_mode_t val) { lsm6dsox_ctrl7_g_t reg; @@ -1190,7 +1200,7 @@ int32_t lsm6dsox_gy_power_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_gy_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_gy_power_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_g_hm_mode_t *val) { lsm6dsox_ctrl7_g_t reg; @@ -1224,7 +1234,7 @@ int32_t lsm6dsox_gy_power_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_status_reg_get(const stmdev_ctx_t *ctx, lsm6dsox_status_reg_t *val) { int32_t ret; @@ -1242,7 +1252,7 @@ int32_t lsm6dsox_status_reg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_status_reg_t reg; @@ -1262,7 +1272,7 @@ int32_t lsm6dsox_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_status_reg_t reg; @@ -1282,7 +1292,7 @@ int32_t lsm6dsox_gy_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_status_reg_t reg; @@ -1304,7 +1314,7 @@ int32_t lsm6dsox_temp_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsox_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1323,7 +1333,7 @@ int32_t lsm6dsox_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsox_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1342,7 +1352,7 @@ int32_t lsm6dsox_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsox_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1361,7 +1371,7 @@ int32_t lsm6dsox_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsox_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1380,7 +1390,7 @@ int32_t lsm6dsox_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsox_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1399,7 +1409,7 @@ int32_t lsm6dsox_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsox_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1416,7 +1426,7 @@ int32_t lsm6dsox_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_ctrl7_g_t reg; int32_t ret; @@ -1440,7 +1450,7 @@ int32_t lsm6dsox_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_ctrl7_g_t reg; int32_t ret; @@ -1471,7 +1481,7 @@ int32_t lsm6dsox_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_timestamp_rst(stmdev_ctx_t *ctx) +int32_t lsm6dsox_timestamp_rst(const stmdev_ctx_t *ctx) { uint8_t rst_val = 0xAA; return lsm6dsox_write_reg(ctx, LSM6DSOX_TIMESTAMP2, &rst_val, 1); @@ -1485,7 +1495,7 @@ int32_t lsm6dsox_timestamp_rst(stmdev_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_ctrl10_c_t reg; int32_t ret; @@ -1509,7 +1519,7 @@ int32_t lsm6dsox_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_ctrl10_c_t reg; int32_t ret; @@ -1530,7 +1540,7 @@ int32_t lsm6dsox_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t lsm6dsox_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; @@ -1565,7 +1575,7 @@ int32_t lsm6dsox_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_rounding_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_rounding_t val) { lsm6dsox_ctrl5_c_t reg; @@ -1590,7 +1600,7 @@ int32_t lsm6dsox_rounding_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_rounding_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_rounding_t *val) { lsm6dsox_ctrl5_c_t reg; @@ -1642,7 +1652,7 @@ int32_t lsm6dsox_rounding_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_rounding_on_status_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_rounding_on_status_set(const stmdev_ctx_t *ctx, lsm6dsox_rounding_status_t val) { lsm6dsox_ctrl5_c_t reg; @@ -1677,7 +1687,7 @@ int32_t lsm6dsox_rounding_on_status_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_rounding_on_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_rounding_on_status_get(const stmdev_ctx_t *ctx, lsm6dsox_rounding_status_t *val) { lsm6dsox_ctrl5_c_t reg; @@ -1713,7 +1723,7 @@ int32_t lsm6dsox_rounding_on_status_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsox_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1734,7 +1744,7 @@ int32_t lsm6dsox_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsox_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1759,7 +1769,7 @@ int32_t lsm6dsox_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsox_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1783,7 +1793,7 @@ int32_t lsm6dsox_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsox_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1802,7 +1812,7 @@ int32_t lsm6dsox_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_ois_angular_rate_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_ois_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -1829,7 +1839,7 @@ int32_t lsm6dsox_ois_angular_rate_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_ois_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_ois_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -1857,7 +1867,7 @@ int32_t lsm6dsox_ois_acceleration_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; @@ -1881,7 +1891,7 @@ int32_t lsm6dsox_aux_temperature_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_ois_angular_rate_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_ois_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -1909,7 +1919,7 @@ int32_t lsm6dsox_aux_ois_angular_rate_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_ois_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_ois_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; @@ -1934,7 +1944,7 @@ int32_t lsm6dsox_aux_ois_acceleration_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsox_number_of_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1963,7 +1973,7 @@ int32_t lsm6dsox_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_steps_reset(stmdev_ctx_t *ctx) +int32_t lsm6dsox_steps_reset(const stmdev_ctx_t *ctx) { lsm6dsox_emb_func_src_t reg; int32_t ret; @@ -1997,7 +2007,7 @@ int32_t lsm6dsox_steps_reset(stmdev_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsox_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -2039,7 +2049,7 @@ int32_t lsm6dsox_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_internal_freq_fine_t reg; int32_t ret; @@ -2067,7 +2077,7 @@ int32_t lsm6dsox_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_internal_freq_fine_t reg; int32_t ret; @@ -2090,7 +2100,7 @@ int32_t lsm6dsox_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_mem_bank_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dsox_reg_access_t val) { lsm6dsox_func_cfg_access_t reg; @@ -2119,7 +2129,7 @@ int32_t lsm6dsox_mem_bank_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_mem_bank_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dsox_reg_access_t *val) { lsm6dsox_func_cfg_access_t reg; @@ -2159,7 +2169,7 @@ int32_t lsm6dsox_mem_bank_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dsox_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val) { lsm6dsox_page_rw_t page_rw; @@ -2234,7 +2244,7 @@ int32_t lsm6dsox_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dsox_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len) { lsm6dsox_page_rw_t page_rw; @@ -2336,7 +2346,7 @@ int32_t lsm6dsox_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dsox_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val) { lsm6dsox_page_rw_t page_rw; @@ -2411,7 +2421,7 @@ int32_t lsm6dsox_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t address, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_dataready_pulsed_t val) { lsm6dsox_counter_bdr_reg1_t reg; @@ -2440,7 +2450,7 @@ int32_t lsm6dsox_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_dataready_pulsed_t *val) { lsm6dsox_counter_bdr_reg1_t reg; @@ -2475,7 +2485,7 @@ int32_t lsm6dsox_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsox_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -2493,7 +2503,7 @@ int32_t lsm6dsox_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_ctrl3_c_t reg; int32_t ret; @@ -2517,7 +2527,7 @@ int32_t lsm6dsox_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_ctrl3_c_t reg; int32_t ret; @@ -2537,7 +2547,7 @@ int32_t lsm6dsox_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_ctrl3_c_t reg; int32_t ret; @@ -2562,7 +2572,7 @@ int32_t lsm6dsox_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_ctrl3_c_t reg; int32_t ret; @@ -2581,7 +2591,7 @@ int32_t lsm6dsox_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_ctrl3_c_t reg; int32_t ret; @@ -2605,7 +2615,7 @@ int32_t lsm6dsox_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_ctrl3_c_t reg; int32_t ret; @@ -2624,7 +2634,7 @@ int32_t lsm6dsox_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dsox_st_xl_t val) { lsm6dsox_ctrl5_c_t reg; @@ -2649,7 +2659,7 @@ int32_t lsm6dsox_xl_self_test_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dsox_st_xl_t *val) { lsm6dsox_ctrl5_c_t reg; @@ -2687,7 +2697,7 @@ int32_t lsm6dsox_xl_self_test_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dsox_st_g_t val) { lsm6dsox_ctrl5_c_t reg; @@ -2712,7 +2722,7 @@ int32_t lsm6dsox_gy_self_test_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dsox_st_g_t *val) { lsm6dsox_ctrl5_c_t reg; @@ -2763,7 +2773,7 @@ int32_t lsm6dsox_gy_self_test_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_ctrl1_xl_t reg; int32_t ret; @@ -2787,7 +2797,7 @@ int32_t lsm6dsox_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_ctrl1_xl_t reg; int32_t ret; @@ -2808,7 +2818,7 @@ int32_t lsm6dsox_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_ctrl4_c_t reg; int32_t ret; @@ -2834,7 +2844,7 @@ int32_t lsm6dsox_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_ctrl4_c_t reg; int32_t ret; @@ -2854,7 +2864,7 @@ int32_t lsm6dsox_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_ctrl4_c_t reg; @@ -2880,7 +2890,7 @@ int32_t lsm6dsox_filter_settling_mask_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_ctrl4_c_t reg; @@ -2900,7 +2910,7 @@ int32_t lsm6dsox_filter_settling_mask_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsox_ftype_t val) { lsm6dsox_ctrl6_c_t reg; @@ -2925,7 +2935,7 @@ int32_t lsm6dsox_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsox_ftype_t *val) { lsm6dsox_ctrl6_c_t reg; @@ -2983,7 +2993,7 @@ int32_t lsm6dsox_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_ctrl8_xl_t reg; int32_t ret; @@ -3007,7 +3017,7 @@ int32_t lsm6dsox_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_ctrl8_xl_t reg; int32_t ret; @@ -3028,7 +3038,7 @@ int32_t lsm6dsox_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, lsm6dsox_hp_slope_xl_en_t val) { lsm6dsox_ctrl8_xl_t reg; @@ -3057,7 +3067,7 @@ int32_t lsm6dsox_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, lsm6dsox_hp_slope_xl_en_t *val) { lsm6dsox_ctrl8_xl_t reg; @@ -3179,7 +3189,7 @@ int32_t lsm6dsox_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_ctrl8_xl_t reg; int32_t ret; @@ -3205,7 +3215,7 @@ int32_t lsm6dsox_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_ctrl8_xl_t reg; int32_t ret; @@ -3225,7 +3235,7 @@ int32_t lsm6dsox_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dsox_slope_fds_t val) { lsm6dsox_tap_cfg0_t reg; @@ -3251,7 +3261,7 @@ int32_t lsm6dsox_xl_hp_path_internal_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dsox_slope_fds_t *val) { lsm6dsox_tap_cfg0_t reg; @@ -3287,7 +3297,7 @@ int32_t lsm6dsox_xl_hp_path_internal_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_gy_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dsox_hpm_g_t val) { lsm6dsox_ctrl7_g_t reg; @@ -3315,7 +3325,7 @@ int32_t lsm6dsox_gy_hp_path_internal_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_gy_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dsox_hpm_g_t *val) { lsm6dsox_ctrl7_g_t reg; @@ -3374,7 +3384,7 @@ int32_t lsm6dsox_gy_hp_path_internal_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_ois_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_ois_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_spi2_read_en_t val) { lsm6dsox_func_cfg_access_t func_cfg_access; @@ -3416,7 +3426,7 @@ int32_t lsm6dsox_ois_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_ois_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_ois_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_spi2_read_en_t *val) { lsm6dsox_func_cfg_access_t func_cfg_access; @@ -3469,7 +3479,7 @@ int32_t lsm6dsox_ois_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_sdo_ocs_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_ois_pu_dis_t val) { lsm6dsox_pin_ctrl_t reg; @@ -3495,7 +3505,7 @@ int32_t lsm6dsox_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_sdo_ocs_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_ois_pu_dis_t *val) { lsm6dsox_pin_ctrl_t reg; @@ -3529,7 +3539,7 @@ int32_t lsm6dsox_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_pw_on_ctrl_set(const stmdev_ctx_t *ctx, lsm6dsox_ois_on_t val) { lsm6dsox_ctrl7_g_t reg; @@ -3555,7 +3565,7 @@ int32_t lsm6dsox_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_pw_on_ctrl_get(const stmdev_ctx_t *ctx, lsm6dsox_ois_on_t *val) { lsm6dsox_ctrl7_g_t reg; @@ -3595,7 +3605,7 @@ int32_t lsm6dsox_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_xl_fs_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_xl_fs_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_xl_fs_mode_t val) { lsm6dsox_ctrl8_xl_t reg; @@ -3625,7 +3635,7 @@ int32_t lsm6dsox_aux_xl_fs_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_xl_fs_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_xl_fs_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_xl_fs_mode_t *val) { lsm6dsox_ctrl8_xl_t reg; @@ -3659,7 +3669,7 @@ int32_t lsm6dsox_aux_xl_fs_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_status_reg_get(const stmdev_ctx_t *ctx, lsm6dsox_spi2_status_reg_ois_t *val) { int32_t ret; @@ -3678,7 +3688,7 @@ int32_t lsm6dsox_aux_status_reg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_spi2_status_reg_ois_t reg; @@ -3699,7 +3709,7 @@ int32_t lsm6dsox_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_spi2_status_reg_ois_t reg; @@ -3720,7 +3730,7 @@ int32_t lsm6dsox_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_spi2_status_reg_ois_t reg; @@ -3742,7 +3752,7 @@ int32_t lsm6dsox_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dsox_den_lh_ois_t val) { lsm6dsox_ui_int_ois_t reg; @@ -3767,7 +3777,7 @@ int32_t lsm6dsox_aux_den_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dsox_den_lh_ois_t *val) { lsm6dsox_ui_int_ois_t reg; @@ -3801,7 +3811,7 @@ int32_t lsm6dsox_aux_den_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_den_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_lvl2_ois_t val) { lsm6dsox_ui_ctrl1_ois_t ctrl1_ois; @@ -3842,7 +3852,7 @@ int32_t lsm6dsox_aux_den_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_den_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_lvl2_ois_t *val) { lsm6dsox_ui_ctrl1_ois_t ctrl1_ois; @@ -3889,7 +3899,7 @@ int32_t lsm6dsox_aux_den_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_aux_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_ui_int_ois_t reg; int32_t ret; @@ -3914,7 +3924,7 @@ int32_t lsm6dsox_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_ui_int_ois_t reg; int32_t ret; @@ -3939,7 +3949,7 @@ int32_t lsm6dsox_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_ois_en_spi2_t val) { lsm6dsox_ui_ctrl1_ois_t reg; @@ -3971,7 +3981,7 @@ int32_t lsm6dsox_aux_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_ois_en_spi2_t *val) { lsm6dsox_ui_ctrl1_ois_t reg; @@ -4009,7 +4019,7 @@ int32_t lsm6dsox_aux_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsox_fs_g_ois_t val) { lsm6dsox_ui_ctrl1_ois_t reg; @@ -4034,7 +4044,7 @@ int32_t lsm6dsox_aux_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsox_fs_g_ois_t *val) { lsm6dsox_ui_ctrl1_ois_t reg; @@ -4080,7 +4090,7 @@ int32_t lsm6dsox_aux_gy_full_scale_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_spi_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_sim_ois_t val) { lsm6dsox_ui_ctrl1_ois_t reg; @@ -4105,7 +4115,7 @@ int32_t lsm6dsox_aux_spi_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_spi_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_sim_ois_t *val) { lsm6dsox_ui_ctrl1_ois_t reg; @@ -4140,7 +4150,7 @@ int32_t lsm6dsox_aux_spi_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsox_ftype_ois_t val) { lsm6dsox_ui_ctrl2_ois_t reg; @@ -4165,7 +4175,7 @@ int32_t lsm6dsox_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsox_ftype_ois_t *val) { lsm6dsox_ui_ctrl2_ois_t reg; @@ -4207,7 +4217,7 @@ int32_t lsm6dsox_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_gy_hp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsox_hpm_ois_t val) { lsm6dsox_ui_ctrl2_ois_t reg; @@ -4233,7 +4243,7 @@ int32_t lsm6dsox_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_gy_hp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsox_hpm_ois_t *val) { lsm6dsox_ui_ctrl2_ois_t reg; @@ -4284,7 +4294,7 @@ int32_t lsm6dsox_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_gy_clamp_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_gy_clamp_set(const stmdev_ctx_t *ctx, lsm6dsox_st_ois_clampdis_t val) { lsm6dsox_ui_ctrl3_ois_t reg; @@ -4314,7 +4324,7 @@ int32_t lsm6dsox_aux_gy_clamp_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_gy_clamp_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_gy_clamp_get(const stmdev_ctx_t *ctx, lsm6dsox_st_ois_clampdis_t *val) { lsm6dsox_ui_ctrl3_ois_t reg; @@ -4349,7 +4359,7 @@ int32_t lsm6dsox_aux_gy_clamp_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_xl_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_xl_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsox_filter_xl_conf_ois_t val) { lsm6dsox_ui_ctrl3_ois_t reg; @@ -4375,7 +4385,7 @@ int32_t lsm6dsox_aux_xl_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_xl_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_xl_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsox_filter_xl_conf_ois_t *val) { lsm6dsox_ui_ctrl3_ois_t reg; @@ -4434,7 +4444,7 @@ int32_t lsm6dsox_aux_xl_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsox_fs_xl_ois_t val) { lsm6dsox_ui_ctrl3_ois_t reg; @@ -4459,7 +4469,7 @@ int32_t lsm6dsox_aux_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_aux_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsox_fs_xl_ois_t *val) { lsm6dsox_ui_ctrl3_ois_t reg; @@ -4515,7 +4525,7 @@ int32_t lsm6dsox_aux_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_sdo_pu_en_t val) { lsm6dsox_pin_ctrl_t reg; @@ -4540,7 +4550,7 @@ int32_t lsm6dsox_sdo_sa0_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_sdo_pu_en_t *val) { lsm6dsox_pin_ctrl_t reg; @@ -4574,7 +4584,7 @@ int32_t lsm6dsox_sdo_sa0_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsox_sim_t val) +int32_t lsm6dsox_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_sim_t val) { lsm6dsox_ctrl3_c_t reg; int32_t ret; @@ -4598,7 +4608,7 @@ int32_t lsm6dsox_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsox_sim_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsox_sim_t *val) +int32_t lsm6dsox_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_sim_t *val) { lsm6dsox_ctrl3_c_t reg; int32_t ret; @@ -4632,7 +4642,7 @@ int32_t lsm6dsox_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsox_sim_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_i2c_interface_set(const stmdev_ctx_t *ctx, lsm6dsox_i2c_disable_t val) { lsm6dsox_ctrl4_c_t reg; @@ -4658,7 +4668,7 @@ int32_t lsm6dsox_i2c_interface_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_i2c_interface_get(const stmdev_ctx_t *ctx, lsm6dsox_i2c_disable_t *val) { lsm6dsox_ctrl4_c_t reg; @@ -4693,7 +4703,7 @@ int32_t lsm6dsox_i2c_interface_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_i3c_disable_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_i3c_disable_set(const stmdev_ctx_t *ctx, lsm6dsox_i3c_disable_t val) { lsm6dsox_i3c_bus_avb_t i3c_bus_avb; @@ -4733,7 +4743,7 @@ int32_t lsm6dsox_i3c_disable_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_i3c_disable_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_i3c_disable_get(const stmdev_ctx_t *ctx, lsm6dsox_i3c_disable_t *val) { lsm6dsox_ctrl9_xl_t ctrl9_xl; @@ -4798,7 +4808,7 @@ int32_t lsm6dsox_i3c_disable_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsox_pp_od_t val) +int32_t lsm6dsox_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_pp_od_t val) { lsm6dsox_i3c_bus_avb_t i3c_bus_avb; lsm6dsox_ctrl3_c_t ctrl3_c; @@ -4836,7 +4846,7 @@ int32_t lsm6dsox_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsox_pp_od_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_pp_od_t *val) { lsm6dsox_i3c_bus_avb_t i3c_bus_avb; @@ -4885,7 +4895,7 @@ int32_t lsm6dsox_pin_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pin_polarity_set(const stmdev_ctx_t *ctx, lsm6dsox_h_lactive_t val) { lsm6dsox_ctrl3_c_t reg; @@ -4910,7 +4920,7 @@ int32_t lsm6dsox_pin_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pin_polarity_get(const stmdev_ctx_t *ctx, lsm6dsox_h_lactive_t *val) { lsm6dsox_ctrl3_c_t reg; @@ -4944,7 +4954,7 @@ int32_t lsm6dsox_pin_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_ctrl4_c_t reg; int32_t ret; @@ -4968,7 +4978,7 @@ int32_t lsm6dsox_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_ctrl4_c_t reg; int32_t ret; @@ -4987,7 +4997,7 @@ int32_t lsm6dsox_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_int_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_int_notification_set(const stmdev_ctx_t *ctx, lsm6dsox_lir_t val) { lsm6dsox_tap_cfg0_t tap_cfg0; @@ -5036,7 +5046,7 @@ int32_t lsm6dsox_int_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_int_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_int_notification_get(const stmdev_ctx_t *ctx, lsm6dsox_lir_t *val) { lsm6dsox_tap_cfg0_t tap_cfg0; @@ -5125,7 +5135,7 @@ int32_t lsm6dsox_int_notification_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_wkup_ths_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_wkup_ths_weight_set(const stmdev_ctx_t *ctx, lsm6dsox_wake_ths_w_t val) { lsm6dsox_wake_up_dur_t reg; @@ -5153,7 +5163,7 @@ int32_t lsm6dsox_wkup_ths_weight_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_wkup_ths_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_wkup_ths_weight_get(const stmdev_ctx_t *ctx, lsm6dsox_wake_ths_w_t *val) { lsm6dsox_wake_up_dur_t reg; @@ -5188,7 +5198,7 @@ int32_t lsm6dsox_wkup_ths_weight_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_wake_up_ths_t reg; int32_t ret; @@ -5213,7 +5223,7 @@ int32_t lsm6dsox_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_wake_up_ths_t reg; int32_t ret; @@ -5233,7 +5243,7 @@ int32_t lsm6dsox_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_wake_up_ths_t reg; @@ -5259,7 +5269,7 @@ int32_t lsm6dsox_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_wake_up_ths_t reg; @@ -5280,7 +5290,7 @@ int32_t lsm6dsox_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_wake_up_dur_t reg; int32_t ret; @@ -5305,7 +5315,7 @@ int32_t lsm6dsox_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_wake_up_dur_t reg; int32_t ret; @@ -5337,7 +5347,7 @@ int32_t lsm6dsox_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_ctrl4_c_t reg; int32_t ret; @@ -5361,7 +5371,7 @@ int32_t lsm6dsox_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_ctrl4_c_t reg; int32_t ret; @@ -5383,7 +5393,7 @@ int32_t lsm6dsox_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_act_pin_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_act_pin_notification_set(const stmdev_ctx_t *ctx, lsm6dsox_sleep_status_on_int_t val) { lsm6dsox_tap_cfg0_t reg; @@ -5411,7 +5421,7 @@ int32_t lsm6dsox_act_pin_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_act_pin_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_act_pin_notification_get(const stmdev_ctx_t *ctx, lsm6dsox_sleep_status_on_int_t *val) { lsm6dsox_tap_cfg0_t reg; @@ -5445,7 +5455,7 @@ int32_t lsm6dsox_act_pin_notification_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_act_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_act_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_inact_en_t val) { lsm6dsox_tap_cfg2_t reg; @@ -5470,7 +5480,7 @@ int32_t lsm6dsox_act_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_act_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_act_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_inact_en_t *val) { lsm6dsox_tap_cfg2_t reg; @@ -5513,7 +5523,7 @@ int32_t lsm6dsox_act_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_wake_up_dur_t reg; int32_t ret; @@ -5538,7 +5548,7 @@ int32_t lsm6dsox_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_wake_up_dur_t reg; int32_t ret; @@ -5570,7 +5580,7 @@ int32_t lsm6dsox_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_tap_cfg0_t reg; @@ -5595,7 +5605,7 @@ int32_t lsm6dsox_tap_detection_on_z_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_tap_cfg0_t reg; @@ -5615,7 +5625,7 @@ int32_t lsm6dsox_tap_detection_on_z_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_tap_cfg0_t reg; @@ -5640,7 +5650,7 @@ int32_t lsm6dsox_tap_detection_on_y_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_tap_cfg0_t reg; @@ -5660,7 +5670,7 @@ int32_t lsm6dsox_tap_detection_on_y_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_tap_cfg0_t reg; @@ -5685,7 +5695,7 @@ int32_t lsm6dsox_tap_detection_on_x_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_tap_cfg0_t reg; @@ -5705,7 +5715,7 @@ int32_t lsm6dsox_tap_detection_on_x_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_tap_cfg1_t reg; int32_t ret; @@ -5729,7 +5739,7 @@ int32_t lsm6dsox_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_tap_cfg1_t reg; int32_t ret; @@ -5749,7 +5759,7 @@ int32_t lsm6dsox_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_tap_axis_priority_set(const stmdev_ctx_t *ctx, lsm6dsox_tap_priority_t val) { lsm6dsox_tap_cfg1_t reg; @@ -5775,7 +5785,7 @@ int32_t lsm6dsox_tap_axis_priority_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_tap_axis_priority_get(const stmdev_ctx_t *ctx, lsm6dsox_tap_priority_t *val) { lsm6dsox_tap_cfg1_t reg; @@ -5825,7 +5835,7 @@ int32_t lsm6dsox_tap_axis_priority_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_tap_cfg2_t reg; int32_t ret; @@ -5849,7 +5859,7 @@ int32_t lsm6dsox_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_tap_cfg2_t reg; int32_t ret; @@ -5868,7 +5878,7 @@ int32_t lsm6dsox_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_tap_ths_6d_t reg; int32_t ret; @@ -5892,7 +5902,7 @@ int32_t lsm6dsox_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_tap_ths_6d_t reg; int32_t ret; @@ -5916,7 +5926,7 @@ int32_t lsm6dsox_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_int_dur2_t reg; int32_t ret; @@ -5945,7 +5955,7 @@ int32_t lsm6dsox_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_int_dur2_t reg; int32_t ret; @@ -5970,7 +5980,7 @@ int32_t lsm6dsox_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_int_dur2_t reg; int32_t ret; @@ -6000,7 +6010,7 @@ int32_t lsm6dsox_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_int_dur2_t reg; int32_t ret; @@ -6026,7 +6036,7 @@ int32_t lsm6dsox_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_int_dur2_t reg; int32_t ret; @@ -6057,7 +6067,7 @@ int32_t lsm6dsox_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_int_dur2_t reg; int32_t ret; @@ -6076,7 +6086,7 @@ int32_t lsm6dsox_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_tap_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_single_double_tap_t val) { lsm6dsox_wake_up_ths_t reg; @@ -6101,7 +6111,7 @@ int32_t lsm6dsox_tap_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_tap_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_single_double_tap_t *val) { lsm6dsox_wake_up_ths_t reg; @@ -6148,7 +6158,7 @@ int32_t lsm6dsox_tap_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_6d_threshold_set(const stmdev_ctx_t *ctx, lsm6dsox_sixd_ths_t val) { lsm6dsox_tap_ths_6d_t reg; @@ -6173,7 +6183,7 @@ int32_t lsm6dsox_6d_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_6d_threshold_get(const stmdev_ctx_t *ctx, lsm6dsox_sixd_ths_t *val) { lsm6dsox_tap_ths_6d_t reg; @@ -6215,7 +6225,7 @@ int32_t lsm6dsox_6d_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_tap_ths_6d_t reg; int32_t ret; @@ -6239,7 +6249,7 @@ int32_t lsm6dsox_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_tap_ths_6d_t reg; int32_t ret; @@ -6270,7 +6280,7 @@ int32_t lsm6dsox_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_ff_threshold_set(const stmdev_ctx_t *ctx, lsm6dsox_ff_ths_t val) { lsm6dsox_free_fall_t reg; @@ -6295,7 +6305,7 @@ int32_t lsm6dsox_ff_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_ff_threshold_get(const stmdev_ctx_t *ctx, lsm6dsox_ff_ths_t *val) { lsm6dsox_free_fall_t reg; @@ -6354,7 +6364,7 @@ int32_t lsm6dsox_ff_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_wake_up_dur_t wake_up_dur; lsm6dsox_free_fall_t free_fall; @@ -6395,7 +6405,7 @@ int32_t lsm6dsox_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_wake_up_dur_t wake_up_dur; lsm6dsox_free_fall_t free_fall; @@ -6434,7 +6444,7 @@ int32_t lsm6dsox_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsox_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val) { lsm6dsox_fifo_ctrl1_t fifo_ctrl1; lsm6dsox_fifo_ctrl2_t fifo_ctrl2; @@ -6468,7 +6478,7 @@ int32_t lsm6dsox_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsox_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dsox_fifo_ctrl1_t fifo_ctrl1; lsm6dsox_fifo_ctrl2_t fifo_ctrl2; @@ -6496,7 +6506,7 @@ int32_t lsm6dsox_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_compression_algo_init_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_compression_algo_init_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_emb_func_init_b_t reg; @@ -6534,7 +6544,7 @@ int32_t lsm6dsox_compression_algo_init_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_compression_algo_init_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_compression_algo_init_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_emb_func_init_b_t reg; @@ -6566,7 +6576,7 @@ int32_t lsm6dsox_compression_algo_init_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_compression_algo_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_compression_algo_set(const stmdev_ctx_t *ctx, lsm6dsox_uncoptr_rate_t val) { lsm6dsox_fifo_ctrl2_t fifo_ctrl2; @@ -6595,7 +6605,7 @@ int32_t lsm6dsox_compression_algo_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_compression_algo_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_compression_algo_get(const stmdev_ctx_t *ctx, lsm6dsox_uncoptr_rate_t *val) { lsm6dsox_fifo_ctrl2_t reg; @@ -6641,7 +6651,7 @@ int32_t lsm6dsox_compression_algo_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_fifo_ctrl2_t reg; @@ -6666,7 +6676,7 @@ int32_t lsm6dsox_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_fifo_ctrl2_t reg; @@ -6687,7 +6697,7 @@ int32_t lsm6dsox_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_compression_algo_real_time_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_compression_algo_real_time_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_fifo_ctrl2_t reg; @@ -6712,7 +6722,7 @@ int32_t lsm6dsox_compression_algo_real_time_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_compression_algo_real_time_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_compression_algo_real_time_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_fifo_ctrl2_t reg; @@ -6733,7 +6743,7 @@ int32_t lsm6dsox_compression_algo_real_time_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_fifo_ctrl2_t reg; int32_t ret; @@ -6758,7 +6768,7 @@ int32_t lsm6dsox_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_fifo_ctrl2_t reg; int32_t ret; @@ -6778,7 +6788,7 @@ int32_t lsm6dsox_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_xl_batch_set(const stmdev_ctx_t *ctx, lsm6dsox_bdr_xl_t val) { lsm6dsox_fifo_ctrl3_t reg; @@ -6804,7 +6814,7 @@ int32_t lsm6dsox_fifo_xl_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_xl_batch_get(const stmdev_ctx_t *ctx, lsm6dsox_bdr_xl_t *val) { lsm6dsox_fifo_ctrl3_t reg; @@ -6879,7 +6889,7 @@ int32_t lsm6dsox_fifo_xl_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_gy_batch_set(const stmdev_ctx_t *ctx, lsm6dsox_bdr_gy_t val) { lsm6dsox_fifo_ctrl3_t reg; @@ -6905,7 +6915,7 @@ int32_t lsm6dsox_fifo_gy_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_gy_batch_get(const stmdev_ctx_t *ctx, lsm6dsox_bdr_gy_t *val) { lsm6dsox_fifo_ctrl3_t reg; @@ -6979,7 +6989,7 @@ int32_t lsm6dsox_fifo_gy_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_fifo_mode_t val) { lsm6dsox_fifo_ctrl4_t reg; @@ -7004,7 +7014,7 @@ int32_t lsm6dsox_fifo_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_fifo_mode_t *val) { lsm6dsox_fifo_ctrl4_t reg; @@ -7055,7 +7065,7 @@ int32_t lsm6dsox_fifo_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_temp_batch_set(const stmdev_ctx_t *ctx, lsm6dsox_odr_t_batch_t val) { lsm6dsox_fifo_ctrl4_t reg; @@ -7081,7 +7091,7 @@ int32_t lsm6dsox_fifo_temp_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_temp_batch_get(const stmdev_ctx_t *ctx, lsm6dsox_odr_t_batch_t *val) { lsm6dsox_fifo_ctrl4_t reg; @@ -7125,7 +7135,7 @@ int32_t lsm6dsox_fifo_temp_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, lsm6dsox_odr_ts_batch_t val) { lsm6dsox_fifo_ctrl4_t reg; @@ -7152,7 +7162,7 @@ int32_t lsm6dsox_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, lsm6dsox_odr_ts_batch_t *val) { lsm6dsox_fifo_ctrl4_t reg; @@ -7196,7 +7206,7 @@ int32_t lsm6dsox_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, lsm6dsox_trig_counter_bdr_t val) { lsm6dsox_counter_bdr_reg1_t reg; @@ -7225,7 +7235,7 @@ int32_t lsm6dsox_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, lsm6dsox_trig_counter_bdr_t *val) { lsm6dsox_counter_bdr_reg1_t reg; @@ -7262,7 +7272,7 @@ int32_t lsm6dsox_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_counter_bdr_reg1_t reg; int32_t ret; @@ -7290,7 +7300,7 @@ int32_t lsm6dsox_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_rst_batch_counter_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_counter_bdr_reg1_t reg; @@ -7312,7 +7322,7 @@ int32_t lsm6dsox_rst_batch_counter_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_batch_counter_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { lsm6dsox_counter_bdr_reg1_t counter_bdr_reg1; @@ -7348,7 +7358,7 @@ int32_t lsm6dsox_batch_counter_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dsox_counter_bdr_reg1_t counter_bdr_reg1; @@ -7377,7 +7387,7 @@ int32_t lsm6dsox_batch_counter_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsox_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dsox_fifo_status1_t fifo_status1; lsm6dsox_fifo_status2_t fifo_status2; @@ -7405,7 +7415,7 @@ int32_t lsm6dsox_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_status_get(const stmdev_ctx_t *ctx, lsm6dsox_fifo_status2_t *val) { int32_t ret; @@ -7423,7 +7433,7 @@ int32_t lsm6dsox_fifo_status_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_fifo_status2_t reg; int32_t ret; @@ -7443,7 +7453,7 @@ int32_t lsm6dsox_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_fifo_status2_t reg; int32_t ret; @@ -7462,7 +7472,7 @@ int32_t lsm6dsox_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_fifo_status2_t reg; int32_t ret; @@ -7481,7 +7491,7 @@ int32_t lsm6dsox_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fifo_sensor_tag_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, lsm6dsox_fifo_tag_t *val) { lsm6dsox_fifo_data_out_tag_t reg; @@ -7598,7 +7608,7 @@ int32_t lsm6dsox_fifo_sensor_tag_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_emb_func_fifo_cfg_t reg; int32_t ret; @@ -7635,7 +7645,7 @@ int32_t lsm6dsox_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_emb_func_fifo_cfg_t reg; int32_t ret; @@ -7666,7 +7676,7 @@ int32_t lsm6dsox_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_slv0_config_t reg; int32_t ret; @@ -7701,7 +7711,7 @@ int32_t lsm6dsox_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_slv0_config_t reg; int32_t ret; @@ -7731,7 +7741,7 @@ int32_t lsm6dsox_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_slv1_config_t reg; int32_t ret; @@ -7766,7 +7776,7 @@ int32_t lsm6dsox_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_slv1_config_t reg; int32_t ret; @@ -7796,7 +7806,7 @@ int32_t lsm6dsox_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_slv2_config_t reg; int32_t ret; @@ -7831,7 +7841,7 @@ int32_t lsm6dsox_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_slv2_config_t reg; int32_t ret; @@ -7861,7 +7871,7 @@ int32_t lsm6dsox_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_slv3_config_t reg; int32_t ret; @@ -7896,7 +7906,7 @@ int32_t lsm6dsox_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_slv3_config_t reg; int32_t ret; @@ -7938,7 +7948,7 @@ int32_t lsm6dsox_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_den_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_den_mode_t val) { lsm6dsox_ctrl6_c_t reg; @@ -7963,7 +7973,7 @@ int32_t lsm6dsox_den_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_den_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_den_mode_t *val) { lsm6dsox_ctrl6_c_t reg; @@ -8009,7 +8019,7 @@ int32_t lsm6dsox_den_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dsox_den_lh_t val) { lsm6dsox_ctrl9_xl_t reg; @@ -8034,7 +8044,7 @@ int32_t lsm6dsox_den_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dsox_den_lh_t *val) { lsm6dsox_ctrl9_xl_t reg; @@ -8068,7 +8078,7 @@ int32_t lsm6dsox_den_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_den_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_den_enable_set(const stmdev_ctx_t *ctx, lsm6dsox_den_xl_g_t val) { lsm6dsox_ctrl9_xl_t reg; @@ -8093,7 +8103,7 @@ int32_t lsm6dsox_den_enable_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_den_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_den_enable_get(const stmdev_ctx_t *ctx, lsm6dsox_den_xl_g_t *val) { lsm6dsox_ctrl9_xl_t reg; @@ -8131,7 +8141,7 @@ int32_t lsm6dsox_den_enable_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_ctrl9_xl_t reg; int32_t ret; @@ -8155,7 +8165,7 @@ int32_t lsm6dsox_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_ctrl9_xl_t reg; int32_t ret; @@ -8174,7 +8184,7 @@ int32_t lsm6dsox_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_ctrl9_xl_t reg; int32_t ret; @@ -8198,7 +8208,7 @@ int32_t lsm6dsox_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_ctrl9_xl_t reg; int32_t ret; @@ -8217,7 +8227,7 @@ int32_t lsm6dsox_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_ctrl9_xl_t reg; int32_t ret; @@ -8241,7 +8251,7 @@ int32_t lsm6dsox_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_ctrl9_xl_t reg; int32_t ret; @@ -8272,7 +8282,7 @@ int32_t lsm6dsox_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_pedo_sens_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pedo_sens_set(const stmdev_ctx_t *ctx, lsm6dsox_pedo_md_t val) { lsm6dsox_pedo_cmd_reg_t pedo_cmd_reg; @@ -8300,7 +8310,7 @@ int32_t lsm6dsox_pedo_sens_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_pedo_sens_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pedo_sens_get(const stmdev_ctx_t *ctx, lsm6dsox_pedo_md_t *val) { lsm6dsox_pedo_cmd_reg_t pedo_cmd_reg; @@ -8340,7 +8350,7 @@ int32_t lsm6dsox_pedo_sens_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_pedo_step_detect_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_emb_func_status_t reg; int32_t ret; @@ -8370,7 +8380,7 @@ int32_t lsm6dsox_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_pedo_debounce_steps_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -8389,7 +8399,7 @@ int32_t lsm6dsox_pedo_debounce_steps_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_pedo_debounce_steps_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -8408,7 +8418,7 @@ int32_t lsm6dsox_pedo_debounce_steps_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_pedo_steps_period_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pedo_steps_period_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; @@ -8436,7 +8446,7 @@ int32_t lsm6dsox_pedo_steps_period_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_pedo_steps_period_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pedo_steps_period_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -8465,7 +8475,7 @@ int32_t lsm6dsox_pedo_steps_period_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_pedo_int_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pedo_int_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_carry_count_en_t val) { lsm6dsox_pedo_cmd_reg_t reg; @@ -8493,7 +8503,7 @@ int32_t lsm6dsox_pedo_int_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_pedo_int_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pedo_int_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_carry_count_en_t *val) { lsm6dsox_pedo_cmd_reg_t reg; @@ -8541,7 +8551,7 @@ int32_t lsm6dsox_pedo_int_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_motion_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_motion_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_emb_func_status_t reg; @@ -8585,7 +8595,7 @@ int32_t lsm6dsox_motion_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_emb_func_status_t reg; @@ -8630,7 +8640,7 @@ int32_t lsm6dsox_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_mag_sensitivity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; @@ -8659,7 +8669,7 @@ int32_t lsm6dsox_sh_mag_sensitivity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_mag_sensitivity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -8688,7 +8698,7 @@ int32_t lsm6dsox_sh_mag_sensitivity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_mlc_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; @@ -8717,7 +8727,7 @@ int32_t lsm6dsox_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -8746,7 +8756,7 @@ int32_t lsm6dsox_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsox_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -8808,7 +8818,7 @@ int32_t lsm6dsox_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsox_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -8877,7 +8887,7 @@ int32_t lsm6dsox_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_mag_soft_iron_set(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsox_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[12]; uint8_t index; @@ -8994,7 +9004,7 @@ int32_t lsm6dsox_mag_soft_iron_set(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsox_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[12]; uint8_t index; @@ -9108,7 +9118,7 @@ int32_t lsm6dsox_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_mag_z_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_mag_z_orient_set(const stmdev_ctx_t *ctx, lsm6dsox_mag_z_axis_t val) { lsm6dsox_mag_cfg_a_t reg; @@ -9138,7 +9148,7 @@ int32_t lsm6dsox_mag_z_orient_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_mag_z_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_mag_z_orient_get(const stmdev_ctx_t *ctx, lsm6dsox_mag_z_axis_t *val) { lsm6dsox_mag_cfg_a_t reg; @@ -9192,7 +9202,7 @@ int32_t lsm6dsox_mag_z_orient_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_mag_y_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_mag_y_orient_set(const stmdev_ctx_t *ctx, lsm6dsox_mag_y_axis_t val) { lsm6dsox_mag_cfg_a_t reg; @@ -9222,7 +9232,7 @@ int32_t lsm6dsox_mag_y_orient_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_mag_y_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_mag_y_orient_get(const stmdev_ctx_t *ctx, lsm6dsox_mag_y_axis_t *val) { lsm6dsox_mag_cfg_a_t reg; @@ -9276,7 +9286,7 @@ int32_t lsm6dsox_mag_y_orient_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_mag_x_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_mag_x_orient_set(const stmdev_ctx_t *ctx, lsm6dsox_mag_x_axis_t val) { lsm6dsox_mag_cfg_b_t reg; @@ -9306,7 +9316,7 @@ int32_t lsm6dsox_mag_x_orient_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_mag_x_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_mag_x_orient_get(const stmdev_ctx_t *ctx, lsm6dsox_mag_x_axis_t *val) { lsm6dsox_mag_cfg_b_t reg; @@ -9371,7 +9381,7 @@ int32_t lsm6dsox_mag_x_orient_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_emb_func_status_t reg; @@ -9402,7 +9412,7 @@ int32_t lsm6dsox_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fsm_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fsm_enable_set(const stmdev_ctx_t *ctx, lsm6dsox_emb_fsm_enable_t *val) { int32_t ret; @@ -9437,7 +9447,7 @@ int32_t lsm6dsox_fsm_enable_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fsm_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fsm_enable_get(const stmdev_ctx_t *ctx, lsm6dsox_emb_fsm_enable_t *val) { int32_t ret; @@ -9467,7 +9477,7 @@ int32_t lsm6dsox_fsm_enable_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsox_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -9498,7 +9508,7 @@ int32_t lsm6dsox_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsox_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -9529,7 +9539,7 @@ int32_t lsm6dsox_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_long_clr_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_long_clr_set(const stmdev_ctx_t *ctx, lsm6dsox_fsm_lc_clr_t val) { lsm6dsox_fsm_long_counter_clear_t reg; @@ -9567,7 +9577,7 @@ int32_t lsm6dsox_long_clr_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_long_clr_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_long_clr_get(const stmdev_ctx_t *ctx, lsm6dsox_fsm_lc_clr_t *val) { lsm6dsox_fsm_long_counter_clear_t reg; @@ -9619,7 +9629,7 @@ int32_t lsm6dsox_long_clr_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fsm_out_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dsox_fsm_out_t *val) { int32_t ret; @@ -9647,7 +9657,7 @@ int32_t lsm6dsox_fsm_out_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fsm_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fsm_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsox_fsm_odr_t val) { lsm6dsox_emb_func_odr_cfg_b_t reg; @@ -9686,7 +9696,7 @@ int32_t lsm6dsox_fsm_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fsm_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fsm_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsox_fsm_odr_t *val) { lsm6dsox_emb_func_odr_cfg_b_t reg; @@ -9739,7 +9749,7 @@ int32_t lsm6dsox_fsm_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_emb_func_init_b_t reg; int32_t ret; @@ -9775,7 +9785,7 @@ int32_t lsm6dsox_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_emb_func_init_b_t reg; int32_t ret; @@ -9808,7 +9818,7 @@ int32_t lsm6dsox_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_long_cnt_int_value_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val) { int32_t ret; @@ -9840,7 +9850,7 @@ int32_t lsm6dsox_long_cnt_int_value_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_long_cnt_int_value_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val) { int32_t ret; @@ -9870,7 +9880,7 @@ int32_t lsm6dsox_long_cnt_int_value_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fsm_number_of_programs_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; @@ -9888,7 +9898,7 @@ int32_t lsm6dsox_fsm_number_of_programs_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fsm_number_of_programs_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -9907,7 +9917,7 @@ int32_t lsm6dsox_fsm_number_of_programs_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fsm_start_address_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val) { int32_t ret; @@ -9937,7 +9947,7 @@ int32_t lsm6dsox_fsm_start_address_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_fsm_start_address_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val) { int32_t ret; @@ -9978,7 +9988,7 @@ int32_t lsm6dsox_fsm_start_address_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_mlc_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_mlc_status_get(const stmdev_ctx_t *ctx, lsm6dsox_mlc_status_mainpage_t *val) { return lsm6dsox_read_reg(ctx, LSM6DSOX_MLC_STATUS_MAINPAGE, @@ -9994,7 +10004,7 @@ int32_t lsm6dsox_mlc_status_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_mlc_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_mlc_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsox_mlc_odr_t val) { lsm6dsox_emb_func_odr_cfg_c_t reg; @@ -10032,7 +10042,7 @@ int32_t lsm6dsox_mlc_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_mlc_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_mlc_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsox_mlc_odr_t *val) { lsm6dsox_emb_func_odr_cfg_c_t reg; @@ -10097,7 +10107,7 @@ int32_t lsm6dsox_mlc_data_rate_get(stmdev_ctx_t *ctx, * @param val union of registers from SENSOR_HUB_1 to SENSOR_HUB_18 * */ -int32_t lsm6dsox_sh_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_read_data_raw_get(const stmdev_ctx_t *ctx, lsm6dsox_emb_sh_read_t *val, uint8_t len) { @@ -10127,7 +10137,7 @@ int32_t lsm6dsox_sh_read_data_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_slave_connected_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_slave_connected_set(const stmdev_ctx_t *ctx, lsm6dsox_aux_sens_on_t val) { lsm6dsox_master_config_t reg; @@ -10162,7 +10172,7 @@ int32_t lsm6dsox_sh_slave_connected_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_slave_connected_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_slave_connected_get(const stmdev_ctx_t *ctx, lsm6dsox_aux_sens_on_t *val) { lsm6dsox_master_config_t reg; @@ -10214,7 +10224,7 @@ int32_t lsm6dsox_sh_slave_connected_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_master_config_t reg; int32_t ret; @@ -10248,7 +10258,7 @@ int32_t lsm6dsox_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_master_config_t reg; int32_t ret; @@ -10277,7 +10287,7 @@ int32_t lsm6dsox_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_shub_pu_en_t val) { lsm6dsox_master_config_t reg; @@ -10312,7 +10322,7 @@ int32_t lsm6dsox_sh_pin_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_shub_pu_en_t *val) { lsm6dsox_master_config_t reg; @@ -10357,7 +10367,7 @@ int32_t lsm6dsox_sh_pin_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_master_config_t reg; int32_t ret; @@ -10392,7 +10402,7 @@ int32_t lsm6dsox_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_master_config_t reg; int32_t ret; @@ -10421,7 +10431,7 @@ int32_t lsm6dsox_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_syncro_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_start_config_t val) { lsm6dsox_master_config_t reg; @@ -10456,7 +10466,7 @@ int32_t lsm6dsox_sh_syncro_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_syncro_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_start_config_t *val) { lsm6dsox_master_config_t reg; @@ -10501,7 +10511,7 @@ int32_t lsm6dsox_sh_syncro_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_write_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_write_once_t val) { lsm6dsox_master_config_t reg; @@ -10537,7 +10547,7 @@ int32_t lsm6dsox_sh_write_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_write_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_write_once_t *val) { lsm6dsox_master_config_t reg; @@ -10580,7 +10590,7 @@ int32_t lsm6dsox_sh_write_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_reset_set(stmdev_ctx_t *ctx) +int32_t lsm6dsox_sh_reset_set(const stmdev_ctx_t *ctx) { lsm6dsox_master_config_t reg; int32_t ret; @@ -10620,7 +10630,7 @@ int32_t lsm6dsox_sh_reset_set(stmdev_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_master_config_t reg; int32_t ret; @@ -10649,7 +10659,7 @@ int32_t lsm6dsox_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsox_shub_odr_t val) { lsm6dsox_slv0_config_t reg; @@ -10684,7 +10694,7 @@ int32_t lsm6dsox_sh_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsox_shub_odr_t *val) { lsm6dsox_slv0_config_t reg; @@ -10739,7 +10749,7 @@ int32_t lsm6dsox_sh_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_cfg_write(const stmdev_ctx_t *ctx, lsm6dsox_sh_cfg_write_t *val) { lsm6dsox_slv0_add_t reg; @@ -10785,7 +10795,7 @@ int32_t lsm6dsox_sh_cfg_write(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_slv0_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, lsm6dsox_sh_cfg_read_t *val) { lsm6dsox_slv0_add_t slv0_add; @@ -10839,7 +10849,7 @@ int32_t lsm6dsox_sh_slv0_cfg_read(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_slv1_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, lsm6dsox_sh_cfg_read_t *val) { lsm6dsox_slv1_add_t slv1_add; @@ -10893,7 +10903,7 @@ int32_t lsm6dsox_sh_slv1_cfg_read(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_slv2_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, lsm6dsox_sh_cfg_read_t *val) { lsm6dsox_slv2_add_t slv2_add; @@ -10947,7 +10957,7 @@ int32_t lsm6dsox_sh_slv2_cfg_read(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_slv3_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, lsm6dsox_sh_cfg_read_t *val) { lsm6dsox_slv3_add_t slv3_add; @@ -10998,7 +11008,7 @@ int32_t lsm6dsox_sh_slv3_cfg_read(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_sh_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_status_get(const stmdev_ctx_t *ctx, lsm6dsox_status_master_t *val) { int32_t ret; @@ -11039,7 +11049,7 @@ int32_t lsm6dsox_sh_status_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_s4s_tph_res_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_s4s_tph_res_set(const stmdev_ctx_t *ctx, lsm6dsox_s4s_tph_res_t val) { lsm6dsox_s4s_tph_l_t reg; @@ -11064,7 +11074,7 @@ int32_t lsm6dsox_s4s_tph_res_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_s4s_tph_res_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_s4s_tph_res_get(const stmdev_ctx_t *ctx, lsm6dsox_s4s_tph_res_t *val) { lsm6dsox_s4s_tph_l_t reg; @@ -11099,7 +11109,7 @@ int32_t lsm6dsox_s4s_tph_res_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_s4s_tph_val_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsox_s4s_tph_val_set(const stmdev_ctx_t *ctx, uint16_t val) { lsm6dsox_s4s_tph_l_t s4s_tph_l; lsm6dsox_s4s_tph_h_t s4s_tph_h; @@ -11140,7 +11150,7 @@ int32_t lsm6dsox_s4s_tph_val_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_s4s_tph_val_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsox_s4s_tph_val_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dsox_s4s_tph_l_t s4s_tph_l; lsm6dsox_s4s_tph_h_t s4s_tph_h; @@ -11170,7 +11180,7 @@ int32_t lsm6dsox_s4s_tph_val_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_s4s_res_ratio_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_s4s_res_ratio_set(const stmdev_ctx_t *ctx, lsm6dsox_s4s_res_ratio_t val) { lsm6dsox_s4s_rr_t reg; @@ -11196,7 +11206,7 @@ int32_t lsm6dsox_s4s_res_ratio_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_s4s_res_ratio_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_s4s_res_ratio_get(const stmdev_ctx_t *ctx, lsm6dsox_s4s_res_ratio_t *val) { lsm6dsox_s4s_rr_t reg; @@ -11238,7 +11248,7 @@ int32_t lsm6dsox_s4s_res_ratio_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_s4s_command_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_s4s_command_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_s4s_st_cmd_code_t reg; int32_t ret; @@ -11264,7 +11274,7 @@ int32_t lsm6dsox_s4s_command_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_s4s_command_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_s4s_command_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_s4s_st_cmd_code_t reg; int32_t ret; @@ -11284,7 +11294,7 @@ int32_t lsm6dsox_s4s_command_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_s4s_dt_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsox_s4s_dt_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsox_s4s_dt_reg_t reg; int32_t ret; @@ -11308,7 +11318,7 @@ int32_t lsm6dsox_s4s_dt_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_s4s_dt_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsox_s4s_dt_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsox_s4s_dt_reg_t reg; int32_t ret; @@ -11344,7 +11354,7 @@ int32_t lsm6dsox_s4s_dt_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_id_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, +int32_t lsm6dsox_id_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dsox_id_t *val) { int32_t ret = 0; @@ -11378,7 +11388,7 @@ int32_t lsm6dsox_id_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_init_set(stmdev_ctx_t *ctx, lsm6dsox_init_t val) +int32_t lsm6dsox_init_set(const stmdev_ctx_t *ctx, lsm6dsox_init_t val) { lsm6dsox_emb_func_init_a_t emb_func_init_a; lsm6dsox_emb_func_init_b_t emb_func_init_b; @@ -11465,7 +11475,7 @@ int32_t lsm6dsox_init_set(stmdev_ctx_t *ctx, lsm6dsox_init_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_bus_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_bus_mode_set(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dsox_bus_mode_t val) { @@ -11571,7 +11581,7 @@ int32_t lsm6dsox_bus_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_bus_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_bus_mode_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dsox_bus_mode_t *val) { @@ -11685,7 +11695,7 @@ int32_t lsm6dsox_bus_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_status_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, +int32_t lsm6dsox_status_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dsox_status_t *val) { lsm6dsox_spi2_status_reg_ois_t spi2_status_reg_ois; @@ -11745,7 +11755,7 @@ int32_t lsm6dsox_status_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_pin_conf_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pin_conf_set(const stmdev_ctx_t *ctx, lsm6dsox_pin_conf_t val) { lsm6dsox_i3c_bus_avb_t i3c_bus_avb; @@ -11798,7 +11808,7 @@ int32_t lsm6dsox_pin_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_pin_conf_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pin_conf_get(const stmdev_ctx_t *ctx, lsm6dsox_pin_conf_t *val) { lsm6dsox_i3c_bus_avb_t i3c_bus_avb; @@ -11838,7 +11848,7 @@ int32_t lsm6dsox_pin_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_interrupt_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_interrupt_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_int_mode_t val) { lsm6dsox_tap_cfg0_t tap_cfg0; @@ -11899,7 +11909,7 @@ int32_t lsm6dsox_interrupt_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_interrupt_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_interrupt_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_int_mode_t *val) { lsm6dsox_tap_cfg0_t tap_cfg0; @@ -11947,21 +11957,22 @@ int32_t lsm6dsox_interrupt_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm6dsox_pin_int1_route_t val) { lsm6dsox_pin_int2_route_t pin_int2_route; - lsm6dsox_emb_func_int1_t emb_func_int1; - lsm6dsox_fsm_int1_a_t fsm_int1_a; - lsm6dsox_fsm_int1_b_t fsm_int1_b; - lsm6dsox_int1_ctrl_t int1_ctrl; + lsm6dsox_emb_func_int1_t emb_func_int1 = {0}; + lsm6dsox_fsm_int1_a_t fsm_int1_a = {0}; + lsm6dsox_fsm_int1_b_t fsm_int1_b = {0}; + lsm6dsox_int1_ctrl_t int1_ctrl = {0}; lsm6dsox_int2_ctrl_t int2_ctrl; - lsm6dsox_mlc_int1_t mlc_int1; + lsm6dsox_mlc_int1_t mlc_int1 = {0}; lsm6dsox_tap_cfg2_t tap_cfg2; lsm6dsox_md2_cfg_t md2_cfg; - lsm6dsox_md1_cfg_t md1_cfg; + lsm6dsox_md1_cfg_t md1_cfg = {0}; lsm6dsox_ctrl4_c_t ctrl4_c; int32_t ret; + int1_ctrl.int1_drdy_xl = val.drdy_xl; int1_ctrl.int1_drdy_g = val.drdy_g; int1_ctrl.int1_boot = val.boot; @@ -12194,7 +12205,7 @@ int32_t lsm6dsox_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm6dsox_pin_int1_route_t *val) { lsm6dsox_emb_func_int1_t emb_func_int1; @@ -12334,7 +12345,7 @@ int32_t lsm6dsox_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pin_int2_route_set(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dsox_pin_int2_route_t val) { @@ -12576,7 +12587,7 @@ int32_t lsm6dsox_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pin_int2_route_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dsox_pin_int2_route_t *val) { @@ -12727,7 +12738,7 @@ int32_t lsm6dsox_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_all_sources_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_all_sources_get(const stmdev_ctx_t *ctx, lsm6dsox_all_sources_t *val) { lsm6dsox_emb_func_status_mainpage_t emb_func_status_mainpage; @@ -12857,24 +12868,24 @@ int32_t lsm6dsox_all_sources_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, +int32_t lsm6dsox_mode_set(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dsox_md_t *val) { lsm6dsox_func_cfg_access_t func_cfg_access; - lsm6dsox_spi2_ctrl1_ois_t spi2_ctrl1_ois; - lsm6dsox_spi2_ctrl2_ois_t spi2_ctrl2_ois; - lsm6dsox_spi2_ctrl3_ois_t spi2_ctrl3_ois; - lsm6dsox_ui_ctrl1_ois_t ui_ctrl1_ois; - lsm6dsox_ui_ctrl2_ois_t ui_ctrl2_ois; - lsm6dsox_ui_ctrl3_ois_t ui_ctrl3_ois; - lsm6dsox_ctrl1_xl_t ctrl1_xl; - lsm6dsox_ctrl8_xl_t ctrl8_xl; - lsm6dsox_ctrl2_g_t ctrl2_g; - lsm6dsox_ctrl3_c_t ctrl3_c; - lsm6dsox_ctrl4_c_t ctrl4_c; - lsm6dsox_ctrl5_c_t ctrl5_c; - lsm6dsox_ctrl6_c_t ctrl6_c; - lsm6dsox_ctrl7_g_t ctrl7_g; + lsm6dsox_spi2_ctrl1_ois_t spi2_ctrl1_ois = {0}; + lsm6dsox_spi2_ctrl2_ois_t spi2_ctrl2_ois = {0}; + lsm6dsox_spi2_ctrl3_ois_t spi2_ctrl3_ois = {0}; + lsm6dsox_ui_ctrl1_ois_t ui_ctrl1_ois = {0}; + lsm6dsox_ui_ctrl2_ois_t ui_ctrl2_ois = {0}; + lsm6dsox_ui_ctrl3_ois_t ui_ctrl3_ois = {0}; + lsm6dsox_ctrl1_xl_t ctrl1_xl = {0}; + lsm6dsox_ctrl8_xl_t ctrl8_xl = {0}; + lsm6dsox_ctrl2_g_t ctrl2_g = {0}; + lsm6dsox_ctrl3_c_t ctrl3_c = {0}; + lsm6dsox_ctrl4_c_t ctrl4_c = {0}; + lsm6dsox_ctrl5_c_t ctrl5_c = {0}; + lsm6dsox_ctrl6_c_t ctrl6_c = {0}; + lsm6dsox_ctrl7_g_t ctrl7_g = {0}; uint8_t xl_hm_mode; uint8_t g_hm_mode; uint8_t xl_ulp_en; @@ -12970,7 +12981,7 @@ int32_t lsm6dsox_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, { switch (val->fsm.odr) { - case LSM6DSOX_FSM_12Hz5: + case LSM6DSOX_ODR_FSM_12Hz5: if ((val->fsm.sens != LSM6DSOX_FSM_GY) && (odr_xl == 0x00U)) { odr_xl = 0x01U; @@ -12984,7 +12995,7 @@ int32_t lsm6dsox_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, break; - case LSM6DSOX_FSM_26Hz: + case LSM6DSOX_ODR_FSM_26Hz: if ((val->fsm.sens != LSM6DSOX_FSM_GY) && (odr_xl < 0x02U)) { odr_xl = 0x02U; @@ -12998,7 +13009,7 @@ int32_t lsm6dsox_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, break; - case LSM6DSOX_FSM_52Hz: + case LSM6DSOX_ODR_FSM_52Hz: if ((val->fsm.sens != LSM6DSOX_FSM_GY) && (odr_xl < 0x03U)) { odr_xl = 0x03U; @@ -13012,7 +13023,7 @@ int32_t lsm6dsox_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, break; - case LSM6DSOX_FSM_104Hz: + case LSM6DSOX_ODR_FSM_104Hz: if ((val->fsm.sens != LSM6DSOX_FSM_GY) && (odr_xl < 0x04U)) { odr_xl = 0x04U; @@ -13038,7 +13049,7 @@ int32_t lsm6dsox_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, { switch (val->mlc.odr) { - case LSM6DSOX_MLC_12Hz5: + case LSM6DSOX_ODR_PRGS_12Hz5: if (odr_xl == 0x00U) { odr_xl = 0x01U; @@ -13052,7 +13063,7 @@ int32_t lsm6dsox_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, break; - case LSM6DSOX_MLC_26Hz: + case LSM6DSOX_ODR_PRGS_26Hz: if (odr_xl < 0x02U) { odr_xl = 0x02U; @@ -13066,7 +13077,7 @@ int32_t lsm6dsox_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, break; - case LSM6DSOX_MLC_52Hz: + case LSM6DSOX_ODR_PRGS_52Hz: if (odr_xl < 0x03U) { odr_xl = 0x03U; @@ -13080,7 +13091,7 @@ int32_t lsm6dsox_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, break; - case LSM6DSOX_MLC_104Hz: + case LSM6DSOX_ODR_PRGS_104Hz: if (odr_xl < 0x04U) { odr_xl = 0x04U; @@ -13409,7 +13420,7 @@ int32_t lsm6dsox_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, +int32_t lsm6dsox_mode_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dsox_md_t *val) { lsm6dsox_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; @@ -13749,24 +13760,24 @@ int32_t lsm6dsox_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, { switch (emb_func_odr_cfg_b.fsm_odr) { - case LSM6DSOX_FSM_12Hz5: - val->fsm.odr = LSM6DSOX_FSM_12Hz5; + case LSM6DSOX_ODR_FSM_12Hz5: + val->fsm.odr = LSM6DSOX_ODR_FSM_12Hz5; break; - case LSM6DSOX_FSM_26Hz: - val->fsm.odr = LSM6DSOX_FSM_26Hz; + case LSM6DSOX_ODR_FSM_26Hz: + val->fsm.odr = LSM6DSOX_ODR_FSM_26Hz; break; - case LSM6DSOX_FSM_52Hz: - val->fsm.odr = LSM6DSOX_FSM_52Hz; + case LSM6DSOX_ODR_FSM_52Hz: + val->fsm.odr = LSM6DSOX_ODR_FSM_52Hz; break; - case LSM6DSOX_FSM_104Hz: - val->fsm.odr = LSM6DSOX_FSM_104Hz; + case LSM6DSOX_ODR_FSM_104Hz: + val->fsm.odr = LSM6DSOX_ODR_FSM_104Hz; break; default: - val->fsm.odr = LSM6DSOX_FSM_12Hz5; + val->fsm.odr = LSM6DSOX_ODR_FSM_12Hz5; break; } @@ -13793,24 +13804,24 @@ int32_t lsm6dsox_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, { switch (emb_func_odr_cfg_c.mlc_odr) { - case LSM6DSOX_MLC_12Hz5: - val->mlc.odr = LSM6DSOX_MLC_12Hz5; + case LSM6DSOX_ODR_PRGS_12Hz5: + val->mlc.odr = LSM6DSOX_ODR_PRGS_12Hz5; break; - case LSM6DSOX_MLC_26Hz: - val->mlc.odr = LSM6DSOX_MLC_26Hz; + case LSM6DSOX_ODR_PRGS_26Hz: + val->mlc.odr = LSM6DSOX_ODR_PRGS_26Hz; break; - case LSM6DSOX_MLC_52Hz: - val->mlc.odr = LSM6DSOX_MLC_52Hz; + case LSM6DSOX_ODR_PRGS_52Hz: + val->mlc.odr = LSM6DSOX_ODR_PRGS_52Hz; break; - case LSM6DSOX_MLC_104Hz: - val->mlc.odr = LSM6DSOX_MLC_104Hz; + case LSM6DSOX_ODR_PRGS_104Hz: + val->mlc.odr = LSM6DSOX_ODR_PRGS_104Hz; break; default: - val->mlc.odr = LSM6DSOX_MLC_12Hz5; + val->mlc.odr = LSM6DSOX_ODR_PRGS_12Hz5; break; } @@ -14103,7 +14114,7 @@ int32_t lsm6dsox_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_data_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, +int32_t lsm6dsox_data_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dsox_md_t *md, lsm6dsox_data_t *data) { uint8_t buff[14]; @@ -14299,7 +14310,7 @@ int32_t lsm6dsox_data_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_embedded_sens_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_embedded_sens_set(const stmdev_ctx_t *ctx, lsm6dsox_emb_sens_t *val) { lsm6dsox_emb_func_en_a_t emb_func_en_a; @@ -14355,7 +14366,7 @@ int32_t lsm6dsox_embedded_sens_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_embedded_sens_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_embedded_sens_get(const stmdev_ctx_t *ctx, lsm6dsox_emb_sens_t *emb_sens) { lsm6dsox_emb_func_en_a_t emb_func_en_a; @@ -14399,7 +14410,7 @@ int32_t lsm6dsox_embedded_sens_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsox_embedded_sens_off(stmdev_ctx_t *ctx) +int32_t lsm6dsox_embedded_sens_off(const stmdev_ctx_t *ctx) { lsm6dsox_emb_func_en_a_t emb_func_en_a; lsm6dsox_emb_func_en_b_t emb_func_en_b; diff --git a/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.h b/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.h index 145b6bb4..c492cc7e 100644 --- a/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.h +++ b/sensor/stmemsc/lsm6dsox_STdC/driver/lsm6dsox_reg.h @@ -186,11 +186,9 @@ typedef struct #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t ois_ctrl_from_ui : 1; uint8_t not_used_01 : 5; -uint8_t reg_access : - 2; /* shub_reg_access + func_cfg_access */ + uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */ #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN -uint8_t reg_access : - 2; /* shub_reg_access + func_cfg_access */ + uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */ uint8_t not_used_01 : 5; uint8_t ois_ctrl_from_ui : 1; #endif /* DRV_BYTE_ORDER */ @@ -472,11 +470,9 @@ typedef struct uint8_t ftype : 3; uint8_t usr_off_w : 1; uint8_t xl_hm_mode : 1; -uint8_t den_mode : - 3; /* trig_en + lvl1_en + lvl2_en */ + uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN -uint8_t den_mode : - 3; /* trig_en + lvl1_en + lvl2_en */ + uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ uint8_t xl_hm_mode : 1; uint8_t usr_off_w : 1; uint8_t ftype : 3; @@ -1673,13 +1669,11 @@ typedef struct typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN -uint8_t fsm_lc_clr : - 2; /* fsm_lc_cleared + fsm_lc_clear */ + uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ uint8_t not_used_01 : 6; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN uint8_t not_used_01 : 6; -uint8_t fsm_lc_clr : - 2; /* fsm_lc_cleared + fsm_lc_clear */ + uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ #endif /* DRV_BYTE_ORDER */ } lsm6dsox_fsm_long_counter_clear_t; @@ -3022,10 +3016,10 @@ typedef union * them with a custom implementation. */ -int32_t lsm6dsox_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm6dsox_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lsm6dsox_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm6dsox_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -3051,9 +3045,9 @@ typedef enum LSM6DSOX_4g = 2, LSM6DSOX_8g = 3, } lsm6dsox_fs_xl_t; -int32_t lsm6dsox_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsox_fs_xl_t val); -int32_t lsm6dsox_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsox_fs_xl_t *val); typedef enum @@ -3071,9 +3065,9 @@ typedef enum LSM6DSOX_XL_ODR_6667Hz = 10, LSM6DSOX_XL_ODR_1Hz6 = 11, /* (low power only) */ } lsm6dsox_odr_xl_t; -int32_t lsm6dsox_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsox_odr_xl_t val); -int32_t lsm6dsox_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsox_odr_xl_t *val); typedef enum @@ -3084,9 +3078,9 @@ typedef enum LSM6DSOX_1000dps = 4, LSM6DSOX_2000dps = 6, } lsm6dsox_fs_g_t; -int32_t lsm6dsox_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsox_fs_g_t val); -int32_t lsm6dsox_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsox_fs_g_t *val); typedef enum @@ -3103,14 +3097,14 @@ typedef enum LSM6DSOX_GY_ODR_3333Hz = 9, LSM6DSOX_GY_ODR_6667Hz = 10, } lsm6dsox_odr_g_t; -int32_t lsm6dsox_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_gy_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsox_odr_g_t val); -int32_t lsm6dsox_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsox_odr_g_t *val); -int32_t lsm6dsox_block_data_update_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3118,9 +3112,9 @@ typedef enum LSM6DSOX_LSb_1mg = 0, LSM6DSOX_LSb_16mg = 1, } lsm6dsox_usr_off_w_t; -int32_t lsm6dsox_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_offset_weight_set(const stmdev_ctx_t *ctx, lsm6dsox_usr_off_w_t val); -int32_t lsm6dsox_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_offset_weight_get(const stmdev_ctx_t *ctx, lsm6dsox_usr_off_w_t *val); typedef enum @@ -3129,9 +3123,9 @@ typedef enum LSM6DSOX_LOW_NORMAL_POWER_MD = 1, LSM6DSOX_ULTRA_LOW_POWER_MD = 2, } lsm6dsox_xl_hm_mode_t; -int32_t lsm6dsox_xl_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_power_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_xl_hm_mode_t val); -int32_t lsm6dsox_xl_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_power_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_xl_hm_mode_t *val); typedef enum @@ -3139,47 +3133,47 @@ typedef enum LSM6DSOX_GY_HIGH_PERFORMANCE = 0, LSM6DSOX_GY_NORMAL = 1, } lsm6dsox_g_hm_mode_t; -int32_t lsm6dsox_gy_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_gy_power_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_g_hm_mode_t val); -int32_t lsm6dsox_gy_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_gy_power_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_g_hm_mode_t *val); -int32_t lsm6dsox_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_status_reg_get(const stmdev_ctx_t *ctx, lsm6dsox_status_reg_t *val); -int32_t lsm6dsox_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_xl_usr_offset_x_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsox_xl_usr_offset_x_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsox_xl_usr_offset_y_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsox_xl_usr_offset_y_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsox_xl_usr_offset_z_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsox_xl_usr_offset_z_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsox_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_timestamp_rst(stmdev_ctx_t *ctx); +int32_t lsm6dsox_timestamp_rst(const stmdev_ctx_t *ctx); -int32_t lsm6dsox_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); +int32_t lsm6dsox_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); typedef enum { @@ -3188,9 +3182,9 @@ typedef enum LSM6DSOX_ROUND_GY = 2, LSM6DSOX_ROUND_GY_XL = 3, } lsm6dsox_rounding_t; -int32_t lsm6dsox_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_rounding_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_rounding_t val); -int32_t lsm6dsox_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_rounding_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_rounding_t *val); typedef enum @@ -3198,45 +3192,45 @@ typedef enum LSM6DSOX_STAT_RND_DISABLE = 0, LSM6DSOX_STAT_RND_ENABLE = 1, } lsm6dsox_rounding_status_t; -int32_t lsm6dsox_rounding_on_status_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_rounding_on_status_set(const stmdev_ctx_t *ctx, lsm6dsox_rounding_status_t val); -int32_t lsm6dsox_rounding_on_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_rounding_on_status_get(const stmdev_ctx_t *ctx, lsm6dsox_rounding_status_t *val); -int32_t lsm6dsox_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsox_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsox_angular_rate_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsox_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsox_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsox_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsox_ois_angular_rate_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_ois_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsox_ois_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_ois_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsox_aux_temperature_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsox_aux_ois_angular_rate_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_ois_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsox_aux_ois_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_ois_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsox_number_of_steps_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_number_of_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsox_steps_reset(stmdev_ctx_t *ctx); +int32_t lsm6dsox_steps_reset(const stmdev_ctx_t *ctx); -int32_t lsm6dsox_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsox_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsox_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3244,19 +3238,19 @@ typedef enum LSM6DSOX_SENSOR_HUB_BANK = 1, LSM6DSOX_EMBEDDED_FUNC_BANK = 2, } lsm6dsox_reg_access_t; -int32_t lsm6dsox_mem_bank_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dsox_reg_access_t val); -int32_t lsm6dsox_mem_bank_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dsox_reg_access_t *val); -int32_t lsm6dsox_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dsox_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val); -int32_t lsm6dsox_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dsox_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val); -int32_t lsm6dsox_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dsox_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); -int32_t lsm6dsox_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dsox_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val); typedef enum @@ -3264,21 +3258,21 @@ typedef enum LSM6DSOX_DRDY_LATCHED = 0, LSM6DSOX_DRDY_PULSED = 1, } lsm6dsox_dataready_pulsed_t; -int32_t lsm6dsox_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_dataready_pulsed_t val); -int32_t lsm6dsox_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_dataready_pulsed_t *val); -int32_t lsm6dsox_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsox_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsox_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3286,9 +3280,9 @@ typedef enum LSM6DSOX_XL_ST_POSITIVE = 1, LSM6DSOX_XL_ST_NEGATIVE = 2, } lsm6dsox_st_xl_t; -int32_t lsm6dsox_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dsox_st_xl_t val); -int32_t lsm6dsox_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dsox_st_xl_t *val); typedef enum @@ -3297,20 +3291,20 @@ typedef enum LSM6DSOX_GY_ST_POSITIVE = 1, LSM6DSOX_GY_ST_NEGATIVE = 3, } lsm6dsox_st_g_t; -int32_t lsm6dsox_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dsox_st_g_t val); -int32_t lsm6dsox_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dsox_st_g_t *val); -int32_t lsm6dsox_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3324,13 +3318,13 @@ typedef enum LSM6DSOX_AGGRESSIVE = 6, LSM6DSOX_XTREME = 7, } lsm6dsox_ftype_t; -int32_t lsm6dsox_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsox_ftype_t val); -int32_t lsm6dsox_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsox_ftype_t *val); -int32_t lsm6dsox_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3358,13 +3352,13 @@ typedef enum LSM6DSOX_LP_ODR_DIV_400 = 0x06, LSM6DSOX_LP_ODR_DIV_800 = 0x07, } lsm6dsox_hp_slope_xl_en_t; -int32_t lsm6dsox_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, lsm6dsox_hp_slope_xl_en_t val); -int32_t lsm6dsox_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, lsm6dsox_hp_slope_xl_en_t *val); -int32_t lsm6dsox_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_xl_fast_settling_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3372,9 +3366,9 @@ typedef enum LSM6DSOX_USE_SLOPE = 0, LSM6DSOX_USE_HPF = 1, } lsm6dsox_slope_fds_t; -int32_t lsm6dsox_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dsox_slope_fds_t val); -int32_t lsm6dsox_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dsox_slope_fds_t *val); typedef enum @@ -3385,9 +3379,9 @@ typedef enum LSM6DSOX_HP_FILTER_260mHz = 0x82, LSM6DSOX_HP_FILTER_1Hz04 = 0x83, } lsm6dsox_hpm_g_t; -int32_t lsm6dsox_gy_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dsox_hpm_g_t val); -int32_t lsm6dsox_gy_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dsox_hpm_g_t *val); typedef enum @@ -3397,9 +3391,9 @@ typedef enum LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI = 0x02, LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI_AUX = 0x03, } lsm6dsox_spi2_read_en_t; -int32_t lsm6dsox_ois_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_ois_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_spi2_read_en_t val); -int32_t lsm6dsox_ois_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_ois_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_spi2_read_en_t *val); typedef enum @@ -3407,9 +3401,9 @@ typedef enum LSM6DSOX_AUX_PULL_UP_DISC = 0, LSM6DSOX_AUX_PULL_UP_CONNECT = 1, } lsm6dsox_ois_pu_dis_t; -int32_t lsm6dsox_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_sdo_ocs_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_ois_pu_dis_t val); -int32_t lsm6dsox_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_sdo_ocs_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_ois_pu_dis_t *val); typedef enum @@ -3417,9 +3411,9 @@ typedef enum LSM6DSOX_AUX_ON = 1, LSM6DSOX_AUX_ON_BY_AUX_INTERFACE = 0, } lsm6dsox_ois_on_t; -int32_t lsm6dsox_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_pw_on_ctrl_set(const stmdev_ctx_t *ctx, lsm6dsox_ois_on_t val); -int32_t lsm6dsox_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_pw_on_ctrl_get(const stmdev_ctx_t *ctx, lsm6dsox_ois_on_t *val); typedef enum @@ -3427,21 +3421,21 @@ typedef enum LSM6DSOX_USE_SAME_XL_FS = 0, LSM6DSOX_USE_DIFFERENT_XL_FS = 1, } lsm6dsox_xl_fs_mode_t; -int32_t lsm6dsox_aux_xl_fs_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_xl_fs_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_xl_fs_mode_t val); -int32_t lsm6dsox_aux_xl_fs_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_xl_fs_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_xl_fs_mode_t *val); -int32_t lsm6dsox_aux_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_status_reg_get(const stmdev_ctx_t *ctx, lsm6dsox_spi2_status_reg_ois_t *val); -int32_t lsm6dsox_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3449,9 +3443,9 @@ typedef enum LSM6DSOX_AUX_DEN_ACTIVE_LOW = 0, LSM6DSOX_AUX_DEN_ACTIVE_HIGH = 1, } lsm6dsox_den_lh_ois_t; -int32_t lsm6dsox_aux_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dsox_den_lh_ois_t val); -int32_t lsm6dsox_aux_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dsox_den_lh_ois_t *val); typedef enum @@ -3460,13 +3454,13 @@ typedef enum LSM6DSOX_AUX_DEN_LEVEL_LATCH = 3, LSM6DSOX_AUX_DEN_LEVEL_TRIG = 2, } lsm6dsox_lvl2_ois_t; -int32_t lsm6dsox_aux_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_den_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_lvl2_ois_t val); -int32_t lsm6dsox_aux_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_den_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_lvl2_ois_t *val); -int32_t lsm6dsox_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3475,9 +3469,9 @@ typedef enum LSM6DSOX_MODE_3_GY = 1, LSM6DSOX_MODE_4_GY_XL = 3, } lsm6dsox_ois_en_spi2_t; -int32_t lsm6dsox_aux_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_ois_en_spi2_t val); -int32_t lsm6dsox_aux_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_ois_en_spi2_t *val); typedef enum @@ -3488,9 +3482,9 @@ typedef enum LSM6DSOX_1000dps_AUX = 4, LSM6DSOX_2000dps_AUX = 6, } lsm6dsox_fs_g_ois_t; -int32_t lsm6dsox_aux_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsox_fs_g_ois_t val); -int32_t lsm6dsox_aux_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsox_fs_g_ois_t *val); typedef enum @@ -3498,9 +3492,9 @@ typedef enum LSM6DSOX_AUX_SPI_4_WIRE = 0, LSM6DSOX_AUX_SPI_3_WIRE = 1, } lsm6dsox_sim_ois_t; -int32_t lsm6dsox_aux_spi_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_sim_ois_t val); -int32_t lsm6dsox_aux_spi_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_sim_ois_t *val); typedef enum @@ -3510,9 +3504,9 @@ typedef enum LSM6DSOX_172Hz70 = 2, LSM6DSOX_937Hz91 = 3, } lsm6dsox_ftype_ois_t; -int32_t lsm6dsox_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsox_ftype_ois_t val); -int32_t lsm6dsox_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsox_ftype_ois_t *val); typedef enum @@ -3523,9 +3517,9 @@ typedef enum LSM6DSOX_AUX_HP_Hz260 = 0x12, LSM6DSOX_AUX_HP_1Hz040 = 0x13, } lsm6dsox_hpm_ois_t; -int32_t lsm6dsox_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_gy_hp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsox_hpm_ois_t val); -int32_t lsm6dsox_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_gy_hp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsox_hpm_ois_t *val); typedef enum @@ -3533,9 +3527,9 @@ typedef enum LSM6DSOX_ENABLE_CLAMP = 0, LSM6DSOX_DISABLE_CLAMP = 1, } lsm6dsox_st_ois_clampdis_t; -int32_t lsm6dsox_aux_gy_clamp_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_gy_clamp_set(const stmdev_ctx_t *ctx, lsm6dsox_st_ois_clampdis_t val); -int32_t lsm6dsox_aux_gy_clamp_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_gy_clamp_get(const stmdev_ctx_t *ctx, lsm6dsox_st_ois_clampdis_t *val); typedef enum @@ -3549,9 +3543,9 @@ typedef enum LSM6DSOX_8Hz30 = 6, LSM6DSOX_4Hz15 = 7, } lsm6dsox_filter_xl_conf_ois_t; -int32_t lsm6dsox_aux_xl_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_xl_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsox_filter_xl_conf_ois_t val); -int32_t lsm6dsox_aux_xl_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_xl_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsox_filter_xl_conf_ois_t *val); typedef enum @@ -3561,9 +3555,9 @@ typedef enum LSM6DSOX_AUX_4g = 2, LSM6DSOX_AUX_8g = 3, } lsm6dsox_fs_xl_ois_t; -int32_t lsm6dsox_aux_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsox_fs_xl_ois_t val); -int32_t lsm6dsox_aux_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_aux_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsox_fs_xl_ois_t *val); typedef enum @@ -3571,9 +3565,9 @@ typedef enum LSM6DSOX_PULL_UP_DISC = 0, LSM6DSOX_PULL_UP_CONNECT = 1, } lsm6dsox_sdo_pu_en_t; -int32_t lsm6dsox_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_sdo_pu_en_t val); -int32_t lsm6dsox_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_sdo_pu_en_t *val); typedef enum @@ -3581,17 +3575,17 @@ typedef enum LSM6DSOX_SPI_4_WIRE = 0, LSM6DSOX_SPI_3_WIRE = 1, } lsm6dsox_sim_t; -int32_t lsm6dsox_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsox_sim_t val); -int32_t lsm6dsox_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsox_sim_t *val); +int32_t lsm6dsox_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_sim_t val); +int32_t lsm6dsox_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_sim_t *val); typedef enum { LSM6DSOX_I2C_ENABLE = 0, LSM6DSOX_I2C_DISABLE = 1, } lsm6dsox_i2c_disable_t; -int32_t lsm6dsox_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_i2c_interface_set(const stmdev_ctx_t *ctx, lsm6dsox_i2c_disable_t val); -int32_t lsm6dsox_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_i2c_interface_get(const stmdev_ctx_t *ctx, lsm6dsox_i2c_disable_t *val); typedef enum @@ -3602,9 +3596,9 @@ typedef enum LSM6DSOX_I3C_ENABLE_T_1ms = 0x02, LSM6DSOX_I3C_ENABLE_T_25ms = 0x03, } lsm6dsox_i3c_disable_t; -int32_t lsm6dsox_i3c_disable_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_i3c_disable_set(const stmdev_ctx_t *ctx, lsm6dsox_i3c_disable_t val); -int32_t lsm6dsox_i3c_disable_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_i3c_disable_get(const stmdev_ctx_t *ctx, lsm6dsox_i3c_disable_t *val); typedef enum @@ -3614,9 +3608,9 @@ typedef enum LSM6DSOX_INT1_NOPULL_DOWN_INT2_PUSH_PULL = 0x02, LSM6DSOX_INT1_NOPULL_DOWN_INT2_OPEN_DRAIN = 0x03, } lsm6dsox_pp_od_t; -int32_t lsm6dsox_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_pp_od_t val); -int32_t lsm6dsox_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_pp_od_t *val); typedef enum @@ -3624,13 +3618,13 @@ typedef enum LSM6DSOX_ACTIVE_HIGH = 0, LSM6DSOX_ACTIVE_LOW = 1, } lsm6dsox_h_lactive_t; -int32_t lsm6dsox_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pin_polarity_set(const stmdev_ctx_t *ctx, lsm6dsox_h_lactive_t val); -int32_t lsm6dsox_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pin_polarity_get(const stmdev_ctx_t *ctx, lsm6dsox_h_lactive_t *val); -int32_t lsm6dsox_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3639,9 +3633,9 @@ typedef enum LSM6DSOX_BASE_PULSED_EMB_LATCHED = 2, LSM6DSOX_ALL_INT_LATCHED = 3, } lsm6dsox_lir_t; -int32_t lsm6dsox_int_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_int_notification_set(const stmdev_ctx_t *ctx, lsm6dsox_lir_t val); -int32_t lsm6dsox_int_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_int_notification_get(const stmdev_ctx_t *ctx, lsm6dsox_lir_t *val); typedef enum @@ -3649,33 +3643,33 @@ typedef enum LSM6DSOX_LSb_FS_DIV_64 = 0, LSM6DSOX_LSb_FS_DIV_256 = 1, } lsm6dsox_wake_ths_w_t; -int32_t lsm6dsox_wkup_ths_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_wkup_ths_weight_set(const stmdev_ctx_t *ctx, lsm6dsox_wake_ths_w_t val); -int32_t lsm6dsox_wkup_ths_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_wkup_ths_weight_get(const stmdev_ctx_t *ctx, lsm6dsox_wake_ths_w_t *val); -int32_t lsm6dsox_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSOX_DRIVE_SLEEP_CHG_EVENT = 0, LSM6DSOX_DRIVE_SLEEP_STATUS = 1, } lsm6dsox_sleep_status_on_int_t; -int32_t lsm6dsox_act_pin_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_act_pin_notification_set(const stmdev_ctx_t *ctx, lsm6dsox_sleep_status_on_int_t val); -int32_t lsm6dsox_act_pin_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_act_pin_notification_get(const stmdev_ctx_t *ctx, lsm6dsox_sleep_status_on_int_t *val); typedef enum @@ -3685,31 +3679,31 @@ typedef enum LSM6DSOX_XL_12Hz5_GY_SLEEP = 2, LSM6DSOX_XL_12Hz5_GY_PD = 3, } lsm6dsox_inact_en_t; -int32_t lsm6dsox_act_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_act_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_inact_en_t val); -int32_t lsm6dsox_act_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_act_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_inact_en_t *val); -int32_t lsm6dsox_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3720,34 +3714,34 @@ typedef enum LSM6DSOX_YZX = 5, LSM6DSOX_ZXY = 6, } lsm6dsox_tap_priority_t; -int32_t lsm6dsox_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_tap_axis_priority_set(const stmdev_ctx_t *ctx, lsm6dsox_tap_priority_t val); -int32_t lsm6dsox_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_tap_axis_priority_get(const stmdev_ctx_t *ctx, lsm6dsox_tap_priority_t *val); -int32_t lsm6dsox_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSOX_ONLY_SINGLE = 0, LSM6DSOX_BOTH_SINGLE_DOUBLE = 1, } lsm6dsox_single_double_tap_t; -int32_t lsm6dsox_tap_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_single_double_tap_t val); -int32_t lsm6dsox_tap_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_single_double_tap_t *val); typedef enum @@ -3757,13 +3751,13 @@ typedef enum LSM6DSOX_DEG_60 = 2, LSM6DSOX_DEG_50 = 3, } lsm6dsox_sixd_ths_t; -int32_t lsm6dsox_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_6d_threshold_set(const stmdev_ctx_t *ctx, lsm6dsox_sixd_ths_t val); -int32_t lsm6dsox_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_6d_threshold_get(const stmdev_ctx_t *ctx, lsm6dsox_sixd_ths_t *val); -int32_t lsm6dsox_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3776,20 +3770,20 @@ typedef enum LSM6DSOX_FF_TSH_469mg = 6, LSM6DSOX_FF_TSH_500mg = 7, } lsm6dsox_ff_ths_t; -int32_t lsm6dsox_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_ff_threshold_set(const stmdev_ctx_t *ctx, lsm6dsox_ff_ths_t val); -int32_t lsm6dsox_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_ff_threshold_get(const stmdev_ctx_t *ctx, lsm6dsox_ff_ths_t *val); -int32_t lsm6dsox_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsox_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsox_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsox_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsox_compression_algo_init_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_compression_algo_init_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_compression_algo_init_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_compression_algo_init_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3800,23 +3794,23 @@ typedef enum LSM6DSOX_CMP_16_TO_1 = 0x06, LSM6DSOX_CMP_32_TO_1 = 0x07, } lsm6dsox_uncoptr_rate_t; -int32_t lsm6dsox_compression_algo_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_compression_algo_set(const stmdev_ctx_t *ctx, lsm6dsox_uncoptr_rate_t val); -int32_t lsm6dsox_compression_algo_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_compression_algo_get(const stmdev_ctx_t *ctx, lsm6dsox_uncoptr_rate_t *val); -int32_t lsm6dsox_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_compression_algo_real_time_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_compression_algo_real_time_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_compression_algo_real_time_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_compression_algo_real_time_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3834,9 +3828,9 @@ typedef enum LSM6DSOX_XL_BATCHED_AT_6667Hz = 10, LSM6DSOX_XL_BATCHED_AT_6Hz5 = 11, } lsm6dsox_bdr_xl_t; -int32_t lsm6dsox_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_xl_batch_set(const stmdev_ctx_t *ctx, lsm6dsox_bdr_xl_t val); -int32_t lsm6dsox_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_xl_batch_get(const stmdev_ctx_t *ctx, lsm6dsox_bdr_xl_t *val); typedef enum @@ -3854,9 +3848,9 @@ typedef enum LSM6DSOX_GY_BATCHED_AT_6667Hz = 10, LSM6DSOX_GY_BATCHED_AT_6Hz5 = 11, } lsm6dsox_bdr_gy_t; -int32_t lsm6dsox_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_gy_batch_set(const stmdev_ctx_t *ctx, lsm6dsox_bdr_gy_t val); -int32_t lsm6dsox_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_gy_batch_get(const stmdev_ctx_t *ctx, lsm6dsox_bdr_gy_t *val); typedef enum @@ -3868,9 +3862,9 @@ typedef enum LSM6DSOX_STREAM_MODE = 6, LSM6DSOX_BYPASS_TO_FIFO_MODE = 7, } lsm6dsox_fifo_mode_t; -int32_t lsm6dsox_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_fifo_mode_t val); -int32_t lsm6dsox_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_fifo_mode_t *val); typedef enum @@ -3880,9 +3874,9 @@ typedef enum LSM6DSOX_TEMP_BATCHED_AT_12Hz5 = 2, LSM6DSOX_TEMP_BATCHED_AT_52Hz = 3, } lsm6dsox_odr_t_batch_t; -int32_t lsm6dsox_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_temp_batch_set(const stmdev_ctx_t *ctx, lsm6dsox_odr_t_batch_t val); -int32_t lsm6dsox_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_temp_batch_get(const stmdev_ctx_t *ctx, lsm6dsox_odr_t_batch_t *val); typedef enum @@ -3892,9 +3886,9 @@ typedef enum LSM6DSOX_DEC_8 = 2, LSM6DSOX_DEC_32 = 3, } lsm6dsox_odr_ts_batch_t; -int32_t lsm6dsox_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, lsm6dsox_odr_ts_batch_t val); -int32_t lsm6dsox_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, lsm6dsox_odr_ts_batch_t *val); typedef enum @@ -3928,53 +3922,53 @@ typedef enum LSM6DSOX_ROTATION_TAG, LSM6DSOX_SENSORHUB_NACK_TAG = 0x19, } lsm6dsox_fifo_tag_t; -int32_t lsm6dsox_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, lsm6dsox_trig_counter_bdr_t val); -int32_t lsm6dsox_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, lsm6dsox_trig_counter_bdr_t *val); -int32_t lsm6dsox_rst_batch_counter_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_rst_batch_counter_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_batch_counter_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsox_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsox_fifo_data_level_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsox_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_status_get(const stmdev_ctx_t *ctx, lsm6dsox_fifo_status2_t *val); -int32_t lsm6dsox_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_fifo_sensor_tag_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, lsm6dsox_fifo_tag_t *val); -int32_t lsm6dsox_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_sh_batch_slave_0_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_sh_batch_slave_1_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_sh_batch_slave_2_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_sh_batch_slave_3_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3985,9 +3979,9 @@ typedef enum LSM6DSOX_LEVEL_TRIGGER = 2, LSM6DSOX_EDGE_TRIGGER = 4, } lsm6dsox_den_mode_t; -int32_t lsm6dsox_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_den_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_den_mode_t val); -int32_t lsm6dsox_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_den_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_den_mode_t *val); typedef enum @@ -3995,9 +3989,9 @@ typedef enum LSM6DSOX_DEN_ACT_LOW = 0, LSM6DSOX_DEN_ACT_HIGH = 1, } lsm6dsox_den_lh_t; -int32_t lsm6dsox_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dsox_den_lh_t val); -int32_t lsm6dsox_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dsox_den_lh_t *val); typedef enum @@ -4006,19 +4000,19 @@ typedef enum LSM6DSOX_STAMP_IN_XL_DATA = 1, LSM6DSOX_STAMP_IN_GY_XL_DATA = 2, } lsm6dsox_den_xl_g_t; -int32_t lsm6dsox_den_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_den_enable_set(const stmdev_ctx_t *ctx, lsm6dsox_den_xl_g_t val); -int32_t lsm6dsox_den_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_den_enable_get(const stmdev_ctx_t *ctx, lsm6dsox_den_xl_g_t *val); -int32_t lsm6dsox_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -4026,32 +4020,32 @@ typedef enum LSM6DSOX_FALSE_STEP_REJ = 0x10, LSM6DSOX_FALSE_STEP_REJ_ADV_MODE = 0x30, } lsm6dsox_pedo_md_t; -int32_t lsm6dsox_pedo_sens_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pedo_sens_set(const stmdev_ctx_t *ctx, lsm6dsox_pedo_md_t val); -int32_t lsm6dsox_pedo_sens_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pedo_sens_get(const stmdev_ctx_t *ctx, lsm6dsox_pedo_md_t *val); -int32_t lsm6dsox_pedo_step_detect_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pedo_step_detect_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_pedo_debounce_steps_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsox_pedo_debounce_steps_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsox_pedo_steps_period_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pedo_steps_period_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsox_pedo_steps_period_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pedo_steps_period_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsox_pedo_adv_detection_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pedo_adv_detection_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_pedo_adv_detection_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pedo_adv_detection_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_pedo_false_step_rejection_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pedo_false_step_rejection_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_pedo_false_step_rejection_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pedo_false_step_rejection_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -4059,32 +4053,32 @@ typedef enum LSM6DSOX_EVERY_STEP = 0, LSM6DSOX_COUNT_OVERFLOW = 1, } lsm6dsox_carry_count_en_t; -int32_t lsm6dsox_pedo_int_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pedo_int_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_carry_count_en_t val); -int32_t lsm6dsox_pedo_int_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pedo_int_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_carry_count_en_t *val); -int32_t lsm6dsox_motion_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_motion_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_sh_mag_sensitivity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsox_sh_mag_sensitivity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsox_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_mlc_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsox_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsox_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsox_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsox_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsox_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsox_mag_soft_iron_set(stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsox_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsox_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsox_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum { @@ -4095,9 +4089,9 @@ typedef enum LSM6DSOX_Z_EQ_MIN_Z = 4, LSM6DSOX_Z_EQ_Z = 5, } lsm6dsox_mag_z_axis_t; -int32_t lsm6dsox_mag_z_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_mag_z_orient_set(const stmdev_ctx_t *ctx, lsm6dsox_mag_z_axis_t val); -int32_t lsm6dsox_mag_z_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_mag_z_orient_get(const stmdev_ctx_t *ctx, lsm6dsox_mag_z_axis_t *val); typedef enum @@ -4109,9 +4103,9 @@ typedef enum LSM6DSOX_Y_EQ_MIN_Z = 4, LSM6DSOX_Y_EQ_Z = 5, } lsm6dsox_mag_y_axis_t; -int32_t lsm6dsox_mag_y_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_mag_y_orient_set(const stmdev_ctx_t *ctx, lsm6dsox_mag_y_axis_t val); -int32_t lsm6dsox_mag_y_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_mag_y_orient_get(const stmdev_ctx_t *ctx, lsm6dsox_mag_y_axis_t *val); typedef enum @@ -4123,12 +4117,12 @@ typedef enum LSM6DSOX_X_EQ_MIN_Z = 4, LSM6DSOX_X_EQ_Z = 5, } lsm6dsox_mag_x_axis_t; -int32_t lsm6dsox_mag_x_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_mag_x_orient_set(const stmdev_ctx_t *ctx, lsm6dsox_mag_x_axis_t val); -int32_t lsm6dsox_mag_x_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_mag_x_orient_get(const stmdev_ctx_t *ctx, lsm6dsox_mag_x_axis_t *val); -int32_t lsm6dsox_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct @@ -4136,13 +4130,13 @@ typedef struct lsm6dsox_fsm_enable_a_t fsm_enable_a; lsm6dsox_fsm_enable_b_t fsm_enable_b; } lsm6dsox_emb_fsm_enable_t; -int32_t lsm6dsox_fsm_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fsm_enable_set(const stmdev_ctx_t *ctx, lsm6dsox_emb_fsm_enable_t *val); -int32_t lsm6dsox_fsm_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fsm_enable_get(const stmdev_ctx_t *ctx, lsm6dsox_emb_fsm_enable_t *val); -int32_t lsm6dsox_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsox_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsox_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsox_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum { @@ -4150,9 +4144,9 @@ typedef enum LSM6DSOX_LC_CLEAR = 1, LSM6DSOX_LC_CLEAR_DONE = 2, } lsm6dsox_fsm_lc_clr_t; -int32_t lsm6dsox_long_clr_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_long_clr_set(const stmdev_ctx_t *ctx, lsm6dsox_fsm_lc_clr_t val); -int32_t lsm6dsox_long_clr_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_long_clr_get(const stmdev_ctx_t *ctx, lsm6dsox_fsm_lc_clr_t *val); typedef struct @@ -4174,7 +4168,7 @@ typedef struct lsm6dsox_fsm_outs7_t fsm_outs15; lsm6dsox_fsm_outs8_t fsm_outs16; } lsm6dsox_fsm_out_t; -int32_t lsm6dsox_fsm_out_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dsox_fsm_out_t *val); typedef enum @@ -4184,30 +4178,30 @@ typedef enum LSM6DSOX_ODR_FSM_52Hz = 2, LSM6DSOX_ODR_FSM_104Hz = 3, } lsm6dsox_fsm_odr_t; -int32_t lsm6dsox_fsm_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fsm_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsox_fsm_odr_t val); -int32_t lsm6dsox_fsm_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fsm_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsox_fsm_odr_t *val); -int32_t lsm6dsox_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_long_cnt_int_value_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsox_long_cnt_int_value_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsox_fsm_number_of_programs_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_fsm_number_of_programs_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_fsm_start_address_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsox_fsm_start_address_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsox_mlc_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_mlc_status_get(const stmdev_ctx_t *ctx, lsm6dsox_mlc_status_mainpage_t *val); typedef enum @@ -4217,9 +4211,9 @@ typedef enum LSM6DSOX_ODR_PRGS_52Hz = 2, LSM6DSOX_ODR_PRGS_104Hz = 3, } lsm6dsox_mlc_odr_t; -int32_t lsm6dsox_mlc_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_mlc_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsox_mlc_odr_t val); -int32_t lsm6dsox_mlc_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_mlc_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsox_mlc_odr_t *val); typedef struct @@ -4243,7 +4237,7 @@ typedef struct lsm6dsox_sensor_hub_17_t sh_byte_17; lsm6dsox_sensor_hub_18_t sh_byte_18; } lsm6dsox_emb_sh_read_t; -int32_t lsm6dsox_sh_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_read_data_raw_get(const stmdev_ctx_t *ctx, lsm6dsox_emb_sh_read_t *val, uint8_t len); @@ -4254,35 +4248,35 @@ typedef enum LSM6DSOX_SLV_0_1_2 = 2, LSM6DSOX_SLV_0_1_2_3 = 3, } lsm6dsox_aux_sens_on_t; -int32_t lsm6dsox_sh_slave_connected_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_slave_connected_set(const stmdev_ctx_t *ctx, lsm6dsox_aux_sens_on_t val); -int32_t lsm6dsox_sh_slave_connected_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_slave_connected_get(const stmdev_ctx_t *ctx, lsm6dsox_aux_sens_on_t *val); -int32_t lsm6dsox_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSOX_EXT_PULL_UP = 0, LSM6DSOX_INTERNAL_PULL_UP = 1, } lsm6dsox_shub_pu_en_t; -int32_t lsm6dsox_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_shub_pu_en_t val); -int32_t lsm6dsox_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_shub_pu_en_t *val); -int32_t lsm6dsox_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSOX_EXT_ON_INT2_PIN = 1, LSM6DSOX_XL_GY_DRDY = 0, } lsm6dsox_start_config_t; -int32_t lsm6dsox_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_syncro_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_start_config_t val); -int32_t lsm6dsox_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_syncro_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_start_config_t *val); typedef enum @@ -4290,13 +4284,13 @@ typedef enum LSM6DSOX_EACH_SH_CYCLE = 0, LSM6DSOX_ONLY_FIRST_CYCLE = 1, } lsm6dsox_write_once_t; -int32_t lsm6dsox_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_write_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_write_once_t val); -int32_t lsm6dsox_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_write_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_write_once_t *val); -int32_t lsm6dsox_sh_reset_set(stmdev_ctx_t *ctx); -int32_t lsm6dsox_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_sh_reset_set(const stmdev_ctx_t *ctx); +int32_t lsm6dsox_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -4305,9 +4299,9 @@ typedef enum LSM6DSOX_SH_ODR_26Hz = 2, LSM6DSOX_SH_ODR_13Hz = 3, } lsm6dsox_shub_odr_t; -int32_t lsm6dsox_sh_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsox_shub_odr_t val); -int32_t lsm6dsox_sh_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsox_shub_odr_t *val); typedef struct @@ -4316,7 +4310,7 @@ typedef struct uint8_t slv0_subadd; uint8_t slv0_data; } lsm6dsox_sh_cfg_write_t; -int32_t lsm6dsox_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_cfg_write(const stmdev_ctx_t *ctx, lsm6dsox_sh_cfg_write_t *val); typedef struct @@ -4325,29 +4319,29 @@ typedef struct uint8_t slv_subadd; uint8_t slv_len; } lsm6dsox_sh_cfg_read_t; -int32_t lsm6dsox_sh_slv0_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, lsm6dsox_sh_cfg_read_t *val); -int32_t lsm6dsox_sh_slv1_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, lsm6dsox_sh_cfg_read_t *val); -int32_t lsm6dsox_sh_slv2_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, lsm6dsox_sh_cfg_read_t *val); -int32_t lsm6dsox_sh_slv3_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, lsm6dsox_sh_cfg_read_t *val); -int32_t lsm6dsox_sh_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_sh_status_get(const stmdev_ctx_t *ctx, lsm6dsox_status_master_t *val); typedef enum { LSM6DSOX_S4S_TPH_7bit = 0, LSM6DSOX_S4S_TPH_15bit = 1, } lsm6dsox_s4s_tph_res_t; -int32_t lsm6dsox_s4s_tph_res_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_s4s_tph_res_set(const stmdev_ctx_t *ctx, lsm6dsox_s4s_tph_res_t val); -int32_t lsm6dsox_s4s_tph_res_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_s4s_tph_res_get(const stmdev_ctx_t *ctx, lsm6dsox_s4s_tph_res_t *val); -int32_t lsm6dsox_s4s_tph_val_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsox_s4s_tph_val_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsox_s4s_tph_val_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsox_s4s_tph_val_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum { @@ -4356,48 +4350,52 @@ typedef enum LSM6DSOX_S4S_DT_RES_13 = 2, LSM6DSOX_S4S_DT_RES_14 = 3, } lsm6dsox_s4s_res_ratio_t; -int32_t lsm6dsox_s4s_res_ratio_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_s4s_res_ratio_set(const stmdev_ctx_t *ctx, lsm6dsox_s4s_res_ratio_t val); -int32_t lsm6dsox_s4s_res_ratio_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_s4s_res_ratio_get(const stmdev_ctx_t *ctx, lsm6dsox_s4s_res_ratio_t *val); -int32_t lsm6dsox_s4s_command_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_s4s_command_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_s4s_command_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_s4s_command_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsox_s4s_dt_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsox_s4s_dt_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsox_s4s_dt_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsox_s4s_dt_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { uint8_t ui; uint8_t aux; } lsm6dsox_id_t; -int32_t lsm6dsox_id_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, +int32_t lsm6dsox_id_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dsox_id_t *val); +typedef enum +{ + LSM6DSOX_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */ + LSM6DSOX_SPI_4W = 0x06, /* Only SPI: SDO / SDI separated pins */ + LSM6DSOX_SPI_3W = 0x07, /* Only SPI: SDO / SDI share the same pin */ + LSM6DSOX_I2C = 0x04, /* Only I2C */ + LSM6DSOX_I3C_T_50us = 0x02, /* I3C: available time equal to 50 μs */ + LSM6DSOX_I3C_T_2us = 0x12, /* I3C: available time equal to 2 μs */ + LSM6DSOX_I3C_T_1ms = 0x22, /* I3C: available time equal to 1 ms */ + LSM6DSOX_I3C_T_25ms = 0x32, /* I3C: available time equal to 25 ms */ +} lsm6dsox_ui_bus_md_t; + +typedef enum +{ + LSM6DSOX_SPI_4W_AUX = 0x00, + LSM6DSOX_SPI_3W_AUX = 0x01, +} lsm6dsox_aux_bus_md_t; + typedef struct { - enum - { - LSM6DSOX_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */ - LSM6DSOX_SPI_4W = 0x06, /* Only SPI: SDO / SDI separated pins */ - LSM6DSOX_SPI_3W = 0x07, /* Only SPI: SDO / SDI share the same pin */ - LSM6DSOX_I2C = 0x04, /* Only I2C */ - LSM6DSOX_I3C_T_50us = 0x02, /* I3C: available time equal to 50 μs */ - LSM6DSOX_I3C_T_2us = 0x12, /* I3C: available time equal to 2 μs */ - LSM6DSOX_I3C_T_1ms = 0x22, /* I3C: available time equal to 1 ms */ - LSM6DSOX_I3C_T_25ms = 0x32, /* I3C: available time equal to 25 ms */ - } ui_bus_md; - enum - { - LSM6DSOX_SPI_4W_AUX = 0x00, - LSM6DSOX_SPI_3W_AUX = 0x01, - } aux_bus_md; + lsm6dsox_ui_bus_md_t ui_bus_md; + lsm6dsox_aux_bus_md_t aux_bus_md; } lsm6dsox_bus_mode_t; -int32_t lsm6dsox_bus_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_bus_mode_set(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dsox_bus_mode_t val); -int32_t lsm6dsox_bus_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_bus_mode_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dsox_bus_mode_t *val); @@ -4413,79 +4411,68 @@ typedef enum LSM6DSOX_TILT = 0x40, /* Tilt algo initialization request */ LSM6DSOX_SMOTION = 0x80, /* Significant Motion initialization request */ } lsm6dsox_init_t; -int32_t lsm6dsox_init_set(stmdev_ctx_t *ctx, lsm6dsox_init_t val); +int32_t lsm6dsox_init_set(const stmdev_ctx_t *ctx, lsm6dsox_init_t val); typedef struct { -uint8_t sw_reset : - 1; /* Restoring configuration registers */ + uint8_t sw_reset : 1; /* Restoring configuration registers */ uint8_t boot : 1; /* Restoring calibration parameters */ uint8_t drdy_xl : 1; /* Accelerometer data ready */ uint8_t drdy_g : 1; /* Gyroscope data ready */ uint8_t drdy_temp : 1; /* Temperature data ready */ uint8_t ois_drdy_xl : 1; /* Accelerometer data ready on OIS */ uint8_t ois_drdy_g : 1; /* Gyroscope data ready on OIS */ -uint8_t ois_gyro_settling : - 1; /* Gyroscope is in the settling phase */ + uint8_t ois_gyro_settling : 1; /* Gyroscope is in the settling phase */ } lsm6dsox_status_t; -int32_t lsm6dsox_status_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, +int32_t lsm6dsox_status_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dsox_status_t *val); typedef struct { uint8_t sdo_sa0_pull_up : 1; /* 1 = pull-up on SDO/SA0 pin */ -uint8_t aux_sdo_ocs_pull_up : - 1; /* 1 = pull-up on OCS_Aux/SDO_Aux pins */ + uint8_t aux_sdo_ocs_pull_up : 1; /* 1 = pull-up on OCS_Aux/SDO_Aux pins */ uint8_t int1_int2_push_pull : 1; /* 1 = push-pull / 0 = open-drain*/ -uint8_t int1_pull_down : - 1; /* 1 = pull-down always disabled (0=auto) */ + uint8_t int1_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */ } lsm6dsox_pin_conf_t; -int32_t lsm6dsox_pin_conf_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pin_conf_set(const stmdev_ctx_t *ctx, lsm6dsox_pin_conf_t val); -int32_t lsm6dsox_pin_conf_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pin_conf_get(const stmdev_ctx_t *ctx, lsm6dsox_pin_conf_t *val); typedef struct { uint8_t active_low : 1; /* 1 = active low / 0 = active high */ -uint8_t base_latched : - 1; /* base functions are: FF, WU, 6D, Tap, Act/Inac */ -uint8_t emb_latched : - 1; /* emb functions are: Pedo, Tilt, SMot, Timestamp */ + uint8_t base_latched : 1; /* base functions are: FF, WU, 6D, Tap, Act/Inac */ + uint8_t emb_latched : 1; /* emb functions are: Pedo, Tilt, SMot, Timestamp */ } lsm6dsox_int_mode_t; -int32_t lsm6dsox_interrupt_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_interrupt_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_int_mode_t val); -int32_t lsm6dsox_interrupt_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_interrupt_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_int_mode_t *val); typedef struct { uint8_t drdy_xl : 1; /* Accelerometer data ready */ uint8_t drdy_g : 1; /* Gyroscope data ready */ -uint8_t drdy_temp : - 1; /* Temperature data ready (1 = int2 pin disable) */ + uint8_t drdy_temp : 1; /* Temperature data ready (1 = int2 pin disable) */ uint8_t boot : 1; /* Restoring calibration parameters */ uint8_t fifo_th : 1; /* FIFO threshold reached */ uint8_t fifo_ovr : 1; /* FIFO overrun */ uint8_t fifo_full : 1; /* FIFO full */ uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */ -uint8_t den_flag : - 1; /* external trigger level recognition (DEN) */ + uint8_t den_flag : 1; /* external trigger level recognition (DEN) */ uint8_t sh_endop : 1; /* sensor hub end operation */ -uint8_t timestamp : - 1; /* timestamp overflow (1 = int2 pin disable) */ + uint8_t timestamp : 1; /* timestamp overflow (1 = int2 pin disable) */ uint8_t six_d : 1; /* orientation change (6D/4D detection) */ uint8_t double_tap : 1; /* double-tap event */ uint8_t free_fall : 1; /* free fall event */ uint8_t wake_up : 1; /* wake up event */ uint8_t single_tap : 1; /* single-tap event */ -uint8_t sleep_change : - 1; /* Act/Inact (or Vice-versa) status changed */ + uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ uint8_t step_detector : 1; /* Step detected */ uint8_t tilt : 1; /* Relative tilt event detected */ uint8_t sig_mot : 1; /* "significant motion" event detected */ -uint8_t fsm_lc : - 1; /* fsm long counter timeout interrupt event */ + uint8_t fsm_lc : 1; /* fsm long counter timeout interrupt event */ uint8_t fsm1 : 1; /* fsm 1 interrupt event */ uint8_t fsm2 : 1; /* fsm 2 interrupt event */ uint8_t fsm3 : 1; /* fsm 3 interrupt event */ @@ -4512,9 +4499,9 @@ uint8_t fsm_lc : uint8_t mlc8 : 1; /* mlc 8 interrupt event */ } lsm6dsox_pin_int1_route_t; -int32_t lsm6dsox_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm6dsox_pin_int1_route_t val); -int32_t lsm6dsox_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm6dsox_pin_int1_route_t *val); typedef struct @@ -4533,13 +4520,11 @@ typedef struct uint8_t free_fall : 1; /* free fall event */ uint8_t wake_up : 1; /* wake up event */ uint8_t single_tap : 1; /* single-tap event */ -uint8_t sleep_change : - 1; /* Act/Inact (or Vice-versa) status changed */ + uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ uint8_t step_detector : 1; /* Step detected */ uint8_t tilt : 1; /* Relative tilt event detected */ uint8_t sig_mot : 1; /* "significant motion" event detected */ -uint8_t fsm_lc : - 1; /* fsm long counter timeout interrupt event */ + uint8_t fsm_lc : 1; /* fsm long counter timeout interrupt event */ uint8_t fsm1 : 1; /* fsm 1 interrupt event */ uint8_t fsm2 : 1; /* fsm 2 interrupt event */ uint8_t fsm3 : 1; /* fsm 3 interrupt event */ @@ -4566,10 +4551,10 @@ uint8_t fsm_lc : uint8_t mlc8 : 1; /* mlc 8 interrupt event */ } lsm6dsox_pin_int2_route_t; -int32_t lsm6dsox_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pin_int2_route_set(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dsox_pin_int2_route_t val); -int32_t lsm6dsox_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_pin_int2_route_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dsox_pin_int2_route_t *val); @@ -4578,10 +4563,8 @@ typedef struct uint8_t drdy_xl : 1; /* Accelerometer data ready */ uint8_t drdy_g : 1; /* Gyroscope data ready */ uint8_t drdy_temp : 1; /* Temperature data ready */ -uint8_t den_flag : - 1; /* external trigger level recognition (DEN) */ -uint8_t timestamp : - 1; /* timestamp overflow (1 = int2 pin disable) */ + uint8_t den_flag : 1; /* external trigger level recognition (DEN) */ + uint8_t timestamp : 1; /* timestamp overflow (1 = int2 pin disable) */ uint8_t free_fall : 1; /* free fall event */ uint8_t wake_up : 1; /* wake up event */ uint8_t wake_up_z : 1; /* wake up on Z axis event */ @@ -4593,30 +4576,19 @@ uint8_t timestamp : uint8_t tap_y : 1; /* single-tap on Y axis event */ uint8_t tap_x : 1; /* single-tap on X axis event */ uint8_t tap_sign : 1; /* sign of tap event (0-pos / 1-neg) */ -uint8_t six_d : - 1; /* orientation change (6D/4D detection) */ -uint8_t six_d_xl : - 1; /* X-axis low 6D/4D event (under threshold) */ -uint8_t six_d_xh : - 1; /* X-axis high 6D/4D event (over threshold) */ -uint8_t six_d_yl : - 1; /* Y-axis low 6D/4D event (under threshold) */ -uint8_t six_d_yh : - 1; /* Y-axis high 6D/4D event (over threshold) */ -uint8_t six_d_zl : - 1; /* Z-axis low 6D/4D event (under threshold) */ -uint8_t six_d_zh : - 1; /* Z-axis high 6D/4D event (over threshold) */ -uint8_t sleep_change : - 1; /* Act/Inact (or Vice-versa) status changed */ -uint8_t sleep_state : - 1; /* Act/Inact status flag (0-Act / 1-Inact) */ + uint8_t six_d : 1; /* orientation change (6D/4D detection) */ + uint8_t six_d_xl : 1; /* X-axis low 6D/4D event (under threshold) */ + uint8_t six_d_xh : 1; /* X-axis high 6D/4D event (over threshold) */ + uint8_t six_d_yl : 1; /* Y-axis low 6D/4D event (under threshold) */ + uint8_t six_d_yh : 1; /* Y-axis high 6D/4D event (over threshold) */ + uint8_t six_d_zl : 1; /* Z-axis low 6D/4D event (under threshold) */ + uint8_t six_d_zh : 1; /* Z-axis high 6D/4D event (over threshold) */ + uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ + uint8_t sleep_state : 1; /* Act/Inact status flag (0-Act / 1-Inact) */ uint8_t step_detector : 1; /* Step detected */ uint8_t tilt : 1; /* Relative tilt event detected */ -uint8_t sig_mot : - 1; /* "significant motion" event detected */ -uint8_t fsm_lc : - 1; /* fsm long counter timeout interrupt event */ + uint8_t sig_mot : 1; /* "significant motion" event detected */ + uint8_t fsm_lc : 1; /* fsm long counter timeout interrupt event */ uint8_t fsm1 : 1; /* fsm 1 interrupt event */ uint8_t fsm2 : 1; /* fsm 2 interrupt event */ uint8_t fsm3 : 1; /* fsm 3 interrupt event */ @@ -4642,183 +4614,186 @@ uint8_t fsm_lc : uint8_t mlc7 : 1; /* mlc 7 interrupt event */ uint8_t mlc8 : 1; /* mlc 8 interrupt event */ uint8_t sh_endop : 1; /* sensor hub end operation */ -uint8_t sh_slave0_nack : - 1; /* Not acknowledge on sensor hub slave 0 */ -uint8_t sh_slave1_nack : - 1; /* Not acknowledge on sensor hub slave 1 */ -uint8_t sh_slave2_nack : - 1; /* Not acknowledge on sensor hub slave 2 */ -uint8_t sh_slave3_nack : - 1; /* Not acknowledge on sensor hub slave 3 */ -uint8_t sh_wr_once : - 1; /* "WRITE_ONCE" end on sensor hub slave 0 */ -uint16_t fifo_diff : - 10; /* Number of unread sensor data in FIFO*/ + uint8_t sh_slave0_nack : 1; /* Not acknowledge on sensor hub slave 0 */ + uint8_t sh_slave1_nack : 1; /* Not acknowledge on sensor hub slave 1 */ + uint8_t sh_slave2_nack : 1; /* Not acknowledge on sensor hub slave 2 */ + uint8_t sh_slave3_nack : 1; /* Not acknowledge on sensor hub slave 3 */ + uint8_t sh_wr_once : 1; /* "WRITE_ONCE" end on sensor hub slave 0 */ + uint16_t fifo_diff : 10; /* Number of unread sensor data in FIFO*/ uint8_t fifo_ovr_latched : 1; /* Latched FIFO overrun status */ -uint8_t fifo_bdr : - 1; /* FIFO Batch counter threshold reached */ + uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */ uint8_t fifo_full : 1; /* FIFO full */ uint8_t fifo_ovr : 1; /* FIFO overrun */ uint8_t fifo_th : 1; /* FIFO threshold reached */ } lsm6dsox_all_sources_t; -int32_t lsm6dsox_all_sources_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_all_sources_get(const stmdev_ctx_t *ctx, lsm6dsox_all_sources_t *val); typedef struct { uint8_t odr_fine_tune; } lsm6dsox_dev_cal_t; -int32_t lsm6dsox_calibration_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_calibration_get(const stmdev_ctx_t *ctx, lsm6dsox_dev_cal_t *val); +typedef enum +{ + LSM6DSOX_XL_UI_OFF = 0x00, /* in power down */ + LSM6DSOX_XL_UI_1Hz6_LP = 0x1B, /* @1Hz6 (low power) */ + LSM6DSOX_XL_UI_1Hz6_ULP = 0x2B, /* @1Hz6 (ultra low/Gy, OIS imu off) */ + LSM6DSOX_XL_UI_12Hz5_HP = 0x01, /* @12Hz5 (high performance) */ + LSM6DSOX_XL_UI_12Hz5_LP = 0x11, /* @12Hz5 (low power) */ + LSM6DSOX_XL_UI_12Hz5_ULP = 0x21, /* @12Hz5 (ultra low/Gy, OIS imu off) */ + LSM6DSOX_XL_UI_26Hz_HP = 0x02, /* @26Hz (high performance) */ + LSM6DSOX_XL_UI_26Hz_LP = 0x12, /* @26Hz (low power) */ + LSM6DSOX_XL_UI_26Hz_ULP = 0x22, /* @26Hz (ultra low/Gy, OIS imu off) */ + LSM6DSOX_XL_UI_52Hz_HP = 0x03, /* @52Hz (high performance) */ + LSM6DSOX_XL_UI_52Hz_LP = 0x13, /* @52Hz (low power) */ + LSM6DSOX_XL_UI_52Hz_ULP = 0x23, /* @52Hz (ultra low/Gy, OIS imu off) */ + LSM6DSOX_XL_UI_104Hz_HP = 0x04, /* @104Hz (high performance) */ + LSM6DSOX_XL_UI_104Hz_NM = 0x14, /* @104Hz (normal mode) */ + LSM6DSOX_XL_UI_104Hz_ULP = 0x24, /* @104Hz (ultra low/Gy, OIS imu off) */ + LSM6DSOX_XL_UI_208Hz_HP = 0x05, /* @208Hz (high performance) */ + LSM6DSOX_XL_UI_208Hz_NM = 0x15, /* @208Hz (normal mode) */ + LSM6DSOX_XL_UI_208Hz_ULP = 0x25, /* @208Hz (ultra low/Gy, OIS imu off) */ + LSM6DSOX_XL_UI_416Hz_HP = 0x06, /* @416Hz (high performance) */ + LSM6DSOX_XL_UI_833Hz_HP = 0x07, /* @833Hz (high performance) */ + LSM6DSOX_XL_UI_1667Hz_HP = 0x08, /* @1kHz66 (high performance) */ + LSM6DSOX_XL_UI_3333Hz_HP = 0x09, /* @3kHz33 (high performance) */ + LSM6DSOX_XL_UI_6667Hz_HP = 0x0A, /* @6kHz66 (high performance) */ +} lsm6dsox_ui_xl_odr_t; + +typedef enum +{ + LSM6DSOX_XL_UI_2g = 0, + LSM6DSOX_XL_UI_4g = 2, + LSM6DSOX_XL_UI_8g = 3, + LSM6DSOX_XL_UI_16g = 1, /* OIS full scale is also forced to be 16g */ +} lsm6dsox_ui_xl_fs_t; + +typedef enum +{ + LSM6DSOX_GY_UI_OFF = 0x00, /* gy in power down */ + LSM6DSOX_GY_UI_12Hz5_LP = 0x11, /* gy @12Hz5 (low power) */ + LSM6DSOX_GY_UI_12Hz5_HP = 0x01, /* gy @12Hz5 (high performance) */ + LSM6DSOX_GY_UI_26Hz_LP = 0x12, /* gy @26Hz (low power) */ + LSM6DSOX_GY_UI_26Hz_HP = 0x02, /* gy @26Hz (high performance) */ + LSM6DSOX_GY_UI_52Hz_LP = 0x13, /* gy @52Hz (low power) */ + LSM6DSOX_GY_UI_52Hz_HP = 0x03, /* gy @52Hz (high performance) */ + LSM6DSOX_GY_UI_104Hz_NM = 0x14, /* gy @104Hz (low power) */ + LSM6DSOX_GY_UI_104Hz_HP = 0x04, /* gy @104Hz (high performance) */ + LSM6DSOX_GY_UI_208Hz_NM = 0x15, /* gy @208Hz (low power) */ + LSM6DSOX_GY_UI_208Hz_HP = 0x05, /* gy @208Hz (high performance) */ + LSM6DSOX_GY_UI_416Hz_HP = 0x06, /* gy @416Hz (high performance) */ + LSM6DSOX_GY_UI_833Hz_HP = 0x07, /* gy @833Hz (high performance) */ + LSM6DSOX_GY_UI_1667Hz_HP = 0x08, /* gy @1kHz66 (high performance) */ + LSM6DSOX_GY_UI_3333Hz_HP = 0x09, /* gy @3kHz33 (high performance) */ + LSM6DSOX_GY_UI_6667Hz_HP = 0x0A, /* gy @6kHz66 (high performance) */ +} lsm6dsox_ui_gy_odr_t; + +typedef enum +{ + LSM6DSOX_GY_UI_250dps = 0, + LSM6DSOX_GY_UI_125dps = 1, + LSM6DSOX_GY_UI_500dps = 2, + LSM6DSOX_GY_UI_1000dps = 4, + LSM6DSOX_GY_UI_2000dps = 6, +} lsm6dsox_ui_gy_fs_t; + +typedef enum +{ + LSM6DSOX_OIS_ONLY_AUX = 0x00, /* Auxiliary SPI full control */ + LSM6DSOX_OIS_ONLY_UI = 0x02, /* Primary interface full control */ + LSM6DSOX_OIS_MIXED = 0x01, /* Enabling by UI / read-config by AUX */ +} lsm6dsox_ois_ctrl_md_t; + +typedef enum +{ + LSM6DSOX_XL_OIS_OFF = 0x00, /* in power down */ + LSM6DSOX_XL_OIS_6667Hz_HP = 0x01, /* @6kHz OIS imu active/NO ULP on UI */ +} lsm6dsox_ois_xl_odr_t; + +typedef enum +{ + LSM6DSOX_XL_OIS_2g = 0, + LSM6DSOX_XL_OIS_4g = 2, + LSM6DSOX_XL_OIS_8g = 3, + LSM6DSOX_XL_OIS_16g = 1, /* UI full scale is also forced to be 16g */ +} lsm6dsox_ois_xl_fs_t; + +typedef enum +{ + LSM6DSOX_GY_OIS_OFF = 0x00, /* in power down */ + LSM6DSOX_GY_OIS_6667Hz_HP = 0x01, /* @6kHz No Ultra Low Power*/ +} lsm6dsox_ois_gy_odr_t; + +typedef enum +{ + LSM6DSOX_GY_OIS_250dps = 0, + LSM6DSOX_GY_OIS_125dps = 1, + LSM6DSOX_GY_OIS_500dps = 2, + LSM6DSOX_GY_OIS_1000dps = 4, + LSM6DSOX_GY_OIS_2000dps = 6, +} lsm6dsox_ois_gy_fs_t; + +typedef enum +{ + LSM6DSOX_FSM_DISABLE = 0x00, + LSM6DSOX_FSM_XL = 0x01, + LSM6DSOX_FSM_GY = 0x02, + LSM6DSOX_FSM_XL_GY = 0x03, +} lsm6dsox_fsm_sens_t; + +typedef enum +{ + LSM6DSOX_MLC_DISABLE = 0x00, + LSM6DSOX_MLC_XL = 0x01, + LSM6DSOX_MLC_XL_GY = 0x03, +} lsm6dsox_mlc_sens_t; + typedef struct { struct { struct { - enum - { - LSM6DSOX_XL_UI_OFF = 0x00, /* in power down */ - LSM6DSOX_XL_UI_1Hz6_LP = 0x1B, /* @1Hz6 (low power) */ - LSM6DSOX_XL_UI_1Hz6_ULP = 0x2B, /* @1Hz6 (ultra low/Gy, OIS imu off) */ - LSM6DSOX_XL_UI_12Hz5_HP = 0x01, /* @12Hz5 (high performance) */ - LSM6DSOX_XL_UI_12Hz5_LP = 0x11, /* @12Hz5 (low power) */ - LSM6DSOX_XL_UI_12Hz5_ULP = 0x21, /* @12Hz5 (ultra low/Gy, OIS imu off) */ - LSM6DSOX_XL_UI_26Hz_HP = 0x02, /* @26Hz (high performance) */ - LSM6DSOX_XL_UI_26Hz_LP = 0x12, /* @26Hz (low power) */ - LSM6DSOX_XL_UI_26Hz_ULP = 0x22, /* @26Hz (ultra low/Gy, OIS imu off) */ - LSM6DSOX_XL_UI_52Hz_HP = 0x03, /* @52Hz (high performance) */ - LSM6DSOX_XL_UI_52Hz_LP = 0x13, /* @52Hz (low power) */ - LSM6DSOX_XL_UI_52Hz_ULP = 0x23, /* @52Hz (ultra low/Gy, OIS imu off) */ - LSM6DSOX_XL_UI_104Hz_HP = 0x04, /* @104Hz (high performance) */ - LSM6DSOX_XL_UI_104Hz_NM = 0x14, /* @104Hz (normal mode) */ - LSM6DSOX_XL_UI_104Hz_ULP = 0x24, /* @104Hz (ultra low/Gy, OIS imu off) */ - LSM6DSOX_XL_UI_208Hz_HP = 0x05, /* @208Hz (high performance) */ - LSM6DSOX_XL_UI_208Hz_NM = 0x15, /* @208Hz (normal mode) */ - LSM6DSOX_XL_UI_208Hz_ULP = 0x25, /* @208Hz (ultra low/Gy, OIS imu off) */ - LSM6DSOX_XL_UI_416Hz_HP = 0x06, /* @416Hz (high performance) */ - LSM6DSOX_XL_UI_833Hz_HP = 0x07, /* @833Hz (high performance) */ - LSM6DSOX_XL_UI_1667Hz_HP = 0x08, /* @1kHz66 (high performance) */ - LSM6DSOX_XL_UI_3333Hz_HP = 0x09, /* @3kHz33 (high performance) */ - LSM6DSOX_XL_UI_6667Hz_HP = 0x0A, /* @6kHz66 (high performance) */ - } odr; - enum - { - LSM6DSOX_XL_UI_2g = 0, - LSM6DSOX_XL_UI_4g = 2, - LSM6DSOX_XL_UI_8g = 3, - LSM6DSOX_XL_UI_16g = 1, /* OIS full scale is also forced to be 16g */ - } fs; + lsm6dsox_ui_xl_odr_t odr; + lsm6dsox_ui_xl_fs_t fs; } xl; struct { - enum - { - LSM6DSOX_GY_UI_OFF = 0x00, /* gy in power down */ - LSM6DSOX_GY_UI_12Hz5_LP = 0x11, /* gy @12Hz5 (low power) */ - LSM6DSOX_GY_UI_12Hz5_HP = 0x01, /* gy @12Hz5 (high performance) */ - LSM6DSOX_GY_UI_26Hz_LP = 0x12, /* gy @26Hz (low power) */ - LSM6DSOX_GY_UI_26Hz_HP = 0x02, /* gy @26Hz (high performance) */ - LSM6DSOX_GY_UI_52Hz_LP = 0x13, /* gy @52Hz (low power) */ - LSM6DSOX_GY_UI_52Hz_HP = 0x03, /* gy @52Hz (high performance) */ - LSM6DSOX_GY_UI_104Hz_NM = 0x14, /* gy @104Hz (low power) */ - LSM6DSOX_GY_UI_104Hz_HP = 0x04, /* gy @104Hz (high performance) */ - LSM6DSOX_GY_UI_208Hz_NM = 0x15, /* gy @208Hz (low power) */ - LSM6DSOX_GY_UI_208Hz_HP = 0x05, /* gy @208Hz (high performance) */ - LSM6DSOX_GY_UI_416Hz_HP = 0x06, /* gy @416Hz (high performance) */ - LSM6DSOX_GY_UI_833Hz_HP = 0x07, /* gy @833Hz (high performance) */ - LSM6DSOX_GY_UI_1667Hz_HP = 0x08, /* gy @1kHz66 (high performance) */ - LSM6DSOX_GY_UI_3333Hz_HP = 0x09, /* gy @3kHz33 (high performance) */ - LSM6DSOX_GY_UI_6667Hz_HP = 0x0A, /* gy @6kHz66 (high performance) */ - } odr; - enum - { - LSM6DSOX_GY_UI_250dps = 0, - LSM6DSOX_GY_UI_125dps = 1, - LSM6DSOX_GY_UI_500dps = 2, - LSM6DSOX_GY_UI_1000dps = 4, - LSM6DSOX_GY_UI_2000dps = 6, - } fs; + lsm6dsox_ui_gy_odr_t odr; + lsm6dsox_ui_gy_fs_t fs; } gy; } ui; struct { - enum - { - LSM6DSOX_OIS_ONLY_AUX = 0x00, /* Auxiliary SPI full control */ - LSM6DSOX_OIS_ONLY_UI = 0x02, /* Primary interface full control */ - LSM6DSOX_OIS_MIXED = 0x01, /* Enabling by UI / read-config by AUX */ - } ctrl_md; + lsm6dsox_ois_ctrl_md_t ctrl_md; struct { - enum - { - LSM6DSOX_XL_OIS_OFF = 0x00, /* in power down */ - LSM6DSOX_XL_OIS_6667Hz_HP = 0x01, /* @6kHz OIS imu active/NO ULP on UI */ - } odr; - enum - { - LSM6DSOX_XL_OIS_2g = 0, - LSM6DSOX_XL_OIS_4g = 2, - LSM6DSOX_XL_OIS_8g = 3, - LSM6DSOX_XL_OIS_16g = 1, /* UI full scale is also forced to be 16g */ - } fs; + lsm6dsox_ois_xl_odr_t odr; + lsm6dsox_ois_xl_fs_t fs; } xl; struct { - enum - { - LSM6DSOX_GY_OIS_OFF = 0x00, /* in power down */ - LSM6DSOX_GY_OIS_6667Hz_HP = 0x01, /* @6kHz No Ultra Low Power*/ - } odr; - enum - { - LSM6DSOX_GY_OIS_250dps = 0, - LSM6DSOX_GY_OIS_125dps = 1, - LSM6DSOX_GY_OIS_500dps = 2, - LSM6DSOX_GY_OIS_1000dps = 4, - LSM6DSOX_GY_OIS_2000dps = 6, - } fs; + lsm6dsox_ois_gy_odr_t odr; + lsm6dsox_ois_gy_fs_t fs; } gy; } ois; struct { - enum - { - LSM6DSOX_FSM_DISABLE = 0x00, - LSM6DSOX_FSM_XL = 0x01, - LSM6DSOX_FSM_GY = 0x02, - LSM6DSOX_FSM_XL_GY = 0x03, - } sens; - enum - { - LSM6DSOX_FSM_12Hz5 = 0x00, - LSM6DSOX_FSM_26Hz = 0x01, - LSM6DSOX_FSM_52Hz = 0x02, - LSM6DSOX_FSM_104Hz = 0x03, - } odr; + lsm6dsox_fsm_sens_t sens; + lsm6dsox_fsm_odr_t odr; } fsm; struct { - enum - { - LSM6DSOX_MLC_DISABLE = 0x00, - LSM6DSOX_MLC_XL = 0x01, - LSM6DSOX_MLC_XL_GY = 0x03, - } sens; - enum - { - LSM6DSOX_MLC_12Hz5 = 0x00, - LSM6DSOX_MLC_26Hz = 0x01, - LSM6DSOX_MLC_52Hz = 0x02, - LSM6DSOX_MLC_104Hz = 0x03, - } odr; + lsm6dsox_mlc_sens_t sens; + lsm6dsox_mlc_odr_t odr; } mlc; } lsm6dsox_md_t; -int32_t lsm6dsox_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, +int32_t lsm6dsox_mode_set(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dsox_md_t *val); -int32_t lsm6dsox_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, +int32_t lsm6dsox_mode_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dsox_md_t *val); typedef struct @@ -4855,7 +4830,7 @@ typedef struct } gy; } ois; } lsm6dsox_data_t; -int32_t lsm6dsox_data_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, +int32_t lsm6dsox_data_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, lsm6dsox_md_t *md, lsm6dsox_data_t *data); typedef struct @@ -4867,11 +4842,11 @@ typedef struct uint8_t fsm : 1; /* finite state machine */ uint8_t fifo_compr : 1; /* mlc 8 interrupt event */ } lsm6dsox_emb_sens_t; -int32_t lsm6dsox_embedded_sens_set(stmdev_ctx_t *ctx, +int32_t lsm6dsox_embedded_sens_set(const stmdev_ctx_t *ctx, lsm6dsox_emb_sens_t *emb_sens); -int32_t lsm6dsox_embedded_sens_get(stmdev_ctx_t *ctx, +int32_t lsm6dsox_embedded_sens_get(const stmdev_ctx_t *ctx, lsm6dsox_emb_sens_t *emb_sens); -int32_t lsm6dsox_embedded_sens_off(stmdev_ctx_t *ctx); +int32_t lsm6dsox_embedded_sens_off(const stmdev_ctx_t *ctx); /** * @} diff --git a/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.c b/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.c index 706e883c..333d6e59 100644 --- a/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.c +++ b/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm6dsr_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm6dsr_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lsm6dsr_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm6dsr_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm6dsr_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -171,7 +181,7 @@ float_t lsm6dsr_from_lsb_to_nsec(int32_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsr_fs_xl_t val) { lsm6dsr_ctrl1_xl_t ctrl1_xl; @@ -197,7 +207,7 @@ int32_t lsm6dsr_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsr_fs_xl_t *val) { lsm6dsr_ctrl1_xl_t ctrl1_xl; @@ -239,7 +249,7 @@ int32_t lsm6dsr_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsr_odr_xl_t val) { lsm6dsr_odr_xl_t odr_xl = val; @@ -389,7 +399,7 @@ int32_t lsm6dsr_xl_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsr_odr_xl_t *val) { lsm6dsr_ctrl1_xl_t ctrl1_xl; @@ -463,7 +473,7 @@ int32_t lsm6dsr_xl_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsr_fs_g_t val) { lsm6dsr_ctrl2_g_t ctrl2_g; @@ -488,7 +498,7 @@ int32_t lsm6dsr_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsr_fs_g_t *val) { lsm6dsr_ctrl2_g_t ctrl2_g; @@ -538,7 +548,7 @@ int32_t lsm6dsr_gy_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_gy_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsr_odr_g_t val) { lsm6dsr_odr_g_t odr_gy = val; @@ -687,7 +697,7 @@ int32_t lsm6dsr_gy_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsr_odr_g_t *val) { lsm6dsr_ctrl2_g_t ctrl2_g; @@ -757,7 +767,7 @@ int32_t lsm6dsr_gy_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_ctrl3_c_t ctrl3_c; int32_t ret; @@ -781,7 +791,7 @@ int32_t lsm6dsr_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_ctrl3_c_t ctrl3_c; int32_t ret; @@ -801,7 +811,7 @@ int32_t lsm6dsr_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_offset_weight_set(const stmdev_ctx_t *ctx, lsm6dsr_usr_off_w_t val) { lsm6dsr_ctrl6_c_t ctrl6_c; @@ -827,7 +837,7 @@ int32_t lsm6dsr_xl_offset_weight_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_offset_weight_get(const stmdev_ctx_t *ctx, lsm6dsr_usr_off_w_t *val) { lsm6dsr_ctrl6_c_t ctrl6_c; @@ -861,7 +871,7 @@ int32_t lsm6dsr_xl_offset_weight_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_power_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_xl_hm_mode_t val) { lsm6dsr_ctrl6_c_t ctrl6_c; @@ -886,7 +896,7 @@ int32_t lsm6dsr_xl_power_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_power_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_xl_hm_mode_t *val) { lsm6dsr_ctrl6_c_t ctrl6_c; @@ -920,7 +930,7 @@ int32_t lsm6dsr_xl_power_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_gy_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_gy_power_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_g_hm_mode_t val) { lsm6dsr_ctrl7_g_t ctrl7_g; @@ -945,7 +955,7 @@ int32_t lsm6dsr_gy_power_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_gy_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_gy_power_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_g_hm_mode_t *val) { lsm6dsr_ctrl7_g_t ctrl7_g; @@ -981,7 +991,7 @@ int32_t lsm6dsr_gy_power_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_all_sources_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_all_sources_get(const stmdev_ctx_t *ctx, lsm6dsr_all_sources_t *val) { int32_t ret; @@ -1052,7 +1062,7 @@ int32_t lsm6dsr_all_sources_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_status_reg_get(const stmdev_ctx_t *ctx, lsm6dsr_status_reg_t *val) { int32_t ret; @@ -1070,7 +1080,7 @@ int32_t lsm6dsr_status_reg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_status_reg_t status_reg; @@ -1091,7 +1101,7 @@ int32_t lsm6dsr_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_status_reg_t status_reg; @@ -1112,7 +1122,7 @@ int32_t lsm6dsr_gy_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_status_reg_t status_reg; @@ -1135,7 +1145,7 @@ int32_t lsm6dsr_temp_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsr_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1154,7 +1164,7 @@ int32_t lsm6dsr_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsr_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1173,7 +1183,7 @@ int32_t lsm6dsr_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsr_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1192,7 +1202,7 @@ int32_t lsm6dsr_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsr_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1211,7 +1221,7 @@ int32_t lsm6dsr_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsr_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1230,7 +1240,7 @@ int32_t lsm6dsr_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsr_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1247,7 +1257,7 @@ int32_t lsm6dsr_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_ctrl7_g_t ctrl7_g; int32_t ret; @@ -1271,7 +1281,7 @@ int32_t lsm6dsr_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_ctrl7_g_t ctrl7_g; int32_t ret; @@ -1302,7 +1312,7 @@ int32_t lsm6dsr_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_timestamp_rst(stmdev_ctx_t *ctx) +int32_t lsm6dsr_timestamp_rst(const stmdev_ctx_t *ctx) { uint8_t rst_val = 0xAA; return lsm6dsr_write_reg(ctx, LSM6DSR_TIMESTAMP2, &rst_val, 1); @@ -1316,7 +1326,7 @@ int32_t lsm6dsr_timestamp_rst(stmdev_ctx_t *ctx) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_ctrl10_c_t ctrl10_c; int32_t ret; @@ -1341,7 +1351,7 @@ int32_t lsm6dsr_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_ctrl10_c_t ctrl10_c; int32_t ret; @@ -1362,7 +1372,7 @@ int32_t lsm6dsr_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t lsm6dsr_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; @@ -1396,7 +1406,7 @@ int32_t lsm6dsr_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_rounding_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_rounding_t val) { lsm6dsr_ctrl5_c_t ctrl5_c; @@ -1421,7 +1431,7 @@ int32_t lsm6dsr_rounding_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_rounding_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_rounding_t *val) { lsm6dsr_ctrl5_c_t ctrl5_c; @@ -1465,7 +1475,7 @@ int32_t lsm6dsr_rounding_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsr_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1486,7 +1496,7 @@ int32_t lsm6dsr_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsr_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1511,7 +1521,7 @@ int32_t lsm6dsr_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsr_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1535,7 +1545,7 @@ int32_t lsm6dsr_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsr_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1552,7 +1562,7 @@ int32_t lsm6dsr_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsr_number_of_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1581,7 +1591,7 @@ int32_t lsm6dsr_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_steps_reset(stmdev_ctx_t *ctx) +int32_t lsm6dsr_steps_reset(const stmdev_ctx_t *ctx) { lsm6dsr_emb_func_src_t emb_func_src; int32_t ret; @@ -1631,7 +1641,7 @@ int32_t lsm6dsr_steps_reset(stmdev_ctx_t *ctx) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_internal_freq_fine_t internal_freq_fine; int32_t ret; @@ -1659,7 +1669,7 @@ int32_t lsm6dsr_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_internal_freq_fine_t internal_freq_fine; int32_t ret; @@ -1680,7 +1690,7 @@ int32_t lsm6dsr_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_mem_bank_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dsr_reg_access_t val) { lsm6dsr_func_cfg_access_t func_cfg_access; @@ -1708,7 +1718,7 @@ int32_t lsm6dsr_mem_bank_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_mem_bank_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dsr_reg_access_t *val) { lsm6dsr_func_cfg_access_t func_cfg_access; @@ -1748,7 +1758,7 @@ int32_t lsm6dsr_mem_bank_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add, +int32_t lsm6dsr_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t add, uint8_t *val) { lsm6dsr_page_rw_t page_rw; @@ -1823,7 +1833,7 @@ int32_t lsm6dsr_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add, +int32_t lsm6dsr_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t add, uint8_t *buf, uint8_t len) { lsm6dsr_page_rw_t page_rw; @@ -1933,7 +1943,7 @@ int32_t lsm6dsr_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add, +int32_t lsm6dsr_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, uint8_t *val) { lsm6dsr_page_rw_t page_rw; @@ -2007,7 +2017,7 @@ int32_t lsm6dsr_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_dataready_pulsed_t val) { lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1; @@ -2035,7 +2045,7 @@ int32_t lsm6dsr_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_dataready_pulsed_t *val) { lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1; @@ -2070,7 +2080,7 @@ int32_t lsm6dsr_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsr_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -2087,7 +2097,7 @@ int32_t lsm6dsr_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2111,7 +2121,7 @@ int32_t lsm6dsr_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2131,7 +2141,7 @@ int32_t lsm6dsr_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2156,7 +2166,7 @@ int32_t lsm6dsr_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2175,7 +2185,7 @@ int32_t lsm6dsr_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2199,7 +2209,7 @@ int32_t lsm6dsr_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2220,7 +2230,7 @@ int32_t lsm6dsr_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dsr_st_xl_t val) { lsm6dsr_ctrl5_c_t ctrl5_c; @@ -2245,7 +2255,7 @@ int32_t lsm6dsr_xl_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dsr_st_xl_t *val) { lsm6dsr_ctrl5_c_t ctrl5_c; @@ -2283,7 +2293,7 @@ int32_t lsm6dsr_xl_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dsr_st_g_t val) { lsm6dsr_ctrl5_c_t ctrl5_c; @@ -2308,7 +2318,7 @@ int32_t lsm6dsr_gy_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dsr_st_g_t *val) { lsm6dsr_ctrl5_c_t ctrl5_c; @@ -2359,7 +2369,7 @@ int32_t lsm6dsr_gy_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_ctrl1_xl_t ctrl1_xl; int32_t ret; @@ -2384,7 +2394,7 @@ int32_t lsm6dsr_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_ctrl1_xl_t ctrl1_xl; int32_t ret; @@ -2404,7 +2414,7 @@ int32_t lsm6dsr_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_ctrl4_c_t ctrl4_c; int32_t ret; @@ -2429,7 +2439,7 @@ int32_t lsm6dsr_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_ctrl4_c_t ctrl4_c; int32_t ret; @@ -2449,7 +2459,7 @@ int32_t lsm6dsr_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_ctrl4_c_t ctrl4_c; @@ -2475,7 +2485,7 @@ int32_t lsm6dsr_filter_settling_mask_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_ctrl4_c_t ctrl4_c; @@ -2495,7 +2505,7 @@ int32_t lsm6dsr_filter_settling_mask_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsr_ftype_t val) { lsm6dsr_ctrl6_c_t ctrl6_c; @@ -2520,7 +2530,7 @@ int32_t lsm6dsr_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsr_ftype_t *val) { lsm6dsr_ctrl6_c_t ctrl6_c; @@ -2578,7 +2588,7 @@ int32_t lsm6dsr_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -2603,7 +2613,7 @@ int32_t lsm6dsr_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -2623,7 +2633,7 @@ int32_t lsm6dsr_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, lsm6dsr_hp_slope_xl_en_t val) { lsm6dsr_ctrl8_xl_t ctrl8_xl; @@ -2652,7 +2662,7 @@ int32_t lsm6dsr_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, lsm6dsr_hp_slope_xl_en_t *val) { lsm6dsr_ctrl8_xl_t ctrl8_xl; @@ -2774,7 +2784,7 @@ int32_t lsm6dsr_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -2801,7 +2811,7 @@ int32_t lsm6dsr_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -2821,7 +2831,7 @@ int32_t lsm6dsr_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dsr_slope_fds_t val) { lsm6dsr_tap_cfg0_t tap_cfg0; @@ -2848,7 +2858,7 @@ int32_t lsm6dsr_xl_hp_path_internal_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dsr_slope_fds_t *val) { lsm6dsr_tap_cfg0_t tap_cfg0; @@ -2883,7 +2893,7 @@ int32_t lsm6dsr_xl_hp_path_internal_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_gy_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dsr_hpm_g_t val) { lsm6dsr_ctrl7_g_t ctrl7_g; @@ -2910,7 +2920,7 @@ int32_t lsm6dsr_gy_hp_path_internal_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_gy_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dsr_hpm_g_t *val) { lsm6dsr_ctrl7_g_t ctrl7_g; @@ -2970,7 +2980,7 @@ int32_t lsm6dsr_gy_hp_path_internal_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_sdo_ocs_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_ois_pu_dis_t val) { lsm6dsr_pin_ctrl_t pin_ctrl; @@ -2997,7 +3007,7 @@ int32_t lsm6dsr_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_sdo_ocs_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_ois_pu_dis_t *val) { lsm6dsr_pin_ctrl_t pin_ctrl; @@ -3031,7 +3041,7 @@ int32_t lsm6dsr_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_pw_on_ctrl_set(const stmdev_ctx_t *ctx, lsm6dsr_ois_on_t val) { lsm6dsr_ctrl7_g_t ctrl7_g; @@ -3057,7 +3067,7 @@ int32_t lsm6dsr_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_pw_on_ctrl_get(const stmdev_ctx_t *ctx, lsm6dsr_ois_on_t *val) { lsm6dsr_ctrl7_g_t ctrl7_g; @@ -3091,7 +3101,7 @@ int32_t lsm6dsr_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_status_reg_get(const stmdev_ctx_t *ctx, lsm6dsr_status_spiaux_t *val) { int32_t ret; @@ -3109,7 +3119,7 @@ int32_t lsm6dsr_aux_status_reg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_status_spiaux_t status_spiaux; @@ -3130,7 +3140,7 @@ int32_t lsm6dsr_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_status_spiaux_t status_spiaux; @@ -3151,7 +3161,7 @@ int32_t lsm6dsr_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_status_spiaux_t status_spiaux; @@ -3173,7 +3183,7 @@ int32_t lsm6dsr_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dsr_st_xl_ois_t val) { lsm6dsr_int_ois_t int_ois; @@ -3199,7 +3209,7 @@ int32_t lsm6dsr_aux_xl_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dsr_st_xl_ois_t *val) { lsm6dsr_int_ois_t int_ois; @@ -3237,7 +3247,7 @@ int32_t lsm6dsr_aux_xl_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dsr_den_lh_ois_t val) { lsm6dsr_int_ois_t int_ois; @@ -3262,7 +3272,7 @@ int32_t lsm6dsr_aux_den_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dsr_den_lh_ois_t *val) { lsm6dsr_int_ois_t int_ois; @@ -3296,7 +3306,7 @@ int32_t lsm6dsr_aux_den_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_den_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_lvl2_ois_t val) { lsm6dsr_int_ois_t int_ois; @@ -3335,7 +3345,7 @@ int32_t lsm6dsr_aux_den_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_den_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_lvl2_ois_t *val) { lsm6dsr_int_ois_t int_ois; @@ -3381,7 +3391,7 @@ int32_t lsm6dsr_aux_den_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_aux_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_int_ois_t int_ois; int32_t ret; @@ -3406,7 +3416,7 @@ int32_t lsm6dsr_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_int_ois_t int_ois; int32_t ret; @@ -3430,7 +3440,7 @@ int32_t lsm6dsr_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_ois_en_spi2_t val) { lsm6dsr_ctrl1_ois_t ctrl1_ois; @@ -3463,7 +3473,7 @@ int32_t lsm6dsr_aux_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_ois_en_spi2_t *val) { lsm6dsr_ctrl1_ois_t ctrl1_ois; @@ -3501,7 +3511,7 @@ int32_t lsm6dsr_aux_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsr_fs_g_ois_t val) { lsm6dsr_ctrl1_ois_t ctrl1_ois; @@ -3528,7 +3538,7 @@ int32_t lsm6dsr_aux_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsr_fs_g_ois_t *val) { lsm6dsr_ctrl1_ois_t ctrl1_ois; @@ -3575,7 +3585,7 @@ int32_t lsm6dsr_aux_gy_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_spi_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_sim_ois_t val) { lsm6dsr_ctrl1_ois_t ctrl1_ois; @@ -3601,7 +3611,7 @@ int32_t lsm6dsr_aux_spi_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_spi_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_sim_ois_t *val) { lsm6dsr_ctrl1_ois_t ctrl1_ois; @@ -3635,7 +3645,7 @@ int32_t lsm6dsr_aux_spi_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsr_ftype_ois_t val) { lsm6dsr_ctrl2_ois_t ctrl2_ois; @@ -3661,7 +3671,7 @@ int32_t lsm6dsr_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsr_ftype_ois_t *val) { lsm6dsr_ctrl2_ois_t ctrl2_ois; @@ -3703,7 +3713,7 @@ int32_t lsm6dsr_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_gy_hp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsr_hpm_ois_t val) { lsm6dsr_ctrl2_ois_t ctrl2_ois; @@ -3730,7 +3740,7 @@ int32_t lsm6dsr_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_gy_hp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsr_hpm_ois_t *val) { lsm6dsr_ctrl2_ois_t ctrl2_ois; @@ -3778,7 +3788,7 @@ int32_t lsm6dsr_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_gy_clamp_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_gy_clamp_set(const stmdev_ctx_t *ctx, lsm6dsr_st_ois_clampdis_t val) { lsm6dsr_ctrl3_ois_t ctrl3_ois; @@ -3806,7 +3816,7 @@ int32_t lsm6dsr_aux_gy_clamp_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_gy_clamp_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_gy_clamp_get(const stmdev_ctx_t *ctx, lsm6dsr_st_ois_clampdis_t *val) { lsm6dsr_ctrl3_ois_t ctrl3_ois; @@ -3840,7 +3850,7 @@ int32_t lsm6dsr_aux_gy_clamp_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dsr_st_ois_t val) { lsm6dsr_ctrl3_ois_t ctrl3_ois; @@ -3866,7 +3876,7 @@ int32_t lsm6dsr_aux_gy_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dsr_st_ois_t *val) { lsm6dsr_ctrl3_ois_t ctrl3_ois; @@ -3904,7 +3914,7 @@ int32_t lsm6dsr_aux_gy_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_xl_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_xl_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsr_filter_xl_conf_ois_t val) { lsm6dsr_ctrl3_ois_t ctrl3_ois; @@ -3930,7 +3940,7 @@ int32_t lsm6dsr_aux_xl_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_xl_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_xl_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsr_filter_xl_conf_ois_t *val) { lsm6dsr_ctrl3_ois_t ctrl3_ois; @@ -3988,7 +3998,7 @@ int32_t lsm6dsr_aux_xl_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsr_fs_xl_ois_t val) { lsm6dsr_ctrl3_ois_t ctrl3_ois; @@ -4014,7 +4024,7 @@ int32_t lsm6dsr_aux_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_aux_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsr_fs_xl_ois_t *val) { lsm6dsr_ctrl3_ois_t ctrl3_ois; @@ -4069,7 +4079,7 @@ int32_t lsm6dsr_aux_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_sdo_pu_en_t val) { lsm6dsr_pin_ctrl_t pin_ctrl; @@ -4094,7 +4104,7 @@ int32_t lsm6dsr_sdo_sa0_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_sdo_pu_en_t *val) { lsm6dsr_pin_ctrl_t pin_ctrl; @@ -4128,7 +4138,7 @@ int32_t lsm6dsr_sdo_sa0_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_int1_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_int1_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_pd_dis_int1_t val) { lsm6dsr_i3c_bus_avb_t i3c_bus_avb; @@ -4155,7 +4165,7 @@ int32_t lsm6dsr_int1_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_int1_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_int1_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_pd_dis_int1_t *val) { lsm6dsr_i3c_bus_avb_t i3c_bus_avb; @@ -4190,7 +4200,7 @@ int32_t lsm6dsr_int1_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsr_sim_t val) +int32_t lsm6dsr_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_sim_t val) { lsm6dsr_ctrl3_c_t ctrl3_c; int32_t ret; @@ -4214,7 +4224,7 @@ int32_t lsm6dsr_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsr_sim_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsr_sim_t *val) +int32_t lsm6dsr_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_sim_t *val) { lsm6dsr_ctrl3_c_t ctrl3_c; int32_t ret; @@ -4247,7 +4257,7 @@ int32_t lsm6dsr_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsr_sim_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_i2c_interface_set(const stmdev_ctx_t *ctx, lsm6dsr_i2c_disable_t val) { lsm6dsr_ctrl4_c_t ctrl4_c; @@ -4272,7 +4282,7 @@ int32_t lsm6dsr_i2c_interface_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_i2c_interface_get(const stmdev_ctx_t *ctx, lsm6dsr_i2c_disable_t *val) { lsm6dsr_ctrl4_c_t ctrl4_c; @@ -4306,7 +4316,7 @@ int32_t lsm6dsr_i2c_interface_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_i3c_disable_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_i3c_disable_set(const stmdev_ctx_t *ctx, lsm6dsr_i3c_disable_t val) { lsm6dsr_ctrl9_xl_t ctrl9_xl; @@ -4346,7 +4356,7 @@ int32_t lsm6dsr_i3c_disable_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_i3c_disable_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_i3c_disable_get(const stmdev_ctx_t *ctx, lsm6dsr_i3c_disable_t *val) { lsm6dsr_ctrl9_xl_t ctrl9_xl; @@ -4413,7 +4423,7 @@ int32_t lsm6dsr_i3c_disable_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm6dsr_pin_int1_route_t *val) { lsm6dsr_tap_cfg2_t tap_cfg2; @@ -4531,7 +4541,7 @@ int32_t lsm6dsr_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm6dsr_pin_int1_route_t *val) { int32_t ret; @@ -4585,7 +4595,7 @@ int32_t lsm6dsr_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm6dsr_pin_int2_route_t *val) { lsm6dsr_tap_cfg2_t tap_cfg2; @@ -4703,7 +4713,7 @@ int32_t lsm6dsr_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pin_int2_route_get(const stmdev_ctx_t *ctx, lsm6dsr_pin_int2_route_t *val) { int32_t ret; @@ -4756,7 +4766,7 @@ int32_t lsm6dsr_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsr_pp_od_t val) +int32_t lsm6dsr_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_pp_od_t val) { lsm6dsr_ctrl3_c_t ctrl3_c; int32_t ret; @@ -4780,7 +4790,7 @@ int32_t lsm6dsr_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsr_pp_od_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsr_pp_od_t *val) +int32_t lsm6dsr_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_pp_od_t *val) { lsm6dsr_ctrl3_c_t ctrl3_c; int32_t ret; @@ -4813,7 +4823,7 @@ int32_t lsm6dsr_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsr_pp_od_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pin_polarity_set(const stmdev_ctx_t *ctx, lsm6dsr_h_lactive_t val) { lsm6dsr_ctrl3_c_t ctrl3_c; @@ -4838,7 +4848,7 @@ int32_t lsm6dsr_pin_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pin_polarity_get(const stmdev_ctx_t *ctx, lsm6dsr_h_lactive_t *val) { lsm6dsr_ctrl3_c_t ctrl3_c; @@ -4872,7 +4882,7 @@ int32_t lsm6dsr_pin_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_ctrl4_c_t ctrl4_c; int32_t ret; @@ -4896,7 +4906,7 @@ int32_t lsm6dsr_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_ctrl4_c_t ctrl4_c; int32_t ret; @@ -4915,7 +4925,7 @@ int32_t lsm6dsr_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_int_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_int_notification_set(const stmdev_ctx_t *ctx, lsm6dsr_lir_t val) { lsm6dsr_tap_cfg0_t tap_cfg0; @@ -4964,7 +4974,7 @@ int32_t lsm6dsr_int_notification_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_int_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_int_notification_get(const stmdev_ctx_t *ctx, lsm6dsr_lir_t *val) { lsm6dsr_tap_cfg0_t tap_cfg0; @@ -5038,7 +5048,7 @@ int32_t lsm6dsr_int_notification_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_wkup_ths_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_wkup_ths_weight_set(const stmdev_ctx_t *ctx, lsm6dsr_wake_ths_w_t val) { lsm6dsr_wake_up_dur_t wake_up_dur; @@ -5067,7 +5077,7 @@ int32_t lsm6dsr_wkup_ths_weight_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_wkup_ths_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_wkup_ths_weight_get(const stmdev_ctx_t *ctx, lsm6dsr_wake_ths_w_t *val) { lsm6dsr_wake_up_dur_t wake_up_dur; @@ -5103,7 +5113,7 @@ int32_t lsm6dsr_wkup_ths_weight_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_wake_up_ths_t wake_up_ths; int32_t ret; @@ -5130,7 +5140,7 @@ int32_t lsm6dsr_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_wake_up_ths_t wake_up_ths; int32_t ret; @@ -5150,7 +5160,7 @@ int32_t lsm6dsr_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_wake_up_ths_t wake_up_ths; @@ -5177,7 +5187,7 @@ int32_t lsm6dsr_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_wake_up_ths_t wake_up_ths; @@ -5198,7 +5208,7 @@ int32_t lsm6dsr_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_wake_up_dur_t wake_up_dur; int32_t ret; @@ -5224,7 +5234,7 @@ int32_t lsm6dsr_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_wake_up_dur_t wake_up_dur; int32_t ret; @@ -5257,7 +5267,7 @@ int32_t lsm6dsr_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_ctrl4_c_t ctrl4_c; int32_t ret; @@ -5281,7 +5291,7 @@ int32_t lsm6dsr_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_ctrl4_c_t ctrl4_c; int32_t ret; @@ -5302,7 +5312,7 @@ int32_t lsm6dsr_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_act_pin_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_act_pin_notification_set(const stmdev_ctx_t *ctx, lsm6dsr_sleep_status_on_int_t val) { lsm6dsr_tap_cfg0_t tap_cfg0; @@ -5330,7 +5340,7 @@ int32_t lsm6dsr_act_pin_notification_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_act_pin_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_act_pin_notification_get(const stmdev_ctx_t *ctx, lsm6dsr_sleep_status_on_int_t *val) { lsm6dsr_tap_cfg0_t tap_cfg0; @@ -5364,7 +5374,7 @@ int32_t lsm6dsr_act_pin_notification_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_act_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_act_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_inact_en_t val) { lsm6dsr_tap_cfg2_t tap_cfg2; @@ -5389,7 +5399,7 @@ int32_t lsm6dsr_act_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_act_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_act_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_inact_en_t *val) { lsm6dsr_tap_cfg2_t tap_cfg2; @@ -5431,7 +5441,7 @@ int32_t lsm6dsr_act_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_wake_up_dur_t wake_up_dur; int32_t ret; @@ -5457,7 +5467,7 @@ int32_t lsm6dsr_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_wake_up_dur_t wake_up_dur; int32_t ret; @@ -5490,7 +5500,7 @@ int32_t lsm6dsr_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_tap_cfg0_t tap_cfg0; int32_t ret; @@ -5515,7 +5525,7 @@ int32_t lsm6dsr_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_tap_cfg0_t tap_cfg0; @@ -5535,7 +5545,7 @@ int32_t lsm6dsr_tap_detection_on_z_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_tap_cfg0_t tap_cfg0; int32_t ret; @@ -5560,7 +5570,7 @@ int32_t lsm6dsr_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_tap_cfg0_t tap_cfg0; @@ -5580,7 +5590,7 @@ int32_t lsm6dsr_tap_detection_on_y_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_tap_cfg0_t tap_cfg0; int32_t ret; @@ -5605,7 +5615,7 @@ int32_t lsm6dsr_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_tap_cfg0_t tap_cfg0; @@ -5625,7 +5635,7 @@ int32_t lsm6dsr_tap_detection_on_x_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_tap_cfg1_t tap_cfg1; int32_t ret; @@ -5650,7 +5660,7 @@ int32_t lsm6dsr_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_tap_cfg1_t tap_cfg1; int32_t ret; @@ -5669,7 +5679,7 @@ int32_t lsm6dsr_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_tap_axis_priority_set(const stmdev_ctx_t *ctx, lsm6dsr_tap_priority_t val) { lsm6dsr_tap_cfg1_t tap_cfg1; @@ -5694,7 +5704,7 @@ int32_t lsm6dsr_tap_axis_priority_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_tap_axis_priority_get(const stmdev_ctx_t *ctx, lsm6dsr_tap_priority_t *val) { lsm6dsr_tap_cfg1_t tap_cfg1; @@ -5744,7 +5754,7 @@ int32_t lsm6dsr_tap_axis_priority_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_tap_cfg2_t tap_cfg2; int32_t ret; @@ -5769,7 +5779,7 @@ int32_t lsm6dsr_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_tap_cfg2_t tap_cfg2; int32_t ret; @@ -5788,7 +5798,7 @@ int32_t lsm6dsr_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -5814,7 +5824,7 @@ int32_t lsm6dsr_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -5838,7 +5848,7 @@ int32_t lsm6dsr_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_int_dur2_t int_dur2; int32_t ret; @@ -5867,7 +5877,7 @@ int32_t lsm6dsr_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_int_dur2_t int_dur2; int32_t ret; @@ -5890,7 +5900,7 @@ int32_t lsm6dsr_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_int_dur2_t int_dur2; int32_t ret; @@ -5919,7 +5929,7 @@ int32_t lsm6dsr_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_int_dur2_t int_dur2; int32_t ret; @@ -5944,7 +5954,7 @@ int32_t lsm6dsr_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_int_dur2_t int_dur2; int32_t ret; @@ -5973,7 +5983,7 @@ int32_t lsm6dsr_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_int_dur2_t int_dur2; int32_t ret; @@ -5992,7 +6002,7 @@ int32_t lsm6dsr_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_tap_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_single_double_tap_t val) { lsm6dsr_wake_up_ths_t wake_up_ths; @@ -6019,7 +6029,7 @@ int32_t lsm6dsr_tap_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_tap_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_single_double_tap_t *val) { lsm6dsr_wake_up_ths_t wake_up_ths; @@ -6067,7 +6077,7 @@ int32_t lsm6dsr_tap_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_6d_threshold_set(const stmdev_ctx_t *ctx, lsm6dsr_sixd_ths_t val) { lsm6dsr_tap_ths_6d_t tap_ths_6d; @@ -6094,7 +6104,7 @@ int32_t lsm6dsr_6d_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_6d_threshold_get(const stmdev_ctx_t *ctx, lsm6dsr_sixd_ths_t *val) { lsm6dsr_tap_ths_6d_t tap_ths_6d; @@ -6137,7 +6147,7 @@ int32_t lsm6dsr_6d_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -6163,7 +6173,7 @@ int32_t lsm6dsr_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -6196,7 +6206,7 @@ int32_t lsm6dsr_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_ff_threshold_set(const stmdev_ctx_t *ctx, lsm6dsr_ff_ths_t val) { lsm6dsr_free_fall_t free_fall; @@ -6222,7 +6232,7 @@ int32_t lsm6dsr_ff_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_ff_threshold_get(const stmdev_ctx_t *ctx, lsm6dsr_ff_ths_t *val) { lsm6dsr_free_fall_t free_fall; @@ -6280,7 +6290,7 @@ int32_t lsm6dsr_ff_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_wake_up_dur_t wake_up_dur; lsm6dsr_free_fall_t free_fall; @@ -6320,7 +6330,7 @@ int32_t lsm6dsr_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_wake_up_dur_t wake_up_dur; lsm6dsr_free_fall_t free_fall; @@ -6361,7 +6371,7 @@ int32_t lsm6dsr_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsr_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val) { lsm6dsr_fifo_ctrl1_t fifo_ctrl1; lsm6dsr_fifo_ctrl2_t fifo_ctrl2; @@ -6395,7 +6405,7 @@ int32_t lsm6dsr_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsr_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dsr_fifo_ctrl1_t fifo_ctrl1; lsm6dsr_fifo_ctrl2_t fifo_ctrl2; @@ -6425,7 +6435,7 @@ int32_t lsm6dsr_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_compression_algo_init_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_compression_algo_init_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_emb_func_init_b_t emb_func_init_b; @@ -6463,7 +6473,7 @@ int32_t lsm6dsr_compression_algo_init_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_compression_algo_init_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_compression_algo_init_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_emb_func_init_b_t emb_func_init_b; @@ -6494,7 +6504,7 @@ int32_t lsm6dsr_compression_algo_init_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_compression_algo_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_compression_algo_set(const stmdev_ctx_t *ctx, lsm6dsr_uncoptr_rate_t val) { lsm6dsr_fifo_ctrl2_t fifo_ctrl2; @@ -6550,7 +6560,7 @@ int32_t lsm6dsr_compression_algo_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_compression_algo_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_compression_algo_get(const stmdev_ctx_t *ctx, lsm6dsr_uncoptr_rate_t *val) { lsm6dsr_fifo_ctrl2_t fifo_ctrl2; @@ -6598,7 +6608,7 @@ int32_t lsm6dsr_compression_algo_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_fifo_ctrl2_t fifo_ctrl2; @@ -6625,7 +6635,7 @@ int32_t lsm6dsr_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_fifo_ctrl2_t fifo_ctrl2; @@ -6646,7 +6656,7 @@ int32_t lsm6dsr_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_compression_algo_real_time_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_compression_algo_real_time_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_fifo_ctrl2_t fifo_ctrl2; @@ -6673,7 +6683,7 @@ int32_t lsm6dsr_compression_algo_real_time_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_compression_algo_real_time_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_compression_algo_real_time_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_fifo_ctrl2_t fifo_ctrl2; @@ -6695,7 +6705,7 @@ int32_t lsm6dsr_compression_algo_real_time_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -6722,7 +6732,7 @@ int32_t lsm6dsr_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -6743,7 +6753,7 @@ int32_t lsm6dsr_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_xl_batch_set(const stmdev_ctx_t *ctx, lsm6dsr_bdr_xl_t val) { lsm6dsr_fifo_ctrl3_t fifo_ctrl3; @@ -6771,7 +6781,7 @@ int32_t lsm6dsr_fifo_xl_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_xl_batch_get(const stmdev_ctx_t *ctx, lsm6dsr_bdr_xl_t *val) { lsm6dsr_fifo_ctrl3_t fifo_ctrl3; @@ -6847,7 +6857,7 @@ int32_t lsm6dsr_fifo_xl_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_gy_batch_set(const stmdev_ctx_t *ctx, lsm6dsr_bdr_gy_t val) { lsm6dsr_fifo_ctrl3_t fifo_ctrl3; @@ -6875,7 +6885,7 @@ int32_t lsm6dsr_fifo_gy_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_gy_batch_get(const stmdev_ctx_t *ctx, lsm6dsr_bdr_gy_t *val) { lsm6dsr_fifo_ctrl3_t fifo_ctrl3; @@ -6950,7 +6960,7 @@ int32_t lsm6dsr_fifo_gy_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_fifo_mode_t val) { lsm6dsr_fifo_ctrl4_t fifo_ctrl4; @@ -6977,7 +6987,7 @@ int32_t lsm6dsr_fifo_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_fifo_mode_t *val) { lsm6dsr_fifo_ctrl4_t fifo_ctrl4; @@ -7029,7 +7039,7 @@ int32_t lsm6dsr_fifo_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_temp_batch_set(const stmdev_ctx_t *ctx, lsm6dsr_odr_t_batch_t val) { lsm6dsr_fifo_ctrl4_t fifo_ctrl4; @@ -7057,7 +7067,7 @@ int32_t lsm6dsr_fifo_temp_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_temp_batch_get(const stmdev_ctx_t *ctx, lsm6dsr_odr_t_batch_t *val) { lsm6dsr_fifo_ctrl4_t fifo_ctrl4; @@ -7102,7 +7112,7 @@ int32_t lsm6dsr_fifo_temp_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, lsm6dsr_odr_ts_batch_t val) { lsm6dsr_fifo_ctrl4_t fifo_ctrl4; @@ -7132,7 +7142,7 @@ int32_t lsm6dsr_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, lsm6dsr_odr_ts_batch_t *val) { lsm6dsr_fifo_ctrl4_t fifo_ctrl4; @@ -7177,7 +7187,7 @@ int32_t lsm6dsr_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, lsm6dsr_trig_counter_bdr_t val) { lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1; @@ -7206,7 +7216,7 @@ int32_t lsm6dsr_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, lsm6dsr_trig_counter_bdr_t *val) { lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1; @@ -7242,7 +7252,7 @@ int32_t lsm6dsr_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1; int32_t ret; @@ -7269,7 +7279,7 @@ int32_t lsm6dsr_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1; int32_t ret; @@ -7290,7 +7300,7 @@ int32_t lsm6dsr_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_batch_counter_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { lsm6dsr_counter_bdr_reg2_t counter_bdr_reg1; @@ -7326,7 +7336,7 @@ int32_t lsm6dsr_batch_counter_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1; @@ -7357,7 +7367,7 @@ int32_t lsm6dsr_batch_counter_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsr_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dsr_fifo_status1_t fifo_status1; lsm6dsr_fifo_status2_t fifo_status2; @@ -7386,7 +7396,7 @@ int32_t lsm6dsr_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_status_get(const stmdev_ctx_t *ctx, lsm6dsr_fifo_status2_t *val) { int32_t ret; @@ -7404,7 +7414,7 @@ int32_t lsm6dsr_fifo_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_fifo_status2_t fifo_status2; int32_t ret; @@ -7425,7 +7435,7 @@ int32_t lsm6dsr_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_fifo_status2_t fifo_status2; int32_t ret; @@ -7445,7 +7455,7 @@ int32_t lsm6dsr_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_fifo_status2_t fifo_status2; int32_t ret; @@ -7465,7 +7475,7 @@ int32_t lsm6dsr_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fifo_sensor_tag_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, lsm6dsr_fifo_tag_t *val) { lsm6dsr_fifo_data_out_tag_t fifo_data_out_tag; @@ -7581,7 +7591,7 @@ int32_t lsm6dsr_fifo_sensor_tag_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_emb_func_fifo_cfg_t emb_func_fifo_cfg; int32_t ret; @@ -7618,7 +7628,7 @@ int32_t lsm6dsr_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_emb_func_fifo_cfg_t emb_func_fifo_cfg; int32_t ret; @@ -7648,7 +7658,7 @@ int32_t lsm6dsr_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_slv0_config_t slv0_config; int32_t ret; @@ -7685,7 +7695,7 @@ int32_t lsm6dsr_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_slv0_config_t slv0_config; int32_t ret; @@ -7716,7 +7726,7 @@ int32_t lsm6dsr_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_slv1_config_t slv1_config; int32_t ret; @@ -7753,7 +7763,7 @@ int32_t lsm6dsr_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_slv1_config_t slv1_config; int32_t ret; @@ -7784,7 +7794,7 @@ int32_t lsm6dsr_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_slv2_config_t slv2_config; int32_t ret; @@ -7821,7 +7831,7 @@ int32_t lsm6dsr_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_slv2_config_t slv2_config; int32_t ret; @@ -7852,7 +7862,7 @@ int32_t lsm6dsr_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_slv3_config_t slv3_config; int32_t ret; @@ -7889,7 +7899,7 @@ int32_t lsm6dsr_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_slv3_config_t slv3_config; int32_t ret; @@ -7932,7 +7942,7 @@ int32_t lsm6dsr_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_den_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_den_mode_t val) { lsm6dsr_ctrl6_c_t ctrl6_c; @@ -7957,7 +7967,7 @@ int32_t lsm6dsr_den_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_den_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_den_mode_t *val) { lsm6dsr_ctrl6_c_t ctrl6_c; @@ -8003,7 +8013,7 @@ int32_t lsm6dsr_den_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dsr_den_lh_t val) { lsm6dsr_ctrl9_xl_t ctrl9_xl; @@ -8029,7 +8039,7 @@ int32_t lsm6dsr_den_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dsr_den_lh_t *val) { lsm6dsr_ctrl9_xl_t ctrl9_xl; @@ -8063,7 +8073,7 @@ int32_t lsm6dsr_den_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_den_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_den_enable_set(const stmdev_ctx_t *ctx, lsm6dsr_den_xl_g_t val) { lsm6dsr_ctrl9_xl_t ctrl9_xl; @@ -8089,7 +8099,7 @@ int32_t lsm6dsr_den_enable_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_den_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_den_enable_get(const stmdev_ctx_t *ctx, lsm6dsr_den_xl_g_t *val) { lsm6dsr_ctrl9_xl_t ctrl9_xl; @@ -8127,7 +8137,7 @@ int32_t lsm6dsr_den_enable_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -8152,7 +8162,7 @@ int32_t lsm6dsr_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -8171,7 +8181,7 @@ int32_t lsm6dsr_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -8196,7 +8206,7 @@ int32_t lsm6dsr_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -8215,7 +8225,7 @@ int32_t lsm6dsr_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -8239,7 +8249,7 @@ int32_t lsm6dsr_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -8270,7 +8280,7 @@ int32_t lsm6dsr_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -8306,7 +8316,7 @@ int32_t lsm6dsr_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -8339,7 +8349,7 @@ int32_t lsm6dsr_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_pedo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pedo_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_pedo_mode_t val) { lsm6dsr_adv_pedo_t adv_pedo; @@ -8406,7 +8416,7 @@ int32_t lsm6dsr_pedo_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_pedo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pedo_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_pedo_mode_t *val) { lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg; @@ -8446,7 +8456,7 @@ int32_t lsm6dsr_pedo_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_pedo_step_detect_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_emb_func_status_t emb_func_status; int32_t ret; @@ -8476,7 +8486,7 @@ int32_t lsm6dsr_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_pedo_debounce_steps_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -8495,7 +8505,7 @@ int32_t lsm6dsr_pedo_debounce_steps_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_pedo_debounce_steps_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -8513,7 +8523,7 @@ int32_t lsm6dsr_pedo_debounce_steps_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_pedo_steps_period_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsr_pedo_steps_period_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -8540,7 +8550,7 @@ int32_t lsm6dsr_pedo_steps_period_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_pedo_steps_period_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pedo_steps_period_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -8568,7 +8578,7 @@ int32_t lsm6dsr_pedo_steps_period_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_pedo_adv_detection_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_pedo_adv_detection_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg; int32_t ret; @@ -8594,7 +8604,7 @@ int32_t lsm6dsr_pedo_adv_detection_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_pedo_adv_detection_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pedo_adv_detection_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg; @@ -8615,7 +8625,7 @@ int32_t lsm6dsr_pedo_adv_detection_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_pedo_false_step_rejection_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pedo_false_step_rejection_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg; @@ -8642,7 +8652,7 @@ int32_t lsm6dsr_pedo_false_step_rejection_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_pedo_false_step_rejection_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pedo_false_step_rejection_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg; @@ -8664,7 +8674,7 @@ int32_t lsm6dsr_pedo_false_step_rejection_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_pedo_int_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pedo_int_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_carry_count_en_t val) { lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg; @@ -8692,7 +8702,7 @@ int32_t lsm6dsr_pedo_int_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_pedo_int_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pedo_int_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_carry_count_en_t *val) { lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg; @@ -8740,7 +8750,7 @@ int32_t lsm6dsr_pedo_int_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -8776,7 +8786,7 @@ int32_t lsm6dsr_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -8806,7 +8816,7 @@ int32_t lsm6dsr_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_motion_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_motion_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_emb_func_status_t emb_func_status; @@ -8850,7 +8860,7 @@ int32_t lsm6dsr_motion_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -8886,7 +8896,7 @@ int32_t lsm6dsr_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -8916,7 +8926,7 @@ int32_t lsm6dsr_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_emb_func_status_t emb_func_status; @@ -8960,7 +8970,7 @@ int32_t lsm6dsr_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsr_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -8987,7 +8997,7 @@ int32_t lsm6dsr_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsr_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -9014,7 +9024,7 @@ int32_t lsm6dsr_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsr_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -9070,7 +9080,7 @@ int32_t lsm6dsr_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsr_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -9131,7 +9141,7 @@ int32_t lsm6dsr_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_mag_soft_iron_set(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsr_mag_soft_iron_set(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[12]; int32_t ret; @@ -9234,7 +9244,7 @@ int32_t lsm6dsr_mag_soft_iron_set(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_mag_soft_iron_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsr_mag_soft_iron_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[12]; int32_t ret; @@ -9334,7 +9344,7 @@ int32_t lsm6dsr_mag_soft_iron_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_mag_z_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_mag_z_orient_set(const stmdev_ctx_t *ctx, lsm6dsr_mag_z_axis_t val) { lsm6dsr_mag_cfg_a_t mag_cfg_a; @@ -9362,7 +9372,7 @@ int32_t lsm6dsr_mag_z_orient_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_mag_z_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_mag_z_orient_get(const stmdev_ctx_t *ctx, lsm6dsr_mag_z_axis_t *val) { lsm6dsr_mag_cfg_a_t mag_cfg_a; @@ -9415,7 +9425,7 @@ int32_t lsm6dsr_mag_z_orient_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_mag_y_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_mag_y_orient_set(const stmdev_ctx_t *ctx, lsm6dsr_mag_y_axis_t val) { lsm6dsr_mag_cfg_a_t mag_cfg_a; @@ -9443,7 +9453,7 @@ int32_t lsm6dsr_mag_y_orient_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_mag_y_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_mag_y_orient_get(const stmdev_ctx_t *ctx, lsm6dsr_mag_y_axis_t *val) { lsm6dsr_mag_cfg_a_t mag_cfg_a; @@ -9495,7 +9505,7 @@ int32_t lsm6dsr_mag_y_orient_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_mag_x_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_mag_x_orient_set(const stmdev_ctx_t *ctx, lsm6dsr_mag_x_axis_t val) { lsm6dsr_mag_cfg_b_t mag_cfg_b; @@ -9523,7 +9533,7 @@ int32_t lsm6dsr_mag_x_orient_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_mag_x_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_mag_x_orient_get(const stmdev_ctx_t *ctx, lsm6dsr_mag_x_axis_t *val) { lsm6dsr_mag_cfg_b_t mag_cfg_b; @@ -9588,7 +9598,7 @@ int32_t lsm6dsr_mag_x_orient_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_emb_func_status_t emb_func_status; @@ -9619,7 +9629,7 @@ int32_t lsm6dsr_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; @@ -9655,7 +9665,7 @@ int32_t lsm6dsr_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -9691,7 +9701,7 @@ int32_t lsm6dsr_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fsm_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fsm_enable_set(const stmdev_ctx_t *ctx, lsm6dsr_emb_fsm_enable_t *val) { lsm6dsr_emb_func_en_b_t emb_func_en_b; @@ -9767,7 +9777,7 @@ int32_t lsm6dsr_fsm_enable_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fsm_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fsm_enable_get(const stmdev_ctx_t *ctx, lsm6dsr_emb_fsm_enable_t *val) { int32_t ret; @@ -9803,7 +9813,7 @@ int32_t lsm6dsr_fsm_enable_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsr_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -9834,7 +9844,7 @@ int32_t lsm6dsr_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsr_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -9865,7 +9875,7 @@ int32_t lsm6dsr_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_long_clr_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_long_clr_set(const stmdev_ctx_t *ctx, lsm6dsr_fsm_lc_clr_t val) { lsm6dsr_fsm_long_counter_clear_t fsm_long_counter_clear; @@ -9902,7 +9912,7 @@ int32_t lsm6dsr_long_clr_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_long_clr_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_long_clr_get(const stmdev_ctx_t *ctx, lsm6dsr_fsm_lc_clr_t *val) { lsm6dsr_fsm_long_counter_clear_t fsm_long_counter_clear; @@ -9951,7 +9961,7 @@ int32_t lsm6dsr_long_clr_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsr_fsm_out_t *val) +int32_t lsm6dsr_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dsr_fsm_out_t *val) { int32_t ret; @@ -9979,7 +9989,7 @@ int32_t lsm6dsr_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsr_fsm_out_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fsm_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fsm_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsr_fsm_odr_t val) { lsm6dsr_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; @@ -10018,7 +10028,7 @@ int32_t lsm6dsr_fsm_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fsm_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fsm_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsr_fsm_odr_t *val) { lsm6dsr_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; @@ -10071,7 +10081,7 @@ int32_t lsm6dsr_fsm_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_emb_func_init_b_t emb_func_init_b; int32_t ret; @@ -10107,7 +10117,7 @@ int32_t lsm6dsr_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_emb_func_init_b_t emb_func_init_b; int32_t ret; @@ -10140,7 +10150,7 @@ int32_t lsm6dsr_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_long_cnt_int_value_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; @@ -10171,7 +10181,7 @@ int32_t lsm6dsr_long_cnt_int_value_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_long_cnt_int_value_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -10199,7 +10209,7 @@ int32_t lsm6dsr_long_cnt_int_value_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fsm_number_of_programs_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -10223,7 +10233,7 @@ int32_t lsm6dsr_fsm_number_of_programs_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fsm_number_of_programs_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -10242,7 +10252,7 @@ int32_t lsm6dsr_fsm_number_of_programs_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsr_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -10270,7 +10280,7 @@ int32_t lsm6dsr_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_fsm_start_address_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -10309,7 +10319,7 @@ int32_t lsm6dsr_fsm_start_address_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_read_data_raw_get(const stmdev_ctx_t *ctx, lsm6dsr_emb_sh_read_t *val) { int32_t ret; @@ -10337,7 +10347,7 @@ int32_t lsm6dsr_sh_read_data_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_slave_connected_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_slave_connected_set(const stmdev_ctx_t *ctx, lsm6dsr_aux_sens_on_t val) { lsm6dsr_master_config_t master_config; @@ -10374,7 +10384,7 @@ int32_t lsm6dsr_sh_slave_connected_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_slave_connected_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_slave_connected_get(const stmdev_ctx_t *ctx, lsm6dsr_aux_sens_on_t *val) { lsm6dsr_master_config_t master_config; @@ -10427,7 +10437,7 @@ int32_t lsm6dsr_sh_slave_connected_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_master_config_t master_config; int32_t ret; @@ -10463,7 +10473,7 @@ int32_t lsm6dsr_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_master_config_t master_config; int32_t ret; @@ -10493,7 +10503,7 @@ int32_t lsm6dsr_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_shub_pu_en_t val) { lsm6dsr_master_config_t master_config; @@ -10530,7 +10540,7 @@ int32_t lsm6dsr_sh_pin_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_shub_pu_en_t *val) { lsm6dsr_master_config_t master_config; @@ -10575,7 +10585,7 @@ int32_t lsm6dsr_sh_pin_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_master_config_t master_config; int32_t ret; @@ -10611,7 +10621,7 @@ int32_t lsm6dsr_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_master_config_t master_config; int32_t ret; @@ -10641,7 +10651,7 @@ int32_t lsm6dsr_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_syncro_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_start_config_t val) { lsm6dsr_master_config_t master_config; @@ -10678,7 +10688,7 @@ int32_t lsm6dsr_sh_syncro_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_syncro_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_start_config_t *val) { lsm6dsr_master_config_t master_config; @@ -10724,7 +10734,7 @@ int32_t lsm6dsr_sh_syncro_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_write_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_write_once_t val) { lsm6dsr_master_config_t master_config; @@ -10762,7 +10772,7 @@ int32_t lsm6dsr_sh_write_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_write_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_write_once_t *val) { lsm6dsr_master_config_t master_config; @@ -10806,7 +10816,7 @@ int32_t lsm6dsr_sh_write_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_reset_set(stmdev_ctx_t *ctx) +int32_t lsm6dsr_sh_reset_set(const stmdev_ctx_t *ctx) { lsm6dsr_master_config_t master_config; int32_t ret; @@ -10849,7 +10859,7 @@ int32_t lsm6dsr_sh_reset_set(stmdev_ctx_t *ctx) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_master_config_t master_config; int32_t ret; @@ -10879,7 +10889,7 @@ int32_t lsm6dsr_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsr_shub_odr_t val) { lsm6dsr_slv0_config_t slv0_config; @@ -10916,7 +10926,7 @@ int32_t lsm6dsr_sh_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsr_shub_odr_t *val) { lsm6dsr_slv0_config_t slv0_config; @@ -10972,7 +10982,7 @@ int32_t lsm6dsr_sh_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_cfg_write(const stmdev_ctx_t *ctx, lsm6dsr_sh_cfg_write_t *val) { lsm6dsr_slv0_add_t slv0_add; @@ -11019,7 +11029,7 @@ int32_t lsm6dsr_sh_cfg_write(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_slv0_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, lsm6dsr_sh_cfg_read_t *val) { lsm6dsr_slv0_config_t slv0_config; @@ -11074,7 +11084,7 @@ int32_t lsm6dsr_sh_slv0_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_slv1_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, lsm6dsr_sh_cfg_read_t *val) { lsm6dsr_slv1_config_t slv1_config; @@ -11128,7 +11138,7 @@ int32_t lsm6dsr_sh_slv1_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_slv2_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, lsm6dsr_sh_cfg_read_t *val) { lsm6dsr_slv2_config_t slv2_config; @@ -11183,7 +11193,7 @@ int32_t lsm6dsr_sh_slv2_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_slv3_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, lsm6dsr_sh_cfg_read_t *val) { lsm6dsr_slv3_config_t slv3_config; @@ -11235,7 +11245,7 @@ int32_t lsm6dsr_sh_slv3_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_sh_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_status_get(const stmdev_ctx_t *ctx, lsm6dsr_status_master_t *val) { int32_t ret; @@ -11276,7 +11286,7 @@ int32_t lsm6dsr_sh_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_s4s_tph_res_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_s4s_tph_res_set(const stmdev_ctx_t *ctx, lsm6dsr_s4s_tph_res_t val) { lsm6dsr_s4s_tph_l_t s4s_tph_l; @@ -11302,7 +11312,7 @@ int32_t lsm6dsr_s4s_tph_res_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_s4s_tph_res_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_s4s_tph_res_get(const stmdev_ctx_t *ctx, lsm6dsr_s4s_tph_res_t *val) { lsm6dsr_s4s_tph_l_t s4s_tph_l; @@ -11337,7 +11347,7 @@ int32_t lsm6dsr_s4s_tph_res_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_s4s_tph_val_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsr_s4s_tph_val_set(const stmdev_ctx_t *ctx, uint16_t val) { lsm6dsr_s4s_tph_l_t s4s_tph_l; lsm6dsr_s4s_tph_h_t s4s_tph_h; @@ -11376,7 +11386,7 @@ int32_t lsm6dsr_s4s_tph_val_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_s4s_tph_val_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsr_s4s_tph_val_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dsr_s4s_tph_l_t s4s_tph_l; lsm6dsr_s4s_tph_h_t s4s_tph_h; @@ -11405,7 +11415,7 @@ int32_t lsm6dsr_s4s_tph_val_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_s4s_res_ratio_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_s4s_res_ratio_set(const stmdev_ctx_t *ctx, lsm6dsr_s4s_res_ratio_t val) { lsm6dsr_s4s_rr_t s4s_rr; @@ -11430,7 +11440,7 @@ int32_t lsm6dsr_s4s_res_ratio_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_s4s_res_ratio_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_s4s_res_ratio_get(const stmdev_ctx_t *ctx, lsm6dsr_s4s_res_ratio_t *val) { lsm6dsr_s4s_rr_t s4s_rr; @@ -11472,7 +11482,7 @@ int32_t lsm6dsr_s4s_res_ratio_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_s4s_command_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_s4s_command_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_s4s_st_cmd_code_t s4s_st_cmd_code; int32_t ret; @@ -11498,7 +11508,7 @@ int32_t lsm6dsr_s4s_command_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_s4s_command_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_s4s_command_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_s4s_st_cmd_code_t s4s_st_cmd_code; int32_t ret; @@ -11518,7 +11528,7 @@ int32_t lsm6dsr_s4s_command_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_s4s_dt_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsr_s4s_dt_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsr_s4s_dt_reg_t s4s_dt_reg; int32_t ret; @@ -11544,7 +11554,7 @@ int32_t lsm6dsr_s4s_dt_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsr_s4s_dt_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsr_s4s_dt_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsr_s4s_dt_reg_t s4s_dt_reg; int32_t ret; diff --git a/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.h b/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.h index 1321ee94..2719bfcf 100644 --- a/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.h +++ b/sensor/stmemsc/lsm6dsr_STdC/driver/lsm6dsr_reg.h @@ -185,11 +185,9 @@ typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t not_used_01 : 6; -uint8_t reg_access : - 2; /* shub_reg_access + func_cfg_access */ + uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */ #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN -uint8_t reg_access : - 2; /* shub_reg_access + func_cfg_access */ + uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */ uint8_t not_used_01 : 6; #endif /* DRV_BYTE_ORDER */ } lsm6dsr_func_cfg_access_t; @@ -468,11 +466,9 @@ typedef struct uint8_t ftype : 3; uint8_t usr_off_w : 1; uint8_t xl_hm_mode : 1; -uint8_t den_mode : - 3; /* trig_en + lvl1_en + lvl2_en */ + uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN -uint8_t den_mode : - 3; /* trig_en + lvl1_en + lvl2_en */ + uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ uint8_t xl_hm_mode : 1; uint8_t usr_off_w : 1; uint8_t ftype : 3; @@ -1480,13 +1476,11 @@ typedef struct typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN -uint8_t fsm_lc_clr : - 2; /* fsm_lc_cleared + fsm_lc_clear */ + uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ uint8_t not_used_01 : 6; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN uint8_t not_used_01 : 6; -uint8_t fsm_lc_clr : - 2; /* fsm_lc_cleared + fsm_lc_clear */ + uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ #endif /* DRV_BYTE_ORDER */ } lsm6dsr_fsm_long_counter_clear_t; @@ -2793,10 +2787,10 @@ typedef union * them with a custom implementation. */ -int32_t lsm6dsr_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm6dsr_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lsm6dsr_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm6dsr_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -2823,9 +2817,9 @@ typedef enum LSM6DSR_4g = 2, LSM6DSR_8g = 3, } lsm6dsr_fs_xl_t; -int32_t lsm6dsr_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsr_fs_xl_t val); -int32_t lsm6dsr_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsr_fs_xl_t *val); typedef enum @@ -2843,9 +2837,9 @@ typedef enum LSM6DSR_XL_ODR_6667Hz = 10, LSM6DSR_XL_ODR_1Hz6 = 11, /* (low power only) */ } lsm6dsr_odr_xl_t; -int32_t lsm6dsr_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsr_odr_xl_t val); -int32_t lsm6dsr_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsr_odr_xl_t *val); typedef enum @@ -2857,9 +2851,9 @@ typedef enum LSM6DSR_2000dps = 12, LSM6DSR_4000dps = 1, } lsm6dsr_fs_g_t; -int32_t lsm6dsr_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsr_fs_g_t val); -int32_t lsm6dsr_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsr_fs_g_t *val); typedef enum @@ -2876,13 +2870,13 @@ typedef enum LSM6DSR_GY_ODR_3332Hz = 9, LSM6DSR_GY_ODR_6667Hz = 10, } lsm6dsr_odr_g_t; -int32_t lsm6dsr_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_gy_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsr_odr_g_t val); -int32_t lsm6dsr_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsr_odr_g_t *val); -int32_t lsm6dsr_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2890,9 +2884,9 @@ typedef enum LSM6DSR_LSb_1mg = 0, LSM6DSR_LSb_16mg = 1, } lsm6dsr_usr_off_w_t; -int32_t lsm6dsr_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_offset_weight_set(const stmdev_ctx_t *ctx, lsm6dsr_usr_off_w_t val); -int32_t lsm6dsr_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_offset_weight_get(const stmdev_ctx_t *ctx, lsm6dsr_usr_off_w_t *val); typedef enum @@ -2900,9 +2894,9 @@ typedef enum LSM6DSR_HIGH_PERFORMANCE_MD = 0, LSM6DSR_LOW_NORMAL_POWER_MD = 1, } lsm6dsr_xl_hm_mode_t; -int32_t lsm6dsr_xl_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_power_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_xl_hm_mode_t val); -int32_t lsm6dsr_xl_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_power_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_xl_hm_mode_t *val); typedef enum @@ -2910,9 +2904,9 @@ typedef enum LSM6DSR_GY_HIGH_PERFORMANCE = 0, LSM6DSR_GY_NORMAL = 1, } lsm6dsr_g_hm_mode_t; -int32_t lsm6dsr_gy_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_gy_power_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_g_hm_mode_t val); -int32_t lsm6dsr_gy_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_gy_power_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_g_hm_mode_t *val); typedef struct @@ -2926,39 +2920,39 @@ typedef struct lsm6dsr_fsm_status_a_t fsm_status_a; lsm6dsr_fsm_status_b_t fsm_status_b; } lsm6dsr_all_sources_t; -int32_t lsm6dsr_all_sources_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_all_sources_get(const stmdev_ctx_t *ctx, lsm6dsr_all_sources_t *val); -int32_t lsm6dsr_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_status_reg_get(const stmdev_ctx_t *ctx, lsm6dsr_status_reg_t *val); -int32_t lsm6dsr_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsr_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsr_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsr_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsr_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsr_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsr_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsr_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsr_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsr_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsr_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsr_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsr_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_timestamp_rst(stmdev_ctx_t *ctx); +int32_t lsm6dsr_timestamp_rst(const stmdev_ctx_t *ctx); -int32_t lsm6dsr_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); +int32_t lsm6dsr_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); typedef enum { @@ -2967,25 +2961,25 @@ typedef enum LSM6DSR_ROUND_GY = 2, LSM6DSR_ROUND_GY_XL = 3, } lsm6dsr_rounding_t; -int32_t lsm6dsr_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_rounding_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_rounding_t val); -int32_t lsm6dsr_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_rounding_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_rounding_t *val); -int32_t lsm6dsr_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsr_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsr_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsr_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsr_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsr_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsr_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsr_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsr_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsr_number_of_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsr_steps_reset(stmdev_ctx_t *ctx); +int32_t lsm6dsr_steps_reset(const stmdev_ctx_t *ctx); typedef enum { @@ -2993,18 +2987,18 @@ typedef enum LSM6DSR_SENSOR_HUB_BANK = 1, LSM6DSR_EMBEDDED_FUNC_BANK = 2, } lsm6dsr_reg_access_t; -int32_t lsm6dsr_mem_bank_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dsr_reg_access_t val); -int32_t lsm6dsr_mem_bank_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dsr_reg_access_t *val); -int32_t lsm6dsr_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dsr_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val); -int32_t lsm6dsr_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dsr_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); -int32_t lsm6dsr_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add, +int32_t lsm6dsr_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, uint8_t *val); -int32_t lsm6dsr_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dsr_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val); typedef enum @@ -3012,21 +3006,21 @@ typedef enum LSM6DSR_DRDY_LATCHED = 0, LSM6DSR_DRDY_PULSED = 1, } lsm6dsr_dataready_pulsed_t; -int32_t lsm6dsr_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_dataready_pulsed_t val); -int32_t lsm6dsr_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_dataready_pulsed_t *val); -int32_t lsm6dsr_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsr_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsr_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3034,9 +3028,9 @@ typedef enum LSM6DSR_XL_ST_POSITIVE = 1, LSM6DSR_XL_ST_NEGATIVE = 2, } lsm6dsr_st_xl_t; -int32_t lsm6dsr_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dsr_st_xl_t val); -int32_t lsm6dsr_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dsr_st_xl_t *val); typedef enum @@ -3045,20 +3039,20 @@ typedef enum LSM6DSR_GY_ST_POSITIVE = 1, LSM6DSR_GY_ST_NEGATIVE = 3, } lsm6dsr_st_g_t; -int32_t lsm6dsr_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dsr_st_g_t val); -int32_t lsm6dsr_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dsr_st_g_t *val); -int32_t lsm6dsr_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3072,13 +3066,13 @@ typedef enum LSM6DSR_AGGRESSIVE = 6, LSM6DSR_XTREME = 7, } lsm6dsr_ftype_t; -int32_t lsm6dsr_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsr_ftype_t val); -int32_t lsm6dsr_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsr_ftype_t *val); -int32_t lsm6dsr_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3106,22 +3100,22 @@ typedef enum LSM6DSR_LP_ODR_DIV_400 = 0x06, LSM6DSR_LP_ODR_DIV_800 = 0x07, } lsm6dsr_hp_slope_xl_en_t; -int32_t lsm6dsr_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, lsm6dsr_hp_slope_xl_en_t val); -int32_t lsm6dsr_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, lsm6dsr_hp_slope_xl_en_t *val); -int32_t lsm6dsr_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSR_USE_SLOPE = 0, LSM6DSR_USE_HPF = 1, } lsm6dsr_slope_fds_t; -int32_t lsm6dsr_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dsr_slope_fds_t val); -int32_t lsm6dsr_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dsr_slope_fds_t *val); typedef enum @@ -3132,9 +3126,9 @@ typedef enum LSM6DSR_HP_FILTER_260mHz = 0x82, LSM6DSR_HP_FILTER_1Hz04 = 0x83, } lsm6dsr_hpm_g_t; -int32_t lsm6dsr_gy_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dsr_hpm_g_t val); -int32_t lsm6dsr_gy_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dsr_hpm_g_t *val); typedef enum @@ -3142,9 +3136,9 @@ typedef enum LSM6DSR_AUX_PULL_UP_DISC = 0, LSM6DSR_AUX_PULL_UP_CONNECT = 1, } lsm6dsr_ois_pu_dis_t; -int32_t lsm6dsr_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_sdo_ocs_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_ois_pu_dis_t val); -int32_t lsm6dsr_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_sdo_ocs_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_ois_pu_dis_t *val); typedef enum @@ -3152,21 +3146,21 @@ typedef enum LSM6DSR_AUX_ON = 1, LSM6DSR_AUX_ON_BY_AUX_INTERFACE = 0, } lsm6dsr_ois_on_t; -int32_t lsm6dsr_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_pw_on_ctrl_set(const stmdev_ctx_t *ctx, lsm6dsr_ois_on_t val); -int32_t lsm6dsr_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_pw_on_ctrl_get(const stmdev_ctx_t *ctx, lsm6dsr_ois_on_t *val); -int32_t lsm6dsr_aux_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_status_reg_get(const stmdev_ctx_t *ctx, lsm6dsr_status_spiaux_t *val); -int32_t lsm6dsr_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3175,9 +3169,9 @@ typedef enum LSM6DSR_AUX_XL_POS = 1, LSM6DSR_AUX_XL_NEG = 2, } lsm6dsr_st_xl_ois_t; -int32_t lsm6dsr_aux_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dsr_st_xl_ois_t val); -int32_t lsm6dsr_aux_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dsr_st_xl_ois_t *val); typedef enum @@ -3185,9 +3179,9 @@ typedef enum LSM6DSR_AUX_DEN_ACTIVE_LOW = 0, LSM6DSR_AUX_DEN_ACTIVE_HIGH = 1, } lsm6dsr_den_lh_ois_t; -int32_t lsm6dsr_aux_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dsr_den_lh_ois_t val); -int32_t lsm6dsr_aux_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dsr_den_lh_ois_t *val); typedef enum @@ -3196,13 +3190,13 @@ typedef enum LSM6DSR_AUX_DEN_LEVEL_LATCH = 3, LSM6DSR_AUX_DEN_LEVEL_TRIG = 2, } lsm6dsr_lvl2_ois_t; -int32_t lsm6dsr_aux_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_den_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_lvl2_ois_t val); -int32_t lsm6dsr_aux_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_den_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_lvl2_ois_t *val); -int32_t lsm6dsr_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_aux_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3210,9 +3204,9 @@ typedef enum LSM6DSR_MODE_3_GY = 1, LSM6DSR_MODE_4_GY_XL = 3, } lsm6dsr_ois_en_spi2_t; -int32_t lsm6dsr_aux_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_ois_en_spi2_t val); -int32_t lsm6dsr_aux_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_ois_en_spi2_t *val); typedef enum @@ -3223,9 +3217,9 @@ typedef enum LSM6DSR_1000dps_AUX = 0x02, LSM6DSR_2000dps_AUX = 0x03, } lsm6dsr_fs_g_ois_t; -int32_t lsm6dsr_aux_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsr_fs_g_ois_t val); -int32_t lsm6dsr_aux_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsr_fs_g_ois_t *val); typedef enum @@ -3233,9 +3227,9 @@ typedef enum LSM6DSR_AUX_SPI_4_WIRE = 0, LSM6DSR_AUX_SPI_3_WIRE = 1, } lsm6dsr_sim_ois_t; -int32_t lsm6dsr_aux_spi_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_sim_ois_t val); -int32_t lsm6dsr_aux_spi_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_sim_ois_t *val); typedef enum @@ -3245,9 +3239,9 @@ typedef enum LSM6DSR_172Hz70 = 2, LSM6DSR_937Hz91 = 3, } lsm6dsr_ftype_ois_t; -int32_t lsm6dsr_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsr_ftype_ois_t val); -int32_t lsm6dsr_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsr_ftype_ois_t *val); typedef enum @@ -3258,9 +3252,9 @@ typedef enum LSM6DSR_AUX_HP_Hz260 = 0x12, LSM6DSR_AUX_HP_1Hz040 = 0x13, } lsm6dsr_hpm_ois_t; -int32_t lsm6dsr_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_gy_hp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsr_hpm_ois_t val); -int32_t lsm6dsr_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_gy_hp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsr_hpm_ois_t *val); typedef enum @@ -3268,9 +3262,9 @@ typedef enum LSM6DSR_ENABLE_CLAMP = 0, LSM6DSR_DISABLE_CLAMP = 1, } lsm6dsr_st_ois_clampdis_t; -int32_t lsm6dsr_aux_gy_clamp_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_gy_clamp_set(const stmdev_ctx_t *ctx, lsm6dsr_st_ois_clampdis_t val); -int32_t lsm6dsr_aux_gy_clamp_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_gy_clamp_get(const stmdev_ctx_t *ctx, lsm6dsr_st_ois_clampdis_t *val); typedef enum @@ -3279,9 +3273,9 @@ typedef enum LSM6DSR_AUX_GY_POS = 1, LSM6DSR_AUX_GY_NEG = 3, } lsm6dsr_st_ois_t; -int32_t lsm6dsr_aux_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dsr_st_ois_t val); -int32_t lsm6dsr_aux_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dsr_st_ois_t *val); typedef enum @@ -3295,9 +3289,9 @@ typedef enum LSM6DSR_8Hz3 = 6, LSM6DSR_4Hz11 = 7, } lsm6dsr_filter_xl_conf_ois_t; -int32_t lsm6dsr_aux_xl_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_xl_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsr_filter_xl_conf_ois_t val); -int32_t lsm6dsr_aux_xl_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_xl_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsr_filter_xl_conf_ois_t *val); typedef enum @@ -3307,9 +3301,9 @@ typedef enum LSM6DSR_AUX_4g = 2, LSM6DSR_AUX_8g = 3, } lsm6dsr_fs_xl_ois_t; -int32_t lsm6dsr_aux_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsr_fs_xl_ois_t val); -int32_t lsm6dsr_aux_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_aux_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsr_fs_xl_ois_t *val); typedef enum @@ -3317,9 +3311,9 @@ typedef enum LSM6DSR_PULL_UP_DISC = 0, LSM6DSR_PULL_UP_CONNECT = 1, } lsm6dsr_sdo_pu_en_t; -int32_t lsm6dsr_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_sdo_pu_en_t val); -int32_t lsm6dsr_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_sdo_pu_en_t *val); typedef enum @@ -3327,9 +3321,9 @@ typedef enum LSM6DSR_PULL_DOWN_CONNECT = 0, LSM6DSR_PULL_DOWN_DISC = 1, } lsm6dsr_pd_dis_int1_t; -int32_t lsm6dsr_int1_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_int1_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_pd_dis_int1_t val); -int32_t lsm6dsr_int1_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_int1_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_pd_dis_int1_t *val); typedef enum @@ -3337,17 +3331,17 @@ typedef enum LSM6DSR_SPI_4_WIRE = 0, LSM6DSR_SPI_3_WIRE = 1, } lsm6dsr_sim_t; -int32_t lsm6dsr_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsr_sim_t val); -int32_t lsm6dsr_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsr_sim_t *val); +int32_t lsm6dsr_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_sim_t val); +int32_t lsm6dsr_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_sim_t *val); typedef enum { LSM6DSR_I2C_ENABLE = 0, LSM6DSR_I2C_DISABLE = 1, } lsm6dsr_i2c_disable_t; -int32_t lsm6dsr_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_i2c_interface_set(const stmdev_ctx_t *ctx, lsm6dsr_i2c_disable_t val); -int32_t lsm6dsr_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_i2c_interface_get(const stmdev_ctx_t *ctx, lsm6dsr_i2c_disable_t *val); typedef enum @@ -3358,9 +3352,9 @@ typedef enum LSM6DSR_I3C_ENABLE_T_1ms = 0x02, LSM6DSR_I3C_ENABLE_T_25ms = 0x03, } lsm6dsr_i3c_disable_t; -int32_t lsm6dsr_i3c_disable_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_i3c_disable_set(const stmdev_ctx_t *ctx, lsm6dsr_i3c_disable_t val); -int32_t lsm6dsr_i3c_disable_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_i3c_disable_get(const stmdev_ctx_t *ctx, lsm6dsr_i3c_disable_t *val); typedef struct @@ -3371,9 +3365,9 @@ typedef struct lsm6dsr_fsm_int1_a_t fsm_int1_a; lsm6dsr_fsm_int1_b_t fsm_int1_b; } lsm6dsr_pin_int1_route_t; -int32_t lsm6dsr_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm6dsr_pin_int1_route_t *val); -int32_t lsm6dsr_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm6dsr_pin_int1_route_t *val); typedef struct @@ -3384,9 +3378,9 @@ typedef struct lsm6dsr_fsm_int2_a_t fsm_int2_a; lsm6dsr_fsm_int2_b_t fsm_int2_b; } lsm6dsr_pin_int2_route_t; -int32_t lsm6dsr_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm6dsr_pin_int2_route_t *val); -int32_t lsm6dsr_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pin_int2_route_get(const stmdev_ctx_t *ctx, lsm6dsr_pin_int2_route_t *val); typedef enum @@ -3394,21 +3388,21 @@ typedef enum LSM6DSR_PUSH_PULL = 0, LSM6DSR_OPEN_DRAIN = 1, } lsm6dsr_pp_od_t; -int32_t lsm6dsr_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsr_pp_od_t val); -int32_t lsm6dsr_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsr_pp_od_t *val); +int32_t lsm6dsr_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_pp_od_t val); +int32_t lsm6dsr_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_pp_od_t *val); typedef enum { LSM6DSR_ACTIVE_HIGH = 0, LSM6DSR_ACTIVE_LOW = 1, } lsm6dsr_h_lactive_t; -int32_t lsm6dsr_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pin_polarity_set(const stmdev_ctx_t *ctx, lsm6dsr_h_lactive_t val); -int32_t lsm6dsr_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pin_polarity_get(const stmdev_ctx_t *ctx, lsm6dsr_h_lactive_t *val); -int32_t lsm6dsr_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3417,9 +3411,9 @@ typedef enum LSM6DSR_BASE_PULSED_EMB_LATCHED = 2, LSM6DSR_ALL_INT_LATCHED = 3, } lsm6dsr_lir_t; -int32_t lsm6dsr_int_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_int_notification_set(const stmdev_ctx_t *ctx, lsm6dsr_lir_t val); -int32_t lsm6dsr_int_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_int_notification_get(const stmdev_ctx_t *ctx, lsm6dsr_lir_t *val); typedef enum @@ -3427,33 +3421,33 @@ typedef enum LSM6DSR_LSb_FS_DIV_64 = 0, LSM6DSR_LSb_FS_DIV_256 = 1, } lsm6dsr_wake_ths_w_t; -int32_t lsm6dsr_wkup_ths_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_wkup_ths_weight_set(const stmdev_ctx_t *ctx, lsm6dsr_wake_ths_w_t val); -int32_t lsm6dsr_wkup_ths_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_wkup_ths_weight_get(const stmdev_ctx_t *ctx, lsm6dsr_wake_ths_w_t *val); -int32_t lsm6dsr_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSR_DRIVE_SLEEP_CHG_EVENT = 0, LSM6DSR_DRIVE_SLEEP_STATUS = 1, } lsm6dsr_sleep_status_on_int_t; -int32_t lsm6dsr_act_pin_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_act_pin_notification_set(const stmdev_ctx_t *ctx, lsm6dsr_sleep_status_on_int_t val); -int32_t lsm6dsr_act_pin_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_act_pin_notification_get(const stmdev_ctx_t *ctx, lsm6dsr_sleep_status_on_int_t *val); typedef enum @@ -3463,31 +3457,31 @@ typedef enum LSM6DSR_XL_12Hz5_GY_SLEEP = 2, LSM6DSR_XL_12Hz5_GY_PD = 3, } lsm6dsr_inact_en_t; -int32_t lsm6dsr_act_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_act_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_inact_en_t val); -int32_t lsm6dsr_act_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_act_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_inact_en_t *val); -int32_t lsm6dsr_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3498,34 +3492,34 @@ typedef enum LSM6DSR_YZX = 5, LSM6DSR_ZXY = 6, } lsm6dsr_tap_priority_t; -int32_t lsm6dsr_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_tap_axis_priority_set(const stmdev_ctx_t *ctx, lsm6dsr_tap_priority_t val); -int32_t lsm6dsr_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_tap_axis_priority_get(const stmdev_ctx_t *ctx, lsm6dsr_tap_priority_t *val); -int32_t lsm6dsr_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSR_ONLY_SINGLE = 0, LSM6DSR_BOTH_SINGLE_DOUBLE = 1, } lsm6dsr_single_double_tap_t; -int32_t lsm6dsr_tap_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_single_double_tap_t val); -int32_t lsm6dsr_tap_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_single_double_tap_t *val); typedef enum @@ -3535,13 +3529,13 @@ typedef enum LSM6DSR_DEG_60 = 2, LSM6DSR_DEG_50 = 3, } lsm6dsr_sixd_ths_t; -int32_t lsm6dsr_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_6d_threshold_set(const stmdev_ctx_t *ctx, lsm6dsr_sixd_ths_t val); -int32_t lsm6dsr_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_6d_threshold_get(const stmdev_ctx_t *ctx, lsm6dsr_sixd_ths_t *val); -int32_t lsm6dsr_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3554,20 +3548,20 @@ typedef enum LSM6DSR_FF_TSH_469mg = 6, LSM6DSR_FF_TSH_500mg = 7, } lsm6dsr_ff_ths_t; -int32_t lsm6dsr_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_ff_threshold_set(const stmdev_ctx_t *ctx, lsm6dsr_ff_ths_t val); -int32_t lsm6dsr_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_ff_threshold_get(const stmdev_ctx_t *ctx, lsm6dsr_ff_ths_t *val); -int32_t lsm6dsr_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsr_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsr_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsr_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsr_compression_algo_init_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_compression_algo_init_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_compression_algo_init_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_compression_algo_init_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3578,23 +3572,23 @@ typedef enum LSM6DSR_CMP_16_TO_1 = 0x06, LSM6DSR_CMP_32_TO_1 = 0x07, } lsm6dsr_uncoptr_rate_t; -int32_t lsm6dsr_compression_algo_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_compression_algo_set(const stmdev_ctx_t *ctx, lsm6dsr_uncoptr_rate_t val); -int32_t lsm6dsr_compression_algo_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_compression_algo_get(const stmdev_ctx_t *ctx, lsm6dsr_uncoptr_rate_t *val); -int32_t lsm6dsr_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_compression_algo_real_time_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_compression_algo_real_time_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_compression_algo_real_time_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_compression_algo_real_time_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3611,9 +3605,9 @@ typedef enum LSM6DSR_XL_BATCHED_AT_6667Hz = 10, LSM6DSR_XL_BATCHED_AT_6Hz5 = 11, } lsm6dsr_bdr_xl_t; -int32_t lsm6dsr_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_xl_batch_set(const stmdev_ctx_t *ctx, lsm6dsr_bdr_xl_t val); -int32_t lsm6dsr_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_xl_batch_get(const stmdev_ctx_t *ctx, lsm6dsr_bdr_xl_t *val); typedef enum @@ -3631,9 +3625,9 @@ typedef enum LSM6DSR_GY_BATCHED_AT_6667Hz = 10, LSM6DSR_GY_BATCHED_6Hz5 = 11, } lsm6dsr_bdr_gy_t; -int32_t lsm6dsr_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_gy_batch_set(const stmdev_ctx_t *ctx, lsm6dsr_bdr_gy_t val); -int32_t lsm6dsr_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_gy_batch_get(const stmdev_ctx_t *ctx, lsm6dsr_bdr_gy_t *val); typedef enum @@ -3645,9 +3639,9 @@ typedef enum LSM6DSR_STREAM_MODE = 6, LSM6DSR_BYPASS_TO_FIFO_MODE = 7, } lsm6dsr_fifo_mode_t; -int32_t lsm6dsr_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_fifo_mode_t val); -int32_t lsm6dsr_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_fifo_mode_t *val); typedef enum @@ -3657,9 +3651,9 @@ typedef enum LSM6DSR_TEMP_BATCHED_AT_12Hz5 = 2, LSM6DSR_TEMP_BATCHED_AT_1Hz6 = 3, } lsm6dsr_odr_t_batch_t; -int32_t lsm6dsr_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_temp_batch_set(const stmdev_ctx_t *ctx, lsm6dsr_odr_t_batch_t val); -int32_t lsm6dsr_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_temp_batch_get(const stmdev_ctx_t *ctx, lsm6dsr_odr_t_batch_t *val); typedef enum @@ -3669,9 +3663,9 @@ typedef enum LSM6DSR_DEC_8 = 2, LSM6DSR_DEC_32 = 3, } lsm6dsr_odr_ts_batch_t; -int32_t lsm6dsr_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, lsm6dsr_odr_ts_batch_t val); -int32_t lsm6dsr_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, lsm6dsr_odr_ts_batch_t *val); typedef enum @@ -3679,30 +3673,30 @@ typedef enum LSM6DSR_XL_BATCH_EVENT = 0, LSM6DSR_GYRO_BATCH_EVENT = 1, } lsm6dsr_trig_counter_bdr_t; -int32_t lsm6dsr_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, lsm6dsr_trig_counter_bdr_t val); -int32_t lsm6dsr_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, lsm6dsr_trig_counter_bdr_t *val); -int32_t lsm6dsr_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_rst_batch_counter_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_batch_counter_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsr_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsr_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsr_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsr_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_status_get(const stmdev_ctx_t *ctx, lsm6dsr_fifo_status2_t *val); -int32_t lsm6dsr_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3729,23 +3723,23 @@ typedef enum LSM6DSR_ROTATION_TAG, LSM6DSR_SENSORHUB_NACK_TAG = 0x19, } lsm6dsr_fifo_tag_t; -int32_t lsm6dsr_fifo_sensor_tag_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, lsm6dsr_fifo_tag_t *val); -int32_t lsm6dsr_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3755,9 +3749,9 @@ typedef enum LSM6DSR_LEVEL_TRIGGER = 2, LSM6DSR_EDGE_TRIGGER = 4, } lsm6dsr_den_mode_t; -int32_t lsm6dsr_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_den_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_den_mode_t val); -int32_t lsm6dsr_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_den_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_den_mode_t *val); typedef enum @@ -3765,9 +3759,9 @@ typedef enum LSM6DSR_DEN_ACT_LOW = 0, LSM6DSR_DEN_ACT_HIGH = 1, } lsm6dsr_den_lh_t; -int32_t lsm6dsr_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dsr_den_lh_t val); -int32_t lsm6dsr_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dsr_den_lh_t *val); typedef enum @@ -3776,22 +3770,22 @@ typedef enum LSM6DSR_STAMP_IN_XL_DATA = 1, LSM6DSR_STAMP_IN_GY_XL_DATA = 2, } lsm6dsr_den_xl_g_t; -int32_t lsm6dsr_den_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_den_enable_set(const stmdev_ctx_t *ctx, lsm6dsr_den_xl_g_t val); -int32_t lsm6dsr_den_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_den_enable_get(const stmdev_ctx_t *ctx, lsm6dsr_den_xl_g_t *val); -int32_t lsm6dsr_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3799,31 +3793,31 @@ typedef enum LSM6DSR_PEDO_BASE_FALSE_STEP_REJ = 0x01, LSM6DSR_PEDO_ADV_FALSE_STEP_REJ = 0x03, } lsm6dsr_pedo_mode_t; -int32_t lsm6dsr_pedo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pedo_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_pedo_mode_t val); -int32_t lsm6dsr_pedo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pedo_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_pedo_mode_t *val); -int32_t lsm6dsr_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_pedo_step_detect_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_pedo_debounce_steps_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsr_pedo_debounce_steps_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsr_pedo_steps_period_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pedo_steps_period_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsr_pedo_steps_period_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pedo_steps_period_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsr_pedo_adv_detection_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pedo_adv_detection_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_pedo_adv_detection_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pedo_adv_detection_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_pedo_false_step_rejection_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pedo_false_step_rejection_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_pedo_false_step_rejection_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pedo_false_step_rejection_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3831,31 +3825,31 @@ typedef enum LSM6DSR_EVERY_STEP = 0, LSM6DSR_COUNT_OVERFLOW = 1, } lsm6dsr_carry_count_en_t; -int32_t lsm6dsr_pedo_int_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pedo_int_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_carry_count_en_t val); -int32_t lsm6dsr_pedo_int_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_pedo_int_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_carry_count_en_t *val); -int32_t lsm6dsr_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_motion_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_motion_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsr_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsr_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsr_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsr_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsr_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsr_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsr_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsr_mag_soft_iron_set(stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsr_mag_soft_iron_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsr_mag_soft_iron_set(const stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsr_mag_soft_iron_get(const stmdev_ctx_t *ctx, int16_t *val); typedef enum { @@ -3866,9 +3860,9 @@ typedef enum LSM6DSR_Z_EQ_MIN_Z = 4, LSM6DSR_Z_EQ_Z = 5, } lsm6dsr_mag_z_axis_t; -int32_t lsm6dsr_mag_z_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_mag_z_orient_set(const stmdev_ctx_t *ctx, lsm6dsr_mag_z_axis_t val); -int32_t lsm6dsr_mag_z_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_mag_z_orient_get(const stmdev_ctx_t *ctx, lsm6dsr_mag_z_axis_t *val); typedef enum @@ -3880,9 +3874,9 @@ typedef enum LSM6DSR_Y_EQ_MIN_Z = 4, LSM6DSR_Y_EQ_Z = 5, } lsm6dsr_mag_y_axis_t; -int32_t lsm6dsr_mag_y_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_mag_y_orient_set(const stmdev_ctx_t *ctx, lsm6dsr_mag_y_axis_t val); -int32_t lsm6dsr_mag_y_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_mag_y_orient_get(const stmdev_ctx_t *ctx, lsm6dsr_mag_y_axis_t *val); typedef enum @@ -3894,29 +3888,29 @@ typedef enum LSM6DSR_X_EQ_MIN_Z = 4, LSM6DSR_X_EQ_Z = 5, } lsm6dsr_mag_x_axis_t; -int32_t lsm6dsr_mag_x_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_mag_x_orient_set(const stmdev_ctx_t *ctx, lsm6dsr_mag_x_axis_t val); -int32_t lsm6dsr_mag_x_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_mag_x_orient_get(const stmdev_ctx_t *ctx, lsm6dsr_mag_x_axis_t *val); -int32_t lsm6dsr_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { lsm6dsr_fsm_enable_a_t fsm_enable_a; lsm6dsr_fsm_enable_b_t fsm_enable_b; } lsm6dsr_emb_fsm_enable_t; -int32_t lsm6dsr_fsm_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fsm_enable_set(const stmdev_ctx_t *ctx, lsm6dsr_emb_fsm_enable_t *val); -int32_t lsm6dsr_fsm_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fsm_enable_get(const stmdev_ctx_t *ctx, lsm6dsr_emb_fsm_enable_t *val); -int32_t lsm6dsr_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsr_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsr_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsr_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum { @@ -3924,9 +3918,9 @@ typedef enum LSM6DSR_LC_CLEAR = 1, LSM6DSR_LC_CLEAR_DONE = 2, } lsm6dsr_fsm_lc_clr_t; -int32_t lsm6dsr_long_clr_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_long_clr_set(const stmdev_ctx_t *ctx, lsm6dsr_fsm_lc_clr_t val); -int32_t lsm6dsr_long_clr_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_long_clr_get(const stmdev_ctx_t *ctx, lsm6dsr_fsm_lc_clr_t *val); typedef struct @@ -3948,7 +3942,7 @@ typedef struct lsm6dsr_fsm_outs15_t fsm_outs15; lsm6dsr_fsm_outs16_t fsm_outs16; } lsm6dsr_fsm_out_t; -int32_t lsm6dsr_fsm_out_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dsr_fsm_out_t *val); typedef enum @@ -3958,27 +3952,27 @@ typedef enum LSM6DSR_ODR_FSM_52Hz = 2, LSM6DSR_ODR_FSM_104Hz = 3, } lsm6dsr_fsm_odr_t; -int32_t lsm6dsr_fsm_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fsm_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsr_fsm_odr_t val); -int32_t lsm6dsr_fsm_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fsm_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsr_fsm_odr_t *val); -int32_t lsm6dsr_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_long_cnt_int_value_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsr_long_cnt_int_value_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsr_fsm_number_of_programs_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsr_fsm_number_of_programs_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsr_fsm_start_address_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsr_fsm_start_address_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef struct @@ -4002,7 +3996,7 @@ typedef struct lsm6dsr_sensor_hub_17_t sh_byte_17; lsm6dsr_sensor_hub_18_t sh_byte_18; } lsm6dsr_emb_sh_read_t; -int32_t lsm6dsr_sh_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_read_data_raw_get(const stmdev_ctx_t *ctx, lsm6dsr_emb_sh_read_t *val); typedef enum @@ -4012,35 +4006,35 @@ typedef enum LSM6DSR_SLV_0_1_2 = 2, LSM6DSR_SLV_0_1_2_3 = 3, } lsm6dsr_aux_sens_on_t; -int32_t lsm6dsr_sh_slave_connected_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_slave_connected_set(const stmdev_ctx_t *ctx, lsm6dsr_aux_sens_on_t val); -int32_t lsm6dsr_sh_slave_connected_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_slave_connected_get(const stmdev_ctx_t *ctx, lsm6dsr_aux_sens_on_t *val); -int32_t lsm6dsr_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSR_EXT_PULL_UP = 0, LSM6DSR_INTERNAL_PULL_UP = 1, } lsm6dsr_shub_pu_en_t; -int32_t lsm6dsr_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_shub_pu_en_t val); -int32_t lsm6dsr_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_shub_pu_en_t *val); -int32_t lsm6dsr_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSR_EXT_ON_INT2_PIN = 1, LSM6DSR_XL_GY_DRDY = 0, } lsm6dsr_start_config_t; -int32_t lsm6dsr_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_syncro_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_start_config_t val); -int32_t lsm6dsr_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_syncro_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_start_config_t *val); typedef enum @@ -4048,13 +4042,13 @@ typedef enum LSM6DSR_EACH_SH_CYCLE = 0, LSM6DSR_ONLY_FIRST_CYCLE = 1, } lsm6dsr_write_once_t; -int32_t lsm6dsr_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_write_mode_set(const stmdev_ctx_t *ctx, lsm6dsr_write_once_t val); -int32_t lsm6dsr_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_write_mode_get(const stmdev_ctx_t *ctx, lsm6dsr_write_once_t *val); -int32_t lsm6dsr_sh_reset_set(stmdev_ctx_t *ctx); -int32_t lsm6dsr_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_sh_reset_set(const stmdev_ctx_t *ctx); +int32_t lsm6dsr_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -4063,9 +4057,9 @@ typedef enum LSM6DSR_SH_ODR_26Hz = 2, LSM6DSR_SH_ODR_13Hz = 3, } lsm6dsr_shub_odr_t; -int32_t lsm6dsr_sh_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsr_shub_odr_t val); -int32_t lsm6dsr_sh_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsr_shub_odr_t *val); typedef struct @@ -4074,7 +4068,7 @@ typedef struct uint8_t slv0_subadd; uint8_t slv0_data; } lsm6dsr_sh_cfg_write_t; -int32_t lsm6dsr_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_cfg_write(const stmdev_ctx_t *ctx, lsm6dsr_sh_cfg_write_t *val); typedef struct @@ -4083,16 +4077,16 @@ typedef struct uint8_t slv_subadd; uint8_t slv_len; } lsm6dsr_sh_cfg_read_t; -int32_t lsm6dsr_sh_slv0_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, lsm6dsr_sh_cfg_read_t *val); -int32_t lsm6dsr_sh_slv1_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, lsm6dsr_sh_cfg_read_t *val); -int32_t lsm6dsr_sh_slv2_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, lsm6dsr_sh_cfg_read_t *val); -int32_t lsm6dsr_sh_slv3_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, lsm6dsr_sh_cfg_read_t *val); -int32_t lsm6dsr_sh_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_sh_status_get(const stmdev_ctx_t *ctx, lsm6dsr_status_master_t *val); typedef enum @@ -4100,13 +4094,13 @@ typedef enum LSM6DSR_S4S_TPH_7bit = 0, LSM6DSR_S4S_TPH_15bit = 1, } lsm6dsr_s4s_tph_res_t; -int32_t lsm6dsr_s4s_tph_res_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_s4s_tph_res_set(const stmdev_ctx_t *ctx, lsm6dsr_s4s_tph_res_t val); -int32_t lsm6dsr_s4s_tph_res_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_s4s_tph_res_get(const stmdev_ctx_t *ctx, lsm6dsr_s4s_tph_res_t *val); -int32_t lsm6dsr_s4s_tph_val_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsr_s4s_tph_val_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsr_s4s_tph_val_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsr_s4s_tph_val_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum { @@ -4115,16 +4109,16 @@ typedef enum LSM6DSR_S4S_DT_RES_13 = 2, LSM6DSR_S4S_DT_RES_14 = 3, } lsm6dsr_s4s_res_ratio_t; -int32_t lsm6dsr_s4s_res_ratio_set(stmdev_ctx_t *ctx, +int32_t lsm6dsr_s4s_res_ratio_set(const stmdev_ctx_t *ctx, lsm6dsr_s4s_res_ratio_t val); -int32_t lsm6dsr_s4s_res_ratio_get(stmdev_ctx_t *ctx, +int32_t lsm6dsr_s4s_res_ratio_get(const stmdev_ctx_t *ctx, lsm6dsr_s4s_res_ratio_t *val); -int32_t lsm6dsr_s4s_command_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_s4s_command_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_s4s_command_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_s4s_command_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsr_s4s_dt_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsr_s4s_dt_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsr_s4s_dt_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsr_s4s_dt_get(const stmdev_ctx_t *ctx, uint8_t *val); /** *@} diff --git a/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.c b/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.c index d4357d65..5e94f7a3 100644 --- a/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.c +++ b/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm6dsrx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm6dsrx_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lsm6dsrx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm6dsrx_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm6dsrx_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -171,7 +181,7 @@ float_t lsm6dsrx_from_lsb_to_nsec(int32_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsrx_fs_xl_t val) { lsm6dsrx_ctrl1_xl_t ctrl1_xl; @@ -197,7 +207,7 @@ int32_t lsm6dsrx_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsrx_fs_xl_t *val) { lsm6dsrx_ctrl1_xl_t ctrl1_xl; @@ -239,7 +249,7 @@ int32_t lsm6dsrx_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsrx_odr_xl_t val) { lsm6dsrx_odr_xl_t odr_xl = val; @@ -496,7 +506,7 @@ int32_t lsm6dsrx_xl_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsrx_odr_xl_t *val) { lsm6dsrx_ctrl1_xl_t ctrl1_xl; @@ -570,7 +580,7 @@ int32_t lsm6dsrx_xl_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsrx_fs_g_t val) { lsm6dsrx_ctrl2_g_t ctrl2_g; @@ -595,7 +605,7 @@ int32_t lsm6dsrx_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsrx_fs_g_t *val) { lsm6dsrx_ctrl2_g_t ctrl2_g; @@ -645,7 +655,7 @@ int32_t lsm6dsrx_gy_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_gy_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsrx_odr_g_t val) { lsm6dsrx_odr_g_t odr_gy = val; @@ -901,7 +911,7 @@ int32_t lsm6dsrx_gy_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsrx_odr_g_t *val) { lsm6dsrx_ctrl2_g_t ctrl2_g; @@ -971,7 +981,7 @@ int32_t lsm6dsrx_gy_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -995,7 +1005,7 @@ int32_t lsm6dsrx_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_ctrl3_c_t ctrl3_c; @@ -1016,7 +1026,7 @@ int32_t lsm6dsrx_block_data_update_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_offset_weight_set(const stmdev_ctx_t *ctx, lsm6dsrx_usr_off_w_t val) { lsm6dsrx_ctrl6_c_t ctrl6_c; @@ -1042,7 +1052,7 @@ int32_t lsm6dsrx_xl_offset_weight_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_offset_weight_get(const stmdev_ctx_t *ctx, lsm6dsrx_usr_off_w_t *val) { lsm6dsrx_ctrl6_c_t ctrl6_c; @@ -1076,7 +1086,7 @@ int32_t lsm6dsrx_xl_offset_weight_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_power_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_xl_hm_mode_t val) { lsm6dsrx_ctrl6_c_t ctrl6_c; @@ -1101,7 +1111,7 @@ int32_t lsm6dsrx_xl_power_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_power_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_xl_hm_mode_t *val) { lsm6dsrx_ctrl6_c_t ctrl6_c; @@ -1135,7 +1145,7 @@ int32_t lsm6dsrx_xl_power_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_gy_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_gy_power_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_g_hm_mode_t val) { lsm6dsrx_ctrl7_g_t ctrl7_g; @@ -1160,7 +1170,7 @@ int32_t lsm6dsrx_gy_power_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_gy_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_gy_power_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_g_hm_mode_t *val) { lsm6dsrx_ctrl7_g_t ctrl7_g; @@ -1196,7 +1206,7 @@ int32_t lsm6dsrx_gy_power_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_all_sources_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_all_sources_get(const stmdev_ctx_t *ctx, lsm6dsrx_all_sources_t *val) { int32_t ret; @@ -1273,7 +1283,7 @@ int32_t lsm6dsrx_all_sources_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_status_reg_get(const stmdev_ctx_t *ctx, lsm6dsrx_status_reg_t *val) { int32_t ret; @@ -1291,7 +1301,7 @@ int32_t lsm6dsrx_status_reg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_status_reg_t status_reg; @@ -1312,7 +1322,7 @@ int32_t lsm6dsrx_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_status_reg_t status_reg; @@ -1333,7 +1343,7 @@ int32_t lsm6dsrx_gy_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_status_reg_t status_reg; @@ -1356,7 +1366,7 @@ int32_t lsm6dsrx_temp_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsrx_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1375,7 +1385,7 @@ int32_t lsm6dsrx_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsrx_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1394,7 +1404,7 @@ int32_t lsm6dsrx_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsrx_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1413,7 +1423,7 @@ int32_t lsm6dsrx_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsrx_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1432,7 +1442,7 @@ int32_t lsm6dsrx_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsrx_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1451,7 +1461,7 @@ int32_t lsm6dsrx_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsrx_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1468,7 +1478,7 @@ int32_t lsm6dsrx_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_ctrl7_g_t ctrl7_g; int32_t ret; @@ -1492,7 +1502,7 @@ int32_t lsm6dsrx_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_ctrl7_g_t ctrl7_g; int32_t ret; @@ -1523,7 +1533,7 @@ int32_t lsm6dsrx_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_timestamp_rst(stmdev_ctx_t *ctx) +int32_t lsm6dsrx_timestamp_rst(const stmdev_ctx_t *ctx) { uint8_t rst_val = 0xAA; return lsm6dsrx_write_reg(ctx, LSM6DSRX_TIMESTAMP2, &rst_val, 1); @@ -1537,7 +1547,7 @@ int32_t lsm6dsrx_timestamp_rst(stmdev_ctx_t *ctx) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_ctrl10_c_t ctrl10_c; int32_t ret; @@ -1562,7 +1572,7 @@ int32_t lsm6dsrx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_ctrl10_c_t ctrl10_c; int32_t ret; @@ -1583,7 +1593,7 @@ int32_t lsm6dsrx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t lsm6dsrx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; @@ -1617,7 +1627,7 @@ int32_t lsm6dsrx_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_rounding_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_rounding_t val) { lsm6dsrx_ctrl5_c_t ctrl5_c; @@ -1642,7 +1652,7 @@ int32_t lsm6dsrx_rounding_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_rounding_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_rounding_t *val) { lsm6dsrx_ctrl5_c_t ctrl5_c; @@ -1686,7 +1696,7 @@ int32_t lsm6dsrx_rounding_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsrx_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1707,7 +1717,7 @@ int32_t lsm6dsrx_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsrx_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1732,7 +1742,7 @@ int32_t lsm6dsrx_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsrx_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1756,7 +1766,7 @@ int32_t lsm6dsrx_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -1773,7 +1783,7 @@ int32_t lsm6dsrx_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsrx_number_of_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1802,7 +1812,7 @@ int32_t lsm6dsrx_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_steps_reset(stmdev_ctx_t *ctx) +int32_t lsm6dsrx_steps_reset(const stmdev_ctx_t *ctx) { lsm6dsrx_emb_func_src_t emb_func_src; int32_t ret; @@ -1852,7 +1862,7 @@ int32_t lsm6dsrx_steps_reset(stmdev_ctx_t *ctx) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_internal_freq_fine_t internal_freq_fine; int32_t ret; @@ -1880,7 +1890,7 @@ int32_t lsm6dsrx_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_internal_freq_fine_t internal_freq_fine; int32_t ret; @@ -1901,7 +1911,7 @@ int32_t lsm6dsrx_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_mem_bank_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dsrx_reg_access_t val) { lsm6dsrx_func_cfg_access_t func_cfg_access; @@ -1929,7 +1939,7 @@ int32_t lsm6dsrx_mem_bank_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_mem_bank_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dsrx_reg_access_t *val) { lsm6dsrx_func_cfg_access_t func_cfg_access; @@ -1969,7 +1979,7 @@ int32_t lsm6dsrx_mem_bank_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add, +int32_t lsm6dsrx_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t add, uint8_t *val) { lsm6dsrx_page_rw_t page_rw; @@ -2044,7 +2054,7 @@ int32_t lsm6dsrx_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add, +int32_t lsm6dsrx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t add, uint8_t *buf, uint8_t len) { lsm6dsrx_page_rw_t page_rw; @@ -2154,7 +2164,7 @@ int32_t lsm6dsrx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add, +int32_t lsm6dsrx_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, uint8_t *val) { lsm6dsrx_page_rw_t page_rw; @@ -2228,7 +2238,7 @@ int32_t lsm6dsrx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_dataready_pulsed_t val) { lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1; @@ -2256,7 +2266,7 @@ int32_t lsm6dsrx_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_dataready_pulsed_t *val) { lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1; @@ -2291,7 +2301,7 @@ int32_t lsm6dsrx_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsrx_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -2308,7 +2318,7 @@ int32_t lsm6dsrx_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2332,7 +2342,7 @@ int32_t lsm6dsrx_reset_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2352,7 +2362,7 @@ int32_t lsm6dsrx_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2377,7 +2387,7 @@ int32_t lsm6dsrx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2396,7 +2406,7 @@ int32_t lsm6dsrx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2420,7 +2430,7 @@ int32_t lsm6dsrx_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -2441,7 +2451,7 @@ int32_t lsm6dsrx_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dsrx_st_xl_t val) { lsm6dsrx_ctrl5_c_t ctrl5_c; @@ -2466,7 +2476,7 @@ int32_t lsm6dsrx_xl_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dsrx_st_xl_t *val) { lsm6dsrx_ctrl5_c_t ctrl5_c; @@ -2504,7 +2514,7 @@ int32_t lsm6dsrx_xl_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dsrx_st_g_t val) { lsm6dsrx_ctrl5_c_t ctrl5_c; @@ -2529,7 +2539,7 @@ int32_t lsm6dsrx_gy_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dsrx_st_g_t *val) { lsm6dsrx_ctrl5_c_t ctrl5_c; @@ -2580,7 +2590,7 @@ int32_t lsm6dsrx_gy_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_ctrl1_xl_t ctrl1_xl; int32_t ret; @@ -2605,7 +2615,7 @@ int32_t lsm6dsrx_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_ctrl1_xl_t ctrl1_xl; int32_t ret; @@ -2625,7 +2635,7 @@ int32_t lsm6dsrx_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_ctrl4_c_t ctrl4_c; int32_t ret; @@ -2650,7 +2660,7 @@ int32_t lsm6dsrx_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_ctrl4_c_t ctrl4_c; int32_t ret; @@ -2670,7 +2680,7 @@ int32_t lsm6dsrx_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_ctrl4_c_t ctrl4_c; @@ -2696,7 +2706,7 @@ int32_t lsm6dsrx_filter_settling_mask_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_ctrl4_c_t ctrl4_c; @@ -2716,7 +2726,7 @@ int32_t lsm6dsrx_filter_settling_mask_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsrx_ftype_t val) { lsm6dsrx_ctrl6_c_t ctrl6_c; @@ -2741,7 +2751,7 @@ int32_t lsm6dsrx_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsrx_ftype_t *val) { lsm6dsrx_ctrl6_c_t ctrl6_c; @@ -2799,7 +2809,7 @@ int32_t lsm6dsrx_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -2824,7 +2834,7 @@ int32_t lsm6dsrx_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -2844,7 +2854,7 @@ int32_t lsm6dsrx_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, lsm6dsrx_hp_slope_xl_en_t val) { lsm6dsrx_ctrl8_xl_t ctrl8_xl; @@ -2873,7 +2883,7 @@ int32_t lsm6dsrx_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, lsm6dsrx_hp_slope_xl_en_t *val) { lsm6dsrx_ctrl8_xl_t ctrl8_xl; @@ -2995,7 +3005,7 @@ int32_t lsm6dsrx_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -3022,7 +3032,7 @@ int32_t lsm6dsrx_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_ctrl8_xl_t ctrl8_xl; int32_t ret; @@ -3042,7 +3052,7 @@ int32_t lsm6dsrx_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dsrx_slope_fds_t val) { lsm6dsrx_tap_cfg0_t tap_cfg0; @@ -3069,7 +3079,7 @@ int32_t lsm6dsrx_xl_hp_path_internal_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dsrx_slope_fds_t *val) { lsm6dsrx_tap_cfg0_t tap_cfg0; @@ -3104,7 +3114,7 @@ int32_t lsm6dsrx_xl_hp_path_internal_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_gy_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dsrx_hpm_g_t val) { lsm6dsrx_ctrl7_g_t ctrl7_g; @@ -3131,7 +3141,7 @@ int32_t lsm6dsrx_gy_hp_path_internal_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_gy_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dsrx_hpm_g_t *val) { lsm6dsrx_ctrl7_g_t ctrl7_g; @@ -3191,7 +3201,7 @@ int32_t lsm6dsrx_gy_hp_path_internal_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_sdo_ocs_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_ois_pu_dis_t val) { lsm6dsrx_pin_ctrl_t pin_ctrl; @@ -3218,7 +3228,7 @@ int32_t lsm6dsrx_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_sdo_ocs_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_ois_pu_dis_t *val) { lsm6dsrx_pin_ctrl_t pin_ctrl; @@ -3252,7 +3262,7 @@ int32_t lsm6dsrx_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_pw_on_ctrl_set(const stmdev_ctx_t *ctx, lsm6dsrx_ois_on_t val) { lsm6dsrx_ctrl7_g_t ctrl7_g; @@ -3278,7 +3288,7 @@ int32_t lsm6dsrx_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_pw_on_ctrl_get(const stmdev_ctx_t *ctx, lsm6dsrx_ois_on_t *val) { lsm6dsrx_ctrl7_g_t ctrl7_g; @@ -3312,7 +3322,7 @@ int32_t lsm6dsrx_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_status_reg_get(const stmdev_ctx_t *ctx, lsm6dsrx_status_spiaux_t *val) { int32_t ret; @@ -3330,7 +3340,7 @@ int32_t lsm6dsrx_aux_status_reg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_status_spiaux_t status_spiaux; @@ -3351,7 +3361,7 @@ int32_t lsm6dsrx_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_status_spiaux_t status_spiaux; @@ -3372,7 +3382,7 @@ int32_t lsm6dsrx_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_status_spiaux_t status_spiaux; @@ -3394,7 +3404,7 @@ int32_t lsm6dsrx_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dsrx_st_xl_ois_t val) { lsm6dsrx_int_ois_t int_ois; @@ -3420,7 +3430,7 @@ int32_t lsm6dsrx_aux_xl_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dsrx_st_xl_ois_t *val) { lsm6dsrx_int_ois_t int_ois; @@ -3458,7 +3468,7 @@ int32_t lsm6dsrx_aux_xl_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dsrx_den_lh_ois_t val) { lsm6dsrx_int_ois_t int_ois; @@ -3483,7 +3493,7 @@ int32_t lsm6dsrx_aux_den_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dsrx_den_lh_ois_t *val) { lsm6dsrx_int_ois_t int_ois; @@ -3517,7 +3527,7 @@ int32_t lsm6dsrx_aux_den_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_den_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_lvl2_ois_t val) { lsm6dsrx_int_ois_t int_ois; @@ -3556,7 +3566,7 @@ int32_t lsm6dsrx_aux_den_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_den_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_lvl2_ois_t *val) { lsm6dsrx_int_ois_t int_ois; @@ -3602,7 +3612,7 @@ int32_t lsm6dsrx_aux_den_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_aux_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_int_ois_t int_ois; int32_t ret; @@ -3627,7 +3637,7 @@ int32_t lsm6dsrx_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_int_ois_t int_ois; int32_t ret; @@ -3651,7 +3661,7 @@ int32_t lsm6dsrx_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_ois_en_spi2_t val) { lsm6dsrx_ctrl1_ois_t ctrl1_ois; @@ -3685,7 +3695,7 @@ int32_t lsm6dsrx_aux_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_ois_en_spi2_t *val) { lsm6dsrx_ctrl1_ois_t ctrl1_ois; @@ -3724,7 +3734,7 @@ int32_t lsm6dsrx_aux_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsrx_fs_g_ois_t val) { lsm6dsrx_ctrl1_ois_t ctrl1_ois; @@ -3752,7 +3762,7 @@ int32_t lsm6dsrx_aux_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsrx_fs_g_ois_t *val) { lsm6dsrx_ctrl1_ois_t ctrl1_ois; @@ -3799,7 +3809,7 @@ int32_t lsm6dsrx_aux_gy_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_spi_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_sim_ois_t val) { lsm6dsrx_ctrl1_ois_t ctrl1_ois; @@ -3826,7 +3836,7 @@ int32_t lsm6dsrx_aux_spi_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_spi_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_sim_ois_t *val) { lsm6dsrx_ctrl1_ois_t ctrl1_ois; @@ -3861,7 +3871,7 @@ int32_t lsm6dsrx_aux_spi_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsrx_ftype_ois_t val) { lsm6dsrx_ctrl2_ois_t ctrl2_ois; @@ -3888,7 +3898,7 @@ int32_t lsm6dsrx_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsrx_ftype_ois_t *val) { lsm6dsrx_ctrl2_ois_t ctrl2_ois; @@ -3931,7 +3941,7 @@ int32_t lsm6dsrx_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_gy_hp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsrx_hpm_ois_t val) { lsm6dsrx_ctrl2_ois_t ctrl2_ois; @@ -3959,7 +3969,7 @@ int32_t lsm6dsrx_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_gy_hp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsrx_hpm_ois_t *val) { lsm6dsrx_ctrl2_ois_t ctrl2_ois; @@ -4008,7 +4018,7 @@ int32_t lsm6dsrx_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_gy_clamp_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_gy_clamp_set(const stmdev_ctx_t *ctx, lsm6dsrx_st_ois_clampdis_t val) { lsm6dsrx_ctrl3_ois_t ctrl3_ois; @@ -4037,7 +4047,7 @@ int32_t lsm6dsrx_aux_gy_clamp_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_gy_clamp_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_gy_clamp_get(const stmdev_ctx_t *ctx, lsm6dsrx_st_ois_clampdis_t *val) { lsm6dsrx_ctrl3_ois_t ctrl3_ois; @@ -4072,7 +4082,7 @@ int32_t lsm6dsrx_aux_gy_clamp_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dsrx_st_ois_t val) { lsm6dsrx_ctrl3_ois_t ctrl3_ois; @@ -4099,7 +4109,7 @@ int32_t lsm6dsrx_aux_gy_self_test_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dsrx_st_ois_t *val) { lsm6dsrx_ctrl3_ois_t ctrl3_ois; @@ -4138,7 +4148,7 @@ int32_t lsm6dsrx_aux_gy_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_xl_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_xl_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsrx_filter_xl_conf_ois_t val) { lsm6dsrx_ctrl3_ois_t ctrl3_ois; @@ -4165,7 +4175,7 @@ int32_t lsm6dsrx_aux_xl_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_xl_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_xl_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsrx_filter_xl_conf_ois_t *val) { lsm6dsrx_ctrl3_ois_t ctrl3_ois; @@ -4224,7 +4234,7 @@ int32_t lsm6dsrx_aux_xl_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsrx_fs_xl_ois_t val) { lsm6dsrx_ctrl3_ois_t ctrl3_ois; @@ -4251,7 +4261,7 @@ int32_t lsm6dsrx_aux_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_aux_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsrx_fs_xl_ois_t *val) { lsm6dsrx_ctrl3_ois_t ctrl3_ois; @@ -4307,7 +4317,7 @@ int32_t lsm6dsrx_aux_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_sdo_pu_en_t val) { lsm6dsrx_pin_ctrl_t pin_ctrl; @@ -4332,7 +4342,7 @@ int32_t lsm6dsrx_sdo_sa0_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_sdo_pu_en_t *val) { lsm6dsrx_pin_ctrl_t pin_ctrl; @@ -4366,7 +4376,7 @@ int32_t lsm6dsrx_sdo_sa0_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_int1_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_int1_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_pd_dis_int1_t val) { lsm6dsrx_i3c_bus_avb_t i3c_bus_avb; @@ -4393,7 +4403,7 @@ int32_t lsm6dsrx_int1_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_int1_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_int1_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_pd_dis_int1_t *val) { lsm6dsrx_i3c_bus_avb_t i3c_bus_avb; @@ -4428,7 +4438,7 @@ int32_t lsm6dsrx_int1_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsrx_sim_t val) +int32_t lsm6dsrx_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_sim_t val) { lsm6dsrx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -4452,7 +4462,7 @@ int32_t lsm6dsrx_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsrx_sim_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsrx_sim_t *val) +int32_t lsm6dsrx_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_sim_t *val) { lsm6dsrx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -4485,7 +4495,7 @@ int32_t lsm6dsrx_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsrx_sim_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_i2c_interface_set(const stmdev_ctx_t *ctx, lsm6dsrx_i2c_disable_t val) { lsm6dsrx_ctrl4_c_t ctrl4_c; @@ -4510,7 +4520,7 @@ int32_t lsm6dsrx_i2c_interface_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_i2c_interface_get(const stmdev_ctx_t *ctx, lsm6dsrx_i2c_disable_t *val) { lsm6dsrx_ctrl4_c_t ctrl4_c; @@ -4544,7 +4554,7 @@ int32_t lsm6dsrx_i2c_interface_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_i3c_disable_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_i3c_disable_set(const stmdev_ctx_t *ctx, lsm6dsrx_i3c_disable_t val) { lsm6dsrx_ctrl9_xl_t ctrl9_xl; @@ -4584,7 +4594,7 @@ int32_t lsm6dsrx_i3c_disable_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_i3c_disable_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_i3c_disable_get(const stmdev_ctx_t *ctx, lsm6dsrx_i3c_disable_t *val) { lsm6dsrx_ctrl9_xl_t ctrl9_xl; @@ -4651,7 +4661,7 @@ int32_t lsm6dsrx_i3c_disable_get(stmdev_ctx_t *ctx, * FSM_INT1_B * */ -int32_t lsm6dsrx_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm6dsrx_pin_int1_route_t *val) { lsm6dsrx_pin_int2_route_t pin_int2_route; @@ -4802,7 +4812,7 @@ int32_t lsm6dsrx_pin_int1_route_set(stmdev_ctx_t *ctx, * EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B * */ -int32_t lsm6dsrx_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm6dsrx_pin_int1_route_t *val) { int32_t ret; @@ -4861,7 +4871,7 @@ int32_t lsm6dsrx_pin_int1_route_get(stmdev_ctx_t *ctx, * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B * */ -int32_t lsm6dsrx_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm6dsrx_pin_int2_route_t *val) { lsm6dsrx_pin_int1_route_t pin_int1_route; @@ -5011,7 +5021,7 @@ int32_t lsm6dsrx_pin_int2_route_set(stmdev_ctx_t *ctx, * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B * */ -int32_t lsm6dsrx_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pin_int2_route_get(const stmdev_ctx_t *ctx, lsm6dsrx_pin_int2_route_t *val) { int32_t ret; @@ -5070,7 +5080,7 @@ int32_t lsm6dsrx_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsrx_pp_od_t val) +int32_t lsm6dsrx_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_pp_od_t val) { lsm6dsrx_ctrl3_c_t ctrl3_c; int32_t ret; @@ -5094,7 +5104,7 @@ int32_t lsm6dsrx_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsrx_pp_od_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_pp_od_t *val) { lsm6dsrx_ctrl3_c_t ctrl3_c; @@ -5128,7 +5138,7 @@ int32_t lsm6dsrx_pin_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pin_polarity_set(const stmdev_ctx_t *ctx, lsm6dsrx_h_lactive_t val) { lsm6dsrx_ctrl3_c_t ctrl3_c; @@ -5153,7 +5163,7 @@ int32_t lsm6dsrx_pin_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pin_polarity_get(const stmdev_ctx_t *ctx, lsm6dsrx_h_lactive_t *val) { lsm6dsrx_ctrl3_c_t ctrl3_c; @@ -5187,7 +5197,7 @@ int32_t lsm6dsrx_pin_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_ctrl4_c_t ctrl4_c; int32_t ret; @@ -5211,7 +5221,7 @@ int32_t lsm6dsrx_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_ctrl4_c_t ctrl4_c; int32_t ret; @@ -5230,7 +5240,7 @@ int32_t lsm6dsrx_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_int_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_int_notification_set(const stmdev_ctx_t *ctx, lsm6dsrx_lir_t val) { lsm6dsrx_tap_cfg0_t tap_cfg0; @@ -5279,7 +5289,7 @@ int32_t lsm6dsrx_int_notification_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_int_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_int_notification_get(const stmdev_ctx_t *ctx, lsm6dsrx_lir_t *val) { lsm6dsrx_tap_cfg0_t tap_cfg0; @@ -5353,7 +5363,7 @@ int32_t lsm6dsrx_int_notification_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_wkup_ths_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_wkup_ths_weight_set(const stmdev_ctx_t *ctx, lsm6dsrx_wake_ths_w_t val) { lsm6dsrx_wake_up_dur_t wake_up_dur; @@ -5382,7 +5392,7 @@ int32_t lsm6dsrx_wkup_ths_weight_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_wkup_ths_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_wkup_ths_weight_get(const stmdev_ctx_t *ctx, lsm6dsrx_wake_ths_w_t *val) { lsm6dsrx_wake_up_dur_t wake_up_dur; @@ -5418,7 +5428,7 @@ int32_t lsm6dsrx_wkup_ths_weight_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_wake_up_ths_t wake_up_ths; int32_t ret; @@ -5445,7 +5455,7 @@ int32_t lsm6dsrx_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_wake_up_ths_t wake_up_ths; int32_t ret; @@ -5465,7 +5475,7 @@ int32_t lsm6dsrx_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_wake_up_ths_t wake_up_ths; @@ -5492,7 +5502,7 @@ int32_t lsm6dsrx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_wake_up_ths_t wake_up_ths; @@ -5513,7 +5523,7 @@ int32_t lsm6dsrx_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_wake_up_dur_t wake_up_dur; int32_t ret; @@ -5539,7 +5549,7 @@ int32_t lsm6dsrx_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_wake_up_dur_t wake_up_dur; int32_t ret; @@ -5572,7 +5582,7 @@ int32_t lsm6dsrx_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_ctrl4_c_t ctrl4_c; int32_t ret; @@ -5596,7 +5606,7 @@ int32_t lsm6dsrx_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_ctrl4_c_t ctrl4_c; int32_t ret; @@ -5617,7 +5627,7 @@ int32_t lsm6dsrx_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_act_pin_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_act_pin_notification_set(const stmdev_ctx_t *ctx, lsm6dsrx_sleep_status_on_int_t val) { lsm6dsrx_tap_cfg0_t tap_cfg0; @@ -5645,7 +5655,7 @@ int32_t lsm6dsrx_act_pin_notification_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_act_pin_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_act_pin_notification_get(const stmdev_ctx_t *ctx, lsm6dsrx_sleep_status_on_int_t *val) { lsm6dsrx_tap_cfg0_t tap_cfg0; @@ -5679,7 +5689,7 @@ int32_t lsm6dsrx_act_pin_notification_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_act_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_act_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_inact_en_t val) { lsm6dsrx_tap_cfg2_t tap_cfg2; @@ -5704,7 +5714,7 @@ int32_t lsm6dsrx_act_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_act_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_act_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_inact_en_t *val) { lsm6dsrx_tap_cfg2_t tap_cfg2; @@ -5746,7 +5756,7 @@ int32_t lsm6dsrx_act_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_wake_up_dur_t wake_up_dur; int32_t ret; @@ -5772,7 +5782,7 @@ int32_t lsm6dsrx_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_wake_up_dur_t wake_up_dur; int32_t ret; @@ -5805,7 +5815,7 @@ int32_t lsm6dsrx_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_tap_cfg0_t tap_cfg0; @@ -5831,7 +5841,7 @@ int32_t lsm6dsrx_tap_detection_on_z_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_tap_cfg0_t tap_cfg0; @@ -5851,7 +5861,7 @@ int32_t lsm6dsrx_tap_detection_on_z_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_tap_cfg0_t tap_cfg0; @@ -5877,7 +5887,7 @@ int32_t lsm6dsrx_tap_detection_on_y_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_tap_cfg0_t tap_cfg0; @@ -5897,7 +5907,7 @@ int32_t lsm6dsrx_tap_detection_on_y_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_tap_cfg0_t tap_cfg0; @@ -5923,7 +5933,7 @@ int32_t lsm6dsrx_tap_detection_on_x_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_tap_cfg0_t tap_cfg0; @@ -5943,7 +5953,7 @@ int32_t lsm6dsrx_tap_detection_on_x_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_tap_cfg1_t tap_cfg1; int32_t ret; @@ -5968,7 +5978,7 @@ int32_t lsm6dsrx_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_tap_cfg1_t tap_cfg1; int32_t ret; @@ -5987,7 +5997,7 @@ int32_t lsm6dsrx_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_tap_axis_priority_set(const stmdev_ctx_t *ctx, lsm6dsrx_tap_priority_t val) { lsm6dsrx_tap_cfg1_t tap_cfg1; @@ -6012,7 +6022,7 @@ int32_t lsm6dsrx_tap_axis_priority_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_tap_axis_priority_get(const stmdev_ctx_t *ctx, lsm6dsrx_tap_priority_t *val) { lsm6dsrx_tap_cfg1_t tap_cfg1; @@ -6062,7 +6072,7 @@ int32_t lsm6dsrx_tap_axis_priority_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_tap_cfg2_t tap_cfg2; int32_t ret; @@ -6087,7 +6097,7 @@ int32_t lsm6dsrx_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_tap_cfg2_t tap_cfg2; int32_t ret; @@ -6106,7 +6116,7 @@ int32_t lsm6dsrx_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -6132,7 +6142,7 @@ int32_t lsm6dsrx_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -6156,7 +6166,7 @@ int32_t lsm6dsrx_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_int_dur2_t int_dur2; int32_t ret; @@ -6185,7 +6195,7 @@ int32_t lsm6dsrx_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_int_dur2_t int_dur2; int32_t ret; @@ -6208,7 +6218,7 @@ int32_t lsm6dsrx_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_int_dur2_t int_dur2; int32_t ret; @@ -6237,7 +6247,7 @@ int32_t lsm6dsrx_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_int_dur2_t int_dur2; int32_t ret; @@ -6262,7 +6272,7 @@ int32_t lsm6dsrx_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_int_dur2_t int_dur2; int32_t ret; @@ -6291,7 +6301,7 @@ int32_t lsm6dsrx_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_int_dur2_t int_dur2; int32_t ret; @@ -6310,7 +6320,7 @@ int32_t lsm6dsrx_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_tap_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_single_double_tap_t val) { lsm6dsrx_wake_up_ths_t wake_up_ths; @@ -6337,7 +6347,7 @@ int32_t lsm6dsrx_tap_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_tap_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_single_double_tap_t *val) { lsm6dsrx_wake_up_ths_t wake_up_ths; @@ -6385,7 +6395,7 @@ int32_t lsm6dsrx_tap_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_6d_threshold_set(const stmdev_ctx_t *ctx, lsm6dsrx_sixd_ths_t val) { lsm6dsrx_tap_ths_6d_t tap_ths_6d; @@ -6412,7 +6422,7 @@ int32_t lsm6dsrx_6d_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_6d_threshold_get(const stmdev_ctx_t *ctx, lsm6dsrx_sixd_ths_t *val) { lsm6dsrx_tap_ths_6d_t tap_ths_6d; @@ -6455,7 +6465,7 @@ int32_t lsm6dsrx_6d_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -6481,7 +6491,7 @@ int32_t lsm6dsrx_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -6514,7 +6524,7 @@ int32_t lsm6dsrx_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_ff_threshold_set(const stmdev_ctx_t *ctx, lsm6dsrx_ff_ths_t val) { lsm6dsrx_free_fall_t free_fall; @@ -6541,7 +6551,7 @@ int32_t lsm6dsrx_ff_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_ff_threshold_get(const stmdev_ctx_t *ctx, lsm6dsrx_ff_ths_t *val) { lsm6dsrx_free_fall_t free_fall; @@ -6600,7 +6610,7 @@ int32_t lsm6dsrx_ff_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_wake_up_dur_t wake_up_dur; lsm6dsrx_free_fall_t free_fall; @@ -6640,7 +6650,7 @@ int32_t lsm6dsrx_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_wake_up_dur_t wake_up_dur; lsm6dsrx_free_fall_t free_fall; @@ -6681,7 +6691,7 @@ int32_t lsm6dsrx_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsrx_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val) { lsm6dsrx_fifo_ctrl1_t fifo_ctrl1; lsm6dsrx_fifo_ctrl2_t fifo_ctrl2; @@ -6715,7 +6725,7 @@ int32_t lsm6dsrx_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsrx_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dsrx_fifo_ctrl1_t fifo_ctrl1; lsm6dsrx_fifo_ctrl2_t fifo_ctrl2; @@ -6744,7 +6754,7 @@ int32_t lsm6dsrx_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_compression_algo_init_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_compression_algo_init_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_emb_func_init_b_t emb_func_init_b; @@ -6782,7 +6792,7 @@ int32_t lsm6dsrx_compression_algo_init_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_compression_algo_init_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_compression_algo_init_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_emb_func_init_b_t emb_func_init_b; @@ -6813,7 +6823,7 @@ int32_t lsm6dsrx_compression_algo_init_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_compression_algo_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_compression_algo_set(const stmdev_ctx_t *ctx, lsm6dsrx_uncoptr_rate_t val) { lsm6dsrx_fifo_ctrl2_t fifo_ctrl2; @@ -6869,7 +6879,7 @@ int32_t lsm6dsrx_compression_algo_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_compression_algo_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_compression_algo_get(const stmdev_ctx_t *ctx, lsm6dsrx_uncoptr_rate_t *val) { lsm6dsrx_fifo_ctrl2_t fifo_ctrl2; @@ -6917,7 +6927,7 @@ int32_t lsm6dsrx_compression_algo_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_fifo_ctrl2_t fifo_ctrl2; @@ -6944,7 +6954,7 @@ int32_t lsm6dsrx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_fifo_ctrl2_t fifo_ctrl2; @@ -6965,7 +6975,7 @@ int32_t lsm6dsrx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_compression_algo_real_time_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_compression_algo_real_time_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_fifo_ctrl2_t fifo_ctrl2; @@ -6992,7 +7002,7 @@ int32_t lsm6dsrx_compression_algo_real_time_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_compression_algo_real_time_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_compression_algo_real_time_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_fifo_ctrl2_t fifo_ctrl2; @@ -7014,7 +7024,7 @@ int32_t lsm6dsrx_compression_algo_real_time_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -7041,7 +7051,7 @@ int32_t lsm6dsrx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -7062,7 +7072,7 @@ int32_t lsm6dsrx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_xl_batch_set(const stmdev_ctx_t *ctx, lsm6dsrx_bdr_xl_t val) { lsm6dsrx_fifo_ctrl3_t fifo_ctrl3; @@ -7090,7 +7100,7 @@ int32_t lsm6dsrx_fifo_xl_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_xl_batch_get(const stmdev_ctx_t *ctx, lsm6dsrx_bdr_xl_t *val) { lsm6dsrx_fifo_ctrl3_t fifo_ctrl3; @@ -7166,7 +7176,7 @@ int32_t lsm6dsrx_fifo_xl_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_gy_batch_set(const stmdev_ctx_t *ctx, lsm6dsrx_bdr_gy_t val) { lsm6dsrx_fifo_ctrl3_t fifo_ctrl3; @@ -7194,7 +7204,7 @@ int32_t lsm6dsrx_fifo_gy_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_gy_batch_get(const stmdev_ctx_t *ctx, lsm6dsrx_bdr_gy_t *val) { lsm6dsrx_fifo_ctrl3_t fifo_ctrl3; @@ -7269,7 +7279,7 @@ int32_t lsm6dsrx_fifo_gy_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_fifo_mode_t val) { lsm6dsrx_fifo_ctrl4_t fifo_ctrl4; @@ -7296,7 +7306,7 @@ int32_t lsm6dsrx_fifo_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_fifo_mode_t *val) { lsm6dsrx_fifo_ctrl4_t fifo_ctrl4; @@ -7348,7 +7358,7 @@ int32_t lsm6dsrx_fifo_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_temp_batch_set(const stmdev_ctx_t *ctx, lsm6dsrx_odr_t_batch_t val) { lsm6dsrx_fifo_ctrl4_t fifo_ctrl4; @@ -7376,7 +7386,7 @@ int32_t lsm6dsrx_fifo_temp_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_temp_batch_get(const stmdev_ctx_t *ctx, lsm6dsrx_odr_t_batch_t *val) { lsm6dsrx_fifo_ctrl4_t fifo_ctrl4; @@ -7421,7 +7431,7 @@ int32_t lsm6dsrx_fifo_temp_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, lsm6dsrx_odr_ts_batch_t val) { lsm6dsrx_fifo_ctrl4_t fifo_ctrl4; @@ -7451,7 +7461,7 @@ int32_t lsm6dsrx_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, lsm6dsrx_odr_ts_batch_t *val) { lsm6dsrx_fifo_ctrl4_t fifo_ctrl4; @@ -7496,7 +7506,7 @@ int32_t lsm6dsrx_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, lsm6dsrx_trig_counter_bdr_t val) { lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1; @@ -7525,7 +7535,7 @@ int32_t lsm6dsrx_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, lsm6dsrx_trig_counter_bdr_t *val) { lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1; @@ -7561,7 +7571,7 @@ int32_t lsm6dsrx_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1; int32_t ret; @@ -7588,7 +7598,7 @@ int32_t lsm6dsrx_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_rst_batch_counter_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1; @@ -7610,7 +7620,7 @@ int32_t lsm6dsrx_rst_batch_counter_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_batch_counter_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { lsm6dsrx_counter_bdr_reg2_t counter_bdr_reg1; @@ -7647,7 +7657,7 @@ int32_t lsm6dsrx_batch_counter_threshold_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1; @@ -7677,7 +7687,7 @@ int32_t lsm6dsrx_batch_counter_threshold_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsrx_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dsrx_fifo_status1_t fifo_status1; lsm6dsrx_fifo_status2_t fifo_status2; @@ -7705,7 +7715,7 @@ int32_t lsm6dsrx_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_status_get(const stmdev_ctx_t *ctx, lsm6dsrx_fifo_status2_t *val) { int32_t ret; @@ -7723,7 +7733,7 @@ int32_t lsm6dsrx_fifo_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_fifo_status2_t fifo_status2; int32_t ret; @@ -7744,7 +7754,7 @@ int32_t lsm6dsrx_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_fifo_status2_t fifo_status2; int32_t ret; @@ -7764,7 +7774,7 @@ int32_t lsm6dsrx_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_fifo_status2_t fifo_status2; int32_t ret; @@ -7784,7 +7794,7 @@ int32_t lsm6dsrx_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fifo_sensor_tag_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, lsm6dsrx_fifo_tag_t *val) { lsm6dsrx_fifo_data_out_tag_t fifo_data_out_tag; @@ -7900,7 +7910,7 @@ int32_t lsm6dsrx_fifo_sensor_tag_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_emb_func_fifo_cfg_t emb_func_fifo_cfg; int32_t ret; @@ -7937,7 +7947,7 @@ int32_t lsm6dsrx_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_emb_func_fifo_cfg_t emb_func_fifo_cfg; int32_t ret; @@ -7967,7 +7977,7 @@ int32_t lsm6dsrx_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_slv0_config_t slv0_config; int32_t ret; @@ -8004,7 +8014,7 @@ int32_t lsm6dsrx_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_slv0_config_t slv0_config; int32_t ret; @@ -8035,7 +8045,7 @@ int32_t lsm6dsrx_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_slv1_config_t slv1_config; int32_t ret; @@ -8072,7 +8082,7 @@ int32_t lsm6dsrx_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_slv1_config_t slv1_config; int32_t ret; @@ -8103,7 +8113,7 @@ int32_t lsm6dsrx_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_slv2_config_t slv2_config; int32_t ret; @@ -8140,7 +8150,7 @@ int32_t lsm6dsrx_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_slv2_config_t slv2_config; int32_t ret; @@ -8171,7 +8181,7 @@ int32_t lsm6dsrx_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_slv3_config_t slv3_config; int32_t ret; @@ -8208,7 +8218,7 @@ int32_t lsm6dsrx_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_slv3_config_t slv3_config; int32_t ret; @@ -8251,7 +8261,7 @@ int32_t lsm6dsrx_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_den_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_den_mode_t val) { lsm6dsrx_ctrl6_c_t ctrl6_c; @@ -8276,7 +8286,7 @@ int32_t lsm6dsrx_den_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_den_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_den_mode_t *val) { lsm6dsrx_ctrl6_c_t ctrl6_c; @@ -8322,7 +8332,7 @@ int32_t lsm6dsrx_den_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dsrx_den_lh_t val) { lsm6dsrx_ctrl9_xl_t ctrl9_xl; @@ -8348,7 +8358,7 @@ int32_t lsm6dsrx_den_polarity_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dsrx_den_lh_t *val) { lsm6dsrx_ctrl9_xl_t ctrl9_xl; @@ -8382,7 +8392,7 @@ int32_t lsm6dsrx_den_polarity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_den_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_den_enable_set(const stmdev_ctx_t *ctx, lsm6dsrx_den_xl_g_t val) { lsm6dsrx_ctrl9_xl_t ctrl9_xl; @@ -8408,7 +8418,7 @@ int32_t lsm6dsrx_den_enable_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_den_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_den_enable_get(const stmdev_ctx_t *ctx, lsm6dsrx_den_xl_g_t *val) { lsm6dsrx_ctrl9_xl_t ctrl9_xl; @@ -8446,7 +8456,7 @@ int32_t lsm6dsrx_den_enable_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -8471,7 +8481,7 @@ int32_t lsm6dsrx_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -8490,7 +8500,7 @@ int32_t lsm6dsrx_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -8515,7 +8525,7 @@ int32_t lsm6dsrx_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -8534,7 +8544,7 @@ int32_t lsm6dsrx_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -8558,7 +8568,7 @@ int32_t lsm6dsrx_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_ctrl9_xl_t ctrl9_xl; int32_t ret; @@ -8589,7 +8599,7 @@ int32_t lsm6dsrx_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -8625,7 +8635,7 @@ int32_t lsm6dsrx_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -8655,7 +8665,7 @@ int32_t lsm6dsrx_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_pedo_step_detect_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_emb_func_status_t emb_func_status; int32_t ret; @@ -8685,7 +8695,7 @@ int32_t lsm6dsrx_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_pedo_debounce_steps_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -8704,7 +8714,7 @@ int32_t lsm6dsrx_pedo_debounce_steps_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_pedo_debounce_steps_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -8723,7 +8733,7 @@ int32_t lsm6dsrx_pedo_debounce_steps_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_pedo_steps_period_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pedo_steps_period_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; @@ -8751,7 +8761,7 @@ int32_t lsm6dsrx_pedo_steps_period_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_pedo_steps_period_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pedo_steps_period_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -8780,7 +8790,7 @@ int32_t lsm6dsrx_pedo_steps_period_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_pedo_int_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pedo_int_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_carry_count_en_t val) { lsm6dsrx_pedo_cmd_reg_t pedo_cmd_reg; @@ -8808,7 +8818,7 @@ int32_t lsm6dsrx_pedo_int_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_pedo_int_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pedo_int_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_carry_count_en_t *val) { lsm6dsrx_pedo_cmd_reg_t pedo_cmd_reg; @@ -8856,7 +8866,7 @@ int32_t lsm6dsrx_pedo_int_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -8892,7 +8902,7 @@ int32_t lsm6dsrx_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -8922,7 +8932,7 @@ int32_t lsm6dsrx_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_motion_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_motion_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_emb_func_status_t emb_func_status; @@ -8966,7 +8976,7 @@ int32_t lsm6dsrx_motion_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -9002,7 +9012,7 @@ int32_t lsm6dsrx_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -9032,7 +9042,7 @@ int32_t lsm6dsrx_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_emb_func_status_t emb_func_status; @@ -9076,7 +9086,7 @@ int32_t lsm6dsrx_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsrx_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -9103,7 +9113,7 @@ int32_t lsm6dsrx_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsrx_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -9130,7 +9140,7 @@ int32_t lsm6dsrx_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsrx_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -9186,7 +9196,7 @@ int32_t lsm6dsrx_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsrx_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -9248,7 +9258,7 @@ int32_t lsm6dsrx_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_mag_soft_iron_set(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsrx_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[12]; int32_t ret; @@ -9351,7 +9361,7 @@ int32_t lsm6dsrx_mag_soft_iron_set(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsrx_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[12]; int32_t ret; @@ -9451,7 +9461,7 @@ int32_t lsm6dsrx_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_mag_z_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_mag_z_orient_set(const stmdev_ctx_t *ctx, lsm6dsrx_mag_z_axis_t val) { lsm6dsrx_mag_cfg_a_t mag_cfg_a; @@ -9479,7 +9489,7 @@ int32_t lsm6dsrx_mag_z_orient_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_mag_z_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_mag_z_orient_get(const stmdev_ctx_t *ctx, lsm6dsrx_mag_z_axis_t *val) { lsm6dsrx_mag_cfg_a_t mag_cfg_a; @@ -9532,7 +9542,7 @@ int32_t lsm6dsrx_mag_z_orient_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_mag_y_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_mag_y_orient_set(const stmdev_ctx_t *ctx, lsm6dsrx_mag_y_axis_t val) { lsm6dsrx_mag_cfg_a_t mag_cfg_a; @@ -9560,7 +9570,7 @@ int32_t lsm6dsrx_mag_y_orient_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_mag_y_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_mag_y_orient_get(const stmdev_ctx_t *ctx, lsm6dsrx_mag_y_axis_t *val) { lsm6dsrx_mag_cfg_a_t mag_cfg_a; @@ -9612,7 +9622,7 @@ int32_t lsm6dsrx_mag_y_orient_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_mag_x_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_mag_x_orient_set(const stmdev_ctx_t *ctx, lsm6dsrx_mag_x_axis_t val) { lsm6dsrx_mag_cfg_b_t mag_cfg_b; @@ -9640,7 +9650,7 @@ int32_t lsm6dsrx_mag_x_orient_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_mag_x_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_mag_x_orient_get(const stmdev_ctx_t *ctx, lsm6dsrx_mag_x_axis_t *val) { lsm6dsrx_mag_cfg_b_t mag_cfg_b; @@ -9705,7 +9715,7 @@ int32_t lsm6dsrx_mag_x_orient_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_emb_func_status_t emb_func_status; @@ -9736,7 +9746,7 @@ int32_t lsm6dsrx_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; @@ -9772,7 +9782,7 @@ int32_t lsm6dsrx_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -9808,7 +9818,7 @@ int32_t lsm6dsrx_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fsm_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fsm_enable_set(const stmdev_ctx_t *ctx, lsm6dsrx_emb_fsm_enable_t *val) { lsm6dsrx_emb_func_en_b_t emb_func_en_b; @@ -9884,7 +9894,7 @@ int32_t lsm6dsrx_fsm_enable_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fsm_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fsm_enable_get(const stmdev_ctx_t *ctx, lsm6dsrx_emb_fsm_enable_t *val) { int32_t ret; @@ -9920,7 +9930,7 @@ int32_t lsm6dsrx_fsm_enable_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsrx_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -9951,7 +9961,7 @@ int32_t lsm6dsrx_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsrx_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -9982,7 +9992,7 @@ int32_t lsm6dsrx_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_long_clr_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_long_clr_set(const stmdev_ctx_t *ctx, lsm6dsrx_fsm_lc_clr_t val) { lsm6dsrx_fsm_long_counter_clear_t fsm_long_counter_clear; @@ -10019,7 +10029,7 @@ int32_t lsm6dsrx_long_clr_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_long_clr_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_long_clr_get(const stmdev_ctx_t *ctx, lsm6dsrx_fsm_lc_clr_t *val) { lsm6dsrx_fsm_long_counter_clear_t fsm_long_counter_clear; @@ -10068,7 +10078,7 @@ int32_t lsm6dsrx_long_clr_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fsm_out_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dsrx_fsm_out_t *val) { int32_t ret; @@ -10097,7 +10107,7 @@ int32_t lsm6dsrx_fsm_out_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fsm_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fsm_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsrx_fsm_odr_t val) { lsm6dsrx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; @@ -10136,7 +10146,7 @@ int32_t lsm6dsrx_fsm_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fsm_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fsm_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsrx_fsm_odr_t *val) { lsm6dsrx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; @@ -10189,7 +10199,7 @@ int32_t lsm6dsrx_fsm_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_emb_func_init_b_t emb_func_init_b; int32_t ret; @@ -10225,7 +10235,7 @@ int32_t lsm6dsrx_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_emb_func_init_b_t emb_func_init_b; int32_t ret; @@ -10258,7 +10268,7 @@ int32_t lsm6dsrx_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_long_cnt_int_value_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; @@ -10289,7 +10299,7 @@ int32_t lsm6dsrx_long_cnt_int_value_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_long_cnt_int_value_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -10317,7 +10327,7 @@ int32_t lsm6dsrx_long_cnt_int_value_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fsm_number_of_programs_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -10341,7 +10351,7 @@ int32_t lsm6dsrx_fsm_number_of_programs_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fsm_number_of_programs_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -10360,7 +10370,7 @@ int32_t lsm6dsrx_fsm_number_of_programs_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fsm_start_address_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; @@ -10389,7 +10399,7 @@ int32_t lsm6dsrx_fsm_start_address_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_fsm_start_address_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -10431,7 +10441,7 @@ int32_t lsm6dsrx_fsm_start_address_get(stmdev_ctx_t *ctx, * in EMB_FUNC_INIT_B * */ -int32_t lsm6dsrx_mlc_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_mlc_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_emb_func_en_b_t reg; int32_t ret; @@ -10478,7 +10488,7 @@ int32_t lsm6dsrx_mlc_set(stmdev_ctx_t *ctx, uint8_t val) * reg EMB_FUNC_EN_B * */ -int32_t lsm6dsrx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_emb_func_en_b_t reg; int32_t ret; @@ -10506,7 +10516,7 @@ int32_t lsm6dsrx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val) * @param val register MLC_STATUS_MAINPAGE * */ -int32_t lsm6dsrx_mlc_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_mlc_status_get(const stmdev_ctx_t *ctx, lsm6dsrx_mlc_status_mainpage_t *val) { return lsm6dsrx_read_reg(ctx, LSM6DSRX_MLC_STATUS_MAINPAGE, @@ -10521,7 +10531,7 @@ int32_t lsm6dsrx_mlc_status_get(stmdev_ctx_t *ctx, * reg EMB_FUNC_ODR_CFG_C * */ -int32_t lsm6dsrx_mlc_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_mlc_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsrx_mlc_odr_t val) { lsm6dsrx_emb_func_odr_cfg_c_t reg; @@ -10558,7 +10568,7 @@ int32_t lsm6dsrx_mlc_data_rate_set(stmdev_ctx_t *ctx, * reg EMB_FUNC_ODR_CFG_C * */ -int32_t lsm6dsrx_mlc_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_mlc_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsrx_mlc_odr_t *val) { lsm6dsrx_emb_func_odr_cfg_c_t reg; @@ -10610,7 +10620,7 @@ int32_t lsm6dsrx_mlc_data_rate_get(stmdev_ctx_t *ctx, * @param uint8_t * : buffer that stores data read * */ -int32_t lsm6dsrx_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm6dsrx_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -10637,7 +10647,7 @@ int32_t lsm6dsrx_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff) * @param buff buffer that contains data to write * */ -int32_t lsm6dsrx_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_mlc_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; @@ -10665,7 +10675,7 @@ int32_t lsm6dsrx_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx, * @param buff buffer that stores data read * */ -int32_t lsm6dsrx_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; @@ -10706,7 +10716,7 @@ int32_t lsm6dsrx_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_read_data_raw_get(const stmdev_ctx_t *ctx, lsm6dsrx_emb_sh_read_t *val) { int32_t ret; @@ -10735,7 +10745,7 @@ int32_t lsm6dsrx_sh_read_data_raw_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_slave_connected_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_slave_connected_set(const stmdev_ctx_t *ctx, lsm6dsrx_aux_sens_on_t val) { lsm6dsrx_master_config_t master_config; @@ -10772,7 +10782,7 @@ int32_t lsm6dsrx_sh_slave_connected_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_slave_connected_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_slave_connected_get(const stmdev_ctx_t *ctx, lsm6dsrx_aux_sens_on_t *val) { lsm6dsrx_master_config_t master_config; @@ -10825,7 +10835,7 @@ int32_t lsm6dsrx_sh_slave_connected_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_master_config_t master_config; int32_t ret; @@ -10861,7 +10871,7 @@ int32_t lsm6dsrx_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_master_config_t master_config; int32_t ret; @@ -10891,7 +10901,7 @@ int32_t lsm6dsrx_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_shub_pu_en_t val) { lsm6dsrx_master_config_t master_config; @@ -10928,7 +10938,7 @@ int32_t lsm6dsrx_sh_pin_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_shub_pu_en_t *val) { lsm6dsrx_master_config_t master_config; @@ -10973,7 +10983,7 @@ int32_t lsm6dsrx_sh_pin_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_master_config_t master_config; int32_t ret; @@ -11009,7 +11019,7 @@ int32_t lsm6dsrx_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_master_config_t master_config; int32_t ret; @@ -11039,7 +11049,7 @@ int32_t lsm6dsrx_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_syncro_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_start_config_t val) { lsm6dsrx_master_config_t master_config; @@ -11076,7 +11086,7 @@ int32_t lsm6dsrx_sh_syncro_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_syncro_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_start_config_t *val) { lsm6dsrx_master_config_t master_config; @@ -11122,7 +11132,7 @@ int32_t lsm6dsrx_sh_syncro_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_write_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_write_once_t val) { lsm6dsrx_master_config_t master_config; @@ -11160,7 +11170,7 @@ int32_t lsm6dsrx_sh_write_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_write_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_write_once_t *val) { lsm6dsrx_master_config_t master_config; @@ -11204,7 +11214,7 @@ int32_t lsm6dsrx_sh_write_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_reset_set(stmdev_ctx_t *ctx) +int32_t lsm6dsrx_sh_reset_set(const stmdev_ctx_t *ctx) { lsm6dsrx_master_config_t master_config; int32_t ret; @@ -11247,7 +11257,7 @@ int32_t lsm6dsrx_sh_reset_set(stmdev_ctx_t *ctx) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_master_config_t master_config; int32_t ret; @@ -11277,7 +11287,7 @@ int32_t lsm6dsrx_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsrx_shub_odr_t val) { lsm6dsrx_slv0_config_t slv0_config; @@ -11314,7 +11324,7 @@ int32_t lsm6dsrx_sh_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsrx_shub_odr_t *val) { lsm6dsrx_slv0_config_t slv0_config; @@ -11370,7 +11380,7 @@ int32_t lsm6dsrx_sh_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_cfg_write(const stmdev_ctx_t *ctx, lsm6dsrx_sh_cfg_write_t *val) { lsm6dsrx_slv0_add_t slv0_add; @@ -11417,7 +11427,7 @@ int32_t lsm6dsrx_sh_cfg_write(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_slv0_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, lsm6dsrx_sh_cfg_read_t *val) { lsm6dsrx_slv0_config_t slv0_config; @@ -11472,7 +11482,7 @@ int32_t lsm6dsrx_sh_slv0_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_slv1_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, lsm6dsrx_sh_cfg_read_t *val) { lsm6dsrx_slv1_config_t slv1_config; @@ -11526,7 +11536,7 @@ int32_t lsm6dsrx_sh_slv1_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_slv2_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, lsm6dsrx_sh_cfg_read_t *val) { lsm6dsrx_slv2_config_t slv2_config; @@ -11581,7 +11591,7 @@ int32_t lsm6dsrx_sh_slv2_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_slv3_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, lsm6dsrx_sh_cfg_read_t *val) { lsm6dsrx_slv3_config_t slv3_config; @@ -11633,7 +11643,7 @@ int32_t lsm6dsrx_sh_slv3_cfg_read(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_sh_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_status_get(const stmdev_ctx_t *ctx, lsm6dsrx_status_master_t *val) { int32_t ret; @@ -11674,7 +11684,7 @@ int32_t lsm6dsrx_sh_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_s4s_tph_res_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_s4s_tph_res_set(const stmdev_ctx_t *ctx, lsm6dsrx_s4s_tph_res_t val) { lsm6dsrx_s4s_tph_l_t s4s_tph_l; @@ -11701,7 +11711,7 @@ int32_t lsm6dsrx_s4s_tph_res_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_s4s_tph_res_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_s4s_tph_res_get(const stmdev_ctx_t *ctx, lsm6dsrx_s4s_tph_res_t *val) { lsm6dsrx_s4s_tph_l_t s4s_tph_l; @@ -11737,7 +11747,7 @@ int32_t lsm6dsrx_s4s_tph_res_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_s4s_tph_val_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsrx_s4s_tph_val_set(const stmdev_ctx_t *ctx, uint16_t val) { lsm6dsrx_s4s_tph_l_t s4s_tph_l; lsm6dsrx_s4s_tph_h_t s4s_tph_h; @@ -11777,7 +11787,7 @@ int32_t lsm6dsrx_s4s_tph_val_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_s4s_tph_val_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsrx_s4s_tph_val_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dsrx_s4s_tph_l_t s4s_tph_l; lsm6dsrx_s4s_tph_h_t s4s_tph_h; @@ -11807,7 +11817,7 @@ int32_t lsm6dsrx_s4s_tph_val_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_s4s_res_ratio_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_s4s_res_ratio_set(const stmdev_ctx_t *ctx, lsm6dsrx_s4s_res_ratio_t val) { lsm6dsrx_s4s_rr_t s4s_rr; @@ -11832,7 +11842,7 @@ int32_t lsm6dsrx_s4s_res_ratio_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_s4s_res_ratio_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_s4s_res_ratio_get(const stmdev_ctx_t *ctx, lsm6dsrx_s4s_res_ratio_t *val) { lsm6dsrx_s4s_rr_t s4s_rr; @@ -11874,7 +11884,7 @@ int32_t lsm6dsrx_s4s_res_ratio_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_s4s_command_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_s4s_command_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_s4s_st_cmd_code_t s4s_st_cmd_code; int32_t ret; @@ -11900,7 +11910,7 @@ int32_t lsm6dsrx_s4s_command_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_s4s_command_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_s4s_command_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_s4s_st_cmd_code_t s4s_st_cmd_code; int32_t ret; @@ -11920,7 +11930,7 @@ int32_t lsm6dsrx_s4s_command_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_s4s_dt_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsrx_s4s_dt_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsrx_s4s_dt_reg_t s4s_dt_reg; int32_t ret; @@ -11946,7 +11956,7 @@ int32_t lsm6dsrx_s4s_dt_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsrx_s4s_dt_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsrx_s4s_dt_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsrx_s4s_dt_reg_t s4s_dt_reg; int32_t ret; diff --git a/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.h b/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.h index 1a734795..eea85f2e 100644 --- a/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.h +++ b/sensor/stmemsc/lsm6dsrx_STdC/driver/lsm6dsrx_reg.h @@ -185,11 +185,9 @@ typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN uint8_t not_used_01 : 6; -uint8_t reg_access : - 2; /* shub_reg_access + func_cfg_access */ + uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */ #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN -uint8_t reg_access : - 2; /* shub_reg_access + func_cfg_access */ + uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */ uint8_t not_used_01 : 6; #endif /* DRV_BYTE_ORDER */ } lsm6dsrx_func_cfg_access_t; @@ -468,11 +466,9 @@ typedef struct uint8_t ftype : 3; uint8_t usr_off_w : 1; uint8_t xl_hm_mode : 1; -uint8_t den_mode : - 3; /* trig_en + lvl1_en + lvl2_en */ + uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN -uint8_t den_mode : - 3; /* trig_en + lvl1_en + lvl2_en */ + uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ uint8_t xl_hm_mode : 1; uint8_t usr_off_w : 1; uint8_t ftype : 3; @@ -1562,13 +1558,11 @@ typedef struct typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN -uint8_t fsm_lc_clr : - 2; /* fsm_lc_cleared + fsm_lc_clear */ + uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ uint8_t not_used_01 : 6; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN uint8_t not_used_01 : 6; -uint8_t fsm_lc_clr : - 2; /* fsm_lc_cleared + fsm_lc_clear */ + uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ #endif /* DRV_BYTE_ORDER */ } lsm6dsrx_fsm_long_counter_clear_t; @@ -2901,10 +2895,10 @@ typedef union * them with a custom implementation. */ -int32_t lsm6dsrx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm6dsrx_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lsm6dsrx_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm6dsrx_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -2931,9 +2925,9 @@ typedef enum LSM6DSRX_4g = 2, LSM6DSRX_8g = 3, } lsm6dsrx_fs_xl_t; -int32_t lsm6dsrx_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsrx_fs_xl_t val); -int32_t lsm6dsrx_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsrx_fs_xl_t *val); typedef enum @@ -2951,9 +2945,9 @@ typedef enum LSM6DSRX_XL_ODR_6667Hz = 10, LSM6DSRX_XL_ODR_1Hz6 = 11, /* (low power only) */ } lsm6dsrx_odr_xl_t; -int32_t lsm6dsrx_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsrx_odr_xl_t val); -int32_t lsm6dsrx_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsrx_odr_xl_t *val); typedef enum @@ -2965,9 +2959,9 @@ typedef enum LSM6DSRX_2000dps = 12, LSM6DSRX_4000dps = 1, } lsm6dsrx_fs_g_t; -int32_t lsm6dsrx_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsrx_fs_g_t val); -int32_t lsm6dsrx_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsrx_fs_g_t *val); typedef enum @@ -2984,14 +2978,14 @@ typedef enum LSM6DSRX_GY_ODR_3332Hz = 9, LSM6DSRX_GY_ODR_6667Hz = 10, } lsm6dsrx_odr_g_t; -int32_t lsm6dsrx_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_gy_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsrx_odr_g_t val); -int32_t lsm6dsrx_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsrx_odr_g_t *val); -int32_t lsm6dsrx_block_data_update_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_block_data_update_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -2999,9 +2993,9 @@ typedef enum LSM6DSRX_LSb_1mg = 0, LSM6DSRX_LSb_16mg = 1, } lsm6dsrx_usr_off_w_t; -int32_t lsm6dsrx_xl_offset_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_offset_weight_set(const stmdev_ctx_t *ctx, lsm6dsrx_usr_off_w_t val); -int32_t lsm6dsrx_xl_offset_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_offset_weight_get(const stmdev_ctx_t *ctx, lsm6dsrx_usr_off_w_t *val); typedef enum @@ -3009,9 +3003,9 @@ typedef enum LSM6DSRX_HIGH_PERFORMANCE_MD = 0, LSM6DSRX_LOW_NORMAL_POWER_MD = 1, } lsm6dsrx_xl_hm_mode_t; -int32_t lsm6dsrx_xl_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_power_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_xl_hm_mode_t val); -int32_t lsm6dsrx_xl_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_power_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_xl_hm_mode_t *val); typedef enum @@ -3019,9 +3013,9 @@ typedef enum LSM6DSRX_GY_HIGH_PERFORMANCE = 0, LSM6DSRX_GY_NORMAL = 1, } lsm6dsrx_g_hm_mode_t; -int32_t lsm6dsrx_gy_power_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_gy_power_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_g_hm_mode_t val); -int32_t lsm6dsrx_gy_power_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_gy_power_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_g_hm_mode_t *val); typedef struct @@ -3036,45 +3030,45 @@ typedef struct lsm6dsrx_fsm_status_b_t fsm_status_b; lsm6dsrx_mlc_status_mainpage_t mlc_status; } lsm6dsrx_all_sources_t; -int32_t lsm6dsrx_all_sources_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_all_sources_get(const stmdev_ctx_t *ctx, lsm6dsrx_all_sources_t *val); -int32_t lsm6dsrx_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_status_reg_get(const stmdev_ctx_t *ctx, lsm6dsrx_status_reg_t *val); -int32_t lsm6dsrx_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_xl_usr_offset_x_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsrx_xl_usr_offset_x_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsrx_xl_usr_offset_y_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsrx_xl_usr_offset_y_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsrx_xl_usr_offset_z_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsrx_xl_usr_offset_z_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsrx_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_timestamp_rst(stmdev_ctx_t *ctx); +int32_t lsm6dsrx_timestamp_rst(const stmdev_ctx_t *ctx); -int32_t lsm6dsrx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); +int32_t lsm6dsrx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); typedef enum { @@ -3083,28 +3077,28 @@ typedef enum LSM6DSRX_ROUND_GY = 2, LSM6DSRX_ROUND_GY_XL = 3, } lsm6dsrx_rounding_t; -int32_t lsm6dsrx_rounding_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_rounding_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_rounding_t val); -int32_t lsm6dsrx_rounding_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_rounding_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_rounding_t *val); -int32_t lsm6dsrx_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsrx_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsrx_angular_rate_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsrx_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsrx_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_number_of_steps_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_number_of_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsrx_steps_reset(stmdev_ctx_t *ctx); +int32_t lsm6dsrx_steps_reset(const stmdev_ctx_t *ctx); typedef enum { @@ -3112,18 +3106,18 @@ typedef enum LSM6DSRX_SENSOR_HUB_BANK = 1, LSM6DSRX_EMBEDDED_FUNC_BANK = 2, } lsm6dsrx_reg_access_t; -int32_t lsm6dsrx_mem_bank_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dsrx_reg_access_t val); -int32_t lsm6dsrx_mem_bank_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dsrx_reg_access_t *val); -int32_t lsm6dsrx_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dsrx_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val); -int32_t lsm6dsrx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dsrx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); -int32_t lsm6dsrx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add, +int32_t lsm6dsrx_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, uint8_t *val); -int32_t lsm6dsrx_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dsrx_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val); typedef enum @@ -3131,21 +3125,21 @@ typedef enum LSM6DSRX_DRDY_LATCHED = 0, LSM6DSRX_DRDY_PULSED = 1, } lsm6dsrx_dataready_pulsed_t; -int32_t lsm6dsrx_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_dataready_pulsed_t val); -int32_t lsm6dsrx_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_dataready_pulsed_t *val); -int32_t lsm6dsrx_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsrx_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsrx_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3153,9 +3147,9 @@ typedef enum LSM6DSRX_XL_ST_POSITIVE = 1, LSM6DSRX_XL_ST_NEGATIVE = 2, } lsm6dsrx_st_xl_t; -int32_t lsm6dsrx_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dsrx_st_xl_t val); -int32_t lsm6dsrx_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dsrx_st_xl_t *val); typedef enum @@ -3164,20 +3158,20 @@ typedef enum LSM6DSRX_GY_ST_POSITIVE = 1, LSM6DSRX_GY_ST_NEGATIVE = 3, } lsm6dsrx_st_g_t; -int32_t lsm6dsrx_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dsrx_st_g_t val); -int32_t lsm6dsrx_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dsrx_st_g_t *val); -int32_t lsm6dsrx_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3191,13 +3185,13 @@ typedef enum LSM6DSRX_AGGRESSIVE = 6, LSM6DSRX_XTREME = 7, } lsm6dsrx_ftype_t; -int32_t lsm6dsrx_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsrx_ftype_t val); -int32_t lsm6dsrx_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsrx_ftype_t *val); -int32_t lsm6dsrx_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3225,13 +3219,13 @@ typedef enum LSM6DSRX_LP_ODR_DIV_400 = 0x06, LSM6DSRX_LP_ODR_DIV_800 = 0x07, } lsm6dsrx_hp_slope_xl_en_t; -int32_t lsm6dsrx_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, lsm6dsrx_hp_slope_xl_en_t val); -int32_t lsm6dsrx_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, lsm6dsrx_hp_slope_xl_en_t *val); -int32_t lsm6dsrx_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_xl_fast_settling_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3239,9 +3233,9 @@ typedef enum LSM6DSRX_USE_SLOPE = 0, LSM6DSRX_USE_HPF = 1, } lsm6dsrx_slope_fds_t; -int32_t lsm6dsrx_xl_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dsrx_slope_fds_t val); -int32_t lsm6dsrx_xl_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dsrx_slope_fds_t *val); typedef enum @@ -3252,9 +3246,9 @@ typedef enum LSM6DSRX_HP_FILTER_260mHz = 0x82, LSM6DSRX_HP_FILTER_1Hz04 = 0x83, } lsm6dsrx_hpm_g_t; -int32_t lsm6dsrx_gy_hp_path_internal_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, lsm6dsrx_hpm_g_t val); -int32_t lsm6dsrx_gy_hp_path_internal_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, lsm6dsrx_hpm_g_t *val); typedef enum @@ -3262,9 +3256,9 @@ typedef enum LSM6DSRX_AUX_PULL_UP_DISC = 0, LSM6DSRX_AUX_PULL_UP_CONNECT = 1, } lsm6dsrx_ois_pu_dis_t; -int32_t lsm6dsrx_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_sdo_ocs_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_ois_pu_dis_t val); -int32_t lsm6dsrx_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_sdo_ocs_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_ois_pu_dis_t *val); typedef enum @@ -3272,21 +3266,21 @@ typedef enum LSM6DSRX_AUX_ON = 1, LSM6DSRX_AUX_ON_BY_AUX_INTERFACE = 0, } lsm6dsrx_ois_on_t; -int32_t lsm6dsrx_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_pw_on_ctrl_set(const stmdev_ctx_t *ctx, lsm6dsrx_ois_on_t val); -int32_t lsm6dsrx_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_pw_on_ctrl_get(const stmdev_ctx_t *ctx, lsm6dsrx_ois_on_t *val); -int32_t lsm6dsrx_aux_status_reg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_status_reg_get(const stmdev_ctx_t *ctx, lsm6dsrx_status_spiaux_t *val); -int32_t lsm6dsrx_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3295,9 +3289,9 @@ typedef enum LSM6DSRX_AUX_XL_POS = 1, LSM6DSRX_AUX_XL_NEG = 2, } lsm6dsrx_st_xl_ois_t; -int32_t lsm6dsrx_aux_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dsrx_st_xl_ois_t val); -int32_t lsm6dsrx_aux_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dsrx_st_xl_ois_t *val); typedef enum @@ -3305,9 +3299,9 @@ typedef enum LSM6DSRX_AUX_DEN_ACTIVE_LOW = 0, LSM6DSRX_AUX_DEN_ACTIVE_HIGH = 1, } lsm6dsrx_den_lh_ois_t; -int32_t lsm6dsrx_aux_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dsrx_den_lh_ois_t val); -int32_t lsm6dsrx_aux_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dsrx_den_lh_ois_t *val); typedef enum @@ -3316,13 +3310,13 @@ typedef enum LSM6DSRX_AUX_DEN_LEVEL_LATCH = 3, LSM6DSRX_AUX_DEN_LEVEL_TRIG = 2, } lsm6dsrx_lvl2_ois_t; -int32_t lsm6dsrx_aux_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_den_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_lvl2_ois_t val); -int32_t lsm6dsrx_aux_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_den_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_lvl2_ois_t *val); -int32_t lsm6dsrx_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3331,9 +3325,9 @@ typedef enum LSM6DSRX_MODE_3_GY = 1, LSM6DSRX_MODE_4_GY_XL = 3, } lsm6dsrx_ois_en_spi2_t; -int32_t lsm6dsrx_aux_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_ois_en_spi2_t val); -int32_t lsm6dsrx_aux_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_ois_en_spi2_t *val); typedef enum @@ -3344,9 +3338,9 @@ typedef enum LSM6DSRX_1000dps_AUX = 0x02, LSM6DSRX_2000dps_AUX = 0x03, } lsm6dsrx_fs_g_ois_t; -int32_t lsm6dsrx_aux_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsrx_fs_g_ois_t val); -int32_t lsm6dsrx_aux_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsrx_fs_g_ois_t *val); typedef enum @@ -3354,9 +3348,9 @@ typedef enum LSM6DSRX_AUX_SPI_4_WIRE = 0, LSM6DSRX_AUX_SPI_3_WIRE = 1, } lsm6dsrx_sim_ois_t; -int32_t lsm6dsrx_aux_spi_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_sim_ois_t val); -int32_t lsm6dsrx_aux_spi_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_sim_ois_t *val); typedef enum @@ -3366,9 +3360,9 @@ typedef enum LSM6DSRX_172Hz70 = 2, LSM6DSRX_937Hz91 = 3, } lsm6dsrx_ftype_ois_t; -int32_t lsm6dsrx_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsrx_ftype_ois_t val); -int32_t lsm6dsrx_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsrx_ftype_ois_t *val); typedef enum @@ -3379,9 +3373,9 @@ typedef enum LSM6DSRX_AUX_HP_Hz260 = 0x12, LSM6DSRX_AUX_HP_1Hz040 = 0x13, } lsm6dsrx_hpm_ois_t; -int32_t lsm6dsrx_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_gy_hp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsrx_hpm_ois_t val); -int32_t lsm6dsrx_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_gy_hp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsrx_hpm_ois_t *val); typedef enum @@ -3389,9 +3383,9 @@ typedef enum LSM6DSRX_ENABLE_CLAMP = 0, LSM6DSRX_DISABLE_CLAMP = 1, } lsm6dsrx_st_ois_clampdis_t; -int32_t lsm6dsrx_aux_gy_clamp_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_gy_clamp_set(const stmdev_ctx_t *ctx, lsm6dsrx_st_ois_clampdis_t val); -int32_t lsm6dsrx_aux_gy_clamp_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_gy_clamp_get(const stmdev_ctx_t *ctx, lsm6dsrx_st_ois_clampdis_t *val); typedef enum @@ -3400,9 +3394,9 @@ typedef enum LSM6DSRX_AUX_GY_POS = 1, LSM6DSRX_AUX_GY_NEG = 3, } lsm6dsrx_st_ois_t; -int32_t lsm6dsrx_aux_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dsrx_st_ois_t val); -int32_t lsm6dsrx_aux_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dsrx_st_ois_t *val); typedef enum @@ -3416,9 +3410,9 @@ typedef enum LSM6DSRX_8Hz3 = 6, LSM6DSRX_4Hz11 = 7, } lsm6dsrx_filter_xl_conf_ois_t; -int32_t lsm6dsrx_aux_xl_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_xl_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsrx_filter_xl_conf_ois_t val); -int32_t lsm6dsrx_aux_xl_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_xl_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsrx_filter_xl_conf_ois_t *val); typedef enum @@ -3428,9 +3422,9 @@ typedef enum LSM6DSRX_AUX_4g = 2, LSM6DSRX_AUX_8g = 3, } lsm6dsrx_fs_xl_ois_t; -int32_t lsm6dsrx_aux_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsrx_fs_xl_ois_t val); -int32_t lsm6dsrx_aux_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_aux_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsrx_fs_xl_ois_t *val); typedef enum @@ -3438,9 +3432,9 @@ typedef enum LSM6DSRX_PULL_UP_DISC = 0, LSM6DSRX_PULL_UP_CONNECT = 1, } lsm6dsrx_sdo_pu_en_t; -int32_t lsm6dsrx_sdo_sa0_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_sdo_pu_en_t val); -int32_t lsm6dsrx_sdo_sa0_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_sdo_pu_en_t *val); typedef enum @@ -3448,9 +3442,9 @@ typedef enum LSM6DSRX_PULL_DOWN_CONNECT = 0, LSM6DSRX_PULL_DOWN_DISC = 1, } lsm6dsrx_pd_dis_int1_t; -int32_t lsm6dsrx_int1_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_int1_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_pd_dis_int1_t val); -int32_t lsm6dsrx_int1_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_int1_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_pd_dis_int1_t *val); typedef enum @@ -3458,17 +3452,17 @@ typedef enum LSM6DSRX_SPI_4_WIRE = 0, LSM6DSRX_SPI_3_WIRE = 1, } lsm6dsrx_sim_t; -int32_t lsm6dsrx_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsrx_sim_t val); -int32_t lsm6dsrx_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsrx_sim_t *val); +int32_t lsm6dsrx_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_sim_t val); +int32_t lsm6dsrx_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_sim_t *val); typedef enum { LSM6DSRX_I2C_ENABLE = 0, LSM6DSRX_I2C_DISABLE = 1, } lsm6dsrx_i2c_disable_t; -int32_t lsm6dsrx_i2c_interface_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_i2c_interface_set(const stmdev_ctx_t *ctx, lsm6dsrx_i2c_disable_t val); -int32_t lsm6dsrx_i2c_interface_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_i2c_interface_get(const stmdev_ctx_t *ctx, lsm6dsrx_i2c_disable_t *val); typedef enum @@ -3479,9 +3473,9 @@ typedef enum LSM6DSRX_I3C_ENABLE_T_1ms = 0x02, LSM6DSRX_I3C_ENABLE_T_25ms = 0x03, } lsm6dsrx_i3c_disable_t; -int32_t lsm6dsrx_i3c_disable_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_i3c_disable_set(const stmdev_ctx_t *ctx, lsm6dsrx_i3c_disable_t val); -int32_t lsm6dsrx_i3c_disable_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_i3c_disable_get(const stmdev_ctx_t *ctx, lsm6dsrx_i3c_disable_t *val); typedef struct @@ -3493,9 +3487,9 @@ typedef struct lsm6dsrx_fsm_int1_b_t fsm_int1_b; lsm6dsrx_mlc_int1_t mlc_int1; } lsm6dsrx_pin_int1_route_t; -int32_t lsm6dsrx_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm6dsrx_pin_int1_route_t *val); -int32_t lsm6dsrx_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm6dsrx_pin_int1_route_t *val); typedef struct @@ -3507,9 +3501,9 @@ typedef struct lsm6dsrx_fsm_int2_b_t fsm_int2_b; lsm6dsrx_mlc_int2_t mlc_int2; } lsm6dsrx_pin_int2_route_t; -int32_t lsm6dsrx_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm6dsrx_pin_int2_route_t *val); -int32_t lsm6dsrx_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pin_int2_route_get(const stmdev_ctx_t *ctx, lsm6dsrx_pin_int2_route_t *val); typedef enum @@ -3517,9 +3511,9 @@ typedef enum LSM6DSRX_PUSH_PULL = 0, LSM6DSRX_OPEN_DRAIN = 1, } lsm6dsrx_pp_od_t; -int32_t lsm6dsrx_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_pp_od_t val); -int32_t lsm6dsrx_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_pp_od_t *val); typedef enum @@ -3527,13 +3521,13 @@ typedef enum LSM6DSRX_ACTIVE_HIGH = 0, LSM6DSRX_ACTIVE_LOW = 1, } lsm6dsrx_h_lactive_t; -int32_t lsm6dsrx_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pin_polarity_set(const stmdev_ctx_t *ctx, lsm6dsrx_h_lactive_t val); -int32_t lsm6dsrx_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pin_polarity_get(const stmdev_ctx_t *ctx, lsm6dsrx_h_lactive_t *val); -int32_t lsm6dsrx_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3542,9 +3536,9 @@ typedef enum LSM6DSRX_BASE_PULSED_EMB_LATCHED = 2, LSM6DSRX_ALL_INT_LATCHED = 3, } lsm6dsrx_lir_t; -int32_t lsm6dsrx_int_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_int_notification_set(const stmdev_ctx_t *ctx, lsm6dsrx_lir_t val); -int32_t lsm6dsrx_int_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_int_notification_get(const stmdev_ctx_t *ctx, lsm6dsrx_lir_t *val); typedef enum @@ -3552,33 +3546,33 @@ typedef enum LSM6DSRX_LSb_FS_DIV_64 = 0, LSM6DSRX_LSb_FS_DIV_256 = 1, } lsm6dsrx_wake_ths_w_t; -int32_t lsm6dsrx_wkup_ths_weight_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_wkup_ths_weight_set(const stmdev_ctx_t *ctx, lsm6dsrx_wake_ths_w_t val); -int32_t lsm6dsrx_wkup_ths_weight_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_wkup_ths_weight_get(const stmdev_ctx_t *ctx, lsm6dsrx_wake_ths_w_t *val); -int32_t lsm6dsrx_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSRX_DRIVE_SLEEP_CHG_EVENT = 0, LSM6DSRX_DRIVE_SLEEP_STATUS = 1, } lsm6dsrx_sleep_status_on_int_t; -int32_t lsm6dsrx_act_pin_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_act_pin_notification_set(const stmdev_ctx_t *ctx, lsm6dsrx_sleep_status_on_int_t val); -int32_t lsm6dsrx_act_pin_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_act_pin_notification_get(const stmdev_ctx_t *ctx, lsm6dsrx_sleep_status_on_int_t *val); typedef enum @@ -3588,31 +3582,31 @@ typedef enum LSM6DSRX_XL_12Hz5_GY_SLEEP = 2, LSM6DSRX_XL_12Hz5_GY_PD = 3, } lsm6dsrx_inact_en_t; -int32_t lsm6dsrx_act_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_act_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_inact_en_t val); -int32_t lsm6dsrx_act_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_act_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_inact_en_t *val); -int32_t lsm6dsrx_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_tap_detection_on_z_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_tap_detection_on_z_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_tap_detection_on_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_tap_detection_on_y_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_tap_detection_on_y_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_tap_detection_on_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_tap_detection_on_x_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_tap_detection_on_x_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_tap_detection_on_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3623,34 +3617,34 @@ typedef enum LSM6DSRX_YZX = 5, LSM6DSRX_ZXY = 6, } lsm6dsrx_tap_priority_t; -int32_t lsm6dsrx_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_tap_axis_priority_set(const stmdev_ctx_t *ctx, lsm6dsrx_tap_priority_t val); -int32_t lsm6dsrx_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_tap_axis_priority_get(const stmdev_ctx_t *ctx, lsm6dsrx_tap_priority_t *val); -int32_t lsm6dsrx_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSRX_ONLY_SINGLE = 0, LSM6DSRX_BOTH_SINGLE_DOUBLE = 1, } lsm6dsrx_single_double_tap_t; -int32_t lsm6dsrx_tap_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_single_double_tap_t val); -int32_t lsm6dsrx_tap_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_single_double_tap_t *val); typedef enum @@ -3660,13 +3654,13 @@ typedef enum LSM6DSRX_DEG_60 = 2, LSM6DSRX_DEG_50 = 3, } lsm6dsrx_sixd_ths_t; -int32_t lsm6dsrx_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_6d_threshold_set(const stmdev_ctx_t *ctx, lsm6dsrx_sixd_ths_t val); -int32_t lsm6dsrx_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_6d_threshold_get(const stmdev_ctx_t *ctx, lsm6dsrx_sixd_ths_t *val); -int32_t lsm6dsrx_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3679,20 +3673,20 @@ typedef enum LSM6DSRX_FF_TSH_469mg = 6, LSM6DSRX_FF_TSH_500mg = 7, } lsm6dsrx_ff_ths_t; -int32_t lsm6dsrx_ff_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_ff_threshold_set(const stmdev_ctx_t *ctx, lsm6dsrx_ff_ths_t val); -int32_t lsm6dsrx_ff_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_ff_threshold_get(const stmdev_ctx_t *ctx, lsm6dsrx_ff_ths_t *val); -int32_t lsm6dsrx_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsrx_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsrx_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsrx_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsrx_compression_algo_init_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_compression_algo_init_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_compression_algo_init_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_compression_algo_init_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3703,23 +3697,23 @@ typedef enum LSM6DSRX_CMP_16_TO_1 = 0x06, LSM6DSRX_CMP_32_TO_1 = 0x07, } lsm6dsrx_uncoptr_rate_t; -int32_t lsm6dsrx_compression_algo_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_compression_algo_set(const stmdev_ctx_t *ctx, lsm6dsrx_uncoptr_rate_t val); -int32_t lsm6dsrx_compression_algo_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_compression_algo_get(const stmdev_ctx_t *ctx, lsm6dsrx_uncoptr_rate_t *val); -int32_t lsm6dsrx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_compression_algo_real_time_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_compression_algo_real_time_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_compression_algo_real_time_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_compression_algo_real_time_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3737,9 +3731,9 @@ typedef enum LSM6DSRX_XL_BATCHED_AT_6667Hz = 10, LSM6DSRX_XL_BATCHED_AT_6Hz5 = 11, } lsm6dsrx_bdr_xl_t; -int32_t lsm6dsrx_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_xl_batch_set(const stmdev_ctx_t *ctx, lsm6dsrx_bdr_xl_t val); -int32_t lsm6dsrx_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_xl_batch_get(const stmdev_ctx_t *ctx, lsm6dsrx_bdr_xl_t *val); typedef enum @@ -3757,9 +3751,9 @@ typedef enum LSM6DSRX_GY_BATCHED_AT_6667Hz = 10, LSM6DSRX_GY_BATCHED_6Hz5 = 11, } lsm6dsrx_bdr_gy_t; -int32_t lsm6dsrx_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_gy_batch_set(const stmdev_ctx_t *ctx, lsm6dsrx_bdr_gy_t val); -int32_t lsm6dsrx_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_gy_batch_get(const stmdev_ctx_t *ctx, lsm6dsrx_bdr_gy_t *val); typedef enum @@ -3771,9 +3765,9 @@ typedef enum LSM6DSRX_STREAM_MODE = 6, LSM6DSRX_BYPASS_TO_FIFO_MODE = 7, } lsm6dsrx_fifo_mode_t; -int32_t lsm6dsrx_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_fifo_mode_t val); -int32_t lsm6dsrx_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_fifo_mode_t *val); typedef enum @@ -3783,9 +3777,9 @@ typedef enum LSM6DSRX_TEMP_BATCHED_AT_12Hz5 = 2, LSM6DSRX_TEMP_BATCHED_AT_1Hz6 = 3, } lsm6dsrx_odr_t_batch_t; -int32_t lsm6dsrx_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_temp_batch_set(const stmdev_ctx_t *ctx, lsm6dsrx_odr_t_batch_t val); -int32_t lsm6dsrx_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_temp_batch_get(const stmdev_ctx_t *ctx, lsm6dsrx_odr_t_batch_t *val); typedef enum @@ -3795,9 +3789,9 @@ typedef enum LSM6DSRX_DEC_8 = 2, LSM6DSRX_DEC_32 = 3, } lsm6dsrx_odr_ts_batch_t; -int32_t lsm6dsrx_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, lsm6dsrx_odr_ts_batch_t val); -int32_t lsm6dsrx_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, lsm6dsrx_odr_ts_batch_t *val); typedef enum @@ -3805,32 +3799,32 @@ typedef enum LSM6DSRX_XL_BATCH_EVENT = 0, LSM6DSRX_GYRO_BATCH_EVENT = 1, } lsm6dsrx_trig_counter_bdr_t; -int32_t lsm6dsrx_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, lsm6dsrx_trig_counter_bdr_t val); -int32_t lsm6dsrx_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, lsm6dsrx_trig_counter_bdr_t *val); -int32_t lsm6dsrx_rst_batch_counter_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_rst_batch_counter_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_batch_counter_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsrx_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsrx_fifo_data_level_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsrx_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_status_get(const stmdev_ctx_t *ctx, lsm6dsrx_fifo_status2_t *val); -int32_t lsm6dsrx_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3857,26 +3851,26 @@ typedef enum LSM6DSRX_ROTATION_TAG, LSM6DSRX_SENSORHUB_NACK_TAG = 0x19, } lsm6dsrx_fifo_tag_t; -int32_t lsm6dsrx_fifo_sensor_tag_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, lsm6dsrx_fifo_tag_t *val); -int32_t lsm6dsrx_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_sh_batch_slave_0_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_sh_batch_slave_1_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_sh_batch_slave_2_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_sh_batch_slave_3_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum @@ -3887,9 +3881,9 @@ typedef enum LSM6DSRX_LEVEL_TRIGGER = 2, LSM6DSRX_EDGE_TRIGGER = 4, } lsm6dsrx_den_mode_t; -int32_t lsm6dsrx_den_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_den_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_den_mode_t val); -int32_t lsm6dsrx_den_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_den_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_den_mode_t *val); typedef enum @@ -3897,9 +3891,9 @@ typedef enum LSM6DSRX_DEN_ACT_LOW = 0, LSM6DSRX_DEN_ACT_HIGH = 1, } lsm6dsrx_den_lh_t; -int32_t lsm6dsrx_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dsrx_den_lh_t val); -int32_t lsm6dsrx_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dsrx_den_lh_t *val); typedef enum @@ -3908,34 +3902,34 @@ typedef enum LSM6DSRX_STAMP_IN_XL_DATA = 1, LSM6DSRX_STAMP_IN_GY_XL_DATA = 2, } lsm6dsrx_den_xl_g_t; -int32_t lsm6dsrx_den_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_den_enable_set(const stmdev_ctx_t *ctx, lsm6dsrx_den_xl_g_t val); -int32_t lsm6dsrx_den_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_den_enable_get(const stmdev_ctx_t *ctx, lsm6dsrx_den_xl_g_t *val); -int32_t lsm6dsrx_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_pedo_step_detect_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pedo_step_detect_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_pedo_debounce_steps_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsrx_pedo_debounce_steps_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsrx_pedo_steps_period_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pedo_steps_period_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsrx_pedo_steps_period_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pedo_steps_period_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum @@ -3943,32 +3937,32 @@ typedef enum LSM6DSRX_EVERY_STEP = 0, LSM6DSRX_COUNT_OVERFLOW = 1, } lsm6dsrx_carry_count_en_t; -int32_t lsm6dsrx_pedo_int_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pedo_int_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_carry_count_en_t val); -int32_t lsm6dsrx_pedo_int_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_pedo_int_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_carry_count_en_t *val); -int32_t lsm6dsrx_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_motion_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_motion_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsrx_mag_sensitivity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsrx_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsrx_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsrx_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsrx_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsrx_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsrx_mag_soft_iron_set(stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsrx_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsrx_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsrx_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum { @@ -3979,9 +3973,9 @@ typedef enum LSM6DSRX_Z_EQ_MIN_Z = 4, LSM6DSRX_Z_EQ_Z = 5, } lsm6dsrx_mag_z_axis_t; -int32_t lsm6dsrx_mag_z_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_mag_z_orient_set(const stmdev_ctx_t *ctx, lsm6dsrx_mag_z_axis_t val); -int32_t lsm6dsrx_mag_z_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_mag_z_orient_get(const stmdev_ctx_t *ctx, lsm6dsrx_mag_z_axis_t *val); typedef enum @@ -3993,9 +3987,9 @@ typedef enum LSM6DSRX_Y_EQ_MIN_Z = 4, LSM6DSRX_Y_EQ_Z = 5, } lsm6dsrx_mag_y_axis_t; -int32_t lsm6dsrx_mag_y_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_mag_y_orient_set(const stmdev_ctx_t *ctx, lsm6dsrx_mag_y_axis_t val); -int32_t lsm6dsrx_mag_y_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_mag_y_orient_get(const stmdev_ctx_t *ctx, lsm6dsrx_mag_y_axis_t *val); typedef enum @@ -4007,29 +4001,29 @@ typedef enum LSM6DSRX_X_EQ_MIN_Z = 4, LSM6DSRX_X_EQ_Z = 5, } lsm6dsrx_mag_x_axis_t; -int32_t lsm6dsrx_mag_x_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_mag_x_orient_set(const stmdev_ctx_t *ctx, lsm6dsrx_mag_x_axis_t val); -int32_t lsm6dsrx_mag_x_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_mag_x_orient_get(const stmdev_ctx_t *ctx, lsm6dsrx_mag_x_axis_t *val); -int32_t lsm6dsrx_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { lsm6dsrx_fsm_enable_a_t fsm_enable_a; lsm6dsrx_fsm_enable_b_t fsm_enable_b; } lsm6dsrx_emb_fsm_enable_t; -int32_t lsm6dsrx_fsm_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fsm_enable_set(const stmdev_ctx_t *ctx, lsm6dsrx_emb_fsm_enable_t *val); -int32_t lsm6dsrx_fsm_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fsm_enable_get(const stmdev_ctx_t *ctx, lsm6dsrx_emb_fsm_enable_t *val); -int32_t lsm6dsrx_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsrx_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsrx_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsrx_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum { @@ -4037,9 +4031,9 @@ typedef enum LSM6DSRX_LC_CLEAR = 1, LSM6DSRX_LC_CLEAR_DONE = 2, } lsm6dsrx_fsm_lc_clr_t; -int32_t lsm6dsrx_long_clr_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_long_clr_set(const stmdev_ctx_t *ctx, lsm6dsrx_fsm_lc_clr_t val); -int32_t lsm6dsrx_long_clr_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_long_clr_get(const stmdev_ctx_t *ctx, lsm6dsrx_fsm_lc_clr_t *val); typedef struct @@ -4061,7 +4055,7 @@ typedef struct lsm6dsrx_fsm_outs15_t fsm_outs15; lsm6dsrx_fsm_outs16_t fsm_outs16; } lsm6dsrx_fsm_out_t; -int32_t lsm6dsrx_fsm_out_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dsrx_fsm_out_t *val); typedef enum @@ -4071,33 +4065,33 @@ typedef enum LSM6DSRX_ODR_FSM_52Hz = 2, LSM6DSRX_ODR_FSM_104Hz = 3, } lsm6dsrx_fsm_odr_t; -int32_t lsm6dsrx_fsm_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fsm_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsrx_fsm_odr_t val); -int32_t lsm6dsrx_fsm_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fsm_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsrx_fsm_odr_t *val); -int32_t lsm6dsrx_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_long_cnt_int_value_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsrx_long_cnt_int_value_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsrx_fsm_number_of_programs_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsrx_fsm_number_of_programs_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsrx_fsm_start_address_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsrx_fsm_start_address_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsrx_mlc_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_mlc_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_mlc_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_mlc_status_get(const stmdev_ctx_t *ctx, lsm6dsrx_mlc_status_mainpage_t *val); typedef enum @@ -4107,16 +4101,16 @@ typedef enum LSM6DSRX_ODR_PRGS_52Hz = 2, LSM6DSRX_ODR_PRGS_104Hz = 3, } lsm6dsrx_mlc_odr_t; -int32_t lsm6dsrx_mlc_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_mlc_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsrx_mlc_odr_t val); -int32_t lsm6dsrx_mlc_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_mlc_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsrx_mlc_odr_t *val); -int32_t lsm6dsrx_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6dsrx_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm6dsrx_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_mlc_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsrx_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef struct @@ -4140,7 +4134,7 @@ typedef struct lsm6dsrx_sensor_hub_17_t sh_byte_17; lsm6dsrx_sensor_hub_18_t sh_byte_18; } lsm6dsrx_emb_sh_read_t; -int32_t lsm6dsrx_sh_read_data_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_read_data_raw_get(const stmdev_ctx_t *ctx, lsm6dsrx_emb_sh_read_t *val); typedef enum @@ -4150,35 +4144,35 @@ typedef enum LSM6DSRX_SLV_0_1_2 = 2, LSM6DSRX_SLV_0_1_2_3 = 3, } lsm6dsrx_aux_sens_on_t; -int32_t lsm6dsrx_sh_slave_connected_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_slave_connected_set(const stmdev_ctx_t *ctx, lsm6dsrx_aux_sens_on_t val); -int32_t lsm6dsrx_sh_slave_connected_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_slave_connected_get(const stmdev_ctx_t *ctx, lsm6dsrx_aux_sens_on_t *val); -int32_t lsm6dsrx_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSRX_EXT_PULL_UP = 0, LSM6DSRX_INTERNAL_PULL_UP = 1, } lsm6dsrx_shub_pu_en_t; -int32_t lsm6dsrx_sh_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_shub_pu_en_t val); -int32_t lsm6dsrx_sh_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_shub_pu_en_t *val); -int32_t lsm6dsrx_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSRX_EXT_ON_INT2_PIN = 1, LSM6DSRX_XL_GY_DRDY = 0, } lsm6dsrx_start_config_t; -int32_t lsm6dsrx_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_syncro_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_start_config_t val); -int32_t lsm6dsrx_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_syncro_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_start_config_t *val); typedef enum @@ -4186,13 +4180,13 @@ typedef enum LSM6DSRX_EACH_SH_CYCLE = 0, LSM6DSRX_ONLY_FIRST_CYCLE = 1, } lsm6dsrx_write_once_t; -int32_t lsm6dsrx_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_write_mode_set(const stmdev_ctx_t *ctx, lsm6dsrx_write_once_t val); -int32_t lsm6dsrx_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_write_mode_get(const stmdev_ctx_t *ctx, lsm6dsrx_write_once_t *val); -int32_t lsm6dsrx_sh_reset_set(stmdev_ctx_t *ctx); -int32_t lsm6dsrx_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_sh_reset_set(const stmdev_ctx_t *ctx); +int32_t lsm6dsrx_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -4201,9 +4195,9 @@ typedef enum LSM6DSRX_SH_ODR_26Hz = 2, LSM6DSRX_SH_ODR_13Hz = 3, } lsm6dsrx_shub_odr_t; -int32_t lsm6dsrx_sh_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsrx_shub_odr_t val); -int32_t lsm6dsrx_sh_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsrx_shub_odr_t *val); typedef struct @@ -4212,7 +4206,7 @@ typedef struct uint8_t slv0_subadd; uint8_t slv0_data; } lsm6dsrx_sh_cfg_write_t; -int32_t lsm6dsrx_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_cfg_write(const stmdev_ctx_t *ctx, lsm6dsrx_sh_cfg_write_t *val); typedef struct @@ -4221,16 +4215,16 @@ typedef struct uint8_t slv_subadd; uint8_t slv_len; } lsm6dsrx_sh_cfg_read_t; -int32_t lsm6dsrx_sh_slv0_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, lsm6dsrx_sh_cfg_read_t *val); -int32_t lsm6dsrx_sh_slv1_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, lsm6dsrx_sh_cfg_read_t *val); -int32_t lsm6dsrx_sh_slv2_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, lsm6dsrx_sh_cfg_read_t *val); -int32_t lsm6dsrx_sh_slv3_cfg_read(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, lsm6dsrx_sh_cfg_read_t *val); -int32_t lsm6dsrx_sh_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_sh_status_get(const stmdev_ctx_t *ctx, lsm6dsrx_status_master_t *val); typedef enum @@ -4238,13 +4232,13 @@ typedef enum LSM6DSRX_S4S_TPH_7bit = 0, LSM6DSRX_S4S_TPH_15bit = 1, } lsm6dsrx_s4s_tph_res_t; -int32_t lsm6dsrx_s4s_tph_res_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_s4s_tph_res_set(const stmdev_ctx_t *ctx, lsm6dsrx_s4s_tph_res_t val); -int32_t lsm6dsrx_s4s_tph_res_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_s4s_tph_res_get(const stmdev_ctx_t *ctx, lsm6dsrx_s4s_tph_res_t *val); -int32_t lsm6dsrx_s4s_tph_val_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsrx_s4s_tph_val_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsrx_s4s_tph_val_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsrx_s4s_tph_val_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum { @@ -4253,16 +4247,16 @@ typedef enum LSM6DSRX_S4S_DT_RES_13 = 2, LSM6DSRX_S4S_DT_RES_14 = 3, } lsm6dsrx_s4s_res_ratio_t; -int32_t lsm6dsrx_s4s_res_ratio_set(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_s4s_res_ratio_set(const stmdev_ctx_t *ctx, lsm6dsrx_s4s_res_ratio_t val); -int32_t lsm6dsrx_s4s_res_ratio_get(stmdev_ctx_t *ctx, +int32_t lsm6dsrx_s4s_res_ratio_get(const stmdev_ctx_t *ctx, lsm6dsrx_s4s_res_ratio_t *val); -int32_t lsm6dsrx_s4s_command_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_s4s_command_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_s4s_command_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_s4s_command_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsrx_s4s_dt_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsrx_s4s_dt_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsrx_s4s_dt_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsrx_s4s_dt_get(const stmdev_ctx_t *ctx, uint8_t *val); /** *@} diff --git a/sensor/stmemsc/lsm6dsv16b_STdC/driver/lsm6dsv16b_reg.c b/sensor/stmemsc/lsm6dsv16b_STdC/driver/lsm6dsv16b_reg.c new file mode 100644 index 00000000..e27f9071 --- /dev/null +++ b/sensor/stmemsc/lsm6dsv16b_STdC/driver/lsm6dsv16b_reg.c @@ -0,0 +1,7664 @@ +/** + ****************************************************************************** + * @file lsm6dsv16b_reg.c + * @author Sensors Software Solution Team + * @brief LSM6DSV16B driver file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2024 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "lsm6dsv16b_reg.h" + +/** + * @defgroup LSM6DSV16B + * @brief This file provides a set of functions needed to drive the + * lsm6dsv16b enhanced inertial module. + * @{ + * + */ + +/** + * @defgroup Interfaces functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +/** + * @brief Read generic device register + * + * @param ctx communication interface handler.(ptr) + * @param reg first register address to read. + * @param data buffer for data read.(ptr) + * @param len number of consecutive register to read. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak lsm6dsv16b_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) +{ + int32_t ret; + + if (ctx == NULL) + { + return -1; + } + + ret = ctx->read_reg(ctx->handle, reg, data, len); + + return ret; +} + +/** + * @brief Write generic device register + * + * @param ctx communication interface handler.(ptr) + * @param reg first register address to write. + * @param data the buffer contains data to be written.(ptr) + * @param len number of consecutive register to write. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak lsm6dsv16b_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) +{ + int32_t ret; + + if (ctx == NULL) + { + return -1; + } + + ret = ctx->write_reg(ctx->handle, reg, data, len); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Private functions + * @brief Section collect all the utility functions needed by APIs. + * @{ + * + */ + +static void bytecpy(uint8_t *target, uint8_t *source) +{ + if ((target != NULL) && (source != NULL)) + { + *target = *source; + } +} + +/** + * @} + * + */ + +/** + * @defgroup Sensitivity + * @brief These functions convert raw-data into engineering units. + * @{ + * + */ +float_t lsm6dsv16b_from_sflp_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.061f; +} + +float_t lsm6dsv16b_from_fs2_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.061f; +} + +float_t lsm6dsv16b_from_fs4_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.122f; +} + +float_t lsm6dsv16b_from_fs8_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.244f; +} + +float_t lsm6dsv16b_from_fs16_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.488f; +} + +float_t lsm6dsv16b_from_fs125_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 4.375f; +} + +float_t lsm6dsv16b_from_fs250_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 8.750f; +} + +float_t lsm6dsv16b_from_fs500_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 17.50f; +} + +float_t lsm6dsv16b_from_fs1000_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 35.0f; +} + +float_t lsm6dsv16b_from_fs2000_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 70.0f; +} + +float_t lsm6dsv16b_from_fs4000_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 140.0f; +} + +float_t lsm6dsv16b_from_lsb_to_celsius(int16_t lsb) +{ + return (((float_t)lsb / 256.0f) + 25.0f); +} + +uint64_t lsm6dsv16b_from_lsb_to_nsec(uint32_t lsb) +{ + return ((uint64_t)lsb * 21750); +} + +float_t lsm6dsv16b_from_lsb_to_mv(int16_t lsb) +{ + return ((float_t)lsb) / 78.0f; +} + +/** + * @} + * + */ + +/** + * @defgroup Common + * @brief This section groups common useful functions. + * + */ + +/** + * @brief Reset of the device.[set] + * + * @param ctx read / write interface definitions + * @param val Reset of the device. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_reset_set(const stmdev_ctx_t *ctx, lsm6dsv16b_reset_t val) +{ + lsm6dsv16b_func_cfg_access_t func_cfg_access; + lsm6dsv16b_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + ctrl3.boot = ((uint8_t)val & 0x04U) >> 2; + ctrl3.sw_reset = ((uint8_t)val & 0x02U) >> 1; + func_cfg_access.sw_por = (uint8_t)val & 0x01U; + + if (ret == 0) + { + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL3, (uint8_t *)&ctrl3, 1); + } + if (ret == 0) + { + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Global reset of the device.[get] + * + * @param ctx read / write interface definitions + * @param val Global reset of the device. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_reset_get(const stmdev_ctx_t *ctx, lsm6dsv16b_reset_t *val) +{ + lsm6dsv16b_func_cfg_access_t func_cfg_access; + lsm6dsv16b_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + switch ((ctrl3.sw_reset << 2) + (ctrl3.boot << 1) + func_cfg_access.sw_por) + { + case LSM6DSV16B_READY: + *val = LSM6DSV16B_READY; + break; + + case LSM6DSV16B_GLOBAL_RST: + *val = LSM6DSV16B_GLOBAL_RST; + break; + + case LSM6DSV16B_RESTORE_CAL_PARAM: + *val = LSM6DSV16B_RESTORE_CAL_PARAM; + break; + + case LSM6DSV16B_RESTORE_CTRL_REGS: + *val = LSM6DSV16B_RESTORE_CTRL_REGS; + break; + + default: + *val = LSM6DSV16B_GLOBAL_RST; + break; + } + return ret; +} + +/** + * @brief Change memory bank.[set] + * + * @param ctx read / write interface definitions + * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dsv16b_mem_bank_t val) +{ + lsm6dsv16b_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret == 0) + { + func_cfg_access.emb_func_reg_access = (uint8_t)val & 0x01U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Change memory bank.[get] + * + * @param ctx read / write interface definitions + * @param val MAIN_MEM_BANK, SENSOR_HUB_MEM_BANK, EMBED_FUNC_MEM_BANK, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dsv16b_mem_bank_t *val) +{ + lsm6dsv16b_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + switch (func_cfg_access.emb_func_reg_access) + { + case LSM6DSV16B_MAIN_MEM_BANK: + *val = LSM6DSV16B_MAIN_MEM_BANK; + break; + + case LSM6DSV16B_EMBED_FUNC_MEM_BANK: + *val = LSM6DSV16B_EMBED_FUNC_MEM_BANK; + break; + + default: + *val = LSM6DSV16B_MAIN_MEM_BANK; + break; + } + return ret; +} + +/** + * @brief Device ID.[get] + * + * @param ctx read / write interface definitions + * @param val Device ID. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16b_who_am_i_t who_am_i; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WHO_AM_I, (uint8_t *)&who_am_i, 1); + *val = who_am_i.id; + + return ret; +} + +/** + * @brief Accelerometer output data rate (ODR) selection.[set] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv16b_xl_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_xl_data_rate_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_xl_data_rate_t val) +{ + lsm6dsv16b_ctrl1_t ctrl1; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret == 0) + { + ctrl1.odr_xl = (uint8_t)val & 0xFU; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL1, (uint8_t *)&ctrl1, 1); + } + + return ret; +} + +/** + * @brief Accelerometer output data rate (ODR) selection.[get] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv16b_xl_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_xl_data_rate_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_xl_data_rate_t *val) +{ + lsm6dsv16b_ctrl1_t ctrl1; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL1, (uint8_t *)&ctrl1, 1); + + switch (ctrl1.odr_xl) + { + case LSM6DSV16B_XL_ODR_OFF: + *val = LSM6DSV16B_XL_ODR_OFF; + break; + + case LSM6DSV16B_XL_ODR_AT_1Hz875: + *val = LSM6DSV16B_XL_ODR_AT_1Hz875; + break; + + case LSM6DSV16B_XL_ODR_AT_7Hz5: + *val = LSM6DSV16B_XL_ODR_AT_7Hz5; + break; + + case LSM6DSV16B_XL_ODR_AT_15Hz: + *val = LSM6DSV16B_XL_ODR_AT_15Hz; + break; + + case LSM6DSV16B_XL_ODR_AT_30Hz: + *val = LSM6DSV16B_XL_ODR_AT_30Hz; + break; + + case LSM6DSV16B_XL_ODR_AT_60Hz: + *val = LSM6DSV16B_XL_ODR_AT_60Hz; + break; + + case LSM6DSV16B_XL_ODR_AT_120Hz: + *val = LSM6DSV16B_XL_ODR_AT_120Hz; + break; + + case LSM6DSV16B_XL_ODR_AT_240Hz: + *val = LSM6DSV16B_XL_ODR_AT_240Hz; + break; + + case LSM6DSV16B_XL_ODR_AT_480Hz: + *val = LSM6DSV16B_XL_ODR_AT_480Hz; + break; + + case LSM6DSV16B_XL_ODR_AT_960Hz: + *val = LSM6DSV16B_XL_ODR_AT_960Hz; + break; + + case LSM6DSV16B_XL_ODR_AT_1920Hz: + *val = LSM6DSV16B_XL_ODR_AT_1920Hz; + break; + + case LSM6DSV16B_XL_ODR_AT_3840Hz: + *val = LSM6DSV16B_XL_ODR_AT_3840Hz; + break; + + case LSM6DSV16B_XL_ODR_AT_7680Hz: + *val = LSM6DSV16B_XL_ODR_AT_7680Hz; + break; + + default: + *val = LSM6DSV16B_XL_ODR_OFF; + break; + } + return ret; +} + +/** + * @brief Accelerometer operating mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv16b_xl_mode_t struct + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_xl_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16b_xl_mode_t val) +{ + lsm6dsv16b_ctrl1_t ctrl1; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL1, (uint8_t *)&ctrl1, 1); + + if (ret == 0) + { + ctrl1.op_mode_xl = (uint8_t)val & 0x07U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL1, (uint8_t *)&ctrl1, 1); + } + + return ret; +} + +/** + * @brief Accelerometer operating mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv16b_xl_mode_t struct + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_xl_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16b_xl_mode_t *val) +{ + lsm6dsv16b_ctrl1_t ctrl1; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL1, (uint8_t *)&ctrl1, 1); + + switch (ctrl1.op_mode_xl) + { + case LSM6DSV16B_XL_HIGH_PERFORMANCE_MD: + *val = LSM6DSV16B_XL_HIGH_PERFORMANCE_MD; + break; + + case LSM6DSV16B_XL_HIGH_PERFORMANCE_TDM_MD: + *val = LSM6DSV16B_XL_HIGH_PERFORMANCE_TDM_MD; + break; + + case LSM6DSV16B_XL_LOW_POWER_2_AVG_MD: + *val = LSM6DSV16B_XL_LOW_POWER_2_AVG_MD; + break; + + case LSM6DSV16B_XL_LOW_POWER_4_AVG_MD: + *val = LSM6DSV16B_XL_LOW_POWER_4_AVG_MD; + break; + + case LSM6DSV16B_XL_LOW_POWER_8_AVG_MD: + *val = LSM6DSV16B_XL_LOW_POWER_8_AVG_MD; + break; + + default: + *val = LSM6DSV16B_XL_HIGH_PERFORMANCE_MD; + break; + } + return ret; +} + +/** + * @brief Gyroscope output data rate (ODR) selection.[set] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv16b_gy_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_gy_data_rate_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_gy_data_rate_t val) +{ + lsm6dsv16b_ctrl2_t ctrl2; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL2, (uint8_t *)&ctrl2, 1); + + if (ret == 0) + { + ctrl2.odr_g = (uint8_t)val & 0xFU; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL2, (uint8_t *)&ctrl2, 1); + } + + return ret; +} + +/** + * @brief Gyroscope output data rate (ODR) selection.[get] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv16b_gy_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_gy_data_rate_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_gy_data_rate_t *val) +{ + lsm6dsv16b_ctrl2_t ctrl2; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL2, (uint8_t *)&ctrl2, 1); + + switch (ctrl2.odr_g) + { + case LSM6DSV16B_GY_ODR_OFF: + *val = LSM6DSV16B_GY_ODR_OFF; + break; + + case LSM6DSV16B_GY_ODR_AT_7Hz5: + *val = LSM6DSV16B_GY_ODR_AT_7Hz5; + break; + + case LSM6DSV16B_GY_ODR_AT_15Hz: + *val = LSM6DSV16B_GY_ODR_AT_15Hz; + break; + + case LSM6DSV16B_GY_ODR_AT_30Hz: + *val = LSM6DSV16B_GY_ODR_AT_30Hz; + break; + + case LSM6DSV16B_GY_ODR_AT_60Hz: + *val = LSM6DSV16B_GY_ODR_AT_60Hz; + break; + + case LSM6DSV16B_GY_ODR_AT_120Hz: + *val = LSM6DSV16B_GY_ODR_AT_120Hz; + break; + + case LSM6DSV16B_GY_ODR_AT_240Hz: + *val = LSM6DSV16B_GY_ODR_AT_240Hz; + break; + + case LSM6DSV16B_GY_ODR_AT_480Hz: + *val = LSM6DSV16B_GY_ODR_AT_480Hz; + break; + + case LSM6DSV16B_GY_ODR_AT_960Hz: + *val = LSM6DSV16B_GY_ODR_AT_960Hz; + break; + + case LSM6DSV16B_GY_ODR_AT_1920Hz: + *val = LSM6DSV16B_GY_ODR_AT_1920Hz; + break; + + case LSM6DSV16B_GY_ODR_AT_3840Hz: + *val = LSM6DSV16B_GY_ODR_AT_3840Hz; + break; + + case LSM6DSV16B_GY_ODR_AT_7680Hz: + *val = LSM6DSV16B_GY_ODR_AT_7680Hz; + break; + + default: + *val = LSM6DSV16B_GY_ODR_OFF; + break; + } + return ret; +} + +/** + * @brief Gyroscope operating mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURANCY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_gy_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16b_gy_mode_t val) +{ + lsm6dsv16b_ctrl2_t ctrl2; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret == 0) + { + ctrl2.op_mode_g = (uint8_t)val & 0x07U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL2, (uint8_t *)&ctrl2, 1); + } + + return ret; +} + +/** + * @brief Gyroscope operating mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURANCY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_gy_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16b_gy_mode_t *val) +{ + lsm6dsv16b_ctrl2_t ctrl2; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL2, (uint8_t *)&ctrl2, 1); + switch (ctrl2.op_mode_g) + { + case LSM6DSV16B_GY_HIGH_PERFORMANCE_MD: + *val = LSM6DSV16B_GY_HIGH_PERFORMANCE_MD; + break; + + case LSM6DSV16B_GY_SLEEP_MD: + *val = LSM6DSV16B_GY_SLEEP_MD; + break; + + case LSM6DSV16B_GY_LOW_POWER_MD: + *val = LSM6DSV16B_GY_LOW_POWER_MD; + break; + + default: + *val = LSM6DSV16B_GY_HIGH_PERFORMANCE_MD; + break; + } + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[set] + * + * @param ctx read / write interface definitions + * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16b_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret == 0) + { + ctrl3.if_inc = val; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL3, (uint8_t *)&ctrl3, 1); + } + + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[get] + * + * @param ctx read / write interface definitions + * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16b_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL3, (uint8_t *)&ctrl3, 1); + *val = ctrl3.if_inc; + + + return ret; +} + +/** + * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [set] + * + * @param ctx read / write interface definitions + * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16b_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL3, (uint8_t *)&ctrl3, 1); + + if (ret == 0) + { + ctrl3.bdu = val; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL3, (uint8_t *)&ctrl3, 1); + } + + return ret; +} + +/** + * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [get] + * + * @param ctx read / write interface definitions + * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16b_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL3, (uint8_t *)&ctrl3, 1); + *val = ctrl3.bdu; + + return ret; +} + +/** + * @brief Enables pulsed data-ready mode (~75 us).[set] + * + * @param ctx read / write interface definitions + * @param val DRDY_LATCHED, DRDY_PULSED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_data_ready_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_data_ready_mode_t val) +{ + lsm6dsv16b_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL4, (uint8_t *)&ctrl4, 1); + + if (ret == 0) + { + ctrl4.drdy_pulsed = (uint8_t)val & 0x1U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL4, (uint8_t *)&ctrl4, 1); + } + + return ret; +} + +/** + * @brief Enables pulsed data-ready mode (~75 us).[get] + * + * @param ctx read / write interface definitions + * @param val DRDY_LATCHED, DRDY_PULSED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_data_ready_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_data_ready_mode_t *val) +{ + lsm6dsv16b_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL4, (uint8_t *)&ctrl4, 1); + + switch (ctrl4.drdy_pulsed) + { + case LSM6DSV16B_DRDY_LATCHED: + *val = LSM6DSV16B_DRDY_LATCHED; + break; + + case LSM6DSV16B_DRDY_PULSED: + *val = LSM6DSV16B_DRDY_PULSED; + break; + + default: + *val = LSM6DSV16B_DRDY_LATCHED; + break; + } + return ret; +} + +/** + * @brief Gyroscope full-scale selection[set] + * + * @param ctx read / write interface definitions + * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_gy_full_scale_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_gy_full_scale_t val) +{ + lsm6dsv16b_ctrl6_t ctrl6; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL6, (uint8_t *)&ctrl6, 1); + + if (ret == 0) + { + ctrl6.fs_g = (uint8_t)val & 0xFU; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL6, (uint8_t *)&ctrl6, 1); + } + + return ret; +} + +/** + * @brief Gyroscope full-scale selection[get] + * + * @param ctx read / write interface definitions + * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_gy_full_scale_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_gy_full_scale_t *val) +{ + lsm6dsv16b_ctrl6_t ctrl6; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL6, (uint8_t *)&ctrl6, 1); + + switch (ctrl6.fs_g) + { + case LSM6DSV16B_125dps: + *val = LSM6DSV16B_125dps; + break; + + case LSM6DSV16B_250dps: + *val = LSM6DSV16B_250dps; + break; + + case LSM6DSV16B_500dps: + *val = LSM6DSV16B_500dps; + break; + + case LSM6DSV16B_1000dps: + *val = LSM6DSV16B_1000dps; + break; + + case LSM6DSV16B_2000dps: + *val = LSM6DSV16B_2000dps; + break; + + case LSM6DSV16B_4000dps: + *val = LSM6DSV16B_4000dps; + break; + + default: + *val = LSM6DSV16B_125dps; + break; + } + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[set] + * + * @param ctx read / write interface definitions + * @param val 2g, 4g, 8g, 16g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_xl_full_scale_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_xl_full_scale_t val) +{ + lsm6dsv16b_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL8, (uint8_t *)&ctrl8, 1); + + if (ret == 0) + { + ctrl8.fs_xl = (uint8_t)val & 0x3U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL8, (uint8_t *)&ctrl8, 1); + } + + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[get] + * + * @param ctx read / write interface definitions + * @param val 2g, 4g, 8g, 16g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_xl_full_scale_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_xl_full_scale_t *val) +{ + lsm6dsv16b_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL8, (uint8_t *)&ctrl8, 1); + + switch (ctrl8.fs_xl) + { + case LSM6DSV16B_2g: + *val = LSM6DSV16B_2g; + break; + + case LSM6DSV16B_4g: + *val = LSM6DSV16B_4g; + break; + + case LSM6DSV16B_8g: + *val = LSM6DSV16B_8g; + break; + + case LSM6DSV16B_16g: + *val = LSM6DSV16B_16g; + break; + + default: + *val = LSM6DSV16B_2g; + break; + } + return ret; +} + +/** + * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[set] + * + * @param ctx read / write interface definitions + * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_xl_dual_channel_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16b_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL8, (uint8_t *)&ctrl8, 1); + + if (ret == 0) + { + ctrl8.xl_dualc_en = val; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL8, (uint8_t *)&ctrl8, 1); + } + + return ret; +} + +/** + * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[get] + * + * @param ctx read / write interface definitions + * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16b_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL8, (uint8_t *)&ctrl8, 1); + *val = ctrl8.xl_dualc_en; + + return ret; +} + +/** + * @brief Accelerometer self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_xl_self_test_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_xl_self_test_t val) +{ + lsm6dsv16b_ctrl10_t ctrl10; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL10, (uint8_t *)&ctrl10, 1); + + if (ret == 0) + { + ctrl10.st_xl = (uint8_t)val & 0x3U; + ctrl10.xl_st_offset = ((uint8_t)val & 0x04U) >> 2; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL10, (uint8_t *)&ctrl10, 1); + } + + return ret; +} + +/** + * @brief Accelerometer self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_xl_self_test_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_xl_self_test_t *val) +{ + lsm6dsv16b_ctrl10_t ctrl10; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL10, (uint8_t *)&ctrl10, 1); + + //switch (ctrl10.xl_st_offset) + switch (ctrl10.st_xl) + { + case LSM6DSV16B_XL_ST_DISABLE: + *val = LSM6DSV16B_XL_ST_DISABLE; + break; + + case LSM6DSV16B_XL_ST_POSITIVE: + *val = LSM6DSV16B_XL_ST_POSITIVE; + break; + + case LSM6DSV16B_XL_ST_NEGATIVE: + *val = LSM6DSV16B_XL_ST_NEGATIVE; + break; + + default: + *val = LSM6DSV16B_XL_ST_DISABLE; + break; + } + return ret; +} + +/** + * @brief Gyroscope self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_gy_self_test_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_gy_self_test_t val) +{ + lsm6dsv16b_ctrl10_t ctrl10; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL10, (uint8_t *)&ctrl10, 1); + + if (ret == 0) + { + ctrl10.st_g = (uint8_t)val & 0x3U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL10, (uint8_t *)&ctrl10, 1); + } + + return ret; +} + +/** + * @brief Gyroscope self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_gy_self_test_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_gy_self_test_t *val) +{ + lsm6dsv16b_ctrl10_t ctrl10; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL10, (uint8_t *)&ctrl10, 1); + + switch (ctrl10.st_g) + { + case LSM6DSV16B_GY_ST_DISABLE: + *val = LSM6DSV16B_GY_ST_DISABLE; + break; + + case LSM6DSV16B_GY_ST_POSITIVE: + *val = LSM6DSV16B_GY_ST_POSITIVE; + break; + + case LSM6DSV16B_GY_ST_NEGATIVE: + *val = LSM6DSV16B_GY_ST_NEGATIVE; + break; + + default: + *val = LSM6DSV16B_GY_ST_DISABLE; + break; + } + return ret; +} + +/** + * @brief Get the status of all the interrupt sources.[get] + * + * @param ctx read / write interface definitions + * @param val Get the status of all the interrupt sources. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_all_sources_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_all_sources_t *val) +{ + lsm6dsv16b_emb_func_status_mainpage_t emb_func_status_mainpage; + lsm6dsv16b_emb_func_exec_status_t emb_func_exec_status; + lsm6dsv16b_fsm_status_mainpage_t fsm_status_mainpage; + lsm6dsv16b_functions_enable_t functions_enable; + lsm6dsv16b_emb_func_src_t emb_func_src; + lsm6dsv16b_fifo_status2_t fifo_status2; + lsm6dsv16b_all_int_src_t all_int_src; + lsm6dsv16b_wake_up_src_t wake_up_src; + lsm6dsv16b_status_reg_t status_reg; + lsm6dsv16b_d6d_src_t d6d_src; + lsm6dsv16b_tap_src_t tap_src; + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret == 0) + { + functions_enable.dis_rst_lir_all_int = PROPERTY_ENABLE; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_STATUS1, (uint8_t *)&buff, 4); + } + bytecpy((uint8_t *)&fifo_status2, &buff[1]); + bytecpy((uint8_t *)&all_int_src, &buff[2]); + bytecpy((uint8_t *)&status_reg, &buff[3]); + + val->fifo_ovr = fifo_status2.fifo_ovr_ia; + val->fifo_bdr = fifo_status2.counter_bdr_ia; + val->fifo_full = fifo_status2.fifo_full_ia; + val->fifo_th = fifo_status2.fifo_wtm_ia; + + val->free_fall = all_int_src.ff_ia; + val->wake_up = all_int_src.wu_ia; + val->six_d = all_int_src.d6d_ia; + + val->drdy_xl = status_reg.xlda; + val->drdy_gy = status_reg.gda; + val->drdy_temp = status_reg.tda; + val->timestamp = status_reg.timestamp_endcount; + + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + if (ret == 0) + { + functions_enable.dis_rst_lir_all_int = PROPERTY_DISABLE; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_SRC, (uint8_t *)&buff, 6); + } + + if (ret == 0) + { + bytecpy((uint8_t *)&wake_up_src, &buff[0]); + bytecpy((uint8_t *)&tap_src, &buff[1]); + bytecpy((uint8_t *)&d6d_src, &buff[2]); + bytecpy((uint8_t *)&emb_func_status_mainpage, &buff[4]); + bytecpy((uint8_t *)&fsm_status_mainpage, &buff[5]); + + val->sleep_change = wake_up_src.sleep_change_ia; + val->wake_up_x = wake_up_src.x_wu; + val->wake_up_y = wake_up_src.y_wu; + val->wake_up_z = wake_up_src.z_wu; + val->sleep_state = wake_up_src.sleep_state; + + val->tap_x = tap_src.x_tap; + val->tap_y = tap_src.y_tap; + val->tap_z = tap_src.z_tap; + val->tap_sign = tap_src.tap_sign; + val->double_tap = tap_src.double_tap; + val->single_tap = tap_src.single_tap; + + val->six_d_zl = d6d_src.zl; + val->six_d_zh = d6d_src.zh; + val->six_d_yl = d6d_src.yl; + val->six_d_yh = d6d_src.yh; + val->six_d_xl = d6d_src.xl; + val->six_d_xh = d6d_src.xh; + + val->step_detector = emb_func_status_mainpage.is_step_det; + val->tilt = emb_func_status_mainpage.is_tilt; + val->sig_mot = emb_func_status_mainpage.is_sigmot; + val->fsm_lc = emb_func_status_mainpage.is_fsm_lc; + + val->fsm1 = fsm_status_mainpage.is_fsm1; + val->fsm2 = fsm_status_mainpage.is_fsm2; + val->fsm3 = fsm_status_mainpage.is_fsm3; + val->fsm4 = fsm_status_mainpage.is_fsm4; + val->fsm5 = fsm_status_mainpage.is_fsm5; + val->fsm6 = fsm_status_mainpage.is_fsm6; + val->fsm7 = fsm_status_mainpage.is_fsm7; + val->fsm8 = fsm_status_mainpage.is_fsm8; + + } + + + if (ret == 0) + { + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, + 1); + } + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + val->emb_func_stand_by = emb_func_exec_status.emb_func_endop; + val->emb_func_time_exceed = emb_func_exec_status.emb_func_exec_ovr; + val->step_count_inc = emb_func_src.stepcounter_bit_set; + val->step_count_overflow = emb_func_src.step_overflow; + val->step_on_delta_time = emb_func_src.step_count_delta_ia; + + val->step_detector = emb_func_src.step_detected; + + return ret; +} + +int32_t lsm6dsv16b_flag_data_ready_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_data_ready_t *val) +{ + lsm6dsv16b_status_reg_t status; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_STATUS_REG, (uint8_t *)&status, 1); + val->drdy_xl = status.xlda; + val->drdy_gy = status.gda; + val->drdy_temp = status.tda; + + return ret; +} + +/** + * @brief Temperature data output register[get] + * + * @param ctx read / write interface definitions + * @param val Temperature data output register + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_OUT_TEMP_L, &buff[0], 2); + *val = (int16_t)buff[1]; + *val = (*val * 256) + (int16_t)buff[0]; + + return ret; +} + +/** + * @brief Angular rate sensor.[get] + * + * @param ctx read / write interface definitions + * @param val Angular rate sensor. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_OUTX_L_G, &buff[0], 6); + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Linear acceleration sensor.[get] + * + * @param ctx read / write interface definitions + * @param val Linear acceleration sensor. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_OUTZ_L_A, &buff[0], 6); + val[2] = (int16_t)buff[1]; + val[2] = (val[2] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[0] = (int16_t)buff[5]; + val[0] = (val[0] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Linear acceleration sensor for Dual channel mode.[get] + * + * @param ctx read / write interface definitions + * @param val Linear acceleration sensor or Dual channel mode. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_UI_OUTZ_L_A_DUALC, &buff[0], 6); + val[2] = (int16_t)buff[1]; + val[2] = (val[2] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[0] = (int16_t)buff[5]; + val[0] = (val[0] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement.[get] + * + * @param ctx read / write interface definitions + * @param val Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val) +{ + lsm6dsv16b_internal_freq_t internal_freq; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INTERNAL_FREQ, (uint8_t *)&internal_freq, 1); + *val = (int8_t)internal_freq.freq_fine; + + return ret; +} + +/** + * @brief Enable accelerometer axis.[set] + * + * @param ctx read / write interface definitions + * @param val Enable accelerometer axis. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tdm_xl_axis_set(const stmdev_ctx_t *ctx, lsm6dsv16b_tdm_xl_axis_t val) +{ + lsm6dsv16b_tdm_cfg1_t tdm_cfg1; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1); + if (ret == 0) + { + tdm_cfg1.tdm_xl_z_en = val.z; + tdm_cfg1.tdm_xl_y_en = val.y; + tdm_cfg1.tdm_xl_x_en = val.x; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1); + } + + return ret; +} + +/** + * @brief Enable accelerometer axis.[get] + * + * @param ctx read / write interface definitions + * @param val Enable accelerometer axis. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tdm_xl_axis_get(const stmdev_ctx_t *ctx, lsm6dsv16b_tdm_xl_axis_t *val) +{ + lsm6dsv16b_tdm_cfg1_t tdm_cfg1; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1); + val->x = tdm_cfg1.tdm_xl_x_en; + val->y = tdm_cfg1.tdm_xl_y_en; + val->z = tdm_cfg1.tdm_xl_z_en; + + return ret; +} + +/** + * @brief Write buffer in a page.[set] + * + * @param ctx read / write interface definitions + * @param val Write buffer in a page. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len) +{ + lsm6dsv16b_page_address_t page_address; + lsm6dsv16b_page_sel_t page_sel; + lsm6dsv16b_page_rw_t page_rw; + uint8_t msb; + uint8_t lsb; + int32_t ret; + uint8_t i ; + + msb = ((uint8_t)(address >> 8) & 0x0FU); + lsb = (uint8_t)address & 0xFFU; + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + + /* set page write */ + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_ENABLE; + ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); + + /* select page */ + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, 1); + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, + 1); + + /* set page addr */ + page_address.page_addr = lsb; + ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + + for (i = 0; ((i < len) && (ret == 0)); i++) + { + ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_VALUE, &buf[i], 1); + lsb++; + + /* Check if page wrap */ + if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) + { + msb++; + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, 1); + + if (ret == 0) + { + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, + 1); + } + } + } + + page_sel.page_sel = 0; + page_sel.not_used0 = 1;// Default value + ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, + 1); + + /* unset page write */ + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Read buffer in a page.[set] + * + * @param ctx read / write interface definitions + * @param val Write buffer in a page. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len) +{ + lsm6dsv16b_page_address_t page_address; + lsm6dsv16b_page_sel_t page_sel; + lsm6dsv16b_page_rw_t page_rw; + uint8_t msb; + uint8_t lsb; + int32_t ret; + uint8_t i ; + + msb = ((uint8_t)(address >> 8) & 0x0FU); + lsb = (uint8_t)address & 0xFFU; + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + + /* set page write */ + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_ENABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); + + /* select page */ + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, 1); + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, + 1); + + /* set page addr */ + page_address.page_addr = lsb; + ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + + for (i = 0; ((i < len) && (ret == 0)); i++) + { + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_VALUE, &buf[i], 1); + lsb++; + + /* Check if page wrap */ + if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) + { + msb++; + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, 1); + + if (ret == 0) + { + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, + 1); + } + } + } + + page_sel.page_sel = 0; + page_sel.not_used0 = 1;// Default value + ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, + 1); + + /* unset page write */ + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Timestamp + * @brief This section groups all the functions that manage the + * timestamp generation. + * @{ + * + */ + +/** + * @brief Enables timestamp counter.[set] + * + * @param ctx read / write interface definitions + * @param val Enables timestamp counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16b_functions_enable_t functions_enable; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret == 0) + { + functions_enable.timestamp_en = val; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + return ret; +} + +/** + * @brief Enables timestamp counter.[get] + * + * @param ctx read / write interface definitions + * @param val Enables timestamp counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16b_functions_enable_t functions_enable; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + *val = functions_enable.timestamp_en; + + return ret; +} + +/** + * @brief Timestamp data output.[get] + * + * @param ctx read / write interface definitions + * @param val Timestamp data output. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) +{ + uint8_t buff[4]; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TIMESTAMP0, &buff[0], 4); + *val = buff[3]; + *val = (*val * 256U) + buff[2]; + *val = (*val * 256U) + buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Filters + * @brief This section group all the functions concerning the + * filters configuration + * @{ + * + */ + +/** + * @brief Protocol anti-spike filters.[set] + * + * @param ctx read / write interface definitions + * @param val AUTO, ALWAYS_ACTIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_filt_anti_spike_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_anti_spike_t val) +{ + lsm6dsv16b_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + + if (ret == 0) + { + if_cfg.asf_ctrl = (uint8_t)val & 0x01U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Protocol anti-spike filters.[get] + * + * @param ctx read / write interface definitions + * @param val AUTO, ALWAYS_ACTIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_filt_anti_spike_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_anti_spike_t *val) +{ + lsm6dsv16b_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + switch (if_cfg.asf_ctrl) + { + case LSM6DSV16B_AUTO: + *val = LSM6DSV16B_AUTO; + break; + + case LSM6DSV16B_ALWAYS_ACTIVE: + *val = LSM6DSV16B_ALWAYS_ACTIVE; + break; + + default: + *val = LSM6DSV16B_AUTO; + break; + } + return ret; +} + +/** + * @brief It masks DRDY and Interrupts RQ until filter settling ends.[set] + * + * @param ctx read / write interface definitions + * @param val It masks DRDY and Interrupts RQ until filter settling ends. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_filt_settling_mask_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_settling_mask_t val) +{ + lsm6dsv16b_emb_func_cfg_t emb_func_cfg; + lsm6dsv16b_tdm_cfg2_t tdm_cfg2; + lsm6dsv16b_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL4, (uint8_t *)&ctrl4, 1); + + if (ret == 0) + { + ctrl4.drdy_mask = val.drdy; + + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL4, (uint8_t *)&ctrl4, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + } + + if (ret == 0) + { + emb_func_cfg.emb_func_irq_mask_xl_settl = val.irq_xl; + emb_func_cfg.emb_func_irq_mask_g_settl = val.irq_g; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1); + } + + if (ret == 0) + { + tdm_cfg2.tdm_data_mask = val.tdm_excep_code; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1); + } + + return ret; +} + +/** + * @brief It masks DRDY and Interrupts RQ until filter settling ends.[get] + * + * @param ctx read / write interface definitions + * @param val It masks DRDY and Interrupts RQ until filter settling ends. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_filt_settling_mask_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_settling_mask_t *val) +{ + lsm6dsv16b_emb_func_cfg_t emb_func_cfg; + lsm6dsv16b_tdm_cfg2_t tdm_cfg2; + lsm6dsv16b_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + } + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1); + } + + val->drdy = ctrl4.drdy_mask; + val->irq_xl = emb_func_cfg.emb_func_irq_mask_xl_settl; + val->irq_g = emb_func_cfg.emb_func_irq_mask_g_settl; + val->tdm_excep_code = tdm_cfg2.tdm_data_mask; + + return ret; +} + +/** + * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[set] + * + * @param ctx read / write interface definitions + * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_gy_lp1_bandwidth_t val) +{ + lsm6dsv16b_ctrl6_t ctrl6; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL6, (uint8_t *)&ctrl6, 1); + if (ret == 0) + { + ctrl6.lpf1_g_bw = (uint8_t)val & 0x7U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL6, (uint8_t *)&ctrl6, 1); + } + + return ret; +} + +/** + * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[get] + * + * @param ctx read / write interface definitions + * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_gy_lp1_bandwidth_t *val) +{ + lsm6dsv16b_ctrl6_t ctrl6; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL6, (uint8_t *)&ctrl6, 1); + + switch (ctrl6.lpf1_g_bw) + { + case LSM6DSV16B_GY_ULTRA_LIGHT: + *val = LSM6DSV16B_GY_ULTRA_LIGHT; + break; + + case LSM6DSV16B_GY_VERY_LIGHT: + *val = LSM6DSV16B_GY_VERY_LIGHT; + break; + + case LSM6DSV16B_GY_LIGHT: + *val = LSM6DSV16B_GY_LIGHT; + break; + + case LSM6DSV16B_GY_MEDIUM: + *val = LSM6DSV16B_GY_MEDIUM; + break; + + case LSM6DSV16B_GY_STRONG: + *val = LSM6DSV16B_GY_STRONG; + break; + + case LSM6DSV16B_GY_VERY_STRONG: + *val = LSM6DSV16B_GY_VERY_STRONG; + break; + + case LSM6DSV16B_GY_AGGRESSIVE: + *val = LSM6DSV16B_GY_AGGRESSIVE; + break; + + case LSM6DSV16B_GY_XTREME: + *val = LSM6DSV16B_GY_XTREME; + break; + + default: + *val = LSM6DSV16B_GY_ULTRA_LIGHT; + break; + } + return ret; +} + +/** + * @brief It enables gyroscope digital LPF1 filter.[set] + * + * @param ctx read / write interface definitions + * @param val It enables gyroscope digital LPF1 filter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_filt_gy_lp1_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16b_ctrl7_t ctrl7; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL7, (uint8_t *)&ctrl7, 1); + + if (ret == 0) + { + ctrl7.lpf1_g_en = val; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL7, (uint8_t *)&ctrl7, 1); + } + + return ret; +} + +/** + * @brief It enables gyroscope digital LPF1 filter.[get] + * + * @param ctx read / write interface definitions + * @param val It enables gyroscope digital LPF1 filter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16b_ctrl7_t ctrl7; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL7, (uint8_t *)&ctrl7, 1); + *val = ctrl7.lpf1_g_en; + + return ret; +} + +/** + * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[set] + * + * @param ctx read / write interface definitions + * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_xl_lp2_bandwidth_t val) +{ + lsm6dsv16b_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret == 0) + { + ctrl8.hp_lpf2_xl_bw = (uint8_t)val & 0x7U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL8, (uint8_t *)&ctrl8, 1); + } + + return ret; +} + +/** + * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[get] + * + * @param ctx read / write interface definitions + * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_xl_lp2_bandwidth_t *val) +{ + lsm6dsv16b_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL8, (uint8_t *)&ctrl8, 1); + switch (ctrl8.hp_lpf2_xl_bw) + { + case LSM6DSV16B_XL_ULTRA_LIGHT: + *val = LSM6DSV16B_XL_ULTRA_LIGHT; + break; + + case LSM6DSV16B_XL_VERY_LIGHT: + *val = LSM6DSV16B_XL_VERY_LIGHT; + break; + + case LSM6DSV16B_XL_LIGHT: + *val = LSM6DSV16B_XL_LIGHT; + break; + + case LSM6DSV16B_XL_MEDIUM: + *val = LSM6DSV16B_XL_MEDIUM; + break; + + case LSM6DSV16B_XL_STRONG: + *val = LSM6DSV16B_XL_STRONG; + break; + + case LSM6DSV16B_XL_VERY_STRONG: + *val = LSM6DSV16B_XL_VERY_STRONG; + break; + + case LSM6DSV16B_XL_AGGRESSIVE: + *val = LSM6DSV16B_XL_AGGRESSIVE; + break; + + case LSM6DSV16B_XL_XTREME: + *val = LSM6DSV16B_XL_XTREME; + break; + + default: + *val = LSM6DSV16B_XL_ULTRA_LIGHT; + break; + } + return ret; +} + +/** + * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[set] + * + * @param ctx read / write interface definitions + * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_filt_xl_lp2_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16b_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.lpf2_xl_en = val; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[get] + * + * @param ctx read / write interface definitions + * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16b_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.lpf2_xl_en; + + return ret; +} + +/** + * @brief Accelerometer slope filter / high-pass filter selection.[set] + * + * @param ctx read / write interface definitions + * @param val Accelerometer slope filter / high-pass filter selection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_filt_xl_hp_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16b_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.hp_slope_xl_en = val; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Accelerometer slope filter / high-pass filter selection.[get] + * + * @param ctx read / write interface definitions + * @param val Accelerometer slope filter / high-pass filter selection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16b_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.hp_slope_xl_en; + + return ret; +} + +/** + * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[set] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_filt_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16b_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.xl_fastsettl_mode = val; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[get] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16b_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.xl_fastsettl_mode; + + return ret; +} + +/** + * @brief Accelerometer high-pass filter mode.[set] + * + * @param ctx read / write interface definitions + * @param val HP_MD_NORMAL, HP_MD_REFERENCE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_filt_xl_hp_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_xl_hp_mode_t val) +{ + lsm6dsv16b_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.hp_ref_mode_xl = (uint8_t)val & 0x01U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Accelerometer high-pass filter mode.[get] + * + * @param ctx read / write interface definitions + * @param val HP_MD_NORMAL, HP_MD_REFERENCE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_xl_hp_mode_t *val) +{ + lsm6dsv16b_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1); + switch (ctrl9.hp_ref_mode_xl) + { + case LSM6DSV16B_HP_MD_NORMAL: + *val = LSM6DSV16B_HP_MD_NORMAL; + break; + + case LSM6DSV16B_HP_MD_REFERENCE: + *val = LSM6DSV16B_HP_MD_REFERENCE; + break; + + default: + *val = LSM6DSV16B_HP_MD_NORMAL; + break; + } + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[set] + * + * @param ctx read / write interface definitions + * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_wkup_act_feed_t val) +{ + lsm6dsv16b_wake_up_ths_t wake_up_ths; + lsm6dsv16b_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + tap_cfg0.slope_fds = (uint8_t)val & 0x01U; + wake_up_ths.usr_off_on_wu = ((uint8_t)val & 0x02U) >> 1; + + if (ret == 0) + { + + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + if (ret == 0) + { + + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[get] + * + * @param ctx read / write interface definitions + * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_wkup_act_feed_t *val) +{ + lsm6dsv16b_wake_up_ths_t wake_up_ths; + lsm6dsv16b_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + switch ((wake_up_ths.usr_off_on_wu << 1) + tap_cfg0.slope_fds) + { + case LSM6DSV16B_WK_FEED_SLOPE: + *val = LSM6DSV16B_WK_FEED_SLOPE; + break; + + case LSM6DSV16B_WK_FEED_HIGH_PASS: + *val = LSM6DSV16B_WK_FEED_HIGH_PASS; + break; + + case LSM6DSV16B_WK_FEED_LP_WITH_OFFSET: + *val = LSM6DSV16B_WK_FEED_LP_WITH_OFFSET; + break; + + default: + *val = LSM6DSV16B_WK_FEED_SLOPE; + break; + } + return ret; +} + +/** + * @brief Mask hw function triggers when xl is settling.[set] + * + * @param ctx read / write interface definitions + * @param val 0 or 1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_mask_trigger_xl_settl_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16b_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + + if (ret == 0) + { + tap_cfg0.hw_func_mask_xl_settl = val & 0x01U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + return ret; +} + +/** + * @brief Mask hw function triggers when xl is settling.[get] + * + * @param ctx read / write interface definitions + * @param val 0 or 1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16b_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + *val = tap_cfg0.hw_func_mask_xl_settl; + + return ret; +} + + +/** + * @brief LPF2 filter on 6D (sixd) function selection.[set] + * + * @param ctx read / write interface definitions + * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_filt_sixd_feed_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_sixd_feed_t val) +{ + lsm6dsv16b_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret == 0) + { + tap_cfg0.low_pass_on_6d = (uint8_t)val & 0x01U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + return ret; +} + +/** + * @brief LPF2 filter on 6D (sixd) function selection.[get] + * + * @param ctx read / write interface definitions + * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_filt_sixd_feed_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_sixd_feed_t *val) +{ + lsm6dsv16b_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + switch (tap_cfg0.low_pass_on_6d) + { + case LSM6DSV16B_SIXD_FEED_ODR_DIV_2: + *val = LSM6DSV16B_SIXD_FEED_ODR_DIV_2; + break; + + case LSM6DSV16B_SIXD_FEED_LOW_PASS: + *val = LSM6DSV16B_SIXD_FEED_LOW_PASS; + break; + + default: + *val = LSM6DSV16B_SIXD_FEED_ODR_DIV_2; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Serial interfaces + * @brief This section groups all the functions concerning + * serial interfaces management (not auxiliary) + * @{ + * + */ + +/** + * @brief Enables pull-up on SDO pin of UI (User Interface).[set] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDO pin of UI (User Interface). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16b_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret == 0) + { + pin_ctrl.sdo_pu_en = val; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Enables pull-up on SDO pin of UI (User Interface).[get] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDO pin of UI (User Interface). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16b_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + *val = pin_ctrl.sdo_pu_en; + + return ret; +} + +/** + * @brief Disables I2C and I3C on UI (User Interface).[set] + * + * @param ctx read / write interface definitions + * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_ui_i2c_i3c_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_ui_i2c_i3c_mode_t val) +{ + lsm6dsv16b_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.i2c_i3c_disable = (uint8_t)val & 0x01U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Disables I2C and I3C on UI (User Interface).[get] + * + * @param ctx read / write interface definitions + * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_ui_i2c_i3c_mode_t *val) +{ + lsm6dsv16b_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + switch (if_cfg.i2c_i3c_disable) + { + case LSM6DSV16B_I2C_I3C_ENABLE: + *val = LSM6DSV16B_I2C_I3C_ENABLE; + break; + + case LSM6DSV16B_I2C_I3C_DISABLE: + *val = LSM6DSV16B_I2C_I3C_DISABLE; + break; + + default: + *val = LSM6DSV16B_I2C_I3C_ENABLE; + break; + } + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val SPI_4_WIRE, SPI_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16b_spi_mode_t val) +{ + lsm6dsv16b_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.sim = (uint8_t)val & 0x01U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val SPI_4_WIRE, SPI_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16b_spi_mode_t *val) +{ + lsm6dsv16b_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + switch (if_cfg.sim) + { + case LSM6DSV16B_SPI_4_WIRE: + *val = LSM6DSV16B_SPI_4_WIRE; + break; + + case LSM6DSV16B_SPI_3_WIRE: + *val = LSM6DSV16B_SPI_3_WIRE; + break; + + default: + *val = LSM6DSV16B_SPI_4_WIRE; + break; + } + return ret; +} + +/** + * @brief Enables pull-up on SDA pin.[set] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDA pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_ui_sda_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16b_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.sda_pu_en = (uint8_t)val & 0x01U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Enables pull-up on SDA pin.[get] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDA pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16b_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + *val = if_cfg.sda_pu_en; + + return ret; +} + +/** + * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[set] + * + * @param ctx read / write interface definitions + * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_i3c_ibi_time_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_i3c_ibi_time_t val) +{ + lsm6dsv16b_ctrl5_t ctrl5; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret == 0) + { + ctrl5.bus_act_sel = (uint8_t)val & 0x03U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL5, (uint8_t *)&ctrl5, 1); + } + + return ret; +} + +/** + * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[get] + * + * @param ctx read / write interface definitions + * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_i3c_ibi_time_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_i3c_ibi_time_t *val) +{ + lsm6dsv16b_ctrl5_t ctrl5; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL5, (uint8_t *)&ctrl5, 1); + switch (ctrl5.bus_act_sel) + { + case LSM6DSV16B_IBI_2us: + *val = LSM6DSV16B_IBI_2us; + break; + + case LSM6DSV16B_IBI_50us: + *val = LSM6DSV16B_IBI_50us; + break; + + case LSM6DSV16B_IBI_1ms: + *val = LSM6DSV16B_IBI_1ms; + break; + + case LSM6DSV16B_IBI_25ms: + *val = LSM6DSV16B_IBI_25ms; + break; + + default: + *val = LSM6DSV16B_IBI_2us; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Interrupt pins + * @brief This section groups all the functions that manage interrupt pins + * @{ + * + */ + +/** + * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[set] + * + * @param ctx read / write interface definitions + * @param val PUSH_PULL, OPEN_DRAIN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_int_pin_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_int_pin_mode_t val) +{ + lsm6dsv16b_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.pp_od = (uint8_t)val & 0x01U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[get] + * + * @param ctx read / write interface definitions + * @param val PUSH_PULL, OPEN_DRAIN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_int_pin_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_int_pin_mode_t *val) +{ + lsm6dsv16b_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + switch (if_cfg.pp_od) + { + case LSM6DSV16B_PUSH_PULL: + *val = LSM6DSV16B_PUSH_PULL; + break; + + case LSM6DSV16B_OPEN_DRAIN: + *val = LSM6DSV16B_OPEN_DRAIN; + break; + + default: + *val = LSM6DSV16B_PUSH_PULL; + break; + } + return ret; +} + +/** + * @brief Interrupt activation level.[set] + * + * @param ctx read / write interface definitions + * @param val ACTIVE_HIGH, ACTIVE_LOW, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_pin_polarity_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_pin_polarity_t val) +{ + lsm6dsv16b_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.h_lactive = (uint8_t)val & 0x01U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Interrupt activation level.[get] + * + * @param ctx read / write interface definitions + * @param val ACTIVE_HIGH, ACTIVE_LOW, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_pin_polarity_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_pin_polarity_t *val) +{ + lsm6dsv16b_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + switch (if_cfg.h_lactive) + { + case LSM6DSV16B_ACTIVE_HIGH: + *val = LSM6DSV16B_ACTIVE_HIGH; + break; + + case LSM6DSV16B_ACTIVE_LOW: + *val = LSM6DSV16B_ACTIVE_LOW; + break; + + default: + *val = LSM6DSV16B_ACTIVE_HIGH; + break; + } + return ret; +} + +/** + * @brief It routes interrupt signals on INT 1 pin.[set] + * + * @param ctx read / write interface definitions + * @param val It routes interrupt signals on INT 1 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_pin_int1_route_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_pin_int_route_t val) +{ + lsm6dsv16b_functions_enable_t functions_enable; + lsm6dsv16b_pin_int_route_t pin_int2_route; + lsm6dsv16b_inactivity_dur_t inactivity_dur; + lsm6dsv16b_emb_func_int1_t emb_func_int1; + lsm6dsv16b_pedo_cmd_reg_t pedo_cmd_reg; + lsm6dsv16b_int2_ctrl_t int2_ctrl; + lsm6dsv16b_int1_ctrl_t int1_ctrl; + lsm6dsv16b_fsm_int1_t fsm_int1; + lsm6dsv16b_md1_cfg_t md1_cfg; + lsm6dsv16b_md2_cfg_t md2_cfg; + lsm6dsv16b_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + } + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FSM_INT1, (uint8_t *)&fsm_int1, 1); + } + + if (ret == 0) + { + emb_func_int1.int1_step_detector = val.step_detector; + emb_func_int1.int1_tilt = val.tilt; + emb_func_int1.int1_sig_mot = val.sig_mot; + emb_func_int1.int1_fsm_lc = val.fsm_lc; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + } + if (ret == 0) + { + fsm_int1.int1_fsm1 = val.fsm1; + fsm_int1.int1_fsm2 = val.fsm2; + fsm_int1.int1_fsm3 = val.fsm3; + fsm_int1.int1_fsm4 = val.fsm4; + fsm_int1.int1_fsm5 = val.fsm5; + fsm_int1.int1_fsm6 = val.fsm6; + fsm_int1.int1_fsm7 = val.fsm7; + fsm_int1.int1_fsm8 = val.fsm8; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FSM_INT1, (uint8_t *)&fsm_int1, 1); + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL4, (uint8_t *)&ctrl4, 1); + } + if (ret == 0) + { + if ((val.emb_func_stand_by | val.timestamp) != PROPERTY_DISABLE) + { + ctrl4.int2_on_int1 = PROPERTY_ENABLE; + } + else + { + ctrl4.int2_on_int1 = PROPERTY_DISABLE; + } + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL4, (uint8_t *)&ctrl4, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + } + + if (ret == 0) + { + int2_ctrl.int2_emb_func_endop = val.emb_func_stand_by; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + } + + + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + if (ret == 0) + { + md2_cfg.int2_timestamp = val.timestamp; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + if (ret == 0) + { + inactivity_dur.sleep_status_on_int = val.sleep_status; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + } + + if (ret == 0) + { + int1_ctrl.int1_drdy_xl = val.drdy_xl; + int1_ctrl.int1_drdy_g = val.drdy_gy; + int1_ctrl.int1_fifo_th = val.fifo_th; + int1_ctrl.int1_fifo_ovr = val.fifo_ovr; + int1_ctrl.int1_fifo_full = val.fifo_full; + int1_ctrl.int1_cnt_bdr = val.fifo_bdr; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_MD1_CFG, (uint8_t *)&md1_cfg, 1); + } + + if (ret == 0) + { + if ((emb_func_int1.int1_fsm_lc + | emb_func_int1.int1_sig_mot + | emb_func_int1.int1_step_detector + | emb_func_int1.int1_tilt + | fsm_int1.int1_fsm1 + | fsm_int1.int1_fsm2 + | fsm_int1.int1_fsm3 + | fsm_int1.int1_fsm4 + | fsm_int1.int1_fsm5 + | fsm_int1.int1_fsm6 + | fsm_int1.int1_fsm7 + | fsm_int1.int1_fsm8) != PROPERTY_DISABLE) + { + md1_cfg.int1_emb_func = PROPERTY_ENABLE; + } + else + { + md1_cfg.int1_emb_func = PROPERTY_DISABLE; + } + md1_cfg.int1_6d = val.six_d; + md1_cfg.int1_double_tap = val.double_tap; + md1_cfg.int1_ff = val.free_fall; + md1_cfg.int1_wu = val.wake_up; + md1_cfg.int1_single_tap = val.single_tap; + if ((val.sleep_status | val.sleep_change) != PROPERTY_DISABLE) + { + md1_cfg.int1_sleep_change = PROPERTY_ENABLE; + } + else + { + md1_cfg.int1_sleep_change = PROPERTY_DISABLE; + } + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_MD1_CFG, (uint8_t *)&md1_cfg, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + if (ret == 0) + { + pedo_cmd_reg.carry_count_en = val.step_count_overflow; + ret = lsm6dsv16b_ln_pg_write(ctx, LSM6DSV16B_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + + if (ret == 0) + { + ret = lsm6dsv16b_pin_int2_route_get(ctx, &pin_int2_route); + } + + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + if (ret == 0) + { + if ((pin_int2_route.six_d + | pin_int2_route.double_tap + | pin_int2_route.free_fall + | pin_int2_route.wake_up + | pin_int2_route.single_tap + | pin_int2_route.sleep_status + | pin_int2_route.sleep_change + | val.six_d + | val.double_tap + | val.free_fall + | val.wake_up + | val.single_tap + | val.sleep_status + | val.sleep_change) != PROPERTY_DISABLE) + { + functions_enable.interrupts_enable = PROPERTY_ENABLE; + } + + else + { + functions_enable.interrupts_enable = PROPERTY_DISABLE; + } + + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + return ret; +} + +/** + * @brief It routes interrupt signals on INT 1 pin.[get] + * + * @param ctx read / write interface definitions + * @param val It routes interrupt signals on INT 1 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_pin_int1_route_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_pin_int_route_t *val) +{ + lsm6dsv16b_inactivity_dur_t inactivity_dur; + lsm6dsv16b_emb_func_int1_t emb_func_int1; + lsm6dsv16b_pedo_cmd_reg_t pedo_cmd_reg; + lsm6dsv16b_int1_ctrl_t int1_ctrl; + lsm6dsv16b_int2_ctrl_t int2_ctrl; + lsm6dsv16b_fsm_int1_t fsm_int1; + lsm6dsv16b_md1_cfg_t md1_cfg; + lsm6dsv16b_md2_cfg_t md2_cfg; + lsm6dsv16b_ctrl4_t ctrl4; + int32_t ret; + + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL4, (uint8_t *)&ctrl4, 1); + if (ctrl4.int2_on_int1 == PROPERTY_ENABLE) + { + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop; + } + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_MD2_CFG, (uint8_t *)&md2_cfg, 1); + val->timestamp = md2_cfg.int2_timestamp; + } + } + + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + val->sleep_status = inactivity_dur.sleep_status_on_int; + } + + + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + val->drdy_xl = int1_ctrl.int1_drdy_xl; + val->drdy_gy = int1_ctrl.int1_drdy_g; + val->fifo_th = int1_ctrl.int1_fifo_th; + val->fifo_ovr = int1_ctrl.int1_fifo_ovr; + val->fifo_full = int1_ctrl.int1_fifo_full; + val->fifo_bdr = int1_ctrl.int1_cnt_bdr; + } + + + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_MD1_CFG, (uint8_t *)&md1_cfg, 1); + val->six_d = md1_cfg.int1_6d; + val->double_tap = md1_cfg.int1_double_tap; + val->free_fall = md1_cfg.int1_ff; + val->wake_up = md1_cfg.int1_wu; + val->single_tap = md1_cfg.int1_single_tap; + val->sleep_change = md1_cfg.int1_sleep_change; + } + + if (ret == 0) + { + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + val->step_detector = emb_func_int1.int1_step_detector; + val->tilt = emb_func_int1.int1_tilt; + val->sig_mot = emb_func_int1.int1_sig_mot; + val->fsm_lc = emb_func_int1.int1_fsm_lc; + } + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FSM_INT1, (uint8_t *)&fsm_int1, 1); + val->fsm1 = fsm_int1.int1_fsm1; + val->fsm2 = fsm_int1.int1_fsm2; + val->fsm3 = fsm_int1.int1_fsm3; + val->fsm4 = fsm_int1.int1_fsm4; + val->fsm5 = fsm_int1.int1_fsm5; + val->fsm6 = fsm_int1.int1_fsm6; + val->fsm7 = fsm_int1.int1_fsm7; + val->fsm8 = fsm_int1.int1_fsm8; + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + val->step_count_overflow = pedo_cmd_reg.carry_count_en; + } + + return ret; +} + + +/** + * @brief It routes interrupt signals on INT 2 pin.[set] + * + * @param ctx read / write interface definitions + * @param val It routes interrupt signals on INT 2 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_pin_int2_route_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_pin_int_route_t val) +{ + lsm6dsv16b_functions_enable_t functions_enable; + lsm6dsv16b_pin_int_route_t pin_int1_route; + lsm6dsv16b_inactivity_dur_t inactivity_dur; + lsm6dsv16b_emb_func_int2_t emb_func_int2; + lsm6dsv16b_pedo_cmd_reg_t pedo_cmd_reg; + lsm6dsv16b_int2_ctrl_t int2_ctrl; + lsm6dsv16b_fsm_int2_t fsm_int2; + lsm6dsv16b_md2_cfg_t md2_cfg; + lsm6dsv16b_ctrl4_t ctrl4; + int32_t ret; + + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + } + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FSM_INT2, (uint8_t *)&fsm_int2, 1); + } + + if (ret == 0) + { + emb_func_int2.int2_step_detector = val.step_detector; + emb_func_int2.int2_tilt = val.tilt; + emb_func_int2.int2_sig_mot = val.sig_mot; + emb_func_int2.int2_fsm_lc = val.fsm_lc; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + } + if (ret == 0) + { + fsm_int2.int2_fsm1 = val.fsm1; + fsm_int2.int2_fsm2 = val.fsm2; + fsm_int2.int2_fsm3 = val.fsm3; + fsm_int2.int2_fsm4 = val.fsm4; + fsm_int2.int2_fsm5 = val.fsm5; + fsm_int2.int2_fsm6 = val.fsm6; + fsm_int2.int2_fsm7 = val.fsm7; + fsm_int2.int2_fsm8 = val.fsm8; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FSM_INT2, (uint8_t *)&fsm_int2, 1); + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL4, (uint8_t *)&ctrl4, 1); + } + if (ret == 0) + { + if ((val.emb_func_stand_by | val.timestamp) != PROPERTY_DISABLE) + { + ctrl4.int2_on_int1 = PROPERTY_DISABLE; + } + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL4, (uint8_t *)&ctrl4, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + if (ret == 0) + { + inactivity_dur.sleep_status_on_int = val.sleep_status; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + } + + if (ret == 0) + { + int2_ctrl.int2_drdy_xl = val.drdy_xl; + int2_ctrl.int2_drdy_g = val.drdy_gy; + int2_ctrl.int2_fifo_th = val.fifo_th; + int2_ctrl.int2_fifo_ovr = val.fifo_ovr; + int2_ctrl.int2_fifo_full = val.fifo_full; + int2_ctrl.int2_cnt_bdr = val.fifo_bdr; + int2_ctrl.int2_emb_func_endop = val.emb_func_stand_by; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + if (ret == 0) + { + if ((emb_func_int2.int2_fsm_lc + | emb_func_int2.int2_sig_mot + | emb_func_int2.int2_step_detector + | emb_func_int2.int2_tilt + | fsm_int2.int2_fsm1 + | fsm_int2.int2_fsm2 + | fsm_int2.int2_fsm3 + | fsm_int2.int2_fsm4 + | fsm_int2.int2_fsm5 + | fsm_int2.int2_fsm6 + | fsm_int2.int2_fsm7 + | fsm_int2.int2_fsm8) != PROPERTY_DISABLE) + { + md2_cfg.int2_emb_func = PROPERTY_ENABLE; + } + else + { + md2_cfg.int2_emb_func = PROPERTY_DISABLE; + } + md2_cfg.int2_6d = val.six_d; + md2_cfg.int2_double_tap = val.double_tap; + md2_cfg.int2_ff = val.free_fall; + md2_cfg.int2_wu = val.wake_up; + md2_cfg.int2_single_tap = val.single_tap; + md2_cfg.int2_timestamp = val.timestamp; + if ((val.sleep_status | val.sleep_change) != PROPERTY_DISABLE) + { + md2_cfg.int2_sleep_change = PROPERTY_ENABLE; + } + else + { + md2_cfg.int2_sleep_change = PROPERTY_DISABLE; + } + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + if (ret == 0) + { + pedo_cmd_reg.carry_count_en = val.step_count_overflow; + ret = lsm6dsv16b_ln_pg_write(ctx, LSM6DSV16B_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + + if (ret == 0) + { + ret = lsm6dsv16b_pin_int1_route_get(ctx, &pin_int1_route); + } + + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + if (ret == 0) + { + if ((pin_int1_route.six_d + | pin_int1_route.double_tap + | pin_int1_route.free_fall + | pin_int1_route.wake_up + | pin_int1_route.single_tap + | pin_int1_route.sleep_status + | pin_int1_route.sleep_change + | val.six_d + | val.double_tap + | val.free_fall + | val.wake_up + | val.single_tap + | val.sleep_status + | val.sleep_change) != PROPERTY_DISABLE) + { + functions_enable.interrupts_enable = PROPERTY_ENABLE; + } + + else + { + functions_enable.interrupts_enable = PROPERTY_DISABLE; + } + + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + return ret; +} + +/** + * @brief It routes interrupt signals on INT 2 pin.[get] + * + * @param ctx read / write interface definitions + * @param val It routes interrupt signals on INT 2 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_pin_int2_route_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_pin_int_route_t *val) +{ + lsm6dsv16b_inactivity_dur_t inactivity_dur; + lsm6dsv16b_emb_func_int2_t emb_func_int2; + lsm6dsv16b_pedo_cmd_reg_t pedo_cmd_reg; + lsm6dsv16b_int2_ctrl_t int2_ctrl; + lsm6dsv16b_fsm_int2_t fsm_int2; + lsm6dsv16b_md2_cfg_t md2_cfg; + lsm6dsv16b_ctrl4_t ctrl4; + int32_t ret; + + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL4, (uint8_t *)&ctrl4, 1); + if (ctrl4.int2_on_int1 == PROPERTY_DISABLE) + { + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop; + } + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_MD2_CFG, (uint8_t *)&md2_cfg, 1); + val->timestamp = md2_cfg.int2_timestamp; + } + } + + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + val->sleep_status = inactivity_dur.sleep_status_on_int; + } + + + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + val->drdy_xl = int2_ctrl.int2_drdy_xl; + val->drdy_gy = int2_ctrl.int2_drdy_g; + val->fifo_th = int2_ctrl.int2_fifo_th; + val->fifo_ovr = int2_ctrl.int2_fifo_ovr; + val->fifo_full = int2_ctrl.int2_fifo_full; + val->fifo_bdr = int2_ctrl.int2_cnt_bdr; + } + + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_MD2_CFG, (uint8_t *)&md2_cfg, 1); + val->six_d = md2_cfg.int2_6d; + val->double_tap = md2_cfg.int2_double_tap; + val->free_fall = md2_cfg.int2_ff; + val->wake_up = md2_cfg.int2_wu; + val->single_tap = md2_cfg.int2_single_tap; + val->sleep_change = md2_cfg.int2_sleep_change; + } + + if (ret == 0) + { + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + val->step_detector = emb_func_int2.int2_step_detector; + val->tilt = emb_func_int2.int2_tilt; + val->sig_mot = emb_func_int2.int2_sig_mot; + val->fsm_lc = emb_func_int2.int2_fsm_lc; + } + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FSM_INT2, (uint8_t *)&fsm_int2, 1); + val->fsm1 = fsm_int2.int2_fsm1; + val->fsm2 = fsm_int2.int2_fsm2; + val->fsm3 = fsm_int2.int2_fsm3; + val->fsm4 = fsm_int2.int2_fsm4; + val->fsm5 = fsm_int2.int2_fsm5; + val->fsm6 = fsm_int2.int2_fsm6; + val->fsm7 = fsm_int2.int2_fsm7; + val->fsm8 = fsm_int2.int2_fsm8; + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + val->step_count_overflow = pedo_cmd_reg.carry_count_en; + } + + return ret; +} + +/** + * @brief Enables INT pin when I3C is enabled.[set] + * + * @param ctx read / write interface definitions + * @param val Enables INT pin when I3C is enabled. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_pin_int_en_when_i2c_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16b_ctrl5_t ctrl5; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret == 0) + { + ctrl5.int_en_i3c = val; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL5, (uint8_t *)&ctrl5, 1); + } + + return ret; +} + +/** + * @brief Enables INT pin when I3C is enabled.[get] + * + * @param ctx read / write interface definitions + * @param val Enables INT pin when I3C is enabled. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_pin_int_en_when_i2c_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16b_ctrl5_t ctrl5; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL5, (uint8_t *)&ctrl5, 1); + *val = ctrl5.int_en_i3c; + + return ret; +} + +/** + * @brief Interrupt notification mode.[set] + * + * @param ctx read / write interface definitions + * @param val ALL_INT_PULSED, BASE_LATCHED_EMB_PULSED, BASE_PULSED_EMB_LATCHED, ALL_INT_LATCHED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_int_notification_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_int_notification_t val) +{ + lsm6dsv16b_tap_cfg0_t tap_cfg0; + lsm6dsv16b_page_rw_t page_rw; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret == 0) + { + tap_cfg0.lir = (uint8_t)val & 0x01U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + if (ret == 0) + { + page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Interrupt notification mode.[get] + * + * @param ctx read / write interface definitions + * @param val ALL_INT_PULSED, BASE_LATCHED_EMB_PULSED, BASE_PULSED_EMB_LATCHED, ALL_INT_LATCHED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_int_notification_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_int_notification_t *val) +{ + lsm6dsv16b_tap_cfg0_t tap_cfg0; + lsm6dsv16b_page_rw_t page_rw; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret == 0) + { + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir) + { + case LSM6DSV16B_ALL_INT_PULSED: + *val = LSM6DSV16B_ALL_INT_PULSED; + break; + + case LSM6DSV16B_BASE_LATCHED_EMB_PULSED: + *val = LSM6DSV16B_BASE_LATCHED_EMB_PULSED; + break; + + case LSM6DSV16B_BASE_PULSED_EMB_LATCHED: + *val = LSM6DSV16B_BASE_PULSED_EMB_LATCHED; + break; + + case LSM6DSV16B_ALL_INT_LATCHED: + *val = LSM6DSV16B_ALL_INT_LATCHED; + break; + + default: + *val = LSM6DSV16B_ALL_INT_PULSED; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Wake Up event and Activity / Inactivity detection + * @brief This section groups all the functions that manage the Wake Up + * event generation. + * @{ + * + */ + +/** + * @brief Enable activity/inactivity (sleep) function.[set] + * + * @param ctx read / write interface definitions + * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_act_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16b_act_mode_t val) +{ + lsm6dsv16b_functions_enable_t functions_enable; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret == 0) + { + functions_enable.inact_en = (uint8_t)val & 0x03U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + return ret; +} + +/** + * @brief Enable activity/inactivity (sleep) function.[get] + * + * @param ctx read / write interface definitions + * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_act_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16b_act_mode_t *val) +{ + lsm6dsv16b_functions_enable_t functions_enable; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + switch (functions_enable.inact_en) + { + case LSM6DSV16B_XL_AND_GY_NOT_AFFECTED: + *val = LSM6DSV16B_XL_AND_GY_NOT_AFFECTED; + break; + + case LSM6DSV16B_XL_LOW_POWER_GY_NOT_AFFECTED: + *val = LSM6DSV16B_XL_LOW_POWER_GY_NOT_AFFECTED; + break; + + case LSM6DSV16B_XL_LOW_POWER_GY_SLEEP: + *val = LSM6DSV16B_XL_LOW_POWER_GY_SLEEP; + break; + + case LSM6DSV16B_XL_LOW_POWER_GY_POWER_DOWN: + *val = LSM6DSV16B_XL_LOW_POWER_GY_POWER_DOWN; + break; + + default: + *val = LSM6DSV16B_XL_AND_GY_NOT_AFFECTED; + break; + } + return ret; +} + +/** + * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[set] + * + * @param ctx read / write interface definitions + * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_act_from_sleep_to_act_dur_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_act_from_sleep_to_act_dur_t val) +{ + lsm6dsv16b_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret == 0) + { + inactivity_dur.inact_dur = (uint8_t)val & 0x3U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + return ret; +} + +/** + * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[get] + * + * @param ctx read / write interface definitions + * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_act_from_sleep_to_act_dur_t *val) +{ + lsm6dsv16b_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + switch (inactivity_dur.inact_dur) + { + case LSM6DSV16B_SLEEP_TO_ACT_AT_1ST_SAMPLE: + *val = LSM6DSV16B_SLEEP_TO_ACT_AT_1ST_SAMPLE; + break; + + case LSM6DSV16B_SLEEP_TO_ACT_AT_2ND_SAMPLE: + *val = LSM6DSV16B_SLEEP_TO_ACT_AT_2ND_SAMPLE; + break; + + case LSM6DSV16B_SLEEP_TO_ACT_AT_3RD_SAMPLE: + *val = LSM6DSV16B_SLEEP_TO_ACT_AT_3RD_SAMPLE; + break; + + case LSM6DSV16B_SLEEP_TO_ACT_AT_4th_SAMPLE: + *val = LSM6DSV16B_SLEEP_TO_ACT_AT_4th_SAMPLE; + break; + + default: + *val = LSM6DSV16B_SLEEP_TO_ACT_AT_1ST_SAMPLE; + break; + } + return ret; +} + +/** + * @brief Selects the accelerometer data rate during Inactivity.[set] + * + * @param ctx read / write interface definitions + * @param val 1Hz875, 15Hz, 30Hz, 60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_act_sleep_xl_odr_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_act_sleep_xl_odr_t val) +{ + lsm6dsv16b_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret == 0) + { + inactivity_dur.xl_inact_odr = (uint8_t)val & 0x03U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + return ret; +} + +/** + * @brief Selects the accelerometer data rate during Inactivity.[get] + * + * @param ctx read / write interface definitions + * @param val 1Hz875, 15Hz, 30Hz, 60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_act_sleep_xl_odr_t *val) +{ + lsm6dsv16b_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + switch (inactivity_dur.xl_inact_odr) + { + case LSM6DSV16B_1Hz875: + *val = LSM6DSV16B_1Hz875; + break; + + case LSM6DSV16B_15Hz: + *val = LSM6DSV16B_15Hz; + break; + + case LSM6DSV16B_30Hz: + *val = LSM6DSV16B_30Hz; + break; + + case LSM6DSV16B_60Hz: + *val = LSM6DSV16B_60Hz; + break; + + default: + *val = LSM6DSV16B_1Hz875; + break; + } + return ret; +} + +/** + * @brief Wakeup and activity/inactivity threshold.[set] + * + * @param ctx read / write interface definitions + * @param val Wakeup and activity/inactivity threshold. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_act_thresholds_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_act_thresholds_t val) +{ + lsm6dsv16b_inactivity_ths_t inactivity_ths; + lsm6dsv16b_inactivity_dur_t inactivity_dur; + lsm6dsv16b_wake_up_ths_t wake_up_ths; + int32_t ret; + float_t tmp; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + if ((val.wk_ths_mg < (uint32_t)(7.8125f * 63.0f)) + && (val.inact_ths_mg < (uint32_t)(7.8125f * 63.0f))) + { + inactivity_dur.wu_inact_ths_w = 0; + + tmp = (float_t)val.inact_ths_mg / 7.8125f; + inactivity_ths.inact_ths = (uint8_t)tmp; + + tmp = (float_t)val.wk_ths_mg / 7.8125f; + wake_up_ths.wk_ths = (uint8_t)tmp; + } + else if ((val.wk_ths_mg < (uint32_t)(15.625f * 63.0f)) + && (val.inact_ths_mg < (uint32_t)(15.625f * 63.0f))) + { + inactivity_dur.wu_inact_ths_w = 1; + + tmp = (float_t)val.inact_ths_mg / 15.625f; + inactivity_ths.inact_ths = (uint8_t)tmp; + + tmp = (float_t)val.wk_ths_mg / 15.625f; + wake_up_ths.wk_ths = (uint8_t)tmp; + } + else if ((val.wk_ths_mg < (uint32_t)(31.25f * 63.0f)) + && (val.inact_ths_mg < (uint32_t)(31.25f * 63.0f))) + { + inactivity_dur.wu_inact_ths_w = 2; + + tmp = (float_t)val.inact_ths_mg / 31.25f; + inactivity_ths.inact_ths = (uint8_t)tmp; + + tmp = (float_t)val.wk_ths_mg / 31.25f; + wake_up_ths.wk_ths = (uint8_t)tmp; + } + else if ((val.wk_ths_mg < (uint32_t)(62.5f * 63.0f)) + && (val.inact_ths_mg < (uint32_t)(62.5f * 63.0f))) + { + inactivity_dur.wu_inact_ths_w = 3; + + tmp = (float_t)val.inact_ths_mg / 62.5f; + inactivity_ths.inact_ths = (uint8_t)tmp; + + tmp = (float_t)val.wk_ths_mg / 62.5f; + wake_up_ths.wk_ths = (uint8_t)tmp; + } + else if ((val.wk_ths_mg < (uint32_t)(125.0f * 63.0f)) + && (val.inact_ths_mg < (uint32_t)(125.0f * 63.0f))) + { + inactivity_dur.wu_inact_ths_w = 4; + + tmp = (float_t)val.inact_ths_mg / 125.0f; + inactivity_ths.inact_ths = (uint8_t)tmp; + + tmp = (float_t)val.wk_ths_mg / 125.0f; + wake_up_ths.wk_ths = (uint8_t)tmp; + } + else if ((val.wk_ths_mg < (uint32_t)(250.0f * 63.0f)) + && (val.inact_ths_mg < (uint32_t)(250.0f * 63.0f))) + { + inactivity_dur.wu_inact_ths_w = 5; + + tmp = (float_t)val.inact_ths_mg / 250.0f; + inactivity_ths.inact_ths = (uint8_t)tmp; + + tmp = (float_t)val.wk_ths_mg / 250.0f; + wake_up_ths.wk_ths = (uint8_t)tmp; + } + else // out of limit + { + inactivity_dur.wu_inact_ths_w = 5; + inactivity_ths.inact_ths = 0x3FU; + wake_up_ths.wk_ths = 0x3FU; + } + + if (ret == 0) + { + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + if (ret == 0) + { + + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + } + if (ret == 0) + { + + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + return ret; +} + +/** + * @brief Wakeup and activity/inactivity threshold.[get] + * + * @param ctx read / write interface definitions + * @param val Wakeup and activity/inactivity threshold. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_act_thresholds_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_act_thresholds_t *val) +{ + lsm6dsv16b_inactivity_dur_t inactivity_dur; + lsm6dsv16b_inactivity_ths_t inactivity_ths; + lsm6dsv16b_wake_up_ths_t wake_up_ths; + int32_t ret; + float_t tmp; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + } + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + switch (inactivity_dur.wu_inact_ths_w) + { + case 0: + tmp = (float_t)wake_up_ths.wk_ths * 7.8125f; + val->wk_ths_mg = (uint32_t)tmp; + + tmp = (float_t)inactivity_ths.inact_ths * 7.8125f; + val->inact_ths_mg = (uint32_t)tmp; + break; + + case 1: + tmp = (float_t)wake_up_ths.wk_ths * 15.625f; + val->wk_ths_mg = (uint32_t)tmp; + + tmp = (float_t)inactivity_ths.inact_ths * 15.625f; + val->inact_ths_mg = (uint32_t)tmp; + break; + + case 2: + tmp = (float_t)wake_up_ths.wk_ths * 31.25f; + val->wk_ths_mg = (uint32_t)tmp; + + tmp = (float_t)inactivity_ths.inact_ths * 31.25f; + val->inact_ths_mg = (uint32_t)tmp; + break; + + case 3: + tmp = (float_t)wake_up_ths.wk_ths * 62.5f; + val->wk_ths_mg = (uint32_t)tmp; + + tmp = (float_t)inactivity_ths.inact_ths * 62.5f; + val->inact_ths_mg = (uint32_t)tmp; + break; + + case 4: + tmp = (float_t)wake_up_ths.wk_ths * 125.0f; + val->wk_ths_mg = (uint32_t)tmp; + + tmp = (float_t)inactivity_ths.inact_ths * 125.0f; + val->inact_ths_mg = (uint32_t)tmp; + break; + + default: + tmp = (float_t)wake_up_ths.wk_ths * 250.0f; + val->wk_ths_mg = (uint32_t)tmp; + + tmp = (float_t)inactivity_ths.inact_ths * 250.0f; + val->inact_ths_mg = (uint32_t)tmp; + break; + } + + return ret; +} + +/** + * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [set] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_act_wkup_time_windows_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_act_wkup_time_windows_t val) +{ + lsm6dsv16b_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + wake_up_dur.wake_dur = val.shock; + wake_up_dur.sleep_dur = val.quiet; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + } + + return ret; +} + +/** + * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [get] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_act_wkup_time_windows_t *val) +{ + lsm6dsv16b_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + val->shock = wake_up_dur.wake_dur; + val->quiet = wake_up_dur.sleep_dur; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Tap Generator + * @brief This section groups all the functions that manage the + * tap and double tap event generation. + * @{ + * + */ + +/** + * @brief Enable axis for Tap - Double Tap detection.[set] + * + * @param ctx read / write interface definitions + * @param val Enable axis for Tap - Double Tap detection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tap_detection_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_tap_detection_t val) +{ + lsm6dsv16b_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret == 0) + { + tap_cfg0.tap_x_en = val.tap_x_en; + tap_cfg0.tap_y_en = val.tap_y_en; + tap_cfg0.tap_z_en = val.tap_z_en; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + return ret; +} + +/** + * @brief Enable axis for Tap - Double Tap detection.[get] + * + * @param ctx read / write interface definitions + * @param val Enable axis for Tap - Double Tap detection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tap_detection_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_tap_detection_t *val) +{ + lsm6dsv16b_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + val->tap_x_en = tap_cfg0.tap_x_en; + val->tap_y_en = tap_cfg0.tap_y_en; + val->tap_z_en = tap_cfg0.tap_z_en; + + return ret; +} + +/** + * @brief axis Tap - Double Tap recognition thresholds.[set] + * + * @param ctx read / write interface definitions + * @param val axis Tap - Double Tap recognition thresholds. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tap_thresholds_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_tap_thresholds_t val) +{ + lsm6dsv16b_tap_ths_6d_t tap_ths_6d; + lsm6dsv16b_tap_cfg2_t tap_cfg2; + lsm6dsv16b_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + } + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + + tap_cfg1.tap_ths_z = val.z; + tap_cfg2.tap_ths_y = val.y; + tap_ths_6d.tap_ths_x = val.x; + + if (ret == 0) + { + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + if (ret == 0) + { + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + } + if (ret == 0) + { + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + } + + return ret; +} + +/** + * @brief axis Tap - Double Tap recognition thresholds.[get] + * + * @param ctx read / write interface definitions + * @param val axis Tap - Double Tap recognition thresholds. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tap_thresholds_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_tap_thresholds_t *val) +{ + lsm6dsv16b_tap_ths_6d_t tap_ths_6d; + lsm6dsv16b_tap_cfg2_t tap_cfg2; + lsm6dsv16b_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + } + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + + val->z = tap_cfg1.tap_ths_z; + val->y = tap_cfg2.tap_ths_y; + val->x = tap_ths_6d.tap_ths_x; + + return ret; +} + +/** + * @brief Selection of axis priority for TAP detection.[set] + * + * @param ctx read / write interface definitions + * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY , + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tap_axis_priority_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_tap_axis_priority_t val) +{ + lsm6dsv16b_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret == 0) + { + tap_cfg1.tap_priority = (uint8_t)val & 0x07U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + } + + return ret; +} + +/** + * @brief Selection of axis priority for TAP detection.[get] + * + * @param ctx read / write interface definitions + * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY , + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tap_axis_priority_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_tap_axis_priority_t *val) +{ + lsm6dsv16b_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + switch (tap_cfg1.tap_priority) + { + case LSM6DSV16B_XYZ : + *val = LSM6DSV16B_XYZ ; + break; + + case LSM6DSV16B_YXZ : + *val = LSM6DSV16B_YXZ ; + break; + + case LSM6DSV16B_XZY: + *val = LSM6DSV16B_XZY; + break; + + case LSM6DSV16B_ZYX : + *val = LSM6DSV16B_ZYX ; + break; + + case LSM6DSV16B_YZX : + *val = LSM6DSV16B_YZX ; + break; + + case LSM6DSV16B_ZXY : + *val = LSM6DSV16B_ZXY ; + break; + + default: + *val = LSM6DSV16B_XYZ ; + break; + } + return ret; +} + + +/** + * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[set] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tap_time_windows_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_tap_time_windows_t val) +{ + lsm6dsv16b_tap_dur_t tap_dur; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_DUR, (uint8_t *)&tap_dur, 1); + if (ret == 0) + { + tap_dur.shock = val.shock; + tap_dur.quiet = val.quiet; + tap_dur.dur = val.tap_gap; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TAP_DUR, (uint8_t *)&tap_dur, 1); + } + + return ret; +} + +/** + * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[get] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tap_time_windows_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_tap_time_windows_t *val) +{ + lsm6dsv16b_tap_dur_t tap_dur; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_DUR, (uint8_t *)&tap_dur, 1); + val->shock = tap_dur.shock; + val->quiet = tap_dur.quiet; + val->tap_gap = tap_dur.dur; + + return ret; +} + +/** + * @brief Single/double-tap event enable.[set] + * + * @param ctx read / write interface definitions + * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16b_tap_mode_t val) +{ + lsm6dsv16b_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret == 0) + { + wake_up_ths.single_double_tap = (uint8_t)val & 0x01U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + return ret; +} + +/** + * @brief Single/double-tap event enable.[get] + * + * @param ctx read / write interface definitions + * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16b_tap_mode_t *val) +{ + lsm6dsv16b_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + switch (wake_up_ths.single_double_tap) + { + case LSM6DSV16B_ONLY_SINGLE: + *val = LSM6DSV16B_ONLY_SINGLE; + break; + + case LSM6DSV16B_BOTH_SINGLE_DOUBLE: + *val = LSM6DSV16B_BOTH_SINGLE_DOUBLE; + break; + + default: + *val = LSM6DSV16B_ONLY_SINGLE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Six position detection (6D) + * @brief This section groups all the functions concerning six position + * detection (6D). + * @{ + * + */ + +/** + * @brief Threshold for 4D/6D function.[set] + * + * @param ctx read / write interface definitions + * @param val DEG_80, DEG_70, DEG_60, DEG_50, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_6d_threshold_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_6d_threshold_t val) +{ + lsm6dsv16b_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret == 0) + { + tap_ths_6d.sixd_ths = (uint8_t)val & 0x03U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + + return ret; +} + +/** + * @brief Threshold for 4D/6D function.[get] + * + * @param ctx read / write interface definitions + * @param val DEG_80, DEG_70, DEG_60, DEG_50, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_6d_threshold_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_6d_threshold_t *val) +{ + lsm6dsv16b_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + switch (tap_ths_6d.sixd_ths) + { + case LSM6DSV16B_DEG_80: + *val = LSM6DSV16B_DEG_80; + break; + + case LSM6DSV16B_DEG_70: + *val = LSM6DSV16B_DEG_70; + break; + + case LSM6DSV16B_DEG_60: + *val = LSM6DSV16B_DEG_60; + break; + + case LSM6DSV16B_DEG_50: + *val = LSM6DSV16B_DEG_50; + break; + + default: + *val = LSM6DSV16B_DEG_80; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Free fall + * @brief This section group all the functions concerning the free + * fall detection. + * @{ + * + */ + +/** + * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[set] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16b_wake_up_dur_t wake_up_dur; + lsm6dsv16b_free_fall_t free_fall; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + } + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + if (ret == 0) + { + free_fall.ff_dur = (uint8_t)val & 0x1FU; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + return ret; +} + +/** + * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[get] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16b_wake_up_dur_t wake_up_dur; + lsm6dsv16b_free_fall_t free_fall; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; + + return ret; +} + +/** + * @brief Free fall threshold setting.[set] + * + * @param ctx read / write interface definitions + * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_ff_thresholds_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_ff_thresholds_t val) +{ + lsm6dsv16b_free_fall_t free_fall; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret == 0) + { + free_fall.ff_ths = (uint8_t)val & 0x7U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + return ret; +} + +/** + * @brief Free fall threshold setting.[get] + * + * @param ctx read / write interface definitions + * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_ff_thresholds_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_ff_thresholds_t *val) +{ + lsm6dsv16b_free_fall_t free_fall; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FREE_FALL, (uint8_t *)&free_fall, 1); + + switch (free_fall.ff_ths) + { + case LSM6DSV16B_156_mg: + *val = LSM6DSV16B_156_mg; + break; + + case LSM6DSV16B_219_mg: + *val = LSM6DSV16B_219_mg; + break; + + case LSM6DSV16B_250_mg: + *val = LSM6DSV16B_250_mg; + break; + + case LSM6DSV16B_312_mg: + *val = LSM6DSV16B_312_mg; + break; + + case LSM6DSV16B_344_mg: + *val = LSM6DSV16B_344_mg; + break; + + case LSM6DSV16B_406_mg: + *val = LSM6DSV16B_406_mg; + break; + + case LSM6DSV16B_469_mg: + *val = LSM6DSV16B_469_mg; + break; + + case LSM6DSV16B_500_mg: + *val = LSM6DSV16B_500_mg; + break; + + default: + *val = LSM6DSV16B_156_mg; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup FIFO + * @brief This section group all the functions concerning the fifo usage + * @{ + * + */ + +/** + * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[set] + * + * @param ctx read / write interface definitions + * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16b_fifo_ctrl1_t fifo_ctrl1; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + + if (ret == 0) + { + fifo_ctrl1.wtm = val; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + } + + return ret; +} + +/** + * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[get] + * + * @param ctx read / write interface definitions + * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16b_fifo_ctrl1_t fifo_ctrl1; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + *val = fifo_ctrl1.wtm; + + return ret; +} + +/** + * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[set] + * + * @param ctx read / write interface definitions + * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16b_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.xl_dualc_batch_from_fsm = val; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[get] + * + * @param ctx read / write interface definitions + * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16b_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.xl_dualc_batch_from_fsm; + + return ret; +} + +/** + * @brief It configures the compression algorithm to write non-compressed data at each rate.[set] + * + * @param ctx read / write interface definitions + * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_compress_algo_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_compress_algo_t val) +{ + lsm6dsv16b_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.uncompr_rate = (uint8_t)val & 0x03U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief It configures the compression algorithm to write non-compressed data at each rate.[get] + * + * @param ctx read / write interface definitions + * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_compress_algo_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_compress_algo_t *val) +{ + lsm6dsv16b_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + + switch (fifo_ctrl2.uncompr_rate) + { + case LSM6DSV16B_CMP_DISABLE: + *val = LSM6DSV16B_CMP_DISABLE; + break; + + case LSM6DSV16B_CMP_8_TO_1: + *val = LSM6DSV16B_CMP_8_TO_1; + break; + + case LSM6DSV16B_CMP_16_TO_1: + *val = LSM6DSV16B_CMP_16_TO_1; + break; + + case LSM6DSV16B_CMP_32_TO_1: + *val = LSM6DSV16B_CMP_32_TO_1; + break; + + default: + *val = LSM6DSV16B_CMP_DISABLE; + break; + } + return ret; +} + +/** + * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set] + * + * @param ctx read / write interface definitions + * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, + uint8_t val) +{ + lsm6dsv16b_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.odr_chg_en = val; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get] + * + * @param ctx read / write interface definitions + * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, + uint8_t *val) +{ + lsm6dsv16b_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.odr_chg_en; + + return ret; +} + +/** + * @brief Enables/Disables compression algorithm runtime.[set] + * + * @param ctx read / write interface definitions + * @param val Enables/Disables compression algorithm runtime. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, + uint8_t val) +{ + lsm6dsv16b_emb_func_en_b_t emb_func_en_b; + lsm6dsv16b_fifo_ctrl2_t fifo_ctrl2; + + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.fifo_compr_rt_en = val; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + if (ret == 0) + { + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + emb_func_en_b.fifo_compr_en = val; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables/Disables compression algorithm runtime.[get] + * + * @param ctx read / write interface definitions + * @param val Enables/Disables compression algorithm runtime. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, + uint8_t *val) +{ + lsm6dsv16b_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + + *val = fifo_ctrl2.fifo_compr_rt_en; + + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at threshold level.[set] + * + * @param ctx read / write interface definitions + * @param val Sensing chain FIFO stop values memorization at threshold level. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16b_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.stop_on_wtm = val; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at threshold level.[get] + * + * @param ctx read / write interface definitions + * @param val Sensing chain FIFO stop values memorization at threshold level. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16b_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.stop_on_wtm; + + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[set] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv16b_fifo_xl_batch_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_xl_batch_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_xl_batch_t val) +{ + lsm6dsv16b_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret == 0) + { + fifo_ctrl3.bdr_xl = (uint8_t)val & 0xFU; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + } + + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[get] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv16b_fifo_xl_batch_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_xl_batch_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_xl_batch_t *val) +{ + lsm6dsv16b_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + switch (fifo_ctrl3.bdr_xl) + { + case LSM6DSV16B_XL_NOT_BATCHED: + *val = LSM6DSV16B_XL_NOT_BATCHED; + break; + + case LSM6DSV16B_XL_BATCHED_AT_1Hz875: + *val = LSM6DSV16B_XL_BATCHED_AT_1Hz875; + break; + + case LSM6DSV16B_XL_BATCHED_AT_7Hz5: + *val = LSM6DSV16B_XL_BATCHED_AT_7Hz5; + break; + + case LSM6DSV16B_XL_BATCHED_AT_15Hz: + *val = LSM6DSV16B_XL_BATCHED_AT_15Hz; + break; + + case LSM6DSV16B_XL_BATCHED_AT_30Hz: + *val = LSM6DSV16B_XL_BATCHED_AT_30Hz; + break; + + case LSM6DSV16B_XL_BATCHED_AT_60Hz: + *val = LSM6DSV16B_XL_BATCHED_AT_60Hz; + break; + + case LSM6DSV16B_XL_BATCHED_AT_120Hz: + *val = LSM6DSV16B_XL_BATCHED_AT_120Hz; + break; + + case LSM6DSV16B_XL_BATCHED_AT_240Hz: + *val = LSM6DSV16B_XL_BATCHED_AT_240Hz; + break; + + case LSM6DSV16B_XL_BATCHED_AT_480Hz: + *val = LSM6DSV16B_XL_BATCHED_AT_480Hz; + break; + + case LSM6DSV16B_XL_BATCHED_AT_960Hz: + *val = LSM6DSV16B_XL_BATCHED_AT_960Hz; + break; + + case LSM6DSV16B_XL_BATCHED_AT_1920Hz: + *val = LSM6DSV16B_XL_BATCHED_AT_1920Hz; + break; + + case LSM6DSV16B_XL_BATCHED_AT_3840Hz: + *val = LSM6DSV16B_XL_BATCHED_AT_3840Hz; + break; + + case LSM6DSV16B_XL_BATCHED_AT_7680Hz: + *val = LSM6DSV16B_XL_BATCHED_AT_7680Hz; + break; + + default: + *val = LSM6DSV16B_XL_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[set] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv16b_fifo_gy_batch_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_gy_batch_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_gy_batch_t val) +{ + lsm6dsv16b_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret == 0) + { + fifo_ctrl3.bdr_gy = (uint8_t)val & 0xFU; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + } + + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[get] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv16b_fifo_gy_batch_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_gy_batch_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_gy_batch_t *val) +{ + lsm6dsv16b_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + switch (fifo_ctrl3.bdr_gy) + { + case LSM6DSV16B_GY_NOT_BATCHED: + *val = LSM6DSV16B_GY_NOT_BATCHED; + break; + + case LSM6DSV16B_GY_BATCHED_AT_1Hz875: + *val = LSM6DSV16B_GY_BATCHED_AT_1Hz875; + break; + + case LSM6DSV16B_GY_BATCHED_AT_7Hz5: + *val = LSM6DSV16B_GY_BATCHED_AT_7Hz5; + break; + + case LSM6DSV16B_GY_BATCHED_AT_15Hz: + *val = LSM6DSV16B_GY_BATCHED_AT_15Hz; + break; + + case LSM6DSV16B_GY_BATCHED_AT_30Hz: + *val = LSM6DSV16B_GY_BATCHED_AT_30Hz; + break; + + case LSM6DSV16B_GY_BATCHED_AT_60Hz: + *val = LSM6DSV16B_GY_BATCHED_AT_60Hz; + break; + + case LSM6DSV16B_GY_BATCHED_AT_120Hz: + *val = LSM6DSV16B_GY_BATCHED_AT_120Hz; + break; + + case LSM6DSV16B_GY_BATCHED_AT_240Hz: + *val = LSM6DSV16B_GY_BATCHED_AT_240Hz; + break; + + case LSM6DSV16B_GY_BATCHED_AT_480Hz: + *val = LSM6DSV16B_GY_BATCHED_AT_480Hz; + break; + + case LSM6DSV16B_GY_BATCHED_AT_960Hz: + *val = LSM6DSV16B_GY_BATCHED_AT_960Hz; + break; + + case LSM6DSV16B_GY_BATCHED_AT_1920Hz: + *val = LSM6DSV16B_GY_BATCHED_AT_1920Hz; + break; + + case LSM6DSV16B_GY_BATCHED_AT_3840Hz: + *val = LSM6DSV16B_GY_BATCHED_AT_3840Hz; + break; + + case LSM6DSV16B_GY_BATCHED_AT_7680Hz: + *val = LSM6DSV16B_GY_BATCHED_AT_7680Hz; + break; + + default: + *val = LSM6DSV16B_GY_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief FIFO mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_mode_t val) +{ + lsm6dsv16b_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.fifo_mode = (uint8_t)val & 0x07U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief FIFO mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_mode_t *val) +{ + lsm6dsv16b_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + switch (fifo_ctrl4.fifo_mode) + { + case LSM6DSV16B_BYPASS_MODE: + *val = LSM6DSV16B_BYPASS_MODE; + break; + + case LSM6DSV16B_FIFO_MODE: + *val = LSM6DSV16B_FIFO_MODE; + break; + + case LSM6DSV16B_STREAM_WTM_TO_FULL_MODE: + *val = LSM6DSV16B_STREAM_WTM_TO_FULL_MODE; + break; + + case LSM6DSV16B_STREAM_TO_FIFO_MODE: + *val = LSM6DSV16B_STREAM_TO_FIFO_MODE; + break; + + case LSM6DSV16B_BYPASS_TO_STREAM_MODE: + *val = LSM6DSV16B_BYPASS_TO_STREAM_MODE; + break; + + case LSM6DSV16B_STREAM_MODE: + *val = LSM6DSV16B_STREAM_MODE; + break; + + case LSM6DSV16B_BYPASS_TO_FIFO_MODE: + *val = LSM6DSV16B_BYPASS_TO_FIFO_MODE; + break; + + default: + *val = LSM6DSV16B_BYPASS_MODE; + break; + } + return ret; +} + +/** + * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[set] + * + * @param ctx read / write interface definitions + * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_temp_batch_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_temp_batch_t val) +{ + lsm6dsv16b_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.odr_t_batch = (uint8_t)val & 0x03U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[get] + * + * @param ctx read / write interface definitions + * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_temp_batch_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_temp_batch_t *val) +{ + lsm6dsv16b_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + switch (fifo_ctrl4.odr_t_batch) + { + case LSM6DSV16B_TEMP_NOT_BATCHED: + *val = LSM6DSV16B_TEMP_NOT_BATCHED; + break; + + case LSM6DSV16B_TEMP_BATCHED_AT_1Hz875: + *val = LSM6DSV16B_TEMP_BATCHED_AT_1Hz875; + break; + + case LSM6DSV16B_TEMP_BATCHED_AT_15Hz: + *val = LSM6DSV16B_TEMP_BATCHED_AT_15Hz; + break; + + case LSM6DSV16B_TEMP_BATCHED_AT_60Hz: + *val = LSM6DSV16B_TEMP_BATCHED_AT_60Hz; + break; + + default: + *val = LSM6DSV16B_TEMP_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[set] + * + * @param ctx read / write interface definitions + * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_timestamp_batch_t val) +{ + lsm6dsv16b_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.dec_ts_batch = (uint8_t)val & 0x3U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[get] + * + * @param ctx read / write interface definitions + * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_timestamp_batch_t *val) +{ + lsm6dsv16b_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + switch (fifo_ctrl4.dec_ts_batch) + { + case LSM6DSV16B_TMSTMP_NOT_BATCHED: + *val = LSM6DSV16B_TMSTMP_NOT_BATCHED; + break; + + case LSM6DSV16B_TMSTMP_DEC_1: + *val = LSM6DSV16B_TMSTMP_DEC_1; + break; + + case LSM6DSV16B_TMSTMP_DEC_8: + *val = LSM6DSV16B_TMSTMP_DEC_8; + break; + + case LSM6DSV16B_TMSTMP_DEC_32: + *val = LSM6DSV16B_TMSTMP_DEC_32; + break; + + default: + *val = LSM6DSV16B_TMSTMP_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[set] + * + * @param ctx read / write interface definitions + * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx, + uint16_t val) +{ + lsm6dsv16b_counter_bdr_reg1_t counter_bdr_reg1; + lsm6dsv16b_counter_bdr_reg2_t counter_bdr_reg2; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + + if (ret == 0) + { + counter_bdr_reg2.cnt_bdr_th = (uint8_t)val & 0xFFU; + counter_bdr_reg1.cnt_bdr_th = (uint8_t)(val >> 8) & 0x3U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_COUNTER_BDR_REG2, (uint8_t *)&counter_bdr_reg2, 1); + } + + return ret; +} + +/** + * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[get] + * + * @param ctx read / write interface definitions + * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx, + uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_COUNTER_BDR_REG1, &buff[0], 2); + *val = (uint16_t)buff[0] & 0x3U; + *val = (*val * 256U) + (uint16_t)buff[1]; + + return ret; +} + +/** + * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope.[set] + * + * @param ctx read / write interface definitions + * @param val XL_BATCH_EVENT, GY_BATCH_EVENT + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_batch_cnt_event_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_batch_cnt_event_t val) +{ + lsm6dsv16b_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + + if (ret == 0) + { + counter_bdr_reg1.trig_counter_bdr = (uint8_t)val & 0x03U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + } + + return ret; +} + +/** + * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope.[get] + * + * @param ctx read / write interface definitions + * @param val XL_BATCH_EVENT, GY_BATCH_EVENT + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_batch_cnt_event_t *val) +{ + lsm6dsv16b_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + switch (counter_bdr_reg1.trig_counter_bdr) + { + case LSM6DSV16B_XL_BATCH_EVENT: + *val = LSM6DSV16B_XL_BATCH_EVENT; + break; + + case LSM6DSV16B_GY_BATCH_EVENT: + *val = LSM6DSV16B_GY_BATCH_EVENT; + break; + + default: + *val = LSM6DSV16B_XL_BATCH_EVENT; + break; + } + return ret; +} + +/** + * @brief Batching in FIFO buffer of SFLP.[set] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of SFLP values. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_sflp_batch_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_sflp_raw_t val) +{ + lsm6dsv16b_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + emb_func_fifo_en_a.sflp_game_fifo_en = val.game_rotation; + emb_func_fifo_en_a.sflp_gravity_fifo_en = val.gravity; + emb_func_fifo_en_a.sflp_gbias_fifo_en = val.gbias; + ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_FIFO_EN_A, + (uint8_t *)&emb_func_fifo_en_a, 1); + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of SFLP.[get] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of SFLP values. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_sflp_batch_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_sflp_raw_t *val) +{ + lsm6dsv16b_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + + val->game_rotation = emb_func_fifo_en_a.sflp_game_fifo_en; + val->gravity = emb_func_fifo_en_a.sflp_gravity_fifo_en; + val->gbias = emb_func_fifo_en_a.sflp_gbias_fifo_en; + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Status of FIFO.[get] + * + * @param ctx read / write interface definitions + * @param val Status of FIFO (level and flags). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_status_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_status_t *val) +{ + uint8_t buff[2]; + lsm6dsv16b_fifo_status2_t status; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_STATUS1, (uint8_t *)&buff[0], 2); + bytecpy((uint8_t *)&status, &buff[1]); + + val->fifo_bdr = status.counter_bdr_ia; + val->fifo_ovr = status.fifo_ovr_ia; + val->fifo_full = status.fifo_full_ia; + val->fifo_th = status.fifo_wtm_ia; + + val->fifo_level = (uint16_t)buff[1] & 0x01U; + val->fifo_level = (val->fifo_level * 256U) + buff[0]; + + return ret; +} + +/** + * @brief FIFO data output[get] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv16b_fifo_out_raw_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_out_raw_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_out_raw_t *val) +{ + lsm6dsv16b_fifo_data_out_tag_t fifo_data_out_tag; + uint8_t buff[7]; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_DATA_OUT_TAG, buff, 7); + bytecpy((uint8_t *)&fifo_data_out_tag, &buff[0]); + + switch (fifo_data_out_tag.tag_sensor) + { + case LSM6DSV16B_FIFO_EMPTY: + val->tag = LSM6DSV16B_FIFO_EMPTY; + break; + + case LSM6DSV16B_GY_NC_TAG: + val->tag = LSM6DSV16B_GY_NC_TAG; + break; + + case LSM6DSV16B_XL_NC_TAG: + val->tag = LSM6DSV16B_XL_NC_TAG; + break; + + case LSM6DSV16B_TIMESTAMP_TAG: + val->tag = LSM6DSV16B_TIMESTAMP_TAG; + break; + + case LSM6DSV16B_TEMPERATURE_TAG: + val->tag = LSM6DSV16B_TEMPERATURE_TAG; + break; + + case LSM6DSV16B_CFG_CHANGE_TAG: + val->tag = LSM6DSV16B_CFG_CHANGE_TAG; + break; + + case LSM6DSV16B_XL_NC_T_2_TAG: + val->tag = LSM6DSV16B_XL_NC_T_2_TAG; + break; + + case LSM6DSV16B_XL_NC_T_1_TAG: + val->tag = LSM6DSV16B_XL_NC_T_1_TAG; + break; + + case LSM6DSV16B_XL_2XC_TAG: + val->tag = LSM6DSV16B_XL_2XC_TAG; + break; + + case LSM6DSV16B_XL_3XC_TAG: + val->tag = LSM6DSV16B_XL_3XC_TAG; + break; + + case LSM6DSV16B_GY_NC_T_2_TAG: + val->tag = LSM6DSV16B_GY_NC_T_2_TAG; + break; + + case LSM6DSV16B_GY_NC_T_1_TAG: + val->tag = LSM6DSV16B_GY_NC_T_1_TAG; + break; + + case LSM6DSV16B_GY_2XC_TAG: + val->tag = LSM6DSV16B_GY_2XC_TAG; + break; + + case LSM6DSV16B_GY_3XC_TAG: + val->tag = LSM6DSV16B_GY_3XC_TAG; + break; + + case LSM6DSV16B_STEP_COUNTER_TAG: + val->tag = LSM6DSV16B_STEP_COUNTER_TAG; + break; + + case LSM6DSV16B_SFLP_GAME_ROTATION_VECTOR_TAG: + val->tag = LSM6DSV16B_SFLP_GAME_ROTATION_VECTOR_TAG; + break; + + case LSM6DSV16B_SFLP_GYROSCOPE_BIAS_TAG: + val->tag = LSM6DSV16B_SFLP_GYROSCOPE_BIAS_TAG; + break; + + case LSM6DSV16B_SFLP_GRAVITY_VECTOR_TAG: + val->tag = LSM6DSV16B_SFLP_GRAVITY_VECTOR_TAG; + break; + + case LSM6DSV16B_XL_DUAL_CORE: + val->tag = LSM6DSV16B_XL_DUAL_CORE; + break; + + default: + val->tag = LSM6DSV16B_FIFO_EMPTY; + break; + } + + val->cnt = fifo_data_out_tag.tag_cnt; + + val->data[0] = buff[1]; + val->data[1] = buff[2]; + val->data[2] = buff[3]; + val->data[3] = buff[4]; + val->data[4] = buff[5]; + val->data[5] = buff[6]; + + return ret; +} + +/** + * @brief Batching in FIFO buffer of step counter value.[set] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of step counter value. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16b_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + if (ret == 0) + { + emb_func_fifo_en_a.step_counter_fifo_en = val; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of step counter value.[get] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of step counter value. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16b_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + *val = emb_func_fifo_en_a.step_counter_fifo_en; + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Step Counter + * @brief This section groups all the functions that manage pedometer. + * @{ + * + */ + +/** + * @brief Step counter mode[set] + * + * @param ctx read / write interface definitions + * @param val false_step_rej, step_counter, step_detector, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_stpcnt_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_stpcnt_mode_t val) +{ + lsm6dsv16b_emb_func_en_a_t emb_func_en_a; + lsm6dsv16b_emb_func_en_b_t emb_func_en_b; + lsm6dsv16b_pedo_cmd_reg_t pedo_cmd_reg; + int32_t ret; + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + emb_func_en_a.pedo_en = val.step_counter_enable; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + if (ret == 0) + { + pedo_cmd_reg.fp_rejection_en = val.false_step_rej; + ret = lsm6dsv16b_ln_pg_write(ctx, LSM6DSV16B_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + return ret; +} + +/** + * @brief Step counter mode[get] + * + * @param ctx read / write interface definitions + * @param val false_step_rej, step_counter, step_detector, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_stpcnt_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_stpcnt_mode_t *val) +{ + lsm6dsv16b_emb_func_en_a_t emb_func_en_a; + lsm6dsv16b_pedo_cmd_reg_t pedo_cmd_reg; + int32_t ret; + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + val->false_step_rej = pedo_cmd_reg.fp_rejection_en; + val->step_counter_enable = emb_func_en_a.pedo_en; + + return ret; +} + +/** + * @brief Step counter output, number of detected steps.[get] + * + * @param ctx read / write interface definitions + * @param val Step counter output, number of detected steps. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_STEP_COUNTER_L, &buff[0], 2); + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief Reset step counter.[set] + * + * @param ctx read / write interface definitions + * @param val Reset step counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_stpcnt_rst_step_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16b_emb_func_src_t emb_func_src; + int32_t ret; + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + + if (ret == 0) + { + emb_func_src.pedo_rst_step = val; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Reset step counter.[get] + * + * @param ctx read / write interface definitions + * @param val Reset step counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16b_emb_func_src_t emb_func_src; + int32_t ret; + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + + *val = emb_func_src.pedo_rst_step; + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Pedometer debounce configuration.[set] + * + * @param ctx read / write interface definitions + * @param val Pedometer debounce configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16b_pedo_deb_steps_conf_t pedo_deb_steps_conf; + int32_t ret; + + ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, + 1); + if (ret == 0) + { + pedo_deb_steps_conf.deb_step = val; + ret = lsm6dsv16b_ln_pg_write(ctx, LSM6DSV16B_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, + 1); + } + + return ret; +} + +/** + * @brief Pedometer debounce configuration.[get] + * + * @param ctx read / write interface definitions + * @param val Pedometer debounce configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16b_pedo_deb_steps_conf_t pedo_deb_steps_conf; + int32_t ret; + + ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, + 1); + *val = pedo_deb_steps_conf.deb_step; + + return ret; +} + +/** + * @brief Time period register for step detection on delta time.[set] + * + * @param ctx read / write interface definitions + * @param val Time period register for step detection on delta time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + + ret = lsm6dsv16b_ln_pg_write(ctx, LSM6DSV16B_PEDO_SC_DELTAT_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief Time period register for step detection on delta time.[get] + * + * @param ctx read / write interface definitions + * @param val Time period register for step detection on delta time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_PEDO_SC_DELTAT_L, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Significant motion + * @brief This section groups all the functions that manage the + * significant motion detection. + * @{ + * + */ + +/** + * @brief Enables significant motion detection function.[set] + * + * @param ctx read / write interface definitions + * @param val Enables significant motion detection function. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16b_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { + emb_func_en_a.sign_motion_en = val; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + + return ret; +} + +/** + * @brief Enables significant motion detection function.[get] + * + * @param ctx read / write interface definitions + * @param val Enables significant motion detection function. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16b_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + *val = emb_func_en_a.sign_motion_en; + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Tilt detection + * @brief This section groups all the functions that manage the tilt + * event detection. + * @{ + * + */ + +/** + * @brief Tilt calculation.[set] + * + * @param ctx read / write interface definitions + * @param val Tilt calculation. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16b_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { + emb_func_en_a.tilt_en = val; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Tilt calculation.[get] + * + * @param ctx read / write interface definitions + * @param val Tilt calculation. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16b_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + *val = emb_func_en_a.tilt_en; + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Sensor Fusion Low Power (SFLP) + * @brief This section groups all the functions that manage pedometer. + * @{ + * + */ + +/** + * @brief Enable SFLP Game Rotation Vector (6x).[set] + * + * @param ctx read / write interface definitions + * @param val Enable/Disable game rotation value (0/1). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + lsm6dsv16b_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + emb_func_en_a.sflp_game_en = val; + ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, + (uint8_t *)&emb_func_en_a, 1); + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable SFLP Game Rotation Vector (6x).[get] + * + * @param ctx read / write interface definitions + * @param val Enable/Disable game rotation value (0/1). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + lsm6dsv16b_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + *val = emb_func_en_a.sflp_game_en; + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief SFLP Data Rate (ODR) configuration.[set] + * + * @param ctx read / write interface definitions + * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_sflp_data_rate_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_sflp_data_rate_t val) +{ + lsm6dsv16b_sflp_odr_t sflp_odr; + int32_t ret; + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + sflp_odr.sflp_game_odr = (uint8_t)val & 0x07U; + ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_SFLP_ODR, (uint8_t *)&sflp_odr, + 1); + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief SFLP Data Rate (ODR) configuration.[get] + * + * @param ctx read / write interface definitions + * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_sflp_data_rate_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_sflp_data_rate_t *val) +{ + lsm6dsv16b_sflp_odr_t sflp_odr; + int32_t ret; + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + switch (sflp_odr.sflp_game_odr) + { + case LSM6DSV16B_SFLP_15Hz: + *val = LSM6DSV16B_SFLP_15Hz; + break; + + case LSM6DSV16B_SFLP_30Hz: + *val = LSM6DSV16B_SFLP_30Hz; + break; + + case LSM6DSV16B_SFLP_60Hz: + *val = LSM6DSV16B_SFLP_60Hz; + break; + + case LSM6DSV16B_SFLP_120Hz: + *val = LSM6DSV16B_SFLP_120Hz; + break; + + case LSM6DSV16B_SFLP_240Hz: + *val = LSM6DSV16B_SFLP_240Hz; + break; + + case LSM6DSV16B_SFLP_480Hz: + *val = LSM6DSV16B_SFLP_480Hz; + break; + + default: + *val = LSM6DSV16B_SFLP_15Hz; + break; + } + return ret; +} + +/* + * Original conversion routines taken from: https://github.com/numpy/numpy + * + * uint16_t npy_floatbits_to_halfbits(uint32_t f); + * uint16_t npy_float_to_half(float_t f); + * + * Released under BSD-3-Clause License + */ + +#define NPY_HALF_GENERATE_OVERFLOW 0 /* do not trigger FP overflow */ +#define NPY_HALF_GENERATE_UNDERFLOW 0 /* do not trigger FP underflow */ +#ifndef NPY_HALF_ROUND_TIES_TO_EVEN +#define NPY_HALF_ROUND_TIES_TO_EVEN 1 +#endif + +static uint16_t npy_floatbits_to_halfbits(uint32_t f) +{ + uint32_t f_exp, f_sig; + uint16_t h_sgn, h_exp, h_sig; + + h_sgn = (uint16_t)((f & 0x80000000u) >> 16); + f_exp = (f & 0x7f800000u); + + /* Exponent overflow/NaN converts to signed inf/NaN */ + if (f_exp >= 0x47800000u) + { + if (f_exp == 0x7f800000u) + { + /* Inf or NaN */ + f_sig = (f & 0x007fffffu); + if (f_sig != 0) + { + /* NaN - propagate the flag in the significand... */ + uint16_t ret = (uint16_t)(0x7c00u + (f_sig >> 13)); + /* ...but make sure it stays a NaN */ + if (ret == 0x7c00u) + { + ret++; + } + return h_sgn + ret; + } + else + { + /* signed inf */ + return (uint16_t)(h_sgn + 0x7c00u); + } + } + else + { + /* overflow to signed inf */ +#if NPY_HALF_GENERATE_OVERFLOW + npy_set_floatstatus_overflow(); +#endif + return (uint16_t)(h_sgn + 0x7c00u); + } + } + + /* Exponent underflow converts to a subnormal half or signed zero */ + if (f_exp <= 0x38000000u) + { + /* + * Signed zeros, subnormal floats, and floats with small + * exponents all convert to signed zero half-floats. + */ + if (f_exp < 0x33000000u) + { +#if NPY_HALF_GENERATE_UNDERFLOW + /* If f != 0, it underflowed to 0 */ + if ((f & 0x7fffffff) != 0) + { + npy_set_floatstatus_underflow(); + } +#endif + return h_sgn; + } + /* Make the subnormal significand */ + f_exp >>= 23; + f_sig = (0x00800000u + (f & 0x007fffffu)); +#if NPY_HALF_GENERATE_UNDERFLOW + /* If it's not exactly represented, it underflowed */ + if ((f_sig & (((uint32_t)1 << (126 - f_exp)) - 1)) != 0) + { + npy_set_floatstatus_underflow(); + } +#endif + /* + * Usually the significand is shifted by 13. For subnormals an + * additional shift needs to occur. This shift is one for the largest + * exponent giving a subnormal `f_exp = 0x38000000 >> 23 = 112`, which + * offsets the new first bit. At most the shift can be 1+10 bits. + */ + f_sig >>= (113 - f_exp); + /* Handle rounding by adding 1 to the bit beyond half precision */ +#if NPY_HALF_ROUND_TIES_TO_EVEN + /* + * If the last bit in the half significand is 0 (already even), and + * the remaining bit pattern is 1000...0, then we do not add one + * to the bit after the half significand. However, the (113 - f_exp) + * shift can lose up to 11 bits, so the || checks them in the original. + * In all other cases, we can just add one. + */ + if (((f_sig & 0x00003fffu) != 0x00001000u) || (f & 0x000007ffu)) + { + f_sig += 0x00001000u; + } +#else + f_sig += 0x00001000u; +#endif + h_sig = (uint16_t)(f_sig >> 13); + /* + * If the rounding causes a bit to spill into h_exp, it will + * increment h_exp from zero to one and h_sig will be zero. + * This is the correct result. + */ + return (uint16_t)(h_sgn + h_sig); + } + + /* Regular case with no overflow or underflow */ + h_exp = (uint16_t)((f_exp - 0x38000000u) >> 13); + /* Handle rounding by adding 1 to the bit beyond half precision */ + f_sig = (f & 0x007fffffu); +#if NPY_HALF_ROUND_TIES_TO_EVEN + /* + * If the last bit in the half significand is 0 (already even), and + * the remaining bit pattern is 1000...0, then we do not add one + * to the bit after the half significand. In all other cases, we do. + */ + if ((f_sig & 0x00003fffu) != 0x00001000u) + { + f_sig += 0x00001000u; + } +#else + f_sig += 0x00001000u; +#endif + h_sig = (uint16_t)(f_sig >> 13); + /* + * If the rounding causes a bit to spill into h_exp, it will + * increment h_exp by one and h_sig will be zero. This is the + * correct result. h_exp may increment to 15, at greatest, in + * which case the result overflows to a signed inf. + */ +#if NPY_HALF_GENERATE_OVERFLOW + h_sig += h_exp; + if (h_sig == 0x7c00u) + { + npy_set_floatstatus_overflow(); + } + return h_sgn + h_sig; +#else + return h_sgn + h_exp + h_sig; +#endif +} + +static uint16_t npy_float_to_half(float_t f) +{ + union + { + float_t f; + uint32_t fbits; + } conv; + conv.f = f; + return npy_floatbits_to_halfbits(conv.fbits); +} + +/** + * @brief SFLP GBIAS value. The register value is expressed as half-precision + * floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent + * bits; F: 10 fraction bits).[set] + * + * @param ctx read / write interface definitions + * @param val GBIAS x/y/z val. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_sflp_game_gbias_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_sflp_gbias_t *val) +{ + lsm6dsv16b_sflp_data_rate_t sflp_odr; + lsm6dsv16b_emb_func_exec_status_t emb_func_sts; + lsm6dsv16b_data_ready_t drdy; + lsm6dsv16b_xl_full_scale_t xl_fs; + lsm6dsv16b_ctrl10_t ctrl10; + uint8_t master_config; + uint8_t emb_func_en_saved[2]; + uint8_t conf_saved[2]; + uint8_t reg_zero[2] = {0x0, 0x0}; + uint16_t gbias_hf[3]; + float_t k = 0.005f; + int16_t xl_data[3]; + int32_t data_tmp; + uint8_t *data_ptr = (uint8_t *)&data_tmp; + uint8_t i, j; + int32_t ret; + + ret = lsm6dsv16b_sflp_data_rate_get(ctx, &sflp_odr); + if (ret != 0) + { + return ret; + } + + /* Calculate k factor */ + switch (sflp_odr) + { + case LSM6DSV16B_SFLP_15Hz: + k = 0.04f; + break; + case LSM6DSV16B_SFLP_30Hz: + k = 0.02f; + break; + case LSM6DSV16B_SFLP_60Hz: + k = 0.01f; + break; + case LSM6DSV16B_SFLP_120Hz: + k = 0.005f; + break; + case LSM6DSV16B_SFLP_240Hz: + k = 0.0025f; + break; + case LSM6DSV16B_SFLP_480Hz: + k = 0.00125f; + break; + } + + /* compute gbias as half precision float in order to be put in embedded advanced feature register */ + gbias_hf[0] = npy_float_to_half(val->gbias_x * (3.14159265358979323846f / 180.0f) / k); + gbias_hf[1] = npy_float_to_half(val->gbias_y * (3.14159265358979323846f / 180.0f) / k); + gbias_hf[2] = npy_float_to_half(val->gbias_z * (3.14159265358979323846f / 180.0f) / k); + + /* Save sensor configuration and set high-performance mode (if the sensor is in power-down mode, turn it on) */ + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL1, conf_saved, 2); + ret += lsm6dsv16b_xl_mode_set(ctx, LSM6DSV16B_XL_HIGH_PERFORMANCE_MD); + ret += lsm6dsv16b_gy_mode_set(ctx, LSM6DSV16B_GY_HIGH_PERFORMANCE_MD); + if ((conf_saved[0] & 0x0FU) == LSM6DSV16B_XL_ODR_OFF) + { + ret += lsm6dsv16b_xl_data_rate_set(ctx, LSM6DSV16B_XL_ODR_AT_120Hz); + } + + /* disable algos */ + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, emb_func_en_saved, + 2); + ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, reg_zero, 2); + do + { + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EXEC_STATUS, + (uint8_t *)&emb_func_sts, 1); + } while (emb_func_sts.emb_func_endop != 1); + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + // enable gbias setting + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL10, (uint8_t *)&ctrl10, 1); + ctrl10.emb_func_debug = 1; + ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL10, (uint8_t *)&ctrl10, 1); + + /* enable algos */ + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + emb_func_en_saved[0] |= 0x02; /* force SFLP GAME en */ + ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, emb_func_en_saved, + 2); + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + ret += lsm6dsv16b_xl_full_scale_get(ctx, &xl_fs); + + /* Read XL data */ + do + { + ret += lsm6dsv16b_flag_data_ready_get(ctx, &drdy); + } while (drdy.drdy_xl != 1); + ret += lsm6dsv16b_acceleration_raw_get(ctx, xl_data); + + /* force sflp initialization */ + master_config = 0x40; + ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, &master_config, + 1); + for (i = 0; i < 3; i++) + { + j = 0; + data_tmp = (int32_t)xl_data[i]; + data_tmp <<= xl_fs; // shift based on current fs + ret += lsm6dsv16b_write_reg(ctx, 0x02 + 3 * i, &data_ptr[j++], 1); + ret += lsm6dsv16b_write_reg(ctx, 0x03 + 3 * i, &data_ptr[j++], 1); + ret += lsm6dsv16b_write_reg(ctx, 0x04 + 3 * i, &data_ptr[j], 1); + } + for (i = 0; i < 3; i++) + { + j = 0; + data_tmp = 0; + ret += lsm6dsv16b_write_reg(ctx, 0x0B + 3 * i, &data_ptr[j++], 1); + ret += lsm6dsv16b_write_reg(ctx, 0x0C + 3 * i, &data_ptr[j++], 1); + ret += lsm6dsv16b_write_reg(ctx, 0x0D + 3 * i, &data_ptr[j], 1); + } + master_config = 0x00; + ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, &master_config, + 1); + + // wait end_op (and at least 30 us) + ctx->mdelay(1); + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + do + { + ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EXEC_STATUS, + (uint8_t *)&emb_func_sts, 1); + } while (emb_func_sts.emb_func_endop != 1); + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + /* write gbias in embedded advanced features registers */ + ret += lsm6dsv16b_ln_pg_write(ctx, LSM6DSV16B_SFLP_GAME_GBIASX_L, + (uint8_t *)gbias_hf, 6); + + /* reload previous sensor configuration */ + ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL1, conf_saved, 2); + + // disable gbias setting + ctrl10.emb_func_debug = 0; + ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL10, (uint8_t *)&ctrl10, 1); + + return ret; +} + +/** + * @brief SFLP initial configuration [set] + * + * @param ctx read / write interface definitions + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_sflp_configure(const stmdev_ctx_t *ctx) +{ + uint8_t val = 0x50; + int32_t ret; + + ret = lsm6dsv16b_ln_pg_write(ctx, 0xD2, &val, 1); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Finite State Machine (FSM) + * @brief This section groups all the functions that manage the + * state_machine. + * @{ + * + */ + +/** + * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[set] + * + * @param ctx read / write interface definitions + * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fsm_permission_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_fsm_permission_t val) +{ + lsm6dsv16b_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret == 0) + { + func_cfg_access.fsm_wr_ctrl_en = (uint8_t)val & 0x01U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[get] + * + * @param ctx read / write interface definitions + * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fsm_permission_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_fsm_permission_t *val) +{ + lsm6dsv16b_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + switch (func_cfg_access.fsm_wr_ctrl_en) + { + case LSM6DSV16B_PROTECT_CTRL_REGS: + *val = LSM6DSV16B_PROTECT_CTRL_REGS; + break; + + case LSM6DSV16B_WRITE_CTRL_REG: + *val = LSM6DSV16B_WRITE_CTRL_REG; + break; + + default: + *val = LSM6DSV16B_PROTECT_CTRL_REGS; + break; + } + return ret; +} + +/** + * @brief Return the status of the CTRL registers permission (standard interface vs FSM).[get] + * + * @param ctx read / write interface definitions + * @param val 0: all FSM regs are under std_if control, 1: some regs are under FSM control. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fsm_permission_status(const stmdev_ctx_t *ctx, + lsm6dsv16b_fsm_permission_status_t *val) +{ + lsm6dsv16b_ctrl_status_t status; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL_STATUS, (uint8_t *)&status, 1); + *val = (status.fsm_wr_ctrl_status == 0) ? LSM6DSV16B_STD_IF_CONTROL : LSM6DSV16B_FSM_CONTROL; + + return ret; +} + +/** + * @brief Enable Finite State Machine (FSM) feature.[set] + * + * @param ctx read / write interface definitions + * @param val Enable Finite State Machine (FSM) feature. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fsm_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16b_fsm_mode_t val) +{ + lsm6dsv16b_emb_func_en_b_t emb_func_en_b; + lsm6dsv16b_fsm_enable_t fsm_enable; + int32_t ret; + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + } + if ((val.fsm1_en | val.fsm2_en | val.fsm1_en | val.fsm1_en + | val.fsm1_en | val.fsm2_en | val.fsm1_en | val.fsm1_en) == PROPERTY_ENABLE) + { + emb_func_en_b.fsm_en = PROPERTY_ENABLE; + } + else + { + emb_func_en_b.fsm_en = PROPERTY_DISABLE; + } + if (ret == 0) + { + fsm_enable.fsm1_en = val.fsm1_en; + fsm_enable.fsm2_en = val.fsm2_en; + fsm_enable.fsm3_en = val.fsm3_en; + fsm_enable.fsm4_en = val.fsm4_en; + fsm_enable.fsm5_en = val.fsm5_en; + fsm_enable.fsm6_en = val.fsm6_en; + fsm_enable.fsm7_en = val.fsm7_en; + fsm_enable.fsm8_en = val.fsm8_en; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + } + if (ret == 0) + { + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable Finite State Machine (FSM) feature.[get] + * + * @param ctx read / write interface definitions + * @param val Enable Finite State Machine (FSM) feature. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fsm_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16b_fsm_mode_t *val) +{ + lsm6dsv16b_fsm_enable_t fsm_enable; + int32_t ret; + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + val->fsm1_en = fsm_enable.fsm1_en; + val->fsm2_en = fsm_enable.fsm2_en; + val->fsm3_en = fsm_enable.fsm3_en; + val->fsm4_en = fsm_enable.fsm4_en; + val->fsm5_en = fsm_enable.fsm5_en; + val->fsm6_en = fsm_enable.fsm6_en; + val->fsm7_en = fsm_enable.fsm7_en; + val->fsm8_en = fsm_enable.fsm8_en; + + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[set] + * + * @param ctx read / write interface definitions + * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FSM_LONG_COUNTER_L, (uint8_t *)&buff[0], 2); + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[get] + * + * @param ctx read / write interface definitions + * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FSM_LONG_COUNTER_L, &buff[0], 2); + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief FSM output registers[get] + * + * @param ctx read / write interface definitions + * @param val FSM output registers + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dsv16b_fsm_out_t *val) +{ + int32_t ret; + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FSM_OUTS1, (uint8_t *)val, 8); + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Finite State Machine Output Data Rate (ODR) configuration.[set] + * + * @param ctx read / write interface definitions + * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fsm_data_rate_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_fsm_data_rate_t val) +{ + lsm6dsv16b_fsm_odr_t fsm_odr; + int32_t ret; + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FSM_ODR, (uint8_t *)&fsm_odr, 1); + } + + if (ret == 0) + { + fsm_odr.fsm_odr = (uint8_t)val & 0x07U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FSM_ODR, (uint8_t *)&fsm_odr, 1); + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Finite State Machine Output Data Rate (ODR) configuration.[get] + * + * @param ctx read / write interface definitions + * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fsm_data_rate_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_fsm_data_rate_t *val) +{ + lsm6dsv16b_fsm_odr_t fsm_odr; + int32_t ret; + + ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FSM_ODR, (uint8_t *)&fsm_odr, 1); + } + + ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK); + + switch (fsm_odr.fsm_odr) + { + case LSM6DSV16B_FSM_15Hz: + *val = LSM6DSV16B_FSM_15Hz; + break; + + case LSM6DSV16B_FSM_30Hz: + *val = LSM6DSV16B_FSM_30Hz; + break; + + case LSM6DSV16B_FSM_60Hz: + *val = LSM6DSV16B_FSM_60Hz; + break; + + case LSM6DSV16B_FSM_120Hz: + *val = LSM6DSV16B_FSM_120Hz; + break; + + case LSM6DSV16B_FSM_240Hz: + *val = LSM6DSV16B_FSM_240Hz; + break; + + case LSM6DSV16B_FSM_480Hz: + *val = LSM6DSV16B_FSM_480Hz; + break; + + case LSM6DSV16B_FSM_960Hz: + *val = LSM6DSV16B_FSM_960Hz; + break; + + default: + *val = LSM6DSV16B_FSM_15Hz; + break; + } + return ret; +} + +/** + * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[set] + * + * @param ctx read / write interface definitions + * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fsm_long_cnt_timeout_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = lsm6dsv16b_ln_pg_write(ctx, LSM6DSV16B_FSM_LC_TIMEOUT_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[get] + * + * @param ctx read / write interface definitions + * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_FSM_LC_TIMEOUT_L, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief FSM number of programs.[set] + * + * @param ctx read / write interface definitions + * @param val FSM number of programs. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16b_fsm_programs_t fsm_programs; + int32_t ret; + + ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + if (ret == 0) + { + fsm_programs.fsm_n_prog = val; + ret = lsm6dsv16b_ln_pg_write(ctx, LSM6DSV16B_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + } + + return ret; +} + +/** + * @brief FSM number of programs.[get] + * + * @param ctx read / write interface definitions + * @param val FSM number of programs. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16b_fsm_programs_t fsm_programs; + int32_t ret; + + ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + *val = fsm_programs.fsm_n_prog; + + + return ret; +} + +/** + * @brief FSM start address. First available address is 0x35C.[set] + * + * @param ctx read / write interface definitions + * @param val FSM start address. First available address is 0x35C. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = lsm6dsv16b_ln_pg_write(ctx, LSM6DSV16B_FSM_START_ADD_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief FSM start address. First available address is 0x35C.[get] + * + * @param ctx read / write interface definitions + * @param val FSM start address. First available address is 0x35C. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_FSM_START_ADD_L, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @addtogroup Accelerometer user offset correction + * @brief This section group all the functions concerning the + * usage of Accelerometer user offset correction + * @{ + * + */ + +/** + * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[set] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_xl_offset_on_out_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16b_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.usr_off_on_out = val; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[get] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16b_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.usr_off_on_out; + + return ret; +} + +/** + * @brief Accelerometer user offset correction values in mg.[set] + * + * @param ctx read / write interface definitions + * @param val Accelerometer user offset correction values in mg. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_xl_offset_mg_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_xl_offset_mg_t val) +{ + lsm6dsv16b_z_ofs_usr_t z_ofs_usr; + lsm6dsv16b_y_ofs_usr_t y_ofs_usr; + lsm6dsv16b_x_ofs_usr_t x_ofs_usr; + lsm6dsv16b_ctrl9_t ctrl9; + int32_t ret; + float_t tmp; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + } + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + } + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + } + + + if ((val.x_mg < (0.0078125f * 127.0f)) && (val.x_mg > (0.0078125f * -127.0f)) && + (val.y_mg < (0.0078125f * 127.0f)) && (val.y_mg > (0.0078125f * -127.0f)) && + (val.z_mg < (0.0078125f * 127.0f)) && (val.z_mg > (0.0078125f * -127.0f))) + { + ctrl9.usr_off_w = 0; + + tmp = val.z_mg / 0.0078125f; + z_ofs_usr.z_ofs_usr = (uint8_t)tmp; + + tmp = val.y_mg / 0.0078125f; + y_ofs_usr.y_ofs_usr = (uint8_t)tmp; + + tmp = val.x_mg / 0.0078125f; + x_ofs_usr.x_ofs_usr = (uint8_t)tmp; + } + else if ((val.x_mg < (0.125f * 127.0f)) && (val.x_mg > (0.125f * -127.0f)) && + (val.y_mg < (0.125f * 127.0f)) && (val.y_mg > (0.125f * -127.0f)) && + (val.z_mg < (0.125f * 127.0f)) && (val.z_mg > (0.125f * -127.0f))) + { + ctrl9.usr_off_w = 1; + + tmp = val.z_mg / 0.125f; + z_ofs_usr.z_ofs_usr = (uint8_t)tmp; + + tmp = val.y_mg / 0.125f; + y_ofs_usr.y_ofs_usr = (uint8_t)tmp; + + tmp = val.x_mg / 0.125f; + x_ofs_usr.x_ofs_usr = (uint8_t)tmp; + } + else // out of limit + { + ctrl9.usr_off_w = 1; + z_ofs_usr.z_ofs_usr = 0xFFU; + y_ofs_usr.y_ofs_usr = 0xFFU; + x_ofs_usr.x_ofs_usr = 0xFFU; + } + + if (ret == 0) + { + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + } + if (ret == 0) + { + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + } + if (ret == 0) + { + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + } + if (ret == 0) + { + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1); + } + return ret; +} + +/** + * @brief Accelerometer user offset correction values in mg.[get] + * + * @param ctx read / write interface definitions + * @param val Accelerometer user offset correction values in mg. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_xl_offset_mg_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_xl_offset_mg_t *val) +{ + lsm6dsv16b_z_ofs_usr_t z_ofs_usr; + lsm6dsv16b_y_ofs_usr_t y_ofs_usr; + lsm6dsv16b_x_ofs_usr_t x_ofs_usr; + lsm6dsv16b_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + } + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + } + if (ret == 0) + { + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + } + + if (ctrl9.usr_off_w == PROPERTY_DISABLE) + { + val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.0078125f); + val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.0078125f); + val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.0078125f); + } + else + { + val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.125f); + val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.125f); + val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.125f); + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @addtogroup SenseWire (I3C) + * @brief This section group all the functions concerning the + * usage of SenseWire (I3C) + * @{ + * + */ + +/** + * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[set] + * + * @param ctx read / write interface definitions + * @param val SW_RST_DYN_ADDRESS_RST, GLOBAL_RST_, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_i3c_reset_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_i3c_reset_mode_t val) +{ + lsm6dsv16b_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret == 0) + { + pin_ctrl.ibhr_por_en = (uint8_t)val & 0x01U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[get] + * + * @param ctx read / write interface definitions + * @param val SW_RST_DYN_ADDRESS_RST, GLOBAL_RST_, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_i3c_reset_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_i3c_reset_mode_t *val) +{ + lsm6dsv16b_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + switch (pin_ctrl.ibhr_por_en) + { + case LSM6DSV16B_SW_RST_DYN_ADDRESS_RST: + *val = LSM6DSV16B_SW_RST_DYN_ADDRESS_RST; + break; + + case LSM6DSV16B_I3C_GLOBAL_RST: + *val = LSM6DSV16B_I3C_GLOBAL_RST; + break; + + default: + *val = LSM6DSV16B_SW_RST_DYN_ADDRESS_RST; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @addtogroup Time-Division Multiplexing (TDM) + * @brief This section group all the functions concerning the + * usage of Time-Division Multiplexing (TDM) + * @{ + * + */ + +/** + * @brief Disables pull-up on WCLK pin.[set] + * + * @param ctx read / write interface definitions + * @param val Disables pull-up on WCLK pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tdm_dis_wclk_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16b_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret == 0) + { + pin_ctrl.tdm_wclk_pu_dis = val; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Disables pull-up on WCLK pin.[get] + * + * @param ctx read / write interface definitions + * @param val Disables pull-up on WCLK pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tdm_dis_wclk_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16b_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + *val = pin_ctrl.tdm_wclk_pu_dis; + + return ret; +} + +/** + * @brief Enables pull-up on TDMout pin.[set] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on TDMout pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tdm_tdmout_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16b_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.tdm_out_pu_en = val; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Enables pull-up on TDMout pin.[get] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on TDMout pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tdm_tdmout_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16b_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1); + *val = if_cfg.tdm_out_pu_en; + + return ret; +} + +/** + * @brief WCLK and BCLK frequencies.[set] + * + * @param ctx read / write interface definitions + * @param val WCLK_8kHZ_1024kHz, WCLK_16kHZ_2048kHz, WCLK_8kHZ_2048kHz, WCLK_16kHZ_1024kHz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tdm_wclk_bclk_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_tdm_wclk_bclk_t val) +{ + lsm6dsv16b_tdm_cfg0_t tdm_cfg0; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + if (ret == 0) + { + tdm_cfg0.tdm_wclk_bclk_sel = ((uint8_t)val & 0x4U) >> 2; + tdm_cfg0.tdm_wclk = (uint8_t)val & 0x3U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + } + + return ret; +} + +/** + * @brief WCLK and BCLK frequencies.[get] + * + * @param ctx read / write interface definitions + * @param val WCLK_8kHZ_1024kHz, WCLK_16kHZ_2048kHz, WCLK_8kHZ_2048kHz, WCLK_16kHZ_1024kHz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tdm_wclk_bclk_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_tdm_wclk_bclk_t *val) +{ + lsm6dsv16b_tdm_cfg0_t tdm_cfg0; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + switch ((tdm_cfg0.tdm_wclk_bclk_sel << 2) + tdm_cfg0.tdm_wclk) + { + case LSM6DSV16B_WCLK_16kHZ_BCLK_2048kHz: + *val = LSM6DSV16B_WCLK_16kHZ_BCLK_2048kHz; + break; + + case LSM6DSV16B_WCLK_8kHZ_BCLK_2048kHz: + *val = LSM6DSV16B_WCLK_8kHZ_BCLK_2048kHz; + break; + + default: + *val = LSM6DSV16B_WCLK_8kHZ_BCLK_2048kHz; + break; + } + return ret; +} + +/** + * @brief Selection of TDM slot for transmission.[set] + * + * @param ctx read / write interface definitions + * @param val SLOT_012, SLOT_456, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tdm_slot_set(const stmdev_ctx_t *ctx, lsm6dsv16b_tdm_slot_t val) +{ + lsm6dsv16b_tdm_cfg0_t tdm_cfg0; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + if (ret == 0) + { + tdm_cfg0.tdm_slot_sel = (uint8_t)val & 0x01U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + } + + return ret; +} + +/** + * @brief Selection of TDM slot for transmission.[get] + * + * @param ctx read / write interface definitions + * @param val SLOT_012, SLOT_456, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tdm_slot_get(const stmdev_ctx_t *ctx, lsm6dsv16b_tdm_slot_t *val) +{ + lsm6dsv16b_tdm_cfg0_t tdm_cfg0; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + switch (tdm_cfg0.tdm_slot_sel) + { + case LSM6DSV16B_SLOT_012: + *val = LSM6DSV16B_SLOT_012; + break; + + case LSM6DSV16B_SLOT_456: + *val = LSM6DSV16B_SLOT_456; + break; + + default: + *val = LSM6DSV16B_SLOT_012; + break; + } + return ret; +} + +/** + * @brief BCLK edge selection for TDM interface.[set] + * + * @param ctx read / write interface definitions + * @param val BCLK_RISING, BCLK_FALLING, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tdm_bclk_edge_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_tdm_bclk_edge_t val) +{ + lsm6dsv16b_tdm_cfg0_t tdm_cfg0; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + if (ret == 0) + { + tdm_cfg0.tdm_bclk_edge_sel = (uint8_t)val & 0x01U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + } + + return ret; +} + +/** + * @brief BCLK edge selection for TDM interface.[get] + * + * @param ctx read / write interface definitions + * @param val BCLK_RISING, BCLK_FALLING, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tdm_bclk_edge_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_tdm_bclk_edge_t *val) +{ + lsm6dsv16b_tdm_cfg0_t tdm_cfg0; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + switch (tdm_cfg0.tdm_bclk_edge_sel) + { + case LSM6DSV16B_BCLK_RISING: + *val = LSM6DSV16B_BCLK_RISING; + break; + + case LSM6DSV16B_BCLK_FALLING: + *val = LSM6DSV16B_BCLK_FALLING; + break; + + default: + *val = LSM6DSV16B_BCLK_RISING; + break; + } + return ret; +} + +/** + * @brief Enables TDM delayed configuration.[set] + * + * @param ctx read / write interface definitions + * @param val Enables TDM delayed configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tdm_delayed_conf_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16b_tdm_cfg0_t tdm_cfg0; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + if (ret == 0) + { + tdm_cfg0.tdm_delayed_cfg = val; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + } + + return ret; +} + +/** + * @brief Enables TDM delayed configuration.[get] + * + * @param ctx read / write interface definitions + * @param val Enables TDM delayed configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tdm_delayed_conf_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16b_tdm_cfg0_t tdm_cfg0; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1); + *val = tdm_cfg0.tdm_delayed_cfg; + + return ret; +} + + +/** + * @brief Selects order of transmission of TDM axes.[set] + * + * @param ctx read / write interface definitions + * @param val TDM_ORDER_ZYX, TDM_ORDER_XZY, TDM_ORDER_XYZ, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tdm_axis_order_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_tdm_axis_order_t val) +{ + lsm6dsv16b_tdm_cfg1_t tdm_cfg1; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1); + if (ret == 0) + { + tdm_cfg1.tdm_axes_ord_sel = (uint8_t)val & 0x03U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1); + } + + return ret; +} + +/** + * @brief Selects order of transmission of TDM axes.[get] + * + * @param ctx read / write interface definitions + * @param val TDM_ORDER_ZYX, TDM_ORDER_XZY, TDM_ORDER_XYZ, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tdm_axis_order_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_tdm_axis_order_t *val) +{ + lsm6dsv16b_tdm_cfg1_t tdm_cfg1; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1); + switch (tdm_cfg1.tdm_axes_ord_sel) + { + case LSM6DSV16B_TDM_ORDER_ZYX: + *val = LSM6DSV16B_TDM_ORDER_ZYX; + break; + + case LSM6DSV16B_TDM_ORDER_XZY: + *val = LSM6DSV16B_TDM_ORDER_XZY; + break; + + case LSM6DSV16B_TDM_ORDER_XYZ: + *val = LSM6DSV16B_TDM_ORDER_XYZ; + break; + + default: + *val = LSM6DSV16B_TDM_ORDER_ZYX; + break; + } + return ret; +} + +/** + * @brief TDM channel accelerometer full-scale selection.[set] + * + * @param ctx read / write interface definitions + * @param val TDM_2g, TDM_4g, TDM_8g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tdm_xl_full_scale_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_tdm_xl_full_scale_t val) +{ + lsm6dsv16b_tdm_cfg2_t tdm_cfg2; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1); + if (ret == 0) + { + tdm_cfg2.tdm_fs_xl = (uint8_t)val & 0x3U; + ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1); + } + + return ret; +} + +/** + * @brief TDM channel accelerometer full-scale selection.[get] + * + * @param ctx read / write interface definitions + * @param val TDM_2g, TDM_4g, TDM_8g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16b_tdm_xl_full_scale_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_tdm_xl_full_scale_t *val) +{ + lsm6dsv16b_tdm_cfg2_t tdm_cfg2; + int32_t ret; + + ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1); + switch (tdm_cfg2.tdm_fs_xl) + { + case LSM6DSV16B_TDM_2g: + *val = LSM6DSV16B_TDM_2g; + break; + + case LSM6DSV16B_TDM_4g: + *val = LSM6DSV16B_TDM_4g; + break; + + case LSM6DSV16B_TDM_8g: + *val = LSM6DSV16B_TDM_8g; + break; + + default: + *val = LSM6DSV16B_TDM_2g; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @} + * + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dsv16b_STdC/driver/lsm6dsv16b_reg.h b/sensor/stmemsc/lsm6dsv16b_STdC/driver/lsm6dsv16b_reg.h new file mode 100644 index 00000000..9fa768bc --- /dev/null +++ b/sensor/stmemsc/lsm6dsv16b_STdC/driver/lsm6dsv16b_reg.h @@ -0,0 +1,3408 @@ +/** + ****************************************************************************** + * @file lsm6dsv16b_reg.h + * @author Sensors Software Solution Team + * @brief This file contains all the functions prototypes for the + * lsm6dsv16b_reg.c driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2024 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef LSM6DSV16B_REGS_H +#define LSM6DSV16B_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include + +/** @addtogroup LSM6DSV16B + * @{ + * + */ + +/** @defgroup Endianness definitions + * @{ + * + */ + +#ifndef DRV_BYTE_ORDER +#ifndef __BYTE_ORDER__ + +#define DRV_LITTLE_ENDIAN 1234 +#define DRV_BIG_ENDIAN 4321 + +/** if _BYTE_ORDER is not defined, choose the endianness of your architecture + * by uncommenting the define which fits your platform endianness + */ +//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN +#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN + +#else /* defined __BYTE_ORDER__ */ + +#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ +#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ +#define DRV_BYTE_ORDER __BYTE_ORDER__ + +#endif /* __BYTE_ORDER__*/ +#endif /* DRV_BYTE_ORDER */ + +/** + * @} + * + */ + +/** @defgroup STMicroelectronics sensors common types + * @{ + * + */ + +#ifndef MEMS_SHARED_TYPES +#define MEMS_SHARED_TYPES + +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} bitwise_t; + +#define PROPERTY_DISABLE (0U) +#define PROPERTY_ENABLE (1U) + +/** @addtogroup Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); +typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); + +typedef struct +{ + /** Component mandatory fields **/ + stmdev_write_ptr write_reg; + stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; + /** Customizable optional pointer **/ + void *handle; +} stmdev_ctx_t; + +/** + * @} + * + */ + +#endif /* MEMS_SHARED_TYPES */ + +#ifndef MEMS_UCF_SHARED_TYPES +#define MEMS_UCF_SHARED_TYPES + +/** @defgroup Generic address-data structure definition + * @brief This structure is useful to load a predefined configuration + * of a sensor. + * You can create a sensor configuration by your own or using + * Unico / Unicleo tools available on STMicroelectronics + * web site. + * + * @{ + * + */ + +typedef struct +{ + uint8_t address; + uint8_t data; +} ucf_line_t; + +/** + * @} + * + */ + +#endif /* MEMS_UCF_SHARED_TYPES */ + +/** + * @} + * + */ + +/** @defgroup LSM6DSV16B_Infos + * @{ + * + */ + +/** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ +#define LSM6DSV16B_I2C_ADD_L 0xD5U +#define LSM6DSV16B_I2C_ADD_H 0xD7U + +/** Device Identification (Who am I) **/ +#define LSM6DSV16B_ID 0x71U + +/** + * @} + * + */ + +/** @defgroup bitfields page main + * @{ + * + */ + +#define LSM6DSV16B_FUNC_CFG_ACCESS 0x1U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t sw_por : 1; + uint8_t fsm_wr_ctrl_en : 1; + uint8_t not_used1 : 3; + uint8_t emb_func_reg_access : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_reg_access : 1; + uint8_t not_used1 : 3; + uint8_t fsm_wr_ctrl_en : 1; + uint8_t sw_por : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_func_cfg_access_t; + +#define LSM6DSV16B_PIN_CTRL 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 5; + uint8_t ibhr_por_en : 1; + uint8_t sdo_pu_en : 1; + uint8_t tdm_wclk_pu_dis : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tdm_wclk_pu_dis : 1; + uint8_t sdo_pu_en : 1; + uint8_t ibhr_por_en : 1; + uint8_t not_used0 : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_pin_ctrl_t; + +#define LSM6DSV16B_IF_CFG 0x3U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t i2c_i3c_disable : 1; + uint8_t not_used0 : 1; + uint8_t sim : 1; + uint8_t pp_od : 1; + uint8_t h_lactive : 1; + uint8_t asf_ctrl : 1; + uint8_t tdm_out_pu_en : 1; + uint8_t sda_pu_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sda_pu_en : 1; + uint8_t tdm_out_pu_en : 1; + uint8_t asf_ctrl : 1; + uint8_t h_lactive : 1; + uint8_t pp_od : 1; + uint8_t sim : 1; + uint8_t not_used0 : 1; + uint8_t i2c_i3c_disable : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_if_cfg_t; + +#define LSM6DSV16B_FIFO_CTRL1 0x7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wtm : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t wtm : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fifo_ctrl1_t; + +#define LSM6DSV16B_FIFO_CTRL2 0x8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xl_dualc_batch_from_fsm : 1; + uint8_t uncompr_rate : 2; + uint8_t not_used0 : 1; + uint8_t odr_chg_en : 1; + uint8_t not_used1 : 1; + uint8_t fifo_compr_rt_en : 1; + uint8_t stop_on_wtm : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t stop_on_wtm : 1; + uint8_t fifo_compr_rt_en : 1; + uint8_t not_used1 : 1; + uint8_t odr_chg_en : 1; + uint8_t not_used0 : 1; + uint8_t uncompr_rate : 2; + uint8_t xl_dualc_batch_from_fsm : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fifo_ctrl2_t; + +#define LSM6DSV16B_FIFO_CTRL3 0x9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bdr_xl : 4; + uint8_t bdr_gy : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bdr_gy : 4; + uint8_t bdr_xl : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fifo_ctrl3_t; + +#define LSM6DSV16B_FIFO_CTRL4 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_mode : 3; + uint8_t not_used0 : 1; + uint8_t odr_t_batch : 2; + uint8_t dec_ts_batch : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dec_ts_batch : 2; + uint8_t odr_t_batch : 2; + uint8_t not_used0 : 1; + uint8_t fifo_mode : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fifo_ctrl4_t; + +#define LSM6DSV16B_COUNTER_BDR_REG1 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t cnt_bdr_th : 2; + uint8_t not_used0 : 3; + uint8_t trig_counter_bdr : 2; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t trig_counter_bdr : 2; + uint8_t not_used0 : 3; + uint8_t cnt_bdr_th : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_counter_bdr_reg1_t; + +#define LSM6DSV16B_COUNTER_BDR_REG2 0x0CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t cnt_bdr_th : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t cnt_bdr_th : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_counter_bdr_reg2_t; + +#define LSM6DSV16B_INT1_CTRL 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_drdy_xl : 1; + uint8_t int1_drdy_g : 1; + uint8_t not_used0 : 1; + uint8_t int1_fifo_th : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_fifo_full : 1; + uint8_t int1_cnt_bdr : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t int1_cnt_bdr : 1; + uint8_t int1_fifo_full : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_fifo_th : 1; + uint8_t not_used0 : 1; + uint8_t int1_drdy_g : 1; + uint8_t int1_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_int1_ctrl_t; + +#define LSM6DSV16B_INT2_CTRL 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_drdy_xl : 1; + uint8_t int2_drdy_g : 1; + uint8_t not_used0 : 1; + uint8_t int2_fifo_th : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_fifo_full : 1; + uint8_t int2_cnt_bdr : 1; + uint8_t int2_emb_func_endop : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_emb_func_endop : 1; + uint8_t int2_cnt_bdr : 1; + uint8_t int2_fifo_full : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_fifo_th : 1; + uint8_t not_used0 : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_int2_ctrl_t; + +#define LSM6DSV16B_WHO_AM_I 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t id : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t id : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_who_am_i_t; + +#define LSM6DSV16B_CTRL1 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t odr_xl : 4; + uint8_t op_mode_xl : 3; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t op_mode_xl : 3; + uint8_t odr_xl : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_ctrl1_t; + +#define LSM6DSV16B_CTRL2 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t odr_g : 4; + uint8_t op_mode_g : 3; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t op_mode_g : 3; + uint8_t odr_g : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_ctrl2_t; + +#define LSM6DSV16B_CTRL3 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sw_reset : 1; + uint8_t not_used0 : 1; + uint8_t if_inc : 1; + uint8_t not_used1 : 3; + uint8_t bdu : 1; + uint8_t boot : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t boot : 1; + uint8_t bdu : 1; + uint8_t not_used1 : 3; + uint8_t if_inc : 1; + uint8_t not_used0 : 1; + uint8_t sw_reset : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_ctrl3_t; + +#define LSM6DSV16B_CTRL4 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used1 : 1; + uint8_t drdy_pulsed : 1; + uint8_t int2_drdy_temp : 1; + uint8_t drdy_mask : 1; + uint8_t int2_on_int1 : 1; + uint8_t not_used0 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 3; + uint8_t int2_on_int1 : 1; + uint8_t drdy_mask : 1; + uint8_t int2_drdy_temp : 1; + uint8_t drdy_pulsed : 1; + uint8_t not_used1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_ctrl4_t; + +#define LSM6DSV16B_CTRL5 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int_en_i3c : 1; + uint8_t bus_act_sel : 2; + uint8_t not_used0 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 5; + uint8_t bus_act_sel : 2; + uint8_t int_en_i3c : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_ctrl5_t; + +#define LSM6DSV16B_CTRL6 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_g : 4; + uint8_t lpf1_g_bw : 3; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t lpf1_g_bw : 3; + uint8_t fs_g : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_ctrl6_t; + +#define LSM6DSV16B_CTRL7 0x16U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t lpf1_g_en : 1; + uint8_t not_used0 : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 7; + uint8_t lpf1_g_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_ctrl7_t; + +#define LSM6DSV16B_CTRL8 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_xl : 2; + uint8_t not_used0 : 1; + uint8_t xl_dualc_en : 1; + uint8_t not_used1 : 1; + uint8_t hp_lpf2_xl_bw : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t hp_lpf2_xl_bw : 3; + uint8_t not_used1 : 1; + uint8_t xl_dualc_en : 1; + uint8_t not_used0 : 1; + uint8_t fs_xl : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_ctrl8_t; + +#define LSM6DSV16B_CTRL9 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t usr_off_on_out : 1; + uint8_t usr_off_w : 1; + uint8_t not_used0 : 1; + uint8_t lpf2_xl_en : 1; + uint8_t hp_slope_xl_en : 1; + uint8_t xl_fastsettl_mode : 1; + uint8_t hp_ref_mode_xl : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t hp_ref_mode_xl : 1; + uint8_t xl_fastsettl_mode : 1; + uint8_t hp_slope_xl_en : 1; + uint8_t lpf2_xl_en : 1; + uint8_t not_used0 : 1; + uint8_t usr_off_w : 1; + uint8_t usr_off_on_out : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_ctrl9_t; + +#define LSM6DSV16B_CTRL10 0x19U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t st_xl : 2; + uint8_t st_g : 2; + uint8_t xl_st_offset : 1; + uint8_t not_used1 : 1; + uint8_t emb_func_debug : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t emb_func_debug : 1; + uint8_t not_used1 : 1; + uint8_t xl_st_offset : 1; + uint8_t st_g : 2; + uint8_t st_xl : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_ctrl10_t; + +#define LSM6DSV16B_CTRL_STATUS 0x1AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t fsm_wr_ctrl_status : 1; + uint8_t not_used1 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 5; + uint8_t fsm_wr_ctrl_status : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_ctrl_status_t; + +#define LSM6DSV16B_FIFO_STATUS1 0x1BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t diff_fifo : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t diff_fifo : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fifo_status1_t; + +#define LSM6DSV16B_FIFO_STATUS2 0x1CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t diff_fifo : 1; + uint8_t not_used0 : 2; + uint8_t fifo_ovr_latched : 1; + uint8_t counter_bdr_ia : 1; + uint8_t fifo_full_ia : 1; + uint8_t fifo_ovr_ia : 1; + uint8_t fifo_wtm_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_wtm_ia : 1; + uint8_t fifo_ovr_ia : 1; + uint8_t fifo_full_ia : 1; + uint8_t counter_bdr_ia : 1; + uint8_t fifo_ovr_latched : 1; + uint8_t not_used0 : 2; + uint8_t diff_fifo : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fifo_status2_t; + +#define LSM6DSV16B_ALL_INT_SRC 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ia : 1; + uint8_t wu_ia : 1; + uint8_t tap_ia : 1; + uint8_t not_used0 : 1; + uint8_t d6d_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t not_used1 : 1; + uint8_t emb_func_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_ia : 1; + uint8_t not_used1 : 1; + uint8_t sleep_change_ia : 1; + uint8_t d6d_ia : 1; + uint8_t not_used0 : 1; + uint8_t tap_ia : 1; + uint8_t wu_ia : 1; + uint8_t ff_ia : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_all_int_src_t; + +#define LSM6DSV16B_STATUS_REG 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xlda : 1; + uint8_t gda : 1; + uint8_t tda : 1; + uint8_t not_used0 : 4; + uint8_t timestamp_endcount : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp_endcount : 1; + uint8_t not_used0 : 4; + uint8_t tda : 1; + uint8_t gda : 1; + uint8_t xlda : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_status_reg_t; + +#define LSM6DSV16B_OUT_TEMP_L 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_out_temp_l_t; + +#define LSM6DSV16B_OUT_TEMP_H 0x21U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_out_temp_h_t; + +#define LSM6DSV16B_OUTX_L_G 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_outx_l_g_t; + +#define LSM6DSV16B_OUTX_H_G 0x23U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_outx_h_g_t; + +#define LSM6DSV16B_OUTY_L_G 0x24U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_outy_l_g_t; + +#define LSM6DSV16B_OUTY_H_G 0x25U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_outy_h_g_t; + +#define LSM6DSV16B_OUTZ_L_G 0x26U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_outz_l_g_t; + +#define LSM6DSV16B_OUTZ_H_G 0x27U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_outz_h_g_t; + +#define LSM6DSV16B_OUTZ_L_A 0x28U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_outz_l_a_t; + +#define LSM6DSV16B_OUTZ_H_A 0x29U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_outz_h_a_t; + +#define LSM6DSV16B_OUTY_L_A 0x2AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_outy_l_a_t; + +#define LSM6DSV16B_OUTY_H_A 0x2BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_outy_h_a_t; + +#define LSM6DSV16B_OUTX_L_A 0x2CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_outx_l_a_t; + +#define LSM6DSV16B_OUTX_H_A 0x2DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_outx_h_a_t; + +#define LSM6DSV16B_UI_OUTZ_L_A_DUALC 0x34U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outz_a_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outz_a_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_ui_outz_l_a_dualc_t; + +#define LSM6DSV16B_UI_OUTZ_H_A_DUALC 0x35U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outz_a_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outz_a_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_ui_outz_h_a_dualc_t; + +#define LSM6DSV16B_UI_OUTY_L_A_DUALC 0x36U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outy_a_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outy_a_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_ui_outy_l_a_dualc_t; + +#define LSM6DSV16B_UI_OUTY_H_A_DUALC 0x37U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outy_a_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outy_a_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_ui_outy_h_a_dualc_t; + +#define LSM6DSV16B_UI_OUTX_L_A_DUALC 0x38U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outx_a_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outx_a_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_ui_outx_l_a_dualc_t; + +#define LSM6DSV16B_UI_OUTX_H_A_DUALC 0x39U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outx_a_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outx_a_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_ui_outx_h_a_dualc_t; + +#define LSM6DSV16B_TIMESTAMP0 0x40U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_timestamp0_t; + +#define LSM6DSV16B_TIMESTAMP1 0x41U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_timestamp1_t; + +#define LSM6DSV16B_TIMESTAMP2 0x42U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_timestamp2_t; + +#define LSM6DSV16B_TIMESTAMP3 0x43U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_timestamp3_t; + +#define LSM6DSV16B_WAKE_UP_SRC 0x45U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t x_wu : 1; + uint8_t y_wu : 1; + uint8_t z_wu : 1; + uint8_t wu_ia : 1; + uint8_t sleep_state : 1; + uint8_t ff_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t sleep_change_ia : 1; + uint8_t ff_ia : 1; + uint8_t sleep_state : 1; + uint8_t wu_ia : 1; + uint8_t z_wu : 1; + uint8_t y_wu : 1; + uint8_t x_wu : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_wake_up_src_t; + +#define LSM6DSV16B_TAP_SRC 0x46U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t x_tap : 1; + uint8_t y_tap : 1; + uint8_t z_tap : 1; + uint8_t tap_sign : 1; + uint8_t not_used0 : 1; + uint8_t double_tap : 1; + uint8_t single_tap : 1; + uint8_t tap_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tap_ia : 1; + uint8_t single_tap : 1; + uint8_t double_tap : 1; + uint8_t not_used0 : 1; + uint8_t tap_sign : 1; + uint8_t z_tap : 1; + uint8_t y_tap : 1; + uint8_t x_tap : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_tap_src_t; + +#define LSM6DSV16B_D6D_SRC 0x47U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t zl : 1; + uint8_t zh : 1; + uint8_t yl : 1; + uint8_t yh : 1; + uint8_t xl : 1; + uint8_t xh : 1; + uint8_t d6d_ia : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t d6d_ia : 1; + uint8_t xh : 1; + uint8_t xl : 1; + uint8_t yh : 1; + uint8_t yl : 1; + uint8_t zh : 1; + uint8_t zl : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_d6d_src_t; + +#define LSM6DSV16B_EMB_FUNC_STATUS_MAINPAGE 0x49U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t is_step_det : 1; + uint8_t is_tilt : 1; + uint8_t is_sigmot : 1; + uint8_t not_used1 : 1; + uint8_t is_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t is_sigmot : 1; + uint8_t is_tilt : 1; + uint8_t is_step_det : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_emb_func_status_mainpage_t; + +#define LSM6DSV16B_FSM_STATUS_MAINPAGE 0x4AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm8 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fsm_status_mainpage_t; + +#define LSM6DSV16B_INTERNAL_FREQ 0x4FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t freq_fine : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t freq_fine : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_internal_freq_t; + +#define LSM6DSV16B_FUNCTIONS_ENABLE 0x50U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t inact_en : 2; + uint8_t not_used0 : 1; + uint8_t dis_rst_lir_all_int : 1; + uint8_t not_used1 : 2; + uint8_t timestamp_en : 1; + uint8_t interrupts_enable : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t interrupts_enable : 1; + uint8_t timestamp_en : 1; + uint8_t not_used1 : 2; + uint8_t dis_rst_lir_all_int : 1; + uint8_t not_used0 : 1; + uint8_t inact_en : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_functions_enable_t; + +#define LSM6DSV16B_INACTIVITY_DUR 0x54U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t inact_dur : 2; + uint8_t xl_inact_odr : 2; + uint8_t wu_inact_ths_w : 3; + uint8_t sleep_status_on_int : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sleep_status_on_int : 1; + uint8_t wu_inact_ths_w : 3; + uint8_t xl_inact_odr : 2; + uint8_t inact_dur : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_inactivity_dur_t; + +#define LSM6DSV16B_INACTIVITY_THS 0x55U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t inact_ths : 6; + uint8_t not_used0 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 2; + uint8_t inact_ths : 6; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_inactivity_ths_t; + +#define LSM6DSV16B_TAP_CFG0 0x56U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t lir : 1; + uint8_t tap_x_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_z_en : 1; + uint8_t slope_fds : 1; + uint8_t hw_func_mask_xl_settl : 1; + uint8_t low_pass_on_6d : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t low_pass_on_6d : 1; + uint8_t hw_func_mask_xl_settl : 1; + uint8_t slope_fds : 1; + uint8_t tap_z_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_x_en : 1; + uint8_t lir : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_tap_cfg0_t; + +#define LSM6DSV16B_TAP_CFG1 0x57U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths_z : 5; + uint8_t tap_priority : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tap_priority : 3; + uint8_t tap_ths_z : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_tap_cfg1_t; + +#define LSM6DSV16B_TAP_CFG2 0x58U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths_y : 5; + uint8_t not_used0 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 3; + uint8_t tap_ths_y : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_tap_cfg2_t; + +#define LSM6DSV16B_TAP_THS_6D 0x59U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths_x : 5; + uint8_t sixd_ths : 2; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t sixd_ths : 2; + uint8_t tap_ths_x : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_tap_ths_6d_t; + +#define LSM6DSV16B_TAP_DUR 0x5AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t shock : 2; + uint8_t quiet : 2; + uint8_t dur : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dur : 4; + uint8_t quiet : 2; + uint8_t shock : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_tap_dur_t; + +#define LSM6DSV16B_WAKE_UP_THS 0x5BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wk_ths : 6; + uint8_t usr_off_on_wu : 1; + uint8_t single_double_tap : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t single_double_tap : 1; + uint8_t usr_off_on_wu : 1; + uint8_t wk_ths : 6; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_wake_up_ths_t; + +#define LSM6DSV16B_WAKE_UP_DUR 0x5CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sleep_dur : 4; + uint8_t not_used0 : 1; + uint8_t wake_dur : 2; + uint8_t ff_dur : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 1; + uint8_t wake_dur : 2; + uint8_t not_used0 : 1; + uint8_t sleep_dur : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_wake_up_dur_t; + +#define LSM6DSV16B_FREE_FALL 0x5DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ths : 3; + uint8_t ff_dur : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 5; + uint8_t ff_ths : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_free_fall_t; + +#define LSM6DSV16B_MD1_CFG 0x5EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t int1_emb_func : 1; + uint8_t int1_6d : 1; + uint8_t int1_double_tap : 1; + uint8_t int1_ff : 1; + uint8_t int1_wu : 1; + uint8_t int1_single_tap : 1; + uint8_t int1_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_sleep_change : 1; + uint8_t int1_single_tap : 1; + uint8_t int1_wu : 1; + uint8_t int1_ff : 1; + uint8_t int1_double_tap : 1; + uint8_t int1_6d : 1; + uint8_t int1_emb_func : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_md1_cfg_t; + +#define LSM6DSV16B_MD2_CFG 0x5FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_timestamp : 1; + uint8_t int2_emb_func : 1; + uint8_t int2_6d : 1; + uint8_t int2_double_tap : 1; + uint8_t int2_ff : 1; + uint8_t int2_wu : 1; + uint8_t int2_single_tap : 1; + uint8_t int2_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_sleep_change : 1; + uint8_t int2_single_tap : 1; + uint8_t int2_wu : 1; + uint8_t int2_ff : 1; + uint8_t int2_double_tap : 1; + uint8_t int2_6d : 1; + uint8_t int2_emb_func : 1; + uint8_t int2_timestamp : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_md2_cfg_t; + +#define LSM6DSV16B_EMB_FUNC_CFG 0x63U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t emb_func_disable : 1; + uint8_t emb_func_irq_mask_xl_settl : 1; + uint8_t emb_func_irq_mask_g_settl : 1; + uint8_t not_used1 : 1; + uint8_t xl_dualc_batch_from_if : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t xl_dualc_batch_from_if : 1; + uint8_t not_used1 : 1; + uint8_t emb_func_irq_mask_g_settl : 1; + uint8_t emb_func_irq_mask_xl_settl : 1; + uint8_t emb_func_disable : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_emb_func_cfg_t; + +#define LSM6DSV16B_TDM_CFG0 0x6CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tdm_wclk_bclk_sel : 1; + uint8_t tdm_wclk : 2; + uint8_t not_used0 : 1; + uint8_t tdm_slot_sel : 1; + uint8_t tdm_bclk_edge_sel : 1; + uint8_t tdm_delayed_cfg : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t tdm_delayed_cfg : 1; + uint8_t tdm_bclk_edge_sel : 1; + uint8_t tdm_slot_sel : 1; + uint8_t not_used0 : 1; + uint8_t tdm_wclk : 2; + uint8_t tdm_wclk_bclk_sel : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_tdm_cfg0_t; + +#define LSM6DSV16B_TDM_CFG1 0x6DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t tdm_axes_ord_sel : 2; + uint8_t tdm_xl_z_en : 1; + uint8_t tdm_xl_y_en : 1; + uint8_t tdm_xl_x_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tdm_xl_x_en : 1; + uint8_t tdm_xl_y_en : 1; + uint8_t tdm_xl_z_en : 1; + uint8_t tdm_axes_ord_sel : 2; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_tdm_cfg1_t; + +#define LSM6DSV16B_TDM_CFG2 0x6EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tdm_fs_xl : 2; + uint8_t not_used0 : 1; + uint8_t tdm_data_mask : 1; + uint8_t not_used1 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 4; + uint8_t tdm_data_mask : 1; + uint8_t not_used0 : 1; + uint8_t tdm_fs_xl : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_tdm_cfg2_t; + +#define LSM6DSV16B_Z_OFS_USR 0x73U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t z_ofs_usr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t z_ofs_usr : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_z_ofs_usr_t; + +#define LSM6DSV16B_Y_OFS_USR 0x74U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t y_ofs_usr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t y_ofs_usr : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_y_ofs_usr_t; + +#define LSM6DSV16B_X_OFS_USR 0x75U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t x_ofs_usr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t x_ofs_usr : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_x_ofs_usr_t; + +#define LSM6DSV16B_FIFO_DATA_OUT_TAG 0x78U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t tag_cnt : 2; + uint8_t tag_sensor : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tag_sensor : 5; + uint8_t tag_cnt : 2; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fifo_data_out_tag_t; + +#define LSM6DSV16B_FIFO_DATA_OUT_BYTE_0 0x79U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fifo_data_out_byte_0_t; + +#define LSM6DSV16B_FIFO_DATA_OUT_BYTE_1 0x7AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fifo_data_out_byte_1_t; + +#define LSM6DSV16B_FIFO_DATA_OUT_BYTE_2 0x7BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fifo_data_out_byte_2_t; + +#define LSM6DSV16B_FIFO_DATA_OUT_BYTE_3 0x7CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fifo_data_out_byte_3_t; + +#define LSM6DSV16B_FIFO_DATA_OUT_BYTE_4 0x7DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fifo_data_out_byte_4_t; + +#define LSM6DSV16B_FIFO_DATA_OUT_BYTE_5 0x7EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fifo_data_out_byte_5_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page embedded + * @{ + * + */ + +#define LSM6DSV16B_PAGE_SEL 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t page_sel : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_sel : 4; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_page_sel_t; + +#define LSM6DSV16B_EMB_FUNC_EN_A 0x4U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used2 : 1; + uint8_t sflp_game_en : 1; + uint8_t not_used0 : 1; + uint8_t pedo_en : 1; + uint8_t tilt_en : 1; + uint8_t sign_motion_en : 1; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t sign_motion_en : 1; + uint8_t tilt_en : 1; + uint8_t pedo_en : 1; + uint8_t not_used0 : 1; + uint8_t sflp_game_en : 1; + uint8_t not_used2 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_emb_func_en_a_t; + +#define LSM6DSV16B_EMB_FUNC_EN_B 0x5U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_en : 1; + uint8_t not_used0 : 2; + uint8_t fifo_compr_en : 1; + uint8_t not_used1 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 4; + uint8_t fifo_compr_en : 1; + uint8_t not_used0 : 2; + uint8_t fsm_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_emb_func_en_b_t; + +#define LSM6DSV16B_EMB_FUNC_EXEC_STATUS 0x7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t emb_func_endop : 1; + uint8_t emb_func_exec_ovr : 1; + uint8_t not_used0 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 6; + uint8_t emb_func_exec_ovr : 1; + uint8_t emb_func_endop : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_emb_func_exec_status_t; + +#define LSM6DSV16B_PAGE_ADDRESS 0x8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t page_addr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_addr : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_page_address_t; + +#define LSM6DSV16B_PAGE_VALUE 0x9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t page_value : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_value : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_page_value_t; + +#define LSM6DSV16B_EMB_FUNC_INT1 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t int1_step_detector : 1; + uint8_t int1_tilt : 1; + uint8_t int1_sig_mot : 1; + uint8_t not_used1 : 1; + uint8_t int1_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t int1_sig_mot : 1; + uint8_t int1_tilt : 1; + uint8_t int1_step_detector : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_emb_func_int1_t; + +#define LSM6DSV16B_FSM_INT1 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_fsm1 : 1; + uint8_t int1_fsm2 : 1; + uint8_t int1_fsm3 : 1; + uint8_t int1_fsm4 : 1; + uint8_t int1_fsm5 : 1; + uint8_t int1_fsm6 : 1; + uint8_t int1_fsm7 : 1; + uint8_t int1_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm8 : 1; + uint8_t int1_fsm7 : 1; + uint8_t int1_fsm6 : 1; + uint8_t int1_fsm5 : 1; + uint8_t int1_fsm4 : 1; + uint8_t int1_fsm3 : 1; + uint8_t int1_fsm2 : 1; + uint8_t int1_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fsm_int1_t; + +#define LSM6DSV16B_EMB_FUNC_INT2 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t int2_step_detector : 1; + uint8_t int2_tilt : 1; + uint8_t int2_sig_mot : 1; + uint8_t not_used1 : 1; + uint8_t int2_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t int2_sig_mot : 1; + uint8_t int2_tilt : 1; + uint8_t int2_step_detector : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_emb_func_int2_t; + +#define LSM6DSV16B_FSM_INT2 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_fsm1 : 1; + uint8_t int2_fsm2 : 1; + uint8_t int2_fsm3 : 1; + uint8_t int2_fsm4 : 1; + uint8_t int2_fsm5 : 1; + uint8_t int2_fsm6 : 1; + uint8_t int2_fsm7 : 1; + uint8_t int2_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm8 : 1; + uint8_t int2_fsm7 : 1; + uint8_t int2_fsm6 : 1; + uint8_t int2_fsm5 : 1; + uint8_t int2_fsm4 : 1; + uint8_t int2_fsm3 : 1; + uint8_t int2_fsm2 : 1; + uint8_t int2_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fsm_int2_t; + +#define LSM6DSV16B_EMB_FUNC_STATUS 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t is_step_det : 1; + uint8_t is_tilt : 1; + uint8_t is_sigmot : 1; + uint8_t not_used1 : 1; + uint8_t is_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t is_sigmot : 1; + uint8_t is_tilt : 1; + uint8_t is_step_det : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_emb_func_status_t; + +#define LSM6DSV16B_FSM_STATUS 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm8 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fsm_status_t; + +#define LSM6DSV16B_PAGE_RW 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 5; + uint8_t page_read : 1; + uint8_t page_write : 1; + uint8_t emb_func_lir : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_lir : 1; + uint8_t page_write : 1; + uint8_t page_read : 1; + uint8_t not_used0 : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_page_rw_t; + +#define LSM6DSV16B_EMB_FUNC_FIFO_EN_A 0x44U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t sflp_game_fifo_en : 1; + uint8_t not_used1 : 2; + uint8_t sflp_gravity_fifo_en : 1; + uint8_t sflp_gbias_fifo_en : 1; + uint8_t step_counter_fifo_en : 1; + uint8_t not_used2 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used2 : 1; + uint8_t step_counter_fifo_en : 1; + uint8_t sflp_gbias_fifo_en : 1; + uint8_t sflp_gravity_fifo_en : 1; + uint8_t not_used1 : 2; + uint8_t sflp_game_fifo_en : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_emb_func_fifo_en_a_t; + +#define LSM6DSV16B_FSM_ENABLE 0x46U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm1_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm8_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm8_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm1_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fsm_enable_t; + +#define LSM6DSV16B_FSM_LONG_COUNTER_L 0x48U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fsm_long_counter_l_t; + +#define LSM6DSV16B_FSM_LONG_COUNTER_H 0x49U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fsm_long_counter_h_t; + +#define LSM6DSV16B_INT_ACK_MASK 0x4BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t iack_mask : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t iack_mask : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_int_ack_mask_t; + +#define LSM6DSV16B_FSM_OUTS1 0x4CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm1_n_v : 1; + uint8_t fsm1_p_v : 1; + uint8_t fsm1_n_3 : 1; + uint8_t fsm1_p_3 : 1; + uint8_t fsm1_n_2 : 1; + uint8_t fsm1_p_2 : 1; + uint8_t fsm1_n_1 : 1; + uint8_t fsm1_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm1_p_1 : 1; + uint8_t fsm1_n_1 : 1; + uint8_t fsm1_p_2 : 1; + uint8_t fsm1_n_2 : 1; + uint8_t fsm1_p_3 : 1; + uint8_t fsm1_n_3 : 1; + uint8_t fsm1_p_v : 1; + uint8_t fsm1_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fsm_outs1_t; + +#define LSM6DSV16B_FSM_OUTS2 0x4DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm2_n_v : 1; + uint8_t fsm2_p_v : 1; + uint8_t fsm2_n_3 : 1; + uint8_t fsm2_p_3 : 1; + uint8_t fsm2_n_2 : 1; + uint8_t fsm2_p_2 : 1; + uint8_t fsm2_n_1 : 1; + uint8_t fsm2_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm2_p_1 : 1; + uint8_t fsm2_n_1 : 1; + uint8_t fsm2_p_2 : 1; + uint8_t fsm2_n_2 : 1; + uint8_t fsm2_p_3 : 1; + uint8_t fsm2_n_3 : 1; + uint8_t fsm2_p_v : 1; + uint8_t fsm2_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fsm_outs2_t; + +#define LSM6DSV16B_FSM_OUTS3 0x4EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm3_n_v : 1; + uint8_t fsm3_p_v : 1; + uint8_t fsm3_n_3 : 1; + uint8_t fsm3_p_3 : 1; + uint8_t fsm3_n_2 : 1; + uint8_t fsm3_p_2 : 1; + uint8_t fsm3_n_1 : 1; + uint8_t fsm3_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm3_p_1 : 1; + uint8_t fsm3_n_1 : 1; + uint8_t fsm3_p_2 : 1; + uint8_t fsm3_n_2 : 1; + uint8_t fsm3_p_3 : 1; + uint8_t fsm3_n_3 : 1; + uint8_t fsm3_p_v : 1; + uint8_t fsm3_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fsm_outs3_t; + +#define LSM6DSV16B_FSM_OUTS4 0x4FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm4_n_v : 1; + uint8_t fsm4_p_v : 1; + uint8_t fsm4_n_3 : 1; + uint8_t fsm4_p_3 : 1; + uint8_t fsm4_n_2 : 1; + uint8_t fsm4_p_2 : 1; + uint8_t fsm4_n_1 : 1; + uint8_t fsm4_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm4_p_1 : 1; + uint8_t fsm4_n_1 : 1; + uint8_t fsm4_p_2 : 1; + uint8_t fsm4_n_2 : 1; + uint8_t fsm4_p_3 : 1; + uint8_t fsm4_n_3 : 1; + uint8_t fsm4_p_v : 1; + uint8_t fsm4_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fsm_outs4_t; + +#define LSM6DSV16B_FSM_OUTS5 0x50U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm5_n_v : 1; + uint8_t fsm5_p_v : 1; + uint8_t fsm5_n_3 : 1; + uint8_t fsm5_p_3 : 1; + uint8_t fsm5_n_2 : 1; + uint8_t fsm5_p_2 : 1; + uint8_t fsm5_n_1 : 1; + uint8_t fsm5_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm5_p_1 : 1; + uint8_t fsm5_n_1 : 1; + uint8_t fsm5_p_2 : 1; + uint8_t fsm5_n_2 : 1; + uint8_t fsm5_p_3 : 1; + uint8_t fsm5_n_3 : 1; + uint8_t fsm5_p_v : 1; + uint8_t fsm5_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fsm_outs5_t; + +#define LSM6DSV16B_FSM_OUTS6 0x51U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm6_n_v : 1; + uint8_t fsm6_p_v : 1; + uint8_t fsm6_n_3 : 1; + uint8_t fsm6_p_3 : 1; + uint8_t fsm6_n_2 : 1; + uint8_t fsm6_p_2 : 1; + uint8_t fsm6_n_1 : 1; + uint8_t fsm6_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm6_p_1 : 1; + uint8_t fsm6_n_1 : 1; + uint8_t fsm6_p_2 : 1; + uint8_t fsm6_n_2 : 1; + uint8_t fsm6_p_3 : 1; + uint8_t fsm6_n_3 : 1; + uint8_t fsm6_p_v : 1; + uint8_t fsm6_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fsm_outs6_t; + +#define LSM6DSV16B_FSM_OUTS7 0x52U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm7_n_v : 1; + uint8_t fsm7_p_v : 1; + uint8_t fsm7_n_3 : 1; + uint8_t fsm7_p_3 : 1; + uint8_t fsm7_n_2 : 1; + uint8_t fsm7_p_2 : 1; + uint8_t fsm7_n_1 : 1; + uint8_t fsm7_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm7_p_1 : 1; + uint8_t fsm7_n_1 : 1; + uint8_t fsm7_p_2 : 1; + uint8_t fsm7_n_2 : 1; + uint8_t fsm7_p_3 : 1; + uint8_t fsm7_n_3 : 1; + uint8_t fsm7_p_v : 1; + uint8_t fsm7_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fsm_outs7_t; + +#define LSM6DSV16B_FSM_OUTS8 0x53U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm8_n_v : 1; + uint8_t fsm8_p_v : 1; + uint8_t fsm8_n_3 : 1; + uint8_t fsm8_p_3 : 1; + uint8_t fsm8_n_2 : 1; + uint8_t fsm8_p_2 : 1; + uint8_t fsm8_n_1 : 1; + uint8_t fsm8_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm8_p_1 : 1; + uint8_t fsm8_n_1 : 1; + uint8_t fsm8_p_2 : 1; + uint8_t fsm8_n_2 : 1; + uint8_t fsm8_p_3 : 1; + uint8_t fsm8_n_3 : 1; + uint8_t fsm8_p_v : 1; + uint8_t fsm8_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fsm_outs8_t; + +#define LSM6DSV16B_SFLP_ODR 0x5EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t sflp_game_odr : 3; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t sflp_game_odr : 3; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_sflp_odr_t; + +#define LSM6DSV16B_FSM_ODR 0x5FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t fsm_odr : 3; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t fsm_odr : 3; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fsm_odr_t; + +#define LSM6DSV16B_STEP_COUNTER_L 0x62U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t step : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_step_counter_l_t; + +#define LSM6DSV16B_STEP_COUNTER_H 0x63U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t step : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_step_counter_h_t; + +#define LSM6DSV16B_EMB_FUNC_SRC 0x64U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t stepcounter_bit_set : 1; + uint8_t step_overflow : 1; + uint8_t step_count_delta_ia : 1; + uint8_t step_detected : 1; + uint8_t not_used1 : 1; + uint8_t pedo_rst_step : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pedo_rst_step : 1; + uint8_t not_used1 : 1; + uint8_t step_detected : 1; + uint8_t step_count_delta_ia : 1; + uint8_t step_overflow : 1; + uint8_t stepcounter_bit_set : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_emb_func_src_t; + +#define LSM6DSV16B_EMB_FUNC_INIT_A 0x66U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t sflp_game_init : 1; + uint8_t not_used2 : 1; + uint8_t step_det_init : 1; + uint8_t tilt_init : 1; + uint8_t sig_mot_init : 1; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t not_used1 : 1; + uint8_t sig_mot_init : 1; + uint8_t tilt_init : 1; + uint8_t step_det_init : 1; + uint8_t not_used2 : 1; + uint8_t sflp_game_init : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_emb_func_init_a_t; + +#define LSM6DSV16B_EMB_FUNC_INIT_B 0x67U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_init : 1; + uint8_t not_used0 : 2; + uint8_t fifo_compr_init : 1; + uint8_t not_used1 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 4; + uint8_t fifo_compr_init : 1; + uint8_t not_used0 : 2; + uint8_t fsm_init : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_emb_func_init_b_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page pg0_emb_adv + * @{ + * + */ +#define LSM6DSV16B_EMB_ADV_PG_0 0x000 + +#define LSM6DSV16B_SFLP_GAME_GBIASX_L 0x6EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasx : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_sflp_game_gbiasx_l_t; + +#define LSM6DSV16B_SFLP_GAME_GBIASX_H 0x6FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasx : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_sflp_game_gbiasx_h_t; + +#define LSM6DSV16B_SFLP_GAME_GBIASY_L 0x70U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasy : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_sflp_game_gbiasy_l_t; + +#define LSM6DSV16B_SFLP_GAME_GBIASY_H 0x71U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasy : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_sflp_game_gbiasy_h_t; + +#define LSM6DSV16B_SFLP_GAME_GBIASZ_L 0x72U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_sflp_game_gbiasz_l_t; + +#define LSM6DSV16B_SFLP_GAME_GBIASZ_H 0x73U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_sflp_game_gbiasz_h_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page pg1_emb_adv + * @{ + * + */ + +#define LSM6DSV16B_EMB_ADV_PG_1 0x001 + +#define LSM6DSV16B_FSM_LC_TIMEOUT_L 0x17AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc_timeout : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc_timeout : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fsm_lc_timeout_l_t; + +#define LSM6DSV16B_FSM_LC_TIMEOUT_H 0x17BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc_timeout : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc_timeout : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fsm_lc_timeout_h_t; + +#define LSM6DSV16B_FSM_PROGRAMS 0x17CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_n_prog : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_n_prog : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fsm_programs_t; + +#define LSM6DSV16B_FSM_START_ADD_L 0x17EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_start : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_start : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fsm_start_add_l_t; + +#define LSM6DSV16B_FSM_START_ADD_H 0x17FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_start : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_start : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_fsm_start_add_h_t; + +#define LSM6DSV16B_PEDO_CMD_REG 0x183U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t fp_rejection_en : 1; + uint8_t carry_count_en : 1; + uint8_t not_used1 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 4; + uint8_t carry_count_en : 1; + uint8_t fp_rejection_en : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_pedo_cmd_reg_t; + +#define LSM6DSV16B_PEDO_DEB_STEPS_CONF 0x184U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t deb_step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t deb_step : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_pedo_deb_steps_conf_t; + +#define LSM6DSV16B_PEDO_SC_DELTAT_L 0x1D0U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t pd_sc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pd_sc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_pedo_sc_deltat_l_t; + +#define LSM6DSV16B_PEDO_SC_DELTAT_H 0x1D1U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t pd_sc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pd_sc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv16b_pedo_sc_deltat_h_t; + +/** + * @} + * + */ + +#define LSM6DSV16B_START_FSM_ADD 0x035CU + +/** + * @defgroup LSM6DSV16B_Register_Union + * @brief These unions group all the registers having a bit-field + * description. + * These unions are useful but it's not needed by the driver. + * + * REMOVING this unions you are compliant with: + * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " + * + * @{ + * + */ +typedef union +{ + lsm6dsv16b_func_cfg_access_t func_cfg_access; + lsm6dsv16b_pin_ctrl_t pin_ctrl; + lsm6dsv16b_if_cfg_t if_cfg; + lsm6dsv16b_fifo_ctrl1_t fifo_ctrl1; + lsm6dsv16b_fifo_ctrl2_t fifo_ctrl2; + lsm6dsv16b_fifo_ctrl3_t fifo_ctrl3; + lsm6dsv16b_fifo_ctrl4_t fifo_ctrl4; + lsm6dsv16b_counter_bdr_reg1_t counter_bdr_reg1; + lsm6dsv16b_counter_bdr_reg2_t counter_bdr_reg2; + lsm6dsv16b_int1_ctrl_t int1_ctrl; + lsm6dsv16b_int2_ctrl_t int2_ctrl; + lsm6dsv16b_who_am_i_t who_am_i; + lsm6dsv16b_ctrl1_t ctrl1; + lsm6dsv16b_ctrl2_t ctrl2; + lsm6dsv16b_ctrl3_t ctrl3; + lsm6dsv16b_ctrl4_t ctrl4; + lsm6dsv16b_ctrl5_t ctrl5; + lsm6dsv16b_ctrl6_t ctrl6; + lsm6dsv16b_ctrl7_t ctrl7; + lsm6dsv16b_ctrl8_t ctrl8; + lsm6dsv16b_ctrl9_t ctrl9; + lsm6dsv16b_ctrl10_t ctrl10; + lsm6dsv16b_fifo_status1_t fifo_status1; + lsm6dsv16b_fifo_status2_t fifo_status2; + lsm6dsv16b_all_int_src_t all_int_src; + lsm6dsv16b_status_reg_t status_reg; + lsm6dsv16b_out_temp_l_t out_temp_l; + lsm6dsv16b_out_temp_h_t out_temp_h; + lsm6dsv16b_outx_l_g_t outx_l_g; + lsm6dsv16b_outx_h_g_t outx_h_g; + lsm6dsv16b_outy_l_g_t outy_l_g; + lsm6dsv16b_outy_h_g_t outy_h_g; + lsm6dsv16b_outz_l_g_t outz_l_g; + lsm6dsv16b_outz_h_g_t outz_h_g; + lsm6dsv16b_outz_l_a_t outz_l_a; + lsm6dsv16b_outz_h_a_t outz_h_a; + lsm6dsv16b_outy_l_a_t outy_l_a; + lsm6dsv16b_outy_h_a_t outy_h_a; + lsm6dsv16b_outx_l_a_t outx_l_a; + lsm6dsv16b_outx_h_a_t outx_h_a; + lsm6dsv16b_ui_outz_l_a_dualc_t ui_outz_l_a_dualc; + lsm6dsv16b_ui_outz_h_a_dualc_t ui_outz_h_a_dualc; + lsm6dsv16b_ui_outy_l_a_dualc_t ui_outy_l_a_dualc; + lsm6dsv16b_ui_outy_h_a_dualc_t ui_outy_h_a_dualc; + lsm6dsv16b_ui_outx_l_a_dualc_t ui_outx_l_a_dualc; + lsm6dsv16b_ui_outx_h_a_dualc_t ui_outx_h_a_dualc; + lsm6dsv16b_timestamp0_t timestamp0; + lsm6dsv16b_timestamp1_t timestamp1; + lsm6dsv16b_timestamp2_t timestamp2; + lsm6dsv16b_timestamp3_t timestamp3; + lsm6dsv16b_wake_up_src_t wake_up_src; + lsm6dsv16b_tap_src_t tap_src; + lsm6dsv16b_d6d_src_t d6d_src; + lsm6dsv16b_emb_func_status_mainpage_t emb_func_status_mainpage; + lsm6dsv16b_fsm_status_mainpage_t fsm_status_mainpage; + lsm6dsv16b_internal_freq_t internal_freq; + lsm6dsv16b_functions_enable_t functions_enable; + lsm6dsv16b_inactivity_dur_t inactivity_dur; + lsm6dsv16b_inactivity_ths_t inactivity_ths; + lsm6dsv16b_tap_cfg0_t tap_cfg0; + lsm6dsv16b_tap_cfg1_t tap_cfg1; + lsm6dsv16b_tap_cfg2_t tap_cfg2; + lsm6dsv16b_tap_ths_6d_t tap_ths_6d; + lsm6dsv16b_tap_dur_t int_dur2; + lsm6dsv16b_wake_up_ths_t wake_up_ths; + lsm6dsv16b_wake_up_dur_t wake_up_dur; + lsm6dsv16b_free_fall_t free_fall; + lsm6dsv16b_md1_cfg_t md1_cfg; + lsm6dsv16b_md2_cfg_t md2_cfg; + lsm6dsv16b_emb_func_cfg_t emb_func_cfg; + lsm6dsv16b_tdm_cfg0_t tdm_cfg0; + lsm6dsv16b_tdm_cfg1_t tdm_cfg1; + lsm6dsv16b_tdm_cfg2_t tdm_cfg2; + lsm6dsv16b_z_ofs_usr_t z_ofs_usr; + lsm6dsv16b_y_ofs_usr_t y_ofs_usr; + lsm6dsv16b_x_ofs_usr_t x_ofs_usr; + lsm6dsv16b_fifo_data_out_tag_t fifo_data_out_tag; + lsm6dsv16b_fifo_data_out_byte_0_t fifo_data_out_byte_0; + lsm6dsv16b_fifo_data_out_byte_1_t fifo_data_out_byte_1; + lsm6dsv16b_fifo_data_out_byte_2_t fifo_data_out_byte_2; + lsm6dsv16b_fifo_data_out_byte_3_t fifo_data_out_byte_3; + lsm6dsv16b_fifo_data_out_byte_4_t fifo_data_out_byte_4; + lsm6dsv16b_fifo_data_out_byte_5_t fifo_data_out_byte_5; + lsm6dsv16b_page_sel_t page_sel; + lsm6dsv16b_emb_func_en_a_t emb_func_en_a; + lsm6dsv16b_emb_func_en_b_t emb_func_en_b; + lsm6dsv16b_emb_func_exec_status_t emb_func_exec_status; + lsm6dsv16b_page_address_t page_address; + lsm6dsv16b_page_value_t page_value; + lsm6dsv16b_emb_func_int1_t emb_func_int1; + lsm6dsv16b_fsm_int1_t fsm_int1; + lsm6dsv16b_emb_func_int2_t emb_func_int2; + lsm6dsv16b_fsm_int2_t fsm_int2; + lsm6dsv16b_emb_func_status_t emb_func_status; + lsm6dsv16b_fsm_status_t fsm_status; + lsm6dsv16b_page_rw_t page_rw; + lsm6dsv16b_emb_func_fifo_en_a_t emb_func_fifo_en_a; + lsm6dsv16b_fsm_enable_t fsm_enable; + lsm6dsv16b_fsm_long_counter_l_t fsm_long_counter_l; + lsm6dsv16b_fsm_long_counter_h_t fsm_long_counter_h; + lsm6dsv16b_fsm_outs1_t fsm_outs1; + lsm6dsv16b_fsm_outs2_t fsm_outs2; + lsm6dsv16b_fsm_outs3_t fsm_outs3; + lsm6dsv16b_fsm_outs4_t fsm_outs4; + lsm6dsv16b_fsm_outs5_t fsm_outs5; + lsm6dsv16b_fsm_outs6_t fsm_outs6; + lsm6dsv16b_fsm_outs7_t fsm_outs7; + lsm6dsv16b_fsm_outs8_t fsm_outs8; + lsm6dsv16b_fsm_odr_t fsm_odr; + lsm6dsv16b_step_counter_l_t step_counter_l; + lsm6dsv16b_step_counter_h_t step_counter_h; + lsm6dsv16b_emb_func_src_t emb_func_src; + lsm6dsv16b_emb_func_init_a_t emb_func_init_a; + lsm6dsv16b_emb_func_init_b_t emb_func_init_b; + lsm6dsv16b_fsm_lc_timeout_l_t fsm_lc_timeout_l; + lsm6dsv16b_fsm_lc_timeout_h_t fsm_lc_timeout_h; + lsm6dsv16b_fsm_programs_t fsm_programs; + lsm6dsv16b_fsm_start_add_l_t fsm_start_add_l; + lsm6dsv16b_fsm_start_add_h_t fsm_start_add_h; + lsm6dsv16b_pedo_cmd_reg_t pedo_cmd_reg; + lsm6dsv16b_pedo_deb_steps_conf_t pedo_deb_steps_conf; + lsm6dsv16b_pedo_sc_deltat_l_t pedo_sc_deltat_l; + lsm6dsv16b_pedo_sc_deltat_h_t pedo_sc_deltat_h; + bitwise_t bitwise; + uint8_t byte; +} lsm6dsv16b_reg_t; + + +/** + * @} + * + */ + +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + +int32_t lsm6dsv16b_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); +int32_t lsm6dsv16b_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); + +float_t lsm6dsv16b_from_sflp_to_mg(int16_t lsb); +float_t lsm6dsv16b_from_fs2_to_mg(int16_t lsb); +float_t lsm6dsv16b_from_fs4_to_mg(int16_t lsb); +float_t lsm6dsv16b_from_fs8_to_mg(int16_t lsb); +float_t lsm6dsv16b_from_fs16_to_mg(int16_t lsb); + +float_t lsm6dsv16b_from_fs125_to_mdps(int16_t lsb); +float_t lsm6dsv16b_from_fs500_to_mdps(int16_t lsb); +float_t lsm6dsv16b_from_fs250_to_mdps(int16_t lsb); +float_t lsm6dsv16b_from_fs1000_to_mdps(int16_t lsb); +float_t lsm6dsv16b_from_fs2000_to_mdps(int16_t lsb); +float_t lsm6dsv16b_from_fs4000_to_mdps(int16_t lsb); + +float_t lsm6dsv16b_from_lsb_to_celsius(int16_t lsb); + +uint64_t lsm6dsv16b_from_lsb_to_nsec(uint32_t lsb); + +float_t lsm6dsv16b_from_lsb_to_mv(int16_t lsb); + +typedef enum +{ + LSM6DSV16B_READY = 0x0, + LSM6DSV16B_GLOBAL_RST = 0x1, + LSM6DSV16B_RESTORE_CAL_PARAM = 0x2, + LSM6DSV16B_RESTORE_CTRL_REGS = 0x4, +} lsm6dsv16b_reset_t; +int32_t lsm6dsv16b_reset_set(const stmdev_ctx_t *ctx, lsm6dsv16b_reset_t val); +int32_t lsm6dsv16b_reset_get(const stmdev_ctx_t *ctx, lsm6dsv16b_reset_t *val); + +typedef enum +{ + LSM6DSV16B_MAIN_MEM_BANK = 0x0, + LSM6DSV16B_EMBED_FUNC_MEM_BANK = 0x1, +} lsm6dsv16b_mem_bank_t; +int32_t lsm6dsv16b_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dsv16b_mem_bank_t val); +int32_t lsm6dsv16b_mem_bank_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_mem_bank_t *val); + +int32_t lsm6dsv16b_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16B_XL_ODR_OFF = 0x0, + LSM6DSV16B_XL_ODR_AT_1Hz875 = 0x1, + LSM6DSV16B_XL_ODR_AT_7Hz5 = 0x2, + LSM6DSV16B_XL_ODR_AT_15Hz = 0x3, + LSM6DSV16B_XL_ODR_AT_30Hz = 0x4, + LSM6DSV16B_XL_ODR_AT_60Hz = 0x5, + LSM6DSV16B_XL_ODR_AT_120Hz = 0x6, + LSM6DSV16B_XL_ODR_AT_240Hz = 0x7, + LSM6DSV16B_XL_ODR_AT_480Hz = 0x8, + LSM6DSV16B_XL_ODR_AT_960Hz = 0x9, + LSM6DSV16B_XL_ODR_AT_1920Hz = 0xA, + LSM6DSV16B_XL_ODR_AT_3840Hz = 0xB, + LSM6DSV16B_XL_ODR_AT_7680Hz = 0xC, +} lsm6dsv16b_xl_data_rate_t; +int32_t lsm6dsv16b_xl_data_rate_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_xl_data_rate_t val); +int32_t lsm6dsv16b_xl_data_rate_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_xl_data_rate_t *val); + +typedef enum +{ + LSM6DSV16B_XL_HIGH_PERFORMANCE_MD = 0x0, + LSM6DSV16B_XL_HIGH_PERFORMANCE_TDM_MD = 0x2, + LSM6DSV16B_XL_LOW_POWER_2_AVG_MD = 0x4, + LSM6DSV16B_XL_LOW_POWER_4_AVG_MD = 0x5, + LSM6DSV16B_XL_LOW_POWER_8_AVG_MD = 0x6, +} lsm6dsv16b_xl_mode_t; +int32_t lsm6dsv16b_xl_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16b_xl_mode_t val); +int32_t lsm6dsv16b_xl_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16b_xl_mode_t *val); + +typedef enum +{ + LSM6DSV16B_GY_ODR_OFF = 0x0, + LSM6DSV16B_GY_ODR_AT_7Hz5 = 0x2, + LSM6DSV16B_GY_ODR_AT_15Hz = 0x3, + LSM6DSV16B_GY_ODR_AT_30Hz = 0x4, + LSM6DSV16B_GY_ODR_AT_60Hz = 0x5, + LSM6DSV16B_GY_ODR_AT_120Hz = 0x6, + LSM6DSV16B_GY_ODR_AT_240Hz = 0x7, + LSM6DSV16B_GY_ODR_AT_480Hz = 0x8, + LSM6DSV16B_GY_ODR_AT_960Hz = 0x9, + LSM6DSV16B_GY_ODR_AT_1920Hz = 0xa, + LSM6DSV16B_GY_ODR_AT_3840Hz = 0xb, + LSM6DSV16B_GY_ODR_AT_7680Hz = 0xc, +} lsm6dsv16b_gy_data_rate_t; +int32_t lsm6dsv16b_gy_data_rate_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_gy_data_rate_t val); +int32_t lsm6dsv16b_gy_data_rate_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_gy_data_rate_t *val); + +typedef enum +{ + LSM6DSV16B_GY_HIGH_PERFORMANCE_MD = 0x0, + LSM6DSV16B_GY_SLEEP_MD = 0x4, + LSM6DSV16B_GY_LOW_POWER_MD = 0x5, +} lsm6dsv16b_gy_mode_t; +int32_t lsm6dsv16b_gy_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16b_gy_mode_t val); +int32_t lsm6dsv16b_gy_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16b_gy_mode_t *val); + +int32_t lsm6dsv16b_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16b_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16b_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16b_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16B_DRDY_LATCHED = 0x0, + LSM6DSV16B_DRDY_PULSED = 0x1, +} lsm6dsv16b_data_ready_mode_t; +int32_t lsm6dsv16b_data_ready_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_data_ready_mode_t val); +int32_t lsm6dsv16b_data_ready_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_data_ready_mode_t *val); + +typedef enum +{ + LSM6DSV16B_125dps = 0x0, + LSM6DSV16B_250dps = 0x1, + LSM6DSV16B_500dps = 0x2, + LSM6DSV16B_1000dps = 0x3, + LSM6DSV16B_2000dps = 0x4, + LSM6DSV16B_4000dps = 0xc, +} lsm6dsv16b_gy_full_scale_t; +int32_t lsm6dsv16b_gy_full_scale_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_gy_full_scale_t val); +int32_t lsm6dsv16b_gy_full_scale_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_gy_full_scale_t *val); + +typedef enum +{ + LSM6DSV16B_2g = 0x0, + LSM6DSV16B_4g = 0x1, + LSM6DSV16B_8g = 0x2, + LSM6DSV16B_16g = 0x3, +} lsm6dsv16b_xl_full_scale_t; +int32_t lsm6dsv16b_xl_full_scale_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_xl_full_scale_t val); +int32_t lsm6dsv16b_xl_full_scale_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_xl_full_scale_t *val); + +int32_t lsm6dsv16b_xl_dual_channel_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16b_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16B_XL_ST_DISABLE = 0x0, + LSM6DSV16B_XL_ST_POSITIVE = 0x1, + LSM6DSV16B_XL_ST_NEGATIVE = 0x2, + LSM6DSV16B_XL_ST_OFFSET_POS = 0x5, + LSM6DSV16B_XL_ST_OFFSET_NEG = 0x6, +} lsm6dsv16b_xl_self_test_t; +int32_t lsm6dsv16b_xl_self_test_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_xl_self_test_t val); +int32_t lsm6dsv16b_xl_self_test_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_xl_self_test_t *val); + +typedef enum +{ + LSM6DSV16B_GY_ST_DISABLE = 0x0, + LSM6DSV16B_GY_ST_POSITIVE = 0x1, + LSM6DSV16B_GY_ST_NEGATIVE = 0x2, +} lsm6dsv16b_gy_self_test_t; +int32_t lsm6dsv16b_gy_self_test_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_gy_self_test_t val); +int32_t lsm6dsv16b_gy_self_test_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_gy_self_test_t *val); + +typedef struct +{ + uint8_t drdy_xl : 1; + uint8_t drdy_gy : 1; + uint8_t drdy_temp : 1; + uint8_t gy_settling : 1; + uint8_t den_flag : 1; + uint8_t timestamp : 1; + uint8_t free_fall : 1; + uint8_t wake_up : 1; + uint8_t wake_up_z : 1; + uint8_t wake_up_y : 1; + uint8_t wake_up_x : 1; + uint8_t single_tap : 1; + uint8_t double_tap : 1; + uint8_t tap_z : 1; + uint8_t tap_y : 1; + uint8_t tap_x : 1; + uint8_t tap_sign : 1; + uint8_t six_d : 1; + uint8_t six_d_xl : 1; + uint8_t six_d_xh : 1; + uint8_t six_d_yl : 1; + uint8_t six_d_yh : 1; + uint8_t six_d_zl : 1; + uint8_t six_d_zh : 1; + uint8_t sleep_change : 1; + uint8_t sleep_state : 1; + uint8_t step_detector : 1; + uint8_t step_count_inc : 1; + uint8_t step_count_overflow : 1; + uint8_t step_on_delta_time : 1; + uint8_t emb_func_stand_by : 1; + uint8_t emb_func_time_exceed: 1; + uint8_t tilt : 1; + uint8_t sig_mot : 1; + uint8_t fsm_lc : 1; + uint8_t fsm1 : 1; + uint8_t fsm2 : 1; + uint8_t fsm3 : 1; + uint8_t fsm4 : 1; + uint8_t fsm5 : 1; + uint8_t fsm6 : 1; + uint8_t fsm7 : 1; + uint8_t fsm8 : 1; + uint8_t fifo_bdr : 1; + uint8_t fifo_full : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_th : 1; +} lsm6dsv16b_all_sources_t; +int32_t lsm6dsv16b_all_sources_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_all_sources_t *val); + +typedef struct +{ + uint8_t drdy_xl : 1; + uint8_t drdy_gy : 1; + uint8_t drdy_temp : 1; +} lsm6dsv16b_data_ready_t; +int32_t lsm6dsv16b_flag_data_ready_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_data_ready_t *val); + +int32_t lsm6dsv16b_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsv16b_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsv16b_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsv16b_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsv16b_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, + int16_t *val); + +int32_t lsm6dsv16b_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val); + +typedef struct +{ + uint8_t x : 1; + uint8_t y : 1; + uint8_t z : 1; +} lsm6dsv16b_tdm_xl_axis_t; +int32_t lsm6dsv16b_tdm_xl_axis_set(const stmdev_ctx_t *ctx, lsm6dsv16b_tdm_xl_axis_t val); +int32_t lsm6dsv16b_tdm_xl_axis_get(const stmdev_ctx_t *ctx, lsm6dsv16b_tdm_xl_axis_t *val); + +int32_t lsm6dsv16b_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len); +int32_t lsm6dsv16b_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len); + +int32_t lsm6dsv16b_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16b_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16b_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); + +typedef enum +{ + LSM6DSV16B_AUTO = 0x0, + LSM6DSV16B_ALWAYS_ACTIVE = 0x1, +} lsm6dsv16b_filt_anti_spike_t; +int32_t lsm6dsv16b_filt_anti_spike_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_anti_spike_t val); +int32_t lsm6dsv16b_filt_anti_spike_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_anti_spike_t *val); + +typedef struct +{ + uint8_t drdy : 1; + uint8_t irq_xl : 1; + uint8_t irq_g : 1; + uint8_t tdm_excep_code : 1; +} lsm6dsv16b_filt_settling_mask_t; +int32_t lsm6dsv16b_filt_settling_mask_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_settling_mask_t val); +int32_t lsm6dsv16b_filt_settling_mask_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_settling_mask_t *val); + +typedef enum +{ + LSM6DSV16B_GY_ULTRA_LIGHT = 0x0, + LSM6DSV16B_GY_VERY_LIGHT = 0x1, + LSM6DSV16B_GY_LIGHT = 0x2, + LSM6DSV16B_GY_MEDIUM = 0x3, + LSM6DSV16B_GY_STRONG = 0x4, + LSM6DSV16B_GY_VERY_STRONG = 0x5, + LSM6DSV16B_GY_AGGRESSIVE = 0x6, + LSM6DSV16B_GY_XTREME = 0x7, +} lsm6dsv16b_filt_gy_lp1_bandwidth_t; +int32_t lsm6dsv16b_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_gy_lp1_bandwidth_t val); +int32_t lsm6dsv16b_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_gy_lp1_bandwidth_t *val); + +int32_t lsm6dsv16b_filt_gy_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16b_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16B_XL_ULTRA_LIGHT = 0x0, + LSM6DSV16B_XL_VERY_LIGHT = 0x1, + LSM6DSV16B_XL_LIGHT = 0x2, + LSM6DSV16B_XL_MEDIUM = 0x3, + LSM6DSV16B_XL_STRONG = 0x4, + LSM6DSV16B_XL_VERY_STRONG = 0x5, + LSM6DSV16B_XL_AGGRESSIVE = 0x6, + LSM6DSV16B_XL_XTREME = 0x7, +} lsm6dsv16b_filt_xl_lp2_bandwidth_t; +int32_t lsm6dsv16b_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_xl_lp2_bandwidth_t val); +int32_t lsm6dsv16b_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_xl_lp2_bandwidth_t *val); + +int32_t lsm6dsv16b_filt_xl_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16b_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16b_filt_xl_hp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16b_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16b_filt_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16b_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16B_HP_MD_NORMAL = 0x0, + LSM6DSV16B_HP_MD_REFERENCE = 0x1, +} lsm6dsv16b_filt_xl_hp_mode_t; +int32_t lsm6dsv16b_filt_xl_hp_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_xl_hp_mode_t val); +int32_t lsm6dsv16b_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_xl_hp_mode_t *val); + +typedef enum +{ + LSM6DSV16B_WK_FEED_SLOPE = 0x0, + LSM6DSV16B_WK_FEED_HIGH_PASS = 0x1, + LSM6DSV16B_WK_FEED_LP_WITH_OFFSET = 0x2, +} lsm6dsv16b_filt_wkup_act_feed_t; +int32_t lsm6dsv16b_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_wkup_act_feed_t val); +int32_t lsm6dsv16b_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_wkup_act_feed_t *val); + +int32_t lsm6dsv16b_mask_trigger_xl_settl_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16b_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16B_SIXD_FEED_ODR_DIV_2 = 0x0, + LSM6DSV16B_SIXD_FEED_LOW_PASS = 0x1, +} lsm6dsv16b_filt_sixd_feed_t; +int32_t lsm6dsv16b_filt_sixd_feed_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_sixd_feed_t val); +int32_t lsm6dsv16b_filt_sixd_feed_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_filt_sixd_feed_t *val); + +int32_t lsm6dsv16b_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16b_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16B_I2C_I3C_ENABLE = 0x0, + LSM6DSV16B_I2C_I3C_DISABLE = 0x1, +} lsm6dsv16b_ui_i2c_i3c_mode_t; +int32_t lsm6dsv16b_ui_i2c_i3c_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_ui_i2c_i3c_mode_t val); +int32_t lsm6dsv16b_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_ui_i2c_i3c_mode_t *val); + +typedef enum +{ + LSM6DSV16B_SPI_4_WIRE = 0x0, + LSM6DSV16B_SPI_3_WIRE = 0x1, +} lsm6dsv16b_spi_mode_t; +int32_t lsm6dsv16b_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16b_spi_mode_t val); +int32_t lsm6dsv16b_spi_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_spi_mode_t *val); + +int32_t lsm6dsv16b_ui_sda_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16b_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16B_IBI_2us = 0x0, + LSM6DSV16B_IBI_50us = 0x1, + LSM6DSV16B_IBI_1ms = 0x2, + LSM6DSV16B_IBI_25ms = 0x3, +} lsm6dsv16b_i3c_ibi_time_t; +int32_t lsm6dsv16b_i3c_ibi_time_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_i3c_ibi_time_t val); +int32_t lsm6dsv16b_i3c_ibi_time_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_i3c_ibi_time_t *val); + +typedef enum +{ + LSM6DSV16B_PUSH_PULL = 0x0, + LSM6DSV16B_OPEN_DRAIN = 0x1, +} lsm6dsv16b_int_pin_mode_t; +int32_t lsm6dsv16b_int_pin_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_int_pin_mode_t val); +int32_t lsm6dsv16b_int_pin_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_int_pin_mode_t *val); + +typedef enum +{ + LSM6DSV16B_ACTIVE_HIGH = 0x0, + LSM6DSV16B_ACTIVE_LOW = 0x1, +} lsm6dsv16b_pin_polarity_t; +int32_t lsm6dsv16b_pin_polarity_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_pin_polarity_t val); +int32_t lsm6dsv16b_pin_polarity_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_pin_polarity_t *val); + +typedef struct +{ + uint8_t boot : 1; + uint8_t drdy_xl : 1; + uint8_t drdy_gy : 1; + uint8_t drdy_temp : 1; + uint8_t fifo_th : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_full : 1; + uint8_t fifo_bdr : 1; + uint8_t den_flag : 1; + uint8_t timestamp : 1; // impact on int2 signals + uint8_t six_d : 1; + uint8_t double_tap : 1; + uint8_t free_fall : 1; + uint8_t wake_up : 1; + uint8_t single_tap : 1; + uint8_t sleep_change : 1; + uint8_t sleep_status : 1; + uint8_t step_detector : 1; + uint8_t step_count_overflow : 1; + uint8_t tilt : 1; + uint8_t sig_mot : 1; + uint8_t emb_func_stand_by : 1; // impact on int2 signals + uint8_t fsm_lc : 1; + uint8_t fsm1 : 1; + uint8_t fsm2 : 1; + uint8_t fsm3 : 1; + uint8_t fsm4 : 1; + uint8_t fsm5 : 1; + uint8_t fsm6 : 1; + uint8_t fsm7 : 1; + uint8_t fsm8 : 1; +} lsm6dsv16b_pin_int_route_t; +int32_t lsm6dsv16b_pin_int1_route_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_pin_int_route_t val); +int32_t lsm6dsv16b_pin_int1_route_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_pin_int_route_t *val); +int32_t lsm6dsv16b_pin_int2_route_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_pin_int_route_t val); +int32_t lsm6dsv16b_pin_int2_route_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_pin_int_route_t *val); + +int32_t lsm6dsv16b_pin_int_en_when_i2c_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16b_pin_int_en_when_i2c_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16B_ALL_INT_PULSED = 0x0, + LSM6DSV16B_BASE_LATCHED_EMB_PULSED = 0x1, + LSM6DSV16B_BASE_PULSED_EMB_LATCHED = 0x2, + LSM6DSV16B_ALL_INT_LATCHED = 0x3, +} lsm6dsv16b_int_notification_t; +int32_t lsm6dsv16b_int_notification_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_int_notification_t val); +int32_t lsm6dsv16b_int_notification_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_int_notification_t *val); + +typedef enum +{ + LSM6DSV16B_XL_AND_GY_NOT_AFFECTED = 0x0, + LSM6DSV16B_XL_LOW_POWER_GY_NOT_AFFECTED = 0x1, + LSM6DSV16B_XL_LOW_POWER_GY_SLEEP = 0x2, + LSM6DSV16B_XL_LOW_POWER_GY_POWER_DOWN = 0x3, +} lsm6dsv16b_act_mode_t; +int32_t lsm6dsv16b_act_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16b_act_mode_t val); +int32_t lsm6dsv16b_act_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_act_mode_t *val); + +typedef enum +{ + LSM6DSV16B_SLEEP_TO_ACT_AT_1ST_SAMPLE = 0x0, + LSM6DSV16B_SLEEP_TO_ACT_AT_2ND_SAMPLE = 0x1, + LSM6DSV16B_SLEEP_TO_ACT_AT_3RD_SAMPLE = 0x2, + LSM6DSV16B_SLEEP_TO_ACT_AT_4th_SAMPLE = 0x3, +} lsm6dsv16b_act_from_sleep_to_act_dur_t; +int32_t lsm6dsv16b_act_from_sleep_to_act_dur_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_act_from_sleep_to_act_dur_t val); +int32_t lsm6dsv16b_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_act_from_sleep_to_act_dur_t *val); + +typedef enum +{ + LSM6DSV16B_1Hz875 = 0x0, + LSM6DSV16B_15Hz = 0x1, + LSM6DSV16B_30Hz = 0x2, + LSM6DSV16B_60Hz = 0x3, +} lsm6dsv16b_act_sleep_xl_odr_t; +int32_t lsm6dsv16b_act_sleep_xl_odr_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_act_sleep_xl_odr_t val); +int32_t lsm6dsv16b_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_act_sleep_xl_odr_t *val); + +typedef struct +{ + uint32_t wk_ths_mg; + uint32_t inact_ths_mg; +} lsm6dsv16b_act_thresholds_t; +int32_t lsm6dsv16b_act_thresholds_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_act_thresholds_t val); +int32_t lsm6dsv16b_act_thresholds_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_act_thresholds_t *val); + +typedef struct +{ + uint8_t shock : 2; + uint8_t quiet : 4; +} lsm6dsv16b_act_wkup_time_windows_t; +int32_t lsm6dsv16b_act_wkup_time_windows_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_act_wkup_time_windows_t val); +int32_t lsm6dsv16b_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_act_wkup_time_windows_t *val); + +typedef struct +{ + uint8_t tap_x_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_z_en : 1; +} lsm6dsv16b_tap_detection_t; +int32_t lsm6dsv16b_tap_detection_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_tap_detection_t val); +int32_t lsm6dsv16b_tap_detection_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_tap_detection_t *val); + +typedef struct +{ + uint8_t x : 1; + uint8_t y : 1; + uint8_t z : 1; +} lsm6dsv16b_tap_thresholds_t; +int32_t lsm6dsv16b_tap_thresholds_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_tap_thresholds_t val); +int32_t lsm6dsv16b_tap_thresholds_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_tap_thresholds_t *val); + + +typedef enum +{ + LSM6DSV16B_XYZ = 0x3, + LSM6DSV16B_YXZ = 0x5, + LSM6DSV16B_XZY = 0x6, + LSM6DSV16B_ZYX = 0x0, + LSM6DSV16B_YZX = 0x1, + LSM6DSV16B_ZXY = 0x2, +} lsm6dsv16b_tap_axis_priority_t; +int32_t lsm6dsv16b_tap_axis_priority_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_tap_axis_priority_t val); +int32_t lsm6dsv16b_tap_axis_priority_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_tap_axis_priority_t *val); + +typedef struct +{ + uint8_t shock : 1; + uint8_t quiet : 1; + uint8_t tap_gap : 1; +} lsm6dsv16b_tap_time_windows_t; +int32_t lsm6dsv16b_tap_time_windows_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_tap_time_windows_t val); +int32_t lsm6dsv16b_tap_time_windows_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_tap_time_windows_t *val); + +typedef enum +{ + LSM6DSV16B_ONLY_SINGLE = 0x0, + LSM6DSV16B_BOTH_SINGLE_DOUBLE = 0x1, +} lsm6dsv16b_tap_mode_t; +int32_t lsm6dsv16b_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16b_tap_mode_t val); +int32_t lsm6dsv16b_tap_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_tap_mode_t *val); + +typedef enum +{ + LSM6DSV16B_DEG_80 = 0x0, + LSM6DSV16B_DEG_70 = 0x1, + LSM6DSV16B_DEG_60 = 0x2, + LSM6DSV16B_DEG_50 = 0x3, +} lsm6dsv16b_6d_threshold_t; +int32_t lsm6dsv16b_6d_threshold_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_6d_threshold_t val); +int32_t lsm6dsv16b_6d_threshold_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_6d_threshold_t *val); + +int32_t lsm6dsv16b_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16b_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16B_156_mg = 0x0, + LSM6DSV16B_219_mg = 0x1, + LSM6DSV16B_250_mg = 0x2, + LSM6DSV16B_312_mg = 0x3, + LSM6DSV16B_344_mg = 0x4, + LSM6DSV16B_406_mg = 0x5, + LSM6DSV16B_469_mg = 0x6, + LSM6DSV16B_500_mg = 0x7, +} lsm6dsv16b_ff_thresholds_t; +int32_t lsm6dsv16b_ff_thresholds_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_ff_thresholds_t val); +int32_t lsm6dsv16b_ff_thresholds_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_ff_thresholds_t *val); + +int32_t lsm6dsv16b_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16b_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16b_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16b_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16B_CMP_DISABLE = 0x0, + LSM6DSV16B_CMP_8_TO_1 = 0x1, + LSM6DSV16B_CMP_16_TO_1 = 0x2, + LSM6DSV16B_CMP_32_TO_1 = 0x3, +} lsm6dsv16b_fifo_compress_algo_t; +int32_t lsm6dsv16b_fifo_compress_algo_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_compress_algo_t val); +int32_t lsm6dsv16b_fifo_compress_algo_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_compress_algo_t *val); + +int32_t lsm6dsv16b_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, + uint8_t val); +int32_t lsm6dsv16b_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dsv16b_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, + uint8_t val); +int32_t lsm6dsv16b_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dsv16b_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16b_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16B_XL_NOT_BATCHED = 0x0, + LSM6DSV16B_XL_BATCHED_AT_1Hz875 = 0x1, + LSM6DSV16B_XL_BATCHED_AT_7Hz5 = 0x2, + LSM6DSV16B_XL_BATCHED_AT_15Hz = 0x3, + LSM6DSV16B_XL_BATCHED_AT_30Hz = 0x4, + LSM6DSV16B_XL_BATCHED_AT_60Hz = 0x5, + LSM6DSV16B_XL_BATCHED_AT_120Hz = 0x6, + LSM6DSV16B_XL_BATCHED_AT_240Hz = 0x7, + LSM6DSV16B_XL_BATCHED_AT_480Hz = 0x8, + LSM6DSV16B_XL_BATCHED_AT_960Hz = 0x9, + LSM6DSV16B_XL_BATCHED_AT_1920Hz = 0xA, + LSM6DSV16B_XL_BATCHED_AT_3840Hz = 0xB, + LSM6DSV16B_XL_BATCHED_AT_7680Hz = 0xC, +} lsm6dsv16b_fifo_xl_batch_t; +int32_t lsm6dsv16b_fifo_xl_batch_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_xl_batch_t val); +int32_t lsm6dsv16b_fifo_xl_batch_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_xl_batch_t *val); + +typedef enum +{ + LSM6DSV16B_GY_NOT_BATCHED = 0x0, + LSM6DSV16B_GY_BATCHED_AT_1Hz875 = 0x1, + LSM6DSV16B_GY_BATCHED_AT_7Hz5 = 0x2, + LSM6DSV16B_GY_BATCHED_AT_15Hz = 0x3, + LSM6DSV16B_GY_BATCHED_AT_30Hz = 0x4, + LSM6DSV16B_GY_BATCHED_AT_60Hz = 0x5, + LSM6DSV16B_GY_BATCHED_AT_120Hz = 0x6, + LSM6DSV16B_GY_BATCHED_AT_240Hz = 0x7, + LSM6DSV16B_GY_BATCHED_AT_480Hz = 0x8, + LSM6DSV16B_GY_BATCHED_AT_960Hz = 0x9, + LSM6DSV16B_GY_BATCHED_AT_1920Hz = 0xa, + LSM6DSV16B_GY_BATCHED_AT_3840Hz = 0xb, + LSM6DSV16B_GY_BATCHED_AT_7680Hz = 0xc, +} lsm6dsv16b_fifo_gy_batch_t; +int32_t lsm6dsv16b_fifo_gy_batch_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_gy_batch_t val); +int32_t lsm6dsv16b_fifo_gy_batch_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_gy_batch_t *val); + +typedef enum +{ + LSM6DSV16B_BYPASS_MODE = 0x0, + LSM6DSV16B_FIFO_MODE = 0x1, + LSM6DSV16B_STREAM_WTM_TO_FULL_MODE = 0x2, + LSM6DSV16B_STREAM_TO_FIFO_MODE = 0x3, + LSM6DSV16B_BYPASS_TO_STREAM_MODE = 0x4, + LSM6DSV16B_STREAM_MODE = 0x6, + LSM6DSV16B_BYPASS_TO_FIFO_MODE = 0x7, +} lsm6dsv16b_fifo_mode_t; +int32_t lsm6dsv16b_fifo_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_mode_t val); +int32_t lsm6dsv16b_fifo_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_mode_t *val); + +typedef enum +{ + LSM6DSV16B_TEMP_NOT_BATCHED = 0x0, + LSM6DSV16B_TEMP_BATCHED_AT_1Hz875 = 0x1, + LSM6DSV16B_TEMP_BATCHED_AT_15Hz = 0x2, + LSM6DSV16B_TEMP_BATCHED_AT_60Hz = 0x3, +} lsm6dsv16b_fifo_temp_batch_t; +int32_t lsm6dsv16b_fifo_temp_batch_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_temp_batch_t val); +int32_t lsm6dsv16b_fifo_temp_batch_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_temp_batch_t *val); + +typedef enum +{ + LSM6DSV16B_TMSTMP_NOT_BATCHED = 0x0, + LSM6DSV16B_TMSTMP_DEC_1 = 0x1, + LSM6DSV16B_TMSTMP_DEC_8 = 0x2, + LSM6DSV16B_TMSTMP_DEC_32 = 0x3, +} lsm6dsv16b_fifo_timestamp_batch_t; +int32_t lsm6dsv16b_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_timestamp_batch_t val); +int32_t lsm6dsv16b_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_timestamp_batch_t *val); + +int32_t lsm6dsv16b_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx, + uint16_t val); +int32_t lsm6dsv16b_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx, + uint16_t *val); + +typedef enum +{ + LSM6DSV16B_XL_BATCH_EVENT = 0x0, + LSM6DSV16B_GY_BATCH_EVENT = 0x1, +} lsm6dsv16b_fifo_batch_cnt_event_t; +int32_t lsm6dsv16b_fifo_batch_cnt_event_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_batch_cnt_event_t val); +int32_t lsm6dsv16b_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_batch_cnt_event_t *val); + +typedef struct +{ + uint8_t game_rotation : 1; + uint8_t gravity : 1; + uint8_t gbias : 1; +} lsm6dsv16b_fifo_sflp_raw_t; +int32_t lsm6dsv16b_fifo_sflp_batch_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_sflp_raw_t val); +int32_t lsm6dsv16b_fifo_sflp_batch_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_sflp_raw_t *val); + +typedef struct +{ + uint16_t fifo_level : 9; + uint8_t fifo_bdr : 1; + uint8_t fifo_full : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_th : 1; +} lsm6dsv16b_fifo_status_t; + +int32_t lsm6dsv16b_fifo_status_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_status_t *val); + +typedef struct +{ + enum + { + LSM6DSV16B_FIFO_EMPTY = 0x0, + LSM6DSV16B_GY_NC_TAG = 0x1, + LSM6DSV16B_XL_NC_TAG = 0x2, + LSM6DSV16B_TEMPERATURE_TAG = 0x3, + LSM6DSV16B_TIMESTAMP_TAG = 0x4, + LSM6DSV16B_CFG_CHANGE_TAG = 0x5, + LSM6DSV16B_XL_NC_T_2_TAG = 0x6, + LSM6DSV16B_XL_NC_T_1_TAG = 0x7, + LSM6DSV16B_XL_2XC_TAG = 0x8, + LSM6DSV16B_XL_3XC_TAG = 0x9, + LSM6DSV16B_GY_NC_T_2_TAG = 0xA, + LSM6DSV16B_GY_NC_T_1_TAG = 0xB, + LSM6DSV16B_GY_2XC_TAG = 0xC, + LSM6DSV16B_GY_3XC_TAG = 0xD, + LSM6DSV16B_STEP_COUNTER_TAG = 0x12, + LSM6DSV16B_SFLP_GAME_ROTATION_VECTOR_TAG = 0x13, + LSM6DSV16B_SFLP_GYROSCOPE_BIAS_TAG = 0x16, + LSM6DSV16B_SFLP_GRAVITY_VECTOR_TAG = 0x17, + LSM6DSV16B_XL_DUAL_CORE = 0x1D, + } tag; + uint8_t cnt; + uint8_t data[6]; +} lsm6dsv16b_fifo_out_raw_t; +int32_t lsm6dsv16b_fifo_out_raw_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_fifo_out_raw_t *val); + +int32_t lsm6dsv16b_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16b_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t step_counter_enable : 1; + uint8_t false_step_rej : 1; +} lsm6dsv16b_stpcnt_mode_t; +int32_t lsm6dsv16b_stpcnt_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_stpcnt_mode_t val); +int32_t lsm6dsv16b_stpcnt_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_stpcnt_mode_t *val); + +int32_t lsm6dsv16b_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lsm6dsv16b_stpcnt_rst_step_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16b_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16b_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16b_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16b_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv16b_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lsm6dsv16b_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16b_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16b_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16b_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16b_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv16b_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint16_t *val); + +typedef struct +{ + float_t gbias_x; /* dps */ + float_t gbias_y; /* dps */ + float_t gbias_z; /* dps */ +} lsm6dsv16b_sflp_gbias_t; +int32_t lsm6dsv16b_sflp_game_gbias_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_sflp_gbias_t *val); + +int32_t lsm6dsv16b_sflp_configure(const stmdev_ctx_t *ctx); + +typedef enum +{ + LSM6DSV16B_SFLP_15Hz = 0x0, + LSM6DSV16B_SFLP_30Hz = 0x1, + LSM6DSV16B_SFLP_60Hz = 0x2, + LSM6DSV16B_SFLP_120Hz = 0x3, + LSM6DSV16B_SFLP_240Hz = 0x4, + LSM6DSV16B_SFLP_480Hz = 0x5, +} lsm6dsv16b_sflp_data_rate_t; +int32_t lsm6dsv16b_sflp_data_rate_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_sflp_data_rate_t val); +int32_t lsm6dsv16b_sflp_data_rate_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_sflp_data_rate_t *val); + +typedef enum +{ + LSM6DSV16B_PROTECT_CTRL_REGS = 0x0, + LSM6DSV16B_WRITE_CTRL_REG = 0x1, +} lsm6dsv16b_fsm_permission_t; +int32_t lsm6dsv16b_fsm_permission_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_fsm_permission_t val); +int32_t lsm6dsv16b_fsm_permission_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_fsm_permission_t *val); + +typedef enum +{ + LSM6DSV16B_STD_IF_CONTROL = 0x0, + LSM6DSV16B_FSM_CONTROL = 0x1, +} lsm6dsv16b_fsm_permission_status_t; +int32_t lsm6dsv16b_fsm_permission_status(const stmdev_ctx_t *ctx, + lsm6dsv16b_fsm_permission_status_t *val); + +typedef struct +{ + uint8_t fsm1_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm8_en : 1; +} lsm6dsv16b_fsm_mode_t; +int32_t lsm6dsv16b_fsm_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16b_fsm_mode_t val); +int32_t lsm6dsv16b_fsm_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_fsm_mode_t *val); + +int32_t lsm6dsv16b_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv16b_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); + +typedef struct +{ + uint8_t fsm_outs1; + uint8_t fsm_outs2; + uint8_t fsm_outs3; + uint8_t fsm_outs4; + uint8_t fsm_outs5; + uint8_t fsm_outs6; + uint8_t fsm_outs7; + uint8_t fsm_outs8; +} lsm6dsv16b_fsm_out_t; +int32_t lsm6dsv16b_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dsv16b_fsm_out_t *val); + +typedef enum +{ + LSM6DSV16B_FSM_15Hz = 0x0, + LSM6DSV16B_FSM_30Hz = 0x1, + LSM6DSV16B_FSM_60Hz = 0x2, + LSM6DSV16B_FSM_120Hz = 0x3, + LSM6DSV16B_FSM_240Hz = 0x4, + LSM6DSV16B_FSM_480Hz = 0x5, + LSM6DSV16B_FSM_960Hz = 0x6, +} lsm6dsv16b_fsm_data_rate_t; +int32_t lsm6dsv16b_fsm_data_rate_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_fsm_data_rate_t val); +int32_t lsm6dsv16b_fsm_data_rate_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_fsm_data_rate_t *val); + +int32_t lsm6dsv16b_fsm_long_cnt_timeout_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv16b_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lsm6dsv16b_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16b_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16b_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv16b_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lsm6dsv16b_xl_offset_on_out_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16b_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + float_t z_mg; + float_t y_mg; + float_t x_mg; +} lsm6dsv16b_xl_offset_mg_t; +int32_t lsm6dsv16b_xl_offset_mg_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_xl_offset_mg_t val); +int32_t lsm6dsv16b_xl_offset_mg_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_xl_offset_mg_t *val); + +typedef enum +{ + LSM6DSV16B_SW_RST_DYN_ADDRESS_RST = 0x0, + LSM6DSV16B_I3C_GLOBAL_RST = 0x1, +} lsm6dsv16b_i3c_reset_mode_t; +int32_t lsm6dsv16b_i3c_reset_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_i3c_reset_mode_t val); +int32_t lsm6dsv16b_i3c_reset_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_i3c_reset_mode_t *val); + +int32_t lsm6dsv16b_tdm_dis_wclk_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16b_tdm_dis_wclk_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv16b_tdm_tdmout_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16b_tdm_tdmout_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16B_WCLK_16kHZ_BCLK_2048kHz = 0x1, + LSM6DSV16B_WCLK_8kHZ_BCLK_2048kHz = 0x4, +} lsm6dsv16b_tdm_wclk_bclk_t; +int32_t lsm6dsv16b_tdm_wclk_bclk_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_tdm_wclk_bclk_t val); +int32_t lsm6dsv16b_tdm_wclk_bclk_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_tdm_wclk_bclk_t *val); + +typedef enum +{ + LSM6DSV16B_SLOT_012 = 0x0, + LSM6DSV16B_SLOT_456 = 0x1, +} lsm6dsv16b_tdm_slot_t; +int32_t lsm6dsv16b_tdm_slot_set(const stmdev_ctx_t *ctx, lsm6dsv16b_tdm_slot_t val); +int32_t lsm6dsv16b_tdm_slot_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_tdm_slot_t *val); + +typedef enum +{ + LSM6DSV16B_BCLK_RISING = 0x0, + LSM6DSV16B_BCLK_FALLING = 0x1, +} lsm6dsv16b_tdm_bclk_edge_t; +int32_t lsm6dsv16b_tdm_bclk_edge_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_tdm_bclk_edge_t val); +int32_t lsm6dsv16b_tdm_bclk_edge_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_tdm_bclk_edge_t *val); + +int32_t lsm6dsv16b_tdm_delayed_conf_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16b_tdm_delayed_conf_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV16B_TDM_ORDER_ZYX = 0x0, + LSM6DSV16B_TDM_ORDER_XZY = 0x1, + LSM6DSV16B_TDM_ORDER_XYZ = 0x2, +} lsm6dsv16b_tdm_axis_order_t; +int32_t lsm6dsv16b_tdm_axis_order_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_tdm_axis_order_t val); +int32_t lsm6dsv16b_tdm_axis_order_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_tdm_axis_order_t *val); + +typedef enum +{ + LSM6DSV16B_TDM_2g = 0x0, + LSM6DSV16B_TDM_4g = 0x1, + LSM6DSV16B_TDM_8g = 0x2, +} lsm6dsv16b_tdm_xl_full_scale_t; +int32_t lsm6dsv16b_tdm_xl_full_scale_set(const stmdev_ctx_t *ctx, + lsm6dsv16b_tdm_xl_full_scale_t val); +int32_t lsm6dsv16b_tdm_xl_full_scale_get(const stmdev_ctx_t *ctx, + lsm6dsv16b_tdm_xl_full_scale_t *val); + +/** + * @} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /*LSM6DSV16B_DRIVER_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dsv16bx_STdC/driver/lsm6dsv16bx_reg.c b/sensor/stmemsc/lsm6dsv16bx_STdC/driver/lsm6dsv16bx_reg.c index 13b0638a..5120c590 100644 --- a/sensor/stmemsc/lsm6dsv16bx_STdC/driver/lsm6dsv16bx_reg.c +++ b/sensor/stmemsc/lsm6dsv16bx_STdC/driver/lsm6dsv16bx_reg.c @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2022 STMicroelectronics. + *

© Copyright (c) 2024 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm6dsv16bx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm6dsv16bx_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lsm6dsv16bx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm6dsv16bx_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm6dsv16bx_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -198,7 +208,7 @@ float_t lsm6dsv16bx_from_lsb_to_mv(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_reset_set(stmdev_ctx_t *ctx, lsm6dsv16bx_reset_t val) +int32_t lsm6dsv16bx_reset_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_reset_t val) { lsm6dsv16bx_func_cfg_access_t func_cfg_access; lsm6dsv16bx_ctrl3_t ctrl3; @@ -234,7 +244,7 @@ int32_t lsm6dsv16bx_reset_set(stmdev_ctx_t *ctx, lsm6dsv16bx_reset_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_reset_get(stmdev_ctx_t *ctx, lsm6dsv16bx_reset_t *val) +int32_t lsm6dsv16bx_reset_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_reset_t *val) { lsm6dsv16bx_func_cfg_access_t func_cfg_access; lsm6dsv16bx_ctrl3_t ctrl3; @@ -279,7 +289,7 @@ int32_t lsm6dsv16bx_reset_get(stmdev_ctx_t *ctx, lsm6dsv16bx_reset_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsv16bx_mem_bank_t val) +int32_t lsm6dsv16bx_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_mem_bank_t val) { lsm6dsv16bx_func_cfg_access_t func_cfg_access; int32_t ret; @@ -302,7 +312,7 @@ int32_t lsm6dsv16bx_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsv16bx_mem_bank_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_mem_bank_get(stmdev_ctx_t *ctx, lsm6dsv16bx_mem_bank_t *val) +int32_t lsm6dsv16bx_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_mem_bank_t *val) { lsm6dsv16bx_func_cfg_access_t func_cfg_access; int32_t ret; @@ -334,7 +344,7 @@ int32_t lsm6dsv16bx_mem_bank_get(stmdev_ctx_t *ctx, lsm6dsv16bx_mem_bank_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_device_id_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_who_am_i_t who_am_i; int32_t ret; @@ -349,11 +359,11 @@ int32_t lsm6dsv16bx_device_id_get(stmdev_ctx_t *ctx, uint8_t *val) * @brief Accelerometer output data rate (ODR) selection.[set] * * @param ctx read / write interface definitions - * @param val XL_ODR_OFF, XL_ODR_AT_1Hz875, XL_ODR_AT_7Hz5, XL_ODR_AT_15Hz, XL_ODR_AT_30Hz, XL_ODR_AT_60Hz, XL_ODR_AT_120Hz, XL_ODR_AT_240Hz, XL_ODR_AT_480Hz, XL_ODR_AT_960Hz, XL_ODR_AT_1920Hz, XL_ODR_AT_3840Hz, XL_ODR_AT_7680Hz, + * @param val lsm6dsv16bx_xl_data_rate_t enum * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_xl_data_rate_t val) { lsm6dsv16bx_ctrl1_t ctrl1; @@ -373,11 +383,11 @@ int32_t lsm6dsv16bx_xl_data_rate_set(stmdev_ctx_t *ctx, * @brief Accelerometer output data rate (ODR) selection.[get] * * @param ctx read / write interface definitions - * @param val XL_ODR_OFF, XL_ODR_AT_1Hz875, XL_ODR_AT_7Hz5, XL_ODR_AT_15Hz, XL_ODR_AT_30Hz, XL_ODR_AT_60Hz, XL_ODR_AT_120Hz, XL_ODR_AT_240Hz, XL_ODR_AT_480Hz, XL_ODR_AT_960Hz, XL_ODR_AT_1920Hz, XL_ODR_AT_3840Hz, XL_ODR_AT_7680Hz, + * @param val lsm6dsv16bx_xl_data_rate_t enum * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_xl_data_rate_t *val) { lsm6dsv16bx_ctrl1_t ctrl1; @@ -450,11 +460,11 @@ int32_t lsm6dsv16bx_xl_data_rate_get(stmdev_ctx_t *ctx, * @brief Accelerometer operating mode selection.[set] * * @param ctx read / write interface definitions - * @param val XL_HIGH_PERFORMANCE_MD, XL_HIGH_ACCURANCY_ODR_MD, XL_LOW_POWER_2_AVG_MD, XL_LOW_POWER_4_AVG_MD, XL_LOW_POWER_8_AVG_MD, XL_NORMAL_MD, + * @param val lsm6dsv16bx_xl_mode_t struct * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_xl_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_mode_t val) +int32_t lsm6dsv16bx_xl_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_xl_mode_t val) { lsm6dsv16bx_ctrl1_t ctrl1; int32_t ret; @@ -474,11 +484,11 @@ int32_t lsm6dsv16bx_xl_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_mode_t val) * @brief Accelerometer operating mode selection.[get] * * @param ctx read / write interface definitions - * @param val XL_HIGH_PERFORMANCE_MD, XL_HIGH_ACCURANCY_ODR_MD, XL_LOW_POWER_2_AVG_MD, XL_LOW_POWER_4_AVG_MD, XL_LOW_POWER_8_AVG_MD, XL_NORMAL_MD, + * @param val lsm6dsv16bx_xl_mode_t struct * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_xl_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_mode_t *val) +int32_t lsm6dsv16bx_xl_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_xl_mode_t *val) { lsm6dsv16bx_ctrl1_t ctrl1; int32_t ret; @@ -491,8 +501,8 @@ int32_t lsm6dsv16bx_xl_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_mode_t *val) *val = LSM6DSV16BX_XL_HIGH_PERFORMANCE_MD; break; - case LSM6DSV16BX_XL_HIGH_ACCURANCY_ODR_MD: - *val = LSM6DSV16BX_XL_HIGH_ACCURANCY_ODR_MD; + case LSM6DSV16BX_XL_HIGH_PERFORMANCE_TDM_MD: + *val = LSM6DSV16BX_XL_HIGH_PERFORMANCE_TDM_MD; break; case LSM6DSV16BX_XL_LOW_POWER_2_AVG_MD: @@ -507,10 +517,6 @@ int32_t lsm6dsv16bx_xl_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_mode_t *val) *val = LSM6DSV16BX_XL_LOW_POWER_8_AVG_MD; break; - case LSM6DSV16BX_XL_NORMAL_MD: - *val = LSM6DSV16BX_XL_NORMAL_MD; - break; - default: *val = LSM6DSV16BX_XL_HIGH_PERFORMANCE_MD; break; @@ -522,11 +528,11 @@ int32_t lsm6dsv16bx_xl_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_mode_t *val) * @brief Gyroscope output data rate (ODR) selection.[set] * * @param ctx read / write interface definitions - * @param val GY_ODR_OFF, GY_ODR_AT_7Hz5, GY_ODR_AT_15Hz, GY_ODR_AT_30Hz, GY_ODR_AT_60Hz, GY_ODR_AT_120Hz, GY_ODR_AT_240Hz, GY_ODR_AT_480Hz, GY_ODR_AT_960Hz, GY_ODR_AT_1920Hz, GY_ODR_AT_3840Hz, GY_ODR_AT_7680Hz, + * @param val lsm6dsv16bx_gy_data_rate_t enum * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_gy_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_gy_data_rate_t val) { lsm6dsv16bx_ctrl2_t ctrl2; @@ -547,11 +553,11 @@ int32_t lsm6dsv16bx_gy_data_rate_set(stmdev_ctx_t *ctx, * @brief Gyroscope output data rate (ODR) selection.[get] * * @param ctx read / write interface definitions - * @param val GY_ODR_OFF, GY_ODR_AT_7Hz5, GY_ODR_AT_15Hz, GY_ODR_AT_30Hz, GY_ODR_AT_60Hz, GY_ODR_AT_120Hz, GY_ODR_AT_240Hz, GY_ODR_AT_480Hz, GY_ODR_AT_960Hz, GY_ODR_AT_1920Hz, GY_ODR_AT_3840Hz, GY_ODR_AT_7680Hz, + * @param val lsm6dsv16bx_gy_data_rate_t enum * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_gy_data_rate_t *val) { lsm6dsv16bx_ctrl2_t ctrl2; @@ -624,7 +630,7 @@ int32_t lsm6dsv16bx_gy_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_gy_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_gy_mode_t val) +int32_t lsm6dsv16bx_gy_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_gy_mode_t val) { lsm6dsv16bx_ctrl2_t ctrl2; int32_t ret; @@ -647,7 +653,7 @@ int32_t lsm6dsv16bx_gy_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_gy_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_gy_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_gy_mode_t *val) +int32_t lsm6dsv16bx_gy_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_gy_mode_t *val) { lsm6dsv16bx_ctrl2_t ctrl2; int32_t ret; @@ -659,10 +665,6 @@ int32_t lsm6dsv16bx_gy_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_gy_mode_t *val) *val = LSM6DSV16BX_GY_HIGH_PERFORMANCE_MD; break; - case LSM6DSV16BX_GY_HIGH_ACCURANCY_ODR_MD: - *val = LSM6DSV16BX_GY_HIGH_ACCURANCY_ODR_MD; - break; - case LSM6DSV16BX_GY_SLEEP_MD: *val = LSM6DSV16BX_GY_SLEEP_MD; break; @@ -686,7 +688,7 @@ int32_t lsm6dsv16bx_gy_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_gy_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_ctrl3_t ctrl3; int32_t ret; @@ -709,7 +711,7 @@ int32_t lsm6dsv16bx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_ctrl3_t ctrl3; int32_t ret; @@ -729,7 +731,7 @@ int32_t lsm6dsv16bx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_ctrl3_t ctrl3; int32_t ret; @@ -753,7 +755,7 @@ int32_t lsm6dsv16bx_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_ctrl3_t ctrl3; int32_t ret; @@ -772,7 +774,7 @@ int32_t lsm6dsv16bx_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_data_ready_mode_t val) { lsm6dsv16bx_ctrl4_t ctrl4; @@ -797,7 +799,7 @@ int32_t lsm6dsv16bx_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_data_ready_mode_t *val) { lsm6dsv16bx_ctrl4_t ctrl4; @@ -830,7 +832,7 @@ int32_t lsm6dsv16bx_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_gy_full_scale_t val) { lsm6dsv16bx_ctrl6_t ctrl6; @@ -855,7 +857,7 @@ int32_t lsm6dsv16bx_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_gy_full_scale_t *val) { lsm6dsv16bx_ctrl6_t ctrl6; @@ -904,7 +906,7 @@ int32_t lsm6dsv16bx_gy_full_scale_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_xl_full_scale_t val) { lsm6dsv16bx_ctrl8_t ctrl8; @@ -929,7 +931,7 @@ int32_t lsm6dsv16bx_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_xl_full_scale_t *val) { lsm6dsv16bx_ctrl8_t ctrl8; @@ -970,7 +972,7 @@ int32_t lsm6dsv16bx_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_xl_dual_channel_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_xl_dual_channel_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_ctrl8_t ctrl8; int32_t ret; @@ -994,7 +996,7 @@ int32_t lsm6dsv16bx_xl_dual_channel_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_xl_dual_channel_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_ctrl8_t ctrl8; int32_t ret; @@ -1013,7 +1015,7 @@ int32_t lsm6dsv16bx_xl_dual_channel_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_xl_self_test_t val) { lsm6dsv16bx_ctrl10_t ctrl10; @@ -1039,7 +1041,7 @@ int32_t lsm6dsv16bx_xl_self_test_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_xl_self_test_t *val) { lsm6dsv16bx_ctrl10_t ctrl10; @@ -1077,7 +1079,7 @@ int32_t lsm6dsv16bx_xl_self_test_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_gy_self_test_t val) { lsm6dsv16bx_ctrl10_t ctrl10; @@ -1102,7 +1104,7 @@ int32_t lsm6dsv16bx_gy_self_test_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_gy_self_test_t *val) { lsm6dsv16bx_ctrl10_t ctrl10; @@ -1139,7 +1141,7 @@ int32_t lsm6dsv16bx_gy_self_test_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_all_sources_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_all_sources_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_all_sources_t *val) { lsm6dsv16bx_emb_func_status_mainpage_t emb_func_status_mainpage; @@ -1258,7 +1260,8 @@ int32_t lsm6dsv16bx_all_sources_get(stmdev_ctx_t *ctx, } if (ret == 0) { - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, 1); + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, + 1); } if (ret == 0) { @@ -1278,7 +1281,7 @@ int32_t lsm6dsv16bx_all_sources_get(stmdev_ctx_t *ctx, return ret; } -int32_t lsm6dsv16bx_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_flag_data_ready_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_data_ready_t *val) { lsm6dsv16bx_status_reg_t status; @@ -1288,6 +1291,7 @@ int32_t lsm6dsv16bx_flag_data_ready_get(stmdev_ctx_t *ctx, val->drdy_xl = status.xlda; val->drdy_gy = status.gda; val->drdy_temp = status.tda; + val->drdy_ah_qvar = status.ah_qvarda; return ret; } @@ -1300,7 +1304,7 @@ int32_t lsm6dsv16bx_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsv16bx_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1320,7 +1324,7 @@ int32_t lsm6dsv16bx_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsv16bx_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1344,7 +1348,7 @@ int32_t lsm6dsv16bx_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsv16bx_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1368,12 +1372,12 @@ int32_t lsm6dsv16bx_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_dual_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsv16bx_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_UI_OUTZ_L_A_OIS_DUALC, &buff[0], 6); + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_UI_OUTZ_L_A_DUALC, &buff[0], 6); val[2] = (int16_t)buff[1]; val[2] = (val[2] * 256) + (int16_t)buff[0]; val[1] = (int16_t)buff[3]; @@ -1392,7 +1396,7 @@ int32_t lsm6dsv16bx_dual_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_ah_qvar_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsv16bx_ah_qvar_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1412,7 +1416,7 @@ int32_t lsm6dsv16bx_ah_qvar_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_odr_cal_reg_get(stmdev_ctx_t *ctx, int8_t *val) +int32_t lsm6dsv16bx_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val) { lsm6dsv16bx_internal_freq_t internal_freq; int32_t ret; @@ -1431,7 +1435,7 @@ int32_t lsm6dsv16bx_odr_cal_reg_get(stmdev_ctx_t *ctx, int8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_xl_axis_set(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_axis_t val) +int32_t lsm6dsv16bx_tdm_xl_axis_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_xl_axis_t val) { lsm6dsv16bx_tdm_cfg1_t tdm_cfg1; int32_t ret; @@ -1456,7 +1460,7 @@ int32_t lsm6dsv16bx_xl_axis_set(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_axis_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_xl_axis_get(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_axis_t *val) +int32_t lsm6dsv16bx_tdm_xl_axis_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_xl_axis_t *val) { lsm6dsv16bx_tdm_cfg1_t tdm_cfg1; int32_t ret; @@ -1477,7 +1481,7 @@ int32_t lsm6dsv16bx_xl_axis_get(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_axis_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dsv16bx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len) { lsm6dsv16bx_page_address_t page_address; @@ -1556,7 +1560,7 @@ int32_t lsm6dsv16bx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dsv16bx_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len) { lsm6dsv16bx_page_address_t page_address; @@ -1648,7 +1652,7 @@ int32_t lsm6dsv16bx_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_functions_enable_t functions_enable; int32_t ret; @@ -1671,7 +1675,7 @@ int32_t lsm6dsv16bx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_functions_enable_t functions_enable; int32_t ret; @@ -1690,7 +1694,7 @@ int32_t lsm6dsv16bx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t lsm6dsv16bx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; @@ -1725,7 +1729,7 @@ int32_t lsm6dsv16bx_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_filt_anti_spike_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_anti_spike_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_anti_spike_t val) { lsm6dsv16bx_if_cfg_t if_cfg; @@ -1750,7 +1754,7 @@ int32_t lsm6dsv16bx_filt_anti_spike_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_filt_anti_spike_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_anti_spike_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_anti_spike_t *val) { lsm6dsv16bx_if_cfg_t if_cfg; @@ -1782,7 +1786,7 @@ int32_t lsm6dsv16bx_filt_anti_spike_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_filt_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_settling_mask_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_settling_mask_t val) { lsm6dsv16bx_emb_func_cfg_t emb_func_cfg; @@ -1833,7 +1837,7 @@ int32_t lsm6dsv16bx_filt_settling_mask_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_filt_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_settling_mask_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_settling_mask_t *val) { lsm6dsv16bx_emb_func_cfg_t emb_func_cfg; @@ -1867,7 +1871,7 @@ int32_t lsm6dsv16bx_filt_settling_mask_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_filt_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_gy_lp1_bandwidth_t val) { lsm6dsv16bx_ctrl6_t ctrl6; @@ -1891,7 +1895,7 @@ int32_t lsm6dsv16bx_filt_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_filt_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_gy_lp1_bandwidth_t *val) { lsm6dsv16bx_ctrl6_t ctrl6; @@ -1941,14 +1945,14 @@ int32_t lsm6dsv16bx_filt_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, } /** - * @brief It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.[set] + * @brief It enables gyroscope digital LPF1 filter.[set] * * @param ctx read / write interface definitions - * @param val It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW. + * @param val It enables gyroscope digital LPF1 filter. * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_filt_gy_lp1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_filt_gy_lp1_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_ctrl7_t ctrl7; int32_t ret; @@ -1965,14 +1969,14 @@ int32_t lsm6dsv16bx_filt_gy_lp1_set(stmdev_ctx_t *ctx, uint8_t val) } /** - * @brief It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.[get] + * @brief It enables gyroscope digital LPF1 filter.[get] * * @param ctx read / write interface definitions - * @param val It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW. + * @param val It enables gyroscope digital LPF1 filter. * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_filt_gy_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_ctrl7_t ctrl7; int32_t ret; @@ -1991,7 +1995,7 @@ int32_t lsm6dsv16bx_filt_gy_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_filt_ah_qvar_conf_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_ah_qvar_conf_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_ah_qvar_conf_t val) { lsm6dsv16bx_ctrl9_t ctrl9; @@ -2027,7 +2031,7 @@ int32_t lsm6dsv16bx_filt_ah_qvar_conf_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_filt_ah_qvar_conf_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_ah_qvar_conf_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_ah_qvar_conf_t *val) { lsm6dsv16bx_ctrl8_t ctrl8; @@ -2054,7 +2058,7 @@ int32_t lsm6dsv16bx_filt_ah_qvar_conf_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_filt_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_xl_lp2_bandwidth_t val) { lsm6dsv16bx_ctrl8_t ctrl8; @@ -2078,7 +2082,7 @@ int32_t lsm6dsv16bx_filt_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_filt_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_xl_lp2_bandwidth_t *val) { lsm6dsv16bx_ctrl8_t ctrl8; @@ -2134,7 +2138,7 @@ int32_t lsm6dsv16bx_filt_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_filt_xl_lp2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_filt_xl_lp2_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_ctrl9_t ctrl9; int32_t ret; @@ -2157,7 +2161,7 @@ int32_t lsm6dsv16bx_filt_xl_lp2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_filt_xl_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_ctrl9_t ctrl9; int32_t ret; @@ -2176,7 +2180,7 @@ int32_t lsm6dsv16bx_filt_xl_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_filt_xl_hp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_filt_xl_hp_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_ctrl9_t ctrl9; int32_t ret; @@ -2199,7 +2203,7 @@ int32_t lsm6dsv16bx_filt_xl_hp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_filt_xl_hp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_ctrl9_t ctrl9; int32_t ret; @@ -2218,7 +2222,7 @@ int32_t lsm6dsv16bx_filt_xl_hp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_filt_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_filt_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_ctrl9_t ctrl9; int32_t ret; @@ -2241,7 +2245,7 @@ int32_t lsm6dsv16bx_filt_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_filt_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_ctrl9_t ctrl9; int32_t ret; @@ -2260,7 +2264,7 @@ int32_t lsm6dsv16bx_filt_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_filt_xl_hp_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_xl_hp_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_xl_hp_mode_t val) { lsm6dsv16bx_ctrl9_t ctrl9; @@ -2284,7 +2288,7 @@ int32_t lsm6dsv16bx_filt_xl_hp_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_filt_xl_hp_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_xl_hp_mode_t *val) { lsm6dsv16bx_ctrl9_t ctrl9; @@ -2316,7 +2320,7 @@ int32_t lsm6dsv16bx_filt_xl_hp_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_filt_wkup_act_feed_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_wkup_act_feed_t val) { lsm6dsv16bx_wake_up_ths_t wake_up_ths; @@ -2354,7 +2358,7 @@ int32_t lsm6dsv16bx_filt_wkup_act_feed_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_filt_wkup_act_feed_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_wkup_act_feed_t *val) { lsm6dsv16bx_wake_up_ths_t wake_up_ths; @@ -2396,7 +2400,7 @@ int32_t lsm6dsv16bx_filt_wkup_act_feed_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_mask_trigger_xl_settl_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_mask_trigger_xl_settl_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_tap_cfg0_t tap_cfg0; int32_t ret; @@ -2420,7 +2424,7 @@ int32_t lsm6dsv16bx_mask_trigger_xl_settl_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_mask_trigger_xl_settl_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_tap_cfg0_t tap_cfg0; int32_t ret; @@ -2440,7 +2444,7 @@ int32_t lsm6dsv16bx_mask_trigger_xl_settl_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_filt_sixd_feed_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_sixd_feed_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_sixd_feed_t val) { lsm6dsv16bx_tap_cfg0_t tap_cfg0; @@ -2464,7 +2468,7 @@ int32_t lsm6dsv16bx_filt_sixd_feed_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_filt_sixd_feed_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_sixd_feed_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_sixd_feed_t *val) { lsm6dsv16bx_tap_cfg0_t tap_cfg0; @@ -2509,7 +2513,7 @@ int32_t lsm6dsv16bx_filt_sixd_feed_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_pin_ctrl_t pin_ctrl; int32_t ret; @@ -2532,7 +2536,7 @@ int32_t lsm6dsv16bx_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_pin_ctrl_t pin_ctrl; int32_t ret; @@ -2551,7 +2555,7 @@ int32_t lsm6dsv16bx_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_ui_i2c_i3c_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_ui_i2c_i3c_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_ui_i2c_i3c_mode_t val) { lsm6dsv16bx_if_cfg_t if_cfg; @@ -2575,7 +2579,7 @@ int32_t lsm6dsv16bx_ui_i2c_i3c_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_ui_i2c_i3c_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_ui_i2c_i3c_mode_t *val) { lsm6dsv16bx_if_cfg_t if_cfg; @@ -2607,7 +2611,7 @@ int32_t lsm6dsv16bx_ui_i2c_i3c_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_spi_mode_t val) +int32_t lsm6dsv16bx_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_spi_mode_t val) { lsm6dsv16bx_if_cfg_t if_cfg; int32_t ret; @@ -2630,7 +2634,7 @@ int32_t lsm6dsv16bx_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_spi_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_spi_mode_t *val) +int32_t lsm6dsv16bx_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_spi_mode_t *val) { lsm6dsv16bx_if_cfg_t if_cfg; int32_t ret; @@ -2661,7 +2665,7 @@ int32_t lsm6dsv16bx_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_spi_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_ui_sda_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_ui_sda_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_if_cfg_t if_cfg; int32_t ret; @@ -2684,7 +2688,7 @@ int32_t lsm6dsv16bx_ui_sda_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_ui_sda_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_if_cfg_t if_cfg; int32_t ret; @@ -2703,7 +2707,7 @@ int32_t lsm6dsv16bx_ui_sda_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_i3c_ibi_time_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_i3c_ibi_time_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_i3c_ibi_time_t val) { lsm6dsv16bx_ctrl5_t ctrl5; @@ -2727,7 +2731,7 @@ int32_t lsm6dsv16bx_i3c_ibi_time_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_i3c_ibi_time_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_i3c_ibi_time_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_i3c_ibi_time_t *val) { lsm6dsv16bx_ctrl5_t ctrl5; @@ -2779,7 +2783,7 @@ int32_t lsm6dsv16bx_i3c_ibi_time_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_int_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_int_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_int_pin_mode_t val) { lsm6dsv16bx_if_cfg_t if_cfg; @@ -2803,7 +2807,7 @@ int32_t lsm6dsv16bx_int_pin_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_int_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_int_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_int_pin_mode_t *val) { lsm6dsv16bx_if_cfg_t if_cfg; @@ -2835,7 +2839,7 @@ int32_t lsm6dsv16bx_int_pin_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_pin_polarity_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_pin_polarity_t val) { lsm6dsv16bx_if_cfg_t if_cfg; @@ -2859,7 +2863,7 @@ int32_t lsm6dsv16bx_pin_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_pin_polarity_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_pin_polarity_t *val) { lsm6dsv16bx_if_cfg_t if_cfg; @@ -2891,11 +2895,11 @@ int32_t lsm6dsv16bx_pin_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_pin_int1_route_set(stmdev_ctx_t *ctx, - lsm6dsv16bx_pin_int1_route_t val) +int32_t lsm6dsv16bx_pin_int1_route_set(const stmdev_ctx_t *ctx, + lsm6dsv16bx_pin_int_route_t val) { lsm6dsv16bx_functions_enable_t functions_enable; - lsm6dsv16bx_pin_int2_route_t pin_int2_route; + lsm6dsv16bx_pin_int_route_t pin_int2_route; lsm6dsv16bx_inactivity_dur_t inactivity_dur; lsm6dsv16bx_emb_func_int1_t emb_func_int1; lsm6dsv16bx_pedo_cmd_reg_t pedo_cmd_reg; @@ -3127,8 +3131,8 @@ int32_t lsm6dsv16bx_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_pin_int1_route_get(stmdev_ctx_t *ctx, - lsm6dsv16bx_pin_int1_route_t *val) +int32_t lsm6dsv16bx_pin_int1_route_get(const stmdev_ctx_t *ctx, + lsm6dsv16bx_pin_int_route_t *val) { lsm6dsv16bx_inactivity_dur_t inactivity_dur; lsm6dsv16bx_emb_func_int1_t emb_func_int1; @@ -3241,17 +3245,18 @@ int32_t lsm6dsv16bx_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_pin_int2_route_set(stmdev_ctx_t *ctx, - lsm6dsv16bx_pin_int2_route_t val) +int32_t lsm6dsv16bx_pin_int2_route_set(const stmdev_ctx_t *ctx, + lsm6dsv16bx_pin_int_route_t val) { lsm6dsv16bx_functions_enable_t functions_enable; - lsm6dsv16bx_pin_int1_route_t pin_int1_route; + lsm6dsv16bx_pin_int_route_t pin_int1_route; lsm6dsv16bx_inactivity_dur_t inactivity_dur; lsm6dsv16bx_emb_func_int2_t emb_func_int2; lsm6dsv16bx_pedo_cmd_reg_t pedo_cmd_reg; lsm6dsv16bx_int2_ctrl_t int2_ctrl; lsm6dsv16bx_fsm_int2_t fsm_int2; lsm6dsv16bx_mlc_int2_t mlc_int2; + lsm6dsv16bx_ctrl7_t ctrl7; lsm6dsv16bx_md2_cfg_t md2_cfg; lsm6dsv16bx_ctrl4_t ctrl4; int32_t ret; @@ -3343,6 +3348,13 @@ int32_t lsm6dsv16bx_pin_int2_route_set(stmdev_ctx_t *ctx, ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1); + ctrl7.int2_drdy_ah_qvar = val.drdy_ah_qvar; + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1); + } + if (ret == 0) { ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1); @@ -3450,8 +3462,8 @@ int32_t lsm6dsv16bx_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_pin_int2_route_get(stmdev_ctx_t *ctx, - lsm6dsv16bx_pin_int2_route_t *val) +int32_t lsm6dsv16bx_pin_int2_route_get(const stmdev_ctx_t *ctx, + lsm6dsv16bx_pin_int_route_t *val) { lsm6dsv16bx_inactivity_dur_t inactivity_dur; lsm6dsv16bx_emb_func_int2_t emb_func_int2; @@ -3459,6 +3471,7 @@ int32_t lsm6dsv16bx_pin_int2_route_get(stmdev_ctx_t *ctx, lsm6dsv16bx_int2_ctrl_t int2_ctrl; lsm6dsv16bx_fsm_int2_t fsm_int2; lsm6dsv16bx_mlc_int2_t mlc_int2; + lsm6dsv16bx_ctrl7_t ctrl7; lsm6dsv16bx_md2_cfg_t md2_cfg; lsm6dsv16bx_ctrl4_t ctrl4; int32_t ret; @@ -3497,6 +3510,11 @@ int32_t lsm6dsv16bx_pin_int2_route_get(stmdev_ctx_t *ctx, val->fifo_bdr = int2_ctrl.int2_cnt_bdr; } + if (ret == 0) + { + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1); + val->drdy_ah_qvar = ctrl7.int2_drdy_ah_qvar; + } if (ret == 0) { @@ -3561,7 +3579,7 @@ int32_t lsm6dsv16bx_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_pin_int_en_when_i2c_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_pin_int_en_when_i2c_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_ctrl5_t ctrl5; int32_t ret; @@ -3584,7 +3602,7 @@ int32_t lsm6dsv16bx_pin_int_en_when_i2c_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_pin_int_en_when_i2c_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_pin_int_en_when_i2c_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_ctrl5_t ctrl5; int32_t ret; @@ -3603,7 +3621,7 @@ int32_t lsm6dsv16bx_pin_int_en_when_i2c_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_int_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_int_notification_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_int_notification_t val) { lsm6dsv16bx_tap_cfg0_t tap_cfg0; @@ -3645,7 +3663,7 @@ int32_t lsm6dsv16bx_int_notification_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_int_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_int_notification_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_int_notification_t *val) { lsm6dsv16bx_tap_cfg0_t tap_cfg0; @@ -3710,7 +3728,7 @@ int32_t lsm6dsv16bx_int_notification_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_act_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_act_mode_t val) +int32_t lsm6dsv16bx_act_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_act_mode_t val) { lsm6dsv16bx_functions_enable_t functions_enable; int32_t ret; @@ -3733,7 +3751,7 @@ int32_t lsm6dsv16bx_act_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_act_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_act_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_act_mode_t *val) +int32_t lsm6dsv16bx_act_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_act_mode_t *val) { lsm6dsv16bx_functions_enable_t functions_enable; int32_t ret; @@ -3772,7 +3790,7 @@ int32_t lsm6dsv16bx_act_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_act_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_act_from_sleep_to_act_dur_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_act_from_sleep_to_act_dur_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_act_from_sleep_to_act_dur_t val) { lsm6dsv16bx_inactivity_dur_t inactivity_dur; @@ -3796,7 +3814,7 @@ int32_t lsm6dsv16bx_act_from_sleep_to_act_dur_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_act_from_sleep_to_act_dur_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_act_from_sleep_to_act_dur_t *val) { lsm6dsv16bx_inactivity_dur_t inactivity_dur; @@ -3836,7 +3854,7 @@ int32_t lsm6dsv16bx_act_from_sleep_to_act_dur_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_act_sleep_xl_odr_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_act_sleep_xl_odr_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_act_sleep_xl_odr_t val) { lsm6dsv16bx_inactivity_dur_t inactivity_dur; @@ -3860,7 +3878,7 @@ int32_t lsm6dsv16bx_act_sleep_xl_odr_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_act_sleep_xl_odr_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_act_sleep_xl_odr_t *val) { lsm6dsv16bx_inactivity_dur_t inactivity_dur; @@ -3900,7 +3918,7 @@ int32_t lsm6dsv16bx_act_sleep_xl_odr_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_act_thresholds_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_act_thresholds_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_act_thresholds_t val) { lsm6dsv16bx_inactivity_ths_t inactivity_ths; @@ -4019,7 +4037,7 @@ int32_t lsm6dsv16bx_act_thresholds_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_act_thresholds_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_act_thresholds_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_act_thresholds_t *val) { lsm6dsv16bx_inactivity_dur_t inactivity_dur; @@ -4100,7 +4118,7 @@ int32_t lsm6dsv16bx_act_thresholds_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_act_wkup_time_windows_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_act_wkup_time_windows_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_act_wkup_time_windows_t val) { lsm6dsv16bx_wake_up_dur_t wake_up_dur; @@ -4125,7 +4143,7 @@ int32_t lsm6dsv16bx_act_wkup_time_windows_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_act_wkup_time_windows_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_act_wkup_time_windows_t *val) { lsm6dsv16bx_wake_up_dur_t wake_up_dur; @@ -4159,7 +4177,7 @@ int32_t lsm6dsv16bx_act_wkup_time_windows_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tap_detection_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tap_detection_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_tap_detection_t val) { lsm6dsv16bx_tap_cfg0_t tap_cfg0; @@ -4185,7 +4203,7 @@ int32_t lsm6dsv16bx_tap_detection_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tap_detection_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tap_detection_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tap_detection_t *val) { lsm6dsv16bx_tap_cfg0_t tap_cfg0; @@ -4207,7 +4225,7 @@ int32_t lsm6dsv16bx_tap_detection_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tap_thresholds_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tap_thresholds_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_tap_thresholds_t val) { lsm6dsv16bx_tap_ths_6d_t tap_ths_6d; @@ -4253,7 +4271,7 @@ int32_t lsm6dsv16bx_tap_thresholds_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tap_thresholds_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tap_thresholds_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tap_thresholds_t *val) { lsm6dsv16bx_tap_ths_6d_t tap_ths_6d; @@ -4286,7 +4304,7 @@ int32_t lsm6dsv16bx_tap_thresholds_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tap_axis_priority_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_tap_axis_priority_t val) { lsm6dsv16bx_tap_cfg1_t tap_cfg1; @@ -4310,7 +4328,7 @@ int32_t lsm6dsv16bx_tap_axis_priority_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tap_axis_priority_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tap_axis_priority_t *val) { lsm6dsv16bx_tap_cfg1_t tap_cfg1; @@ -4359,7 +4377,7 @@ int32_t lsm6dsv16bx_tap_axis_priority_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tap_time_windows_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tap_time_windows_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_tap_time_windows_t val) { lsm6dsv16bx_tap_dur_t tap_dur; @@ -4385,7 +4403,7 @@ int32_t lsm6dsv16bx_tap_time_windows_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tap_time_windows_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tap_time_windows_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tap_time_windows_t *val) { lsm6dsv16bx_tap_dur_t tap_dur; @@ -4407,7 +4425,7 @@ int32_t lsm6dsv16bx_tap_time_windows_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tap_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_tap_mode_t val) +int32_t lsm6dsv16bx_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_tap_mode_t val) { lsm6dsv16bx_wake_up_ths_t wake_up_ths; int32_t ret; @@ -4430,7 +4448,7 @@ int32_t lsm6dsv16bx_tap_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_tap_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tap_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_tap_mode_t *val) +int32_t lsm6dsv16bx_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tap_mode_t *val) { lsm6dsv16bx_wake_up_ths_t wake_up_ths; int32_t ret; @@ -4474,7 +4492,7 @@ int32_t lsm6dsv16bx_tap_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_tap_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_6d_threshold_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_6d_threshold_t val) { lsm6dsv16bx_tap_ths_6d_t tap_ths_6d; @@ -4498,7 +4516,7 @@ int32_t lsm6dsv16bx_6d_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_6d_threshold_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_6d_threshold_t *val) { lsm6dsv16bx_tap_ths_6d_t tap_ths_6d; @@ -4551,7 +4569,7 @@ int32_t lsm6dsv16bx_6d_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_ff_time_windows_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_wake_up_dur_t wake_up_dur; lsm6dsv16bx_free_fall_t free_fall; @@ -4585,7 +4603,7 @@ int32_t lsm6dsv16bx_ff_time_windows_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_ff_time_windows_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_wake_up_dur_t wake_up_dur; lsm6dsv16bx_free_fall_t free_fall; @@ -4610,7 +4628,7 @@ int32_t lsm6dsv16bx_ff_time_windows_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_ff_thresholds_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_ff_thresholds_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_ff_thresholds_t val) { lsm6dsv16bx_free_fall_t free_fall; @@ -4634,7 +4652,7 @@ int32_t lsm6dsv16bx_ff_thresholds_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_ff_thresholds_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_ff_thresholds_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_ff_thresholds_t *val) { lsm6dsv16bx_free_fall_t free_fall; @@ -4703,7 +4721,7 @@ int32_t lsm6dsv16bx_ff_thresholds_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_fifo_ctrl1_t fifo_ctrl1; int32_t ret; @@ -4727,7 +4745,7 @@ int32_t lsm6dsv16bx_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_fifo_ctrl1_t fifo_ctrl1; int32_t ret; @@ -4746,7 +4764,7 @@ int32_t lsm6dsv16bx_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_xl_dual_fsm_batch_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -4769,7 +4787,7 @@ int32_t lsm6dsv16bx_fifo_xl_dual_fsm_batch_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_xl_dual_fsm_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -4788,7 +4806,7 @@ int32_t lsm6dsv16bx_fifo_xl_dual_fsm_batch_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_compress_algo_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_compress_algo_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_compress_algo_t val) { lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2; @@ -4812,7 +4830,7 @@ int32_t lsm6dsv16bx_fifo_compress_algo_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_compress_algo_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_compress_algo_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_compress_algo_t *val) { lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2; @@ -4853,7 +4871,7 @@ int32_t lsm6dsv16bx_fifo_compress_algo_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2; @@ -4877,7 +4895,7 @@ int32_t lsm6dsv16bx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2; @@ -4897,7 +4915,7 @@ int32_t lsm6dsv16bx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_compress_algo_real_time_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_emb_func_en_b_t emb_func_en_b; @@ -4939,7 +4957,7 @@ int32_t lsm6dsv16bx_fifo_compress_algo_real_time_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_compress_algo_real_time_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2; @@ -4960,7 +4978,7 @@ int32_t lsm6dsv16bx_fifo_compress_algo_real_time_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -4983,7 +5001,7 @@ int32_t lsm6dsv16bx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -4998,11 +5016,11 @@ int32_t lsm6dsv16bx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[set] * * @param ctx read / write interface definitions - * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz, + * @param val lsm6dsv16bx_fifo_xl_batch_t enum * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_xl_batch_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_xl_batch_t val) { lsm6dsv16bx_fifo_ctrl3_t fifo_ctrl3; @@ -5022,11 +5040,11 @@ int32_t lsm6dsv16bx_fifo_xl_batch_set(stmdev_ctx_t *ctx, * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[get] * * @param ctx read / write interface definitions - * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz, + * @param val lsm6dsv16bx_fifo_xl_batch_t enum * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_xl_batch_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_xl_batch_t *val) { lsm6dsv16bx_fifo_ctrl3_t fifo_ctrl3; @@ -5098,11 +5116,11 @@ int32_t lsm6dsv16bx_fifo_xl_batch_get(stmdev_ctx_t *ctx, * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[set] * * @param ctx read / write interface definitions - * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz, + * @param val lsm6dsv16bx_fifo_gy_batch_t enum * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_gy_batch_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_gy_batch_t val) { lsm6dsv16bx_fifo_ctrl3_t fifo_ctrl3; @@ -5122,11 +5140,11 @@ int32_t lsm6dsv16bx_fifo_gy_batch_set(stmdev_ctx_t *ctx, * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[get] * * @param ctx read / write interface definitions - * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz, + * @param val lsm6dsv16bx_fifo_gy_batch_t enum * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_gy_batch_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_gy_batch_t *val) { lsm6dsv16bx_fifo_ctrl3_t fifo_ctrl3; @@ -5202,7 +5220,7 @@ int32_t lsm6dsv16bx_fifo_gy_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_mode_t val) { lsm6dsv16bx_fifo_ctrl4_t fifo_ctrl4; @@ -5226,7 +5244,7 @@ int32_t lsm6dsv16bx_fifo_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_mode_t *val) { lsm6dsv16bx_fifo_ctrl4_t fifo_ctrl4; @@ -5278,7 +5296,7 @@ int32_t lsm6dsv16bx_fifo_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_temp_batch_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_temp_batch_t val) { lsm6dsv16bx_fifo_ctrl4_t fifo_ctrl4; @@ -5302,7 +5320,7 @@ int32_t lsm6dsv16bx_fifo_temp_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_temp_batch_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_temp_batch_t *val) { lsm6dsv16bx_fifo_ctrl4_t fifo_ctrl4; @@ -5342,7 +5360,7 @@ int32_t lsm6dsv16bx_fifo_temp_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_timestamp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_timestamp_batch_t val) { lsm6dsv16bx_fifo_ctrl4_t fifo_ctrl4; @@ -5366,7 +5384,7 @@ int32_t lsm6dsv16bx_fifo_timestamp_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_timestamp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_timestamp_batch_t *val) { lsm6dsv16bx_fifo_ctrl4_t fifo_ctrl4; @@ -5406,15 +5424,22 @@ int32_t lsm6dsv16bx_fifo_timestamp_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_batch_counter_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { - uint8_t buff[2]; + lsm6dsv16bx_counter_bdr_reg1_t counter_bdr_reg1; + lsm6dsv16bx_counter_bdr_reg2_t counter_bdr_reg2; int32_t ret; - buff[1] = (uint8_t)(val / 256U); - buff[0] = (uint8_t)(val - (buff[1] * 256U)); - ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, (uint8_t *)&buff[0], 2); + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + + if (ret == 0) + { + counter_bdr_reg2.cnt_bdr_th = (uint8_t)val & 0xFFU; + counter_bdr_reg1.cnt_bdr_th = (uint8_t)(val >> 8) & 0x3U; + ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG2, (uint8_t *)&counter_bdr_reg2, 1); + } return ret; } @@ -5427,15 +5452,15 @@ int32_t lsm6dsv16bx_fifo_batch_counter_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, &buff[0], 2); - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + *val = (uint16_t)buff[0] & 0x3U; + *val = (*val * 256U) + (uint16_t)buff[1]; return ret; } @@ -5448,7 +5473,7 @@ int32_t lsm6dsv16bx_fifo_batch_counter_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_batch_ah_qvar_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_fifo_batch_ah_qvar_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_counter_bdr_reg1_t counter_bdr_reg1; int32_t ret; @@ -5471,7 +5496,7 @@ int32_t lsm6dsv16bx_fifo_batch_ah_qvar_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_batch_ah_qvar_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_fifo_batch_ah_qvar_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_counter_bdr_reg1_t counter_bdr_reg1; int32_t ret; @@ -5483,14 +5508,14 @@ int32_t lsm6dsv16bx_fifo_batch_ah_qvar_get(stmdev_ctx_t *ctx, uint8_t *val) } /** - * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope and EIS gyroscope.[set] + * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope.[set] * * @param ctx read / write interface definitions - * @param val XL_BATCH_EVENT, GY_BATCH_EVENT, GY_EIS_BATCH_EVENT, + * @param val XL_BATCH_EVENT, GY_BATCH_EVENT * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_batch_cnt_event_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_batch_cnt_event_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_batch_cnt_event_t val) { lsm6dsv16bx_counter_bdr_reg1_t counter_bdr_reg1; @@ -5508,14 +5533,14 @@ int32_t lsm6dsv16bx_fifo_batch_cnt_event_set(stmdev_ctx_t *ctx, } /** - * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope and EIS gyroscope.[get] + * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope.[get] * * @param ctx read / write interface definitions - * @param val XL_BATCH_EVENT, GY_BATCH_EVENT, GY_EIS_BATCH_EVENT, + * @param val XL_BATCH_EVENT, GY_BATCH_EVENT * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_batch_cnt_event_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_batch_cnt_event_t *val) { lsm6dsv16bx_counter_bdr_reg1_t counter_bdr_reg1; @@ -5532,10 +5557,6 @@ int32_t lsm6dsv16bx_fifo_batch_cnt_event_get(stmdev_ctx_t *ctx, *val = LSM6DSV16BX_GY_BATCH_EVENT; break; - case LSM6DSV16BX_GY_EIS_BATCH_EVENT: - *val = LSM6DSV16BX_GY_EIS_BATCH_EVENT; - break; - default: *val = LSM6DSV16BX_XL_BATCH_EVENT; break; @@ -5551,7 +5572,7 @@ int32_t lsm6dsv16bx_fifo_batch_cnt_event_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_sflp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_sflp_batch_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_sflp_raw_t val) { lsm6dsv16bx_emb_func_fifo_en_a_t emb_func_fifo_en_a; @@ -5581,7 +5602,7 @@ int32_t lsm6dsv16bx_fifo_sflp_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_sflp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_sflp_batch_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_sflp_raw_t *val) { lsm6dsv16bx_emb_func_fifo_en_a_t emb_func_fifo_en_a; @@ -5610,7 +5631,7 @@ int32_t lsm6dsv16bx_fifo_sflp_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_status_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_status_t *val) { uint8_t buff[2]; @@ -5635,17 +5656,11 @@ int32_t lsm6dsv16bx_fifo_status_get(stmdev_ctx_t *ctx, * @brief FIFO data output[get] * * @param ctx read / write interface definitions - * @param val FIFO_EMPTY, GY_NC_TAG, XL_NC_TAG, TIMESTAMP_TAG, - TEMPERATURE_TAG, CFG_CHANGE_TAG, XL_NC_T_2_TAG, - XL_NC_T_1_TAG, XL_2XC_TAG, XL_3XC_TAG, GY_NC_T_2_TAG, - GY_NC_T_1_TAG, GY_2XC_TAG, GY_3XC_TAG, STEP_COUNTER_TAG, - SFLP_GAME_ROTATION_VECTOR_TAG, SFLP_GYROSCOPE_BIAS_TAG, - SFLP_GRAVITY_VECTOR_TAG, MLC_RESULT_TAG, - MLC_FILTER, MLC_FEATURE, XL_DUAL_CORE, AH_QVAR, + * @param val lsm6dsv16bx_fifo_out_raw_t enum * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_out_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_out_raw_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_out_raw_t *val) { lsm6dsv16bx_fifo_data_out_tag_t fifo_data_out_tag; @@ -5774,7 +5789,7 @@ int32_t lsm6dsv16bx_fifo_out_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_stpcnt_batch_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_emb_func_fifo_en_a_t emb_func_fifo_en_a; int32_t ret; @@ -5804,7 +5819,7 @@ int32_t lsm6dsv16bx_fifo_stpcnt_batch_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_stpcnt_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_emb_func_fifo_en_a_t emb_func_fifo_en_a; int32_t ret; @@ -5831,7 +5846,7 @@ int32_t lsm6dsv16bx_fifo_stpcnt_batch_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_mlc_batch_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_fifo_mlc_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_emb_func_fifo_en_a_t emb_func_fifo_en_a; int32_t ret; @@ -5861,7 +5876,7 @@ int32_t lsm6dsv16bx_fifo_mlc_batch_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_mlc_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_fifo_mlc_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_emb_func_fifo_en_a_t emb_func_fifo_en_a; int32_t ret; @@ -5887,7 +5902,7 @@ int32_t lsm6dsv16bx_fifo_mlc_batch_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_mlc_filt_batch_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_fifo_mlc_filt_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_emb_func_fifo_en_b_t emb_func_fifo_en_b; int32_t ret; @@ -5917,7 +5932,7 @@ int32_t lsm6dsv16bx_fifo_mlc_filt_batch_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fifo_mlc_filt_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_fifo_mlc_filt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_emb_func_fifo_en_b_t emb_func_fifo_en_b; int32_t ret; @@ -5955,7 +5970,7 @@ int32_t lsm6dsv16bx_fifo_mlc_filt_batch_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_stpcnt_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_stpcnt_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_stpcnt_mode_t val) { lsm6dsv16bx_emb_func_en_a_t emb_func_en_a; @@ -6007,7 +6022,7 @@ int32_t lsm6dsv16bx_stpcnt_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_stpcnt_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_stpcnt_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_stpcnt_mode_t *val) { lsm6dsv16bx_emb_func_en_a_t emb_func_en_a; @@ -6040,7 +6055,7 @@ int32_t lsm6dsv16bx_stpcnt_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsv16bx_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -6067,7 +6082,7 @@ int32_t lsm6dsv16bx_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_stpcnt_rst_step_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_stpcnt_rst_step_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_emb_func_src_t emb_func_src; int32_t ret; @@ -6097,7 +6112,7 @@ int32_t lsm6dsv16bx_stpcnt_rst_step_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_stpcnt_rst_step_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_emb_func_src_t emb_func_src; int32_t ret; @@ -6123,16 +6138,18 @@ int32_t lsm6dsv16bx_stpcnt_rst_step_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_pedo_deb_steps_conf_t pedo_deb_steps_conf; int32_t ret; - ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, + 1); if (ret == 0) { pedo_deb_steps_conf.deb_step = val; - ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, + 1); } return ret; @@ -6146,12 +6163,13 @@ int32_t lsm6dsv16bx_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_pedo_deb_steps_conf_t pedo_deb_steps_conf; int32_t ret; - ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, + 1); *val = pedo_deb_steps_conf.deb_step; return ret; @@ -6165,7 +6183,7 @@ int32_t lsm6dsv16bx_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsv16bx_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -6186,7 +6204,7 @@ int32_t lsm6dsv16bx_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsv16bx_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -6219,7 +6237,7 @@ int32_t lsm6dsv16bx_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -6249,7 +6267,7 @@ int32_t lsm6dsv16bx_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -6288,7 +6306,7 @@ int32_t lsm6dsv16bx_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -6317,7 +6335,7 @@ int32_t lsm6dsv16bx_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -6354,7 +6372,7 @@ int32_t lsm6dsv16bx_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_sflp_game_rotation_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsv16bx_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint16_t val) { lsm6dsv16bx_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -6381,7 +6399,7 @@ int32_t lsm6dsv16bx_sflp_game_rotation_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_sflp_game_rotation_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsv16bx_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm6dsv16bx_emb_func_en_a_t emb_func_en_a; int32_t ret; @@ -6406,7 +6424,7 @@ int32_t lsm6dsv16bx_sflp_game_rotation_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_sflp_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_sflp_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_sflp_data_rate_t val) { lsm6dsv16bx_sflp_odr_t sflp_odr; @@ -6434,7 +6452,7 @@ int32_t lsm6dsv16bx_sflp_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_sflp_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_sflp_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_sflp_data_rate_t *val) { lsm6dsv16bx_sflp_odr_t sflp_odr; @@ -6485,6 +6503,13 @@ int32_t lsm6dsv16bx_sflp_data_rate_get(stmdev_ctx_t *ctx, * * Released under BSD-3-Clause License */ + +#define NPY_HALF_GENERATE_OVERFLOW 0 /* do not trigger FP overflow */ +#define NPY_HALF_GENERATE_UNDERFLOW 0 /* do not trigger FP underflow */ +#ifndef NPY_HALF_ROUND_TIES_TO_EVEN +#define NPY_HALF_ROUND_TIES_TO_EVEN 1 +#endif + static uint16_t npy_floatbits_to_halfbits(uint32_t f) { uint32_t f_exp, f_sig; @@ -6644,7 +6669,7 @@ static uint16_t npy_float_to_half(float_t f) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_sflp_game_gbias_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_sflp_game_gbias_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_sflp_gbias_t *val) { lsm6dsv16bx_sflp_data_rate_t sflp_odr; @@ -6796,7 +6821,7 @@ int32_t lsm6dsv16bx_sflp_game_gbias_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_sflp_configure(stmdev_ctx_t *ctx) +int32_t lsm6dsv16bx_sflp_configure(const stmdev_ctx_t *ctx) { uint8_t val = 0x50; int32_t ret; @@ -6827,7 +6852,7 @@ int32_t lsm6dsv16bx_sflp_configure(stmdev_ctx_t *ctx) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fsm_permission_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fsm_permission_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_permission_t val) { lsm6dsv16bx_func_cfg_access_t func_cfg_access; @@ -6843,26 +6868,6 @@ int32_t lsm6dsv16bx_fsm_permission_set(stmdev_ctx_t *ctx, return ret; } -/** - * @brief Return the status of the CTRL registers permission (standard interface vs FSM).[get] - * - * @param ctx read / write interface definitions - * @param val 0: all FSM regs are under std_if control, 1: some regs are under FSM control. - * @retval interface status (MANDATORY: return 0 -> no Error) - * - */ -int32_t lsm6dsv16bx_fsm_permission_status_get(stmdev_ctx_t *ctx, - lsm6dsv16bx_fsm_permission_status_t *val) -{ - lsm6dsv16bx_ctrl_status_t status; - int32_t ret; - - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL_STATUS, (uint8_t *)&status, 1); - *val = (status.fsm_wr_ctrl_status == 0) ? LSM6DSV16BX_STD_IF_CONTROL : LSM6DSV16BX_FSM_CONTROL; - - return ret; -} - /** * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[get] * @@ -6871,7 +6876,7 @@ int32_t lsm6dsv16bx_fsm_permission_status_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fsm_permission_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fsm_permission_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_permission_t *val) { lsm6dsv16bx_func_cfg_access_t func_cfg_access; @@ -6896,21 +6901,21 @@ int32_t lsm6dsv16bx_fsm_permission_get(stmdev_ctx_t *ctx, } /** - * @brief Get the FSM permission status + * @brief Return the status of the CTRL registers permission (standard interface vs FSM).[get] * * @param ctx read / write interface definitions - * @param val 0: All reg writable from std if - 1: some regs are under FSM control. + * @param val 0: all FSM regs are under std_if control, 1: some regs are under FSM control. * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fsm_permission_status(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_fsm_permission_status(const stmdev_ctx_t *ctx, + lsm6dsv16bx_fsm_permission_status_t *val) { - lsm6dsv16bx_ctrl_status_t ctrl_status; + lsm6dsv16bx_ctrl_status_t status; int32_t ret; - ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL_STATUS, (uint8_t *)&ctrl_status, 1); - - *val = ctrl_status.fsm_wr_ctrl_status; + ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL_STATUS, (uint8_t *)&status, 1); + *val = (status.fsm_wr_ctrl_status == 0) ? LSM6DSV16BX_STD_IF_CONTROL : LSM6DSV16BX_FSM_CONTROL; return ret; } @@ -6923,7 +6928,7 @@ int32_t lsm6dsv16bx_fsm_permission_status(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fsm_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_mode_t val) +int32_t lsm6dsv16bx_fsm_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_mode_t val) { lsm6dsv16bx_emb_func_en_b_t emb_func_en_b; lsm6dsv16bx_fsm_enable_t fsm_enable; @@ -6977,7 +6982,7 @@ int32_t lsm6dsv16bx_fsm_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fsm_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_mode_t *val) +int32_t lsm6dsv16bx_fsm_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_mode_t *val) { lsm6dsv16bx_fsm_enable_t fsm_enable; int32_t ret; @@ -7010,7 +7015,7 @@ int32_t lsm6dsv16bx_fsm_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fsm_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsv16bx_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -7037,7 +7042,7 @@ int32_t lsm6dsv16bx_fsm_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fsm_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsv16bx_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -7064,7 +7069,7 @@ int32_t lsm6dsv16bx_fsm_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_out_t *val) +int32_t lsm6dsv16bx_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_out_t *val) { int32_t ret; @@ -7087,7 +7092,7 @@ int32_t lsm6dsv16bx_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_out_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fsm_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fsm_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_data_rate_t val) { lsm6dsv16bx_fsm_odr_t fsm_odr; @@ -7118,7 +7123,7 @@ int32_t lsm6dsv16bx_fsm_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fsm_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fsm_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_data_rate_t *val) { lsm6dsv16bx_fsm_odr_t fsm_odr; @@ -7177,7 +7182,7 @@ int32_t lsm6dsv16bx_fsm_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fsm_long_cnt_timeout_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsv16bx_fsm_long_cnt_timeout_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -7197,7 +7202,7 @@ int32_t lsm6dsv16bx_fsm_long_cnt_timeout_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fsm_long_cnt_timeout_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsv16bx_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -7217,7 +7222,7 @@ int32_t lsm6dsv16bx_fsm_long_cnt_timeout_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_fsm_programs_t fsm_programs; int32_t ret; @@ -7240,7 +7245,7 @@ int32_t lsm6dsv16bx_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_fsm_programs_t fsm_programs; int32_t ret; @@ -7260,7 +7265,7 @@ int32_t lsm6dsv16bx_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsv16bx_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -7280,7 +7285,7 @@ int32_t lsm6dsv16bx_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsv16bx_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -7313,7 +7318,7 @@ int32_t lsm6dsv16bx_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_mlc_set(stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_mode_t val) +int32_t lsm6dsv16bx_mlc_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_mode_t val) { lsm6dsv16bx_emb_func_en_b_t emb_en_b; lsm6dsv16bx_emb_func_en_a_t emb_en_a; @@ -7326,7 +7331,7 @@ int32_t lsm6dsv16bx_mlc_set(stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_mode_t val) ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); - switch(val) + switch (val) { case LSM6DSV16BX_MLC_OFF: emb_en_a.mlc_before_fsm_en = 0; @@ -7361,7 +7366,7 @@ int32_t lsm6dsv16bx_mlc_set(stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_mlc_get(stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_mode_t *val) +int32_t lsm6dsv16bx_mlc_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_mode_t *val) { lsm6dsv16bx_emb_func_en_b_t emb_en_b; lsm6dsv16bx_emb_func_en_a_t emb_en_a; @@ -7405,7 +7410,7 @@ int32_t lsm6dsv16bx_mlc_get(stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_mlc_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_mlc_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_data_rate_t val) { lsm6dsv16bx_mlc_odr_t mlc_odr; @@ -7436,7 +7441,7 @@ int32_t lsm6dsv16bx_mlc_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_mlc_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_mlc_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_data_rate_t *val) { lsm6dsv16bx_mlc_odr_t mlc_odr; @@ -7495,7 +7500,7 @@ int32_t lsm6dsv16bx_mlc_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_mlc_out_get(stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_out_t *val) +int32_t lsm6dsv16bx_mlc_out_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_out_t *val) { int32_t ret; @@ -7510,14 +7515,17 @@ int32_t lsm6dsv16bx_mlc_out_get(stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_out_t *val) } /** - * @brief Qvar sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the Qvar sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set] + * @brief Qvar sensor sensitivity value register for the Machine Learning Core. + * This register corresponds to the conversion value of the Qvar sensor. + * The register value is expressed as half-precision floating-point format: + * SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set] * * @param ctx read / write interface definitions - * @param val Qvar sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the Qvar sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). + * @param val Qvar sensor sensitivity value register for the Machine Learning Core. * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_mlc_qvar_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsv16bx_mlc_qvar_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -7530,14 +7538,17 @@ int32_t lsm6dsv16bx_mlc_qvar_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) } /** - * @brief Qvar sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the Qvar sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get] + * @brief Qvar sensor sensitivity value register for the Machine Learning Core. + * This register corresponds to the conversion value of the Qvar sensor. + * The register value is expressed as half-precision floating-point format: + * SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get] * * @param ctx read / write interface definitions - * @param val Qvar sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the Qvar sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). + * @param val Qvar sensor sensitivity value register for the Machine Learning Core. * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_mlc_qvar_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsv16bx_mlc_qvar_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -7570,7 +7581,7 @@ int32_t lsm6dsv16bx_mlc_qvar_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_xl_offset_on_out_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_xl_offset_on_out_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_ctrl9_t ctrl9; int32_t ret; @@ -7593,7 +7604,7 @@ int32_t lsm6dsv16bx_xl_offset_on_out_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_xl_offset_on_out_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_ctrl9_t ctrl9; int32_t ret; @@ -7612,8 +7623,8 @@ int32_t lsm6dsv16bx_xl_offset_on_out_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_xl_offset_mg_set(stmdev_ctx_t *ctx, - lsm6dsv16bxxl_offset_mg_t val) +int32_t lsm6dsv16bx_xl_offset_mg_set(const stmdev_ctx_t *ctx, + lsm6dsv16bx_xl_offset_mg_t val) { lsm6dsv16bx_z_ofs_usr_t z_ofs_usr; lsm6dsv16bx_y_ofs_usr_t y_ofs_usr; @@ -7702,8 +7713,8 @@ int32_t lsm6dsv16bx_xl_offset_mg_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_xl_offset_mg_get(stmdev_ctx_t *ctx, - lsm6dsv16bxxl_offset_mg_t *val) +int32_t lsm6dsv16bx_xl_offset_mg_get(const stmdev_ctx_t *ctx, + lsm6dsv16bx_xl_offset_mg_t *val) { lsm6dsv16bx_z_ofs_usr_t z_ofs_usr; lsm6dsv16bx_y_ofs_usr_t y_ofs_usr; @@ -7755,14 +7766,16 @@ int32_t lsm6dsv16bx_xl_offset_mg_get(stmdev_ctx_t *ctx, */ /** - * @brief Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/Qvar1 and SCx/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode.[set] + * @brief Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are + * connected to the AH1/Qvar1 and AH1/Qvar2 pins. Before setting this bit to 1, + * the accelerometer and gyroscope sensor have to be configured in power-down mode.[set] * * @param ctx read / write interface definitions - * @param val Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/Qvar1 and SCx/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode. + * @param val 1: Enables AH_QVAR chain, 0: Disable the AH_QVAR chain * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_ah_qvar_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_ah_qvar_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_ah_qvar_mode_t val) { lsm6dsv16bx_ctrl10_t ctrl10; @@ -7798,14 +7811,16 @@ int32_t lsm6dsv16bx_ah_qvar_mode_set(stmdev_ctx_t *ctx, } /** - * @brief Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/Qvar1 and SCx/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode.[get] + * @brief Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are + * connected to the AH1/Qvar1 and AH1/Qvar2 pins. Before setting this bit to 1, + * the accelerometer and gyroscope sensor have to be configured in power-down mode.[get] * * @param ctx read / write interface definitions - * @param val Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/Qvar1 and SCx/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode. + * @param val 1: Enables AH_QVAR chain, 0: Disable the AH_QVAR chain * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_ah_qvar_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_ah_qvar_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_ah_qvar_mode_t *val) { lsm6dsv16bx_ctrl10_t ctrl10; @@ -7833,7 +7848,7 @@ int32_t lsm6dsv16bx_ah_qvar_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_ah_qvar_zin_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_ah_qvar_zin_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_ah_qvar_zin_t val) { lsm6dsv16bx_ctrl7_t ctrl7; @@ -7857,7 +7872,7 @@ int32_t lsm6dsv16bx_ah_qvar_zin_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_ah_qvar_zin_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_ah_qvar_zin_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_ah_qvar_zin_t *val) { lsm6dsv16bx_ctrl7_t ctrl7; @@ -7890,14 +7905,17 @@ int32_t lsm6dsv16bx_ah_qvar_zin_get(stmdev_ctx_t *ctx, } /** - * @brief Qvar sensor sensitivity value register for the Finite State Machine. This register corresponds to the conversion value of the Qvar sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set] + * @brief Qvar sensor sensitivity value register for the Finite State Machine. + * This register corresponds to the conversion value of the Qvar sensor. + * The register value is expressed as half-precision floating-point format: + * SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set] * * @param ctx read / write interface definitions - * @param val Qvar sensor sensitivity value register for the Finite State Machine. This register corresponds to the conversion value of the Qvar sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). + * @param val Qvar sensor sensitivity value register for the Finite State Machine. * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fsm_qvar_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsv16bx_fsm_qvar_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -7910,14 +7928,17 @@ int32_t lsm6dsv16bx_fsm_qvar_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) } /** - * @brief Qvar sensor sensitivity value register for the Finite State Machine. This register corresponds to the conversion value of the Qvar sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get] + * @brief Qvar sensor sensitivity value register for the Finite State Machine. + * This register corresponds to the conversion value of the Qvar sensor. + * The register value is expressed as half-precision floating-point format: + * SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get] * * @param ctx read / write interface definitions - * @param val Qvar sensor sensitivity value register for the Finite State Machine. This register corresponds to the conversion value of the Qvar sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). + * @param val Qvar sensor sensitivity value register for the Finite State Machine. * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_fsm_qvar_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsv16bx_fsm_qvar_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -7950,7 +7971,7 @@ int32_t lsm6dsv16bx_fsm_qvar_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_i3c_reset_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_i3c_reset_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_i3c_reset_mode_t val) { lsm6dsv16bx_pin_ctrl_t pin_ctrl; @@ -7974,7 +7995,7 @@ int32_t lsm6dsv16bx_i3c_reset_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_i3c_reset_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_i3c_reset_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_i3c_reset_mode_t *val) { lsm6dsv16bx_pin_ctrl_t pin_ctrl; @@ -8019,7 +8040,7 @@ int32_t lsm6dsv16bx_i3c_reset_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tdm_dis_wclk_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_tdm_dis_wclk_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_pin_ctrl_t pin_ctrl; int32_t ret; @@ -8042,7 +8063,7 @@ int32_t lsm6dsv16bx_tdm_dis_wclk_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tdm_dis_wclk_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_tdm_dis_wclk_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_pin_ctrl_t pin_ctrl; int32_t ret; @@ -8061,7 +8082,7 @@ int32_t lsm6dsv16bx_tdm_dis_wclk_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tdm_tdmout_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_tdm_tdmout_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_if_cfg_t if_cfg; int32_t ret; @@ -8084,7 +8105,7 @@ int32_t lsm6dsv16bx_tdm_tdmout_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tdm_tdmout_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_tdm_tdmout_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_if_cfg_t if_cfg; int32_t ret; @@ -8103,7 +8124,7 @@ int32_t lsm6dsv16bx_tdm_tdmout_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tdm_wclk_bclk_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tdm_wclk_bclk_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_wclk_bclk_t val) { lsm6dsv16bx_tdm_cfg0_t tdm_cfg0; @@ -8128,7 +8149,7 @@ int32_t lsm6dsv16bx_tdm_wclk_bclk_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tdm_wclk_bclk_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tdm_wclk_bclk_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_wclk_bclk_t *val) { lsm6dsv16bx_tdm_cfg0_t tdm_cfg0; @@ -8160,7 +8181,7 @@ int32_t lsm6dsv16bx_tdm_wclk_bclk_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tdm_slot_set(stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_slot_t val) +int32_t lsm6dsv16bx_tdm_slot_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_slot_t val) { lsm6dsv16bx_tdm_cfg0_t tdm_cfg0; int32_t ret; @@ -8183,7 +8204,7 @@ int32_t lsm6dsv16bx_tdm_slot_set(stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_slot_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tdm_slot_get(stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_slot_t *val) +int32_t lsm6dsv16bx_tdm_slot_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_slot_t *val) { lsm6dsv16bx_tdm_cfg0_t tdm_cfg0; int32_t ret; @@ -8214,7 +8235,7 @@ int32_t lsm6dsv16bx_tdm_slot_get(stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_slot_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tdm_bclk_edge_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tdm_bclk_edge_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_bclk_edge_t val) { lsm6dsv16bx_tdm_cfg0_t tdm_cfg0; @@ -8238,7 +8259,7 @@ int32_t lsm6dsv16bx_tdm_bclk_edge_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tdm_bclk_edge_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tdm_bclk_edge_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_bclk_edge_t *val) { lsm6dsv16bx_tdm_cfg0_t tdm_cfg0; @@ -8270,7 +8291,7 @@ int32_t lsm6dsv16bx_tdm_bclk_edge_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tdm_delayed_conf_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16bx_tdm_delayed_conf_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16bx_tdm_cfg0_t tdm_cfg0; int32_t ret; @@ -8293,7 +8314,7 @@ int32_t lsm6dsv16bx_tdm_delayed_conf_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tdm_delayed_conf_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16bx_tdm_delayed_conf_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16bx_tdm_cfg0_t tdm_cfg0; int32_t ret; @@ -8313,7 +8334,7 @@ int32_t lsm6dsv16bx_tdm_delayed_conf_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tdm_axis_order_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tdm_axis_order_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_axis_order_t val) { lsm6dsv16bx_tdm_cfg1_t tdm_cfg1; @@ -8337,7 +8358,7 @@ int32_t lsm6dsv16bx_tdm_axis_order_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tdm_axis_order_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tdm_axis_order_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_axis_order_t *val) { lsm6dsv16bx_tdm_cfg1_t tdm_cfg1; @@ -8373,7 +8394,7 @@ int32_t lsm6dsv16bx_tdm_axis_order_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tdm_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tdm_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_xl_full_scale_t val) { lsm6dsv16bx_tdm_cfg2_t tdm_cfg2; @@ -8397,7 +8418,7 @@ int32_t lsm6dsv16bx_tdm_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16bx_tdm_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tdm_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_xl_full_scale_t *val) { lsm6dsv16bx_tdm_cfg2_t tdm_cfg2; diff --git a/sensor/stmemsc/lsm6dsv16bx_STdC/driver/lsm6dsv16bx_reg.h b/sensor/stmemsc/lsm6dsv16bx_STdC/driver/lsm6dsv16bx_reg.h index a39877fc..d65502c1 100644 --- a/sensor/stmemsc/lsm6dsv16bx_STdC/driver/lsm6dsv16bx_reg.h +++ b/sensor/stmemsc/lsm6dsv16bx_STdC/driver/lsm6dsv16bx_reg.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2022 STMicroelectronics. + *

© Copyright (c) 2024 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -799,65 +799,65 @@ typedef struct #endif /* DRV_BYTE_ORDER */ } lsm6dsv16bx_outx_h_a_t; -#define LSM6DSV16BX_UI_OUTZ_L_A_OIS_DUALC 0x34U +#define LSM6DSV16BX_UI_OUTZ_L_A_DUALC 0x34U typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t ui_outz_a_ois_dualc : 8; + uint8_t ui_outz_a_dualc : 8; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t ui_outz_a_ois_dualc : 8; + uint8_t ui_outz_a_dualc : 8; #endif /* DRV_BYTE_ORDER */ -} lsm6dsv16bx_ui_outz_l_a_ois_dualc_t; +} lsm6dsv16bx_ui_outz_l_a_dualc_t; -#define LSM6DSV16BX_UI_OUTZ_H_A_OIS_DUALC 0x35U +#define LSM6DSV16BX_UI_OUTZ_H_A_DUALC 0x35U typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t ui_outz_a_ois_dualc : 8; + uint8_t ui_outz_a_dualc : 8; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t ui_outz_a_ois_dualc : 8; + uint8_t ui_outz_a_dualc : 8; #endif /* DRV_BYTE_ORDER */ -} lsm6dsv16bx_ui_outz_h_a_ois_dualc_t; +} lsm6dsv16bx_ui_outz_h_a_dualc_t; -#define LSM6DSV16BX_UI_OUTY_L_A_OIS_DUALC 0x36U +#define LSM6DSV16BX_UI_OUTY_L_A_DUALC 0x36U typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t ui_outy_a_ois_dualc : 8; + uint8_t ui_outy_a_dualc : 8; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t ui_outy_a_ois_dualc : 8; + uint8_t ui_outy_a_dualc : 8; #endif /* DRV_BYTE_ORDER */ -} lsm6dsv16bx_ui_outy_l_a_ois_dualc_t; +} lsm6dsv16bx_ui_outy_l_a_dualc_t; -#define LSM6DSV16BX_UI_OUTY_H_A_OIS_DUALC 0x37U +#define LSM6DSV16BX_UI_OUTY_H_A_DUALC 0x37U typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t ui_outy_a_ois_dualc : 8; + uint8_t ui_outy_a_dualc : 8; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t ui_outy_a_ois_dualc : 8; + uint8_t ui_outy_a_dualc : 8; #endif /* DRV_BYTE_ORDER */ -} lsm6dsv16bx_ui_outy_h_a_ois_dualc_t; +} lsm6dsv16bx_ui_outy_h_a_dualc_t; -#define LSM6DSV16BX_UI_OUTX_L_A_OIS_DUALC 0x38U +#define LSM6DSV16BX_UI_OUTX_L_A_DUALC 0x38U typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t ui_outx_a_ois_dualc : 8; + uint8_t ui_outx_a_dualc : 8; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t ui_outx_a_ois_dualc : 8; + uint8_t ui_outx_a_dualc : 8; #endif /* DRV_BYTE_ORDER */ -} lsm6dsv16bx_ui_outx_l_a_ois_dualc_t; +} lsm6dsv16bx_ui_outx_l_a_dualc_t; -#define LSM6DSV16BX_UI_OUTX_H_A_OIS_DUALC 0x39U +#define LSM6DSV16BX_UI_OUTX_H_A_DUALC 0x39U typedef struct { #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t ui_outx_a_ois_dualc : 8; + uint8_t ui_outx_a_dualc : 8; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t ui_outx_a_ois_dualc : 8; + uint8_t ui_outx_a_dualc : 8; #endif /* DRV_BYTE_ORDER */ -} lsm6dsv16bx_ui_outx_h_a_ois_dualc_t; +} lsm6dsv16bx_ui_outx_h_a_dualc_t; #define LSM6DSV16BX_AH_QVAR_OUT_L 0x3AU typedef struct @@ -1285,9 +1285,11 @@ typedef struct uint8_t emb_func_disable : 1; uint8_t emb_func_irq_mask_xl_settl : 1; uint8_t emb_func_irq_mask_g_settl : 1; - uint8_t not_used1 : 2; + uint8_t not_used1 : 1; + uint8_t xl_dualc_batch_from_if : 1; #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used1 : 2; + uint8_t xl_dualc_batch_from_if : 1; + uint8_t not_used1 : 1; uint8_t emb_func_irq_mask_g_settl : 1; uint8_t emb_func_irq_mask_xl_settl : 1; uint8_t emb_func_disable : 1; @@ -1351,24 +1353,6 @@ typedef struct #endif /* DRV_BYTE_ORDER */ } lsm6dsv16bx_tdm_cfg2_t; -#define LSM6DSV16BX_UI_INT_OIS 0x6FU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t not_used0 : 4; - uint8_t st_ois_clampdis : 1; - uint8_t not_used1 : 1; - uint8_t drdy_mask_ois : 1; - uint8_t int2_drdy_ois : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t int2_drdy_ois : 1; - uint8_t drdy_mask_ois : 1; - uint8_t not_used1 : 1; - uint8_t st_ois_clampdis : 1; - uint8_t not_used0 : 4; -#endif /* DRV_BYTE_ORDER */ -} lsm6dsv16bx_ui_int_ois_t; - #define LSM6DSV16BX_Z_OFS_USR 0x73U typedef struct { @@ -2501,12 +2485,12 @@ typedef union lsm6dsv16bx_outy_h_a_t outy_h_a; lsm6dsv16bx_outx_l_a_t outx_l_a; lsm6dsv16bx_outx_h_a_t outx_h_a; - lsm6dsv16bx_ui_outz_l_a_ois_dualc_t ui_outz_l_a_ois_dualc; - lsm6dsv16bx_ui_outz_h_a_ois_dualc_t ui_outz_h_a_ois_dualc; - lsm6dsv16bx_ui_outy_l_a_ois_dualc_t ui_outy_l_a_ois_dualc; - lsm6dsv16bx_ui_outy_h_a_ois_dualc_t ui_outy_h_a_ois_dualc; - lsm6dsv16bx_ui_outx_l_a_ois_dualc_t ui_outx_l_a_ois_dualc; - lsm6dsv16bx_ui_outx_h_a_ois_dualc_t ui_outx_h_a_ois_dualc; + lsm6dsv16bx_ui_outz_l_a_dualc_t ui_outz_l_a_dualc; + lsm6dsv16bx_ui_outz_h_a_dualc_t ui_outz_h_a_dualc; + lsm6dsv16bx_ui_outy_l_a_dualc_t ui_outy_l_a_dualc; + lsm6dsv16bx_ui_outy_h_a_dualc_t ui_outy_h_a_dualc; + lsm6dsv16bx_ui_outx_l_a_dualc_t ui_outx_l_a_dualc; + lsm6dsv16bx_ui_outx_h_a_dualc_t ui_outx_h_a_dualc; lsm6dsv16bx_ah_qvar_out_l_t ah_qvar_out_l; lsm6dsv16bx_ah_qvar_out_h_t ah_qvar_out_h; lsm6dsv16bx_timestamp0_t timestamp0; @@ -2537,7 +2521,6 @@ typedef union lsm6dsv16bx_tdm_cfg0_t tdm_cfg0; lsm6dsv16bx_tdm_cfg1_t tdm_cfg1; lsm6dsv16bx_tdm_cfg2_t tdm_cfg2; - lsm6dsv16bx_ui_int_ois_t ui_int_ois; lsm6dsv16bx_z_ofs_usr_t z_ofs_usr; lsm6dsv16bx_y_ofs_usr_t y_ofs_usr; lsm6dsv16bx_x_ofs_usr_t x_ofs_usr; @@ -2624,10 +2607,10 @@ typedef union * them with a custom implementation. */ -int32_t lsm6dsv16bx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm6dsv16bx_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lsm6dsv16bx_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm6dsv16bx_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -2657,19 +2640,19 @@ typedef enum LSM6DSV16BX_RESTORE_CAL_PARAM = 0x2, LSM6DSV16BX_RESTORE_CTRL_REGS = 0x4, } lsm6dsv16bx_reset_t; -int32_t lsm6dsv16bx_reset_set(stmdev_ctx_t *ctx, lsm6dsv16bx_reset_t val); -int32_t lsm6dsv16bx_reset_get(stmdev_ctx_t *ctx, lsm6dsv16bx_reset_t *val); +int32_t lsm6dsv16bx_reset_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_reset_t val); +int32_t lsm6dsv16bx_reset_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_reset_t *val); typedef enum { LSM6DSV16BX_MAIN_MEM_BANK = 0x0, LSM6DSV16BX_EMBED_FUNC_MEM_BANK = 0x1, } lsm6dsv16bx_mem_bank_t; -int32_t lsm6dsv16bx_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsv16bx_mem_bank_t val); -int32_t lsm6dsv16bx_mem_bank_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_mem_bank_t val); +int32_t lsm6dsv16bx_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_mem_bank_t *val); -int32_t lsm6dsv16bx_device_id_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2687,22 +2670,21 @@ typedef enum LSM6DSV16BX_XL_ODR_AT_3840Hz = 0xB, LSM6DSV16BX_XL_ODR_AT_7680Hz = 0xC, } lsm6dsv16bx_xl_data_rate_t; -int32_t lsm6dsv16bx_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_xl_data_rate_t val); -int32_t lsm6dsv16bx_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_xl_data_rate_t *val); typedef enum { LSM6DSV16BX_XL_HIGH_PERFORMANCE_MD = 0x0, - LSM6DSV16BX_XL_HIGH_ACCURANCY_ODR_MD = 0x1, + LSM6DSV16BX_XL_HIGH_PERFORMANCE_TDM_MD = 0x2, LSM6DSV16BX_XL_LOW_POWER_2_AVG_MD = 0x4, LSM6DSV16BX_XL_LOW_POWER_4_AVG_MD = 0x5, LSM6DSV16BX_XL_LOW_POWER_8_AVG_MD = 0x6, - LSM6DSV16BX_XL_NORMAL_MD = 0x7, } lsm6dsv16bx_xl_mode_t; -int32_t lsm6dsv16bx_xl_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_mode_t val); -int32_t lsm6dsv16bx_xl_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_mode_t *val); +int32_t lsm6dsv16bx_xl_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_xl_mode_t val); +int32_t lsm6dsv16bx_xl_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_xl_mode_t *val); typedef enum { @@ -2719,35 +2701,34 @@ typedef enum LSM6DSV16BX_GY_ODR_AT_3840Hz = 0xb, LSM6DSV16BX_GY_ODR_AT_7680Hz = 0xc, } lsm6dsv16bx_gy_data_rate_t; -int32_t lsm6dsv16bx_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_gy_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_gy_data_rate_t val); -int32_t lsm6dsv16bx_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_gy_data_rate_t *val); typedef enum { LSM6DSV16BX_GY_HIGH_PERFORMANCE_MD = 0x0, - LSM6DSV16BX_GY_HIGH_ACCURANCY_ODR_MD = 0x1, LSM6DSV16BX_GY_SLEEP_MD = 0x4, LSM6DSV16BX_GY_LOW_POWER_MD = 0x5, } lsm6dsv16bx_gy_mode_t; -int32_t lsm6dsv16bx_gy_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_gy_mode_t val); -int32_t lsm6dsv16bx_gy_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_gy_mode_t *val); +int32_t lsm6dsv16bx_gy_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_gy_mode_t val); +int32_t lsm6dsv16bx_gy_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_gy_mode_t *val); -int32_t lsm6dsv16bx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16bx_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSV16BX_DRDY_LATCHED = 0x0, LSM6DSV16BX_DRDY_PULSED = 0x1, } lsm6dsv16bx_data_ready_mode_t; -int32_t lsm6dsv16bx_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_data_ready_mode_t val); -int32_t lsm6dsv16bx_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_data_ready_mode_t *val); typedef enum @@ -2759,9 +2740,9 @@ typedef enum LSM6DSV16BX_2000dps = 0x4, LSM6DSV16BX_4000dps = 0xc, } lsm6dsv16bx_gy_full_scale_t; -int32_t lsm6dsv16bx_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_gy_full_scale_t val); -int32_t lsm6dsv16bx_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_gy_full_scale_t *val); typedef enum @@ -2771,13 +2752,13 @@ typedef enum LSM6DSV16BX_8g = 0x2, LSM6DSV16BX_16g = 0x3, } lsm6dsv16bx_xl_full_scale_t; -int32_t lsm6dsv16bx_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_xl_full_scale_t val); -int32_t lsm6dsv16bx_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_xl_full_scale_t *val); -int32_t lsm6dsv16bx_xl_dual_channel_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_xl_dual_channel_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_xl_dual_channel_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -2787,9 +2768,9 @@ typedef enum LSM6DSV16BX_XL_ST_OFFSET_POS = 0x5, LSM6DSV16BX_XL_ST_OFFSET_NEG = 0x6, } lsm6dsv16bx_xl_self_test_t; -int32_t lsm6dsv16bx_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_xl_self_test_t val); -int32_t lsm6dsv16bx_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_xl_self_test_t *val); typedef enum @@ -2798,9 +2779,9 @@ typedef enum LSM6DSV16BX_GY_ST_POSITIVE = 0x1, LSM6DSV16BX_GY_ST_NEGATIVE = 0x2, } lsm6dsv16bx_gy_self_test_t; -int32_t lsm6dsv16bx_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_gy_self_test_t val); -int32_t lsm6dsv16bx_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_gy_self_test_t *val); typedef struct @@ -2858,7 +2839,7 @@ typedef struct uint8_t fifo_ovr : 1; uint8_t fifo_th : 1; } lsm6dsv16bx_all_sources_t; -int32_t lsm6dsv16bx_all_sources_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_all_sources_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_all_sources_t *val); typedef struct @@ -2866,52 +2847,53 @@ typedef struct uint8_t drdy_xl : 1; uint8_t drdy_gy : 1; uint8_t drdy_temp : 1; + uint8_t drdy_ah_qvar : 1; } lsm6dsv16bx_data_ready_t; -int32_t lsm6dsv16bx_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_flag_data_ready_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_data_ready_t *val); -int32_t lsm6dsv16bx_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsv16bx_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsv16bx_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsv16bx_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsv16bx_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsv16bx_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsv16bx_dual_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsv16bx_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsv16bx_ois_dual_acceleration_raw_get(stmdev_ctx_t *ctx, - int16_t *val); +int32_t lsm6dsv16bx_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, + int16_t *val); -int32_t lsm6dsv16bx_ah_qvar_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsv16bx_ah_qvar_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsv16bx_odr_cal_reg_get(stmdev_ctx_t *ctx, int8_t *val); +int32_t lsm6dsv16bx_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val); typedef struct { uint8_t x : 1; uint8_t y : 1; uint8_t z : 1; -} lsm6dsv16bx_xl_axis_t; -int32_t lsm6dsv16bx_xl_axis_set(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_axis_t val); -int32_t lsm6dsv16bx_xl_axis_get(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_axis_t *val); +} lsm6dsv16bx_tdm_xl_axis_t; +int32_t lsm6dsv16bx_tdm_xl_axis_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_xl_axis_t val); +int32_t lsm6dsv16bx_tdm_xl_axis_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_xl_axis_t *val); -int32_t lsm6dsv16bx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dsv16bx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); -int32_t lsm6dsv16bx_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dsv16bx_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); -int32_t lsm6dsv16bx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16bx_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); +int32_t lsm6dsv16bx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); typedef enum { LSM6DSV16BX_AUTO = 0x0, LSM6DSV16BX_ALWAYS_ACTIVE = 0x1, } lsm6dsv16bx_filt_anti_spike_t; -int32_t lsm6dsv16bx_filt_anti_spike_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_anti_spike_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_anti_spike_t val); -int32_t lsm6dsv16bx_filt_anti_spike_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_anti_spike_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_anti_spike_t *val); typedef struct @@ -2921,9 +2903,9 @@ typedef struct uint8_t irq_g : 1; uint8_t tdm_excep_code : 1; } lsm6dsv16bx_filt_settling_mask_t; -int32_t lsm6dsv16bx_filt_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_settling_mask_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_settling_mask_t val); -int32_t lsm6dsv16bx_filt_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_settling_mask_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_settling_mask_t *val); typedef enum @@ -2937,22 +2919,22 @@ typedef enum LSM6DSV16BX_GY_AGGRESSIVE = 0x6, LSM6DSV16BX_GY_XTREME = 0x7, } lsm6dsv16bx_filt_gy_lp1_bandwidth_t; -int32_t lsm6dsv16bx_filt_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_gy_lp1_bandwidth_t val); -int32_t lsm6dsv16bx_filt_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_gy_lp1_bandwidth_t *val); -int32_t lsm6dsv16bx_filt_gy_lp1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_filt_gy_lp1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_filt_gy_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { uint8_t hpf : 1; uint8_t lpf : 1; } lsm6dsv16bx_filt_ah_qvar_conf_t; -int32_t lsm6dsv16bx_filt_ah_qvar_conf_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_ah_qvar_conf_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_ah_qvar_conf_t val); -int32_t lsm6dsv16bx_filt_ah_qvar_conf_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_ah_qvar_conf_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_ah_qvar_conf_t *val); typedef enum @@ -2966,28 +2948,28 @@ typedef enum LSM6DSV16BX_XL_AGGRESSIVE = 0x6, LSM6DSV16BX_XL_XTREME = 0x7, } lsm6dsv16bx_filt_xl_lp2_bandwidth_t; -int32_t lsm6dsv16bx_filt_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_xl_lp2_bandwidth_t val); -int32_t lsm6dsv16bx_filt_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_xl_lp2_bandwidth_t *val); -int32_t lsm6dsv16bx_filt_xl_lp2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_filt_xl_lp2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_filt_xl_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16bx_filt_xl_hp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_filt_xl_hp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_filt_xl_hp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16bx_filt_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_filt_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_filt_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSV16BX_HP_MD_NORMAL = 0x0, LSM6DSV16BX_HP_MD_REFERENCE = 0x1, } lsm6dsv16bx_filt_xl_hp_mode_t; -int32_t lsm6dsv16bx_filt_xl_hp_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_xl_hp_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_xl_hp_mode_t val); -int32_t lsm6dsv16bx_filt_xl_hp_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_xl_hp_mode_t *val); typedef enum @@ -2996,35 +2978,35 @@ typedef enum LSM6DSV16BX_WK_FEED_HIGH_PASS = 0x1, LSM6DSV16BX_WK_FEED_LP_WITH_OFFSET = 0x2, } lsm6dsv16bx_filt_wkup_act_feed_t; -int32_t lsm6dsv16bx_filt_wkup_act_feed_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_wkup_act_feed_t val); -int32_t lsm6dsv16bx_filt_wkup_act_feed_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_wkup_act_feed_t *val); -int32_t lsm6dsv16bx_mask_trigger_xl_settl_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_mask_trigger_xl_settl_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_mask_trigger_xl_settl_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSV16BX_SIXD_FEED_ODR_DIV_2 = 0x0, LSM6DSV16BX_SIXD_FEED_LOW_PASS = 0x1, } lsm6dsv16bx_filt_sixd_feed_t; -int32_t lsm6dsv16bx_filt_sixd_feed_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_sixd_feed_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_sixd_feed_t val); -int32_t lsm6dsv16bx_filt_sixd_feed_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_filt_sixd_feed_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_filt_sixd_feed_t *val); -int32_t lsm6dsv16bx_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSV16BX_I2C_I3C_ENABLE = 0x0, LSM6DSV16BX_I2C_I3C_DISABLE = 0x1, } lsm6dsv16bx_ui_i2c_i3c_mode_t; -int32_t lsm6dsv16bx_ui_i2c_i3c_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_ui_i2c_i3c_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_ui_i2c_i3c_mode_t val); -int32_t lsm6dsv16bx_ui_i2c_i3c_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_ui_i2c_i3c_mode_t *val); typedef enum @@ -3032,12 +3014,12 @@ typedef enum LSM6DSV16BX_SPI_4_WIRE = 0x0, LSM6DSV16BX_SPI_3_WIRE = 0x1, } lsm6dsv16bx_spi_mode_t; -int32_t lsm6dsv16bx_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_spi_mode_t val); -int32_t lsm6dsv16bx_spi_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_spi_mode_t val); +int32_t lsm6dsv16bx_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_spi_mode_t *val); -int32_t lsm6dsv16bx_ui_sda_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_ui_sda_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_ui_sda_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3046,9 +3028,9 @@ typedef enum LSM6DSV16BX_IBI_1ms = 0x2, LSM6DSV16BX_IBI_25ms = 0x3, } lsm6dsv16bx_i3c_ibi_time_t; -int32_t lsm6dsv16bx_i3c_ibi_time_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_i3c_ibi_time_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_i3c_ibi_time_t val); -int32_t lsm6dsv16bx_i3c_ibi_time_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_i3c_ibi_time_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_i3c_ibi_time_t *val); typedef enum @@ -3056,9 +3038,9 @@ typedef enum LSM6DSV16BX_PUSH_PULL = 0x0, LSM6DSV16BX_OPEN_DRAIN = 0x1, } lsm6dsv16bx_int_pin_mode_t; -int32_t lsm6dsv16bx_int_pin_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_int_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_int_pin_mode_t val); -int32_t lsm6dsv16bx_int_pin_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_int_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_int_pin_mode_t *val); typedef enum @@ -3066,62 +3048,18 @@ typedef enum LSM6DSV16BX_ACTIVE_HIGH = 0x0, LSM6DSV16BX_ACTIVE_LOW = 0x1, } lsm6dsv16bx_pin_polarity_t; -int32_t lsm6dsv16bx_pin_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_pin_polarity_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_pin_polarity_t val); -int32_t lsm6dsv16bx_pin_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_pin_polarity_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_pin_polarity_t *val); typedef struct { uint8_t boot : 1; - uint8_t drdy_ois : 1; - uint8_t drdy_xl : 1; - uint8_t drdy_gy : 1; - uint8_t drdy_temp : 1; - uint8_t fifo_th : 1; - uint8_t fifo_ovr : 1; - uint8_t fifo_full : 1; - uint8_t fifo_bdr : 1; - uint8_t den_flag : 1; - uint8_t timestamp : 1; // impact on int2 signals - uint8_t six_d : 1; - uint8_t double_tap : 1; - uint8_t free_fall : 1; - uint8_t wake_up : 1; - uint8_t single_tap : 1; - uint8_t sleep_change : 1; - uint8_t sleep_status : 1; - uint8_t step_detector : 1; - uint8_t step_count_overflow : 1; - uint8_t tilt : 1; - uint8_t sig_mot : 1; - uint8_t emb_func_stand_by : 1; // impact on int2 signals - uint8_t fsm_lc : 1; - uint8_t fsm1 : 1; - uint8_t fsm2 : 1; - uint8_t fsm3 : 1; - uint8_t fsm4 : 1; - uint8_t fsm5 : 1; - uint8_t fsm6 : 1; - uint8_t fsm7 : 1; - uint8_t fsm8 : 1; - uint8_t mlc1 : 1; - uint8_t mlc2 : 1; - uint8_t mlc3 : 1; - uint8_t mlc4 : 1; -} lsm6dsv16bx_pin_int1_route_t; -int32_t lsm6dsv16bx_pin_int1_route_set(stmdev_ctx_t *ctx, - lsm6dsv16bx_pin_int1_route_t val); -int32_t lsm6dsv16bx_pin_int1_route_get(stmdev_ctx_t *ctx, - lsm6dsv16bx_pin_int1_route_t *val); - -typedef struct -{ - uint8_t boot : 1; - uint8_t drdy_ois : 1; uint8_t drdy_xl : 1; uint8_t drdy_gy : 1; uint8_t drdy_temp : 1; + uint8_t drdy_ah_qvar : 1; uint8_t fifo_th : 1; uint8_t fifo_ovr : 1; uint8_t fifo_full : 1; @@ -3153,14 +3091,18 @@ typedef struct uint8_t mlc2 : 1; uint8_t mlc3 : 1; uint8_t mlc4 : 1; -} lsm6dsv16bx_pin_int2_route_t; -int32_t lsm6dsv16bx_pin_int2_route_set(stmdev_ctx_t *ctx, - lsm6dsv16bx_pin_int2_route_t val); -int32_t lsm6dsv16bx_pin_int2_route_get(stmdev_ctx_t *ctx, - lsm6dsv16bx_pin_int2_route_t *val); - -int32_t lsm6dsv16bx_pin_int_en_when_i2c_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_pin_int_en_when_i2c_get(stmdev_ctx_t *ctx, uint8_t *val); +} lsm6dsv16bx_pin_int_route_t; +int32_t lsm6dsv16bx_pin_int1_route_set(const stmdev_ctx_t *ctx, + lsm6dsv16bx_pin_int_route_t val); +int32_t lsm6dsv16bx_pin_int1_route_get(const stmdev_ctx_t *ctx, + lsm6dsv16bx_pin_int_route_t *val); +int32_t lsm6dsv16bx_pin_int2_route_set(const stmdev_ctx_t *ctx, + lsm6dsv16bx_pin_int_route_t val); +int32_t lsm6dsv16bx_pin_int2_route_get(const stmdev_ctx_t *ctx, + lsm6dsv16bx_pin_int_route_t *val); + +int32_t lsm6dsv16bx_pin_int_en_when_i2c_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_pin_int_en_when_i2c_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3169,9 +3111,9 @@ typedef enum LSM6DSV16BX_BASE_PULSED_EMB_LATCHED = 0x2, LSM6DSV16BX_ALL_INT_LATCHED = 0x3, } lsm6dsv16bx_int_notification_t; -int32_t lsm6dsv16bx_int_notification_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_int_notification_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_int_notification_t val); -int32_t lsm6dsv16bx_int_notification_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_int_notification_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_int_notification_t *val); typedef enum @@ -3181,8 +3123,8 @@ typedef enum LSM6DSV16BX_XL_LOW_POWER_GY_SLEEP = 0x2, LSM6DSV16BX_XL_LOW_POWER_GY_POWER_DOWN = 0x3, } lsm6dsv16bx_act_mode_t; -int32_t lsm6dsv16bx_act_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_act_mode_t val); -int32_t lsm6dsv16bx_act_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_act_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_act_mode_t val); +int32_t lsm6dsv16bx_act_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_act_mode_t *val); typedef enum @@ -3192,9 +3134,9 @@ typedef enum LSM6DSV16BX_SLEEP_TO_ACT_AT_3RD_SAMPLE = 0x2, LSM6DSV16BX_SLEEP_TO_ACT_AT_4th_SAMPLE = 0x3, } lsm6dsv16bx_act_from_sleep_to_act_dur_t; -int32_t lsm6dsv16bx_act_from_sleep_to_act_dur_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_act_from_sleep_to_act_dur_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_act_from_sleep_to_act_dur_t val); -int32_t lsm6dsv16bx_act_from_sleep_to_act_dur_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_act_from_sleep_to_act_dur_t *val); typedef enum @@ -3204,9 +3146,9 @@ typedef enum LSM6DSV16BX_30Hz = 0x2, LSM6DSV16BX_60Hz = 0x3, } lsm6dsv16bx_act_sleep_xl_odr_t; -int32_t lsm6dsv16bx_act_sleep_xl_odr_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_act_sleep_xl_odr_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_act_sleep_xl_odr_t val); -int32_t lsm6dsv16bx_act_sleep_xl_odr_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_act_sleep_xl_odr_t *val); typedef struct @@ -3214,9 +3156,9 @@ typedef struct uint32_t wk_ths_mg; uint32_t inact_ths_mg; } lsm6dsv16bx_act_thresholds_t; -int32_t lsm6dsv16bx_act_thresholds_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_act_thresholds_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_act_thresholds_t val); -int32_t lsm6dsv16bx_act_thresholds_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_act_thresholds_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_act_thresholds_t *val); typedef struct @@ -3224,9 +3166,9 @@ typedef struct uint8_t shock : 2; uint8_t quiet : 4; } lsm6dsv16bx_act_wkup_time_windows_t; -int32_t lsm6dsv16bx_act_wkup_time_windows_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_act_wkup_time_windows_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_act_wkup_time_windows_t val); -int32_t lsm6dsv16bx_act_wkup_time_windows_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_act_wkup_time_windows_t *val); typedef struct @@ -3235,9 +3177,9 @@ typedef struct uint8_t tap_y_en : 1; uint8_t tap_z_en : 1; } lsm6dsv16bx_tap_detection_t; -int32_t lsm6dsv16bx_tap_detection_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tap_detection_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_tap_detection_t val); -int32_t lsm6dsv16bx_tap_detection_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tap_detection_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tap_detection_t *val); typedef struct @@ -3246,9 +3188,9 @@ typedef struct uint8_t y : 1; uint8_t z : 1; } lsm6dsv16bx_tap_thresholds_t; -int32_t lsm6dsv16bx_tap_thresholds_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tap_thresholds_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_tap_thresholds_t val); -int32_t lsm6dsv16bx_tap_thresholds_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tap_thresholds_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tap_thresholds_t *val); @@ -3261,9 +3203,9 @@ typedef enum LSM6DSV16BX_YZX = 0x1, LSM6DSV16BX_ZXY = 0x2, } lsm6dsv16bx_tap_axis_priority_t; -int32_t lsm6dsv16bx_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tap_axis_priority_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_tap_axis_priority_t val); -int32_t lsm6dsv16bx_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tap_axis_priority_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tap_axis_priority_t *val); typedef struct @@ -3272,9 +3214,9 @@ typedef struct uint8_t quiet : 1; uint8_t tap_gap : 1; } lsm6dsv16bx_tap_time_windows_t; -int32_t lsm6dsv16bx_tap_time_windows_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tap_time_windows_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_tap_time_windows_t val); -int32_t lsm6dsv16bx_tap_time_windows_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tap_time_windows_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tap_time_windows_t *val); typedef enum @@ -3282,8 +3224,8 @@ typedef enum LSM6DSV16BX_ONLY_SINGLE = 0x0, LSM6DSV16BX_BOTH_SINGLE_DOUBLE = 0x1, } lsm6dsv16bx_tap_mode_t; -int32_t lsm6dsv16bx_tap_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_tap_mode_t val); -int32_t lsm6dsv16bx_tap_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_tap_mode_t val); +int32_t lsm6dsv16bx_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tap_mode_t *val); typedef enum @@ -3293,13 +3235,13 @@ typedef enum LSM6DSV16BX_DEG_60 = 0x2, LSM6DSV16BX_DEG_50 = 0x3, } lsm6dsv16bx_6d_threshold_t; -int32_t lsm6dsv16bx_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_6d_threshold_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_6d_threshold_t val); -int32_t lsm6dsv16bx_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_6d_threshold_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_6d_threshold_t *val); -int32_t lsm6dsv16bx_ff_time_windows_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_ff_time_windows_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3312,16 +3254,16 @@ typedef enum LSM6DSV16BX_469_mg = 0x6, LSM6DSV16BX_500_mg = 0x7, } lsm6dsv16bx_ff_thresholds_t; -int32_t lsm6dsv16bx_ff_thresholds_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_ff_thresholds_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_ff_thresholds_t val); -int32_t lsm6dsv16bx_ff_thresholds_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_ff_thresholds_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_ff_thresholds_t *val); -int32_t lsm6dsv16bx_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16bx_fifo_xl_dual_fsm_batch_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_fifo_xl_dual_fsm_batch_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3330,23 +3272,23 @@ typedef enum LSM6DSV16BX_CMP_16_TO_1 = 0x2, LSM6DSV16BX_CMP_32_TO_1 = 0x3, } lsm6dsv16bx_fifo_compress_algo_t; -int32_t lsm6dsv16bx_fifo_compress_algo_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_compress_algo_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_compress_algo_t val); -int32_t lsm6dsv16bx_fifo_compress_algo_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_compress_algo_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_compress_algo_t *val); -int32_t lsm6dsv16bx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16bx_fifo_compress_algo_real_time_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_fifo_compress_algo_real_time_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16bx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3364,9 +3306,9 @@ typedef enum LSM6DSV16BX_XL_BATCHED_AT_3840Hz = 0xB, LSM6DSV16BX_XL_BATCHED_AT_7680Hz = 0xC, } lsm6dsv16bx_fifo_xl_batch_t; -int32_t lsm6dsv16bx_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_xl_batch_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_xl_batch_t val); -int32_t lsm6dsv16bx_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_xl_batch_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_xl_batch_t *val); typedef enum @@ -3385,9 +3327,9 @@ typedef enum LSM6DSV16BX_GY_BATCHED_AT_3840Hz = 0xb, LSM6DSV16BX_GY_BATCHED_AT_7680Hz = 0xc, } lsm6dsv16bx_fifo_gy_batch_t; -int32_t lsm6dsv16bx_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_gy_batch_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_gy_batch_t val); -int32_t lsm6dsv16bx_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_gy_batch_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_gy_batch_t *val); typedef enum @@ -3400,9 +3342,9 @@ typedef enum LSM6DSV16BX_STREAM_MODE = 0x6, LSM6DSV16BX_BYPASS_TO_FIFO_MODE = 0x7, } lsm6dsv16bx_fifo_mode_t; -int32_t lsm6dsv16bx_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_mode_t val); -int32_t lsm6dsv16bx_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_mode_t *val); typedef enum @@ -3412,9 +3354,9 @@ typedef enum LSM6DSV16BX_TEMP_BATCHED_AT_15Hz = 0x2, LSM6DSV16BX_TEMP_BATCHED_AT_60Hz = 0x3, } lsm6dsv16bx_fifo_temp_batch_t; -int32_t lsm6dsv16bx_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_temp_batch_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_temp_batch_t val); -int32_t lsm6dsv16bx_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_temp_batch_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_temp_batch_t *val); typedef enum @@ -3424,28 +3366,27 @@ typedef enum LSM6DSV16BX_TMSTMP_DEC_8 = 0x2, LSM6DSV16BX_TMSTMP_DEC_32 = 0x3, } lsm6dsv16bx_fifo_timestamp_batch_t; -int32_t lsm6dsv16bx_fifo_timestamp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_timestamp_batch_t val); -int32_t lsm6dsv16bx_fifo_timestamp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_timestamp_batch_t *val); -int32_t lsm6dsv16bx_fifo_batch_counter_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsv16bx_fifo_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsv16bx_fifo_batch_ah_qvar_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_fifo_batch_ah_qvar_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_fifo_batch_ah_qvar_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_fifo_batch_ah_qvar_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSV16BX_XL_BATCH_EVENT = 0x0, LSM6DSV16BX_GY_BATCH_EVENT = 0x1, - LSM6DSV16BX_GY_EIS_BATCH_EVENT = 0x2, } lsm6dsv16bx_fifo_batch_cnt_event_t; -int32_t lsm6dsv16bx_fifo_batch_cnt_event_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_batch_cnt_event_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_batch_cnt_event_t val); -int32_t lsm6dsv16bx_fifo_batch_cnt_event_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_batch_cnt_event_t *val); typedef struct @@ -3454,9 +3395,9 @@ typedef struct uint8_t gravity : 1; uint8_t gbias : 1; } lsm6dsv16bx_fifo_sflp_raw_t; -int32_t lsm6dsv16bx_fifo_sflp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_sflp_batch_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_sflp_raw_t val); -int32_t lsm6dsv16bx_fifo_sflp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_sflp_batch_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_sflp_raw_t *val); typedef struct @@ -3468,7 +3409,7 @@ typedef struct uint8_t fifo_th : 1; } lsm6dsv16bx_fifo_status_t; -int32_t lsm6dsv16bx_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_status_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_status_t *val); typedef struct @@ -3502,47 +3443,47 @@ typedef struct uint8_t cnt; uint8_t data[6]; } lsm6dsv16bx_fifo_out_raw_t; -int32_t lsm6dsv16bx_fifo_out_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fifo_out_raw_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fifo_out_raw_t *val); -int32_t lsm6dsv16bx_fifo_stpcnt_batch_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_fifo_stpcnt_batch_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16bx_fifo_mlc_batch_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_fifo_mlc_batch_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_fifo_mlc_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_fifo_mlc_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16bx_fifo_mlc_filt_batch_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_fifo_mlc_filt_batch_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_fifo_mlc_filt_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_fifo_mlc_filt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { uint8_t step_counter_enable : 1; uint8_t false_step_rej : 1; } lsm6dsv16bx_stpcnt_mode_t; -int32_t lsm6dsv16bx_stpcnt_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_stpcnt_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_stpcnt_mode_t val); -int32_t lsm6dsv16bx_stpcnt_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_stpcnt_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_stpcnt_mode_t *val); -int32_t lsm6dsv16bx_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsv16bx_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsv16bx_stpcnt_rst_step_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_stpcnt_rst_step_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_stpcnt_rst_step_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16bx_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16bx_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsv16bx_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsv16bx_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv16bx_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsv16bx_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16bx_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16bx_sflp_game_rotation_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsv16bx_sflp_game_rotation_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsv16bx_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv16bx_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef struct { @@ -3550,10 +3491,10 @@ typedef struct float_t gbias_y; /* dps */ float_t gbias_z; /* dps */ } lsm6dsv16bx_sflp_gbias_t; -int32_t lsm6dsv16bx_sflp_game_gbias_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_sflp_game_gbias_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_sflp_gbias_t *val); -int32_t lsm6dsv16bx_sflp_configure(stmdev_ctx_t *ctx); +int32_t lsm6dsv16bx_sflp_configure(const stmdev_ctx_t *ctx); typedef enum { @@ -3564,9 +3505,9 @@ typedef enum LSM6DSV16BX_SFLP_240Hz = 0x4, LSM6DSV16BX_SFLP_480Hz = 0x5, } lsm6dsv16bx_sflp_data_rate_t; -int32_t lsm6dsv16bx_sflp_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_sflp_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_sflp_data_rate_t val); -int32_t lsm6dsv16bx_sflp_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_sflp_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_sflp_data_rate_t *val); typedef enum @@ -3574,19 +3515,18 @@ typedef enum LSM6DSV16BX_PROTECT_CTRL_REGS = 0x0, LSM6DSV16BX_WRITE_CTRL_REG = 0x1, } lsm6dsv16bx_fsm_permission_t; -int32_t lsm6dsv16bx_fsm_permission_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fsm_permission_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_permission_t val); -int32_t lsm6dsv16bx_fsm_permission_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fsm_permission_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_permission_t *val); -int32_t lsm6dsv16bx_fsm_permission_status(stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSV16BX_STD_IF_CONTROL = 0x0, LSM6DSV16BX_FSM_CONTROL = 0x1, } lsm6dsv16bx_fsm_permission_status_t; -int32_t lsm6dsv16bx_fsm_permission_status_get(stmdev_ctx_t *ctx, - lsm6dsv16bx_fsm_permission_status_t *val); +int32_t lsm6dsv16bx_fsm_permission_status(const stmdev_ctx_t *ctx, + lsm6dsv16bx_fsm_permission_status_t *val); typedef struct { @@ -3599,12 +3539,12 @@ typedef struct uint8_t fsm7_en : 1; uint8_t fsm8_en : 1; } lsm6dsv16bx_fsm_mode_t; -int32_t lsm6dsv16bx_fsm_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_mode_t val); -int32_t lsm6dsv16bx_fsm_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fsm_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_mode_t val); +int32_t lsm6dsv16bx_fsm_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_mode_t *val); -int32_t lsm6dsv16bx_fsm_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsv16bx_fsm_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsv16bx_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv16bx_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef struct { @@ -3617,7 +3557,7 @@ typedef struct uint8_t fsm_outs7; uint8_t fsm_outs8; } lsm6dsv16bx_fsm_out_t; -int32_t lsm6dsv16bx_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_out_t *val); +int32_t lsm6dsv16bx_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_out_t *val); typedef enum { @@ -3629,19 +3569,19 @@ typedef enum LSM6DSV16BX_FSM_480Hz = 0x5, LSM6DSV16BX_FSM_960Hz = 0x6, } lsm6dsv16bx_fsm_data_rate_t; -int32_t lsm6dsv16bx_fsm_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fsm_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_data_rate_t val); -int32_t lsm6dsv16bx_fsm_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_fsm_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_data_rate_t *val); -int32_t lsm6dsv16bx_fsm_long_cnt_timeout_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsv16bx_fsm_long_cnt_timeout_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsv16bx_fsm_long_cnt_timeout_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv16bx_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsv16bx_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16bx_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsv16bx_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsv16bx_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv16bx_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum { @@ -3649,8 +3589,8 @@ typedef enum LSM6DSV16BX_MLC_ON = 0x1, LSM6DSV16BX_MLC_ON_BEFORE_FSM = 0x2, } lsm6dsv16bx_mlc_mode_t; -int32_t lsm6dsv16bx_mlc_set(stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_mode_t val); -int32_t lsm6dsv16bx_mlc_get(stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_mode_t *val); +int32_t lsm6dsv16bx_mlc_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_mode_t val); +int32_t lsm6dsv16bx_mlc_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_mode_t *val); typedef enum { @@ -3662,9 +3602,9 @@ typedef enum LSM6DSV16BX_MLC_480Hz = 0x5, LSM6DSV16BX_MLC_960Hz = 0x6, } lsm6dsv16bx_mlc_data_rate_t; -int32_t lsm6dsv16bx_mlc_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_mlc_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_data_rate_t val); -int32_t lsm6dsv16bx_mlc_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_mlc_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_data_rate_t *val); typedef struct @@ -3674,24 +3614,24 @@ typedef struct uint8_t mlc3_src; uint8_t mlc4_src; } lsm6dsv16bx_mlc_out_t; -int32_t lsm6dsv16bx_mlc_out_get(stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_out_t *val); +int32_t lsm6dsv16bx_mlc_out_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_out_t *val); -int32_t lsm6dsv16bx_mlc_qvar_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsv16bx_mlc_qvar_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsv16bx_mlc_qvar_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv16bx_mlc_qvar_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsv16bx_xl_offset_on_out_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_xl_offset_on_out_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_xl_offset_on_out_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { float_t z_mg; float_t y_mg; float_t x_mg; -} lsm6dsv16bxxl_offset_mg_t; -int32_t lsm6dsv16bx_xl_offset_mg_set(stmdev_ctx_t *ctx, - lsm6dsv16bxxl_offset_mg_t val); -int32_t lsm6dsv16bx_xl_offset_mg_get(stmdev_ctx_t *ctx, - lsm6dsv16bxxl_offset_mg_t *val); +} lsm6dsv16bx_xl_offset_mg_t; +int32_t lsm6dsv16bx_xl_offset_mg_set(const stmdev_ctx_t *ctx, + lsm6dsv16bx_xl_offset_mg_t val); +int32_t lsm6dsv16bx_xl_offset_mg_get(const stmdev_ctx_t *ctx, + lsm6dsv16bx_xl_offset_mg_t *val); typedef struct { @@ -3699,9 +3639,9 @@ typedef struct uint8_t ah_qvar2_en : 1; uint8_t swaps : 1; } lsm6dsv16bx_ah_qvar_mode_t; -int32_t lsm6dsv16bx_ah_qvar_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_ah_qvar_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_ah_qvar_mode_t val); -int32_t lsm6dsv16bx_ah_qvar_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_ah_qvar_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_ah_qvar_mode_t *val); typedef enum @@ -3711,38 +3651,38 @@ typedef enum LSM6DSV16BX_300MOhm = 0x2, LSM6DSV16BX_255MOhm = 0x3, } lsm6dsv16bx_ah_qvar_zin_t; -int32_t lsm6dsv16bx_ah_qvar_zin_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_ah_qvar_zin_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_ah_qvar_zin_t val); -int32_t lsm6dsv16bx_ah_qvar_zin_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_ah_qvar_zin_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_ah_qvar_zin_t *val); -int32_t lsm6dsv16bx_fsm_qvar_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsv16bx_fsm_qvar_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsv16bx_fsm_qvar_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv16bx_fsm_qvar_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum { LSM6DSV16BX_SW_RST_DYN_ADDRESS_RST = 0x0, LSM6DSV16BX_I3C_GLOBAL_RST = 0x1, } lsm6dsv16bx_i3c_reset_mode_t; -int32_t lsm6dsv16bx_i3c_reset_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_i3c_reset_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_i3c_reset_mode_t val); -int32_t lsm6dsv16bx_i3c_reset_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_i3c_reset_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_i3c_reset_mode_t *val); -int32_t lsm6dsv16bx_tdm_dis_wclk_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_tdm_dis_wclk_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_tdm_dis_wclk_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_tdm_dis_wclk_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16bx_tdm_tdmout_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_tdm_tdmout_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_tdm_tdmout_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_tdm_tdmout_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSV16BX_WCLK_16kHZ_BCLK_2048kHz = 0x1, LSM6DSV16BX_WCLK_8kHZ_BCLK_2048kHz = 0x4, } lsm6dsv16bx_tdm_wclk_bclk_t; -int32_t lsm6dsv16bx_tdm_wclk_bclk_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tdm_wclk_bclk_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_wclk_bclk_t val); -int32_t lsm6dsv16bx_tdm_wclk_bclk_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tdm_wclk_bclk_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_wclk_bclk_t *val); typedef enum @@ -3750,8 +3690,8 @@ typedef enum LSM6DSV16BX_SLOT_012 = 0x0, LSM6DSV16BX_SLOT_456 = 0x1, } lsm6dsv16bx_tdm_slot_t; -int32_t lsm6dsv16bx_tdm_slot_set(stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_slot_t val); -int32_t lsm6dsv16bx_tdm_slot_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tdm_slot_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_slot_t val); +int32_t lsm6dsv16bx_tdm_slot_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_slot_t *val); typedef enum @@ -3759,13 +3699,13 @@ typedef enum LSM6DSV16BX_BCLK_RISING = 0x0, LSM6DSV16BX_BCLK_FALLING = 0x1, } lsm6dsv16bx_tdm_bclk_edge_t; -int32_t lsm6dsv16bx_tdm_bclk_edge_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tdm_bclk_edge_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_bclk_edge_t val); -int32_t lsm6dsv16bx_tdm_bclk_edge_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tdm_bclk_edge_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_bclk_edge_t *val); -int32_t lsm6dsv16bx_tdm_delayed_conf_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16bx_tdm_delayed_conf_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16bx_tdm_delayed_conf_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16bx_tdm_delayed_conf_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3773,9 +3713,9 @@ typedef enum LSM6DSV16BX_TDM_ORDER_XZY = 0x1, LSM6DSV16BX_TDM_ORDER_XYZ = 0x2, } lsm6dsv16bx_tdm_axis_order_t; -int32_t lsm6dsv16bx_tdm_axis_order_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tdm_axis_order_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_axis_order_t val); -int32_t lsm6dsv16bx_tdm_axis_order_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tdm_axis_order_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_axis_order_t *val); typedef enum @@ -3784,9 +3724,9 @@ typedef enum LSM6DSV16BX_TDM_4g = 0x1, LSM6DSV16BX_TDM_8g = 0x2, } lsm6dsv16bx_tdm_xl_full_scale_t; -int32_t lsm6dsv16bx_tdm_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tdm_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_xl_full_scale_t val); -int32_t lsm6dsv16bx_tdm_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16bx_tdm_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_xl_full_scale_t *val); /** diff --git a/sensor/stmemsc/lsm6dsv16x_STdC/driver/lsm6dsv16x_reg.c b/sensor/stmemsc/lsm6dsv16x_STdC/driver/lsm6dsv16x_reg.c index c6a80f8f..ba215e2c 100644 --- a/sensor/stmemsc/lsm6dsv16x_STdC/driver/lsm6dsv16x_reg.c +++ b/sensor/stmemsc/lsm6dsv16x_STdC/driver/lsm6dsv16x_reg.c @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2022 STMicroelectronics. + *

© Copyright (c) 2024 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm6dsv16x_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm6dsv16x_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lsm6dsv16x_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm6dsv16x_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm6dsv16x_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -200,7 +210,7 @@ float_t lsm6dsv16x_from_lsb_to_mv(int16_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_xl_offset_on_out_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_xl_offset_on_out_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_ctrl9_t ctrl9; int32_t ret; @@ -223,7 +233,7 @@ int32_t lsm6dsv16x_xl_offset_on_out_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_xl_offset_on_out_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_ctrl9_t ctrl9; int32_t ret; @@ -242,7 +252,7 @@ int32_t lsm6dsv16x_xl_offset_on_out_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_xl_offset_mg_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_xl_offset_mg_set(const stmdev_ctx_t *ctx, lsm6dsv16x_xl_offset_mg_t val) { lsm6dsv16x_z_ofs_usr_t z_ofs_usr; @@ -255,7 +265,10 @@ int32_t lsm6dsv16x_xl_offset_mg_set(stmdev_ctx_t *ctx, ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } if ((val.x_mg < (0.0078125f * 127.0f)) && (val.x_mg > (0.0078125f * -127.0f)) && @@ -312,7 +325,7 @@ int32_t lsm6dsv16x_xl_offset_mg_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_xl_offset_mg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_xl_offset_mg_get(const stmdev_ctx_t *ctx, lsm6dsv16x_xl_offset_mg_t *val) { lsm6dsv16x_z_ofs_usr_t z_ofs_usr; @@ -325,7 +338,10 @@ int32_t lsm6dsv16x_xl_offset_mg_get(stmdev_ctx_t *ctx, ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } if (ctrl9.usr_off_w == PROPERTY_DISABLE) { @@ -356,7 +372,7 @@ int32_t lsm6dsv16x_xl_offset_mg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_reset_set(stmdev_ctx_t *ctx, lsm6dsv16x_reset_t val) +int32_t lsm6dsv16x_reset_set(const stmdev_ctx_t *ctx, lsm6dsv16x_reset_t val) { lsm6dsv16x_func_cfg_access_t func_cfg_access; lsm6dsv16x_ctrl3_t ctrl3; @@ -364,7 +380,10 @@ int32_t lsm6dsv16x_reset_set(stmdev_ctx_t *ctx, lsm6dsv16x_reset_t val) ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ctrl3.boot = ((uint8_t)val & 0x04U) >> 2; ctrl3.sw_reset = ((uint8_t)val & 0x02U) >> 1; @@ -384,7 +403,7 @@ int32_t lsm6dsv16x_reset_set(stmdev_ctx_t *ctx, lsm6dsv16x_reset_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_reset_get(stmdev_ctx_t *ctx, lsm6dsv16x_reset_t *val) +int32_t lsm6dsv16x_reset_get(const stmdev_ctx_t *ctx, lsm6dsv16x_reset_t *val) { lsm6dsv16x_func_cfg_access_t func_cfg_access; lsm6dsv16x_ctrl3_t ctrl3; @@ -392,7 +411,10 @@ int32_t lsm6dsv16x_reset_get(stmdev_ctx_t *ctx, lsm6dsv16x_reset_t *val) ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch ((ctrl3.sw_reset << 2) + (ctrl3.boot << 1) + func_cfg_access.sw_por) { @@ -428,13 +450,16 @@ int32_t lsm6dsv16x_reset_get(stmdev_ctx_t *ctx, lsm6dsv16x_reset_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsv16x_mem_bank_t val) +int32_t lsm6dsv16x_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dsv16x_mem_bank_t val) { lsm6dsv16x_func_cfg_access_t func_cfg_access; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } func_cfg_access.shub_reg_access = ((uint8_t)val & 0x02U) >> 1; func_cfg_access.emb_func_reg_access = (uint8_t)val & 0x01U; @@ -451,13 +476,16 @@ int32_t lsm6dsv16x_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsv16x_mem_bank_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_mem_bank_get(stmdev_ctx_t *ctx, lsm6dsv16x_mem_bank_t *val) +int32_t lsm6dsv16x_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dsv16x_mem_bank_t *val) { lsm6dsv16x_func_cfg_access_t func_cfg_access; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch ((func_cfg_access.shub_reg_access << 1) + func_cfg_access.emb_func_reg_access) { @@ -490,7 +518,7 @@ int32_t lsm6dsv16x_mem_bank_get(stmdev_ctx_t *ctx, lsm6dsv16x_mem_bank_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_device_id_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -507,7 +535,7 @@ int32_t lsm6dsv16x_device_id_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv16x_data_rate_t val) { lsm6dsv16x_ctrl1_t ctrl1; @@ -516,11 +544,17 @@ int32_t lsm6dsv16x_xl_data_rate_set(stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL1, (uint8_t *)&ctrl1, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ctrl1.odr_xl = (uint8_t)val & 0x0Fu; ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL1, (uint8_t *)&ctrl1, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } sel = ((uint8_t)val >> 4) & 0xFU; if (sel != 0U) @@ -541,7 +575,7 @@ int32_t lsm6dsv16x_xl_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv16x_data_rate_t *val) { lsm6dsv16x_ctrl1_t ctrl1; @@ -551,7 +585,10 @@ int32_t lsm6dsv16x_xl_data_rate_get(stmdev_ctx_t *ctx, ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL1, (uint8_t *)&ctrl1, 1); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_HAODR_CFG, (uint8_t *)&haodr, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } sel = haodr.haodr_sel; @@ -570,152 +607,162 @@ int32_t lsm6dsv16x_xl_data_rate_get(stmdev_ctx_t *ctx, break; case LSM6DSV16X_ODR_AT_15Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV16X_ODR_AT_15Hz; - break; - case 1: - *val = LSM6DSV16X_ODR_HA01_AT_15Hz625; - break; - case 2: - *val = LSM6DSV16X_ODR_HA02_AT_12Hz5; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_15Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_15Hz625; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_12Hz5; + break; } break; case LSM6DSV16X_ODR_AT_30Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV16X_ODR_AT_30Hz; - break; - case 1: - *val = LSM6DSV16X_ODR_HA01_AT_31Hz25; - break; - case 2: - *val = LSM6DSV16X_ODR_HA02_AT_25Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_30Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_31Hz25; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_25Hz; + break; } break; case LSM6DSV16X_ODR_AT_60Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV16X_ODR_AT_60Hz; - break; - case 1: - *val = LSM6DSV16X_ODR_HA01_AT_62Hz5; - break; - case 2: - *val = LSM6DSV16X_ODR_HA02_AT_50Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_60Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_62Hz5; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_50Hz; + break; } break; case LSM6DSV16X_ODR_AT_120Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV16X_ODR_AT_120Hz; - break; - case 1: - *val = LSM6DSV16X_ODR_HA01_AT_125Hz; - break; - case 2: - *val = LSM6DSV16X_ODR_HA02_AT_100Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_120Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_125Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_100Hz; + break; } break; case LSM6DSV16X_ODR_AT_240Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV16X_ODR_AT_240Hz; - break; - case 1: - *val = LSM6DSV16X_ODR_HA01_AT_250Hz; - break; - case 2: - *val = LSM6DSV16X_ODR_HA02_AT_200Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_240Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_250Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_200Hz; + break; } break; case LSM6DSV16X_ODR_AT_480Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV16X_ODR_AT_480Hz; - break; - case 1: - *val = LSM6DSV16X_ODR_HA01_AT_500Hz; - break; - case 2: - *val = LSM6DSV16X_ODR_HA02_AT_400Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_480Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_500Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_400Hz; + break; } break; case LSM6DSV16X_ODR_AT_960Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV16X_ODR_AT_960Hz; - break; - case 1: - *val = LSM6DSV16X_ODR_HA01_AT_1000Hz; - break; - case 2: - *val = LSM6DSV16X_ODR_HA02_AT_800Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_960Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_1000Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_800Hz; + break; } break; case LSM6DSV16X_ODR_AT_1920Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV16X_ODR_AT_1920Hz; - break; - case 1: - *val = LSM6DSV16X_ODR_HA01_AT_2000Hz; - break; - case 2: - *val = LSM6DSV16X_ODR_HA02_AT_1600Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_1920Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_2000Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_1600Hz; + break; } break; case LSM6DSV16X_ODR_AT_3840Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV16X_ODR_AT_3840Hz; - break; - case 1: - *val = LSM6DSV16X_ODR_HA01_AT_4000Hz; - break; - case 2: - *val = LSM6DSV16X_ODR_HA02_AT_3200Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_3840Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_4000Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_3200Hz; + break; } break; case LSM6DSV16X_ODR_AT_7680Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV16X_ODR_AT_7680Hz; - break; - case 1: - *val = LSM6DSV16X_ODR_HA01_AT_8000Hz; - break; - case 2: - *val = LSM6DSV16X_ODR_HA02_AT_6400Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_7680Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_8000Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_6400Hz; + break; } break; @@ -735,7 +782,7 @@ int32_t lsm6dsv16x_xl_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_xl_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_xl_mode_t val) +int32_t lsm6dsv16x_xl_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_xl_mode_t val) { lsm6dsv16x_ctrl1_t ctrl1; int32_t ret; @@ -759,13 +806,16 @@ int32_t lsm6dsv16x_xl_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_xl_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_xl_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_xl_mode_t *val) +int32_t lsm6dsv16x_xl_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_xl_mode_t *val) { lsm6dsv16x_ctrl1_t ctrl1; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL1, (uint8_t *)&ctrl1, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl1.op_mode_xl) { @@ -813,7 +863,7 @@ int32_t lsm6dsv16x_xl_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_xl_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_gy_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv16x_data_rate_t val) { lsm6dsv16x_ctrl2_t ctrl2; @@ -822,9 +872,13 @@ int32_t lsm6dsv16x_gy_data_rate_set(stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL2, (uint8_t *)&ctrl2, 1); + ctrl2.odr_g = (uint8_t)val & 0x0Fu; ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL2, (uint8_t *)&ctrl2, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } sel = ((uint8_t)val >> 4) & 0xFU; if (sel != 0U) @@ -845,7 +899,7 @@ int32_t lsm6dsv16x_gy_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv16x_data_rate_t *val) { lsm6dsv16x_ctrl2_t ctrl2; @@ -855,7 +909,10 @@ int32_t lsm6dsv16x_gy_data_rate_get(stmdev_ctx_t *ctx, ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL2, (uint8_t *)&ctrl2, 1); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_HAODR_CFG, (uint8_t *)&haodr, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } sel = haodr.haodr_sel; @@ -874,152 +931,162 @@ int32_t lsm6dsv16x_gy_data_rate_get(stmdev_ctx_t *ctx, break; case LSM6DSV16X_ODR_AT_15Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV16X_ODR_AT_15Hz; - break; - case 1: - *val = LSM6DSV16X_ODR_HA01_AT_15Hz625; - break; - case 2: - *val = LSM6DSV16X_ODR_HA02_AT_12Hz5; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_15Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_15Hz625; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_12Hz5; + break; } break; case LSM6DSV16X_ODR_AT_30Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV16X_ODR_AT_30Hz; - break; - case 1: - *val = LSM6DSV16X_ODR_HA01_AT_31Hz25; - break; - case 2: - *val = LSM6DSV16X_ODR_HA02_AT_25Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_30Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_31Hz25; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_25Hz; + break; } break; case LSM6DSV16X_ODR_AT_60Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV16X_ODR_AT_60Hz; - break; - case 1: - *val = LSM6DSV16X_ODR_HA01_AT_62Hz5; - break; - case 2: - *val = LSM6DSV16X_ODR_HA02_AT_50Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_60Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_62Hz5; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_50Hz; + break; } break; case LSM6DSV16X_ODR_AT_120Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV16X_ODR_AT_120Hz; - break; - case 1: - *val = LSM6DSV16X_ODR_HA01_AT_125Hz; - break; - case 2: - *val = LSM6DSV16X_ODR_HA02_AT_100Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_120Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_125Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_100Hz; + break; } break; case LSM6DSV16X_ODR_AT_240Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV16X_ODR_AT_240Hz; - break; - case 1: - *val = LSM6DSV16X_ODR_HA01_AT_250Hz; - break; - case 2: - *val = LSM6DSV16X_ODR_HA02_AT_200Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_240Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_250Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_200Hz; + break; } break; case LSM6DSV16X_ODR_AT_480Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV16X_ODR_AT_480Hz; - break; - case 1: - *val = LSM6DSV16X_ODR_HA01_AT_500Hz; - break; - case 2: - *val = LSM6DSV16X_ODR_HA02_AT_400Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_480Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_500Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_400Hz; + break; } break; case LSM6DSV16X_ODR_AT_960Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV16X_ODR_AT_960Hz; - break; - case 1: - *val = LSM6DSV16X_ODR_HA01_AT_1000Hz; - break; - case 2: - *val = LSM6DSV16X_ODR_HA02_AT_800Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_960Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_1000Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_800Hz; + break; } break; case LSM6DSV16X_ODR_AT_1920Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV16X_ODR_AT_1920Hz; - break; - case 1: - *val = LSM6DSV16X_ODR_HA01_AT_2000Hz; - break; - case 2: - *val = LSM6DSV16X_ODR_HA02_AT_1600Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_1920Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_2000Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_1600Hz; + break; } break; case LSM6DSV16X_ODR_AT_3840Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV16X_ODR_AT_3840Hz; - break; - case 1: - *val = LSM6DSV16X_ODR_HA01_AT_4000Hz; - break; - case 2: - *val = LSM6DSV16X_ODR_HA02_AT_3200Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_3840Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_4000Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_3200Hz; + break; } break; case LSM6DSV16X_ODR_AT_7680Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV16X_ODR_AT_7680Hz; - break; - case 1: - *val = LSM6DSV16X_ODR_HA01_AT_8000Hz; - break; - case 2: - *val = LSM6DSV16X_ODR_HA02_AT_6400Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV16X_ODR_AT_7680Hz; + break; + case 1: + *val = LSM6DSV16X_ODR_HA01_AT_8000Hz; + break; + case 2: + *val = LSM6DSV16X_ODR_HA02_AT_6400Hz; + break; } break; @@ -1039,7 +1106,7 @@ int32_t lsm6dsv16x_gy_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_gy_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_gy_mode_t val) +int32_t lsm6dsv16x_gy_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_gy_mode_t val) { lsm6dsv16x_ctrl2_t ctrl2; int32_t ret; @@ -1062,13 +1129,16 @@ int32_t lsm6dsv16x_gy_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_gy_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_gy_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_gy_mode_t *val) +int32_t lsm6dsv16x_gy_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_gy_mode_t *val) { lsm6dsv16x_ctrl2_t ctrl2; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL2, (uint8_t *)&ctrl2, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl2.op_mode_g) { @@ -1104,7 +1174,7 @@ int32_t lsm6dsv16x_gy_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_gy_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_ctrl3_t ctrl3; int32_t ret; @@ -1127,7 +1197,7 @@ int32_t lsm6dsv16x_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_ctrl3_t ctrl3; int32_t ret; @@ -1146,7 +1216,7 @@ int32_t lsm6dsv16x_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_ctrl3_t ctrl3; int32_t ret; @@ -1170,7 +1240,7 @@ int32_t lsm6dsv16x_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_ctrl3_t ctrl3; int32_t ret; @@ -1189,12 +1259,13 @@ int32_t lsm6dsv16x_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_odr_trig_cfg_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_odr_trig_cfg_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_odr_trig_cfg_t odr_trig; int32_t ret; - if (val >= 1U && val <= 3U) { + if (val >= 1U && val <= 3U) + { return -1; } @@ -1217,7 +1288,7 @@ int32_t lsm6dsv16x_odr_trig_cfg_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_odr_trig_cfg_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_odr_trig_cfg_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_odr_trig_cfg_t odr_trig; int32_t ret; @@ -1236,7 +1307,7 @@ int32_t lsm6dsv16x_odr_trig_cfg_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_data_ready_mode_t val) { lsm6dsv16x_ctrl4_t ctrl4; @@ -1261,7 +1332,7 @@ int32_t lsm6dsv16x_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_data_ready_mode_t *val) { lsm6dsv16x_ctrl4_t ctrl4; @@ -1295,7 +1366,7 @@ int32_t lsm6dsv16x_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_interrupt_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_interrupt_enable_set(const stmdev_ctx_t *ctx, lsm6dsv16x_interrupt_mode_t val) { lsm6dsv16x_tap_cfg0_t cfg; @@ -1305,7 +1376,10 @@ int32_t lsm6dsv16x_interrupt_enable_set(stmdev_ctx_t *ctx, ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); func.interrupts_enable = val.enable; ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&cfg, 1); cfg.lir = val.lir; @@ -1322,7 +1396,7 @@ int32_t lsm6dsv16x_interrupt_enable_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_interrupt_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_interrupt_enable_get(const stmdev_ctx_t *ctx, lsm6dsv16x_interrupt_mode_t *val) { lsm6dsv16x_tap_cfg0_t cfg; @@ -1331,7 +1405,10 @@ int32_t lsm6dsv16x_interrupt_enable_get(stmdev_ctx_t *ctx, ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&cfg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->enable = func.interrupts_enable; val->lir = cfg.lir; @@ -1347,7 +1424,7 @@ int32_t lsm6dsv16x_interrupt_enable_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsv16x_gy_full_scale_t val) { lsm6dsv16x_ctrl6_t ctrl6; @@ -1372,14 +1449,17 @@ int32_t lsm6dsv16x_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsv16x_gy_full_scale_t *val) { lsm6dsv16x_ctrl6_t ctrl6; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL6, (uint8_t *)&ctrl6, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl6.fs_g) { @@ -1419,11 +1499,11 @@ int32_t lsm6dsv16x_gy_full_scale_get(stmdev_ctx_t *ctx, * @brief Accelerometer full-scale selection.[set] * * @param ctx read / write interface definitions - * @param val 2g, 4g, 8g, 16g, + * @param val lsm6dsv16x_xl_full_scale_t * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsv16x_xl_full_scale_t val) { lsm6dsv16x_ctrl8_t ctrl8; @@ -1444,18 +1524,21 @@ int32_t lsm6dsv16x_xl_full_scale_set(stmdev_ctx_t *ctx, * @brief Accelerometer full-scale selection.[get] * * @param ctx read / write interface definitions - * @param val 2g, 4g, 8g, 16g, + * @param val lsm6dsv16x_xl_full_scale_t * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsv16x_xl_full_scale_t *val) { lsm6dsv16x_ctrl8_t ctrl8; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl8.fs_xl) { @@ -1491,7 +1574,7 @@ int32_t lsm6dsv16x_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_xl_dual_channel_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_xl_dual_channel_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_ctrl8_t ctrl8; int32_t ret; @@ -1515,7 +1598,7 @@ int32_t lsm6dsv16x_xl_dual_channel_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_xl_dual_channel_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_ctrl8_t ctrl8; int32_t ret; @@ -1534,7 +1617,7 @@ int32_t lsm6dsv16x_xl_dual_channel_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dsv16x_xl_self_test_t val) { lsm6dsv16x_ctrl10_t ctrl10; @@ -1559,14 +1642,17 @@ int32_t lsm6dsv16x_xl_self_test_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dsv16x_xl_self_test_t *val) { lsm6dsv16x_ctrl10_t ctrl10; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl10.st_xl) { @@ -1598,7 +1684,7 @@ int32_t lsm6dsv16x_xl_self_test_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dsv16x_gy_self_test_t val) { lsm6dsv16x_ctrl10_t ctrl10; @@ -1623,14 +1709,17 @@ int32_t lsm6dsv16x_gy_self_test_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dsv16x_gy_self_test_t *val) { lsm6dsv16x_ctrl10_t ctrl10; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl10.st_g) { @@ -1662,7 +1751,7 @@ int32_t lsm6dsv16x_gy_self_test_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ois_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_xl_self_test_t val) { lsm6dsv16x_spi2_int_ois_t spi2_int_ois; @@ -1687,14 +1776,17 @@ int32_t lsm6dsv16x_ois_xl_self_test_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ois_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_xl_self_test_t *val) { lsm6dsv16x_spi2_int_ois_t spi2_int_ois; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (spi2_int_ois.st_xl_ois) { @@ -1726,7 +1818,7 @@ int32_t lsm6dsv16x_ois_xl_self_test_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ois_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_gy_self_test_t val) { lsm6dsv16x_spi2_int_ois_t spi2_int_ois; @@ -1752,14 +1844,17 @@ int32_t lsm6dsv16x_ois_gy_self_test_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ois_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_gy_self_test_t *val) { lsm6dsv16x_spi2_int_ois_t spi2_int_ois; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (spi2_int_ois.st_g_ois) { @@ -1768,11 +1863,13 @@ int32_t lsm6dsv16x_ois_gy_self_test_get(stmdev_ctx_t *ctx, break; case LSM6DSV16X_OIS_GY_ST_POSITIVE: - *val = (spi2_int_ois.st_ois_clampdis == 1U) ? LSM6DSV16X_OIS_GY_ST_CLAMP_POS : LSM6DSV16X_OIS_GY_ST_POSITIVE; + *val = (spi2_int_ois.st_ois_clampdis == 1U) ? LSM6DSV16X_OIS_GY_ST_CLAMP_POS : + LSM6DSV16X_OIS_GY_ST_POSITIVE; break; case LSM6DSV16X_OIS_GY_ST_NEGATIVE: - *val = (spi2_int_ois.st_ois_clampdis == 1U) ? LSM6DSV16X_OIS_GY_ST_CLAMP_NEG : LSM6DSV16X_OIS_GY_ST_NEGATIVE; + *val = (spi2_int_ois.st_ois_clampdis == 1U) ? LSM6DSV16X_OIS_GY_ST_CLAMP_NEG : + LSM6DSV16X_OIS_GY_ST_NEGATIVE; break; default: @@ -1799,15 +1896,24 @@ int32_t lsm6dsv16x_ois_gy_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsv16x_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm6dsv16x_pin_int_route_t *val) { lsm6dsv16x_int1_ctrl_t int1_ctrl; lsm6dsv16x_md1_cfg_t md1_cfg; int32_t ret; + /* not available on INT1 */ + if (val->drdy_temp == 1) + { + return -1; + } + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } int1_ctrl.int1_drdy_xl = val->drdy_xl; int1_ctrl.int1_drdy_g = val->drdy_g; @@ -1817,10 +1923,16 @@ int32_t lsm6dsv16x_pin_int1_route_set(stmdev_ctx_t *ctx, int1_ctrl.int1_cnt_bdr = val->cnt_bdr; ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MD1_CFG, (uint8_t *)&md1_cfg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } md1_cfg.int1_shub = val->shub; md1_cfg.int1_emb_func = val->emb_func; @@ -1844,7 +1956,7 @@ int32_t lsm6dsv16x_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsv16x_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm6dsv16x_pin_int_route_t *val) { lsm6dsv16x_int1_ctrl_t int1_ctrl; @@ -1852,7 +1964,10 @@ int32_t lsm6dsv16x_pin_int1_route_get(stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->drdy_xl = int1_ctrl.int1_drdy_xl; val->drdy_g = int1_ctrl.int1_drdy_g; @@ -1862,7 +1977,10 @@ int32_t lsm6dsv16x_pin_int1_route_get(stmdev_ctx_t *ctx, val->cnt_bdr = int1_ctrl.int1_cnt_bdr; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MD1_CFG, (uint8_t *)&md1_cfg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->shub = md1_cfg.int1_shub; val->emb_func = md1_cfg.int1_emb_func; @@ -1884,15 +2002,19 @@ int32_t lsm6dsv16x_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsv16x_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm6dsv16x_pin_int_route_t *val) { lsm6dsv16x_int2_ctrl_t int2_ctrl; + lsm6dsv16x_ctrl4_t ctrl4; lsm6dsv16x_md2_cfg_t md2_cfg; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } int2_ctrl.int2_drdy_xl = val->drdy_xl; int2_ctrl.int2_drdy_g = val->drdy_g; @@ -1904,10 +2026,24 @@ int32_t lsm6dsv16x_pin_int2_route_set(stmdev_ctx_t *ctx, int2_ctrl.int2_emb_func_endop = val->emb_func_endop; ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1); + ctrl4.int2_drdy_temp = val->drdy_temp; + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MD2_CFG, (uint8_t *)&md2_cfg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } md2_cfg.int2_timestamp = val->timestamp; md2_cfg.int2_emb_func = val->emb_func; @@ -1931,15 +2067,19 @@ int32_t lsm6dsv16x_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsv16x_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_pin_int2_route_get(const stmdev_ctx_t *ctx, lsm6dsv16x_pin_int_route_t *val) { lsm6dsv16x_int2_ctrl_t int2_ctrl; + lsm6dsv16x_ctrl4_t ctrl4; lsm6dsv16x_md2_cfg_t md2_cfg; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->drdy_xl = int2_ctrl.int2_drdy_xl; val->drdy_g = int2_ctrl.int2_drdy_g; @@ -1950,8 +2090,19 @@ int32_t lsm6dsv16x_pin_int2_route_get(stmdev_ctx_t *ctx, val->drdy_g_eis = int2_ctrl.int2_drdy_g_eis; val->emb_func_endop = int2_ctrl.int2_emb_func_endop; + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } + + val->drdy_temp = ctrl4.int2_drdy_temp; + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MD2_CFG, (uint8_t *)&md2_cfg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->timestamp = md2_cfg.int2_timestamp; val->emb_func = md2_cfg.int2_emb_func; @@ -1978,7 +2129,7 @@ int32_t lsm6dsv16x_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_all_sources_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_all_sources_get(const stmdev_ctx_t *ctx, lsm6dsv16x_all_sources_t *val) { lsm6dsv16x_emb_func_status_mainpage_t emb_func_status_mainpage; @@ -2001,10 +2152,16 @@ int32_t lsm6dsv16x_all_sources_get(stmdev_ctx_t *ctx, ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); functions_enable.dis_rst_lir_all_int = PROPERTY_ENABLE; ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_STATUS1, (uint8_t *)&buff, 4); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } bytecpy((uint8_t *)&fifo_status2, &buff[1]); bytecpy((uint8_t *)&all_int_src, &buff[2]); @@ -2030,10 +2187,16 @@ int32_t lsm6dsv16x_all_sources_get(stmdev_ctx_t *ctx, ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); functions_enable.dis_rst_lir_all_int = PROPERTY_DISABLE; ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_STATUS_REG_OIS, (uint8_t *)&buff, 8); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } bytecpy((uint8_t *)&status_reg_ois, &buff[0]); bytecpy((uint8_t *)&wake_up_src, &buff[1]); @@ -2083,13 +2246,16 @@ int32_t lsm6dsv16x_all_sources_get(stmdev_ctx_t *ctx, val->mlc3 = mlc_status_mainpage.is_mlc3; val->mlc4 = mlc_status_mainpage.is_mlc4; - /* embedded func */ ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); - ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, 1); + ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, + 1); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->emb_func_stand_by = emb_func_exec_status.emb_func_endop; val->emb_func_time_exceed = emb_func_exec_status.emb_func_exec_ovr; @@ -2101,7 +2267,10 @@ int32_t lsm6dsv16x_all_sources_get(stmdev_ctx_t *ctx, /* sensor hub */ ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_STATUS_MASTER_MAINPAGE, (uint8_t *)&status_shub, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->sh_endop = status_shub.sens_hub_endop; val->sh_wr_once = status_shub.wr_once_done; @@ -2113,14 +2282,17 @@ int32_t lsm6dsv16x_all_sources_get(stmdev_ctx_t *ctx, return ret; } -int32_t lsm6dsv16x_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_flag_data_ready_get(const stmdev_ctx_t *ctx, lsm6dsv16x_data_ready_t *val) { lsm6dsv16x_status_reg_t status; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_STATUS_REG, (uint8_t *)&status, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->drdy_xl = status.xlda; val->drdy_gy = status.gda; @@ -2137,7 +2309,7 @@ int32_t lsm6dsv16x_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_int_ack_mask_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_int_ack_mask_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; @@ -2154,7 +2326,7 @@ int32_t lsm6dsv16x_int_ack_mask_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_int_ack_mask_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_int_ack_mask_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -2171,13 +2343,16 @@ int32_t lsm6dsv16x_int_ack_mask_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsv16x_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_OUT_TEMP_L, &buff[0], 2); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -2193,13 +2368,16 @@ int32_t lsm6dsv16x_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsv16x_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_OUTX_L_G, &buff[0], 6); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; @@ -2219,13 +2397,16 @@ int32_t lsm6dsv16x_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ois_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsv16x_ois_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_OUTX_L_G_OIS, &buff[0], 6); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val[0] = (int16_t)buff[1]; val[0] = (*val * 256) + (int16_t)buff[0]; @@ -2245,13 +2426,16 @@ int32_t lsm6dsv16x_ois_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ois_eis_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsv16x_ois_eis_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_OUTX_L_G_OIS_EIS, &buff[0], 6); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val[0] = (int16_t)buff[1]; val[0] = (*val * 256) + (int16_t)buff[0]; @@ -2271,13 +2455,16 @@ int32_t lsm6dsv16x_ois_eis_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsv16x_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_OUTX_L_A, &buff[0], 6); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; @@ -2297,13 +2484,16 @@ int32_t lsm6dsv16x_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_dual_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsv16x_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_OUTX_L_A_OIS_DUALC, &buff[0], 6); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; @@ -2323,13 +2513,16 @@ int32_t lsm6dsv16x_dual_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ah_qvar_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsv16x_ah_qvar_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_AH_QVAR_OUT_L, &buff[0], 2); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -2345,7 +2538,7 @@ int32_t lsm6dsv16x_ah_qvar_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_odr_cal_reg_get(stmdev_ctx_t *ctx, int8_t *val) +int32_t lsm6dsv16x_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val) { lsm6dsv16x_internal_freq_t internal_freq; int32_t ret; @@ -2364,7 +2557,7 @@ int32_t lsm6dsv16x_odr_cal_reg_get(stmdev_ctx_t *ctx, int8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dsv16x_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len) { lsm6dsv16x_page_address_t page_address; @@ -2379,32 +2572,47 @@ int32_t lsm6dsv16x_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, lsb = (uint8_t)address & 0xFFU; ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } /* set page write */ ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1); page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_ENABLE; ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } /* select page */ ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1); page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } /* set page addr */ page_address.page_addr = lsb; ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_ADDRESS, (uint8_t *)&page_address, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } for (i = 0; ((i < len) && (ret == 0)); i++) { ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_VALUE, &buf[i], 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } lsb++; @@ -2413,19 +2621,28 @@ int32_t lsm6dsv16x_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, { msb++; ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } } } page_sel.page_sel = 0; page_sel.not_used0 = 1;// Default value ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } /* unset page write */ ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1); @@ -2454,7 +2671,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, +int32_t lsm6dsv16x_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len) { lsm6dsv16x_page_address_t page_address; @@ -2469,32 +2686,47 @@ int32_t lsm6dsv16x_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, lsb = (uint8_t)address & 0xFFU; ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } /* set page write */ ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1); page_rw.page_read = PROPERTY_ENABLE; page_rw.page_write = PROPERTY_DISABLE; ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } /* select page */ ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1); page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } /* set page addr */ page_address.page_addr = lsb; ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_ADDRESS, (uint8_t *)&page_address, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } for (i = 0; ((i < len) && (ret == 0)); i++) { ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_VALUE, &buf[i], 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } lsb++; @@ -2503,19 +2735,28 @@ int32_t lsm6dsv16x_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, { msb++; ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } } } page_sel.page_sel = 0; page_sel.not_used0 = 1;// Default value ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } /* unset page write */ ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1); @@ -2537,7 +2778,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_emb_function_dbg_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_emb_function_dbg_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_ctrl10_t ctrl10; int32_t ret; @@ -2561,13 +2802,16 @@ int32_t lsm6dsv16x_emb_function_dbg_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_emb_function_dbg_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_emb_function_dbg_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_ctrl10_t ctrl10; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } *val = ctrl10.emb_func_debug; @@ -2595,7 +2839,7 @@ int32_t lsm6dsv16x_emb_function_dbg_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dsv16x_den_polarity_t val) { lsm6dsv16x_ctrl4_t ctrl4; @@ -2620,14 +2864,17 @@ int32_t lsm6dsv16x_den_polarity_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dsv16x_den_polarity_t *val) { lsm6dsv16x_ctrl4_t ctrl4; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl4.int2_in_lh) { @@ -2655,13 +2902,16 @@ int32_t lsm6dsv16x_den_polarity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_den_conf_set(stmdev_ctx_t *ctx, lsm6dsv16x_den_conf_t val) +int32_t lsm6dsv16x_den_conf_set(const stmdev_ctx_t *ctx, lsm6dsv16x_den_conf_t val) { lsm6dsv16x_den_t den; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_DEN, (uint8_t *)&den, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } den.den_z = val.den_z; den.den_y = val.den_y; @@ -2710,19 +2960,22 @@ int32_t lsm6dsv16x_den_conf_set(stmdev_ctx_t *ctx, lsm6dsv16x_den_conf_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_den_conf_get(stmdev_ctx_t *ctx, lsm6dsv16x_den_conf_t *val) +int32_t lsm6dsv16x_den_conf_get(const stmdev_ctx_t *ctx, lsm6dsv16x_den_conf_t *val) { lsm6dsv16x_den_t den; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_DEN, (uint8_t *)&den, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->den_z = den.den_z; val->den_y = den.den_y; val->den_x = den.den_x; - if ((den.den_z | den.den_z | den.den_z) == PROPERTY_ENABLE) + if ((den.den_x | den.den_y | den.den_z) == PROPERTY_ENABLE) { if (den.den_xl_g == PROPERTY_DISABLE && den.den_xl_en == PROPERTY_ENABLE) { @@ -2748,16 +3001,16 @@ int32_t lsm6dsv16x_den_conf_get(stmdev_ctx_t *ctx, lsm6dsv16x_den_conf_t *val) switch ((den.lvl1_en << 1) + den.lvl2_en) { - case LEVEL_TRIGGER: - val->mode = LEVEL_TRIGGER; + case LSM6DSV16X_LEVEL_TRIGGER: + val->mode = LSM6DSV16X_LEVEL_TRIGGER; break; - case LEVEL_LATCHED: - val->mode = LEVEL_LATCHED; + case LSM6DSV16X_LEVEL_LATCHED: + val->mode = LSM6DSV16X_LEVEL_LATCHED; break; default: - val->mode = DEN_NOT_DEFINED; + val->mode = LSM6DSV16X_DEN_NOT_DEFINED; break; } @@ -2784,7 +3037,7 @@ int32_t lsm6dsv16x_den_conf_get(stmdev_ctx_t *ctx, lsm6dsv16x_den_conf_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_eis_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_eis_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsv16x_eis_gy_full_scale_t val) { lsm6dsv16x_ctrl_eis_t ctrl_eis; @@ -2809,14 +3062,17 @@ int32_t lsm6dsv16x_eis_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_eis_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_eis_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsv16x_eis_gy_full_scale_t *val) { lsm6dsv16x_ctrl_eis_t ctrl_eis; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl_eis.fs_g_eis) { @@ -2855,7 +3111,7 @@ int32_t lsm6dsv16x_eis_gy_full_scale_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_eis_gy_on_spi2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_eis_gy_on_spi2_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_ctrl_eis_t ctrl_eis; int32_t ret; @@ -2879,7 +3135,7 @@ int32_t lsm6dsv16x_eis_gy_on_spi2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_eis_gy_on_spi2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_eis_gy_on_spi2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_ctrl_eis_t ctrl_eis; int32_t ret; @@ -2898,7 +3154,7 @@ int32_t lsm6dsv16x_eis_gy_on_spi2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_gy_eis_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_gy_eis_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv16x_gy_eis_data_rate_t val) { lsm6dsv16x_ctrl_eis_t ctrl_eis; @@ -2923,14 +3179,17 @@ int32_t lsm6dsv16x_gy_eis_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_gy_eis_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_gy_eis_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv16x_gy_eis_data_rate_t *val) { lsm6dsv16x_ctrl_eis_t ctrl_eis; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl_eis.odr_g_eis) { @@ -2974,7 +3233,7 @@ int32_t lsm6dsv16x_gy_eis_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_fifo_ctrl1_t fifo_ctrl1; int32_t ret; @@ -2998,7 +3257,7 @@ int32_t lsm6dsv16x_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_fifo_ctrl1_t fifo_ctrl1; int32_t ret; @@ -3017,7 +3276,7 @@ int32_t lsm6dsv16x_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_xl_dual_fsm_batch_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -3040,7 +3299,7 @@ int32_t lsm6dsv16x_fifo_xl_dual_fsm_batch_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_xl_dual_fsm_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -3059,7 +3318,7 @@ int32_t lsm6dsv16x_fifo_xl_dual_fsm_batch_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_compress_algo_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_compress_algo_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_compress_algo_t val) { lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2; @@ -3083,14 +3342,17 @@ int32_t lsm6dsv16x_fifo_compress_algo_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_compress_algo_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_compress_algo_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_compress_algo_t *val) { lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (fifo_ctrl2.uncompr_rate) { @@ -3125,7 +3387,7 @@ int32_t lsm6dsv16x_fifo_compress_algo_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -3148,7 +3410,7 @@ int32_t lsm6dsv16x_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2; @@ -3168,7 +3430,7 @@ int32_t lsm6dsv16x_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_compress_algo_real_time_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_emb_func_en_b_t emb_func_en_b; @@ -3179,10 +3441,16 @@ int32_t lsm6dsv16x_fifo_compress_algo_real_time_set(stmdev_ctx_t *ctx, ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); fifo_ctrl2.fifo_compr_rt_en = val; ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); emb_func_en_b.fifo_compr_en = val; @@ -3200,7 +3468,7 @@ int32_t lsm6dsv16x_fifo_compress_algo_real_time_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_compress_algo_real_time_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2; @@ -3221,7 +3489,7 @@ int32_t lsm6dsv16x_fifo_compress_algo_real_time_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -3244,7 +3512,7 @@ int32_t lsm6dsv16x_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -3263,7 +3531,7 @@ int32_t lsm6dsv16x_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_xl_batch_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_xl_batch_t val) { lsm6dsv16x_fifo_ctrl3_t fifo_ctrl3; @@ -3287,14 +3555,17 @@ int32_t lsm6dsv16x_fifo_xl_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_xl_batch_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_xl_batch_t *val) { lsm6dsv16x_fifo_ctrl3_t fifo_ctrl3; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (fifo_ctrl3.bdr_xl) { @@ -3366,7 +3637,7 @@ int32_t lsm6dsv16x_fifo_xl_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_gy_batch_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_gy_batch_t val) { lsm6dsv16x_fifo_ctrl3_t fifo_ctrl3; @@ -3390,14 +3661,17 @@ int32_t lsm6dsv16x_fifo_gy_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_gy_batch_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_gy_batch_t *val) { lsm6dsv16x_fifo_ctrl3_t fifo_ctrl3; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (fifo_ctrl3.bdr_gy) { @@ -3469,7 +3743,7 @@ int32_t lsm6dsv16x_fifo_gy_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_fifo_mode_t val) +int32_t lsm6dsv16x_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_mode_t val) { lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4; int32_t ret; @@ -3492,13 +3766,16 @@ int32_t lsm6dsv16x_fifo_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_fifo_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_fifo_mode_t *val) +int32_t lsm6dsv16x_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_mode_t *val) { lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (fifo_ctrl4.fifo_mode) { @@ -3545,7 +3822,7 @@ int32_t lsm6dsv16x_fifo_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_fifo_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_gy_eis_batch_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_fifo_gy_eis_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4; int32_t ret; @@ -3568,7 +3845,7 @@ int32_t lsm6dsv16x_fifo_gy_eis_batch_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_gy_eis_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_fifo_gy_eis_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4; int32_t ret; @@ -3587,7 +3864,7 @@ int32_t lsm6dsv16x_fifo_gy_eis_batch_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_temp_batch_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_temp_batch_t val) { lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4; @@ -3611,14 +3888,17 @@ int32_t lsm6dsv16x_fifo_temp_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_temp_batch_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_temp_batch_t *val) { lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (fifo_ctrl4.odr_t_batch) { @@ -3653,7 +3933,7 @@ int32_t lsm6dsv16x_fifo_temp_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_timestamp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_timestamp_batch_t val) { lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4; @@ -3677,14 +3957,17 @@ int32_t lsm6dsv16x_fifo_timestamp_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_timestamp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_timestamp_batch_t *val) { lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (fifo_ctrl4.dec_ts_batch) { @@ -3720,15 +4003,22 @@ int32_t lsm6dsv16x_fifo_timestamp_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_batch_counter_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { - uint8_t buff[2]; + lsm6dsv16x_counter_bdr_reg1_t counter_bdr_reg1; + lsm6dsv16x_counter_bdr_reg2_t counter_bdr_reg2; int32_t ret; - buff[1] = (uint8_t)(val / 256U); - buff[0] = (uint8_t)(val - (buff[1] * 256U)); - ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_COUNTER_BDR_REG1, (uint8_t *)&buff[0], 2); + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + + if (ret == 0) + { + counter_bdr_reg2.cnt_bdr_th = (uint8_t)val & 0xFFU; + counter_bdr_reg1.cnt_bdr_th = (uint8_t)(val >> 8) & 0x3U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_COUNTER_BDR_REG2, (uint8_t *)&counter_bdr_reg2, 1); + } return ret; } @@ -3741,17 +4031,20 @@ int32_t lsm6dsv16x_fifo_batch_counter_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_COUNTER_BDR_REG1, &buff[0], 2); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + *val = (uint16_t)buff[0] & 0x3U; + *val = (*val * 256U) + (uint16_t)buff[1]; return ret; } @@ -3764,7 +4057,7 @@ int32_t lsm6dsv16x_fifo_batch_counter_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_batch_cnt_event_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_batch_cnt_event_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_batch_cnt_event_t val) { lsm6dsv16x_counter_bdr_reg1_t counter_bdr_reg1; @@ -3788,14 +4081,17 @@ int32_t lsm6dsv16x_fifo_batch_cnt_event_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_batch_cnt_event_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_batch_cnt_event_t *val) { lsm6dsv16x_counter_bdr_reg1_t counter_bdr_reg1; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (counter_bdr_reg1.trig_counter_bdr) { @@ -3819,7 +4115,7 @@ int32_t lsm6dsv16x_fifo_batch_cnt_event_get(stmdev_ctx_t *ctx, return ret; } -int32_t lsm6dsv16x_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_status_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_status_t *val) { uint8_t buff[2]; @@ -3827,7 +4123,10 @@ int32_t lsm6dsv16x_fifo_status_get(stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_STATUS1, (uint8_t *)&buff[0], 2); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } bytecpy((uint8_t *)&status, &buff[1]); @@ -3847,18 +4146,11 @@ int32_t lsm6dsv16x_fifo_status_get(stmdev_ctx_t *ctx, * @brief FIFO data output[get] * * @param ctx read / write interface definitions - * @param val FIFO_EMPTY, GY_NC_TAG, XL_NC_TAG, TIMESTAMP_TAG, - TEMPERATURE_TAG, CFG_CHANGE_TAG, XL_NC_T_2_TAG, - XL_NC_T_1_TAG, XL_2XC_TAG, XL_3XC_TAG, GY_NC_T_2_TAG, - GY_NC_T_1_TAG, GY_2XC_TAG, GY_3XC_TAG, SENSORHUB_SLAVE0_TAG, - SENSORHUB_SLAVE1_TAG, SENSORHUB_SLAVE2_TAG, SENSORHUB_SLAVE3_TAG, - STEP_COUNTER_TAG, SFLP_GAME_ROTATION_VECTOR_TAG, SFLP_GYROSCOPE_BIAS_TAG, - SFLP_GRAVITY_VECTOR_TAG, SENSORHUB_NACK_TAG, MLC_RESULT_TAG, - MLC_FILTER, MLC_FEATURE, XL_DUAL_CORE, GY_ENHANCED_EIS, + * @param val lsm6dsv16x_fifo_out_raw_t * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_out_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_out_raw_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_out_raw_t *val) { lsm6dsv16x_fifo_data_out_tag_t fifo_data_out_tag; @@ -3866,7 +4158,10 @@ int32_t lsm6dsv16x_fifo_out_raw_get(stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_DATA_OUT_TAG, buff, 7); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } bytecpy((uint8_t *)&fifo_data_out_tag, &buff[0]); @@ -4009,13 +4304,16 @@ int32_t lsm6dsv16x_fifo_out_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_stpcnt_batch_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_emb_func_fifo_en_a_t emb_func_fifo_en_a; int32_t ret; ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); emb_func_fifo_en_a.step_counter_fifo_en = val; @@ -4034,13 +4332,16 @@ int32_t lsm6dsv16x_fifo_stpcnt_batch_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_stpcnt_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_emb_func_fifo_en_a_t emb_func_fifo_en_a; int32_t ret; ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); *val = emb_func_fifo_en_a.step_counter_fifo_en; @@ -4058,13 +4359,16 @@ int32_t lsm6dsv16x_fifo_stpcnt_batch_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_mlc_batch_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_fifo_mlc_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_emb_func_fifo_en_a_t emb_func_fifo_en_a; int32_t ret; ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); emb_func_fifo_en_a.mlc_fifo_en = val; @@ -4083,13 +4387,16 @@ int32_t lsm6dsv16x_fifo_mlc_batch_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_mlc_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_fifo_mlc_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_emb_func_fifo_en_a_t emb_func_fifo_en_a; int32_t ret; ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); *val = emb_func_fifo_en_a.mlc_fifo_en; @@ -4107,13 +4414,16 @@ int32_t lsm6dsv16x_fifo_mlc_batch_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_mlc_filt_batch_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_fifo_mlc_filt_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_emb_func_fifo_en_b_t emb_func_fifo_en_b; int32_t ret; ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); emb_func_fifo_en_b.mlc_filter_feature_fifo_en = val; @@ -4132,13 +4442,16 @@ int32_t lsm6dsv16x_fifo_mlc_filt_batch_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_mlc_filt_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_fifo_mlc_filt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_emb_func_fifo_en_b_t emb_func_fifo_en_b; int32_t ret; ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); *val = emb_func_fifo_en_b.mlc_filter_feature_fifo_en; @@ -4156,17 +4469,20 @@ int32_t lsm6dsv16x_fifo_mlc_filt_batch_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_sh_batch_slave_set(stmdev_ctx_t *ctx, uint8_t idx, uint8_t val) +int32_t lsm6dsv16x_fifo_sh_batch_slave_set(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t val) { lsm6dsv16x_slv0_config_t slv_config; int32_t ret; ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } - ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV0_CONFIG + idx*3U, (uint8_t *)&slv_config, 1); + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1); slv_config.batch_ext_sens_0_en = val; - ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_CONFIG + idx*3U, (uint8_t *)&slv_config, 1); + ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1); ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); @@ -4181,15 +4497,18 @@ int32_t lsm6dsv16x_fifo_sh_batch_slave_set(stmdev_ctx_t *ctx, uint8_t idx, uint8 * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_sh_batch_slave_get(stmdev_ctx_t *ctx, uint8_t idx, uint8_t *val) +int32_t lsm6dsv16x_fifo_sh_batch_slave_get(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t *val) { lsm6dsv16x_slv0_config_t slv_config; int32_t ret; ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } - ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV0_CONFIG + idx*3U, (uint8_t *)&slv_config, 1); + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1); *val = slv_config.batch_ext_sens_0_en; ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); @@ -4205,7 +4524,7 @@ int32_t lsm6dsv16x_fifo_sh_batch_slave_get(stmdev_ctx_t *ctx, uint8_t idx, uint8 * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_sflp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_sflp_batch_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_sflp_raw_t val) { lsm6dsv16x_emb_func_fifo_en_a_t emb_func_fifo_en_a; @@ -4235,7 +4554,7 @@ int32_t lsm6dsv16x_fifo_sflp_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fifo_sflp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_sflp_batch_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_sflp_raw_t *val) { lsm6dsv16x_emb_func_fifo_en_a_t emb_func_fifo_en_a; @@ -4277,7 +4596,7 @@ int32_t lsm6dsv16x_fifo_sflp_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_anti_spike_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_anti_spike_set(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_anti_spike_t val) { lsm6dsv16x_if_cfg_t if_cfg; @@ -4302,14 +4621,17 @@ int32_t lsm6dsv16x_filt_anti_spike_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_anti_spike_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_anti_spike_get(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_anti_spike_t *val) { lsm6dsv16x_if_cfg_t if_cfg; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (if_cfg.asf_ctrl) { @@ -4337,7 +4659,7 @@ int32_t lsm6dsv16x_filt_anti_spike_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_settling_mask_set(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_settling_mask_t val) { lsm6dsv16x_emb_func_cfg_t emb_func_cfg; @@ -4348,13 +4670,19 @@ int32_t lsm6dsv16x_filt_settling_mask_set(stmdev_ctx_t *ctx, ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1); ctrl4.drdy_mask = val.drdy; ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); emb_func_cfg.emb_func_irq_mask_xl_settl = val.irq_xl; emb_func_cfg.emb_func_irq_mask_g_settl = val.irq_g; ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1); ui_int_ois.drdy_mask_ois = val.ois_drdy; @@ -4371,7 +4699,7 @@ int32_t lsm6dsv16x_filt_settling_mask_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_settling_mask_get(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_settling_mask_t *val) { lsm6dsv16x_emb_func_cfg_t emb_func_cfg; @@ -4398,7 +4726,7 @@ int32_t lsm6dsv16x_filt_settling_mask_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_ois_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_ois_settling_mask_set(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_ois_settling_mask_t val) { lsm6dsv16x_spi2_int_ois_t spi2_int_ois; @@ -4423,7 +4751,7 @@ int32_t lsm6dsv16x_filt_ois_settling_mask_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_ois_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_ois_settling_mask_get(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_ois_settling_mask_t *val) { @@ -4444,7 +4772,7 @@ int32_t lsm6dsv16x_filt_ois_settling_mask_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_gy_lp1_bandwidth_t val) { lsm6dsv16x_ctrl6_t ctrl6; @@ -4468,14 +4796,17 @@ int32_t lsm6dsv16x_filt_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_gy_lp1_bandwidth_t *val) { lsm6dsv16x_ctrl6_t ctrl6; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL6, (uint8_t *)&ctrl6, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl6.lpf1_g_bw) { @@ -4527,7 +4858,7 @@ int32_t lsm6dsv16x_filt_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_gy_lp1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_filt_gy_lp1_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_ctrl7_t ctrl7; int32_t ret; @@ -4551,7 +4882,7 @@ int32_t lsm6dsv16x_filt_gy_lp1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_gy_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_ctrl7_t ctrl7; int32_t ret; @@ -4570,7 +4901,7 @@ int32_t lsm6dsv16x_filt_gy_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_xl_lp2_bandwidth_t val) { lsm6dsv16x_ctrl8_t ctrl8; @@ -4594,14 +4925,17 @@ int32_t lsm6dsv16x_filt_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_xl_lp2_bandwidth_t *val) { lsm6dsv16x_ctrl8_t ctrl8; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl8.hp_lpf2_xl_bw) { @@ -4653,7 +4987,7 @@ int32_t lsm6dsv16x_filt_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_xl_lp2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_filt_xl_lp2_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_ctrl9_t ctrl9; int32_t ret; @@ -4676,7 +5010,7 @@ int32_t lsm6dsv16x_filt_xl_lp2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_xl_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_ctrl9_t ctrl9; int32_t ret; @@ -4695,7 +5029,7 @@ int32_t lsm6dsv16x_filt_xl_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_xl_hp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_filt_xl_hp_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_ctrl9_t ctrl9; int32_t ret; @@ -4718,7 +5052,7 @@ int32_t lsm6dsv16x_filt_xl_hp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_xl_hp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_ctrl9_t ctrl9; int32_t ret; @@ -4737,7 +5071,7 @@ int32_t lsm6dsv16x_filt_xl_hp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_filt_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_ctrl9_t ctrl9; int32_t ret; @@ -4760,7 +5094,7 @@ int32_t lsm6dsv16x_filt_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_ctrl9_t ctrl9; int32_t ret; @@ -4779,7 +5113,7 @@ int32_t lsm6dsv16x_filt_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_xl_hp_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_xl_hp_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_xl_hp_mode_t val) { lsm6dsv16x_ctrl9_t ctrl9; @@ -4803,14 +5137,17 @@ int32_t lsm6dsv16x_filt_xl_hp_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_xl_hp_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_xl_hp_mode_t *val) { lsm6dsv16x_ctrl9_t ctrl9; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl9.hp_ref_mode_xl) { @@ -4838,7 +5175,7 @@ int32_t lsm6dsv16x_filt_xl_hp_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_wkup_act_feed_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_wkup_act_feed_t val) { lsm6dsv16x_wake_up_ths_t wake_up_ths; @@ -4847,11 +5184,17 @@ int32_t lsm6dsv16x_filt_wkup_act_feed_set(stmdev_ctx_t *ctx, ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } tap_cfg0.slope_fds = (uint8_t)val & 0x01U; ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } wake_up_ths.usr_off_on_wu = ((uint8_t)val & 0x02U) >> 1; ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); @@ -4867,7 +5210,7 @@ int32_t lsm6dsv16x_filt_wkup_act_feed_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_wkup_act_feed_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_wkup_act_feed_t *val) { lsm6dsv16x_wake_up_ths_t wake_up_ths; @@ -4876,7 +5219,10 @@ int32_t lsm6dsv16x_filt_wkup_act_feed_get(stmdev_ctx_t *ctx, ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch ((wake_up_ths.usr_off_on_wu << 1) + tap_cfg0.slope_fds) { @@ -4908,7 +5254,7 @@ int32_t lsm6dsv16x_filt_wkup_act_feed_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_mask_trigger_xl_settl_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_mask_trigger_xl_settl_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_tap_cfg0_t tap_cfg0; int32_t ret; @@ -4932,7 +5278,7 @@ int32_t lsm6dsv16x_mask_trigger_xl_settl_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_mask_trigger_xl_settl_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_tap_cfg0_t tap_cfg0; int32_t ret; @@ -4951,7 +5297,7 @@ int32_t lsm6dsv16x_mask_trigger_xl_settl_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_sixd_feed_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_sixd_feed_set(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_sixd_feed_t val) { lsm6dsv16x_tap_cfg0_t tap_cfg0; @@ -4976,14 +5322,17 @@ int32_t lsm6dsv16x_filt_sixd_feed_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_sixd_feed_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_sixd_feed_get(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_sixd_feed_t *val) { lsm6dsv16x_tap_cfg0_t tap_cfg0; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (tap_cfg0.low_pass_on_6d) { @@ -5011,7 +5360,7 @@ int32_t lsm6dsv16x_filt_sixd_feed_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_gy_eis_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_gy_eis_lp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_gy_eis_lp_bandwidth_t val) { lsm6dsv16x_ctrl_eis_t ctrl_eis; @@ -5036,14 +5385,17 @@ int32_t lsm6dsv16x_filt_gy_eis_lp_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_gy_eis_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_gy_eis_lp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_gy_eis_lp_bandwidth_t *val) { lsm6dsv16x_ctrl_eis_t ctrl_eis; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl_eis.lpf_g_eis_bw) { @@ -5071,7 +5423,7 @@ int32_t lsm6dsv16x_filt_gy_eis_lp_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_gy_ois_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_gy_ois_lp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_gy_ois_lp_bandwidth_t val) { lsm6dsv16x_ui_ctrl2_ois_t ui_ctrl2_ois; @@ -5096,7 +5448,7 @@ int32_t lsm6dsv16x_filt_gy_ois_lp_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_gy_ois_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_gy_ois_lp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_gy_ois_lp_bandwidth_t *val) { @@ -5104,7 +5456,10 @@ int32_t lsm6dsv16x_filt_gy_ois_lp_bandwidth_get(stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ui_ctrl2_ois.lpf1_g_ois_bw) { @@ -5140,7 +5495,7 @@ int32_t lsm6dsv16x_filt_gy_ois_lp_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_xl_ois_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_xl_ois_lp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_xl_ois_lp_bandwidth_t val) { lsm6dsv16x_ui_ctrl3_ois_t ui_ctrl3_ois; @@ -5165,14 +5520,17 @@ int32_t lsm6dsv16x_filt_xl_ois_lp_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_filt_xl_ois_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_xl_ois_lp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_xl_ois_lp_bandwidth_t *val) { lsm6dsv16x_ui_ctrl3_ois_t ui_ctrl3_ois; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ui_ctrl3_ois.lpf_xl_ois_bw) { @@ -5237,7 +5595,7 @@ int32_t lsm6dsv16x_filt_xl_ois_lp_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_permission_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_permission_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_permission_t val) { lsm6dsv16x_func_cfg_access_t func_cfg_access; @@ -5262,14 +5620,17 @@ int32_t lsm6dsv16x_fsm_permission_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_permission_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_permission_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_permission_t *val) { lsm6dsv16x_func_cfg_access_t func_cfg_access; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (func_cfg_access.fsm_wr_ctrl_en) { @@ -5297,7 +5658,7 @@ int32_t lsm6dsv16x_fsm_permission_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_permission_status(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_fsm_permission_status(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_ctrl_status_t ctrl_status; int32_t ret; @@ -5317,21 +5678,27 @@ int32_t lsm6dsv16x_fsm_permission_status(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_fsm_mode_t val) +int32_t lsm6dsv16x_fsm_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_mode_t val) { lsm6dsv16x_emb_func_en_b_t emb_func_en_b; lsm6dsv16x_fsm_enable_t fsm_enable; int32_t ret; ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } - if ((val.fsm1_en | val.fsm2_en | val.fsm1_en | val.fsm1_en - | val.fsm1_en | val.fsm2_en | val.fsm1_en | val.fsm1_en) == PROPERTY_ENABLE) + if ((val.fsm1_en | val.fsm2_en | val.fsm3_en | val.fsm4_en + | val.fsm5_en | val.fsm6_en | val.fsm7_en | val.fsm8_en) == PROPERTY_ENABLE) { emb_func_en_b.fsm_en = PROPERTY_ENABLE; } @@ -5366,7 +5733,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_fsm_mode_t *val) +int32_t lsm6dsv16x_fsm_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_mode_t *val) { lsm6dsv16x_fsm_enable_t fsm_enable; int32_t ret; @@ -5374,7 +5741,10 @@ int32_t lsm6dsv16x_fsm_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_fsm_mode_t *val) ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->fsm1_en = fsm_enable.fsm1_en; val->fsm2_en = fsm_enable.fsm2_en; @@ -5396,7 +5766,7 @@ int32_t lsm6dsv16x_fsm_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_fsm_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsv16x_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -5419,7 +5789,7 @@ int32_t lsm6dsv16x_fsm_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsv16x_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -5427,7 +5797,10 @@ int32_t lsm6dsv16x_fsm_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FSM_LONG_COUNTER_L, &buff[0], 2); ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -5443,7 +5816,7 @@ int32_t lsm6dsv16x_fsm_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsv16x_fsm_out_t *val) +int32_t lsm6dsv16x_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_out_t *val) { int32_t ret; @@ -5462,7 +5835,7 @@ int32_t lsm6dsv16x_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsv16x_fsm_out_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_data_rate_t val) { lsm6dsv16x_fsm_odr_t fsm_odr; @@ -5470,7 +5843,10 @@ int32_t lsm6dsv16x_fsm_data_rate_set(stmdev_ctx_t *ctx, ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FSM_ODR, (uint8_t *)&fsm_odr, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } fsm_odr.fsm_odr = (uint8_t)val & 0x07U; ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FSM_ODR, (uint8_t *)&fsm_odr, 1); @@ -5489,7 +5865,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_data_rate_t *val) { lsm6dsv16x_fsm_odr_t fsm_odr; @@ -5498,7 +5874,10 @@ int32_t lsm6dsv16x_fsm_data_rate_get(stmdev_ctx_t *ctx, ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FSM_ODR, (uint8_t *)&fsm_odr, 1); ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (fsm_odr.fsm_odr) { @@ -5546,6 +5925,13 @@ int32_t lsm6dsv16x_fsm_data_rate_get(stmdev_ctx_t *ctx, * * Released under BSD-3-Clause License */ + +#define NPY_HALF_GENERATE_OVERFLOW 0 /* do not trigger FP overflow */ +#define NPY_HALF_GENERATE_UNDERFLOW 0 /* do not trigger FP underflow */ +#ifndef NPY_HALF_ROUND_TIES_TO_EVEN +#define NPY_HALF_ROUND_TIES_TO_EVEN 1 +#endif + static uint16_t npy_floatbits_to_halfbits(uint32_t f) { uint32_t f_exp, f_sig; @@ -5705,7 +6091,7 @@ static uint16_t npy_float_to_half(float_t f) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_sflp_game_gbias_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sflp_game_gbias_set(const stmdev_ctx_t *ctx, lsm6dsv16x_sflp_gbias_t *val) { lsm6dsv16x_sflp_data_rate_t sflp_odr; @@ -5726,7 +6112,10 @@ int32_t lsm6dsv16x_sflp_game_gbias_set(stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16x_sflp_data_rate_get(ctx, &sflp_odr); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } /* Calculate k factor */ switch (sflp_odr) @@ -5864,7 +6253,7 @@ int32_t lsm6dsv16x_sflp_game_gbias_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_ext_sens_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsv16x_fsm_ext_sens_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -5884,14 +6273,17 @@ int32_t lsm6dsv16x_fsm_ext_sens_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_ext_sens_sensitivity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_ext_sens_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_FSM_EXT_SENSITIVITY_L, &buff[0], 2); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -5907,7 +6299,7 @@ int32_t lsm6dsv16x_fsm_ext_sens_sensitivity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_ext_sens_offset_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_ext_sens_offset_set(const stmdev_ctx_t *ctx, lsm6dsv16x_xl_fsm_ext_sens_offset_t val) { uint8_t buff[6]; @@ -5932,14 +6324,17 @@ int32_t lsm6dsv16x_fsm_ext_sens_offset_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_ext_sens_offset_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_ext_sens_offset_get(const stmdev_ctx_t *ctx, lsm6dsv16x_xl_fsm_ext_sens_offset_t *val) { uint8_t buff[6]; int32_t ret; ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_FSM_EXT_OFFX_L, &buff[0], 6); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->x = buff[1]; val->x = (val->x * 256U) + buff[0]; @@ -5959,7 +6354,7 @@ int32_t lsm6dsv16x_fsm_ext_sens_offset_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_ext_sens_matrix_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_ext_sens_matrix_set(const stmdev_ctx_t *ctx, lsm6dsv16x_xl_fsm_ext_sens_matrix_t val) { uint8_t buff[12]; @@ -5990,14 +6385,17 @@ int32_t lsm6dsv16x_fsm_ext_sens_matrix_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_ext_sens_matrix_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_ext_sens_matrix_get(const stmdev_ctx_t *ctx, lsm6dsv16x_xl_fsm_ext_sens_matrix_t *val) { uint8_t buff[12]; int32_t ret; ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_FSM_EXT_MATRIX_XX_L, &buff[0], 12); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->xx = buff[1]; val->xx = (val->xx * 256U) + buff[0]; @@ -6023,7 +6421,7 @@ int32_t lsm6dsv16x_fsm_ext_sens_matrix_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_ext_sens_z_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_ext_sens_z_orient_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_ext_sens_z_orient_t val) { lsm6dsv16x_ext_cfg_a_t ext_cfg_a; @@ -6044,14 +6442,17 @@ int32_t lsm6dsv16x_fsm_ext_sens_z_orient_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_ext_sens_z_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_ext_sens_z_orient_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_ext_sens_z_orient_t *val) { lsm6dsv16x_ext_cfg_a_t ext_cfg_a; int32_t ret; ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ext_cfg_a.ext_z_axis) { @@ -6095,7 +6496,7 @@ int32_t lsm6dsv16x_fsm_ext_sens_z_orient_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_ext_sens_y_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_ext_sens_y_orient_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_ext_sens_y_orient_t val) { lsm6dsv16x_ext_cfg_a_t ext_cfg_a; @@ -6119,14 +6520,17 @@ int32_t lsm6dsv16x_fsm_ext_sens_y_orient_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_ext_sens_y_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_ext_sens_y_orient_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_ext_sens_y_orient_t *val) { lsm6dsv16x_ext_cfg_a_t ext_cfg_a; int32_t ret; ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ext_cfg_a.ext_y_axis) { @@ -6170,7 +6574,7 @@ int32_t lsm6dsv16x_fsm_ext_sens_y_orient_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_ext_sens_x_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_ext_sens_x_orient_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_ext_sens_x_orient_t val) { lsm6dsv16x_ext_cfg_b_t ext_cfg_b; @@ -6194,14 +6598,17 @@ int32_t lsm6dsv16x_fsm_ext_sens_x_orient_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_ext_sens_x_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_ext_sens_x_orient_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_ext_sens_x_orient_t *val) { lsm6dsv16x_ext_cfg_b_t ext_cfg_b; int32_t ret; ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EXT_CFG_B, (uint8_t *)&ext_cfg_b, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ext_cfg_b.ext_x_axis) { @@ -6245,14 +6652,15 @@ int32_t lsm6dsv16x_fsm_ext_sens_x_orient_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_long_cnt_timeout_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsv16x_fsm_long_cnt_timeout_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; buff[1] = (uint8_t)(val / 256U); buff[0] = (uint8_t)(val - (buff[1] * 256U)); - ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_LC_TIMEOUT_L, (uint8_t *)&buff[0], 2); + ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_LC_TIMEOUT_L, + (uint8_t *)&buff[0], 2); return ret; } @@ -6265,13 +6673,17 @@ int32_t lsm6dsv16x_fsm_long_cnt_timeout_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_long_cnt_timeout_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsv16x_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; - ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_LC_TIMEOUT_L, &buff[0], 2); - if (ret != 0) { return ret; } + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_LC_TIMEOUT_L, &buff[0], + 2); + if (ret != 0) + { + return ret; + } *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -6287,16 +6699,18 @@ int32_t lsm6dsv16x_fsm_long_cnt_timeout_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_fsm_programs_t fsm_programs; int32_t ret; - ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_PROGRAMS, + (uint8_t *)&fsm_programs, 1); if (ret == 0) { fsm_programs.fsm_n_prog = val; - ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_PROGRAMS, + (uint8_t *)&fsm_programs, 1); } return ret; @@ -6310,12 +6724,13 @@ int32_t lsm6dsv16x_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_fsm_programs_t fsm_programs; int32_t ret; - ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_PROGRAMS, + (uint8_t *)&fsm_programs, 1); *val = fsm_programs.fsm_n_prog; return ret; @@ -6329,14 +6744,15 @@ int32_t lsm6dsv16x_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsv16x_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; buff[1] = (uint8_t)(val / 256U); buff[0] = (uint8_t)(val - (buff[1] * 256U)); - ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_START_ADD_L, (uint8_t *)&buff[0], 2); + ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_START_ADD_L, + (uint8_t *)&buff[0], 2); return ret; } @@ -6349,13 +6765,16 @@ int32_t lsm6dsv16x_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsv16x_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_START_ADD_L, &buff[0], 2); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -6384,7 +6803,7 @@ int32_t lsm6dsv16x_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ff_time_windows_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_wake_up_dur_t wake_up_dur; lsm6dsv16x_free_fall_t free_fall; @@ -6393,7 +6812,10 @@ int32_t lsm6dsv16x_ff_time_windows_set(stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5; ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FREE_FALL, (uint8_t *)&free_fall, 1); free_fall.ff_dur = (uint8_t)val & 0x1FU; @@ -6410,7 +6832,7 @@ int32_t lsm6dsv16x_ff_time_windows_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ff_time_windows_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_wake_up_dur_t wake_up_dur; lsm6dsv16x_free_fall_t free_fall; @@ -6432,7 +6854,7 @@ int32_t lsm6dsv16x_ff_time_windows_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ff_thresholds_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ff_thresholds_set(const stmdev_ctx_t *ctx, lsm6dsv16x_ff_thresholds_t val) { lsm6dsv16x_free_fall_t free_fall; @@ -6456,14 +6878,17 @@ int32_t lsm6dsv16x_ff_thresholds_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ff_thresholds_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ff_thresholds_get(const stmdev_ctx_t *ctx, lsm6dsv16x_ff_thresholds_t *val) { lsm6dsv16x_free_fall_t free_fall; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FREE_FALL, (uint8_t *)&free_fall, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (free_fall.ff_ths) { @@ -6521,14 +6946,16 @@ int32_t lsm6dsv16x_ff_thresholds_get(stmdev_ctx_t *ctx, */ /** - * @brief It enables Machine Learning Core feature (MLC). When the Machine Learning Core is enabled the Finite State Machine (FSM) programs are executed before executing the MLC algorithms.[set] + * @brief It enables Machine Learning Core feature (MLC). + * When the Machine Learning Core is enabled the Finite State Machine (FSM) + * programs are executed before executing the MLC algorithms.[set] * * @param ctx read / write interface definitions * @param val MLC_OFF, MLC_ON, MLC_BEFORE_FSM, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_mlc_set(stmdev_ctx_t *ctx, lsm6dsv16x_mlc_mode_t val) +int32_t lsm6dsv16x_mlc_set(const stmdev_ctx_t *ctx, lsm6dsv16x_mlc_mode_t val) { lsm6dsv16x_emb_func_en_b_t emb_en_b; lsm6dsv16x_emb_func_en_a_t emb_en_a; @@ -6537,9 +6964,12 @@ int32_t lsm6dsv16x_mlc_set(stmdev_ctx_t *ctx, lsm6dsv16x_mlc_mode_t val) ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } - switch(val) + switch (val) { case LSM6DSV16X_MLC_OFF: emb_en_a.mlc_before_fsm_en = 0; @@ -6567,14 +6997,16 @@ exit: } /** - * @brief It enables Machine Learning Core feature (MLC). When the Machine Learning Core is enabled the Finite State Machine (FSM) programs are executed before executing the MLC algorithms.[get] + * @brief It enables Machine Learning Core feature (MLC). + * When the Machine Learning Core is enabled the Finite State Machine (FSM) + * programs are executed before executing the MLC algorithms.[get] * * @param ctx read / write interface definitions * @param val MLC_OFF, MLC_ON, MLC_BEFORE_FSM, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_mlc_get(stmdev_ctx_t *ctx, lsm6dsv16x_mlc_mode_t *val) +int32_t lsm6dsv16x_mlc_get(const stmdev_ctx_t *ctx, lsm6dsv16x_mlc_mode_t *val) { lsm6dsv16x_emb_func_en_b_t emb_en_b; lsm6dsv16x_emb_func_en_a_t emb_en_a; @@ -6583,7 +7015,10 @@ int32_t lsm6dsv16x_mlc_get(stmdev_ctx_t *ctx, lsm6dsv16x_mlc_mode_t *val) ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U) { @@ -6599,7 +7034,7 @@ int32_t lsm6dsv16x_mlc_get(stmdev_ctx_t *ctx, lsm6dsv16x_mlc_mode_t *val) } else { - /* Do nothing */ + /* Do nothing */ } exit: @@ -6616,7 +7051,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_mlc_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_mlc_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv16x_mlc_data_rate_t val) { lsm6dsv16x_mlc_odr_t mlc_odr; @@ -6624,7 +7059,10 @@ int32_t lsm6dsv16x_mlc_data_rate_set(stmdev_ctx_t *ctx, ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MLC_ODR, (uint8_t *)&mlc_odr, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } mlc_odr.mlc_odr = (uint8_t)val & 0x07U; ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MLC_ODR, (uint8_t *)&mlc_odr, 1); @@ -6643,7 +7081,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_mlc_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_mlc_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv16x_mlc_data_rate_t *val) { lsm6dsv16x_mlc_odr_t mlc_odr; @@ -6652,7 +7090,10 @@ int32_t lsm6dsv16x_mlc_data_rate_get(stmdev_ctx_t *ctx, ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MLC_ODR, (uint8_t *)&mlc_odr, 1); ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (mlc_odr.mlc_odr) { @@ -6700,7 +7141,7 @@ int32_t lsm6dsv16x_mlc_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_mlc_out_get(stmdev_ctx_t *ctx, lsm6dsv16x_mlc_out_t *val) +int32_t lsm6dsv16x_mlc_out_get(const stmdev_ctx_t *ctx, lsm6dsv16x_mlc_out_t *val) { int32_t ret; @@ -6722,7 +7163,7 @@ int32_t lsm6dsv16x_mlc_out_get(stmdev_ctx_t *ctx, lsm6dsv16x_mlc_out_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_mlc_ext_sens_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsv16x_mlc_ext_sens_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -6730,7 +7171,8 @@ int32_t lsm6dsv16x_mlc_ext_sens_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) buff[1] = (uint8_t)(val / 256U); buff[0] = (uint8_t)(val - (buff[1] * 256U)); - ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_MLC_EXT_SENSITIVITY_L, (uint8_t *)&buff[0], 2); + ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_MLC_EXT_SENSITIVITY_L, + (uint8_t *)&buff[0], 2); return ret; } @@ -6743,14 +7185,18 @@ int32_t lsm6dsv16x_mlc_ext_sens_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_mlc_ext_sens_sensitivity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_mlc_ext_sens_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; - ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_MLC_EXT_SENSITIVITY_L, &buff[0], 2); - if (ret != 0) { return ret; } + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_MLC_EXT_SENSITIVITY_L, + &buff[0], 2); + if (ret != 0) + { + return ret; + } *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -6779,7 +7225,7 @@ int32_t lsm6dsv16x_mlc_ext_sens_sensitivity_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ois_ctrl_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_ctrl_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_ctrl_mode_t val) { lsm6dsv16x_func_cfg_access_t func_cfg_access; @@ -6803,14 +7249,17 @@ int32_t lsm6dsv16x_ois_ctrl_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ois_ctrl_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_ctrl_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_ctrl_mode_t *val) { lsm6dsv16x_func_cfg_access_t func_cfg_access; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (func_cfg_access.ois_ctrl_from_ui) { @@ -6838,7 +7287,7 @@ int32_t lsm6dsv16x_ois_ctrl_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ois_reset_set(stmdev_ctx_t *ctx, int8_t val) +int32_t lsm6dsv16x_ois_reset_set(const stmdev_ctx_t *ctx, int8_t val) { lsm6dsv16x_func_cfg_access_t func_cfg_access; int32_t ret; @@ -6861,7 +7310,7 @@ int32_t lsm6dsv16x_ois_reset_set(stmdev_ctx_t *ctx, int8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ois_reset_get(stmdev_ctx_t *ctx, int8_t *val) +int32_t lsm6dsv16x_ois_reset_get(const stmdev_ctx_t *ctx, int8_t *val) { lsm6dsv16x_func_cfg_access_t func_cfg_access; int32_t ret; @@ -6880,7 +7329,7 @@ int32_t lsm6dsv16x_ois_reset_get(stmdev_ctx_t *ctx, int8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ois_interface_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_ois_interface_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_pin_ctrl_t pin_ctrl; int32_t ret; @@ -6903,7 +7352,7 @@ int32_t lsm6dsv16x_ois_interface_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ois_interface_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_ois_interface_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_pin_ctrl_t pin_ctrl; int32_t ret; @@ -6922,7 +7371,7 @@ int32_t lsm6dsv16x_ois_interface_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ois_handshake_from_ui_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_handshake_from_ui_set(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_handshake_t val) { lsm6dsv16x_ui_handshake_ctrl_t ui_handshake_ctrl; @@ -6947,14 +7396,17 @@ int32_t lsm6dsv16x_ois_handshake_from_ui_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ois_handshake_from_ui_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_handshake_from_ui_get(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_handshake_t *val) { lsm6dsv16x_ui_handshake_ctrl_t ui_handshake_ctrl; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_HANDSHAKE_CTRL, (uint8_t *)&ui_handshake_ctrl, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->ack = ui_handshake_ctrl.ui_shared_ack; val->req = ui_handshake_ctrl.ui_shared_req; @@ -6970,7 +7422,7 @@ int32_t lsm6dsv16x_ois_handshake_from_ui_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ois_handshake_from_ois_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_handshake_from_ois_set(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_handshake_t val) { lsm6dsv16x_spi2_handshake_ctrl_t spi2_handshake_ctrl; @@ -6995,14 +7447,17 @@ int32_t lsm6dsv16x_ois_handshake_from_ois_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ois_handshake_from_ois_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_handshake_from_ois_get(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_handshake_t *val) { lsm6dsv16x_spi2_handshake_ctrl_t spi2_handshake_ctrl; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_HANDSHAKE_CTRL, (uint8_t *)&spi2_handshake_ctrl, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->ack = spi2_handshake_ctrl.spi2_shared_ack; val->req = spi2_handshake_ctrl.spi2_shared_req; @@ -7018,7 +7473,7 @@ int32_t lsm6dsv16x_ois_handshake_from_ois_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ois_shared_set(stmdev_ctx_t *ctx, uint8_t val[6]) +int32_t lsm6dsv16x_ois_shared_set(const stmdev_ctx_t *ctx, uint8_t val[6]) { int32_t ret; @@ -7035,7 +7490,7 @@ int32_t lsm6dsv16x_ois_shared_set(stmdev_ctx_t *ctx, uint8_t val[6]) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ois_shared_get(stmdev_ctx_t *ctx, uint8_t val[6]) +int32_t lsm6dsv16x_ois_shared_get(const stmdev_ctx_t *ctx, uint8_t val[6]) { int32_t ret; @@ -7052,7 +7507,7 @@ int32_t lsm6dsv16x_ois_shared_get(stmdev_ctx_t *ctx, uint8_t val[6]) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ois_on_spi2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_ois_on_spi2_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_ui_ctrl1_ois_t ui_ctrl1_ois; int32_t ret; @@ -7075,7 +7530,7 @@ int32_t lsm6dsv16x_ois_on_spi2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ois_on_spi2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_ois_on_spi2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_ui_ctrl1_ois_t ui_ctrl1_ois; int32_t ret; @@ -7094,7 +7549,7 @@ int32_t lsm6dsv16x_ois_on_spi2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ois_chain_set(stmdev_ctx_t *ctx, lsm6dsv16x_ois_chain_t val) +int32_t lsm6dsv16x_ois_chain_set(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_chain_t val) { lsm6dsv16x_ui_ctrl1_ois_t ui_ctrl1_ois; int32_t ret; @@ -7118,13 +7573,16 @@ int32_t lsm6dsv16x_ois_chain_set(stmdev_ctx_t *ctx, lsm6dsv16x_ois_chain_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ois_chain_get(stmdev_ctx_t *ctx, lsm6dsv16x_ois_chain_t *val) +int32_t lsm6dsv16x_ois_chain_get(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_chain_t *val) { lsm6dsv16x_ui_ctrl1_ois_t ui_ctrl1_ois; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->gy = ui_ctrl1_ois.ois_g_en; val->xl = ui_ctrl1_ois.ois_xl_en; @@ -7140,7 +7598,7 @@ int32_t lsm6dsv16x_ois_chain_get(stmdev_ctx_t *ctx, lsm6dsv16x_ois_chain_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ois_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_gy_full_scale_t val) { lsm6dsv16x_ui_ctrl2_ois_t ui_ctrl2_ois; @@ -7164,14 +7622,17 @@ int32_t lsm6dsv16x_ois_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ois_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_gy_full_scale_t *val) { lsm6dsv16x_ui_ctrl2_ois_t ui_ctrl2_ois; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ui_ctrl2_ois.fs_g_ois) { @@ -7207,11 +7668,11 @@ int32_t lsm6dsv16x_ois_gy_full_scale_get(stmdev_ctx_t *ctx, * @brief Selects accelerometer OIS channel full-scale.[set] * * @param ctx read / write interface definitions - * @param val OIS_2g, OIS_4g, OIS_8g, OIS_16g, + * @param val lsm6dsv16x_ois_xl_full_scale_t * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ois_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_xl_full_scale_t val) { lsm6dsv16x_ui_ctrl3_ois_t ui_ctrl3_ois; @@ -7231,18 +7692,21 @@ int32_t lsm6dsv16x_ois_xl_full_scale_set(stmdev_ctx_t *ctx, * @brief Selects accelerometer OIS channel full-scale.[get] * * @param ctx read / write interface definitions - * @param val OIS_2g, OIS_4g, OIS_8g, OIS_16g, + * @param val lsm6dsv16x_ois_xl_full_scale_t * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ois_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_xl_full_scale_t *val) { lsm6dsv16x_ui_ctrl3_ois_t ui_ctrl3_ois; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ui_ctrl3_ois.fs_xl_ois) { @@ -7291,7 +7755,7 @@ int32_t lsm6dsv16x_ois_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_6d_threshold_set(const stmdev_ctx_t *ctx, lsm6dsv16x_6d_threshold_t val) { lsm6dsv16x_tap_ths_6d_t tap_ths_6d; @@ -7315,14 +7779,17 @@ int32_t lsm6dsv16x_6d_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_6d_threshold_get(const stmdev_ctx_t *ctx, lsm6dsv16x_6d_threshold_t *val) { lsm6dsv16x_tap_ths_6d_t tap_ths_6d; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (tap_ths_6d.sixd_ths) { @@ -7358,7 +7825,7 @@ int32_t lsm6dsv16x_6d_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -7381,7 +7848,7 @@ int32_t lsm6dsv16x_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -7413,7 +7880,7 @@ int32_t lsm6dsv16x_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ah_qvar_zin_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ah_qvar_zin_set(const stmdev_ctx_t *ctx, lsm6dsv16x_ah_qvar_zin_t val) { lsm6dsv16x_ctrl7_t ctrl7; @@ -7437,14 +7904,17 @@ int32_t lsm6dsv16x_ah_qvar_zin_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ah_qvar_zin_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ah_qvar_zin_get(const stmdev_ctx_t *ctx, lsm6dsv16x_ah_qvar_zin_t *val) { lsm6dsv16x_ctrl7_t ctrl7; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl7.ah_qvar_c_zin) { @@ -7480,7 +7950,7 @@ int32_t lsm6dsv16x_ah_qvar_zin_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ah_qvar_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ah_qvar_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_ah_qvar_mode_t val) { lsm6dsv16x_ctrl7_t ctrl7; @@ -7504,7 +7974,7 @@ int32_t lsm6dsv16x_ah_qvar_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ah_qvar_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ah_qvar_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_ah_qvar_mode_t *val) { lsm6dsv16x_ctrl7_t ctrl7; @@ -7537,7 +8007,7 @@ int32_t lsm6dsv16x_ah_qvar_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_i3c_reset_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_i3c_reset_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_i3c_reset_mode_t val) { lsm6dsv16x_pin_ctrl_t pin_ctrl; @@ -7561,14 +8031,17 @@ int32_t lsm6dsv16x_i3c_reset_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_i3c_reset_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_i3c_reset_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_i3c_reset_mode_t *val) { lsm6dsv16x_pin_ctrl_t pin_ctrl; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (pin_ctrl.ibhr_por_en) { @@ -7588,6 +8061,48 @@ int32_t lsm6dsv16x_i3c_reset_mode_get(stmdev_ctx_t *ctx, return ret; } +/** + * @brief Enable/Disable INT pin when I3C is used.[set] + * + * @param ctx read / write interface definitions + * @param val 0: disabled, 1: enabled + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_i3c_int_en_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv16x_ctrl5_t ctrl5; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret == 0) + { + ctrl5.int_en_i3c = (uint8_t)val & 0x01U; + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL5, (uint8_t *)&ctrl5, 1); + } + + return ret; +} + +/** + * @brief Enable/Disable INT pin when I3C is used.[get] + * + * @param ctx read / write interface definitions + * @param val 0: disabled, 1: enabled + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv16x_i3c_int_en_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv16x_ctrl5_t ctrl5; + int32_t ret; + + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL5, (uint8_t *)&ctrl5, 1); + *val = ctrl5.int_en_i3c; + + return ret; +} + /** * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[set] * @@ -7596,7 +8111,7 @@ int32_t lsm6dsv16x_i3c_reset_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_i3c_ibi_time_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_i3c_ibi_time_set(const stmdev_ctx_t *ctx, lsm6dsv16x_i3c_ibi_time_t val) { lsm6dsv16x_ctrl5_t ctrl5; @@ -7620,14 +8135,17 @@ int32_t lsm6dsv16x_i3c_ibi_time_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_i3c_ibi_time_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_i3c_ibi_time_get(const stmdev_ctx_t *ctx, lsm6dsv16x_i3c_ibi_time_t *val) { lsm6dsv16x_ctrl5_t ctrl5; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL5, (uint8_t *)&ctrl5, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl5.bus_act_sel) { @@ -7676,7 +8194,7 @@ int32_t lsm6dsv16x_i3c_ibi_time_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_sh_master_interface_pull_up_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sh_master_interface_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_if_cfg_t if_cfg; @@ -7700,7 +8218,7 @@ int32_t lsm6dsv16x_sh_master_interface_pull_up_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_sh_master_interface_pull_up_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sh_master_interface_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_if_cfg_t if_cfg; @@ -7720,7 +8238,7 @@ int32_t lsm6dsv16x_sh_master_interface_pull_up_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val, +int32_t lsm6dsv16x_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, uint8_t len) { int32_t ret; @@ -7740,7 +8258,7 @@ int32_t lsm6dsv16x_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_sh_slave_connected_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sh_slave_connected_set(const stmdev_ctx_t *ctx, lsm6dsv16x_sh_slave_connected_t val) { lsm6dsv16x_master_config_t master_config; @@ -7748,7 +8266,10 @@ int32_t lsm6dsv16x_sh_slave_connected_set(stmdev_ctx_t *ctx, ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } master_config.aux_sens_on = (uint8_t)val & 0x3U; ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); @@ -7767,7 +8288,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_sh_slave_connected_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sh_slave_connected_get(const stmdev_ctx_t *ctx, lsm6dsv16x_sh_slave_connected_t *val) { lsm6dsv16x_master_config_t master_config; @@ -7776,7 +8297,10 @@ int32_t lsm6dsv16x_sh_slave_connected_get(stmdev_ctx_t *ctx, ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (master_config.aux_sens_on) { @@ -7812,14 +8336,17 @@ int32_t lsm6dsv16x_sh_slave_connected_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_master_config_t master_config; int32_t ret; ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } master_config.master_on = val; ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); @@ -7838,7 +8365,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_master_config_t master_config; int32_t ret; @@ -7861,14 +8388,17 @@ int32_t lsm6dsv16x_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_master_config_t master_config; int32_t ret; ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } master_config.pass_through_mode = val; ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); @@ -7887,7 +8417,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_master_config_t master_config; int32_t ret; @@ -7910,7 +8440,7 @@ int32_t lsm6dsv16x_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sh_syncro_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_sh_syncro_mode_t val) { lsm6dsv16x_master_config_t master_config; @@ -7918,7 +8448,10 @@ int32_t lsm6dsv16x_sh_syncro_mode_set(stmdev_ctx_t *ctx, ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } master_config.start_config = (uint8_t)val & 0x01U; ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); @@ -7937,7 +8470,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sh_syncro_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_sh_syncro_mode_t *val) { lsm6dsv16x_master_config_t master_config; @@ -7946,7 +8479,10 @@ int32_t lsm6dsv16x_sh_syncro_mode_get(stmdev_ctx_t *ctx, ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (master_config.start_config) { @@ -7974,7 +8510,7 @@ int32_t lsm6dsv16x_sh_syncro_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sh_write_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_sh_write_mode_t val) { lsm6dsv16x_master_config_t master_config; @@ -7982,7 +8518,10 @@ int32_t lsm6dsv16x_sh_write_mode_set(stmdev_ctx_t *ctx, ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } master_config.write_once = (uint8_t)val & 0x01U; ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); @@ -8001,7 +8540,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sh_write_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_sh_write_mode_t *val) { lsm6dsv16x_master_config_t master_config; @@ -8010,7 +8549,10 @@ int32_t lsm6dsv16x_sh_write_mode_get(stmdev_ctx_t *ctx, ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (master_config.write_once) { @@ -8038,14 +8580,17 @@ int32_t lsm6dsv16x_sh_write_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_sh_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_sh_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_master_config_t master_config; int32_t ret; ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } master_config.rst_master_regs = val; ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1); @@ -8064,7 +8609,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_master_config_t master_config; int32_t ret; @@ -8090,23 +8635,32 @@ int32_t lsm6dsv16x_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sh_cfg_write(const stmdev_ctx_t *ctx, lsm6dsv16x_sh_cfg_write_t *val) { lsm6dsv16x_slv0_add_t reg; int32_t ret; ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } reg.slave0_add = val->slv0_add; reg.rw_0 = 0; ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_ADD, (uint8_t *)®, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_SUBADD, &(val->slv0_subadd), 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_DATAWRITE_SLV0, &(val->slv0_data), 1); @@ -8125,7 +8679,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_sh_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sh_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv16x_sh_data_rate_t val) { lsm6dsv16x_slv0_config_t slv0_config; @@ -8133,7 +8687,10 @@ int32_t lsm6dsv16x_sh_data_rate_set(stmdev_ctx_t *ctx, ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } slv0_config.shub_odr = (uint8_t)val & 0x07U; ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); @@ -8152,7 +8709,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_sh_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sh_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv16x_sh_data_rate_t *val) { lsm6dsv16x_slv0_config_t slv0_config; @@ -8161,7 +8718,10 @@ int32_t lsm6dsv16x_sh_data_rate_get(stmdev_ctx_t *ctx, ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (slv0_config.shub_odr) { @@ -8208,7 +8768,7 @@ int32_t lsm6dsv16x_sh_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_sh_slv_cfg_read(stmdev_ctx_t *ctx, uint8_t idx, +int32_t lsm6dsv16x_sh_slv_cfg_read(const stmdev_ctx_t *ctx, uint8_t idx, lsm6dsv16x_sh_cfg_read_t *val) { lsm6dsv16x_slv0_add_t slv_add; @@ -8216,24 +8776,36 @@ int32_t lsm6dsv16x_sh_slv_cfg_read(stmdev_ctx_t *ctx, uint8_t idx, int32_t ret; ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } slv_add.slave0_add = val->slv_add; slv_add.rw_0 = 1; - ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_ADD + idx*3U, + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_ADD + idx * 3U, (uint8_t *)&slv_add, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } - ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_SUBADD + idx*3U, + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_SUBADD + idx * 3U, &(val->slv_subadd), 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } - ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV0_CONFIG + idx*3U, + ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } slv_config.slave0_numop = val->slv_len; - ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_CONFIG + idx*3U, + ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1); exit: @@ -8250,7 +8822,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_sh_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sh_status_get(const stmdev_ctx_t *ctx, lsm6dsv16x_status_master_t *val) { int32_t ret; @@ -8281,7 +8853,7 @@ int32_t lsm6dsv16x_sh_status_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_pin_ctrl_t pin_ctrl; int32_t ret; @@ -8304,7 +8876,7 @@ int32_t lsm6dsv16x_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_pin_ctrl_t pin_ctrl; int32_t ret; @@ -8323,7 +8895,7 @@ int32_t lsm6dsv16x_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ui_i2c_i3c_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ui_i2c_i3c_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_ui_i2c_i3c_mode_t val) { lsm6dsv16x_if_cfg_t if_cfg; @@ -8347,14 +8919,17 @@ int32_t lsm6dsv16x_ui_i2c_i3c_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ui_i2c_i3c_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_ui_i2c_i3c_mode_t *val) { lsm6dsv16x_if_cfg_t if_cfg; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (if_cfg.i2c_i3c_disable) { @@ -8382,7 +8957,7 @@ int32_t lsm6dsv16x_ui_i2c_i3c_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_spi_mode_t val) +int32_t lsm6dsv16x_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_spi_mode_t val) { lsm6dsv16x_if_cfg_t if_cfg; int32_t ret; @@ -8405,13 +8980,16 @@ int32_t lsm6dsv16x_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_spi_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_spi_mode_t *val) +int32_t lsm6dsv16x_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_spi_mode_t *val) { lsm6dsv16x_if_cfg_t if_cfg; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (if_cfg.sim) { @@ -8439,7 +9017,7 @@ int32_t lsm6dsv16x_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_spi_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ui_sda_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_ui_sda_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_if_cfg_t if_cfg; int32_t ret; @@ -8462,7 +9040,7 @@ int32_t lsm6dsv16x_ui_sda_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_ui_sda_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_if_cfg_t if_cfg; int32_t ret; @@ -8481,7 +9059,7 @@ int32_t lsm6dsv16x_ui_sda_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_spi2_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_spi2_mode_t val) +int32_t lsm6dsv16x_spi2_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_spi2_mode_t val) { lsm6dsv16x_ui_ctrl1_ois_t ui_ctrl1_ois; int32_t ret; @@ -8504,13 +9082,16 @@ int32_t lsm6dsv16x_spi2_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_spi2_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_spi2_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_spi2_mode_t *val) +int32_t lsm6dsv16x_spi2_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_spi2_mode_t *val) { lsm6dsv16x_ui_ctrl1_ois_t ui_ctrl1_ois; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ui_ctrl1_ois.sim_ois) { @@ -8552,13 +9133,16 @@ int32_t lsm6dsv16x_spi2_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_spi2_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_emb_func_en_a_t emb_func_en_a; int32_t ret; ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); emb_func_en_a.sign_motion_en = val; @@ -8577,13 +9161,16 @@ int32_t lsm6dsv16x_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_emb_func_en_a_t emb_func_en_a; int32_t ret; ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); *val = emb_func_en_a.sign_motion_en; @@ -8613,7 +9200,7 @@ int32_t lsm6dsv16x_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_stpcnt_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_stpcnt_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_stpcnt_mode_t val) { lsm6dsv16x_emb_func_en_a_t emb_func_en_a; @@ -8622,11 +9209,17 @@ int32_t lsm6dsv16x_stpcnt_mode_set(stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } if ((val.false_step_rej == PROPERTY_ENABLE) && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) == @@ -8643,9 +9236,11 @@ exit: if (ret == 0) { - ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_CMD_REG, + (uint8_t *)&pedo_cmd_reg, 1); pedo_cmd_reg.fp_rejection_en = val.false_step_rej; - ret += lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + ret += lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_CMD_REG, + (uint8_t *)&pedo_cmd_reg, 1); } return ret; @@ -8659,7 +9254,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_stpcnt_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_stpcnt_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_stpcnt_mode_t *val) { lsm6dsv16x_emb_func_en_a_t emb_func_en_a; @@ -8669,10 +9264,17 @@ int32_t lsm6dsv16x_stpcnt_mode_get(stmdev_ctx_t *ctx, ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } - ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); - if (ret != 0) { return ret; } + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_CMD_REG, + (uint8_t *)&pedo_cmd_reg, 1); + if (ret != 0) + { + return ret; + } val->false_step_rej = pedo_cmd_reg.fp_rejection_en; val->step_counter_enable = emb_func_en_a.pedo_en; @@ -8688,7 +9290,7 @@ int32_t lsm6dsv16x_stpcnt_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsv16x_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -8696,7 +9298,10 @@ int32_t lsm6dsv16x_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val) ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_STEP_COUNTER_L, &buff[0], 2); ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -8712,16 +9317,22 @@ int32_t lsm6dsv16x_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_stpcnt_rst_step_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_stpcnt_rst_step_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_emb_func_src_t emb_func_src; int32_t ret; ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } emb_func_src.pedo_rst_step = val; ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); @@ -8740,13 +9351,16 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_stpcnt_rst_step_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_emb_func_src_t emb_func_src; int32_t ret; ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); *val = emb_func_src.pedo_rst_step; @@ -8764,16 +9378,18 @@ int32_t lsm6dsv16x_stpcnt_rst_step_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_pedo_deb_steps_conf_t pedo_deb_steps_conf; int32_t ret; - ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_DEB_STEPS_CONF, + (uint8_t *)&pedo_deb_steps_conf, 1); if (ret == 0) { pedo_deb_steps_conf.deb_step = val; - ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_DEB_STEPS_CONF, + (uint8_t *)&pedo_deb_steps_conf, 1); } return ret; @@ -8787,12 +9403,13 @@ int32_t lsm6dsv16x_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_pedo_deb_steps_conf_t pedo_deb_steps_conf; int32_t ret; - ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_DEB_STEPS_CONF, + (uint8_t *)&pedo_deb_steps_conf, 1); *val = pedo_deb_steps_conf.deb_step; return ret; @@ -8806,14 +9423,15 @@ int32_t lsm6dsv16x_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsv16x_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; buff[1] = (uint8_t)(val / 256U); buff[0] = (uint8_t)(val - (buff[1] * 256U)); - ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_SC_DELTAT_L, (uint8_t *)&buff[0], 2); + ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_SC_DELTAT_L, + (uint8_t *)&buff[0], 2); return ret; } @@ -8826,13 +9444,17 @@ int32_t lsm6dsv16x_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsv16x_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; - ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_SC_DELTAT_L, &buff[0], 2); - if (ret != 0) { return ret; } + ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_SC_DELTAT_L, &buff[0], + 2); + if (ret != 0) + { + return ret; + } *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -8860,16 +9482,22 @@ int32_t lsm6dsv16x_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_sflp_game_rotation_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_emb_func_en_a_t emb_func_en_a; int32_t ret; ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } emb_func_en_a.sflp_game_en = val; ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, @@ -8889,13 +9517,16 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_sflp_game_rotation_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_emb_func_en_a_t emb_func_en_a; int32_t ret; ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); *val = emb_func_en_a.sflp_game_en; @@ -8913,17 +9544,23 @@ int32_t lsm6dsv16x_sflp_game_rotation_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_sflp_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sflp_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv16x_sflp_data_rate_t val) { lsm6dsv16x_sflp_odr_t sflp_odr; int32_t ret; ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SFLP_ODR, (uint8_t *)&sflp_odr, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } sflp_odr.sflp_game_odr = (uint8_t)val & 0x07U; ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SFLP_ODR, (uint8_t *)&sflp_odr, 1); @@ -8942,7 +9579,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_sflp_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sflp_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv16x_sflp_data_rate_t *val) { lsm6dsv16x_sflp_odr_t sflp_odr; @@ -8951,7 +9588,10 @@ int32_t lsm6dsv16x_sflp_data_rate_get(stmdev_ctx_t *ctx, ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SFLP_ODR, (uint8_t *)&sflp_odr, 1); ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (sflp_odr.sflp_game_odr) { @@ -9008,7 +9648,7 @@ int32_t lsm6dsv16x_sflp_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_tap_detection_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_tap_detection_set(const stmdev_ctx_t *ctx, lsm6dsv16x_tap_detection_t val) { lsm6dsv16x_tap_cfg0_t tap_cfg0; @@ -9034,14 +9674,17 @@ int32_t lsm6dsv16x_tap_detection_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_tap_detection_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_tap_detection_get(const stmdev_ctx_t *ctx, lsm6dsv16x_tap_detection_t *val) { lsm6dsv16x_tap_cfg0_t tap_cfg0; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->tap_x_en = tap_cfg0.tap_x_en; val->tap_y_en = tap_cfg0.tap_y_en; @@ -9058,7 +9701,7 @@ int32_t lsm6dsv16x_tap_detection_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_tap_thresholds_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_tap_thresholds_set(const stmdev_ctx_t *ctx, lsm6dsv16x_tap_thresholds_t val) { lsm6dsv16x_tap_ths_6d_t tap_ths_6d; @@ -9069,7 +9712,10 @@ int32_t lsm6dsv16x_tap_thresholds_set(stmdev_ctx_t *ctx, ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } tap_cfg1.tap_ths_x = val.x; tap_cfg2.tap_ths_y = val.y; @@ -9090,7 +9736,7 @@ int32_t lsm6dsv16x_tap_thresholds_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_tap_thresholds_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_tap_thresholds_get(const stmdev_ctx_t *ctx, lsm6dsv16x_tap_thresholds_t *val) { lsm6dsv16x_tap_ths_6d_t tap_ths_6d; @@ -9101,7 +9747,10 @@ int32_t lsm6dsv16x_tap_thresholds_get(stmdev_ctx_t *ctx, ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->x = tap_cfg1.tap_ths_x; val->y = tap_cfg2.tap_ths_y; @@ -9118,7 +9767,7 @@ int32_t lsm6dsv16x_tap_thresholds_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_tap_axis_priority_set(const stmdev_ctx_t *ctx, lsm6dsv16x_tap_axis_priority_t val) { lsm6dsv16x_tap_cfg1_t tap_cfg1; @@ -9142,14 +9791,17 @@ int32_t lsm6dsv16x_tap_axis_priority_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_tap_axis_priority_get(const stmdev_ctx_t *ctx, lsm6dsv16x_tap_axis_priority_t *val) { lsm6dsv16x_tap_cfg1_t tap_cfg1; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (tap_cfg1.tap_priority) { @@ -9193,7 +9845,7 @@ int32_t lsm6dsv16x_tap_axis_priority_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_tap_time_windows_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_tap_time_windows_set(const stmdev_ctx_t *ctx, lsm6dsv16x_tap_time_windows_t val) { lsm6dsv16x_tap_dur_t tap_dur; @@ -9219,14 +9871,17 @@ int32_t lsm6dsv16x_tap_time_windows_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_tap_time_windows_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_tap_time_windows_get(const stmdev_ctx_t *ctx, lsm6dsv16x_tap_time_windows_t *val) { lsm6dsv16x_tap_dur_t tap_dur; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_DUR, (uint8_t *)&tap_dur, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->shock = tap_dur.shock; val->quiet = tap_dur.quiet; @@ -9243,7 +9898,7 @@ int32_t lsm6dsv16x_tap_time_windows_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_tap_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_tap_mode_t val) +int32_t lsm6dsv16x_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_tap_mode_t val) { lsm6dsv16x_wake_up_ths_t wake_up_ths; int32_t ret; @@ -9266,13 +9921,16 @@ int32_t lsm6dsv16x_tap_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_tap_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_tap_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_tap_mode_t *val) +int32_t lsm6dsv16x_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_tap_mode_t *val) { lsm6dsv16x_wake_up_ths_t wake_up_ths; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (wake_up_ths.single_double_tap) { @@ -9313,13 +9971,16 @@ int32_t lsm6dsv16x_tap_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_tap_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_emb_func_en_a_t emb_func_en_a; int32_t ret; ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); emb_func_en_a.tilt_en = val; @@ -9338,13 +9999,16 @@ int32_t lsm6dsv16x_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_emb_func_en_a_t emb_func_en_a; int32_t ret; ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); *val = emb_func_en_a.tilt_en; @@ -9375,13 +10039,16 @@ int32_t lsm6dsv16x_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t lsm6dsv16x_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TIMESTAMP0, &buff[0], 4); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } *val = buff[3]; *val = (*val * 256U) + buff[2]; @@ -9399,7 +10066,7 @@ int32_t lsm6dsv16x_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv16x_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv16x_functions_enable_t functions_enable; int32_t ret; @@ -9422,7 +10089,7 @@ int32_t lsm6dsv16x_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv16x_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv16x_functions_enable_t functions_enable; int32_t ret; @@ -9454,7 +10121,7 @@ int32_t lsm6dsv16x_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_act_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_act_mode_t val) +int32_t lsm6dsv16x_act_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_act_mode_t val) { lsm6dsv16x_functions_enable_t functions_enable; int32_t ret; @@ -9477,13 +10144,16 @@ int32_t lsm6dsv16x_act_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_act_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_act_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_act_mode_t *val) +int32_t lsm6dsv16x_act_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_act_mode_t *val) { lsm6dsv16x_functions_enable_t functions_enable; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (functions_enable.inact_en) { @@ -9519,7 +10189,7 @@ int32_t lsm6dsv16x_act_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_act_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_act_from_sleep_to_act_dur_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_act_from_sleep_to_act_dur_set(const stmdev_ctx_t *ctx, lsm6dsv16x_act_from_sleep_to_act_dur_t val) { lsm6dsv16x_inactivity_dur_t inactivity_dur; @@ -9543,14 +10213,17 @@ int32_t lsm6dsv16x_act_from_sleep_to_act_dur_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_act_from_sleep_to_act_dur_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx, lsm6dsv16x_act_from_sleep_to_act_dur_t *val) { lsm6dsv16x_inactivity_dur_t inactivity_dur; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (inactivity_dur.inact_dur) { @@ -9586,7 +10259,7 @@ int32_t lsm6dsv16x_act_from_sleep_to_act_dur_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_act_sleep_xl_odr_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_act_sleep_xl_odr_set(const stmdev_ctx_t *ctx, lsm6dsv16x_act_sleep_xl_odr_t val) { lsm6dsv16x_inactivity_dur_t inactivity_dur; @@ -9610,14 +10283,17 @@ int32_t lsm6dsv16x_act_sleep_xl_odr_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_act_sleep_xl_odr_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx, lsm6dsv16x_act_sleep_xl_odr_t *val) { lsm6dsv16x_inactivity_dur_t inactivity_dur; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (inactivity_dur.xl_inact_odr) { @@ -9653,7 +10329,7 @@ int32_t lsm6dsv16x_act_sleep_xl_odr_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_act_thresholds_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_act_thresholds_set(const stmdev_ctx_t *ctx, lsm6dsv16x_act_thresholds_t *val) { lsm6dsv16x_inactivity_ths_t inactivity_ths; @@ -9666,7 +10342,10 @@ int32_t lsm6dsv16x_act_thresholds_set(stmdev_ctx_t *ctx, ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } inactivity_dur.wu_inact_ths_w = val->inactivity_cfg.wu_inact_ths_w; inactivity_dur.xl_inact_odr = val->inactivity_cfg.xl_inact_odr; @@ -9692,7 +10371,7 @@ int32_t lsm6dsv16x_act_thresholds_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_act_thresholds_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_act_thresholds_get(const stmdev_ctx_t *ctx, lsm6dsv16x_act_thresholds_t *val) { lsm6dsv16x_inactivity_dur_t inactivity_dur; @@ -9705,7 +10384,10 @@ int32_t lsm6dsv16x_act_thresholds_get(stmdev_ctx_t *ctx, ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->inactivity_cfg.wu_inact_ths_w = inactivity_dur.wu_inact_ths_w; val->inactivity_cfg.xl_inact_odr = inactivity_dur.xl_inact_odr; @@ -9726,7 +10408,7 @@ int32_t lsm6dsv16x_act_thresholds_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_act_wkup_time_windows_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_act_wkup_time_windows_set(const stmdev_ctx_t *ctx, lsm6dsv16x_act_wkup_time_windows_t val) { lsm6dsv16x_wake_up_dur_t wake_up_dur; @@ -9751,14 +10433,17 @@ int32_t lsm6dsv16x_act_wkup_time_windows_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv16x_act_wkup_time_windows_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, lsm6dsv16x_act_wkup_time_windows_t *val) { lsm6dsv16x_wake_up_dur_t wake_up_dur; int32_t ret; ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->shock = wake_up_dur.wake_dur; val->quiet = wake_up_dur.sleep_dur; diff --git a/sensor/stmemsc/lsm6dsv16x_STdC/driver/lsm6dsv16x_reg.h b/sensor/stmemsc/lsm6dsv16x_STdC/driver/lsm6dsv16x_reg.h index 8371a427..801ab46d 100644 --- a/sensor/stmemsc/lsm6dsv16x_STdC/driver/lsm6dsv16x_reg.h +++ b/sensor/stmemsc/lsm6dsv16x_STdC/driver/lsm6dsv16x_reg.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2022 STMicroelectronics. + *

© Copyright (c) 2024 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -3603,7 +3603,7 @@ typedef struct */ /** - * @defgroup LSM6DSO_Register_Union + * @defgroup LSM6DSV_Register_Union * @brief This union group all the registers having a bit-field * description. * This union is useful but it's not needed by the driver. @@ -3872,10 +3872,10 @@ typedef union * them with a custom implementation. */ -int32_t lsm6dsv16x_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm6dsv16x_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lsm6dsv16x_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm6dsv16x_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -3898,8 +3898,8 @@ float_t lsm6dsv16x_from_lsb_to_nsec(uint32_t lsb); float_t lsm6dsv16x_from_lsb_to_mv(int16_t lsb); -int32_t lsm6dsv16x_xl_offset_on_out_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_xl_offset_on_out_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_xl_offset_on_out_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -3907,9 +3907,9 @@ typedef struct float_t y_mg; float_t x_mg; } lsm6dsv16x_xl_offset_mg_t; -int32_t lsm6dsv16x_xl_offset_mg_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_xl_offset_mg_set(const stmdev_ctx_t *ctx, lsm6dsv16x_xl_offset_mg_t val); -int32_t lsm6dsv16x_xl_offset_mg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_xl_offset_mg_get(const stmdev_ctx_t *ctx, lsm6dsv16x_xl_offset_mg_t *val); typedef enum @@ -3919,8 +3919,8 @@ typedef enum LSM6DSV16X_RESTORE_CAL_PARAM = 0x2, LSM6DSV16X_RESTORE_CTRL_REGS = 0x4, } lsm6dsv16x_reset_t; -int32_t lsm6dsv16x_reset_set(stmdev_ctx_t *ctx, lsm6dsv16x_reset_t val); -int32_t lsm6dsv16x_reset_get(stmdev_ctx_t *ctx, lsm6dsv16x_reset_t *val); +int32_t lsm6dsv16x_reset_set(const stmdev_ctx_t *ctx, lsm6dsv16x_reset_t val); +int32_t lsm6dsv16x_reset_get(const stmdev_ctx_t *ctx, lsm6dsv16x_reset_t *val); typedef enum { @@ -3928,10 +3928,10 @@ typedef enum LSM6DSV16X_EMBED_FUNC_MEM_BANK = 0x1, LSM6DSV16X_SENSOR_HUB_MEM_BANK = 0x2, } lsm6dsv16x_mem_bank_t; -int32_t lsm6dsv16x_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsv16x_mem_bank_t val); -int32_t lsm6dsv16x_mem_bank_get(stmdev_ctx_t *ctx, lsm6dsv16x_mem_bank_t *val); +int32_t lsm6dsv16x_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dsv16x_mem_bank_t val); +int32_t lsm6dsv16x_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dsv16x_mem_bank_t *val); -int32_t lsm6dsv16x_device_id_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3969,13 +3969,13 @@ typedef enum LSM6DSV16X_ODR_HA02_AT_3200Hz = 0x2B, LSM6DSV16X_ODR_HA02_AT_6400Hz = 0x2C, } lsm6dsv16x_data_rate_t; -int32_t lsm6dsv16x_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv16x_data_rate_t val); -int32_t lsm6dsv16x_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv16x_data_rate_t *val); -int32_t lsm6dsv16x_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_gy_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv16x_data_rate_t val); -int32_t lsm6dsv16x_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv16x_data_rate_t *val); @@ -3989,8 +3989,8 @@ typedef enum LSM6DSV16X_XL_LOW_POWER_8_AVG_MD = 0x6, LSM6DSV16X_XL_NORMAL_MD = 0x7, } lsm6dsv16x_xl_mode_t; -int32_t lsm6dsv16x_xl_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_xl_mode_t val); -int32_t lsm6dsv16x_xl_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_xl_mode_t *val); +int32_t lsm6dsv16x_xl_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_xl_mode_t val); +int32_t lsm6dsv16x_xl_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_xl_mode_t *val); typedef enum { @@ -3999,26 +3999,26 @@ typedef enum LSM6DSV16X_GY_SLEEP_MD = 0x4, LSM6DSV16X_GY_LOW_POWER_MD = 0x5, } lsm6dsv16x_gy_mode_t; -int32_t lsm6dsv16x_gy_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_gy_mode_t val); -int32_t lsm6dsv16x_gy_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_gy_mode_t *val); +int32_t lsm6dsv16x_gy_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_gy_mode_t val); +int32_t lsm6dsv16x_gy_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_gy_mode_t *val); -int32_t lsm6dsv16x_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16x_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16x_odr_trig_cfg_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_odr_trig_cfg_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_odr_trig_cfg_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_odr_trig_cfg_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSV16X_DRDY_LATCHED = 0x0, LSM6DSV16X_DRDY_PULSED = 0x1, } lsm6dsv16x_data_ready_mode_t; -int32_t lsm6dsv16x_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_data_ready_mode_t val); -int32_t lsm6dsv16x_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_data_ready_mode_t *val); typedef struct @@ -4026,9 +4026,9 @@ typedef struct uint8_t enable : 1; /* interrupt enable */ uint8_t lir : 1; /* interrupt pulsed or latched */ } lsm6dsv16x_interrupt_mode_t; -int32_t lsm6dsv16x_interrupt_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_interrupt_enable_set(const stmdev_ctx_t *ctx, lsm6dsv16x_interrupt_mode_t val); -int32_t lsm6dsv16x_interrupt_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_interrupt_enable_get(const stmdev_ctx_t *ctx, lsm6dsv16x_interrupt_mode_t *val); typedef enum @@ -4040,9 +4040,9 @@ typedef enum LSM6DSV16X_2000dps = 0x4, LSM6DSV16X_4000dps = 0xc, } lsm6dsv16x_gy_full_scale_t; -int32_t lsm6dsv16x_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsv16x_gy_full_scale_t val); -int32_t lsm6dsv16x_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsv16x_gy_full_scale_t *val); typedef enum @@ -4052,13 +4052,13 @@ typedef enum LSM6DSV16X_8g = 0x2, LSM6DSV16X_16g = 0x3, } lsm6dsv16x_xl_full_scale_t; -int32_t lsm6dsv16x_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsv16x_xl_full_scale_t val); -int32_t lsm6dsv16x_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsv16x_xl_full_scale_t *val); -int32_t lsm6dsv16x_xl_dual_channel_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_xl_dual_channel_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_xl_dual_channel_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -4066,9 +4066,9 @@ typedef enum LSM6DSV16X_XL_ST_POSITIVE = 0x1, LSM6DSV16X_XL_ST_NEGATIVE = 0x2, } lsm6dsv16x_xl_self_test_t; -int32_t lsm6dsv16x_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dsv16x_xl_self_test_t val); -int32_t lsm6dsv16x_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dsv16x_xl_self_test_t *val); typedef enum @@ -4077,9 +4077,9 @@ typedef enum LSM6DSV16X_OIS_XL_ST_POSITIVE = 0x1, LSM6DSV16X_OIS_XL_ST_NEGATIVE = 0x2, } lsm6dsv16x_ois_xl_self_test_t; -int32_t lsm6dsv16x_ois_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_xl_self_test_t val); -int32_t lsm6dsv16x_ois_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_xl_self_test_t *val); typedef enum @@ -4089,9 +4089,9 @@ typedef enum LSM6DSV16X_GY_ST_NEGATIVE = 0x2, } lsm6dsv16x_gy_self_test_t; -int32_t lsm6dsv16x_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dsv16x_gy_self_test_t val); -int32_t lsm6dsv16x_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dsv16x_gy_self_test_t *val); typedef enum @@ -4103,9 +4103,9 @@ typedef enum LSM6DSV16X_OIS_GY_ST_CLAMP_NEG = 0x6, } lsm6dsv16x_ois_gy_self_test_t; -int32_t lsm6dsv16x_ois_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_gy_self_test_t val); -int32_t lsm6dsv16x_ois_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_gy_self_test_t *val); typedef struct @@ -4170,7 +4170,7 @@ typedef struct uint8_t fifo_ovr : 1; uint8_t fifo_th : 1; } lsm6dsv16x_all_sources_t; -int32_t lsm6dsv16x_all_sources_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_all_sources_get(const stmdev_ctx_t *ctx, lsm6dsv16x_all_sources_t *val); typedef struct @@ -4178,6 +4178,7 @@ typedef struct uint8_t drdy_xl : 1; uint8_t drdy_g : 1; uint8_t drdy_g_eis : 1; + uint8_t drdy_temp : 1; uint8_t fifo_th : 1; uint8_t fifo_ovr : 1; uint8_t fifo_full : 1; @@ -4193,13 +4194,13 @@ typedef struct uint8_t freefall : 1; uint8_t sleep_change : 1; } lsm6dsv16x_pin_int_route_t; -int32_t lsm6dsv16x_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm6dsv16x_pin_int_route_t *val); -int32_t lsm6dsv16x_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm6dsv16x_pin_int_route_t *val); -int32_t lsm6dsv16x_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm6dsv16x_pin_int_route_t *val); -int32_t lsm6dsv16x_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_pin_int2_route_get(const stmdev_ctx_t *ctx, lsm6dsv16x_pin_int_route_t *val); typedef struct @@ -4208,48 +4209,48 @@ typedef struct uint8_t drdy_gy : 1; uint8_t drdy_temp : 1; } lsm6dsv16x_data_ready_t; -int32_t lsm6dsv16x_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_flag_data_ready_get(const stmdev_ctx_t *ctx, lsm6dsv16x_data_ready_t *val); -int32_t lsm6dsv16x_int_ack_mask_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_int_ack_mask_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_int_ack_mask_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_int_ack_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16x_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsv16x_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsv16x_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsv16x_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsv16x_ois_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsv16x_ois_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsv16x_ois_eis_angular_rate_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_eis_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsv16x_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsv16x_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsv16x_dual_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsv16x_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsv16x_ois_dual_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsv16x_ah_qvar_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsv16x_ah_qvar_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsv16x_odr_cal_reg_get(stmdev_ctx_t *ctx, int8_t *val); +int32_t lsm6dsv16x_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val); -int32_t lsm6dsv16x_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dsv16x_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); -int32_t lsm6dsv16x_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, +int32_t lsm6dsv16x_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); -int32_t lsm6dsv16x_emb_function_dbg_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_emb_function_dbg_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_emb_function_dbg_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_emb_function_dbg_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSV16X_DEN_ACT_LOW = 0x0, LSM6DSV16X_DEN_ACT_HIGH = 0x1, } lsm6dsv16x_den_polarity_t; -int32_t lsm6dsv16x_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dsv16x_den_polarity_t val); -int32_t lsm6dsv16x_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dsv16x_den_polarity_t *val); typedef struct @@ -4261,13 +4262,13 @@ typedef struct uint8_t den_z : 1; enum { - DEN_NOT_DEFINED = 0x00, - LEVEL_TRIGGER = 0x02, - LEVEL_LATCHED = 0x03, + LSM6DSV16X_DEN_NOT_DEFINED = 0x00, + LSM6DSV16X_LEVEL_TRIGGER = 0x02, + LSM6DSV16X_LEVEL_LATCHED = 0x03, } mode; } lsm6dsv16x_den_conf_t; -int32_t lsm6dsv16x_den_conf_set(stmdev_ctx_t *ctx, lsm6dsv16x_den_conf_t val); -int32_t lsm6dsv16x_den_conf_get(stmdev_ctx_t *ctx, lsm6dsv16x_den_conf_t *val); +int32_t lsm6dsv16x_den_conf_set(const stmdev_ctx_t *ctx, lsm6dsv16x_den_conf_t val); +int32_t lsm6dsv16x_den_conf_get(const stmdev_ctx_t *ctx, lsm6dsv16x_den_conf_t *val); typedef enum { @@ -4277,13 +4278,13 @@ typedef enum LSM6DSV16X_EIS_1000dps = 0x3, LSM6DSV16X_EIS_2000dps = 0x4, } lsm6dsv16x_eis_gy_full_scale_t; -int32_t lsm6dsv16x_eis_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_eis_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsv16x_eis_gy_full_scale_t val); -int32_t lsm6dsv16x_eis_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_eis_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsv16x_eis_gy_full_scale_t *val); -int32_t lsm6dsv16x_eis_gy_on_spi2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_eis_gy_on_spi2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_eis_gy_on_spi2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_eis_gy_on_spi2_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -4291,16 +4292,16 @@ typedef enum LSM6DSV16X_EIS_1920Hz = 0x1, LSM6DSV16X_EIS_960Hz = 0x2, } lsm6dsv16x_gy_eis_data_rate_t; -int32_t lsm6dsv16x_gy_eis_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_gy_eis_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv16x_gy_eis_data_rate_t val); -int32_t lsm6dsv16x_gy_eis_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_gy_eis_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv16x_gy_eis_data_rate_t *val); -int32_t lsm6dsv16x_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16x_fifo_xl_dual_fsm_batch_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_fifo_xl_dual_fsm_batch_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -4309,23 +4310,23 @@ typedef enum LSM6DSV16X_CMP_16_TO_1 = 0x2, LSM6DSV16X_CMP_32_TO_1 = 0x3, } lsm6dsv16x_fifo_compress_algo_t; -int32_t lsm6dsv16x_fifo_compress_algo_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_compress_algo_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_compress_algo_t val); -int32_t lsm6dsv16x_fifo_compress_algo_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_compress_algo_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_compress_algo_t *val); -int32_t lsm6dsv16x_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16x_fifo_compress_algo_real_time_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_fifo_compress_algo_real_time_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16x_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -4343,9 +4344,9 @@ typedef enum LSM6DSV16X_XL_BATCHED_AT_3840Hz = 0xb, LSM6DSV16X_XL_BATCHED_AT_7680Hz = 0xc, } lsm6dsv16x_fifo_xl_batch_t; -int32_t lsm6dsv16x_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_xl_batch_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_xl_batch_t val); -int32_t lsm6dsv16x_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_xl_batch_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_xl_batch_t *val); typedef enum @@ -4364,9 +4365,9 @@ typedef enum LSM6DSV16X_GY_BATCHED_AT_3840Hz = 0xb, LSM6DSV16X_GY_BATCHED_AT_7680Hz = 0xc, } lsm6dsv16x_fifo_gy_batch_t; -int32_t lsm6dsv16x_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_gy_batch_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_gy_batch_t val); -int32_t lsm6dsv16x_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_gy_batch_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_gy_batch_t *val); typedef enum @@ -4379,12 +4380,12 @@ typedef enum LSM6DSV16X_STREAM_MODE = 0x6, LSM6DSV16X_BYPASS_TO_FIFO_MODE = 0x7, } lsm6dsv16x_fifo_mode_t; -int32_t lsm6dsv16x_fifo_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_fifo_mode_t val); -int32_t lsm6dsv16x_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_mode_t val); +int32_t lsm6dsv16x_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_mode_t *val); -int32_t lsm6dsv16x_fifo_gy_eis_batch_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_fifo_gy_eis_batch_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_fifo_gy_eis_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_fifo_gy_eis_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -4393,9 +4394,9 @@ typedef enum LSM6DSV16X_TEMP_BATCHED_AT_15Hz = 0x2, LSM6DSV16X_TEMP_BATCHED_AT_60Hz = 0x3, } lsm6dsv16x_fifo_temp_batch_t; -int32_t lsm6dsv16x_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_temp_batch_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_temp_batch_t val); -int32_t lsm6dsv16x_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_temp_batch_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_temp_batch_t *val); typedef enum @@ -4405,14 +4406,14 @@ typedef enum LSM6DSV16X_TMSTMP_DEC_8 = 0x2, LSM6DSV16X_TMSTMP_DEC_32 = 0x3, } lsm6dsv16x_fifo_timestamp_batch_t; -int32_t lsm6dsv16x_fifo_timestamp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_timestamp_batch_t val); -int32_t lsm6dsv16x_fifo_timestamp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_timestamp_batch_t *val); -int32_t lsm6dsv16x_fifo_batch_counter_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsv16x_fifo_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum @@ -4421,9 +4422,9 @@ typedef enum LSM6DSV16X_GY_BATCH_EVENT = 0x1, LSM6DSV16X_GY_EIS_BATCH_EVENT = 0x2, } lsm6dsv16x_fifo_batch_cnt_event_t; -int32_t lsm6dsv16x_fifo_batch_cnt_event_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_batch_cnt_event_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_batch_cnt_event_t val); -int32_t lsm6dsv16x_fifo_batch_cnt_event_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_batch_cnt_event_t *val); typedef struct @@ -4435,7 +4436,7 @@ typedef struct uint8_t fifo_th : 1; } lsm6dsv16x_fifo_status_t; -int32_t lsm6dsv16x_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_status_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_status_t *val); typedef struct @@ -4474,20 +4475,20 @@ typedef struct uint8_t cnt; uint8_t data[6]; } lsm6dsv16x_fifo_out_raw_t; -int32_t lsm6dsv16x_fifo_out_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_out_raw_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_out_raw_t *val); -int32_t lsm6dsv16x_fifo_stpcnt_batch_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_fifo_stpcnt_batch_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16x_fifo_mlc_batch_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_fifo_mlc_batch_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_fifo_mlc_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_fifo_mlc_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16x_fifo_mlc_filt_batch_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_fifo_mlc_filt_batch_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_fifo_mlc_filt_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_fifo_mlc_filt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16x_fifo_sh_batch_slave_set(stmdev_ctx_t *ctx, uint8_t idx, uint8_t val); -int32_t lsm6dsv16x_fifo_sh_batch_slave_get(stmdev_ctx_t *ctx, uint8_t idx, uint8_t *val); +int32_t lsm6dsv16x_fifo_sh_batch_slave_set(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t val); +int32_t lsm6dsv16x_fifo_sh_batch_slave_get(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t *val); typedef struct { @@ -4495,9 +4496,9 @@ typedef struct uint8_t gravity : 1; uint8_t gbias : 1; } lsm6dsv16x_fifo_sflp_raw_t; -int32_t lsm6dsv16x_fifo_sflp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_sflp_batch_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_sflp_raw_t val); -int32_t lsm6dsv16x_fifo_sflp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fifo_sflp_batch_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_sflp_raw_t *val); typedef enum @@ -4505,9 +4506,9 @@ typedef enum LSM6DSV16X_AUTO = 0x0, LSM6DSV16X_ALWAYS_ACTIVE = 0x1, } lsm6dsv16x_filt_anti_spike_t; -int32_t lsm6dsv16x_filt_anti_spike_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_anti_spike_set(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_anti_spike_t val); -int32_t lsm6dsv16x_filt_anti_spike_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_anti_spike_get(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_anti_spike_t *val); typedef struct @@ -4517,18 +4518,18 @@ typedef struct uint8_t irq_xl : 1; uint8_t irq_g : 1; } lsm6dsv16x_filt_settling_mask_t; -int32_t lsm6dsv16x_filt_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_settling_mask_set(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_settling_mask_t val); -int32_t lsm6dsv16x_filt_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_settling_mask_get(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_settling_mask_t *val); typedef struct { uint8_t ois_drdy : 1; } lsm6dsv16x_filt_ois_settling_mask_t; -int32_t lsm6dsv16x_filt_ois_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_ois_settling_mask_set(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_ois_settling_mask_t val); -int32_t lsm6dsv16x_filt_ois_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_ois_settling_mask_get(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_ois_settling_mask_t *val); typedef enum @@ -4542,13 +4543,13 @@ typedef enum LSM6DSV16X_GY_AGGRESSIVE = 0x6, LSM6DSV16X_GY_XTREME = 0x7, } lsm6dsv16x_filt_gy_lp1_bandwidth_t; -int32_t lsm6dsv16x_filt_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_gy_lp1_bandwidth_t val); -int32_t lsm6dsv16x_filt_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_gy_lp1_bandwidth_t *val); -int32_t lsm6dsv16x_filt_gy_lp1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_filt_gy_lp1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_filt_gy_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -4561,28 +4562,28 @@ typedef enum LSM6DSV16X_XL_AGGRESSIVE = 0x6, LSM6DSV16X_XL_XTREME = 0x7, } lsm6dsv16x_filt_xl_lp2_bandwidth_t; -int32_t lsm6dsv16x_filt_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_xl_lp2_bandwidth_t val); -int32_t lsm6dsv16x_filt_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_xl_lp2_bandwidth_t *val); -int32_t lsm6dsv16x_filt_xl_lp2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_filt_xl_lp2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_filt_xl_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16x_filt_xl_hp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_filt_xl_hp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_filt_xl_hp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16x_filt_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_filt_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_filt_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSV16X_HP_MD_NORMAL = 0x0, LSM6DSV16X_HP_MD_REFERENCE = 0x1, } lsm6dsv16x_filt_xl_hp_mode_t; -int32_t lsm6dsv16x_filt_xl_hp_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_xl_hp_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_xl_hp_mode_t val); -int32_t lsm6dsv16x_filt_xl_hp_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_xl_hp_mode_t *val); typedef enum @@ -4591,22 +4592,22 @@ typedef enum LSM6DSV16X_WK_FEED_HIGH_PASS = 0x1, LSM6DSV16X_WK_FEED_LP_WITH_OFFSET = 0x2, } lsm6dsv16x_filt_wkup_act_feed_t; -int32_t lsm6dsv16x_filt_wkup_act_feed_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_wkup_act_feed_t val); -int32_t lsm6dsv16x_filt_wkup_act_feed_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_wkup_act_feed_t *val); -int32_t lsm6dsv16x_mask_trigger_xl_settl_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_mask_trigger_xl_settl_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_mask_trigger_xl_settl_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSV16X_SIXD_FEED_ODR_DIV_2 = 0x0, LSM6DSV16X_SIXD_FEED_LOW_PASS = 0x1, } lsm6dsv16x_filt_sixd_feed_t; -int32_t lsm6dsv16x_filt_sixd_feed_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_sixd_feed_set(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_sixd_feed_t val); -int32_t lsm6dsv16x_filt_sixd_feed_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_sixd_feed_get(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_sixd_feed_t *val); typedef enum @@ -4614,9 +4615,9 @@ typedef enum LSM6DSV16X_EIS_LP_NORMAL = 0x0, LSM6DSV16X_EIS_LP_LIGHT = 0x1, } lsm6dsv16x_filt_gy_eis_lp_bandwidth_t; -int32_t lsm6dsv16x_filt_gy_eis_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_gy_eis_lp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_gy_eis_lp_bandwidth_t val); -int32_t lsm6dsv16x_filt_gy_eis_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_gy_eis_lp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_gy_eis_lp_bandwidth_t *val); typedef enum @@ -4626,9 +4627,9 @@ typedef enum LSM6DSV16X_OIS_GY_LP_AGGRESSIVE = 0x2, LSM6DSV16X_OIS_GY_LP_LIGHT = 0x3, } lsm6dsv16x_filt_gy_ois_lp_bandwidth_t; -int32_t lsm6dsv16x_filt_gy_ois_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_gy_ois_lp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_gy_ois_lp_bandwidth_t val); -int32_t lsm6dsv16x_filt_gy_ois_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_gy_ois_lp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_gy_ois_lp_bandwidth_t *val); typedef enum @@ -4642,9 +4643,9 @@ typedef enum LSM6DSV16X_OIS_XL_LP_AGGRESSIVE = 0x6, LSM6DSV16X_OIS_XL_LP_XTREME = 0x7, } lsm6dsv16x_filt_xl_ois_lp_bandwidth_t; -int32_t lsm6dsv16x_filt_xl_ois_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_xl_ois_lp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_xl_ois_lp_bandwidth_t val); -int32_t lsm6dsv16x_filt_xl_ois_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_filt_xl_ois_lp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsv16x_filt_xl_ois_lp_bandwidth_t *val); typedef enum @@ -4652,11 +4653,11 @@ typedef enum LSM6DSV16X_PROTECT_CTRL_REGS = 0x0, LSM6DSV16X_WRITE_CTRL_REG = 0x1, } lsm6dsv16x_fsm_permission_t; -int32_t lsm6dsv16x_fsm_permission_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_permission_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_permission_t val); -int32_t lsm6dsv16x_fsm_permission_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_permission_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_permission_t *val); -int32_t lsm6dsv16x_fsm_permission_status(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_fsm_permission_status(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -4669,11 +4670,11 @@ typedef struct uint8_t fsm7_en : 1; uint8_t fsm8_en : 1; } lsm6dsv16x_fsm_mode_t; -int32_t lsm6dsv16x_fsm_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_fsm_mode_t val); -int32_t lsm6dsv16x_fsm_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_fsm_mode_t *val); +int32_t lsm6dsv16x_fsm_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_mode_t val); +int32_t lsm6dsv16x_fsm_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_mode_t *val); -int32_t lsm6dsv16x_fsm_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsv16x_fsm_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsv16x_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv16x_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef struct @@ -4687,7 +4688,7 @@ typedef struct uint8_t fsm_outs7; uint8_t fsm_outs8; } lsm6dsv16x_fsm_out_t; -int32_t lsm6dsv16x_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsv16x_fsm_out_t *val); +int32_t lsm6dsv16x_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_out_t *val); typedef enum { @@ -4699,14 +4700,14 @@ typedef enum LSM6DSV16X_FSM_480Hz = 0x5, LSM6DSV16X_FSM_960Hz = 0x6, } lsm6dsv16x_fsm_data_rate_t; -int32_t lsm6dsv16x_fsm_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_data_rate_t val); -int32_t lsm6dsv16x_fsm_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_data_rate_t *val); -int32_t lsm6dsv16x_fsm_ext_sens_sensitivity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_ext_sens_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsv16x_fsm_ext_sens_sensitivity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_ext_sens_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef struct @@ -4715,9 +4716,9 @@ typedef struct uint16_t y; uint16_t x; } lsm6dsv16x_xl_fsm_ext_sens_offset_t; -int32_t lsm6dsv16x_fsm_ext_sens_offset_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_ext_sens_offset_set(const stmdev_ctx_t *ctx, lsm6dsv16x_xl_fsm_ext_sens_offset_t val); -int32_t lsm6dsv16x_fsm_ext_sens_offset_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_ext_sens_offset_get(const stmdev_ctx_t *ctx, lsm6dsv16x_xl_fsm_ext_sens_offset_t *val); typedef struct @@ -4729,9 +4730,9 @@ typedef struct uint16_t yz; uint16_t zz; } lsm6dsv16x_xl_fsm_ext_sens_matrix_t; -int32_t lsm6dsv16x_fsm_ext_sens_matrix_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_ext_sens_matrix_set(const stmdev_ctx_t *ctx, lsm6dsv16x_xl_fsm_ext_sens_matrix_t val); -int32_t lsm6dsv16x_fsm_ext_sens_matrix_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_ext_sens_matrix_get(const stmdev_ctx_t *ctx, lsm6dsv16x_xl_fsm_ext_sens_matrix_t *val); typedef enum @@ -4743,9 +4744,9 @@ typedef enum LSM6DSV16X_Z_EQ_MIN_Z = 0x4, LSM6DSV16X_Z_EQ_Z = 0x5, } lsm6dsv16x_fsm_ext_sens_z_orient_t; -int32_t lsm6dsv16x_fsm_ext_sens_z_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_ext_sens_z_orient_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_ext_sens_z_orient_t val); -int32_t lsm6dsv16x_fsm_ext_sens_z_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_ext_sens_z_orient_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_ext_sens_z_orient_t *val); typedef enum @@ -4757,9 +4758,9 @@ typedef enum LSM6DSV16X_Y_EQ_MIN_Z = 0x4, LSM6DSV16X_Y_EQ_Z = 0x5, } lsm6dsv16x_fsm_ext_sens_y_orient_t; -int32_t lsm6dsv16x_fsm_ext_sens_y_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_ext_sens_y_orient_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_ext_sens_y_orient_t val); -int32_t lsm6dsv16x_fsm_ext_sens_y_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_ext_sens_y_orient_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_ext_sens_y_orient_t *val); typedef enum @@ -4771,22 +4772,22 @@ typedef enum LSM6DSV16X_X_EQ_MIN_Z = 0x4, LSM6DSV16X_X_EQ_Z = 0x5, } lsm6dsv16x_fsm_ext_sens_x_orient_t; -int32_t lsm6dsv16x_fsm_ext_sens_x_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_ext_sens_x_orient_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_ext_sens_x_orient_t val); -int32_t lsm6dsv16x_fsm_ext_sens_x_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_fsm_ext_sens_x_orient_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_ext_sens_x_orient_t *val); -int32_t lsm6dsv16x_fsm_long_cnt_timeout_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsv16x_fsm_long_cnt_timeout_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsv16x_fsm_long_cnt_timeout_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv16x_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsv16x_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16x_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsv16x_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsv16x_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv16x_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsv16x_ff_time_windows_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_ff_time_windows_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -4799,9 +4800,9 @@ typedef enum LSM6DSV16X_469_mg = 0x6, LSM6DSV16X_500_mg = 0x7, } lsm6dsv16x_ff_thresholds_t; -int32_t lsm6dsv16x_ff_thresholds_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ff_thresholds_set(const stmdev_ctx_t *ctx, lsm6dsv16x_ff_thresholds_t val); -int32_t lsm6dsv16x_ff_thresholds_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ff_thresholds_get(const stmdev_ctx_t *ctx, lsm6dsv16x_ff_thresholds_t *val); typedef enum @@ -4810,8 +4811,8 @@ typedef enum LSM6DSV16X_MLC_ON = 0x1, LSM6DSV16X_MLC_ON_BEFORE_FSM = 0x2, } lsm6dsv16x_mlc_mode_t; -int32_t lsm6dsv16x_mlc_set(stmdev_ctx_t *ctx, lsm6dsv16x_mlc_mode_t val); -int32_t lsm6dsv16x_mlc_get(stmdev_ctx_t *ctx, lsm6dsv16x_mlc_mode_t *val); +int32_t lsm6dsv16x_mlc_set(const stmdev_ctx_t *ctx, lsm6dsv16x_mlc_mode_t val); +int32_t lsm6dsv16x_mlc_get(const stmdev_ctx_t *ctx, lsm6dsv16x_mlc_mode_t *val); typedef enum { @@ -4823,9 +4824,9 @@ typedef enum LSM6DSV16X_MLC_480Hz = 0x5, LSM6DSV16X_MLC_960Hz = 0x6, } lsm6dsv16x_mlc_data_rate_t; -int32_t lsm6dsv16x_mlc_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_mlc_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv16x_mlc_data_rate_t val); -int32_t lsm6dsv16x_mlc_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_mlc_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv16x_mlc_data_rate_t *val); typedef struct @@ -4835,11 +4836,11 @@ typedef struct uint8_t mlc3_src; uint8_t mlc4_src; } lsm6dsv16x_mlc_out_t; -int32_t lsm6dsv16x_mlc_out_get(stmdev_ctx_t *ctx, lsm6dsv16x_mlc_out_t *val); +int32_t lsm6dsv16x_mlc_out_get(const stmdev_ctx_t *ctx, lsm6dsv16x_mlc_out_t *val); -int32_t lsm6dsv16x_mlc_ext_sens_sensitivity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_mlc_ext_sens_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsv16x_mlc_ext_sens_sensitivity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_mlc_ext_sens_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum @@ -4847,44 +4848,44 @@ typedef enum LSM6DSV16X_OIS_CTRL_FROM_OIS = 0x0, LSM6DSV16X_OIS_CTRL_FROM_UI = 0x1, } lsm6dsv16x_ois_ctrl_mode_t; -int32_t lsm6dsv16x_ois_ctrl_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_ctrl_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_ctrl_mode_t val); -int32_t lsm6dsv16x_ois_ctrl_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_ctrl_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_ctrl_mode_t *val); -int32_t lsm6dsv16x_ois_reset_set(stmdev_ctx_t *ctx, int8_t val); -int32_t lsm6dsv16x_ois_reset_get(stmdev_ctx_t *ctx, int8_t *val); +int32_t lsm6dsv16x_ois_reset_set(const stmdev_ctx_t *ctx, int8_t val); +int32_t lsm6dsv16x_ois_reset_get(const stmdev_ctx_t *ctx, int8_t *val); -int32_t lsm6dsv16x_ois_interface_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_ois_interface_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_ois_interface_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_ois_interface_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { uint8_t ack : 1; uint8_t req : 1; } lsm6dsv16x_ois_handshake_t; -int32_t lsm6dsv16x_ois_handshake_from_ui_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_handshake_from_ui_set(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_handshake_t val); -int32_t lsm6dsv16x_ois_handshake_from_ui_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_handshake_from_ui_get(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_handshake_t *val); -int32_t lsm6dsv16x_ois_handshake_from_ois_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_handshake_from_ois_set(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_handshake_t val); -int32_t lsm6dsv16x_ois_handshake_from_ois_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_handshake_from_ois_get(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_handshake_t *val); -int32_t lsm6dsv16x_ois_shared_set(stmdev_ctx_t *ctx, uint8_t val[6]); -int32_t lsm6dsv16x_ois_shared_get(stmdev_ctx_t *ctx, uint8_t val[6]); +int32_t lsm6dsv16x_ois_shared_set(const stmdev_ctx_t *ctx, uint8_t val[6]); +int32_t lsm6dsv16x_ois_shared_get(const stmdev_ctx_t *ctx, uint8_t val[6]); -int32_t lsm6dsv16x_ois_on_spi2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_ois_on_spi2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_ois_on_spi2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_ois_on_spi2_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { uint8_t gy : 1; uint8_t xl : 1; } lsm6dsv16x_ois_chain_t; -int32_t lsm6dsv16x_ois_chain_set(stmdev_ctx_t *ctx, lsm6dsv16x_ois_chain_t val); -int32_t lsm6dsv16x_ois_chain_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_chain_set(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_chain_t val); +int32_t lsm6dsv16x_ois_chain_get(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_chain_t *val); typedef enum @@ -4895,9 +4896,9 @@ typedef enum LSM6DSV16X_OIS_1000dps = 0x3, LSM6DSV16X_OIS_2000dps = 0x4, } lsm6dsv16x_ois_gy_full_scale_t; -int32_t lsm6dsv16x_ois_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_gy_full_scale_t val); -int32_t lsm6dsv16x_ois_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_gy_full_scale_t *val); typedef enum @@ -4907,9 +4908,9 @@ typedef enum LSM6DSV16X_OIS_8g = 0x2, LSM6DSV16X_OIS_16g = 0x3, } lsm6dsv16x_ois_xl_full_scale_t; -int32_t lsm6dsv16x_ois_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_xl_full_scale_t val); -int32_t lsm6dsv16x_ois_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ois_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_xl_full_scale_t *val); typedef enum @@ -4919,13 +4920,13 @@ typedef enum LSM6DSV16X_DEG_60 = 0x2, LSM6DSV16X_DEG_50 = 0x3, } lsm6dsv16x_6d_threshold_t; -int32_t lsm6dsv16x_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_6d_threshold_set(const stmdev_ctx_t *ctx, lsm6dsv16x_6d_threshold_t val); -int32_t lsm6dsv16x_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_6d_threshold_get(const stmdev_ctx_t *ctx, lsm6dsv16x_6d_threshold_t *val); -int32_t lsm6dsv16x_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -4934,18 +4935,18 @@ typedef enum LSM6DSV16X_300MOhm = 0x2, LSM6DSV16X_255MOhm = 0x3, } lsm6dsv16x_ah_qvar_zin_t; -int32_t lsm6dsv16x_ah_qvar_zin_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ah_qvar_zin_set(const stmdev_ctx_t *ctx, lsm6dsv16x_ah_qvar_zin_t val); -int32_t lsm6dsv16x_ah_qvar_zin_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ah_qvar_zin_get(const stmdev_ctx_t *ctx, lsm6dsv16x_ah_qvar_zin_t *val); typedef struct { uint8_t ah_qvar_en : 1; } lsm6dsv16x_ah_qvar_mode_t; -int32_t lsm6dsv16x_ah_qvar_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ah_qvar_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_ah_qvar_mode_t val); -int32_t lsm6dsv16x_ah_qvar_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ah_qvar_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_ah_qvar_mode_t *val); typedef enum @@ -4953,11 +4954,14 @@ typedef enum LSM6DSV16X_SW_RST_DYN_ADDRESS_RST = 0x0, LSM6DSV16X_I3C_GLOBAL_RST = 0x1, } lsm6dsv16x_i3c_reset_mode_t; -int32_t lsm6dsv16x_i3c_reset_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_i3c_reset_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_i3c_reset_mode_t val); -int32_t lsm6dsv16x_i3c_reset_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_i3c_reset_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_i3c_reset_mode_t *val); +int32_t lsm6dsv16x_i3c_int_en_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_i3c_int_en_get(const stmdev_ctx_t *ctx, uint8_t *val); + typedef enum { LSM6DSV16X_IBI_2us = 0x0, @@ -4965,17 +4969,17 @@ typedef enum LSM6DSV16X_IBI_1ms = 0x2, LSM6DSV16X_IBI_25ms = 0x3, } lsm6dsv16x_i3c_ibi_time_t; -int32_t lsm6dsv16x_i3c_ibi_time_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_i3c_ibi_time_set(const stmdev_ctx_t *ctx, lsm6dsv16x_i3c_ibi_time_t val); -int32_t lsm6dsv16x_i3c_ibi_time_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_i3c_ibi_time_get(const stmdev_ctx_t *ctx, lsm6dsv16x_i3c_ibi_time_t *val); -int32_t lsm6dsv16x_sh_master_interface_pull_up_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sh_master_interface_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_sh_master_interface_pull_up_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sh_master_interface_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16x_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val, +int32_t lsm6dsv16x_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, uint8_t len); typedef enum @@ -4985,25 +4989,25 @@ typedef enum LSM6DSV16X_SLV_0_1_2 = 0x2, LSM6DSV16X_SLV_0_1_2_3 = 0x3, } lsm6dsv16x_sh_slave_connected_t; -int32_t lsm6dsv16x_sh_slave_connected_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sh_slave_connected_set(const stmdev_ctx_t *ctx, lsm6dsv16x_sh_slave_connected_t val); -int32_t lsm6dsv16x_sh_slave_connected_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sh_slave_connected_get(const stmdev_ctx_t *ctx, lsm6dsv16x_sh_slave_connected_t *val); -int32_t lsm6dsv16x_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16x_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSV16X_SH_TRG_XL_GY_DRDY = 0x0, LSM6DSV16X_SH_TRIG_INT2 = 0x1, } lsm6dsv16x_sh_syncro_mode_t; -int32_t lsm6dsv16x_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sh_syncro_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_sh_syncro_mode_t val); -int32_t lsm6dsv16x_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sh_syncro_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_sh_syncro_mode_t *val); typedef enum @@ -5011,13 +5015,13 @@ typedef enum LSM6DSV16X_EACH_SH_CYCLE = 0x0, LSM6DSV16X_ONLY_FIRST_CYCLE = 0x1, } lsm6dsv16x_sh_write_mode_t; -int32_t lsm6dsv16x_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sh_write_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_sh_write_mode_t val); -int32_t lsm6dsv16x_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sh_write_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_sh_write_mode_t *val); -int32_t lsm6dsv16x_sh_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_sh_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -5025,7 +5029,7 @@ typedef struct uint8_t slv0_subadd; uint8_t slv0_data; } lsm6dsv16x_sh_cfg_write_t; -int32_t lsm6dsv16x_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sh_cfg_write(const stmdev_ctx_t *ctx, lsm6dsv16x_sh_cfg_write_t *val); typedef enum { @@ -5036,9 +5040,9 @@ typedef enum LSM6DSV16X_SH_240Hz = 0x5, LSM6DSV16X_SH_480Hz = 0x6, } lsm6dsv16x_sh_data_rate_t; -int32_t lsm6dsv16x_sh_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sh_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv16x_sh_data_rate_t val); -int32_t lsm6dsv16x_sh_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sh_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv16x_sh_data_rate_t *val); typedef struct @@ -5047,23 +5051,23 @@ typedef struct uint8_t slv_subadd; uint8_t slv_len; } lsm6dsv16x_sh_cfg_read_t; -int32_t lsm6dsv16x_sh_slv_cfg_read(stmdev_ctx_t *ctx, uint8_t idx, +int32_t lsm6dsv16x_sh_slv_cfg_read(const stmdev_ctx_t *ctx, uint8_t idx, lsm6dsv16x_sh_cfg_read_t *val); -int32_t lsm6dsv16x_sh_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sh_status_get(const stmdev_ctx_t *ctx, lsm6dsv16x_status_master_t *val); -int32_t lsm6dsv16x_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSV16X_I2C_I3C_ENABLE = 0x0, LSM6DSV16X_I2C_I3C_DISABLE = 0x1, } lsm6dsv16x_ui_i2c_i3c_mode_t; -int32_t lsm6dsv16x_ui_i2c_i3c_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ui_i2c_i3c_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_ui_i2c_i3c_mode_t val); -int32_t lsm6dsv16x_ui_i2c_i3c_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_ui_i2c_i3c_mode_t *val); typedef enum @@ -5071,47 +5075,47 @@ typedef enum LSM6DSV16X_SPI_4_WIRE = 0x0, LSM6DSV16X_SPI_3_WIRE = 0x1, } lsm6dsv16x_spi_mode_t; -int32_t lsm6dsv16x_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_spi_mode_t val); -int32_t lsm6dsv16x_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_spi_mode_t *val); +int32_t lsm6dsv16x_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_spi_mode_t val); +int32_t lsm6dsv16x_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_spi_mode_t *val); -int32_t lsm6dsv16x_ui_sda_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_ui_sda_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_ui_sda_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSV16X_SPI2_4_WIRE = 0x0, LSM6DSV16X_SPI2_3_WIRE = 0x1, } lsm6dsv16x_spi2_mode_t; -int32_t lsm6dsv16x_spi2_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_spi2_mode_t val); -int32_t lsm6dsv16x_spi2_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_spi2_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_spi2_mode_t val); +int32_t lsm6dsv16x_spi2_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_spi2_mode_t *val); -int32_t lsm6dsv16x_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { uint8_t step_counter_enable : 1; uint8_t false_step_rej : 1; } lsm6dsv16x_stpcnt_mode_t; -int32_t lsm6dsv16x_stpcnt_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_stpcnt_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_stpcnt_mode_t val); -int32_t lsm6dsv16x_stpcnt_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_stpcnt_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_stpcnt_mode_t *val); -int32_t lsm6dsv16x_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsv16x_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsv16x_stpcnt_rst_step_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_stpcnt_rst_step_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_stpcnt_rst_step_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16x_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16x_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsv16x_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsv16x_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv16x_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsv16x_sflp_game_rotation_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_sflp_game_rotation_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -5119,7 +5123,7 @@ typedef struct float_t gbias_y; /* dps */ float_t gbias_z; /* dps */ } lsm6dsv16x_sflp_gbias_t; -int32_t lsm6dsv16x_sflp_game_gbias_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sflp_game_gbias_set(const stmdev_ctx_t *ctx, lsm6dsv16x_sflp_gbias_t *val); typedef enum @@ -5131,9 +5135,9 @@ typedef enum LSM6DSV16X_SFLP_240Hz = 0x4, LSM6DSV16X_SFLP_480Hz = 0x5, } lsm6dsv16x_sflp_data_rate_t; -int32_t lsm6dsv16x_sflp_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sflp_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv16x_sflp_data_rate_t val); -int32_t lsm6dsv16x_sflp_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_sflp_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv16x_sflp_data_rate_t *val); typedef struct @@ -5142,9 +5146,9 @@ typedef struct uint8_t tap_y_en : 1; uint8_t tap_z_en : 1; } lsm6dsv16x_tap_detection_t; -int32_t lsm6dsv16x_tap_detection_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_tap_detection_set(const stmdev_ctx_t *ctx, lsm6dsv16x_tap_detection_t val); -int32_t lsm6dsv16x_tap_detection_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_tap_detection_get(const stmdev_ctx_t *ctx, lsm6dsv16x_tap_detection_t *val); typedef struct @@ -5153,9 +5157,9 @@ typedef struct uint8_t y : 5; uint8_t z : 5; } lsm6dsv16x_tap_thresholds_t; -int32_t lsm6dsv16x_tap_thresholds_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_tap_thresholds_set(const stmdev_ctx_t *ctx, lsm6dsv16x_tap_thresholds_t val); -int32_t lsm6dsv16x_tap_thresholds_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_tap_thresholds_get(const stmdev_ctx_t *ctx, lsm6dsv16x_tap_thresholds_t *val); typedef enum @@ -5167,9 +5171,9 @@ typedef enum LSM6DSV16X_YZX = 0x5, LSM6DSV16X_ZXY = 0x6, } lsm6dsv16x_tap_axis_priority_t; -int32_t lsm6dsv16x_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_tap_axis_priority_set(const stmdev_ctx_t *ctx, lsm6dsv16x_tap_axis_priority_t val); -int32_t lsm6dsv16x_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_tap_axis_priority_get(const stmdev_ctx_t *ctx, lsm6dsv16x_tap_axis_priority_t *val); typedef struct @@ -5178,9 +5182,9 @@ typedef struct uint8_t quiet : 2; uint8_t tap_gap : 4; } lsm6dsv16x_tap_time_windows_t; -int32_t lsm6dsv16x_tap_time_windows_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_tap_time_windows_set(const stmdev_ctx_t *ctx, lsm6dsv16x_tap_time_windows_t val); -int32_t lsm6dsv16x_tap_time_windows_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_tap_time_windows_get(const stmdev_ctx_t *ctx, lsm6dsv16x_tap_time_windows_t *val); typedef enum @@ -5188,16 +5192,16 @@ typedef enum LSM6DSV16X_ONLY_SINGLE = 0x0, LSM6DSV16X_BOTH_SINGLE_DOUBLE = 0x1, } lsm6dsv16x_tap_mode_t; -int32_t lsm6dsv16x_tap_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_tap_mode_t val); -int32_t lsm6dsv16x_tap_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_tap_mode_t *val); +int32_t lsm6dsv16x_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_tap_mode_t val); +int32_t lsm6dsv16x_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_tap_mode_t *val); -int32_t lsm6dsv16x_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv16x_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); +int32_t lsm6dsv16x_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); -int32_t lsm6dsv16x_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv16x_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv16x_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv16x_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -5206,8 +5210,8 @@ typedef enum LSM6DSV16X_XL_LOW_POWER_GY_SLEEP = 0x2, LSM6DSV16X_XL_LOW_POWER_GY_POWER_DOWN = 0x3, } lsm6dsv16x_act_mode_t; -int32_t lsm6dsv16x_act_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_act_mode_t val); -int32_t lsm6dsv16x_act_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_act_mode_t *val); +int32_t lsm6dsv16x_act_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_act_mode_t val); +int32_t lsm6dsv16x_act_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_act_mode_t *val); typedef enum { @@ -5216,9 +5220,9 @@ typedef enum LSM6DSV16X_SLEEP_TO_ACT_AT_3RD_SAMPLE = 0x2, LSM6DSV16X_SLEEP_TO_ACT_AT_4th_SAMPLE = 0x3, } lsm6dsv16x_act_from_sleep_to_act_dur_t; -int32_t lsm6dsv16x_act_from_sleep_to_act_dur_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_act_from_sleep_to_act_dur_set(const stmdev_ctx_t *ctx, lsm6dsv16x_act_from_sleep_to_act_dur_t val); -int32_t lsm6dsv16x_act_from_sleep_to_act_dur_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx, lsm6dsv16x_act_from_sleep_to_act_dur_t *val); typedef enum @@ -5228,9 +5232,9 @@ typedef enum LSM6DSV16X_30Hz = 0x2, LSM6DSV16X_60Hz = 0x3, } lsm6dsv16x_act_sleep_xl_odr_t; -int32_t lsm6dsv16x_act_sleep_xl_odr_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_act_sleep_xl_odr_set(const stmdev_ctx_t *ctx, lsm6dsv16x_act_sleep_xl_odr_t val); -int32_t lsm6dsv16x_act_sleep_xl_odr_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx, lsm6dsv16x_act_sleep_xl_odr_t *val); typedef struct @@ -5240,9 +5244,9 @@ typedef struct uint8_t threshold; uint8_t duration; } lsm6dsv16x_act_thresholds_t; -int32_t lsm6dsv16x_act_thresholds_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_act_thresholds_set(const stmdev_ctx_t *ctx, lsm6dsv16x_act_thresholds_t *val); -int32_t lsm6dsv16x_act_thresholds_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_act_thresholds_get(const stmdev_ctx_t *ctx, lsm6dsv16x_act_thresholds_t *val); typedef struct @@ -5250,9 +5254,9 @@ typedef struct uint8_t shock : 2; uint8_t quiet : 4; } lsm6dsv16x_act_wkup_time_windows_t; -int32_t lsm6dsv16x_act_wkup_time_windows_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_act_wkup_time_windows_set(const stmdev_ctx_t *ctx, lsm6dsv16x_act_wkup_time_windows_t val); -int32_t lsm6dsv16x_act_wkup_time_windows_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv16x_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, lsm6dsv16x_act_wkup_time_windows_t *val); /** diff --git a/sensor/stmemsc/lsm6dsv32x_STdC/driver/lsm6dsv32x_reg.c b/sensor/stmemsc/lsm6dsv32x_STdC/driver/lsm6dsv32x_reg.c new file mode 100644 index 00000000..21128f19 --- /dev/null +++ b/sensor/stmemsc/lsm6dsv32x_STdC/driver/lsm6dsv32x_reg.c @@ -0,0 +1,10459 @@ +/** + ****************************************************************************** + * @file lsm6dsv32x_reg.c + * @author Sensors Software Solution Team + * @brief LSM6DSV32X driver file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2024 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "lsm6dsv32x_reg.h" + +/** + * @defgroup LSM6DSV32X + * @brief This file provides a set of functions needed to drive the + * lsm6dsv32x enhanced inertial module. + * @{ + * + */ + +/** + * @defgroup Interfaces functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +/** + * @brief Read generic device register + * + * @param ctx communication interface handler.(ptr) + * @param reg first register address to read. + * @param data buffer for data read.(ptr) + * @param len number of consecutive register to read. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak lsm6dsv32x_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) +{ + int32_t ret; + + if (ctx == NULL) + { + return -1; + } + + ret = ctx->read_reg(ctx->handle, reg, data, len); + + return ret; +} + +/** + * @brief Write generic device register + * + * @param ctx communication interface handler.(ptr) + * @param reg first register address to write. + * @param data the buffer contains data to be written.(ptr) + * @param len number of consecutive register to write. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak lsm6dsv32x_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) +{ + int32_t ret; + + if (ctx == NULL) + { + return -1; + } + + ret = ctx->write_reg(ctx->handle, reg, data, len); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Private functions + * @brief Section collect all the utility functions needed by APIs. + * @{ + * + */ + +static void bytecpy(uint8_t *target, uint8_t *source) +{ + if ((target != NULL) && (source != NULL)) + { + *target = *source; + } +} + +/** + * @} + * + */ + +/** + * @defgroup Sensitivity + * @brief These functions convert raw-data into engineering units. + * @{ + * + */ +float_t lsm6dsv32x_from_sflp_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.061f; +} + +float_t lsm6dsv32x_from_fs4_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.122f; +} + +float_t lsm6dsv32x_from_fs8_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.244f; +} + +float_t lsm6dsv32x_from_fs16_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.488f; +} + +float_t lsm6dsv32x_from_fs32_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.976f; +} + +float_t lsm6dsv32x_from_fs125_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 4.375f; +} + +float_t lsm6dsv32x_from_fs250_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 8.750f; +} + +float_t lsm6dsv32x_from_fs500_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 17.50f; +} + +float_t lsm6dsv32x_from_fs1000_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 35.0f; +} + +float_t lsm6dsv32x_from_fs2000_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 70.0f; +} + +float_t lsm6dsv32x_from_fs4000_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 140.0f; +} + +float_t lsm6dsv32x_from_lsb_to_celsius(int16_t lsb) +{ + return (((float_t)lsb / 256.0f) + 25.0f); +} + +float_t lsm6dsv32x_from_lsb_to_nsec(uint32_t lsb) +{ + return ((float_t)lsb * 21750.0f); +} + +float_t lsm6dsv32x_from_lsb_to_mv(int16_t lsb) +{ + return ((float_t)lsb) / 78.0f; +} + +/** + * @} + * + */ + +/** + * @defgroup Accelerometer user offset correction + * @brief This section groups all the functions concerning the + * usage of Accelerometer user offset correction + * @{ + * + */ + +/** + * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[set] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_xl_offset_on_out_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.usr_off_on_out = val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[get] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.usr_off_on_out; + + return ret; +} + +/** + * @brief Accelerometer user offset correction values in mg.[set] + * + * @param ctx read / write interface definitions + * @param val Accelerometer user offset correction values in mg. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_xl_offset_mg_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_xl_offset_mg_t val) +{ + lsm6dsv32x_z_ofs_usr_t z_ofs_usr; + lsm6dsv32x_y_ofs_usr_t y_ofs_usr; + lsm6dsv32x_x_ofs_usr_t x_ofs_usr; + lsm6dsv32x_ctrl9_t ctrl9; + int32_t ret; + float_t tmp; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + if (ret != 0) + { + return ret; + } + + + if ((val.x_mg < (0.0078125f * 127.0f)) && (val.x_mg > (0.0078125f * -127.0f)) && + (val.y_mg < (0.0078125f * 127.0f)) && (val.y_mg > (0.0078125f * -127.0f)) && + (val.z_mg < (0.0078125f * 127.0f)) && (val.z_mg > (0.0078125f * -127.0f))) + { + ctrl9.usr_off_w = 0; + + tmp = val.z_mg / 0.0078125f; + z_ofs_usr.z_ofs_usr = (uint8_t)tmp; + + tmp = val.y_mg / 0.0078125f; + y_ofs_usr.y_ofs_usr = (uint8_t)tmp; + + tmp = val.x_mg / 0.0078125f; + x_ofs_usr.x_ofs_usr = (uint8_t)tmp; + } + else if ((val.x_mg < (0.125f * 127.0f)) && (val.x_mg > (0.125f * -127.0f)) && + (val.y_mg < (0.125f * 127.0f)) && (val.y_mg > (0.125f * -127.0f)) && + (val.z_mg < (0.125f * 127.0f)) && (val.z_mg > (0.125f * -127.0f))) + { + ctrl9.usr_off_w = 1; + + tmp = val.z_mg / 0.125f; + z_ofs_usr.z_ofs_usr = (uint8_t)tmp; + + tmp = val.y_mg / 0.125f; + y_ofs_usr.y_ofs_usr = (uint8_t)tmp; + + tmp = val.x_mg / 0.125f; + x_ofs_usr.x_ofs_usr = (uint8_t)tmp; + } + else // out of limit + { + ctrl9.usr_off_w = 1; + z_ofs_usr.z_ofs_usr = 0xFFU; + y_ofs_usr.y_ofs_usr = 0xFFU; + x_ofs_usr.x_ofs_usr = 0xFFU; + } + + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1); + + return ret; +} + +/** + * @brief Accelerometer user offset correction values in mg.[get] + * + * @param ctx read / write interface definitions + * @param val Accelerometer user offset correction values in mg. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_xl_offset_mg_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_xl_offset_mg_t *val) +{ + lsm6dsv32x_z_ofs_usr_t z_ofs_usr; + lsm6dsv32x_y_ofs_usr_t y_ofs_usr; + lsm6dsv32x_x_ofs_usr_t x_ofs_usr; + lsm6dsv32x_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + if (ret != 0) + { + return ret; + } + + if (ctrl9.usr_off_w == PROPERTY_DISABLE) + { + val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.0078125f); + val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.0078125f); + val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.0078125f); + } + else + { + val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.125f); + val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.125f); + val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.125f); + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @brief Reset of the device.[set] + * + * @param ctx read / write interface definitions + * @param val Reset of the device. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_reset_set(const stmdev_ctx_t *ctx, lsm6dsv32x_reset_t val) +{ + lsm6dsv32x_func_cfg_access_t func_cfg_access; + lsm6dsv32x_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL3, (uint8_t *)&ctrl3, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } + + ctrl3.boot = ((uint8_t)val & 0x04U) >> 2; + ctrl3.sw_reset = ((uint8_t)val & 0x02U) >> 1; + func_cfg_access.sw_por = (uint8_t)val & 0x01U; + + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL3, (uint8_t *)&ctrl3, 1); + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + return ret; +} + +/** + * @brief Global reset of the device.[get] + * + * @param ctx read / write interface definitions + * @param val Global reset of the device. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_reset_get(const stmdev_ctx_t *ctx, lsm6dsv32x_reset_t *val) +{ + lsm6dsv32x_func_cfg_access_t func_cfg_access; + lsm6dsv32x_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL3, (uint8_t *)&ctrl3, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } + + switch ((ctrl3.sw_reset << 2) + (ctrl3.boot << 1) + func_cfg_access.sw_por) + { + case LSM6DSV32X_READY: + *val = LSM6DSV32X_READY; + break; + + case LSM6DSV32X_GLOBAL_RST: + *val = LSM6DSV32X_GLOBAL_RST; + break; + + case LSM6DSV32X_RESTORE_CAL_PARAM: + *val = LSM6DSV32X_RESTORE_CAL_PARAM; + break; + + case LSM6DSV32X_RESTORE_CTRL_REGS: + *val = LSM6DSV32X_RESTORE_CTRL_REGS; + break; + + default: + *val = LSM6DSV32X_GLOBAL_RST; + break; + } + + return ret; +} + +/** + * @brief Change memory bank.[set] + * + * @param ctx read / write interface definitions + * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dsv32x_mem_bank_t val) +{ + lsm6dsv32x_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } + + func_cfg_access.shub_reg_access = ((uint8_t)val & 0x02U) >> 1; + func_cfg_access.emb_func_reg_access = (uint8_t)val & 0x01U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + return ret; +} + +/** + * @brief Change memory bank.[get] + * + * @param ctx read / write interface definitions + * @param val MAIN_MEM_BANK, SENSOR_HUB_MEM_BANK, EMBED_FUNC_MEM_BANK, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dsv32x_mem_bank_t *val) +{ + lsm6dsv32x_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } + + switch ((func_cfg_access.shub_reg_access << 1) + func_cfg_access.emb_func_reg_access) + { + case LSM6DSV32X_MAIN_MEM_BANK: + *val = LSM6DSV32X_MAIN_MEM_BANK; + break; + + case LSM6DSV32X_EMBED_FUNC_MEM_BANK: + *val = LSM6DSV32X_EMBED_FUNC_MEM_BANK; + break; + + case LSM6DSV32X_SENSOR_HUB_MEM_BANK: + *val = LSM6DSV32X_SENSOR_HUB_MEM_BANK; + break; + + default: + *val = LSM6DSV32X_MAIN_MEM_BANK; + break; + } + + return ret; +} + +/** + * @brief Device ID.[get] THis function works also for OIS + * (WHO_AM_I and SPI2_WHO_AM_I have same address) + * + * @param ctx read / write interface definitions + * @param val Device ID. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WHO_AM_I, val, 1); + + return ret; +} + +/** + * @brief Accelerometer output data rate (ODR) selection.[set] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv32x_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_xl_data_rate_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_data_rate_t val) +{ + lsm6dsv32x_ctrl1_t ctrl1; + lsm6dsv32x_haodr_cfg_t haodr; + uint8_t sel; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) + { + return ret; + } + + ctrl1.odr_xl = (uint8_t)val & 0x0Fu; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) + { + return ret; + } + + sel = ((uint8_t)val >> 4) & 0xFU; + if (sel != 0U) + { + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_HAODR_CFG, (uint8_t *)&haodr, 1); + haodr.haodr_sel = sel; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_HAODR_CFG, (uint8_t *)&haodr, 1); + } + + return ret; +} + +/** + * @brief Accelerometer output data rate (ODR) selection.[get] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv32x_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_xl_data_rate_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_data_rate_t *val) +{ + lsm6dsv32x_ctrl1_t ctrl1; + lsm6dsv32x_haodr_cfg_t haodr; + uint8_t sel; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL1, (uint8_t *)&ctrl1, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_HAODR_CFG, (uint8_t *)&haodr, 1); + if (ret != 0) + { + return ret; + } + + sel = haodr.haodr_sel; + + switch (ctrl1.odr_xl) + { + case LSM6DSV32X_ODR_OFF: + *val = LSM6DSV32X_ODR_OFF; + break; + + case LSM6DSV32X_ODR_AT_1Hz875: + *val = LSM6DSV32X_ODR_AT_1Hz875; + break; + + case LSM6DSV32X_ODR_AT_7Hz5: + *val = LSM6DSV32X_ODR_AT_7Hz5; + break; + + case LSM6DSV32X_ODR_AT_15Hz: + switch (sel) + { + default: + case 0: + *val = LSM6DSV32X_ODR_AT_15Hz; + break; + case 1: + *val = LSM6DSV32X_ODR_HA01_AT_15Hz625; + break; + case 2: + *val = LSM6DSV32X_ODR_HA02_AT_12Hz5; + break; + } + break; + + case LSM6DSV32X_ODR_AT_30Hz: + switch (sel) + { + default: + case 0: + *val = LSM6DSV32X_ODR_AT_30Hz; + break; + case 1: + *val = LSM6DSV32X_ODR_HA01_AT_31Hz25; + break; + case 2: + *val = LSM6DSV32X_ODR_HA02_AT_25Hz; + break; + } + break; + + case LSM6DSV32X_ODR_AT_60Hz: + switch (sel) + { + default: + case 0: + *val = LSM6DSV32X_ODR_AT_60Hz; + break; + case 1: + *val = LSM6DSV32X_ODR_HA01_AT_62Hz5; + break; + case 2: + *val = LSM6DSV32X_ODR_HA02_AT_50Hz; + break; + } + break; + + case LSM6DSV32X_ODR_AT_120Hz: + switch (sel) + { + default: + case 0: + *val = LSM6DSV32X_ODR_AT_120Hz; + break; + case 1: + *val = LSM6DSV32X_ODR_HA01_AT_125Hz; + break; + case 2: + *val = LSM6DSV32X_ODR_HA02_AT_100Hz; + break; + } + break; + + case LSM6DSV32X_ODR_AT_240Hz: + switch (sel) + { + default: + case 0: + *val = LSM6DSV32X_ODR_AT_240Hz; + break; + case 1: + *val = LSM6DSV32X_ODR_HA01_AT_250Hz; + break; + case 2: + *val = LSM6DSV32X_ODR_HA02_AT_200Hz; + break; + } + break; + + case LSM6DSV32X_ODR_AT_480Hz: + switch (sel) + { + default: + case 0: + *val = LSM6DSV32X_ODR_AT_480Hz; + break; + case 1: + *val = LSM6DSV32X_ODR_HA01_AT_500Hz; + break; + case 2: + *val = LSM6DSV32X_ODR_HA02_AT_400Hz; + break; + } + break; + + case LSM6DSV32X_ODR_AT_960Hz: + switch (sel) + { + default: + case 0: + *val = LSM6DSV32X_ODR_AT_960Hz; + break; + case 1: + *val = LSM6DSV32X_ODR_HA01_AT_1000Hz; + break; + case 2: + *val = LSM6DSV32X_ODR_HA02_AT_800Hz; + break; + } + break; + + case LSM6DSV32X_ODR_AT_1920Hz: + switch (sel) + { + default: + case 0: + *val = LSM6DSV32X_ODR_AT_1920Hz; + break; + case 1: + *val = LSM6DSV32X_ODR_HA01_AT_2000Hz; + break; + case 2: + *val = LSM6DSV32X_ODR_HA02_AT_1600Hz; + break; + } + break; + + case LSM6DSV32X_ODR_AT_3840Hz: + switch (sel) + { + default: + case 0: + *val = LSM6DSV32X_ODR_AT_3840Hz; + break; + case 1: + *val = LSM6DSV32X_ODR_HA01_AT_4000Hz; + break; + case 2: + *val = LSM6DSV32X_ODR_HA02_AT_3200Hz; + break; + } + break; + + case LSM6DSV32X_ODR_AT_7680Hz: + switch (sel) + { + default: + case 0: + *val = LSM6DSV32X_ODR_AT_7680Hz; + break; + case 1: + *val = LSM6DSV32X_ODR_HA01_AT_8000Hz; + break; + case 2: + *val = LSM6DSV32X_ODR_HA02_AT_6400Hz; + break; + } + break; + + default: + *val = LSM6DSV32X_ODR_OFF; + break; + } + + return ret; +} + +/** + * @brief Accelerometer operating mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val XL_HIGH_PERFORMANCE_MD, XL_HIGH_ACCURACY_ODR_MD, XL_LOW_POWER_2_AVG_MD, XL_LOW_POWER_4_AVG_MD, XL_LOW_POWER_8_AVG_MD, XL_NORMAL_MD, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_xl_mode_set(const stmdev_ctx_t *ctx, lsm6dsv32x_xl_mode_t val) +{ + lsm6dsv32x_ctrl1_t ctrl1; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL1, (uint8_t *)&ctrl1, 1); + + if (ret == 0) + { + ctrl1.op_mode_xl = (uint8_t)val & 0x07U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL1, (uint8_t *)&ctrl1, 1); + } + + return ret; +} + +/** + * @brief Accelerometer operating mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val XL_HIGH_PERFORMANCE_MD, XL_HIGH_ACCURACY_ODR_MD, XL_LOW_POWER_2_AVG_MD, XL_LOW_POWER_4_AVG_MD, XL_LOW_POWER_8_AVG_MD, XL_NORMAL_MD, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_xl_mode_get(const stmdev_ctx_t *ctx, lsm6dsv32x_xl_mode_t *val) +{ + lsm6dsv32x_ctrl1_t ctrl1; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl1.op_mode_xl) + { + case LSM6DSV32X_XL_HIGH_PERFORMANCE_MD: + *val = LSM6DSV32X_XL_HIGH_PERFORMANCE_MD; + break; + + case LSM6DSV32X_XL_HIGH_ACCURACY_ODR_MD: + *val = LSM6DSV32X_XL_HIGH_ACCURACY_ODR_MD; + break; + + case LSM6DSV32X_XL_ODR_TRIGGERED_MD: + *val = LSM6DSV32X_XL_ODR_TRIGGERED_MD; + break; + + case LSM6DSV32X_XL_LOW_POWER_2_AVG_MD: + *val = LSM6DSV32X_XL_LOW_POWER_2_AVG_MD; + break; + + case LSM6DSV32X_XL_LOW_POWER_4_AVG_MD: + *val = LSM6DSV32X_XL_LOW_POWER_4_AVG_MD; + break; + + case LSM6DSV32X_XL_LOW_POWER_8_AVG_MD: + *val = LSM6DSV32X_XL_LOW_POWER_8_AVG_MD; + break; + + case LSM6DSV32X_XL_NORMAL_MD: + *val = LSM6DSV32X_XL_NORMAL_MD; + break; + + default: + *val = LSM6DSV32X_XL_HIGH_PERFORMANCE_MD; + break; + } + + return ret; +} + +/** + * @brief Gyroscope output data rate (ODR) selection.[set] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv32x_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_gy_data_rate_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_data_rate_t val) +{ + lsm6dsv32x_ctrl2_t ctrl2; + lsm6dsv32x_haodr_cfg_t haodr; + uint8_t sel; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL2, (uint8_t *)&ctrl2, 1); + + ctrl2.odr_g = (uint8_t)val & 0x0Fu; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret != 0) + { + return ret; + } + + sel = ((uint8_t)val >> 4) & 0xFU; + if (sel != 0U) + { + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_HAODR_CFG, (uint8_t *)&haodr, 1); + haodr.haodr_sel = sel; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_HAODR_CFG, (uint8_t *)&haodr, 1); + } + + return ret; +} + +/** + * @brief Gyroscope output data rate (ODR) selection.[get] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv32x_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_gy_data_rate_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_data_rate_t *val) +{ + lsm6dsv32x_ctrl2_t ctrl2; + lsm6dsv32x_haodr_cfg_t haodr; + uint8_t sel; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL2, (uint8_t *)&ctrl2, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_HAODR_CFG, (uint8_t *)&haodr, 1); + if (ret != 0) + { + return ret; + } + + sel = haodr.haodr_sel; + + switch (ctrl2.odr_g) + { + case LSM6DSV32X_ODR_OFF: + *val = LSM6DSV32X_ODR_OFF; + break; + + case LSM6DSV32X_ODR_AT_1Hz875: + *val = LSM6DSV32X_ODR_AT_1Hz875; + break; + + case LSM6DSV32X_ODR_AT_7Hz5: + *val = LSM6DSV32X_ODR_AT_7Hz5; + break; + + case LSM6DSV32X_ODR_AT_15Hz: + switch (sel) + { + default: + case 0: + *val = LSM6DSV32X_ODR_AT_15Hz; + break; + case 1: + *val = LSM6DSV32X_ODR_HA01_AT_15Hz625; + break; + case 2: + *val = LSM6DSV32X_ODR_HA02_AT_12Hz5; + break; + } + break; + + case LSM6DSV32X_ODR_AT_30Hz: + switch (sel) + { + default: + case 0: + *val = LSM6DSV32X_ODR_AT_30Hz; + break; + case 1: + *val = LSM6DSV32X_ODR_HA01_AT_31Hz25; + break; + case 2: + *val = LSM6DSV32X_ODR_HA02_AT_25Hz; + break; + } + break; + + case LSM6DSV32X_ODR_AT_60Hz: + switch (sel) + { + default: + case 0: + *val = LSM6DSV32X_ODR_AT_60Hz; + break; + case 1: + *val = LSM6DSV32X_ODR_HA01_AT_62Hz5; + break; + case 2: + *val = LSM6DSV32X_ODR_HA02_AT_50Hz; + break; + } + break; + + case LSM6DSV32X_ODR_AT_120Hz: + switch (sel) + { + default: + case 0: + *val = LSM6DSV32X_ODR_AT_120Hz; + break; + case 1: + *val = LSM6DSV32X_ODR_HA01_AT_125Hz; + break; + case 2: + *val = LSM6DSV32X_ODR_HA02_AT_100Hz; + break; + } + break; + + case LSM6DSV32X_ODR_AT_240Hz: + switch (sel) + { + default: + case 0: + *val = LSM6DSV32X_ODR_AT_240Hz; + break; + case 1: + *val = LSM6DSV32X_ODR_HA01_AT_250Hz; + break; + case 2: + *val = LSM6DSV32X_ODR_HA02_AT_200Hz; + break; + } + break; + + case LSM6DSV32X_ODR_AT_480Hz: + switch (sel) + { + default: + case 0: + *val = LSM6DSV32X_ODR_AT_480Hz; + break; + case 1: + *val = LSM6DSV32X_ODR_HA01_AT_500Hz; + break; + case 2: + *val = LSM6DSV32X_ODR_HA02_AT_400Hz; + break; + } + break; + + case LSM6DSV32X_ODR_AT_960Hz: + switch (sel) + { + default: + case 0: + *val = LSM6DSV32X_ODR_AT_960Hz; + break; + case 1: + *val = LSM6DSV32X_ODR_HA01_AT_1000Hz; + break; + case 2: + *val = LSM6DSV32X_ODR_HA02_AT_800Hz; + break; + } + break; + + case LSM6DSV32X_ODR_AT_1920Hz: + switch (sel) + { + default: + case 0: + *val = LSM6DSV32X_ODR_AT_1920Hz; + break; + case 1: + *val = LSM6DSV32X_ODR_HA01_AT_2000Hz; + break; + case 2: + *val = LSM6DSV32X_ODR_HA02_AT_1600Hz; + break; + } + break; + + case LSM6DSV32X_ODR_AT_3840Hz: + switch (sel) + { + default: + case 0: + *val = LSM6DSV32X_ODR_AT_3840Hz; + break; + case 1: + *val = LSM6DSV32X_ODR_HA01_AT_4000Hz; + break; + case 2: + *val = LSM6DSV32X_ODR_HA02_AT_3200Hz; + break; + } + break; + + case LSM6DSV32X_ODR_AT_7680Hz: + switch (sel) + { + default: + case 0: + *val = LSM6DSV32X_ODR_AT_7680Hz; + break; + case 1: + *val = LSM6DSV32X_ODR_HA01_AT_8000Hz; + break; + case 2: + *val = LSM6DSV32X_ODR_HA02_AT_6400Hz; + break; + } + break; + + default: + *val = LSM6DSV32X_ODR_OFF; + break; + } + + return ret; +} + +/** + * @brief Gyroscope operating mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURACY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_gy_mode_set(const stmdev_ctx_t *ctx, lsm6dsv32x_gy_mode_t val) +{ + lsm6dsv32x_ctrl2_t ctrl2; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret == 0) + { + ctrl2.op_mode_g = (uint8_t)val & 0x07U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL2, (uint8_t *)&ctrl2, 1); + } + + return ret; +} + +/** + * @brief Gyroscope operating mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURACY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_gy_mode_get(const stmdev_ctx_t *ctx, lsm6dsv32x_gy_mode_t *val) +{ + lsm6dsv32x_ctrl2_t ctrl2; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl2.op_mode_g) + { + case LSM6DSV32X_GY_HIGH_PERFORMANCE_MD: + *val = LSM6DSV32X_GY_HIGH_PERFORMANCE_MD; + break; + + case LSM6DSV32X_GY_HIGH_ACCURACY_ODR_MD: + *val = LSM6DSV32X_GY_HIGH_ACCURACY_ODR_MD; + break; + + case LSM6DSV32X_GY_SLEEP_MD: + *val = LSM6DSV32X_GY_SLEEP_MD; + break; + + case LSM6DSV32X_GY_LOW_POWER_MD: + *val = LSM6DSV32X_GY_LOW_POWER_MD; + break; + + default: + *val = LSM6DSV32X_GY_HIGH_PERFORMANCE_MD; + break; + } + + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[set] + * + * @param ctx read / write interface definitions + * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret == 0) + { + ctrl3.if_inc = val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL3, (uint8_t *)&ctrl3, 1); + } + + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[get] + * + * @param ctx read / write interface definitions + * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL3, (uint8_t *)&ctrl3, 1); + *val = ctrl3.if_inc; + + return ret; +} + +/** + * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [set] + * + * @param ctx read / write interface definitions + * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL3, (uint8_t *)&ctrl3, 1); + + if (ret == 0) + { + ctrl3.bdu = val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL3, (uint8_t *)&ctrl3, 1); + } + + return ret; +} + +/** + * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [get] + * + * @param ctx read / write interface definitions + * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_ctrl3_t ctrl3; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL3, (uint8_t *)&ctrl3, 1); + *val = ctrl3.bdu; + + return ret; +} + +/** + * @brief Configure ODR trigger. [set] + * + * @param ctx read / write interface definitions + * @param val number of data in the reference period. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_odr_trig_cfg_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_odr_trig_cfg_t odr_trig; + int32_t ret; + + if (val >= 1U && val <= 3U) + { + return -1; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_ODR_TRIG_CFG, (uint8_t *)&odr_trig, 1); + + if (ret == 0) + { + odr_trig.odr_trig_nodr = val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_ODR_TRIG_CFG, (uint8_t *)&odr_trig, 1); + } + + return ret; +} + +/** + * @brief Configure ODR trigger. [get] + * + * @param ctx read / write interface definitions + * @param val number of data in the reference period. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_odr_trig_cfg_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_odr_trig_cfg_t odr_trig; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_ODR_TRIG_CFG, (uint8_t *)&odr_trig, 1); + *val = odr_trig.odr_trig_nodr; + + return ret; +} + +/** + * @brief Enables pulsed data-ready mode (~75 us).[set] + * + * @param ctx read / write interface definitions + * @param val DRDY_LATCHED, DRDY_PULSED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_data_ready_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_data_ready_mode_t val) +{ + lsm6dsv32x_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1); + + if (ret == 0) + { + ctrl4.drdy_pulsed = (uint8_t)val & 0x1U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1); + } + + return ret; +} + +/** + * @brief Enables pulsed data-ready mode (~75 us).[get] + * + * @param ctx read / write interface definitions + * @param val DRDY_LATCHED, DRDY_PULSED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_data_ready_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_data_ready_mode_t *val) +{ + lsm6dsv32x_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1); + + switch (ctrl4.drdy_pulsed) + { + case LSM6DSV32X_DRDY_LATCHED: + *val = LSM6DSV32X_DRDY_LATCHED; + break; + + case LSM6DSV32X_DRDY_PULSED: + *val = LSM6DSV32X_DRDY_PULSED; + break; + + default: + *val = LSM6DSV32X_DRDY_LATCHED; + break; + } + + return ret; +} + +/** + * @brief Enables interrupt.[set] + * + * @param ctx read / write interface definitions + * @param val enable/disable, latched/pulsed + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_interrupt_enable_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_interrupt_mode_t val) +{ + lsm6dsv32x_tap_cfg0_t cfg; + lsm6dsv32x_functions_enable_t func; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); + func.interrupts_enable = val.enable; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&cfg, 1); + cfg.lir = val.lir; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&cfg, 1); + + return ret; +} + +/** + * @brief Enables latched interrupt mode.[get] + * + * @param ctx read / write interface definitions + * @param val enable/disable, latched/pulsed + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_interrupt_enable_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_interrupt_mode_t *val) +{ + lsm6dsv32x_tap_cfg0_t cfg; + lsm6dsv32x_functions_enable_t func; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&cfg, 1); + if (ret != 0) + { + return ret; + } + + val->enable = func.interrupts_enable; + val->lir = cfg.lir; + + return ret; +} + +/** + * @brief Gyroscope full-scale selection[set] + * + * @param ctx read / write interface definitions + * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_gy_full_scale_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_gy_full_scale_t val) +{ + lsm6dsv32x_ctrl6_t ctrl6; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL6, (uint8_t *)&ctrl6, 1); + + if (ret == 0) + { + ctrl6.fs_g = (uint8_t)val & 0xfu; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL6, (uint8_t *)&ctrl6, 1); + } + + return ret; +} + +/** + * @brief Gyroscope full-scale selection[get] + * + * @param ctx read / write interface definitions + * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_gy_full_scale_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_gy_full_scale_t *val) +{ + lsm6dsv32x_ctrl6_t ctrl6; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL6, (uint8_t *)&ctrl6, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl6.fs_g) + { + case LSM6DSV32X_125dps: + *val = LSM6DSV32X_125dps; + break; + + case LSM6DSV32X_250dps: + *val = LSM6DSV32X_250dps; + break; + + case LSM6DSV32X_500dps: + *val = LSM6DSV32X_500dps; + break; + + case LSM6DSV32X_1000dps: + *val = LSM6DSV32X_1000dps; + break; + + case LSM6DSV32X_2000dps: + *val = LSM6DSV32X_2000dps; + break; + + case LSM6DSV32X_4000dps: + *val = LSM6DSV32X_4000dps; + break; + + default: + *val = LSM6DSV32X_125dps; + break; + } + + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[set] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv32x_xl_full_scale_t + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_xl_full_scale_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_xl_full_scale_t val) +{ + lsm6dsv32x_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL8, (uint8_t *)&ctrl8, 1); + + if (ret == 0) + { + ctrl8.fs_xl = (uint8_t)val & 0x3U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL8, (uint8_t *)&ctrl8, 1); + } + + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[get] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv32x_xl_full_scale_t + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_xl_full_scale_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_xl_full_scale_t *val) +{ + lsm6dsv32x_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl8.fs_xl) + { + + case LSM6DSV32X_4g: + *val = LSM6DSV32X_4g; + break; + + case LSM6DSV32X_8g: + *val = LSM6DSV32X_8g; + break; + + case LSM6DSV32X_16g: + *val = LSM6DSV32X_16g; + break; + + case LSM6DSV32X_32g: + *val = LSM6DSV32X_32g; + break; + + default: + *val = LSM6DSV32X_4g; + break; + } + + return ret; +} + +/** + * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[set] + * + * @param ctx read / write interface definitions + * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_xl_dual_channel_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL8, (uint8_t *)&ctrl8, 1); + + if (ret == 0) + { + ctrl8.xl_dualc_en = val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL8, (uint8_t *)&ctrl8, 1); + } + + return ret; +} + +/** + * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[get] + * + * @param ctx read / write interface definitions + * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL8, (uint8_t *)&ctrl8, 1); + *val = ctrl8.xl_dualc_en; + + return ret; +} + +/** + * @brief Accelerometer self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_xl_self_test_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_xl_self_test_t val) +{ + lsm6dsv32x_ctrl10_t ctrl10; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL10, (uint8_t *)&ctrl10, 1); + + if (ret == 0) + { + ctrl10.st_xl = (uint8_t)val & 0x3U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL10, (uint8_t *)&ctrl10, 1); + } + + return ret; +} + +/** + * @brief Accelerometer self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_xl_self_test_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_xl_self_test_t *val) +{ + lsm6dsv32x_ctrl10_t ctrl10; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL10, (uint8_t *)&ctrl10, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl10.st_xl) + { + case LSM6DSV32X_XL_ST_DISABLE: + *val = LSM6DSV32X_XL_ST_DISABLE; + break; + + case LSM6DSV32X_XL_ST_POSITIVE: + *val = LSM6DSV32X_XL_ST_POSITIVE; + break; + + case LSM6DSV32X_XL_ST_NEGATIVE: + *val = LSM6DSV32X_XL_ST_NEGATIVE; + break; + + default: + *val = LSM6DSV32X_XL_ST_DISABLE; + break; + } + + return ret; +} + +/** + * @brief Gyroscope self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_gy_self_test_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_gy_self_test_t val) +{ + lsm6dsv32x_ctrl10_t ctrl10; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL10, (uint8_t *)&ctrl10, 1); + + if (ret == 0) + { + ctrl10.st_g = (uint8_t)val & 0x3U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL10, (uint8_t *)&ctrl10, 1); + } + + return ret; +} + +/** + * @brief Gyroscope self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_gy_self_test_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_gy_self_test_t *val) +{ + lsm6dsv32x_ctrl10_t ctrl10; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL10, (uint8_t *)&ctrl10, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl10.st_g) + { + case LSM6DSV32X_GY_ST_DISABLE: + *val = LSM6DSV32X_GY_ST_DISABLE; + break; + + case LSM6DSV32X_GY_ST_POSITIVE: + *val = LSM6DSV32X_GY_ST_POSITIVE; + break; + + case LSM6DSV32X_GY_ST_NEGATIVE: + *val = LSM6DSV32X_GY_ST_NEGATIVE; + break; + + default: + *val = LSM6DSV32X_GY_ST_DISABLE; + break; + } + + return ret; +} + +/** + * @brief SPI2 Accelerometer self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ois_xl_self_test_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_xl_self_test_t val) +{ + lsm6dsv32x_spi2_int_ois_t spi2_int_ois; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + + if (ret == 0) + { + spi2_int_ois.st_xl_ois = ((uint8_t)val & 0x3U); + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + } + + return ret; +} + +/** + * @brief SPI2 Accelerometer self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ois_xl_self_test_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_xl_self_test_t *val) +{ + lsm6dsv32x_spi2_int_ois_t spi2_int_ois; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + if (ret != 0) + { + return ret; + } + + switch (spi2_int_ois.st_xl_ois) + { + case LSM6DSV32X_OIS_XL_ST_DISABLE: + *val = LSM6DSV32X_OIS_XL_ST_DISABLE; + break; + + case LSM6DSV32X_OIS_XL_ST_POSITIVE: + *val = LSM6DSV32X_OIS_XL_ST_POSITIVE; + break; + + case LSM6DSV32X_OIS_XL_ST_NEGATIVE: + *val = LSM6DSV32X_OIS_XL_ST_NEGATIVE; + break; + + default: + *val = LSM6DSV32X_OIS_XL_ST_DISABLE; + break; + } + + return ret; +} + +/** + * @brief SPI2 Accelerometer self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val GY_ST_DISABLE, GY_ST_POSITIVE, GY_ST_NEGATIVE, LSM6DSV32X_OIS_GY_ST_CLAMP_POS, LSM6DSV32X_OIS_GY_ST_CLAMP_NEG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ois_gy_self_test_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_gy_self_test_t val) +{ + lsm6dsv32x_spi2_int_ois_t spi2_int_ois; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + + if (ret == 0) + { + spi2_int_ois.st_g_ois = ((uint8_t)val & 0x3U); + spi2_int_ois.st_ois_clampdis = ((uint8_t)val & 0x04U) >> 2; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + } + + return ret; +} + +/** + * @brief SPI2 Accelerometer self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val GY_ST_DISABLE, GY_ST_POSITIVE, GY_ST_NEGATIVE, LSM6DSV32X_OIS_GY_ST_CLAMP_POS, LSM6DSV32X_OIS_GY_ST_CLAMP_NEG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ois_gy_self_test_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_gy_self_test_t *val) +{ + lsm6dsv32x_spi2_int_ois_t spi2_int_ois; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + if (ret != 0) + { + return ret; + } + + switch (spi2_int_ois.st_g_ois) + { + case LSM6DSV32X_OIS_GY_ST_DISABLE: + *val = LSM6DSV32X_OIS_GY_ST_DISABLE; + break; + + case LSM6DSV32X_OIS_GY_ST_POSITIVE: + *val = (spi2_int_ois.st_ois_clampdis == 1U) ? LSM6DSV32X_OIS_GY_ST_CLAMP_POS : + LSM6DSV32X_OIS_GY_ST_POSITIVE; + break; + + case LSM6DSV32X_OIS_GY_ST_NEGATIVE: + *val = (spi2_int_ois.st_ois_clampdis == 1U) ? LSM6DSV32X_OIS_GY_ST_CLAMP_NEG : + LSM6DSV32X_OIS_GY_ST_NEGATIVE; + break; + + default: + *val = LSM6DSV32X_OIS_GY_ST_DISABLE; + break; + } + + return ret; +} + +/** + * @defgroup interrupt_pins + * @brief This section groups all the functions that manage + * interrupt pins + * @{ + * + */ + +/** + * @brief Select the signal that need to route on int1 pad[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val the signals to route on int1 pin. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsv32x_pin_int1_route_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_pin_int_route_t *val) +{ + lsm6dsv32x_int1_ctrl_t int1_ctrl; + lsm6dsv32x_md1_cfg_t md1_cfg; + int32_t ret; + + /* not available on INT1 */ + if (val->drdy_temp == 1) + { + return -1; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + if (ret != 0) + { + return ret; + } + + int1_ctrl.int1_drdy_xl = val->drdy_xl; + int1_ctrl.int1_drdy_g = val->drdy_g; + int1_ctrl.int1_fifo_th = val->fifo_th; + int1_ctrl.int1_fifo_ovr = val->fifo_ovr; + int1_ctrl.int1_fifo_full = val->fifo_full; + int1_ctrl.int1_cnt_bdr = val->cnt_bdr; + + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MD1_CFG, (uint8_t *)&md1_cfg, 1); + if (ret != 0) + { + return ret; + } + + md1_cfg.int1_shub = val->shub; + md1_cfg.int1_emb_func = val->emb_func; + md1_cfg.int1_6d = val->sixd; + md1_cfg.int1_single_tap = val->single_tap; + md1_cfg.int1_double_tap = val->double_tap; + md1_cfg.int1_wu = val->wakeup; + md1_cfg.int1_ff = val->freefall; + md1_cfg.int1_sleep_change = val->sleep_change; + + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_MD1_CFG, (uint8_t *)&md1_cfg, 1); + + return ret; +} + +/** + * @brief Select the signal that need to route on int1 pad.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val the signals that are routed on int1 pin.(ptr) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsv32x_pin_int1_route_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_pin_int_route_t *val) +{ + lsm6dsv32x_int1_ctrl_t int1_ctrl; + lsm6dsv32x_md1_cfg_t md1_cfg; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + if (ret != 0) + { + return ret; + } + + val->drdy_xl = int1_ctrl.int1_drdy_xl; + val->drdy_g = int1_ctrl.int1_drdy_g; + val->fifo_th = int1_ctrl.int1_fifo_th; + val->fifo_ovr = int1_ctrl.int1_fifo_ovr; + val->fifo_full = int1_ctrl.int1_fifo_full; + val->cnt_bdr = int1_ctrl.int1_cnt_bdr; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MD1_CFG, (uint8_t *)&md1_cfg, 1); + if (ret != 0) + { + return ret; + } + + val->shub = md1_cfg.int1_shub; + val->emb_func = md1_cfg.int1_emb_func; + val->sixd = md1_cfg.int1_6d; + val->single_tap = md1_cfg.int1_single_tap; + val->double_tap = md1_cfg.int1_double_tap; + val->wakeup = md1_cfg.int1_wu; + val->freefall = md1_cfg.int1_ff; + val->sleep_change = md1_cfg.int1_sleep_change; + + return ret; +} + +/** + * @brief Select the signal that need to route on int2 pad[set] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val the signals to route on int1 pin. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsv32x_pin_int2_route_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_pin_int_route_t *val) +{ + lsm6dsv32x_int2_ctrl_t int2_ctrl; + lsm6dsv32x_ctrl4_t ctrl4; + lsm6dsv32x_md2_cfg_t md2_cfg; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + if (ret != 0) + { + return ret; + } + + int2_ctrl.int2_drdy_xl = val->drdy_xl; + int2_ctrl.int2_drdy_g = val->drdy_g; + int2_ctrl.int2_fifo_th = val->fifo_th; + int2_ctrl.int2_fifo_ovr = val->fifo_ovr; + int2_ctrl.int2_fifo_full = val->fifo_full; + int2_ctrl.int2_cnt_bdr = val->cnt_bdr; + int2_ctrl.int2_drdy_g_eis = val->drdy_g_eis; + int2_ctrl.int2_emb_func_endop = val->emb_func_endop; + + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1); + ctrl4.int2_drdy_temp = val->drdy_temp; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MD2_CFG, (uint8_t *)&md2_cfg, 1); + if (ret != 0) + { + return ret; + } + + md2_cfg.int2_timestamp = val->timestamp; + md2_cfg.int2_emb_func = val->emb_func; + md2_cfg.int2_6d = val->sixd; + md2_cfg.int2_single_tap = val->single_tap; + md2_cfg.int2_double_tap = val->double_tap; + md2_cfg.int2_wu = val->wakeup; + md2_cfg.int2_ff = val->freefall; + md2_cfg.int2_sleep_change = val->sleep_change; + + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_MD2_CFG, (uint8_t *)&md2_cfg, 1); + + return ret; +} + +/** + * @brief Select the signal that need to route on int2 pad.[get] + * + * @param ctx Read / write interface definitions.(ptr) + * @param val the signals that are routed on int1 pin.(ptr) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6dsv32x_pin_int2_route_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_pin_int_route_t *val) +{ + lsm6dsv32x_int2_ctrl_t int2_ctrl; + lsm6dsv32x_ctrl4_t ctrl4; + lsm6dsv32x_md2_cfg_t md2_cfg; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + if (ret != 0) + { + return ret; + } + + val->drdy_xl = int2_ctrl.int2_drdy_xl; + val->drdy_g = int2_ctrl.int2_drdy_g; + val->fifo_th = int2_ctrl.int2_fifo_th; + val->fifo_ovr = int2_ctrl.int2_fifo_ovr; + val->fifo_full = int2_ctrl.int2_fifo_full; + val->cnt_bdr = int2_ctrl.int2_cnt_bdr; + val->drdy_g_eis = int2_ctrl.int2_drdy_g_eis; + val->emb_func_endop = int2_ctrl.int2_emb_func_endop; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } + + val->drdy_temp = ctrl4.int2_drdy_temp; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MD2_CFG, (uint8_t *)&md2_cfg, 1); + if (ret != 0) + { + return ret; + } + + val->timestamp = md2_cfg.int2_timestamp; + val->emb_func = md2_cfg.int2_emb_func; + val->sixd = md2_cfg.int2_6d; + val->single_tap = md2_cfg.int2_single_tap; + val->double_tap = md2_cfg.int2_double_tap; + val->wakeup = md2_cfg.int2_wu; + val->freefall = md2_cfg.int2_ff; + val->sleep_change = md2_cfg.int2_sleep_change; + + return ret; +} + +/** + * @} + * + */ + +/** + * @brief Get the status of all the interrupt sources.[get] + * + * @param ctx read / write interface definitions + * @param val Get the status of all the interrupt sources. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_all_sources_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_all_sources_t *val) +{ + lsm6dsv32x_emb_func_status_mainpage_t emb_func_status_mainpage; + lsm6dsv32x_emb_func_exec_status_t emb_func_exec_status; + lsm6dsv32x_fsm_status_mainpage_t fsm_status_mainpage; + lsm6dsv32x_mlc_status_mainpage_t mlc_status_mainpage; + lsm6dsv32x_functions_enable_t functions_enable; + lsm6dsv32x_emb_func_src_t emb_func_src; + lsm6dsv32x_fifo_status2_t fifo_status2; + lsm6dsv32x_all_int_src_t all_int_src; + lsm6dsv32x_wake_up_src_t wake_up_src; + lsm6dsv32x_status_reg_t status_reg; + lsm6dsv32x_d6d_src_t d6d_src; + lsm6dsv32x_tap_src_t tap_src; + lsm6dsv32x_ui_status_reg_ois_t status_reg_ois; + lsm6dsv32x_status_master_t status_shub; + uint8_t buff[8]; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + functions_enable.dis_rst_lir_all_int = PROPERTY_ENABLE; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_STATUS1, (uint8_t *)&buff, 4); + if (ret != 0) + { + return ret; + } + + bytecpy((uint8_t *)&fifo_status2, &buff[1]); + bytecpy((uint8_t *)&all_int_src, &buff[2]); + bytecpy((uint8_t *)&status_reg, &buff[3]); + + val->fifo_ovr = fifo_status2.fifo_ovr_ia; + val->fifo_bdr = fifo_status2.counter_bdr_ia; + val->fifo_full = fifo_status2.fifo_full_ia; + val->fifo_th = fifo_status2.fifo_wtm_ia; + + val->free_fall = all_int_src.ff_ia; + val->wake_up = all_int_src.wu_ia; + val->six_d = all_int_src.d6d_ia; + + val->drdy_xl = status_reg.xlda; + val->drdy_gy = status_reg.gda; + val->drdy_temp = status_reg.tda; + val->drdy_ah_qvar = status_reg.ah_qvarda; + val->drdy_eis = status_reg.gda_eis; + val->drdy_ois = status_reg.ois_drdy; + val->timestamp = status_reg.timestamp_endcount; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + functions_enable.dis_rst_lir_all_int = PROPERTY_DISABLE; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_STATUS_REG_OIS, (uint8_t *)&buff, 8); + if (ret != 0) + { + return ret; + } + + bytecpy((uint8_t *)&status_reg_ois, &buff[0]); + bytecpy((uint8_t *)&wake_up_src, &buff[1]); + bytecpy((uint8_t *)&tap_src, &buff[2]); + bytecpy((uint8_t *)&d6d_src, &buff[3]); + bytecpy((uint8_t *)&emb_func_status_mainpage, &buff[5]); + bytecpy((uint8_t *)&fsm_status_mainpage, &buff[6]); + bytecpy((uint8_t *)&mlc_status_mainpage, &buff[7]); + + val->gy_settling = status_reg_ois.gyro_settling; + val->sleep_change = wake_up_src.sleep_change_ia; + val->wake_up_x = wake_up_src.x_wu; + val->wake_up_y = wake_up_src.y_wu; + val->wake_up_z = wake_up_src.z_wu; + val->sleep_state = wake_up_src.sleep_state; + + val->tap_x = tap_src.x_tap; + val->tap_y = tap_src.y_tap; + val->tap_z = tap_src.z_tap; + val->tap_sign = tap_src.tap_sign; + val->double_tap = tap_src.double_tap; + val->single_tap = tap_src.single_tap; + + val->six_d_zl = d6d_src.zl; + val->six_d_zh = d6d_src.zh; + val->six_d_yl = d6d_src.yl; + val->six_d_yh = d6d_src.yh; + val->six_d_xl = d6d_src.xl; + val->six_d_xh = d6d_src.xh; + + val->step_detector = emb_func_status_mainpage.is_step_det; + val->tilt = emb_func_status_mainpage.is_tilt; + val->sig_mot = emb_func_status_mainpage.is_sigmot; + val->fsm_lc = emb_func_status_mainpage.is_fsm_lc; + + val->fsm1 = fsm_status_mainpage.is_fsm1; + val->fsm2 = fsm_status_mainpage.is_fsm2; + val->fsm3 = fsm_status_mainpage.is_fsm3; + val->fsm4 = fsm_status_mainpage.is_fsm4; + val->fsm5 = fsm_status_mainpage.is_fsm5; + val->fsm6 = fsm_status_mainpage.is_fsm6; + val->fsm7 = fsm_status_mainpage.is_fsm7; + val->fsm8 = fsm_status_mainpage.is_fsm8; + + val->mlc1 = mlc_status_mainpage.is_mlc1; + val->mlc2 = mlc_status_mainpage.is_mlc2; + val->mlc3 = mlc_status_mainpage.is_mlc3; + val->mlc4 = mlc_status_mainpage.is_mlc4; + + /* embedded func */ + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, + 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + + val->emb_func_stand_by = emb_func_exec_status.emb_func_endop; + val->emb_func_time_exceed = emb_func_exec_status.emb_func_exec_ovr; + val->step_count_inc = emb_func_src.stepcounter_bit_set; + val->step_count_overflow = emb_func_src.step_overflow; + val->step_on_delta_time = emb_func_src.step_count_delta_ia; + + val->step_detector = emb_func_src.step_detected; + + /* sensor hub */ + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_STATUS_MASTER_MAINPAGE, (uint8_t *)&status_shub, 1); + if (ret != 0) + { + return ret; + } + + val->sh_endop = status_shub.sens_hub_endop; + val->sh_wr_once = status_shub.wr_once_done; + val->sh_slave3_nack = status_shub.slave3_nack; + val->sh_slave2_nack = status_shub.slave2_nack; + val->sh_slave1_nack = status_shub.slave1_nack; + val->sh_slave0_nack = status_shub.slave0_nack; + + return ret; +} + +int32_t lsm6dsv32x_flag_data_ready_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_data_ready_t *val) +{ + lsm6dsv32x_status_reg_t status; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_STATUS_REG, (uint8_t *)&status, 1); + if (ret != 0) + { + return ret; + } + + val->drdy_xl = status.xlda; + val->drdy_gy = status.gda; + val->drdy_temp = status.tda; + + return ret; +} + +/** + * @brief Mask status bit reset[set] + * + * @param ctx read / write interface definitions + * @param val Mask to prevent status bit being reset + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_int_ack_mask_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + int32_t ret; + + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_INT_ACK_MASK, &val, 1); + + return ret; +} + +/** + * @brief Mask status bit reset[get] + * + * @param ctx read / write interface definitions + * @param val Mask to prevent status bit being reset + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_int_ack_mask_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INT_ACK_MASK, val, 1); + + return ret; +} + +/** + * @brief Temperature data output register[get] + * + * @param ctx read / write interface definitions + * @param val Temperature data output register + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_OUT_TEMP_L, &buff[0], 2); + if (ret != 0) + { + return ret; + } + + *val = (int16_t)buff[1]; + *val = (*val * 256) + (int16_t)buff[0]; + + return ret; +} + +/** + * @brief Angular rate sensor.[get] + * + * @param ctx read / write interface definitions + * @param val Angular rate sensor. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_OUTX_L_G, &buff[0], 6); + if (ret != 0) + { + return ret; + } + + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Angular rate sensor.[get] + * + * @param ctx read / write interface definitions + * @param val OIS Angular rate sensor (thru SPI2). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ois_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SPI2_OUTX_L_G_OIS, &buff[0], 6); + if (ret != 0) + { + return ret; + } + + val[0] = (int16_t)buff[1]; + val[0] = (*val * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (*val * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (*val * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Angular rate sensor for OIS gyro or the EIS gyro channel.[get] + * + * @param ctx read / write interface definitions + * @param val Angular rate sensor for OIS gyro or the EIS gyro channel. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ois_eis_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_OUTX_L_G_OIS_EIS, &buff[0], 6); + if (ret != 0) + { + return ret; + } + + val[0] = (int16_t)buff[1]; + val[0] = (*val * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (*val * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (*val * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Linear acceleration sensor.[get] + * + * @param ctx read / write interface definitions + * @param val Linear acceleration sensor. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_OUTX_L_A, &buff[0], 6); + if (ret != 0) + { + return ret; + } + + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Linear acceleration sensor for Dual channel mode.[get] + * + * @param ctx read / write interface definitions + * @param val Linear acceleration sensor or Dual channel mode. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_OUTX_L_A_OIS_DUALC, &buff[0], 6); + if (ret != 0) + { + return ret; + } + + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief ah_qvar data output register.[get] + * + * @param ctx read / write interface definitions + * @param val ah_qvar data output register. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ah_qvar_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_AH_QVAR_OUT_L, &buff[0], 2); + if (ret != 0) + { + return ret; + } + + *val = (int16_t)buff[1]; + *val = (*val * 256) + (int16_t)buff[0]; + + return ret; +} + +/** + * @brief Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement.[get] + * + * @param ctx read / write interface definitions + * @param val Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val) +{ + lsm6dsv32x_internal_freq_t internal_freq; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INTERNAL_FREQ, (uint8_t *)&internal_freq, 1); + *val = (int8_t)internal_freq.freq_fine; + + return ret; +} + +/** + * @brief Write buffer in a page.[set] + * + * @param ctx read / write interface definitions + * @param val Write buffer in a page. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len) +{ + lsm6dsv32x_page_address_t page_address; + lsm6dsv32x_page_sel_t page_sel; + lsm6dsv32x_page_rw_t page_rw; + uint8_t msb; + uint8_t lsb; + int32_t ret; + uint8_t i ; + + msb = ((uint8_t)(address >> 8) & 0x0FU); + lsb = (uint8_t)address & 0xFFU; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } + + /* set page write */ + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_ENABLE; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } + + /* select page */ + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_SEL, (uint8_t *)&page_sel, 1); + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } + + /* set page addr */ + page_address.page_addr = lsb; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) + { + goto exit; + } + + for (i = 0; ((i < len) && (ret == 0)); i++) + { + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_VALUE, &buf[i], 1); + if (ret != 0) + { + goto exit; + } + + lsb++; + + /* Check if page wrap */ + if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) + { + msb++; + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } + + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } + } + } + + page_sel.page_sel = 0; + page_sel.not_used0 = 1;// Default value + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } + + /* unset page write */ + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1); + +exit: + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @defgroup Common + * @brief This section groups common useful functions. + * @{/ + * + */ + +/** + * @brief Read buffer in a page.[set] + * + * @param ctx read / write interface definitions + * @param val Write buffer in a page. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, + uint8_t len) +{ + lsm6dsv32x_page_address_t page_address; + lsm6dsv32x_page_sel_t page_sel; + lsm6dsv32x_page_rw_t page_rw; + uint8_t msb; + uint8_t lsb; + int32_t ret; + uint8_t i ; + + msb = ((uint8_t)(address >> 8) & 0x0FU); + lsb = (uint8_t)address & 0xFFU; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } + + /* set page write */ + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_ENABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1); + if (ret != 0) + { + goto exit; + } + + /* select page */ + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_SEL, (uint8_t *)&page_sel, 1); + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } + + /* set page addr */ + page_address.page_addr = lsb; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + if (ret != 0) + { + goto exit; + } + + for (i = 0; ((i < len) && (ret == 0)); i++) + { + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_VALUE, &buf[i], 1); + if (ret != 0) + { + goto exit; + } + + lsb++; + + /* Check if page wrap */ + if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) + { + msb++; + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } + + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } + } + } + + page_sel.page_sel = 0; + page_sel.not_used0 = 1;// Default value + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_SEL, (uint8_t *)&page_sel, 1); + if (ret != 0) + { + goto exit; + } + + /* unset page write */ + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1); + +exit: + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable debug mode for embedded functions [set] + * + * @param ctx read / write interface definitions + * @param val 0, 1 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_emb_function_dbg_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_ctrl10_t ctrl10; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL10, (uint8_t *)&ctrl10, 1); + + if (ret == 0) + { + ctrl10.emb_func_debug = val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL10, (uint8_t *)&ctrl10, 1); + } + + return ret; +} + +/** + * @brief Enable debug mode for embedded functions [get] + * + * @param ctx read / write interface definitions + * @param val 0, 1 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_emb_function_dbg_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_ctrl10_t ctrl10; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL10, (uint8_t *)&ctrl10, 1); + if (ret != 0) + { + return ret; + } + + *val = ctrl10.emb_func_debug; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Data ENable (DEN) + * @brief This section groups all the functions concerning + * DEN functionality. + * @{ + * + */ + +/** + * @brief It changes the polarity of INT2 pin input trigger for data enable (DEN) or embedded functions.[set] + * + * @param ctx read / write interface definitions + * @param val DEN_ACT_LOW, DEN_ACT_HIGH, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_den_polarity_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_den_polarity_t val) +{ + lsm6dsv32x_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1); + + if (ret == 0) + { + ctrl4.int2_in_lh = (uint8_t)val & 0x1U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1); + } + + return ret; +} + +/** + * @brief It changes the polarity of INT2 pin input trigger for data enable (DEN) or embedded functions.[get] + * + * @param ctx read / write interface definitions + * @param val DEN_ACT_LOW, DEN_ACT_HIGH, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_den_polarity_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_den_polarity_t *val) +{ + lsm6dsv32x_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl4.int2_in_lh) + { + case LSM6DSV32X_DEN_ACT_LOW: + *val = LSM6DSV32X_DEN_ACT_LOW; + break; + + case LSM6DSV32X_DEN_ACT_HIGH: + *val = LSM6DSV32X_DEN_ACT_HIGH; + break; + + default: + *val = LSM6DSV32X_DEN_ACT_LOW; + break; + } + + return ret; +} + +/** + * @brief Data ENable (DEN) configuration.[set] + * + * @param ctx read / write interface definitions + * @param val Data ENable (DEN) configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_den_conf_set(const stmdev_ctx_t *ctx, lsm6dsv32x_den_conf_t val) +{ + lsm6dsv32x_den_t den; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_DEN, (uint8_t *)&den, 1); + if (ret != 0) + { + return ret; + } + + den.den_z = val.den_z; + den.den_y = val.den_y; + den.den_x = val.den_x; + + den.lvl2_en = (uint8_t)val.mode & 0x1U; + den.lvl1_en = ((uint8_t)val.mode & 0x2U) >> 1; + + if (val.stamp_in_gy_data == PROPERTY_ENABLE && val.stamp_in_xl_data == PROPERTY_ENABLE) + { + den.den_xl_g = PROPERTY_DISABLE; + den.den_xl_en = PROPERTY_ENABLE; + } + else if (val.stamp_in_gy_data == PROPERTY_ENABLE && val.stamp_in_xl_data == PROPERTY_DISABLE) + { + den.den_xl_g = PROPERTY_DISABLE; + den.den_xl_en = PROPERTY_DISABLE; + } + else if (val.stamp_in_gy_data == PROPERTY_DISABLE && val.stamp_in_xl_data == PROPERTY_ENABLE) + { + den.den_xl_g = PROPERTY_ENABLE; + den.den_xl_en = PROPERTY_DISABLE; + } + else + { + den.den_xl_g = PROPERTY_DISABLE; + den.den_xl_en = PROPERTY_DISABLE; + den.den_z = PROPERTY_DISABLE; + den.den_y = PROPERTY_DISABLE; + den.den_x = PROPERTY_DISABLE; + den.lvl2_en = PROPERTY_DISABLE; + den.lvl1_en = PROPERTY_DISABLE; + } + + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_DEN, (uint8_t *)&den, 1); + + return ret; +} + + +/** + * @brief Data ENable (DEN) configuration.[get] + * + * @param ctx read / write interface definitions + * @param val Data ENable (DEN) configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_den_conf_get(const stmdev_ctx_t *ctx, lsm6dsv32x_den_conf_t *val) +{ + lsm6dsv32x_den_t den; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_DEN, (uint8_t *)&den, 1); + if (ret != 0) + { + return ret; + } + + val->den_z = den.den_z; + val->den_y = den.den_y; + val->den_x = den.den_x; + + if ((den.den_x | den.den_y | den.den_z) == PROPERTY_ENABLE) + { + if (den.den_xl_g == PROPERTY_DISABLE && den.den_xl_en == PROPERTY_ENABLE) + { + val->stamp_in_gy_data = PROPERTY_ENABLE; + val->stamp_in_xl_data = PROPERTY_ENABLE; + } + else if (den.den_xl_g == PROPERTY_DISABLE && den.den_xl_en == PROPERTY_DISABLE) + { + val->stamp_in_gy_data = PROPERTY_ENABLE; + val->stamp_in_xl_data = PROPERTY_DISABLE; + } + else // ( (den.den_xl_g & !den.den_xl_en) == PROPERTY_ENABLE ) + { + val->stamp_in_gy_data = PROPERTY_DISABLE; + val->stamp_in_xl_data = PROPERTY_ENABLE; + } + } + else + { + val->stamp_in_gy_data = PROPERTY_DISABLE; + val->stamp_in_xl_data = PROPERTY_DISABLE; + } + + switch ((den.lvl1_en << 1) + den.lvl2_en) + { + case LSM6DSV32X_LEVEL_TRIGGER: + val->mode = LSM6DSV32X_LEVEL_TRIGGER; + break; + + case LSM6DSV32X_LEVEL_LATCHED: + val->mode = LSM6DSV32X_LEVEL_LATCHED; + break; + + default: + val->mode = LSM6DSV32X_DEN_NOT_DEFINED; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Electronic Image Stabilization (EIS) + * @brief Electronic Image Stabilization (EIS) + * @{/ + * + */ + +/** + * @brief Gyroscope full-scale selection for EIS channel. WARNING: 4000dps will be available only if also User Interface chain is set to 4000dps[set] + * + * @param ctx read / write interface definitions + * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_eis_gy_full_scale_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_eis_gy_full_scale_t val) +{ + lsm6dsv32x_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + + if (ret == 0) + { + ctrl_eis.fs_g_eis = (uint8_t)val & 0x7U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + } + + return ret; +} + +/** + * @brief Gyroscope full-scale selection for EIS channel. WARNING: 4000dps will be available only if also User Interface chain is set to 4000dps[get] + * + * @param ctx read / write interface definitions + * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_eis_gy_full_scale_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_eis_gy_full_scale_t *val) +{ + lsm6dsv32x_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl_eis.fs_g_eis) + { + case LSM6DSV32X_EIS_125dps: + *val = LSM6DSV32X_EIS_125dps; + break; + + case LSM6DSV32X_EIS_250dps: + *val = LSM6DSV32X_EIS_250dps; + break; + + case LSM6DSV32X_EIS_500dps: + *val = LSM6DSV32X_EIS_500dps; + break; + + case LSM6DSV32X_EIS_1000dps: + *val = LSM6DSV32X_EIS_1000dps; + break; + + case LSM6DSV32X_EIS_2000dps: + *val = LSM6DSV32X_EIS_2000dps; + break; + + default: + *val = LSM6DSV32X_EIS_125dps; + break; + } + return ret; +} + +/** + * @brief Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI).[set] + * + * @param ctx read / write interface definitions + * @param val Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_eis_gy_on_spi2_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + + if (ret == 0) + { + ctrl_eis.g_eis_on_g_ois_out_reg = val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + } + + return ret; +} + +/** + * @brief Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI).[get] + * + * @param ctx read / write interface definitions + * @param val Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_eis_gy_on_spi2_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + *val = ctrl_eis.g_eis_on_g_ois_out_reg; + + return ret; +} + +/** + * @brief Enables and selects the ODR of the gyroscope EIS channel.[set] + * + * @param ctx read / write interface definitions + * @param val EIS_1920Hz, EIS_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_gy_eis_data_rate_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_gy_eis_data_rate_t val) +{ + lsm6dsv32x_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + + if (ret == 0) + { + ctrl_eis.odr_g_eis = (uint8_t)val & 0x03U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + } + + return ret; +} + +/** + * @brief Enables and selects the ODR of the gyroscope EIS channel.[get] + * + * @param ctx read / write interface definitions + * @param val EIS_1920Hz, EIS_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_gy_eis_data_rate_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_gy_eis_data_rate_t *val) +{ + lsm6dsv32x_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl_eis.odr_g_eis) + { + case LSM6DSV32X_EIS_ODR_OFF: + *val = LSM6DSV32X_EIS_ODR_OFF; + break; + + case LSM6DSV32X_EIS_1920Hz: + *val = LSM6DSV32X_EIS_1920Hz; + break; + + case LSM6DSV32X_EIS_960Hz: + *val = LSM6DSV32X_EIS_960Hz; + break; + + default: + *val = LSM6DSV32X_EIS_1920Hz; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup FIFO + * @brief This section group all the functions concerning the FIFO usage + * @{ + * + */ + +/** + * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[set] + * + * @param ctx read / write interface definitions + * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_fifo_ctrl1_t fifo_ctrl1; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + + if (ret == 0) + { + fifo_ctrl1.wtm = val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + } + + return ret; +} + +/** + * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[get] + * + * @param ctx read / write interface definitions + * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_fifo_ctrl1_t fifo_ctrl1; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + *val = fifo_ctrl1.wtm; + + return ret; +} + +/** + * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[set] + * + * @param ctx read / write interface definitions + * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.xl_dualc_batch_from_fsm = val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[get] + * + * @param ctx read / write interface definitions + * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.xl_dualc_batch_from_fsm; + + return ret; +} + +/** + * @brief It configures the compression algorithm to write non-compressed data at each rate.[set] + * + * @param ctx read / write interface definitions + * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_compress_algo_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_compress_algo_t val) +{ + lsm6dsv32x_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.uncompr_rate = (uint8_t)val & 0x03U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief It configures the compression algorithm to write non-compressed data at each rate.[get] + * + * @param ctx read / write interface definitions + * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_compress_algo_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_compress_algo_t *val) +{ + lsm6dsv32x_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + + switch (fifo_ctrl2.uncompr_rate) + { + case LSM6DSV32X_CMP_DISABLE: + *val = LSM6DSV32X_CMP_DISABLE; + break; + + case LSM6DSV32X_CMP_8_TO_1: + *val = LSM6DSV32X_CMP_8_TO_1; + break; + + case LSM6DSV32X_CMP_16_TO_1: + *val = LSM6DSV32X_CMP_16_TO_1; + break; + + case LSM6DSV32X_CMP_32_TO_1: + *val = LSM6DSV32X_CMP_32_TO_1; + break; + + default: + *val = LSM6DSV32X_CMP_DISABLE; + break; + } + return ret; +} + +/** + * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set] + * + * @param ctx read / write interface definitions + * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.odr_chg_en = val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get] + * + * @param ctx read / write interface definitions + * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, + uint8_t *val) +{ + lsm6dsv32x_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.odr_chg_en; + + return ret; +} + +/** + * @brief Enables/Disables compression algorithm runtime.[set] + * + * @param ctx read / write interface definitions + * @param val Enables/Disables compression algorithm runtime. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, + uint8_t val) +{ + lsm6dsv32x_emb_func_en_b_t emb_func_en_b; + lsm6dsv32x_fifo_ctrl2_t fifo_ctrl2; + + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + fifo_ctrl2.fifo_compr_rt_en = val; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + emb_func_en_b.fifo_compr_en = val; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables/Disables compression algorithm runtime.[get] + * + * @param ctx read / write interface definitions + * @param val Enables/Disables compression algorithm runtime. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, + uint8_t *val) +{ + lsm6dsv32x_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + + *val = fifo_ctrl2.fifo_compr_rt_en; + + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at threshold level.[set] + * + * @param ctx read / write interface definitions + * @param val Sensing chain FIFO stop values memorization at threshold level. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.stop_on_wtm = val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at threshold level.[get] + * + * @param ctx read / write interface definitions + * @param val Sensing chain FIFO stop values memorization at threshold level. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.stop_on_wtm; + + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[set] + * + * @param ctx read / write interface definitions + * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_xl_batch_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_xl_batch_t val) +{ + lsm6dsv32x_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret == 0) + { + fifo_ctrl3.bdr_xl = (uint8_t)val & 0xFu; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + } + + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[get] + * + * @param ctx read / write interface definitions + * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_xl_batch_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_xl_batch_t *val) +{ + lsm6dsv32x_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } + + switch (fifo_ctrl3.bdr_xl) + { + case LSM6DSV32X_XL_NOT_BATCHED: + *val = LSM6DSV32X_XL_NOT_BATCHED; + break; + + case LSM6DSV32X_XL_BATCHED_AT_1Hz875: + *val = LSM6DSV32X_XL_BATCHED_AT_1Hz875; + break; + + case LSM6DSV32X_XL_BATCHED_AT_7Hz5: + *val = LSM6DSV32X_XL_BATCHED_AT_7Hz5; + break; + + case LSM6DSV32X_XL_BATCHED_AT_15Hz: + *val = LSM6DSV32X_XL_BATCHED_AT_15Hz; + break; + + case LSM6DSV32X_XL_BATCHED_AT_30Hz: + *val = LSM6DSV32X_XL_BATCHED_AT_30Hz; + break; + + case LSM6DSV32X_XL_BATCHED_AT_60Hz: + *val = LSM6DSV32X_XL_BATCHED_AT_60Hz; + break; + + case LSM6DSV32X_XL_BATCHED_AT_120Hz: + *val = LSM6DSV32X_XL_BATCHED_AT_120Hz; + break; + + case LSM6DSV32X_XL_BATCHED_AT_240Hz: + *val = LSM6DSV32X_XL_BATCHED_AT_240Hz; + break; + + case LSM6DSV32X_XL_BATCHED_AT_480Hz: + *val = LSM6DSV32X_XL_BATCHED_AT_480Hz; + break; + + case LSM6DSV32X_XL_BATCHED_AT_960Hz: + *val = LSM6DSV32X_XL_BATCHED_AT_960Hz; + break; + + case LSM6DSV32X_XL_BATCHED_AT_1920Hz: + *val = LSM6DSV32X_XL_BATCHED_AT_1920Hz; + break; + + case LSM6DSV32X_XL_BATCHED_AT_3840Hz: + *val = LSM6DSV32X_XL_BATCHED_AT_3840Hz; + break; + + case LSM6DSV32X_XL_BATCHED_AT_7680Hz: + *val = LSM6DSV32X_XL_BATCHED_AT_7680Hz; + break; + + default: + *val = LSM6DSV32X_XL_NOT_BATCHED; + break; + } + + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[set] + * + * @param ctx read / write interface definitions + * @param val GY_NOT_BATCHED, GY_BATCHED_AT_1Hz875, GY_BATCHED_AT_7Hz5, GY_BATCHED_AT_15Hz, GY_BATCHED_AT_30Hz, GY_BATCHED_AT_60Hz, GY_BATCHED_AT_120Hz, GY_BATCHED_AT_240Hz, GY_BATCHED_AT_480Hz, GY_BATCHED_AT_960Hz, GY_BATCHED_AT_1920Hz, GY_BATCHED_AT_3840Hz, GY_BATCHED_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_gy_batch_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_gy_batch_t val) +{ + lsm6dsv32x_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret == 0) + { + fifo_ctrl3.bdr_gy = (uint8_t)val & 0x0Fu; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + } + + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[get] + * + * @param ctx read / write interface definitions + * @param val GY_NOT_BATCHED, GY_BATCHED_AT_1Hz875, GY_BATCHED_AT_7Hz5, GY_BATCHED_AT_15Hz, GY_BATCHED_AT_30Hz, GY_BATCHED_AT_60Hz, GY_BATCHED_AT_120Hz, GY_BATCHED_AT_240Hz, GY_BATCHED_AT_480Hz, GY_BATCHED_AT_960Hz, GY_BATCHED_AT_1920Hz, GY_BATCHED_AT_3840Hz, GY_BATCHED_AT_7680Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_gy_batch_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_gy_batch_t *val) +{ + lsm6dsv32x_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret != 0) + { + return ret; + } + + switch (fifo_ctrl3.bdr_gy) + { + case LSM6DSV32X_GY_NOT_BATCHED: + *val = LSM6DSV32X_GY_NOT_BATCHED; + break; + + case LSM6DSV32X_GY_BATCHED_AT_1Hz875: + *val = LSM6DSV32X_GY_BATCHED_AT_1Hz875; + break; + + case LSM6DSV32X_GY_BATCHED_AT_7Hz5: + *val = LSM6DSV32X_GY_BATCHED_AT_7Hz5; + break; + + case LSM6DSV32X_GY_BATCHED_AT_15Hz: + *val = LSM6DSV32X_GY_BATCHED_AT_15Hz; + break; + + case LSM6DSV32X_GY_BATCHED_AT_30Hz: + *val = LSM6DSV32X_GY_BATCHED_AT_30Hz; + break; + + case LSM6DSV32X_GY_BATCHED_AT_60Hz: + *val = LSM6DSV32X_GY_BATCHED_AT_60Hz; + break; + + case LSM6DSV32X_GY_BATCHED_AT_120Hz: + *val = LSM6DSV32X_GY_BATCHED_AT_120Hz; + break; + + case LSM6DSV32X_GY_BATCHED_AT_240Hz: + *val = LSM6DSV32X_GY_BATCHED_AT_240Hz; + break; + + case LSM6DSV32X_GY_BATCHED_AT_480Hz: + *val = LSM6DSV32X_GY_BATCHED_AT_480Hz; + break; + + case LSM6DSV32X_GY_BATCHED_AT_960Hz: + *val = LSM6DSV32X_GY_BATCHED_AT_960Hz; + break; + + case LSM6DSV32X_GY_BATCHED_AT_1920Hz: + *val = LSM6DSV32X_GY_BATCHED_AT_1920Hz; + break; + + case LSM6DSV32X_GY_BATCHED_AT_3840Hz: + *val = LSM6DSV32X_GY_BATCHED_AT_3840Hz; + break; + + case LSM6DSV32X_GY_BATCHED_AT_7680Hz: + *val = LSM6DSV32X_GY_BATCHED_AT_7680Hz; + break; + + default: + *val = LSM6DSV32X_GY_NOT_BATCHED; + break; + } + return ret; +} + + +/** + * @brief FIFO mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dsv32x_fifo_mode_t val) +{ + lsm6dsv32x_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.fifo_mode = (uint8_t)val & 0x07U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief FIFO mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6dsv32x_fifo_mode_t *val) +{ + lsm6dsv32x_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } + + switch (fifo_ctrl4.fifo_mode) + { + case LSM6DSV32X_BYPASS_MODE: + *val = LSM6DSV32X_BYPASS_MODE; + break; + + case LSM6DSV32X_FIFO_MODE: + *val = LSM6DSV32X_FIFO_MODE; + break; + + case LSM6DSV32X_STREAM_WTM_TO_FULL_MODE: + *val = LSM6DSV32X_STREAM_WTM_TO_FULL_MODE; + break; + + case LSM6DSV32X_STREAM_TO_FIFO_MODE: + *val = LSM6DSV32X_STREAM_TO_FIFO_MODE; + break; + + case LSM6DSV32X_BYPASS_TO_STREAM_MODE: + *val = LSM6DSV32X_BYPASS_TO_STREAM_MODE; + break; + + case LSM6DSV32X_STREAM_MODE: + *val = LSM6DSV32X_STREAM_MODE; + break; + + case LSM6DSV32X_BYPASS_TO_FIFO_MODE: + *val = LSM6DSV32X_BYPASS_TO_FIFO_MODE; + break; + + default: + *val = LSM6DSV32X_BYPASS_MODE; + break; + } + return ret; +} + +/** + * @brief Enables FIFO batching of EIS gyroscope output values.[set] + * + * @param ctx read / write interface definitions + * @param val Enables FIFO batching of EIS gyroscope output values. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_gy_eis_batch_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.g_eis_fifo_en = val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief Enables FIFO batching of EIS gyroscope output values.[get] + * + * @param ctx read / write interface definitions + * @param val Enables FIFO batching of EIS gyroscope output values. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_gy_eis_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + *val = fifo_ctrl4.g_eis_fifo_en; + + return ret; +} + +/** + * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[set] + * + * @param ctx read / write interface definitions + * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_temp_batch_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_temp_batch_t val) +{ + lsm6dsv32x_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.odr_t_batch = (uint8_t)val & 0x03U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[get] + * + * @param ctx read / write interface definitions + * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_temp_batch_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_temp_batch_t *val) +{ + lsm6dsv32x_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } + + switch (fifo_ctrl4.odr_t_batch) + { + case LSM6DSV32X_TEMP_NOT_BATCHED: + *val = LSM6DSV32X_TEMP_NOT_BATCHED; + break; + + case LSM6DSV32X_TEMP_BATCHED_AT_1Hz875: + *val = LSM6DSV32X_TEMP_BATCHED_AT_1Hz875; + break; + + case LSM6DSV32X_TEMP_BATCHED_AT_15Hz: + *val = LSM6DSV32X_TEMP_BATCHED_AT_15Hz; + break; + + case LSM6DSV32X_TEMP_BATCHED_AT_60Hz: + *val = LSM6DSV32X_TEMP_BATCHED_AT_60Hz; + break; + + default: + *val = LSM6DSV32X_TEMP_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[set] + * + * @param ctx read / write interface definitions + * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_timestamp_batch_t val) +{ + lsm6dsv32x_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.dec_ts_batch = (uint8_t)val & 0x03U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[get] + * + * @param ctx read / write interface definitions + * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_timestamp_batch_t *val) +{ + lsm6dsv32x_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret != 0) + { + return ret; + } + + switch (fifo_ctrl4.dec_ts_batch) + { + case LSM6DSV32X_TMSTMP_NOT_BATCHED: + *val = LSM6DSV32X_TMSTMP_NOT_BATCHED; + break; + + case LSM6DSV32X_TMSTMP_DEC_1: + *val = LSM6DSV32X_TMSTMP_DEC_1; + break; + + case LSM6DSV32X_TMSTMP_DEC_8: + *val = LSM6DSV32X_TMSTMP_DEC_8; + break; + + case LSM6DSV32X_TMSTMP_DEC_32: + *val = LSM6DSV32X_TMSTMP_DEC_32; + break; + + default: + *val = LSM6DSV32X_TMSTMP_NOT_BATCHED; + break; + } + + return ret; +} + +/** + * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[set] + * + * @param ctx read / write interface definitions + * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx, + uint16_t val) +{ + lsm6dsv32x_counter_bdr_reg1_t counter_bdr_reg1; + lsm6dsv32x_counter_bdr_reg2_t counter_bdr_reg2; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + + if (ret == 0) + { + counter_bdr_reg2.cnt_bdr_th = (uint8_t)val & 0xFFU; + counter_bdr_reg1.cnt_bdr_th = (uint8_t)(val >> 8) & 0x3U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_COUNTER_BDR_REG2, (uint8_t *)&counter_bdr_reg2, 1); + } + + return ret; +} + +/** + * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[get] + * + * @param ctx read / write interface definitions + * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx, + uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_COUNTER_BDR_REG1, &buff[0], 2); + if (ret != 0) + { + return ret; + } + + *val = (uint16_t)buff[0] & 0x3U; + *val = (*val * 256U) + (uint16_t)buff[1]; + + return ret; +} + +/** + * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope and EIS gyroscope.[set] + * + * @param ctx read / write interface definitions + * @param val XL_BATCH_EVENT, GY_BATCH_EVENT, GY_EIS_BATCH_EVENT, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_batch_cnt_event_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_batch_cnt_event_t val) +{ + lsm6dsv32x_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret == 0) + { + counter_bdr_reg1.trig_counter_bdr = (uint8_t)val & 0x03U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + } + + return ret; +} + +/** + * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope and EIS gyroscope.[get] + * + * @param ctx read / write interface definitions + * @param val XL_BATCH_EVENT, GY_BATCH_EVENT, GY_EIS_BATCH_EVENT, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_batch_cnt_event_t *val) +{ + lsm6dsv32x_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret != 0) + { + return ret; + } + + switch (counter_bdr_reg1.trig_counter_bdr) + { + case LSM6DSV32X_XL_BATCH_EVENT: + *val = LSM6DSV32X_XL_BATCH_EVENT; + break; + + case LSM6DSV32X_GY_BATCH_EVENT: + *val = LSM6DSV32X_GY_BATCH_EVENT; + break; + + case LSM6DSV32X_GY_EIS_BATCH_EVENT: + *val = LSM6DSV32X_GY_EIS_BATCH_EVENT; + break; + + default: + *val = LSM6DSV32X_XL_BATCH_EVENT; + break; + } + + return ret; +} + +int32_t lsm6dsv32x_fifo_status_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_status_t *val) +{ + uint8_t buff[2]; + lsm6dsv32x_fifo_status2_t status; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_STATUS1, (uint8_t *)&buff[0], 2); + if (ret != 0) + { + return ret; + } + + bytecpy((uint8_t *)&status, &buff[1]); + + val->fifo_bdr = status.counter_bdr_ia; + val->fifo_ovr = status.fifo_ovr_ia; + val->fifo_full = status.fifo_full_ia; + val->fifo_th = status.fifo_wtm_ia; + + val->fifo_level = (uint16_t)buff[1] & 0x01U; + val->fifo_level = (val->fifo_level * 256U) + buff[0]; + + return ret; +} + + +/** + * @brief FIFO data output[get] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv32x_fifo_out_raw_t + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_out_raw_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_out_raw_t *val) +{ + lsm6dsv32x_fifo_data_out_tag_t fifo_data_out_tag; + uint8_t buff[7]; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_DATA_OUT_TAG, buff, 7); + if (ret != 0) + { + return ret; + } + + bytecpy((uint8_t *)&fifo_data_out_tag, &buff[0]); + + switch (fifo_data_out_tag.tag_sensor) + { + case LSM6DSV32X_FIFO_EMPTY: + val->tag = LSM6DSV32X_FIFO_EMPTY; + break; + + case LSM6DSV32X_GY_NC_TAG: + val->tag = LSM6DSV32X_GY_NC_TAG; + break; + + case LSM6DSV32X_XL_NC_TAG: + val->tag = LSM6DSV32X_XL_NC_TAG; + break; + + case LSM6DSV32X_TIMESTAMP_TAG: + val->tag = LSM6DSV32X_TIMESTAMP_TAG; + break; + + case LSM6DSV32X_TEMPERATURE_TAG: + val->tag = LSM6DSV32X_TEMPERATURE_TAG; + break; + + case LSM6DSV32X_CFG_CHANGE_TAG: + val->tag = LSM6DSV32X_CFG_CHANGE_TAG; + break; + + case LSM6DSV32X_XL_NC_T_2_TAG: + val->tag = LSM6DSV32X_XL_NC_T_2_TAG; + break; + + case LSM6DSV32X_XL_NC_T_1_TAG: + val->tag = LSM6DSV32X_XL_NC_T_1_TAG; + break; + + case LSM6DSV32X_XL_2XC_TAG: + val->tag = LSM6DSV32X_XL_2XC_TAG; + break; + + case LSM6DSV32X_XL_3XC_TAG: + val->tag = LSM6DSV32X_XL_3XC_TAG; + break; + + case LSM6DSV32X_GY_NC_T_2_TAG: + val->tag = LSM6DSV32X_GY_NC_T_2_TAG; + break; + + case LSM6DSV32X_GY_NC_T_1_TAG: + val->tag = LSM6DSV32X_GY_NC_T_1_TAG; + break; + + case LSM6DSV32X_GY_2XC_TAG: + val->tag = LSM6DSV32X_GY_2XC_TAG; + break; + + case LSM6DSV32X_GY_3XC_TAG: + val->tag = LSM6DSV32X_GY_3XC_TAG; + break; + + case LSM6DSV32X_SENSORHUB_SLAVE0_TAG: + val->tag = LSM6DSV32X_SENSORHUB_SLAVE0_TAG; + break; + + case LSM6DSV32X_SENSORHUB_SLAVE1_TAG: + val->tag = LSM6DSV32X_SENSORHUB_SLAVE1_TAG; + break; + + case LSM6DSV32X_SENSORHUB_SLAVE2_TAG: + val->tag = LSM6DSV32X_SENSORHUB_SLAVE2_TAG; + break; + + case LSM6DSV32X_SENSORHUB_SLAVE3_TAG: + val->tag = LSM6DSV32X_SENSORHUB_SLAVE3_TAG; + break; + + case LSM6DSV32X_STEP_COUNTER_TAG: + val->tag = LSM6DSV32X_STEP_COUNTER_TAG; + break; + + case LSM6DSV32X_SFLP_GAME_ROTATION_VECTOR_TAG: + val->tag = LSM6DSV32X_SFLP_GAME_ROTATION_VECTOR_TAG; + break; + + case LSM6DSV32X_SFLP_GYROSCOPE_BIAS_TAG: + val->tag = LSM6DSV32X_SFLP_GYROSCOPE_BIAS_TAG; + break; + + case LSM6DSV32X_SFLP_GRAVITY_VECTOR_TAG: + val->tag = LSM6DSV32X_SFLP_GRAVITY_VECTOR_TAG; + break; + + case LSM6DSV32X_SENSORHUB_NACK_TAG: + val->tag = LSM6DSV32X_SENSORHUB_NACK_TAG; + break; + + case LSM6DSV32X_MLC_RESULT_TAG: + val->tag = LSM6DSV32X_MLC_RESULT_TAG; + break; + + case LSM6DSV32X_MLC_FILTER: + val->tag = LSM6DSV32X_MLC_FILTER; + break; + + case LSM6DSV32X_MLC_FEATURE: + val->tag = LSM6DSV32X_MLC_FEATURE; + break; + + case LSM6DSV32X_XL_DUAL_CORE: + val->tag = LSM6DSV32X_XL_DUAL_CORE; + break; + + case LSM6DSV32X_GY_ENHANCED_EIS: + val->tag = LSM6DSV32X_GY_ENHANCED_EIS; + break; + + default: + val->tag = LSM6DSV32X_FIFO_EMPTY; + break; + } + + val->cnt = fifo_data_out_tag.tag_cnt; + + val->data[0] = buff[1]; + val->data[1] = buff[2]; + val->data[2] = buff[3]; + val->data[3] = buff[4]; + val->data[4] = buff[5]; + val->data[5] = buff[6]; + + return ret; +} + +/** + * @brief Batching in FIFO buffer of step counter value.[set] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of step counter value. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + emb_func_fifo_en_a.step_counter_fifo_en = val; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of step counter value.[get] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of step counter value. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } + + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + *val = emb_func_fifo_en_a.step_counter_fifo_en; + + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of machine learning core results.[set] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of machine learning core results. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_mlc_batch_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + emb_func_fifo_en_a.mlc_fifo_en = val; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of machine learning core results.[get] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of machine learning core results. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_mlc_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + *val = emb_func_fifo_en_a.mlc_fifo_en; + + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables batching in FIFO buffer of machine learning core filters and features.[set] + * + * @param ctx read / write interface definitions + * @param val Enables batching in FIFO buffer of machine learning core filters and features. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_mlc_filt_batch_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_emb_func_fifo_en_b_t emb_func_fifo_en_b; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + emb_func_fifo_en_b.mlc_filter_feature_fifo_en = val; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables batching in FIFO buffer of machine learning core filters and features.[get] + * + * @param ctx read / write interface definitions + * @param val Enables batching in FIFO buffer of machine learning core filters and features. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_mlc_filt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_emb_func_fifo_en_b_t emb_func_fifo_en_b; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + *val = emb_func_fifo_en_b.mlc_filter_feature_fifo_en; + + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable FIFO data batching of slave idx.[set] + * + * @param ctx read / write interface definitions + * @param val Enable FIFO data batching of slave idx. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_sh_batch_slave_set(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t val) +{ + lsm6dsv32x_slv0_config_t slv_config; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1); + slv_config.batch_ext_sens_0_en = val; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1); + + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable FIFO data batching of slave idx.[get] + * + * @param ctx read / write interface definitions + * @param val Enable FIFO data batching of slave idx. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_sh_batch_slave_get(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t *val) +{ + lsm6dsv32x_slv0_config_t slv_config; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1); + *val = slv_config.batch_ext_sens_0_en; + + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of SFLP.[set] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of SFLP values. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_sflp_batch_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_sflp_raw_t val) +{ + lsm6dsv32x_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + emb_func_fifo_en_a.sflp_game_fifo_en = val.game_rotation; + emb_func_fifo_en_a.sflp_gravity_fifo_en = val.gravity; + emb_func_fifo_en_a.sflp_gbias_fifo_en = val.gbias; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A, + (uint8_t *)&emb_func_fifo_en_a, 1); + } + + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of SFLP.[get] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of SFLP values. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fifo_sflp_batch_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_sflp_raw_t *val) +{ + lsm6dsv32x_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + + val->game_rotation = emb_func_fifo_en_a.sflp_game_fifo_en; + val->gravity = emb_func_fifo_en_a.sflp_gravity_fifo_en; + val->gbias = emb_func_fifo_en_a.sflp_gbias_fifo_en; + } + + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Filters + * @brief This section group all the functions concerning the + * filters configuration + * @{ + * + */ + +/** + * @brief Protocol anti-spike filters.[set] + * + * @param ctx read / write interface definitions + * @param val AUTO, ALWAYS_ACTIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_anti_spike_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_anti_spike_t val) +{ + lsm6dsv32x_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1); + + if (ret == 0) + { + if_cfg.asf_ctrl = (uint8_t)val & 0x01U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Protocol anti-spike filters.[get] + * + * @param ctx read / write interface definitions + * @param val AUTO, ALWAYS_ACTIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_anti_spike_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_anti_spike_t *val) +{ + lsm6dsv32x_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + + switch (if_cfg.asf_ctrl) + { + case LSM6DSV32X_AUTO: + *val = LSM6DSV32X_AUTO; + break; + + case LSM6DSV32X_ALWAYS_ACTIVE: + *val = LSM6DSV32X_ALWAYS_ACTIVE; + break; + + default: + *val = LSM6DSV32X_AUTO; + break; + } + + return ret; +} + +/** + * @brief It masks DRDY and Interrupts RQ until filter settling ends.[set] + * + * @param ctx read / write interface definitions + * @param val It masks DRDY and Interrupts RQ until filter settling ends. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_settling_mask_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_settling_mask_t val) +{ + lsm6dsv32x_emb_func_cfg_t emb_func_cfg; + lsm6dsv32x_ui_int_ois_t ui_int_ois; + lsm6dsv32x_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1); + ctrl4.drdy_mask = val.drdy; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + emb_func_cfg.emb_func_irq_mask_xl_settl = val.irq_xl; + emb_func_cfg.emb_func_irq_mask_g_settl = val.irq_g; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1); + ui_int_ois.drdy_mask_ois = val.ois_drdy; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1); + + return ret; +} + +/** + * @brief It masks DRDY and Interrupts RQ until filter settling ends.[get] + * + * @param ctx read / write interface definitions + * @param val It masks DRDY and Interrupts RQ until filter settling ends. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_settling_mask_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_settling_mask_t *val) +{ + lsm6dsv32x_emb_func_cfg_t emb_func_cfg; + lsm6dsv32x_ui_int_ois_t ui_int_ois; + lsm6dsv32x_ctrl4_t ctrl4; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1); + + val->irq_xl = emb_func_cfg.emb_func_irq_mask_xl_settl; + val->irq_g = emb_func_cfg.emb_func_irq_mask_g_settl; + val->drdy = ctrl4.drdy_mask; + + return ret; +} + +/** + * @brief It masks DRDY and Interrupts RQ until filter settling ends.[set] + * + * @param ctx read / write interface definitions + * @param val It masks DRDY and Interrupts RQ until filter settling ends from OIS interface. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_ois_settling_mask_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_ois_settling_mask_t val) +{ + lsm6dsv32x_spi2_int_ois_t spi2_int_ois; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + + if (ret == 0) + { + spi2_int_ois.drdy_mask_ois = val.ois_drdy; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + } + + return ret; +} + +/** + * @brief It masks DRDY and Interrupts RQ until filter settling ends.[get] + * + * @param ctx read / write interface definitions + * @param val It masks DRDY and Interrupts RQ until filter settling ends. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_ois_settling_mask_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_ois_settling_mask_t *val) +{ + + lsm6dsv32x_spi2_int_ois_t spi2_int_ois; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); + val->ois_drdy = spi2_int_ois.drdy_mask_ois; + + return ret; +} + +/** + * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[set] + * + * @param ctx read / write interface definitions + * @param val GY_ULTRA_LIGHT, GY_VERY_LIGHT, GY_LIGHT, GY_MEDIUM, GY_STRONG, GY_VERY_STRONG, GY_AGGRESSIVE, GY_XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_gy_lp1_bandwidth_t val) +{ + lsm6dsv32x_ctrl6_t ctrl6; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL6, (uint8_t *)&ctrl6, 1); + if (ret == 0) + { + ctrl6.lpf1_g_bw = (uint8_t)val & 0x0Fu; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL6, (uint8_t *)&ctrl6, 1); + } + + return ret; +} + +/** + * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[get] + * + * @param ctx read / write interface definitions + * @param val GY_ULTRA_LIGHT, GY_VERY_LIGHT, GY_LIGHT, GY_MEDIUM, GY_STRONG, GY_VERY_STRONG, GY_AGGRESSIVE, GY_XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_gy_lp1_bandwidth_t *val) +{ + lsm6dsv32x_ctrl6_t ctrl6; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL6, (uint8_t *)&ctrl6, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl6.lpf1_g_bw) + { + case LSM6DSV32X_GY_ULTRA_LIGHT: + *val = LSM6DSV32X_GY_ULTRA_LIGHT; + break; + + case LSM6DSV32X_GY_VERY_LIGHT: + *val = LSM6DSV32X_GY_VERY_LIGHT; + break; + + case LSM6DSV32X_GY_LIGHT: + *val = LSM6DSV32X_GY_LIGHT; + break; + + case LSM6DSV32X_GY_MEDIUM: + *val = LSM6DSV32X_GY_MEDIUM; + break; + + case LSM6DSV32X_GY_STRONG: + *val = LSM6DSV32X_GY_STRONG; + break; + + case LSM6DSV32X_GY_VERY_STRONG: + *val = LSM6DSV32X_GY_VERY_STRONG; + break; + + case LSM6DSV32X_GY_AGGRESSIVE: + *val = LSM6DSV32X_GY_AGGRESSIVE; + break; + + case LSM6DSV32X_GY_XTREME: + *val = LSM6DSV32X_GY_XTREME; + break; + + default: + *val = LSM6DSV32X_GY_ULTRA_LIGHT; + break; + } + + return ret; +} + +/** + * @brief It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.[set] + * + * @param ctx read / write interface definitions + * @param val It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_gy_lp1_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_ctrl7_t ctrl7; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret == 0) + { + ctrl7.lpf1_g_en = val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL7, (uint8_t *)&ctrl7, 1); + } + + return ret; +} + + +/** + * @brief It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.[get] + * + * @param ctx read / write interface definitions + * @param val It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_ctrl7_t ctrl7; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL7, (uint8_t *)&ctrl7, 1); + *val = ctrl7.lpf1_g_en; + + return ret; +} + +/** + * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[set] + * + * @param ctx read / write interface definitions + * @param val XL_ULTRA_LIGHT, XL_VERY_LIGHT, XL_LIGHT, XL_MEDIUM, XL_STRONG, XL_VERY_STRONG, XL_AGGRESSIVE, XL_XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_xl_lp2_bandwidth_t val) +{ + lsm6dsv32x_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret == 0) + { + ctrl8.hp_lpf2_xl_bw = (uint8_t)val & 0x07U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL8, (uint8_t *)&ctrl8, 1); + } + + return ret; +} + +/** + * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[get] + * + * @param ctx read / write interface definitions + * @param val XL_ULTRA_LIGHT, XL_VERY_LIGHT, XL_LIGHT, XL_MEDIUM, XL_STRONG, XL_VERY_STRONG, XL_AGGRESSIVE, XL_XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_xl_lp2_bandwidth_t *val) +{ + lsm6dsv32x_ctrl8_t ctrl8; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl8.hp_lpf2_xl_bw) + { + case LSM6DSV32X_XL_ULTRA_LIGHT: + *val = LSM6DSV32X_XL_ULTRA_LIGHT; + break; + + case LSM6DSV32X_XL_VERY_LIGHT: + *val = LSM6DSV32X_XL_VERY_LIGHT; + break; + + case LSM6DSV32X_XL_LIGHT: + *val = LSM6DSV32X_XL_LIGHT; + break; + + case LSM6DSV32X_XL_MEDIUM: + *val = LSM6DSV32X_XL_MEDIUM; + break; + + case LSM6DSV32X_XL_STRONG: + *val = LSM6DSV32X_XL_STRONG; + break; + + case LSM6DSV32X_XL_VERY_STRONG: + *val = LSM6DSV32X_XL_VERY_STRONG; + break; + + case LSM6DSV32X_XL_AGGRESSIVE: + *val = LSM6DSV32X_XL_AGGRESSIVE; + break; + + case LSM6DSV32X_XL_XTREME: + *val = LSM6DSV32X_XL_XTREME; + break; + + default: + *val = LSM6DSV32X_XL_ULTRA_LIGHT; + break; + } + + return ret; +} + +/** + * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[set] + * + * @param ctx read / write interface definitions + * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_xl_lp2_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.lpf2_xl_en = val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[get] + * + * @param ctx read / write interface definitions + * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.lpf2_xl_en; + + return ret; +} + +/** + * @brief Accelerometer slope filter / high-pass filter selection.[set] + * + * @param ctx read / write interface definitions + * @param val Accelerometer slope filter / high-pass filter selection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_xl_hp_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.hp_slope_xl_en = val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Accelerometer slope filter / high-pass filter selection.[get] + * + * @param ctx read / write interface definitions + * @param val Accelerometer slope filter / high-pass filter selection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.hp_slope_xl_en; + + return ret; +} + +/** + * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[set] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.xl_fastsettl_mode = val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[get] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.xl_fastsettl_mode; + + return ret; +} + +/** + * @brief Accelerometer high-pass filter mode.[set] + * + * @param ctx read / write interface definitions + * @param val HP_MD_NORMAL, HP_MD_REFERENCE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_xl_hp_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_xl_hp_mode_t val) +{ + lsm6dsv32x_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.hp_ref_mode_xl = (uint8_t)val & 0x01U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Accelerometer high-pass filter mode.[get] + * + * @param ctx read / write interface definitions + * @param val HP_MD_NORMAL, HP_MD_REFERENCE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_xl_hp_mode_t *val) +{ + lsm6dsv32x_ctrl9_t ctrl9; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl9.hp_ref_mode_xl) + { + case LSM6DSV32X_HP_MD_NORMAL: + *val = LSM6DSV32X_HP_MD_NORMAL; + break; + + case LSM6DSV32X_HP_MD_REFERENCE: + *val = LSM6DSV32X_HP_MD_REFERENCE; + break; + + default: + *val = LSM6DSV32X_HP_MD_NORMAL; + break; + } + + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[set] + * + * @param ctx read / write interface definitions + * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS, WK_FEED_LP_WITH_OFFSET, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_wkup_act_feed_t val) +{ + lsm6dsv32x_wake_up_ths_t wake_up_ths; + lsm6dsv32x_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + + tap_cfg0.slope_fds = (uint8_t)val & 0x01U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + + wake_up_ths.usr_off_on_wu = ((uint8_t)val & 0x02U) >> 1; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[get] + * + * @param ctx read / write interface definitions + * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS, WK_FEED_LP_WITH_OFFSET, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_wkup_act_feed_t *val) +{ + lsm6dsv32x_wake_up_ths_t wake_up_ths; + lsm6dsv32x_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + + switch ((wake_up_ths.usr_off_on_wu << 1) + tap_cfg0.slope_fds) + { + case LSM6DSV32X_WK_FEED_SLOPE: + *val = LSM6DSV32X_WK_FEED_SLOPE; + break; + + case LSM6DSV32X_WK_FEED_HIGH_PASS: + *val = LSM6DSV32X_WK_FEED_HIGH_PASS; + break; + + case LSM6DSV32X_WK_FEED_LP_WITH_OFFSET: + *val = LSM6DSV32X_WK_FEED_LP_WITH_OFFSET; + break; + + default: + *val = LSM6DSV32X_WK_FEED_SLOPE; + break; + } + + return ret; +} + +/** + * @brief Mask hw function triggers when xl is settling.[set] + * + * @param ctx read / write interface definitions + * @param val 0 or 1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_mask_trigger_xl_settl_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + + if (ret == 0) + { + tap_cfg0.hw_func_mask_xl_settl = val & 0x01U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + return ret; +} + +/** + * @brief Mask hw function triggers when xl is settling.[get] + * + * @param ctx read / write interface definitions + * @param val 0 or 1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + *val = tap_cfg0.hw_func_mask_xl_settl; + + return ret; +} + +/** + * @brief LPF2 filter on 6D (sixd) function selection.[set] + * + * @param ctx read / write interface definitions + * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_sixd_feed_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_sixd_feed_t val) +{ + lsm6dsv32x_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + + if (ret == 0) + { + tap_cfg0.low_pass_on_6d = (uint8_t)val & 0x01U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + return ret; +} + +/** + * @brief LPF2 filter on 6D (sixd) function selection.[get] + * + * @param ctx read / write interface definitions + * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_sixd_feed_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_sixd_feed_t *val) +{ + lsm6dsv32x_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + + switch (tap_cfg0.low_pass_on_6d) + { + case LSM6DSV32X_SIXD_FEED_ODR_DIV_2: + *val = LSM6DSV32X_SIXD_FEED_ODR_DIV_2; + break; + + case LSM6DSV32X_SIXD_FEED_LOW_PASS: + *val = LSM6DSV32X_SIXD_FEED_LOW_PASS; + break; + + default: + *val = LSM6DSV32X_SIXD_FEED_ODR_DIV_2; + break; + } + + return ret; +} + +/** + * @brief Gyroscope digital LPF_EIS filter bandwidth selection.[set] + * + * @param ctx read / write interface definitions + * @param val EIS_LP_NORMAL, EIS_LP_LIGHT, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_gy_eis_lp_bandwidth_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_gy_eis_lp_bandwidth_t val) +{ + lsm6dsv32x_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + + if (ret == 0) + { + ctrl_eis.lpf_g_eis_bw = (uint8_t)val & 0x01U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + } + + return ret; +} + +/** + * @brief Gyroscope digital LPF_EIS filter bandwidth selection.[get] + * + * @param ctx read / write interface definitions + * @param val EIS_LP_NORMAL, EIS_LP_LIGHT, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_gy_eis_lp_bandwidth_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_gy_eis_lp_bandwidth_t *val) +{ + lsm6dsv32x_ctrl_eis_t ctrl_eis; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl_eis.lpf_g_eis_bw) + { + case LSM6DSV32X_EIS_LP_NORMAL: + *val = LSM6DSV32X_EIS_LP_NORMAL; + break; + + case LSM6DSV32X_EIS_LP_LIGHT: + *val = LSM6DSV32X_EIS_LP_LIGHT; + break; + + default: + *val = LSM6DSV32X_EIS_LP_NORMAL; + break; + } + + return ret; +} + +/** + * @brief Gyroscope OIS digital LPF1 filter bandwidth selection. This function works also on OIS interface (SPI2_CTRL2_OIS = UI_CTRL2_OIS).[set] + * + * @param ctx read / write interface definitions + * @param val OIS_GY_LP_NORMAL, OIS_GY_LP_STRONG, OIS_GY_LP_AGGRESSIVE, OIS_GY_LP_LIGHT, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_gy_ois_lp_bandwidth_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_gy_ois_lp_bandwidth_t val) +{ + lsm6dsv32x_ui_ctrl2_ois_t ui_ctrl2_ois; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); + + if (ret == 0) + { + ui_ctrl2_ois.lpf1_g_ois_bw = (uint8_t)val & 0x03U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); + } + + return ret; +} + +/** + * @brief Gyroscope OIS digital LPF1 filter bandwidth selection. This function works also on OIS interface (SPI2_CTRL2_OIS = UI_CTRL2_OIS).[get] + * + * @param ctx read / write interface definitions + * @param val OIS_GY_LP_NORMAL, OIS_GY_LP_STRONG, OIS_GY_LP_AGGRESSIVE, OIS_GY_LP_LIGHT, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_gy_ois_lp_bandwidth_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_gy_ois_lp_bandwidth_t *val) +{ + + lsm6dsv32x_ui_ctrl2_ois_t ui_ctrl2_ois; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); + if (ret != 0) + { + return ret; + } + + switch (ui_ctrl2_ois.lpf1_g_ois_bw) + { + case LSM6DSV32X_OIS_GY_LP_NORMAL: + *val = LSM6DSV32X_OIS_GY_LP_NORMAL; + break; + + case LSM6DSV32X_OIS_GY_LP_STRONG: + *val = LSM6DSV32X_OIS_GY_LP_STRONG; + break; + + case LSM6DSV32X_OIS_GY_LP_AGGRESSIVE: + *val = LSM6DSV32X_OIS_GY_LP_AGGRESSIVE; + break; + + case LSM6DSV32X_OIS_GY_LP_LIGHT: + *val = LSM6DSV32X_OIS_GY_LP_LIGHT; + break; + + default: + *val = LSM6DSV32X_OIS_GY_LP_NORMAL; + break; + } + + return ret; +} + +/** + * @brief Selects accelerometer OIS channel bandwidth. This function works also on OIS interface (SPI2_CTRL3_OIS = UI_CTRL3_OIS).[set] + * + * @param ctx read / write interface definitions + * @param val OIS_XL_LP_ULTRA_LIGHT, OIS_XL_LP_VERY_LIGHT, OIS_XL_LP_LIGHT, OIS_XL_LP_NORMAL, OIS_XL_LP_STRONG, OIS_XL_LP_VERY_STRONG, OIS_XL_LP_AGGRESSIVE, OIS_XL_LP_XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_xl_ois_lp_bandwidth_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_xl_ois_lp_bandwidth_t val) +{ + lsm6dsv32x_ui_ctrl3_ois_t ui_ctrl3_ois; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); + + if (ret == 0) + { + ui_ctrl3_ois.lpf_xl_ois_bw = (uint8_t)val & 0x07U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); + } + + return ret; +} + +/** + * @brief Selects accelerometer OIS channel bandwidth. This function works also on OIS interface (SPI2_CTRL3_OIS = UI_CTRL3_OIS).[get] + * + * @param ctx read / write interface definitions + * @param val OIS_XL_LP_ULTRA_LIGHT, OIS_XL_LP_VERY_LIGHT, OIS_XL_LP_LIGHT, OIS_XL_LP_NORMAL, OIS_XL_LP_STRONG, OIS_XL_LP_VERY_STRONG, OIS_XL_LP_AGGRESSIVE, OIS_XL_LP_XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_filt_xl_ois_lp_bandwidth_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_xl_ois_lp_bandwidth_t *val) +{ + lsm6dsv32x_ui_ctrl3_ois_t ui_ctrl3_ois; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); + if (ret != 0) + { + return ret; + } + + switch (ui_ctrl3_ois.lpf_xl_ois_bw) + { + case LSM6DSV32X_OIS_XL_LP_ULTRA_LIGHT: + *val = LSM6DSV32X_OIS_XL_LP_ULTRA_LIGHT; + break; + + case LSM6DSV32X_OIS_XL_LP_VERY_LIGHT: + *val = LSM6DSV32X_OIS_XL_LP_VERY_LIGHT; + break; + + case LSM6DSV32X_OIS_XL_LP_LIGHT: + *val = LSM6DSV32X_OIS_XL_LP_LIGHT; + break; + + case LSM6DSV32X_OIS_XL_LP_NORMAL: + *val = LSM6DSV32X_OIS_XL_LP_NORMAL; + break; + + case LSM6DSV32X_OIS_XL_LP_STRONG: + *val = LSM6DSV32X_OIS_XL_LP_STRONG; + break; + + case LSM6DSV32X_OIS_XL_LP_VERY_STRONG: + *val = LSM6DSV32X_OIS_XL_LP_VERY_STRONG; + break; + + case LSM6DSV32X_OIS_XL_LP_AGGRESSIVE: + *val = LSM6DSV32X_OIS_XL_LP_AGGRESSIVE; + break; + + case LSM6DSV32X_OIS_XL_LP_XTREME: + *val = LSM6DSV32X_OIS_XL_LP_XTREME; + break; + + default: + *val = LSM6DSV32X_OIS_XL_LP_ULTRA_LIGHT; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Finite State Machine (FSM) + * @brief This section groups all the functions that manage the + * state_machine. + * @{ + * + */ + +/** + * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[set] + * + * @param ctx read / write interface definitions + * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_permission_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_fsm_permission_t val) +{ + lsm6dsv32x_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + if (ret == 0) + { + func_cfg_access.fsm_wr_ctrl_en = (uint8_t)val & 0x01U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[get] + * + * @param ctx read / write interface definitions + * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_permission_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fsm_permission_t *val) +{ + lsm6dsv32x_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } + + switch (func_cfg_access.fsm_wr_ctrl_en) + { + case LSM6DSV32X_PROTECT_CTRL_REGS: + *val = LSM6DSV32X_PROTECT_CTRL_REGS; + break; + + case LSM6DSV32X_WRITE_CTRL_REG: + *val = LSM6DSV32X_WRITE_CTRL_REG; + break; + + default: + *val = LSM6DSV32X_PROTECT_CTRL_REGS; + break; + } + + return ret; +} + +/** + * @brief Get the FSM permission status + * + * @param ctx read / write interface definitions + * @param val 0: All reg writable from std if - 1: some regs are under FSM control. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_permission_status(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_ctrl_status_t ctrl_status; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL_STATUS, (uint8_t *)&ctrl_status, 1); + + *val = ctrl_status.fsm_wr_ctrl_status; + + return ret; +} + +/** + * @brief Enable Finite State Machine (FSM) feature.[set] + * + * @param ctx read / write interface definitions + * @param val Enable Finite State Machine (FSM) feature. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_mode_set(const stmdev_ctx_t *ctx, lsm6dsv32x_fsm_mode_t val) +{ + lsm6dsv32x_emb_func_en_b_t emb_func_en_b; + lsm6dsv32x_fsm_enable_t fsm_enable; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + if (ret != 0) + { + goto exit; + } + + if ((val.fsm1_en | val.fsm2_en | val.fsm3_en | val.fsm4_en + | val.fsm5_en | val.fsm6_en | val.fsm7_en | val.fsm8_en) == PROPERTY_ENABLE) + { + emb_func_en_b.fsm_en = PROPERTY_ENABLE; + } + else + { + emb_func_en_b.fsm_en = PROPERTY_DISABLE; + } + + fsm_enable.fsm1_en = val.fsm1_en; + fsm_enable.fsm2_en = val.fsm2_en; + fsm_enable.fsm3_en = val.fsm3_en; + fsm_enable.fsm4_en = val.fsm4_en; + fsm_enable.fsm5_en = val.fsm5_en; + fsm_enable.fsm6_en = val.fsm6_en; + fsm_enable.fsm7_en = val.fsm7_en; + fsm_enable.fsm8_en = val.fsm8_en; + + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + +exit: + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable Finite State Machine (FSM) feature.[get] + * + * @param ctx read / write interface definitions + * @param val Enable Finite State Machine (FSM) feature. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_mode_get(const stmdev_ctx_t *ctx, lsm6dsv32x_fsm_mode_t *val) +{ + lsm6dsv32x_fsm_enable_t fsm_enable; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + + val->fsm1_en = fsm_enable.fsm1_en; + val->fsm2_en = fsm_enable.fsm2_en; + val->fsm3_en = fsm_enable.fsm3_en; + val->fsm4_en = fsm_enable.fsm4_en; + val->fsm5_en = fsm_enable.fsm5_en; + val->fsm6_en = fsm_enable.fsm6_en; + val->fsm7_en = fsm_enable.fsm7_en; + val->fsm8_en = fsm_enable.fsm8_en; + + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[set] + * + * @param ctx read / write interface definitions + * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FSM_LONG_COUNTER_L, (uint8_t *)&buff[0], 2); + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[get] + * + * @param ctx read / write interface definitions + * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FSM_LONG_COUNTER_L, &buff[0], 2); + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief FSM output registers[get] + * + * @param ctx read / write interface definitions + * @param val FSM output registers + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dsv32x_fsm_out_t *val) +{ + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FSM_OUTS1, (uint8_t *)val, 8); + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Finite State Machine Output Data Rate (ODR) configuration.[set] + * + * @param ctx read / write interface definitions + * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_data_rate_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_fsm_data_rate_t val) +{ + lsm6dsv32x_fsm_odr_t fsm_odr; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FSM_ODR, (uint8_t *)&fsm_odr, 1); + if (ret != 0) + { + goto exit; + } + + fsm_odr.fsm_odr = (uint8_t)val & 0x07U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FSM_ODR, (uint8_t *)&fsm_odr, 1); + +exit: + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Finite State Machine Output Data Rate (ODR) configuration.[get] + * + * @param ctx read / write interface definitions + * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_data_rate_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fsm_data_rate_t *val) +{ + lsm6dsv32x_fsm_odr_t fsm_odr; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FSM_ODR, (uint8_t *)&fsm_odr, 1); + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + + switch (fsm_odr.fsm_odr) + { + case LSM6DSV32X_FSM_15Hz: + *val = LSM6DSV32X_FSM_15Hz; + break; + + case LSM6DSV32X_FSM_30Hz: + *val = LSM6DSV32X_FSM_30Hz; + break; + + case LSM6DSV32X_FSM_60Hz: + *val = LSM6DSV32X_FSM_60Hz; + break; + + case LSM6DSV32X_FSM_120Hz: + *val = LSM6DSV32X_FSM_120Hz; + break; + + case LSM6DSV32X_FSM_240Hz: + *val = LSM6DSV32X_FSM_240Hz; + break; + + case LSM6DSV32X_FSM_480Hz: + *val = LSM6DSV32X_FSM_480Hz; + break; + + case LSM6DSV32X_FSM_960Hz: + *val = LSM6DSV32X_FSM_960Hz; + break; + + default: + *val = LSM6DSV32X_FSM_15Hz; + break; + } + + return ret; +} + +/* + * Original conversion routines taken from: https://github.com/numpy/numpy + * + * uint16_t npy_floatbits_to_halfbits(uint32_t f); + * uint16_t npy_float_to_half(float_t f); + * + * Released under BSD-3-Clause License + */ + +#define NPY_HALF_GENERATE_OVERFLOW 0 /* do not trigger FP overflow */ +#define NPY_HALF_GENERATE_UNDERFLOW 0 /* do not trigger FP underflow */ +#ifndef NPY_HALF_ROUND_TIES_TO_EVEN +#define NPY_HALF_ROUND_TIES_TO_EVEN 1 +#endif + +static uint16_t npy_floatbits_to_halfbits(uint32_t f) +{ + uint32_t f_exp, f_sig; + uint16_t h_sgn, h_exp, h_sig; + + h_sgn = (uint16_t)((f & 0x80000000u) >> 16); + f_exp = (f & 0x7f800000u); + + /* Exponent overflow/NaN converts to signed inf/NaN */ + if (f_exp >= 0x47800000u) + { + if (f_exp == 0x7f800000u) + { + /* Inf or NaN */ + f_sig = (f & 0x007fffffu); + if (f_sig != 0U) + { + /* NaN - propagate the flag in the significand... */ + uint16_t ret = (uint16_t)(0x7c00u + (f_sig >> 13)); + /* ...but make sure it stays a NaN */ + if (ret == 0x7c00u) + { + ret++; + } + return h_sgn + ret; + } + else + { + /* signed inf */ + return (uint16_t)(h_sgn + 0x7c00u); + } + } + else + { + /* overflow to signed inf */ +#if NPY_HALF_GENERATE_OVERFLOW + npy_set_floatstatus_overflow(); +#endif + return (uint16_t)(h_sgn + 0x7c00u); + } + } + + /* Exponent underflow converts to a subnormal half or signed zero */ + if (f_exp <= 0x38000000u) + { + /* + * Signed zeros, subnormal floats, and floats with small + * exponents all convert to signed zero half-floats. + */ + if (f_exp < 0x33000000u) + { +#if NPY_HALF_GENERATE_UNDERFLOW + /* If f != 0, it underflowed to 0 */ + if ((f & 0x7fffffff) != 0) + { + npy_set_floatstatus_underflow(); + } +#endif + return h_sgn; + } + /* Make the subnormal significand */ + f_exp >>= 23; + f_sig = (0x00800000u + (f & 0x007fffffu)); +#if NPY_HALF_GENERATE_UNDERFLOW + /* If it's not exactly represented, it underflowed */ + if ((f_sig & (((uint32_t)1 << (126 - f_exp)) - 1)) != 0) + { + npy_set_floatstatus_underflow(); + } +#endif + /* + * Usually the significand is shifted by 13. For subnormals an + * additional shift needs to occur. This shift is one for the largest + * exponent giving a subnormal `f_exp = 0x38000000 >> 23 = 112`, which + * offsets the new first bit. At most the shift can be 1+10 bits. + */ + f_sig >>= (113U - f_exp); + /* Handle rounding by adding 1 to the bit beyond half precision */ +#if NPY_HALF_ROUND_TIES_TO_EVEN + /* + * If the last bit in the half significand is 0 (already even), and + * the remaining bit pattern is 1000...0, then we do not add one + * to the bit after the half significand. However, the (113 - f_exp) + * shift can lose up to 11 bits, so the || checks them in the original. + * In all other cases, we can just add one. + */ + if (((f_sig & 0x00003fffu) != 0x00001000u) || (f & 0x000007ffu)) + { + f_sig += 0x00001000u; + } +#else + f_sig += 0x00001000u; +#endif + h_sig = (uint16_t)(f_sig >> 13); + /* + * If the rounding causes a bit to spill into h_exp, it will + * increment h_exp from zero to one and h_sig will be zero. + * This is the correct result. + */ + return (uint16_t)(h_sgn + h_sig); + } + + /* Regular case with no overflow or underflow */ + h_exp = (uint16_t)((f_exp - 0x38000000u) >> 13); + /* Handle rounding by adding 1 to the bit beyond half precision */ + f_sig = (f & 0x007fffffu); +#if NPY_HALF_ROUND_TIES_TO_EVEN + /* + * If the last bit in the half significand is 0 (already even), and + * the remaining bit pattern is 1000...0, then we do not add one + * to the bit after the half significand. In all other cases, we do. + */ + if ((f_sig & 0x00003fffu) != 0x00001000u) + { + f_sig += 0x00001000u; + } +#else + f_sig += 0x00001000u; +#endif + h_sig = (uint16_t)(f_sig >> 13); + /* + * If the rounding causes a bit to spill into h_exp, it will + * increment h_exp by one and h_sig will be zero. This is the + * correct result. h_exp may increment to 15, at greatest, in + * which case the result overflows to a signed inf. + */ +#if NPY_HALF_GENERATE_OVERFLOW + h_sig += h_exp; + if (h_sig == 0x7c00u) + { + npy_set_floatstatus_overflow(); + } + return h_sgn + h_sig; +#else + return h_sgn + h_exp + h_sig; +#endif +} + +static uint16_t npy_float_to_half(float_t f) +{ + union + { + float_t f; + uint32_t fbits; + } conv; + conv.f = f; + return npy_floatbits_to_halfbits(conv.fbits); +} + +/** + * @brief SFLP GBIAS value. The register value is expressed as half-precision + * floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent + * bits; F: 10 fraction bits).[set] + * + * @param ctx read / write interface definitions + * @param val GBIAS x/y/z val. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_sflp_game_gbias_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_sflp_gbias_t *val) +{ + lsm6dsv32x_sflp_data_rate_t sflp_odr; + lsm6dsv32x_emb_func_exec_status_t emb_func_sts; + lsm6dsv32x_data_ready_t drdy; + lsm6dsv32x_xl_full_scale_t xl_fs; + lsm6dsv32x_ctrl10_t ctrl10; + uint8_t master_config; + uint8_t emb_func_en_saved[2]; + uint8_t conf_saved[2]; + uint8_t reg_zero[2] = {0x0, 0x0}; + uint16_t gbias_hf[3]; + float_t k = 0.005f; + int16_t xl_data[3]; + int32_t data_tmp; + uint8_t *data_ptr = (uint8_t *)&data_tmp; + uint8_t i, j; + int32_t ret; + + ret = lsm6dsv32x_sflp_data_rate_get(ctx, &sflp_odr); + if (ret != 0) + { + return ret; + } + + /* Calculate k factor */ + switch (sflp_odr) + { + default: + case LSM6DSV32X_SFLP_15Hz: + k = 0.04f; + break; + case LSM6DSV32X_SFLP_30Hz: + k = 0.02f; + break; + case LSM6DSV32X_SFLP_60Hz: + k = 0.01f; + break; + case LSM6DSV32X_SFLP_120Hz: + k = 0.005f; + break; + case LSM6DSV32X_SFLP_240Hz: + k = 0.0025f; + break; + case LSM6DSV32X_SFLP_480Hz: + k = 0.00125f; + break; + } + + /* compute gbias as half precision float in order to be put in embedded advanced feature register */ + gbias_hf[0] = npy_float_to_half(val->gbias_x * (3.14159265358979323846f / 180.0f) / k); + gbias_hf[1] = npy_float_to_half(val->gbias_y * (3.14159265358979323846f / 180.0f) / k); + gbias_hf[2] = npy_float_to_half(val->gbias_z * (3.14159265358979323846f / 180.0f) / k); + + /* Save sensor configuration and set high-performance mode (if the sensor is in power-down mode, turn it on) */ + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL1, conf_saved, 2); + ret += lsm6dsv32x_xl_mode_set(ctx, LSM6DSV32X_XL_HIGH_PERFORMANCE_MD); + ret += lsm6dsv32x_gy_mode_set(ctx, LSM6DSV32X_GY_HIGH_PERFORMANCE_MD); + if (((uint8_t)conf_saved[0] & 0x0FU) == (uint8_t)LSM6DSV32X_ODR_OFF) + { + ret += lsm6dsv32x_xl_data_rate_set(ctx, LSM6DSV32X_ODR_AT_120Hz); + } + + /* Make sure to turn the sensor-hub master off */ + ret += lsm6dsv32x_sh_master_get(ctx, &master_config); + ret += lsm6dsv32x_sh_master_set(ctx, 0); + + /* disable algos */ + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, emb_func_en_saved, 2); + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, reg_zero, 2); + do + { + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EXEC_STATUS, + (uint8_t *)&emb_func_sts, 1); + } while (emb_func_sts.emb_func_endop != 1U); + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + // enable gbias setting + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL10, (uint8_t *)&ctrl10, 1); + ctrl10.emb_func_debug = 1; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL10, (uint8_t *)&ctrl10, 1); + + /* enable algos */ + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + emb_func_en_saved[0] |= 0x02U; /* force SFLP GAME en */ + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, emb_func_en_saved, + 2); + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + ret += lsm6dsv32x_xl_full_scale_get(ctx, &xl_fs); + + /* Read XL data */ + do + { + ret += lsm6dsv32x_flag_data_ready_get(ctx, &drdy); + } while (drdy.drdy_xl != 1U); + ret += lsm6dsv32x_acceleration_raw_get(ctx, xl_data); + + /* force sflp initialization */ + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); + for (i = 0; i < 3U; i++) + { + j = 0; + data_tmp = (int32_t)xl_data[i]; + data_tmp <<= xl_fs; // shift based on current fs + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SENSOR_HUB_1 + 3U * i, + &data_ptr[j++], 1); + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SENSOR_HUB_2 + 3U * i, + &data_ptr[j++], 1); + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SENSOR_HUB_3 + 3U * i, &data_ptr[j], + 1); + } + for (i = 0; i < 3U; i++) + { + j = 0; + data_tmp = 0; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SENSOR_HUB_10 + 3U * i, + &data_ptr[j++], 1); + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SENSOR_HUB_11 + 3U * i, + &data_ptr[j++], 1); + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SENSOR_HUB_12 + 3U * i, &data_ptr[j], + 1); + } + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + // wait end_op (and at least 30 us) + ctx->mdelay(1); + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + do + { + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EXEC_STATUS, + (uint8_t *)&emb_func_sts, 1); + } while (emb_func_sts.emb_func_endop != 1U); + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + /* write gbias in embedded advanced features registers */ + ret += lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_SFLP_GAME_GBIASX_L, + (uint8_t *)gbias_hf, 6); + + /* reload previous sensor configuration */ + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL1, conf_saved, 2); + + // disable gbias setting + ctrl10.emb_func_debug = 0; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL10, (uint8_t *)&ctrl10, 1); + + /* reload previous master configuration */ + ret += lsm6dsv32x_sh_master_set(ctx, master_config); + + return ret; +} + +/** + * @brief External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB).[set] + * + * @param ctx read / write interface definitions + * @param val External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_ext_sens_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_FSM_EXT_SENSITIVITY_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB).[get] + * + * @param ctx read / write interface definitions + * @param val External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_ext_sens_sensitivity_get(const stmdev_ctx_t *ctx, + uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_FSM_EXT_SENSITIVITY_L, &buff[0], 2); + if (ret != 0) + { + return ret; + } + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set] + * + * @param ctx read / write interface definitions + * @param val External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_ext_sens_offset_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_xl_fsm_ext_sens_offset_t val) +{ + uint8_t buff[6]; + int32_t ret; + + buff[1] = (uint8_t)(val.x / 256U); + buff[0] = (uint8_t)(val.x - (buff[1] * 256U)); + buff[3] = (uint8_t)(val.y / 256U); + buff[2] = (uint8_t)(val.y - (buff[3] * 256U)); + buff[5] = (uint8_t)(val.z / 256U); + buff[4] = (uint8_t)(val.z - (buff[5] * 256U)); + ret = lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_FSM_EXT_OFFX_L, (uint8_t *)&buff[0], 6); + + return ret; +} + +/** + * @brief External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get] + * + * @param ctx read / write interface definitions + * @param val External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_ext_sens_offset_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_xl_fsm_ext_sens_offset_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_FSM_EXT_OFFX_L, &buff[0], 6); + if (ret != 0) + { + return ret; + } + + val->x = buff[1]; + val->x = (val->x * 256U) + buff[0]; + val->y = buff[3]; + val->y = (val->y * 256U) + buff[2]; + val->z = buff[5]; + val->z = (val->z * 256U) + buff[4]; + + return ret; +} + +/** + * @brief External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set] + * + * @param ctx read / write interface definitions + * @param val External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_ext_sens_matrix_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_xl_fsm_ext_sens_matrix_t val) +{ + uint8_t buff[12]; + int32_t ret; + + buff[1] = (uint8_t)(val.xx / 256U); + buff[0] = (uint8_t)(val.xx - (buff[1] * 256U)); + buff[3] = (uint8_t)(val.xy / 256U); + buff[2] = (uint8_t)(val.xy - (buff[3] * 256U)); + buff[5] = (uint8_t)(val.xz / 256U); + buff[4] = (uint8_t)(val.xz - (buff[5] * 256U)); + buff[7] = (uint8_t)(val.yy / 256U); + buff[6] = (uint8_t)(val.yy - (buff[7] * 256U)); + buff[9] = (uint8_t)(val.yz / 256U); + buff[8] = (uint8_t)(val.yz - (buff[9] * 256U)); + buff[11] = (uint8_t)(val.zz / 256U); + buff[10] = (uint8_t)(val.zz - (buff[11] * 256U)); + ret = lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_FSM_EXT_MATRIX_XX_L, (uint8_t *)&buff[0], 12); + + return ret; +} + +/** + * @brief External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get] + * + * @param ctx read / write interface definitions + * @param val External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_ext_sens_matrix_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_xl_fsm_ext_sens_matrix_t *val) +{ + uint8_t buff[12]; + int32_t ret; + + ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_FSM_EXT_MATRIX_XX_L, &buff[0], 12); + if (ret != 0) + { + return ret; + } + + val->xx = buff[1]; + val->xx = (val->xx * 256U) + buff[0]; + val->xy = buff[3]; + val->xy = (val->xy * 256U) + buff[2]; + val->xz = buff[5]; + val->xz = (val->xz * 256U) + buff[4]; + val->yy = buff[7]; + val->yy = (val->yy * 256U) + buff[6]; + val->yz = buff[9]; + val->yz = (val->yz * 256U) + buff[8]; + val->zz = buff[11]; + val->zz = (val->zz * 256U) + buff[10]; + + return ret; +} + +/** + * @brief External sensor z-axis coordinates rotation.[set] + * + * @param ctx read / write interface definitions + * @param val Z_EQ_Y, Z_EQ_MIN_Y, Z_EQ_X, Z_EQ_MIN_X, Z_EQ_MIN_Z, Z_EQ_Z, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_ext_sens_z_orient_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_fsm_ext_sens_z_orient_t val) +{ + lsm6dsv32x_ext_cfg_a_t ext_cfg_a; + int32_t ret; + + ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + ext_cfg_a.ext_z_axis = (uint8_t)val & 0x07U; + ret += lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + + return ret; +} + +/** + * @brief External sensor z-axis coordinates rotation.[get] + * + * @param ctx read / write interface definitions + * @param val Z_EQ_Y, Z_EQ_MIN_Y, Z_EQ_X, Z_EQ_MIN_X, Z_EQ_MIN_Z, Z_EQ_Z, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_ext_sens_z_orient_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fsm_ext_sens_z_orient_t *val) +{ + lsm6dsv32x_ext_cfg_a_t ext_cfg_a; + int32_t ret; + + ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + if (ret != 0) + { + return ret; + } + + switch (ext_cfg_a.ext_z_axis) + { + case LSM6DSV32X_Z_EQ_Y: + *val = LSM6DSV32X_Z_EQ_Y; + break; + + case LSM6DSV32X_Z_EQ_MIN_Y: + *val = LSM6DSV32X_Z_EQ_MIN_Y; + break; + + case LSM6DSV32X_Z_EQ_X: + *val = LSM6DSV32X_Z_EQ_X; + break; + + case LSM6DSV32X_Z_EQ_MIN_X: + *val = LSM6DSV32X_Z_EQ_MIN_X; + break; + + case LSM6DSV32X_Z_EQ_MIN_Z: + *val = LSM6DSV32X_Z_EQ_MIN_Z; + break; + + case LSM6DSV32X_Z_EQ_Z: + *val = LSM6DSV32X_Z_EQ_Z; + break; + + default: + *val = LSM6DSV32X_Z_EQ_Y; + break; + } + + return ret; +} + +/** + * @brief External sensor Y-axis coordinates rotation.[set] + * + * @param ctx read / write interface definitions + * @param val Y_EQ_Y, Y_EQ_MIN_Y, Y_EQ_X, Y_EQ_MIN_X, Y_EQ_MIN_Z, Y_EQ_Z, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_ext_sens_y_orient_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_fsm_ext_sens_y_orient_t val) +{ + lsm6dsv32x_ext_cfg_a_t ext_cfg_a; + int32_t ret; + + ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + if (ret == 0) + { + ext_cfg_a.ext_y_axis = (uint8_t)val & 0x7U; + ret = lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + } + + return ret; +} + +/** + * @brief External sensor Y-axis coordinates rotation.[get] + * + * @param ctx read / write interface definitions + * @param val Y_EQ_Y, Y_EQ_MIN_Y, Y_EQ_X, Y_EQ_MIN_X, Y_EQ_MIN_Z, Y_EQ_Z, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_ext_sens_y_orient_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fsm_ext_sens_y_orient_t *val) +{ + lsm6dsv32x_ext_cfg_a_t ext_cfg_a; + int32_t ret; + + ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); + if (ret != 0) + { + return ret; + } + + switch (ext_cfg_a.ext_y_axis) + { + case LSM6DSV32X_Y_EQ_Y: + *val = LSM6DSV32X_Y_EQ_Y; + break; + + case LSM6DSV32X_Y_EQ_MIN_Y: + *val = LSM6DSV32X_Y_EQ_MIN_Y; + break; + + case LSM6DSV32X_Y_EQ_X: + *val = LSM6DSV32X_Y_EQ_X; + break; + + case LSM6DSV32X_Y_EQ_MIN_X: + *val = LSM6DSV32X_Y_EQ_MIN_X; + break; + + case LSM6DSV32X_Y_EQ_MIN_Z: + *val = LSM6DSV32X_Y_EQ_MIN_Z; + break; + + case LSM6DSV32X_Y_EQ_Z: + *val = LSM6DSV32X_Y_EQ_Z; + break; + + default: + *val = LSM6DSV32X_Y_EQ_Y; + break; + } + + return ret; +} + +/** + * @brief External sensor X-axis coordinates rotation.[set] + * + * @param ctx read / write interface definitions + * @param val X_EQ_Y, X_EQ_MIN_Y, X_EQ_X, X_EQ_MIN_X, X_EQ_MIN_Z, X_EQ_Z, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_ext_sens_x_orient_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_fsm_ext_sens_x_orient_t val) +{ + lsm6dsv32x_ext_cfg_b_t ext_cfg_b; + int32_t ret; + + ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EXT_CFG_B, (uint8_t *)&ext_cfg_b, 1); + if (ret == 0) + { + ext_cfg_b.ext_x_axis = (uint8_t)val & 0x7U; + ret = lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_EXT_CFG_B, (uint8_t *)&ext_cfg_b, 1); + } + + return ret; +} + +/** + * @brief External sensor X-axis coordinates rotation.[get] + * + * @param ctx read / write interface definitions + * @param val X_EQ_Y, X_EQ_MIN_Y, X_EQ_X, X_EQ_MIN_X, X_EQ_MIN_Z, X_EQ_Z, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_ext_sens_x_orient_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fsm_ext_sens_x_orient_t *val) +{ + lsm6dsv32x_ext_cfg_b_t ext_cfg_b; + int32_t ret; + + ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EXT_CFG_B, (uint8_t *)&ext_cfg_b, 1); + if (ret != 0) + { + return ret; + } + + switch (ext_cfg_b.ext_x_axis) + { + case LSM6DSV32X_X_EQ_Y: + *val = LSM6DSV32X_X_EQ_Y; + break; + + case LSM6DSV32X_X_EQ_MIN_Y: + *val = LSM6DSV32X_X_EQ_MIN_Y; + break; + + case LSM6DSV32X_X_EQ_X: + *val = LSM6DSV32X_X_EQ_X; + break; + + case LSM6DSV32X_X_EQ_MIN_X: + *val = LSM6DSV32X_X_EQ_MIN_X; + break; + + case LSM6DSV32X_X_EQ_MIN_Z: + *val = LSM6DSV32X_X_EQ_MIN_Z; + break; + + case LSM6DSV32X_X_EQ_Z: + *val = LSM6DSV32X_X_EQ_Z; + break; + + default: + *val = LSM6DSV32X_X_EQ_Y; + break; + } + + return ret; +} + +/** + * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[set] + * + * @param ctx read / write interface definitions + * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_long_cnt_timeout_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_FSM_LC_TIMEOUT_L, + (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[get] + * + * @param ctx read / write interface definitions + * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_FSM_LC_TIMEOUT_L, &buff[0], + 2); + if (ret != 0) + { + return ret; + } + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief FSM number of programs.[set] + * + * @param ctx read / write interface definitions + * @param val FSM number of programs. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_fsm_programs_t fsm_programs; + int32_t ret; + + ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_FSM_PROGRAMS, + (uint8_t *)&fsm_programs, 1); + if (ret == 0) + { + fsm_programs.fsm_n_prog = val; + ret = lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_FSM_PROGRAMS, + (uint8_t *)&fsm_programs, 1); + } + + return ret; +} + +/** + * @brief FSM number of programs.[get] + * + * @param ctx read / write interface definitions + * @param val FSM number of programs. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_fsm_programs_t fsm_programs; + int32_t ret; + + ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_FSM_PROGRAMS, + (uint8_t *)&fsm_programs, 1); + *val = fsm_programs.fsm_n_prog; + + return ret; +} + +/** + * @brief FSM start address. First available address is 0x35C.[set] + * + * @param ctx read / write interface definitions + * @param val FSM start address. First available address is 0x35C. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_FSM_START_ADD_L, + (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief FSM start address. First available address is 0x35C.[get] + * + * @param ctx read / write interface definitions + * @param val FSM start address. First available address is 0x35C. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_FSM_START_ADD_L, &buff[0], 2); + if (ret != 0) + { + return ret; + } + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Free fall + * @brief This section group all the functions concerning the free + * fall detection. + * @{ + * + */ + +/** + * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[set] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_wake_up_dur_t wake_up_dur; + lsm6dsv32x_free_fall_t free_fall; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FREE_FALL, (uint8_t *)&free_fall, 1); + free_fall.ff_dur = (uint8_t)val & 0x1FU; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FREE_FALL, (uint8_t *)&free_fall, 1); + + return ret; +} + +/** + * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[get] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_wake_up_dur_t wake_up_dur; + lsm6dsv32x_free_fall_t free_fall; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FREE_FALL, (uint8_t *)&free_fall, 1); + + *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; + + return ret; +} + +/** + * @brief Free fall threshold setting.[set] + * + * @param ctx read / write interface definitions + * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ff_thresholds_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_ff_thresholds_t val) +{ + lsm6dsv32x_free_fall_t free_fall; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret == 0) + { + free_fall.ff_ths = (uint8_t)val & 0x7U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + return ret; +} + +/** + * @brief Free fall threshold setting.[get] + * + * @param ctx read / write interface definitions + * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ff_thresholds_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_ff_thresholds_t *val) +{ + lsm6dsv32x_free_fall_t free_fall; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret != 0) + { + return ret; + } + + switch (free_fall.ff_ths) + { + case LSM6DSV32X_156_mg: + *val = LSM6DSV32X_156_mg; + break; + + case LSM6DSV32X_219_mg: + *val = LSM6DSV32X_219_mg; + break; + + case LSM6DSV32X_250_mg: + *val = LSM6DSV32X_250_mg; + break; + + case LSM6DSV32X_312_mg: + *val = LSM6DSV32X_312_mg; + break; + + case LSM6DSV32X_344_mg: + *val = LSM6DSV32X_344_mg; + break; + + case LSM6DSV32X_406_mg: + *val = LSM6DSV32X_406_mg; + break; + + case LSM6DSV32X_469_mg: + *val = LSM6DSV32X_469_mg; + break; + + case LSM6DSV32X_500_mg: + *val = LSM6DSV32X_500_mg; + break; + + default: + *val = LSM6DSV32X_156_mg; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Machine Learning Core (MLC) + * @brief This section group all the functions concerning the + * usage of Machine Learning Core + * @{ + * + */ + +/** + * @brief It enables Machine Learning Core feature (MLC). + * When the Machine Learning Core is enabled the Finite State Machine (FSM) + * programs are executed before executing the MLC algorithms.[set] + * + * @param ctx read / write interface definitions + * @param val MLC_OFF, MLC_ON, MLC_BEFORE_FSM, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_mlc_set(const stmdev_ctx_t *ctx, lsm6dsv32x_mlc_mode_t val) +{ + lsm6dsv32x_emb_func_en_b_t emb_en_b; + lsm6dsv32x_emb_func_en_a_t emb_en_a; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + if (ret != 0) + { + goto exit; + } + + switch (val) + { + case LSM6DSV32X_MLC_OFF: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 0; + break; + case LSM6DSV32X_MLC_ON: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 1; + break; + case LSM6DSV32X_MLC_ON_BEFORE_FSM: + emb_en_a.mlc_before_fsm_en = 1; + emb_en_b.mlc_en = 0; + break; + default: + break; + } + + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + +exit: + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief It enables Machine Learning Core feature (MLC). + * When the Machine Learning Core is enabled the Finite State Machine (FSM) + * programs are executed before executing the MLC algorithms.[get] + * + * @param ctx read / write interface definitions + * @param val MLC_OFF, MLC_ON, MLC_BEFORE_FSM, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_mlc_get(const stmdev_ctx_t *ctx, lsm6dsv32x_mlc_mode_t *val) +{ + lsm6dsv32x_emb_func_en_b_t emb_en_b; + lsm6dsv32x_emb_func_en_a_t emb_en_a; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + if (ret != 0) + { + goto exit; + } + + if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U) + { + *val = LSM6DSV32X_MLC_OFF; + } + else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U) + { + *val = LSM6DSV32X_MLC_ON; + } + else if (emb_en_a.mlc_before_fsm_en == 1U) + { + *val = LSM6DSV32X_MLC_ON_BEFORE_FSM; + } + else + { + /* Do nothing */ + } + +exit: + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Machine Learning Core Output Data Rate (ODR) configuration.[set] + * + * @param ctx read / write interface definitions + * @param val MLC_15Hz, MLC_30Hz, MLC_60Hz, MLC_120Hz, MLC_240Hz, MLC_480Hz, MLC_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_mlc_data_rate_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_mlc_data_rate_t val) +{ + lsm6dsv32x_mlc_odr_t mlc_odr; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MLC_ODR, (uint8_t *)&mlc_odr, 1); + if (ret != 0) + { + goto exit; + } + + mlc_odr.mlc_odr = (uint8_t)val & 0x07U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_MLC_ODR, (uint8_t *)&mlc_odr, 1); + +exit: + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Machine Learning Core Output Data Rate (ODR) configuration.[get] + * + * @param ctx read / write interface definitions + * @param val MLC_15Hz, MLC_30Hz, MLC_60Hz, MLC_120Hz, MLC_240Hz, MLC_480Hz, MLC_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_mlc_data_rate_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_mlc_data_rate_t *val) +{ + lsm6dsv32x_mlc_odr_t mlc_odr; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MLC_ODR, (uint8_t *)&mlc_odr, 1); + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + + switch (mlc_odr.mlc_odr) + { + case LSM6DSV32X_MLC_15Hz: + *val = LSM6DSV32X_MLC_15Hz; + break; + + case LSM6DSV32X_MLC_30Hz: + *val = LSM6DSV32X_MLC_30Hz; + break; + + case LSM6DSV32X_MLC_60Hz: + *val = LSM6DSV32X_MLC_60Hz; + break; + + case LSM6DSV32X_MLC_120Hz: + *val = LSM6DSV32X_MLC_120Hz; + break; + + case LSM6DSV32X_MLC_240Hz: + *val = LSM6DSV32X_MLC_240Hz; + break; + + case LSM6DSV32X_MLC_480Hz: + *val = LSM6DSV32X_MLC_480Hz; + break; + + case LSM6DSV32X_MLC_960Hz: + *val = LSM6DSV32X_MLC_960Hz; + break; + + default: + *val = LSM6DSV32X_MLC_15Hz; + break; + } + + return ret; +} + +/** + * @brief Output value of all MLC decision trees.[get] + * + * @param ctx read / write interface definitions + * @param val Output value of all MLC decision trees. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_mlc_out_get(const stmdev_ctx_t *ctx, lsm6dsv32x_mlc_out_t *val) +{ + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MLC1_SRC, (uint8_t *)val, 4); + } + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief External sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).Default value is 0x3C00 (when using an external magnetometer this value corresponds to 1 gauss/LSB).[set] + * + * @param ctx read / write interface definitions + * @param val External sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).Default value is 0x3C00 (when using an external magnetometer this value corresponds to 1 gauss/LSB). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_mlc_ext_sens_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + + ret = lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_MLC_EXT_SENSITIVITY_L, + (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief External sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).Default value is 0x3C00 (when using an external magnetometer this value corresponds to 1 gauss/LSB).[get] + * + * @param ctx read / write interface definitions + * @param val External sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).Default value is 0x3C00 (when using an external magnetometer this value corresponds to 1 gauss/LSB). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_mlc_ext_sens_sensitivity_get(const stmdev_ctx_t *ctx, + uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_MLC_EXT_SENSITIVITY_L, + &buff[0], 2); + if (ret != 0) + { + return ret; + } + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Optical Image Stabilization (OIS) + * @brief This section groups all the functions concerning + * Optical Image Stabilization (OIS). + * @{ + * + */ + +/** + * @brief Enable the full control of OIS configurations from the UI (User Interface).[set] + * + * @param ctx read / write interface definitions + * @param val OIS_CTRL_FROM_OIS, OIS_CTRL_FROM_UI, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ois_ctrl_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_ctrl_mode_t val) +{ + lsm6dsv32x_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret == 0) + { + func_cfg_access.ois_ctrl_from_ui = (uint8_t)val & 0x1U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Enable the full control of OIS configurations from the UI (User Interface).[get] + * + * @param ctx read / write interface definitions + * @param val OIS_CTRL_FROM_OIS, OIS_CTRL_FROM_UI, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ois_ctrl_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_ctrl_mode_t *val) +{ + lsm6dsv32x_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret != 0) + { + return ret; + } + + switch (func_cfg_access.ois_ctrl_from_ui) + { + case LSM6DSV32X_OIS_CTRL_FROM_OIS: + *val = LSM6DSV32X_OIS_CTRL_FROM_OIS; + break; + + case LSM6DSV32X_OIS_CTRL_FROM_UI: + *val = LSM6DSV32X_OIS_CTRL_FROM_UI; + break; + + default: + *val = LSM6DSV32X_OIS_CTRL_FROM_OIS; + break; + } + + return ret; +} + +/** + * @brief Resets the control registers of OIS from the UI (User Interface)[set] + * + * @param ctx read / write interface definitions + * @param val Resets the control registers of OIS from the UI (User Interface) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ois_reset_set(const stmdev_ctx_t *ctx, int8_t val) +{ + lsm6dsv32x_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret == 0) + { + func_cfg_access.spi2_reset = (uint8_t)val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Resets the control registers of OIS from the UI (User Interface)[get] + * + * @param ctx read / write interface definitions + * @param val Resets the control registers of OIS from the UI (User Interface) + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ois_reset_get(const stmdev_ctx_t *ctx, int8_t *val) +{ + lsm6dsv32x_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + *val = (int8_t)func_cfg_access.spi2_reset; + + return ret; +} + +/** + * @brief Enable/disable pull up on OIS interface.[set] + * + * @param ctx read / write interface definitions + * @param val Enable/disable pull up on OIS interface. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ois_interface_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret == 0) + { + pin_ctrl.ois_pu_dis = val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Enable/disable pull up on OIS interface.[get] + * + * @param ctx read / write interface definitions + * @param val Enable/disable pull up on OIS interface. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ois_interface_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + *val = pin_ctrl.ois_pu_dis; + + return ret; +} + +/** + * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[set] + * + * @param ctx read / write interface definitions + * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ois_handshake_from_ui_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_handshake_t val) +{ + lsm6dsv32x_ui_handshake_ctrl_t ui_handshake_ctrl; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_HANDSHAKE_CTRL, (uint8_t *)&ui_handshake_ctrl, 1); + if (ret == 0) + { + ui_handshake_ctrl.ui_shared_ack = val.ack; + ui_handshake_ctrl.ui_shared_req = val.req; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_UI_HANDSHAKE_CTRL, (uint8_t *)&ui_handshake_ctrl, 1); + } + + return ret; +} + +/** + * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[get] + * + * @param ctx read / write interface definitions + * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ois_handshake_from_ui_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_handshake_t *val) +{ + lsm6dsv32x_ui_handshake_ctrl_t ui_handshake_ctrl; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_HANDSHAKE_CTRL, (uint8_t *)&ui_handshake_ctrl, 1); + if (ret != 0) + { + return ret; + } + + val->ack = ui_handshake_ctrl.ui_shared_ack; + val->req = ui_handshake_ctrl.ui_shared_req; + + return ret; +} + +/** + * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[set] + * + * @param ctx read / write interface definitions + * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ois_handshake_from_ois_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_handshake_t val) +{ + lsm6dsv32x_spi2_handshake_ctrl_t spi2_handshake_ctrl; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SPI2_HANDSHAKE_CTRL, (uint8_t *)&spi2_handshake_ctrl, 1); + if (ret == 0) + { + spi2_handshake_ctrl.spi2_shared_ack = val.ack; + spi2_handshake_ctrl.spi2_shared_req = val.req; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SPI2_HANDSHAKE_CTRL, (uint8_t *)&spi2_handshake_ctrl, 1); + } + + return ret; +} + +/** + * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[get] + * + * @param ctx read / write interface definitions + * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ois_handshake_from_ois_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_handshake_t *val) +{ + lsm6dsv32x_spi2_handshake_ctrl_t spi2_handshake_ctrl; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SPI2_HANDSHAKE_CTRL, (uint8_t *)&spi2_handshake_ctrl, 1); + if (ret != 0) + { + return ret; + } + + val->ack = spi2_handshake_ctrl.spi2_shared_ack; + val->req = spi2_handshake_ctrl.spi2_shared_req; + + return ret; +} + +/** + * @brief User interface (UI) / SPI2 (OIS) shared registers[set] + * + * @param ctx read / write interface definitions + * @param val User interface (UI) / SPI2 (OIS) shared registers + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ois_shared_set(const stmdev_ctx_t *ctx, uint8_t val[6]) +{ + int32_t ret; + + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_UI_SPI2_SHARED_0, val, 6); + + return ret; +} + +/** + * @brief User interface (UI) / SPI2 (OIS) shared registers[get] + * + * @param ctx read / write interface definitions + * @param val User interface (UI) / SPI2 (OIS) shared registers + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ois_shared_get(const stmdev_ctx_t *ctx, uint8_t val[6]) +{ + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_SPI2_SHARED_0, val, 6); + + return ret; +} + +/** + * @brief In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[set] + * + * @param ctx read / write interface definitions + * @param val In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ois_on_spi2_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_ui_ctrl1_ois_t ui_ctrl1_ois; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + if (ret == 0) + { + ui_ctrl1_ois.spi2_read_en = val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + } + + return ret; +} + +/** + * @brief In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[get] + * + * @param ctx read / write interface definitions + * @param val In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ois_on_spi2_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_ui_ctrl1_ois_t ui_ctrl1_ois; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + *val = ui_ctrl1_ois.spi2_read_en; + + return ret; +} + +/** + * @brief Enables gyroscope/accelerometer OIS chain. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[set] + * + * @param ctx read / write interface definitions + * @param val Enables gyroscope/accelerometer OIS chain. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ois_chain_set(const stmdev_ctx_t *ctx, lsm6dsv32x_ois_chain_t val) +{ + lsm6dsv32x_ui_ctrl1_ois_t ui_ctrl1_ois; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + if (ret == 0) + { + ui_ctrl1_ois.ois_g_en = val.gy; + ui_ctrl1_ois.ois_xl_en = val.xl; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + } + + return ret; +} + +/** + * @brief Enables gyroscope/accelerometer OIS chain.[get] + * + * @param ctx read / write interface definitions + * @param val Enables gyroscope/accelerometer OIS chain. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ois_chain_get(const stmdev_ctx_t *ctx, lsm6dsv32x_ois_chain_t *val) +{ + lsm6dsv32x_ui_ctrl1_ois_t ui_ctrl1_ois; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + if (ret != 0) + { + return ret; + } + + val->gy = ui_ctrl1_ois.ois_g_en; + val->xl = ui_ctrl1_ois.ois_xl_en; + + return ret; +} + +/** + * @brief Gyroscope OIS full-scale selection[set] + * + * @param ctx read / write interface definitions + * @param val OIS_125dps, OIS_250dps, OIS_500dps, OIS_1000dps, OIS_2000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ois_gy_full_scale_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_gy_full_scale_t val) +{ + lsm6dsv32x_ui_ctrl2_ois_t ui_ctrl2_ois; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); + if (ret == 0) + { + ui_ctrl2_ois.fs_g_ois = (uint8_t)val & 0x03U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); + } + + return ret; +} + +/** + * @brief Gyroscope OIS full-scale selection[get] + * + * @param ctx read / write interface definitions + * @param val OIS_125dps, OIS_250dps, OIS_500dps, OIS_1000dps, OIS_2000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ois_gy_full_scale_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_gy_full_scale_t *val) +{ + lsm6dsv32x_ui_ctrl2_ois_t ui_ctrl2_ois; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); + if (ret != 0) + { + return ret; + } + + switch (ui_ctrl2_ois.fs_g_ois) + { + case LSM6DSV32X_OIS_125dps: + *val = LSM6DSV32X_OIS_125dps; + break; + + case LSM6DSV32X_OIS_250dps: + *val = LSM6DSV32X_OIS_250dps; + break; + + case LSM6DSV32X_OIS_500dps: + *val = LSM6DSV32X_OIS_500dps; + break; + + case LSM6DSV32X_OIS_1000dps: + *val = LSM6DSV32X_OIS_1000dps; + break; + + case LSM6DSV32X_OIS_2000dps: + *val = LSM6DSV32X_OIS_2000dps; + break; + + default: + *val = LSM6DSV32X_OIS_125dps; + break; + } + + return ret; +} + +/** + * @brief Selects accelerometer OIS channel full-scale.[set] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv32x_ois_xl_full_scale_t + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ois_xl_full_scale_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_xl_full_scale_t val) +{ + lsm6dsv32x_ui_ctrl3_ois_t ui_ctrl3_ois; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); + if (ret == 0) + { + ui_ctrl3_ois.fs_xl_ois = (uint8_t)val & 0x3U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); + } + + return ret; +} + +/** + * @brief Selects accelerometer OIS channel full-scale.[get] + * + * @param ctx read / write interface definitions + * @param val lsm6dsv32x_ois_xl_full_scale_t + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ois_xl_full_scale_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_xl_full_scale_t *val) +{ + lsm6dsv32x_ui_ctrl3_ois_t ui_ctrl3_ois; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); + if (ret != 0) + { + return ret; + } + + switch (ui_ctrl3_ois.fs_xl_ois) + { + + case LSM6DSV32X_OIS_4g: + *val = LSM6DSV32X_OIS_4g; + break; + + case LSM6DSV32X_OIS_8g: + *val = LSM6DSV32X_OIS_8g; + break; + + case LSM6DSV32X_OIS_16g: + *val = LSM6DSV32X_OIS_16g; + break; + + case LSM6DSV32X_OIS_32g: + *val = LSM6DSV32X_OIS_32g; + break; + + default: + *val = LSM6DSV32X_OIS_4g; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Orientation 6D (and 4D) + * @brief This section groups all the functions concerning six position + * detection (6D). + * @{ + * + */ + +/** + * @brief Threshold for 4D/6D function.[set] + * + * @param ctx read / write interface definitions + * @param val DEG_80, DEG_70, DEG_60, DEG_50, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_6d_threshold_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_6d_threshold_t val) +{ + lsm6dsv32x_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret == 0) + { + tap_ths_6d.sixd_ths = (uint8_t)val & 0x03U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + + return ret; +} + +/** + * @brief Threshold for 4D/6D function.[get] + * + * @param ctx read / write interface definitions + * @param val DEG_80, DEG_70, DEG_60, DEG_50, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_6d_threshold_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_6d_threshold_t *val) +{ + lsm6dsv32x_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) + { + return ret; + } + + switch (tap_ths_6d.sixd_ths) + { + case LSM6DSV32X_DEG_80: + *val = LSM6DSV32X_DEG_80; + break; + + case LSM6DSV32X_DEG_70: + *val = LSM6DSV32X_DEG_70; + break; + + case LSM6DSV32X_DEG_60: + *val = LSM6DSV32X_DEG_60; + break; + + case LSM6DSV32X_DEG_50: + *val = LSM6DSV32X_DEG_50; + break; + + default: + *val = LSM6DSV32X_DEG_80; + break; + } + + return ret; +} + +/** + * @brief 4D orientation detection enable. Z-axis position detection is disabled.[set] + * + * @param ctx read / write interface definitions + * @param val 4D orientation detection enable. Z-axis position detection is disabled. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret == 0) + { + tap_ths_6d.d4d_en = val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + + return ret; +} + +/** + * @brief 4D orientation detection enable. Z-axis position detection is disabled.[get] + * + * @param ctx read / write interface definitions + * @param val 4D orientation detection enable. Z-axis position detection is disabled. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + *val = tap_ths_6d.d4d_en; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup AH_QVAR + * @brief This section group all the functions concerning the + * usage of AH_QVAR + * @{ + * + */ + +/** + * @brief Configures the equivalent input impedance of the AH_QVAR buffers.[set] + * + * @param ctx read / write interface definitions + * @param val 2400MOhm, 730MOhm, 300MOhm, 255MOhm, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ah_qvar_zin_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_ah_qvar_zin_t val) +{ + lsm6dsv32x_ctrl7_t ctrl7; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret == 0) + { + ctrl7.ah_qvar_c_zin = (uint8_t)val & 0x03U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL7, (uint8_t *)&ctrl7, 1); + } + + return ret; +} + +/** + * @brief Configures the equivalent input impedance of the AH_QVAR buffers.[get] + * + * @param ctx read / write interface definitions + * @param val 2400MOhm, 730MOhm, 300MOhm, 255MOhm, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ah_qvar_zin_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_ah_qvar_zin_t *val) +{ + lsm6dsv32x_ctrl7_t ctrl7; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl7.ah_qvar_c_zin) + { + case LSM6DSV32X_2400MOhm: + *val = LSM6DSV32X_2400MOhm; + break; + + case LSM6DSV32X_730MOhm: + *val = LSM6DSV32X_730MOhm; + break; + + case LSM6DSV32X_300MOhm: + *val = LSM6DSV32X_300MOhm; + break; + + case LSM6DSV32X_255MOhm: + *val = LSM6DSV32X_255MOhm; + break; + + default: + *val = LSM6DSV32X_2400MOhm; + break; + } + + return ret; +} + +/** + * @brief Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/AH1/Qvar1 and SCx/AH2/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode.[set] + * + * @param ctx read / write interface definitions + * @param val Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/AH1/Qvar1 and SCx/AH2/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ah_qvar_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_ah_qvar_mode_t val) +{ + lsm6dsv32x_ctrl7_t ctrl7; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret == 0) + { + ctrl7.ah_qvar_en = val.ah_qvar_en; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL7, (uint8_t *)&ctrl7, 1); + } + + return ret; +} + +/** + * @brief Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/AH1/Qvar1 and SCx/AH2/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode.[get] + * + * @param ctx read / write interface definitions + * @param val Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/AH1/Qvar1 and SCx/AH2/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ah_qvar_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_ah_qvar_mode_t *val) +{ + lsm6dsv32x_ctrl7_t ctrl7; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL7, (uint8_t *)&ctrl7, 1); + val->ah_qvar_en = ctrl7.ah_qvar_en; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup SenseWire (I3C) + * @brief This section group all the functions concerning the + * usage of SenseWire (I3C) + * @{ + * + */ + +/** + * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[set] + * + * @param ctx read / write interface definitions + * @param val SW_RST_DYN_ADDRESS_RST, GLOBAL_RST, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_i3c_reset_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_i3c_reset_mode_t val) +{ + lsm6dsv32x_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret == 0) + { + pin_ctrl.ibhr_por_en = (uint8_t)val & 0x01U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[get] + * + * @param ctx read / write interface definitions + * @param val SW_RST_DYN_ADDRESS_RST, I3C_GLOBAL_RST, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_i3c_reset_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_i3c_reset_mode_t *val) +{ + lsm6dsv32x_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret != 0) + { + return ret; + } + + switch (pin_ctrl.ibhr_por_en) + { + case LSM6DSV32X_SW_RST_DYN_ADDRESS_RST: + *val = LSM6DSV32X_SW_RST_DYN_ADDRESS_RST; + break; + + case LSM6DSV32X_I3C_GLOBAL_RST: + *val = LSM6DSV32X_I3C_GLOBAL_RST; + break; + + default: + *val = LSM6DSV32X_SW_RST_DYN_ADDRESS_RST; + break; + } + + return ret; +} + +/** + * @brief Enable/Disable INT pin when I3C is used.[set] + * + * @param ctx read / write interface definitions + * @param val 0: disabled, 1: enabled + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_i3c_int_en_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_ctrl5_t ctrl5; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret == 0) + { + ctrl5.int_en_i3c = (uint8_t)val & 0x01U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL5, (uint8_t *)&ctrl5, 1); + } + + return ret; +} + +/** + * @brief Enable/Disable INT pin when I3C is used.[get] + * + * @param ctx read / write interface definitions + * @param val 0: disabled, 1: enabled + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_i3c_int_en_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_ctrl5_t ctrl5; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL5, (uint8_t *)&ctrl5, 1); + *val = ctrl5.int_en_i3c; + + return ret; +} + +/** + * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[set] + * + * @param ctx read / write interface definitions + * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_i3c_ibi_time_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_i3c_ibi_time_t val) +{ + lsm6dsv32x_ctrl5_t ctrl5; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret == 0) + { + ctrl5.bus_act_sel = (uint8_t)val & 0x03U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL5, (uint8_t *)&ctrl5, 1); + } + + return ret; +} + +/** + * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[get] + * + * @param ctx read / write interface definitions + * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_i3c_ibi_time_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_i3c_ibi_time_t *val) +{ + lsm6dsv32x_ctrl5_t ctrl5; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret != 0) + { + return ret; + } + + switch (ctrl5.bus_act_sel) + { + case LSM6DSV32X_IBI_2us: + *val = LSM6DSV32X_IBI_2us; + break; + + case LSM6DSV32X_IBI_50us: + *val = LSM6DSV32X_IBI_50us; + break; + + case LSM6DSV32X_IBI_1ms: + *val = LSM6DSV32X_IBI_1ms; + break; + + case LSM6DSV32X_IBI_25ms: + *val = LSM6DSV32X_IBI_25ms; + break; + + default: + *val = LSM6DSV32X_IBI_2us; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Sensor hub + * @brief This section groups all the functions that manage the + * sensor hub. + * @{ + * + */ + +/** + * @brief Sensor Hub master I2C pull-up enable.[set] + * + * @param ctx read / write interface definitions + * @param val Sensor Hub master I2C pull-up enable. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_sh_master_interface_pull_up_set(const stmdev_ctx_t *ctx, + uint8_t val) +{ + lsm6dsv32x_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.shub_pu_en = val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Sensor Hub master I2C pull-up enable.[get] + * + * @param ctx read / write interface definitions + * @param val Sensor Hub master I2C pull-up enable. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_sh_master_interface_pull_up_get(const stmdev_ctx_t *ctx, + uint8_t *val) +{ + lsm6dsv32x_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1); + *val = if_cfg.shub_pu_en; + + return ret; +} + +/** + * @brief Sensor hub output registers.[get] + * + * @param ctx read / write interface definitions + * @param val Sensor hub output registers. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, + uint8_t len) +{ + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SENSOR_HUB_1, val, len); + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Number of external sensors to be read by the sensor hub.[set] + * + * @param ctx read / write interface definitions + * @param val SLV_0, SLV_0_1, SLV_0_1_2, SLV_0_1_2_3, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_sh_slave_connected_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_sh_slave_connected_t val) +{ + lsm6dsv32x_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + if (ret != 0) + { + goto exit; + } + + master_config.aux_sens_on = (uint8_t)val & 0x3U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + +exit: + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Number of external sensors to be read by the sensor hub.[get] + * + * @param ctx read / write interface definitions + * @param val SLV_0, SLV_0_1, SLV_0_1_2, SLV_0_1_2_3, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_sh_slave_connected_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_sh_slave_connected_t *val) +{ + lsm6dsv32x_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + + switch (master_config.aux_sens_on) + { + case LSM6DSV32X_SLV_0: + *val = LSM6DSV32X_SLV_0; + break; + + case LSM6DSV32X_SLV_0_1: + *val = LSM6DSV32X_SLV_0_1; + break; + + case LSM6DSV32X_SLV_0_1_2: + *val = LSM6DSV32X_SLV_0_1_2; + break; + + case LSM6DSV32X_SLV_0_1_2_3: + *val = LSM6DSV32X_SLV_0_1_2_3; + break; + + default: + *val = LSM6DSV32X_SLV_0; + break; + } + + return ret; +} + +/** + * @brief Sensor hub I2C master enable.[set] + * + * @param ctx read / write interface definitions + * @param val Sensor hub I2C master enable. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + if (ret != 0) + { + goto exit; + } + + master_config.master_on = val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + +exit: + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Sensor hub I2C master enable.[get] + * + * @param ctx read / write interface definitions + * @param val Sensor hub I2C master enable. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + + *val = master_config.master_on; + + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief I2C interface pass-through.[set] + * + * @param ctx read / write interface definitions + * @param val I2C interface pass-through. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + if (ret != 0) + { + goto exit; + } + + master_config.pass_through_mode = val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + +exit: + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief I2C interface pass-through.[get] + * + * @param ctx read / write interface definitions + * @param val I2C interface pass-through. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + + *val = master_config.pass_through_mode; + + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Sensor hub trigger signal selection.[set] + * + * @param ctx read / write interface definitions + * @param val SH_TRG_XL_GY_DRDY, SH_TRIG_INT2, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_sh_syncro_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_sh_syncro_mode_t val) +{ + lsm6dsv32x_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + if (ret != 0) + { + goto exit; + } + + master_config.start_config = (uint8_t)val & 0x01U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + +exit: + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Sensor hub trigger signal selection.[get] + * + * @param ctx read / write interface definitions + * @param val SH_TRG_XL_GY_DRDY, SH_TRIG_INT2, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_sh_syncro_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_sh_syncro_mode_t *val) +{ + lsm6dsv32x_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + + switch (master_config.start_config) + { + case LSM6DSV32X_SH_TRG_XL_GY_DRDY: + *val = LSM6DSV32X_SH_TRG_XL_GY_DRDY; + break; + + case LSM6DSV32X_SH_TRIG_INT2: + *val = LSM6DSV32X_SH_TRIG_INT2; + break; + + default: + *val = LSM6DSV32X_SH_TRG_XL_GY_DRDY; + break; + } + + return ret; +} + +/** + * @brief Slave 0 write operation is performed only at the first sensor hub cycle.[set] + * + * @param ctx read / write interface definitions + * @param val EACH_SH_CYCLE, ONLY_FIRST_CYCLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_sh_write_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_sh_write_mode_t val) +{ + lsm6dsv32x_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + if (ret != 0) + { + goto exit; + } + + master_config.write_once = (uint8_t)val & 0x01U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + +exit: + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Slave 0 write operation is performed only at the first sensor hub cycle.[get] + * + * @param ctx read / write interface definitions + * @param val EACH_SH_CYCLE, ONLY_FIRST_CYCLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_sh_write_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_sh_write_mode_t *val) +{ + lsm6dsv32x_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + + switch (master_config.write_once) + { + case LSM6DSV32X_EACH_SH_CYCLE: + *val = LSM6DSV32X_EACH_SH_CYCLE; + break; + + case LSM6DSV32X_ONLY_FIRST_CYCLE: + *val = LSM6DSV32X_ONLY_FIRST_CYCLE; + break; + + default: + *val = LSM6DSV32X_EACH_SH_CYCLE; + break; + } + + return ret; +} + +/** + * @brief Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.[set] + * + * @param ctx read / write interface definitions + * @param val Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_sh_reset_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + if (ret != 0) + { + goto exit; + } + + master_config.rst_master_regs = val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + +exit: + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.[get] + * + * @param ctx read / write interface definitions + * @param val Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_master_config_t master_config; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1); + + *val = master_config.rst_master_regs; + + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Configure slave 0 for perform a write.[set] + * + * @param ctx read / write interface definitions + * @param val a structure that contain + * - uint8_t slv1_add; 8 bit i2c device address + * - uint8_t slv1_subadd; 8 bit register device address + * - uint8_t slv1_data; 8 bit data to write + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_sh_cfg_write(const stmdev_ctx_t *ctx, + lsm6dsv32x_sh_cfg_write_t *val) +{ + lsm6dsv32x_slv0_add_t reg; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); + if (ret != 0) + { + return ret; + } + + reg.slave0_add = val->slv0_add; + reg.rw_0 = 0; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SLV0_ADD, (uint8_t *)®, 1); + if (ret != 0) + { + goto exit; + } + + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SLV0_SUBADD, + &(val->slv0_subadd), 1); + if (ret != 0) + { + goto exit; + } + + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_DATAWRITE_SLV0, + &(val->slv0_data), 1); + +exit: + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Rate at which the master communicates.[set] + * + * @param ctx read / write interface definitions + * @param val SH_15Hz, SH_30Hz, SH_60Hz, SH_120Hz, SH_240Hz, SH_480Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_sh_data_rate_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_sh_data_rate_t val) +{ + lsm6dsv32x_slv0_config_t slv0_config; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); + if (ret != 0) + { + goto exit; + } + + slv0_config.shub_odr = (uint8_t)val & 0x07U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); + +exit: + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Rate at which the master communicates.[get] + * + * @param ctx read / write interface definitions + * @param val SH_15Hz, SH_30Hz, SH_60Hz, SH_120Hz, SH_240Hz, SH_480Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_sh_data_rate_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_sh_data_rate_t *val) +{ + lsm6dsv32x_slv0_config_t slv0_config; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + + switch (slv0_config.shub_odr) + { + case LSM6DSV32X_SH_15Hz: + *val = LSM6DSV32X_SH_15Hz; + break; + + case LSM6DSV32X_SH_30Hz: + *val = LSM6DSV32X_SH_30Hz; + break; + + case LSM6DSV32X_SH_60Hz: + *val = LSM6DSV32X_SH_60Hz; + break; + + case LSM6DSV32X_SH_120Hz: + *val = LSM6DSV32X_SH_120Hz; + break; + + case LSM6DSV32X_SH_240Hz: + *val = LSM6DSV32X_SH_240Hz; + break; + + case LSM6DSV32X_SH_480Hz: + *val = LSM6DSV32X_SH_480Hz; + break; + + default: + *val = LSM6DSV32X_SH_15Hz; + break; + } + + return ret; +} + +/** + * @brief Configure slave idx for perform a read.[set] + * + * @param ctx read / write interface definitions + * @param val Structure that contain + * - uint8_t slv_add; 8 bit i2c device address + * - uint8_t slv_subadd; 8 bit register device address + * - uint8_t slv_len; num of bit to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_sh_slv_cfg_read(const stmdev_ctx_t *ctx, uint8_t idx, + lsm6dsv32x_sh_cfg_read_t *val) +{ + lsm6dsv32x_slv0_add_t slv_add; + lsm6dsv32x_slv0_config_t slv_config; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK); + if (ret != 0) + { + return ret; + } + + slv_add.slave0_add = val->slv_add; + slv_add.rw_0 = 1; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SLV0_ADD + idx * 3U, + (uint8_t *)&slv_add, 1); + if (ret != 0) + { + goto exit; + } + + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SLV0_SUBADD + idx * 3U, + &(val->slv_subadd), 1); + if (ret != 0) + { + goto exit; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SLV0_CONFIG + idx * 3U, + (uint8_t *)&slv_config, 1); + if (ret != 0) + { + goto exit; + } + + slv_config.slave0_numop = val->slv_len; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SLV0_CONFIG + idx * 3U, + (uint8_t *)&slv_config, 1); + +exit: + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Sensor hub source register.[get] + * + * @param ctx read / write interface definitions + * @param val union of registers from STATUS_MASTER to + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_sh_status_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_status_master_t *val) +{ + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_STATUS_MASTER_MAINPAGE, (uint8_t *) val, 1); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Serial interfaces + * @brief This section groups all the functions concerning + * serial interfaces management (not auxiliary) + * @{ + * + */ + +/** + * @brief Enables pull-up on SDO pin of UI (User Interface).[set] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDO pin of UI (User Interface). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret == 0) + { + pin_ctrl.sdo_pu_en = val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Enables pull-up on SDO pin of UI (User Interface).[get] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDO pin of UI (User Interface). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + *val = pin_ctrl.sdo_pu_en; + + return ret; +} + +/** + * @brief Disables I2C and I3C on UI (User Interface).[set] + * + * @param ctx read / write interface definitions + * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ui_i2c_i3c_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_ui_i2c_i3c_mode_t val) +{ + lsm6dsv32x_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.i2c_i3c_disable = (uint8_t)val & 0x1U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Disables I2C and I3C on UI (User Interface).[get] + * + * @param ctx read / write interface definitions + * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_ui_i2c_i3c_mode_t *val) +{ + lsm6dsv32x_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + + switch (if_cfg.i2c_i3c_disable) + { + case LSM6DSV32X_I2C_I3C_ENABLE: + *val = LSM6DSV32X_I2C_I3C_ENABLE; + break; + + case LSM6DSV32X_I2C_I3C_DISABLE: + *val = LSM6DSV32X_I2C_I3C_DISABLE; + break; + + default: + *val = LSM6DSV32X_I2C_I3C_ENABLE; + break; + } + + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val SPI_4_WIRE, SPI_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsv32x_spi_mode_t val) +{ + lsm6dsv32x_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.sim = (uint8_t)val & 0x01U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val SPI_4_WIRE, SPI_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsv32x_spi_mode_t *val) +{ + lsm6dsv32x_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret != 0) + { + return ret; + } + + switch (if_cfg.sim) + { + case LSM6DSV32X_SPI_4_WIRE: + *val = LSM6DSV32X_SPI_4_WIRE; + break; + + case LSM6DSV32X_SPI_3_WIRE: + *val = LSM6DSV32X_SPI_3_WIRE; + break; + + default: + *val = LSM6DSV32X_SPI_4_WIRE; + break; + } + + return ret; +} + +/** + * @brief Enables pull-up on SDA pin.[set] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDA pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ui_sda_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.sda_pu_en = val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Enables pull-up on SDA pin.[get] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDA pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_if_cfg_t if_cfg; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1); + *val = if_cfg.sda_pu_en; + + return ret; +} + +/** + * @brief SPI2 (OIS Inteface) Serial Interface Mode selection. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[set] + * + * @param ctx read / write interface definitions + * @param val SPI2_4_WIRE, SPI2_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_spi2_mode_set(const stmdev_ctx_t *ctx, lsm6dsv32x_spi2_mode_t val) +{ + lsm6dsv32x_ui_ctrl1_ois_t ui_ctrl1_ois; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + if (ret == 0) + { + ui_ctrl1_ois.sim_ois = (uint8_t)val & 0x01U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + } + + return ret; +} + +/** + * @brief SPI2 (OIS Inteface) Serial Interface Mode selection. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[get] + * + * @param ctx read / write interface definitions + * @param val SPI2_4_WIRE, SPI2_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_spi2_mode_get(const stmdev_ctx_t *ctx, lsm6dsv32x_spi2_mode_t *val) +{ + lsm6dsv32x_ui_ctrl1_ois_t ui_ctrl1_ois; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); + if (ret != 0) + { + return ret; + } + + switch (ui_ctrl1_ois.sim_ois) + { + case LSM6DSV32X_SPI2_4_WIRE: + *val = LSM6DSV32X_SPI2_4_WIRE; + break; + + case LSM6DSV32X_SPI2_3_WIRE: + *val = LSM6DSV32X_SPI2_3_WIRE; + break; + + default: + *val = LSM6DSV32X_SPI2_4_WIRE; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Significant motion detection + * @brief This section groups all the functions that manage the + * significant motion detection. + * @{ + * + */ + + +/** + * @brief Enables significant motion detection function.[set] + * + * @param ctx read / write interface definitions + * @param val Enables significant motion detection function. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + emb_func_en_a.sign_motion_en = val; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables significant motion detection function.[get] + * + * @param ctx read / write interface definitions + * @param val Enables significant motion detection function. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + *val = emb_func_en_a.sign_motion_en; + + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Step Counter (Pedometer) + * @brief This section groups all the functions that manage pedometer. + * @{ + * + */ + +/** + * @brief Step counter mode[set] + * + * @param ctx read / write interface definitions + * @param val Step counter mode + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_stpcnt_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_stpcnt_mode_t val) +{ + lsm6dsv32x_emb_func_en_a_t emb_func_en_a; + lsm6dsv32x_emb_func_en_b_t emb_func_en_b; + lsm6dsv32x_pedo_cmd_reg_t pedo_cmd_reg; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + if (ret != 0) + { + goto exit; + } + + if ((val.false_step_rej == PROPERTY_ENABLE) + && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) == + PROPERTY_DISABLE)) + { + emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE; + } + + emb_func_en_a.pedo_en = val.step_counter_enable; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + +exit: + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_PEDO_CMD_REG, + (uint8_t *)&pedo_cmd_reg, 1); + pedo_cmd_reg.fp_rejection_en = val.false_step_rej; + ret += lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_PEDO_CMD_REG, + (uint8_t *)&pedo_cmd_reg, 1); + } + + return ret; +} + +/** + * @brief Step counter mode[get] + * + * @param ctx read / write interface definitions + * @param val false_step_rej, step_counter, step_detector, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_stpcnt_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_stpcnt_mode_t *val) +{ + lsm6dsv32x_emb_func_en_a_t emb_func_en_a; + lsm6dsv32x_pedo_cmd_reg_t pedo_cmd_reg; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_PEDO_CMD_REG, + (uint8_t *)&pedo_cmd_reg, 1); + if (ret != 0) + { + return ret; + } + + val->false_step_rej = pedo_cmd_reg.fp_rejection_en; + val->step_counter_enable = emb_func_en_a.pedo_en; + + return ret; +} + +/** + * @brief Step counter output, number of detected steps.[get] + * + * @param ctx read / write interface definitions + * @param val Step counter output, number of detected steps. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_STEP_COUNTER_L, &buff[0], 2); + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief Reset step counter.[set] + * + * @param ctx read / write interface definitions + * @param val Reset step counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_stpcnt_rst_step_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_emb_func_src_t emb_func_src; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + if (ret != 0) + { + goto exit; + } + + emb_func_src.pedo_rst_step = val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + +exit: + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Reset step counter.[get] + * + * @param ctx read / write interface definitions + * @param val Reset step counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_emb_func_src_t emb_func_src; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + *val = emb_func_src.pedo_rst_step; + + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Pedometer debounce configuration.[set] + * + * @param ctx read / write interface definitions + * @param val Pedometer debounce configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_pedo_deb_steps_conf_t pedo_deb_steps_conf; + int32_t ret; + + ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_PEDO_DEB_STEPS_CONF, + (uint8_t *)&pedo_deb_steps_conf, 1); + if (ret == 0) + { + pedo_deb_steps_conf.deb_step = val; + ret = lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_PEDO_DEB_STEPS_CONF, + (uint8_t *)&pedo_deb_steps_conf, 1); + } + + return ret; +} + +/** + * @brief Pedometer debounce configuration.[get] + * + * @param ctx read / write interface definitions + * @param val Pedometer debounce configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_pedo_deb_steps_conf_t pedo_deb_steps_conf; + int32_t ret; + + ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_PEDO_DEB_STEPS_CONF, + (uint8_t *)&pedo_deb_steps_conf, 1); + *val = pedo_deb_steps_conf.deb_step; + + return ret; +} + +/** + * @brief Time period register for step detection on delta time.[set] + * + * @param ctx read / write interface definitions + * @param val Time period register for step detection on delta time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_PEDO_SC_DELTAT_L, + (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief Time period register for step detection on delta time.[get] + * + * @param ctx read / write interface definitions + * @param val Time period register for step detection on delta time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_PEDO_SC_DELTAT_L, &buff[0], + 2); + if (ret != 0) + { + return ret; + } + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Sensor Fusion Low Power (SFLP) + * @brief This section groups all the functions that manage pedometer. + * @{ + * + */ + +/** + * @brief Enable SFLP Game Rotation Vector (6x).[set] + * + * @param ctx read / write interface definitions + * @param val Enable/Disable game rotation value (0/1). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + if (ret != 0) + { + goto exit; + } + + emb_func_en_a.sflp_game_en = val; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, + (uint8_t *)&emb_func_en_a, 1); + +exit: + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable SFLP Game Rotation Vector (6x).[get] + * + * @param ctx read / write interface definitions + * @param val Enable/Disable game rotation value (0/1). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + *val = emb_func_en_a.sflp_game_en; + + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief SFLP Data Rate (ODR) configuration.[set] + * + * @param ctx read / write interface definitions + * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_sflp_data_rate_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_sflp_data_rate_t val) +{ + lsm6dsv32x_sflp_odr_t sflp_odr; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + if (ret != 0) + { + goto exit; + } + + sflp_odr.sflp_game_odr = (uint8_t)val & 0x07U; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + +exit: + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief SFLP Data Rate (ODR) configuration.[get] + * + * @param ctx read / write interface definitions + * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_sflp_data_rate_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_sflp_data_rate_t *val) +{ + lsm6dsv32x_sflp_odr_t sflp_odr; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + if (ret != 0) + { + return ret; + } + + switch (sflp_odr.sflp_game_odr) + { + case LSM6DSV32X_SFLP_15Hz: + *val = LSM6DSV32X_SFLP_15Hz; + break; + + case LSM6DSV32X_SFLP_30Hz: + *val = LSM6DSV32X_SFLP_30Hz; + break; + + case LSM6DSV32X_SFLP_60Hz: + *val = LSM6DSV32X_SFLP_60Hz; + break; + + case LSM6DSV32X_SFLP_120Hz: + *val = LSM6DSV32X_SFLP_120Hz; + break; + + case LSM6DSV32X_SFLP_240Hz: + *val = LSM6DSV32X_SFLP_240Hz; + break; + + case LSM6DSV32X_SFLP_480Hz: + *val = LSM6DSV32X_SFLP_480Hz; + break; + + default: + *val = LSM6DSV32X_SFLP_15Hz; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Tap - Double Tap + * @brief This section groups all the functions that manage the + * tap and double tap event generation. + * @{ + * + */ + +/** + * @brief Enable axis for Tap - Double Tap detection.[set] + * + * @param ctx read / write interface definitions + * @param val Enable axis for Tap - Double Tap detection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_tap_detection_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_tap_detection_t val) +{ + lsm6dsv32x_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret == 0) + { + tap_cfg0.tap_x_en = val.tap_x_en; + tap_cfg0.tap_y_en = val.tap_y_en; + tap_cfg0.tap_z_en = val.tap_z_en; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + return ret; +} + +/** + * @brief Enable axis for Tap - Double Tap detection.[get] + * + * @param ctx read / write interface definitions + * @param val Enable axis for Tap - Double Tap detection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_tap_detection_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_tap_detection_t *val) +{ + lsm6dsv32x_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret != 0) + { + return ret; + } + + val->tap_x_en = tap_cfg0.tap_x_en; + val->tap_y_en = tap_cfg0.tap_y_en; + val->tap_z_en = tap_cfg0.tap_z_en; + + return ret; +} + +/** + * @brief axis Tap - Double Tap recognition thresholds.[set] + * + * @param ctx read / write interface definitions + * @param val axis Tap - Double Tap recognition thresholds. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_tap_thresholds_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_tap_thresholds_t val) +{ + lsm6dsv32x_tap_ths_6d_t tap_ths_6d; + lsm6dsv32x_tap_cfg2_t tap_cfg2; + lsm6dsv32x_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) + { + return ret; + } + + tap_cfg1.tap_ths_x = val.x; + tap_cfg2.tap_ths_y = val.y; + tap_ths_6d.tap_ths_z = val.z; + + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + + return ret; +} + +/** + * @brief axis Tap - Double Tap recognition thresholds.[get] + * + * @param ctx read / write interface definitions + * @param val axis Tap - Double Tap recognition thresholds. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_tap_thresholds_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_tap_thresholds_t *val) +{ + lsm6dsv32x_tap_ths_6d_t tap_ths_6d; + lsm6dsv32x_tap_cfg2_t tap_cfg2; + lsm6dsv32x_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret != 0) + { + return ret; + } + + val->x = tap_cfg1.tap_ths_x; + val->y = tap_cfg2.tap_ths_y; + val->z = tap_ths_6d.tap_ths_z; + + return ret; +} + +/** + * @brief Selection of axis priority for TAP detection.[set] + * + * @param ctx read / write interface definitions + * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY , + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_tap_axis_priority_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_tap_axis_priority_t val) +{ + lsm6dsv32x_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret == 0) + { + tap_cfg1.tap_priority = (uint8_t)val & 0x7U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + } + + return ret; +} + +/** + * @brief Selection of axis priority for TAP detection.[get] + * + * @param ctx read / write interface definitions + * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY , + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_tap_axis_priority_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_tap_axis_priority_t *val) +{ + lsm6dsv32x_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret != 0) + { + return ret; + } + + switch (tap_cfg1.tap_priority) + { + case LSM6DSV32X_XYZ : + *val = LSM6DSV32X_XYZ ; + break; + + case LSM6DSV32X_YXZ : + *val = LSM6DSV32X_YXZ ; + break; + + case LSM6DSV32X_XZY: + *val = LSM6DSV32X_XZY; + break; + + case LSM6DSV32X_ZYX : + *val = LSM6DSV32X_ZYX ; + break; + + case LSM6DSV32X_YZX : + *val = LSM6DSV32X_YZX ; + break; + + case LSM6DSV32X_ZXY : + *val = LSM6DSV32X_ZXY ; + break; + + default: + *val = LSM6DSV32X_XYZ ; + break; + } + + return ret; +} + +/** + * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[set] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_tap_time_windows_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_tap_time_windows_t val) +{ + lsm6dsv32x_tap_dur_t tap_dur; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_DUR, (uint8_t *)&tap_dur, 1); + if (ret == 0) + { + tap_dur.shock = val.shock; + tap_dur.quiet = val.quiet; + tap_dur.dur = val.tap_gap; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_TAP_DUR, (uint8_t *)&tap_dur, 1); + } + + return ret; +} + +/** + * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[get] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_tap_time_windows_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_tap_time_windows_t *val) +{ + lsm6dsv32x_tap_dur_t tap_dur; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_DUR, (uint8_t *)&tap_dur, 1); + if (ret != 0) + { + return ret; + } + + val->shock = tap_dur.shock; + val->quiet = tap_dur.quiet; + val->tap_gap = tap_dur.dur; + + return ret; +} + +/** + * @brief Single/double-tap event enable.[set] + * + * @param ctx read / write interface definitions + * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dsv32x_tap_mode_t val) +{ + lsm6dsv32x_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret == 0) + { + wake_up_ths.single_double_tap = (uint8_t)val & 0x01U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + return ret; +} + +/** + * @brief Single/double-tap event enable.[get] + * + * @param ctx read / write interface definitions + * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dsv32x_tap_mode_t *val) +{ + lsm6dsv32x_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret != 0) + { + return ret; + } + + switch (wake_up_ths.single_double_tap) + { + case LSM6DSV32X_ONLY_SINGLE: + *val = LSM6DSV32X_ONLY_SINGLE; + break; + + case LSM6DSV32X_BOTH_SINGLE_DOUBLE: + *val = LSM6DSV32X_BOTH_SINGLE_DOUBLE; + break; + + default: + *val = LSM6DSV32X_ONLY_SINGLE; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Tilt detection + * @brief This section groups all the functions that manage the tilt + * event detection. + * @{ + * + */ + +/** + * @brief Tilt calculation.[set] + * + * @param ctx read / write interface definitions + * @param val Tilt calculation. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + emb_func_en_a.tilt_en = val; + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Tilt calculation.[get] + * + * @param ctx read / write interface definitions + * @param val Tilt calculation. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK); + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + *val = emb_func_en_a.tilt_en; + + ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Timestamp + * @brief This section groups all the functions that manage the + * timestamp generation. + * @{ + * + */ + +/** + * @brief Timestamp data output.[get] + * + * @param ctx read / write interface definitions + * @param val Timestamp data output. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) +{ + uint8_t buff[4]; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TIMESTAMP0, &buff[0], 4); + if (ret != 0) + { + return ret; + } + + *val = buff[3]; + *val = (*val * 256U) + buff[2]; + *val = (*val * 256U) + buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief Enables timestamp counter.[set] + * + * @param ctx read / write interface definitions + * @param val Enables timestamp counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv32x_functions_enable_t functions_enable; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret == 0) + { + functions_enable.timestamp_en = val; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + return ret; +} + +/** + * @brief Enables timestamp counter.[get] + * + * @param ctx read / write interface definitions + * @param val Enables timestamp counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv32x_functions_enable_t functions_enable; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + *val = functions_enable.timestamp_en; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Wake Up - Activity - Inactivity (Sleep) + * @brief This section groups all the functions that manage the Wake Up + * event generation. + * @{ + * + */ + +/** + * @brief Enable activity/inactivity (sleep) function.[set] + * + * @param ctx read / write interface definitions + * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_act_mode_set(const stmdev_ctx_t *ctx, lsm6dsv32x_act_mode_t val) +{ + lsm6dsv32x_functions_enable_t functions_enable; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret == 0) + { + functions_enable.inact_en = (uint8_t)val & 0x3U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + return ret; +} + +/** + * @brief Enable activity/inactivity (sleep) function.[get] + * + * @param ctx read / write interface definitions + * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_act_mode_get(const stmdev_ctx_t *ctx, lsm6dsv32x_act_mode_t *val) +{ + lsm6dsv32x_functions_enable_t functions_enable; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret != 0) + { + return ret; + } + + switch (functions_enable.inact_en) + { + case LSM6DSV32X_XL_AND_GY_NOT_AFFECTED: + *val = LSM6DSV32X_XL_AND_GY_NOT_AFFECTED; + break; + + case LSM6DSV32X_XL_LOW_POWER_GY_NOT_AFFECTED: + *val = LSM6DSV32X_XL_LOW_POWER_GY_NOT_AFFECTED; + break; + + case LSM6DSV32X_XL_LOW_POWER_GY_SLEEP: + *val = LSM6DSV32X_XL_LOW_POWER_GY_SLEEP; + break; + + case LSM6DSV32X_XL_LOW_POWER_GY_POWER_DOWN: + *val = LSM6DSV32X_XL_LOW_POWER_GY_POWER_DOWN; + break; + + default: + *val = LSM6DSV32X_XL_AND_GY_NOT_AFFECTED; + break; + } + + return ret; +} + +/** + * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[set] + * + * @param ctx read / write interface definitions + * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_act_from_sleep_to_act_dur_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_act_from_sleep_to_act_dur_t val) +{ + lsm6dsv32x_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret == 0) + { + inactivity_dur.inact_dur = (uint8_t)val & 0x3U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + return ret; +} + +/** + * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[get] + * + * @param ctx read / write interface definitions + * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_act_from_sleep_to_act_dur_t *val) +{ + lsm6dsv32x_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret != 0) + { + return ret; + } + + switch (inactivity_dur.inact_dur) + { + case LSM6DSV32X_SLEEP_TO_ACT_AT_1ST_SAMPLE: + *val = LSM6DSV32X_SLEEP_TO_ACT_AT_1ST_SAMPLE; + break; + + case LSM6DSV32X_SLEEP_TO_ACT_AT_2ND_SAMPLE: + *val = LSM6DSV32X_SLEEP_TO_ACT_AT_2ND_SAMPLE; + break; + + case LSM6DSV32X_SLEEP_TO_ACT_AT_3RD_SAMPLE: + *val = LSM6DSV32X_SLEEP_TO_ACT_AT_3RD_SAMPLE; + break; + + case LSM6DSV32X_SLEEP_TO_ACT_AT_4th_SAMPLE: + *val = LSM6DSV32X_SLEEP_TO_ACT_AT_4th_SAMPLE; + break; + + default: + *val = LSM6DSV32X_SLEEP_TO_ACT_AT_1ST_SAMPLE; + break; + } + + return ret; +} + +/** + * @brief Selects the accelerometer data rate during Inactivity.[set] + * + * @param ctx read / write interface definitions + * @param val 1Hz875, 15Hz, 30Hz, 60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_act_sleep_xl_odr_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_act_sleep_xl_odr_t val) +{ + lsm6dsv32x_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret == 0) + { + inactivity_dur.xl_inact_odr = (uint8_t)val & 0x03U; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + return ret; +} + +/** + * @brief Selects the accelerometer data rate during Inactivity.[get] + * + * @param ctx read / write interface definitions + * @param val 1Hz875, 15Hz, 30Hz, 60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_act_sleep_xl_odr_t *val) +{ + lsm6dsv32x_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret != 0) + { + return ret; + } + + switch (inactivity_dur.xl_inact_odr) + { + case LSM6DSV32X_1Hz875: + *val = LSM6DSV32X_1Hz875; + break; + + case LSM6DSV32X_15Hz: + *val = LSM6DSV32X_15Hz; + break; + + case LSM6DSV32X_30Hz: + *val = LSM6DSV32X_30Hz; + break; + + case LSM6DSV32X_60Hz: + *val = LSM6DSV32X_60Hz; + break; + + default: + *val = LSM6DSV32X_1Hz875; + break; + } + + return ret; +} + +/** + * @brief Wakeup and activity/inactivity threshold.[set] + * + * @param ctx read / write interface definitions + * @param val Wakeup and activity/inactivity threshold. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_act_thresholds_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_act_thresholds_t *val) +{ + lsm6dsv32x_inactivity_ths_t inactivity_ths; + lsm6dsv32x_inactivity_dur_t inactivity_dur; + lsm6dsv32x_wake_up_ths_t wake_up_ths; + lsm6dsv32x_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } + + inactivity_dur.wu_inact_ths_w = val->inactivity_cfg.wu_inact_ths_w; + inactivity_dur.xl_inact_odr = val->inactivity_cfg.xl_inact_odr; + inactivity_dur.inact_dur = val->inactivity_cfg.inact_dur; + + inactivity_ths.inact_ths = val->inactivity_ths; + wake_up_ths.wk_ths = val->threshold; + wake_up_dur.wake_dur = val->duration; + + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + + return ret; +} + +/** + * @brief Wakeup and activity/inactivity threshold.[get] + * + * @param ctx read / write interface definitions + * @param val Wakeup and activity/inactivity threshold. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_act_thresholds_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_act_thresholds_t *val) +{ + lsm6dsv32x_inactivity_dur_t inactivity_dur; + lsm6dsv32x_inactivity_ths_t inactivity_ths; + lsm6dsv32x_wake_up_ths_t wake_up_ths; + lsm6dsv32x_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } + + val->inactivity_cfg.wu_inact_ths_w = inactivity_dur.wu_inact_ths_w; + val->inactivity_cfg.xl_inact_odr = inactivity_dur.xl_inact_odr; + val->inactivity_cfg.inact_dur = inactivity_dur.inact_dur; + + val->inactivity_ths = inactivity_ths.inact_ths; + val->threshold = wake_up_ths.wk_ths; + val->duration = wake_up_dur.wake_dur; + + return ret; +} + +/** + * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [set] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_act_wkup_time_windows_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_act_wkup_time_windows_t val) +{ + lsm6dsv32x_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + wake_up_dur.wake_dur = val.shock; + wake_up_dur.sleep_dur = val.quiet; + ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + } + + return ret; +} + +/** + * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [get] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv32x_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_act_wkup_time_windows_t *val) +{ + lsm6dsv32x_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret != 0) + { + return ret; + } + + val->shock = wake_up_dur.wake_dur; + val->quiet = wake_up_dur.sleep_dur; + + return ret; +} + +/** + * @} + * + */ diff --git a/sensor/stmemsc/lsm6dsv32x_STdC/driver/lsm6dsv32x_reg.h b/sensor/stmemsc/lsm6dsv32x_STdC/driver/lsm6dsv32x_reg.h new file mode 100644 index 00000000..af17681a --- /dev/null +++ b/sensor/stmemsc/lsm6dsv32x_STdC/driver/lsm6dsv32x_reg.h @@ -0,0 +1,5273 @@ +/** + ****************************************************************************** + * @file lsm6dsv32x_reg.h + * @author Sensors Software Solution Team + * @brief This file contains all the functions prototypes for the + * lsm6dsv32x_reg.c driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2024 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef LSM6DSV32X_REGS_H +#define LSM6DSV32X_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include + +/** @addtogroup LSM6DSV32X + * @{ + * + */ + +/** @defgroup Endianness definitions + * @{ + * + */ + +#ifndef DRV_BYTE_ORDER +#ifndef __BYTE_ORDER__ + +#define DRV_LITTLE_ENDIAN 1234 +#define DRV_BIG_ENDIAN 4321 + +/** if _BYTE_ORDER is not defined, choose the endianness of your architecture + * by uncommenting the define which fits your platform endianness + */ +//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN +#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN + +#else /* defined __BYTE_ORDER__ */ + +#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ +#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ +#define DRV_BYTE_ORDER __BYTE_ORDER__ + +#endif /* __BYTE_ORDER__*/ +#endif /* DRV_BYTE_ORDER */ + +/** + * @} + * + */ + +/** @defgroup STMicroelectronics sensors common types + * @{ + * + */ + +#ifndef MEMS_SHARED_TYPES +#define MEMS_SHARED_TYPES + +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} bitwise_t; + +#define PROPERTY_DISABLE (0U) +#define PROPERTY_ENABLE (1U) + +/** @addtogroup Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); +typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); + +typedef struct +{ + /** Component mandatory fields **/ + stmdev_write_ptr write_reg; + stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; + /** Customizable optional pointer **/ + void *handle; +} stmdev_ctx_t; + +/** + * @} + * + */ + +#endif /* MEMS_SHARED_TYPES */ + +#ifndef MEMS_UCF_SHARED_TYPES +#define MEMS_UCF_SHARED_TYPES + +/** @defgroup Generic address-data structure definition + * @brief This structure is useful to load a predefined configuration + * of a sensor. + * You can create a sensor configuration by your own or using + * Unico / Unicleo tools available on STMicroelectronics + * web site. + * + * @{ + * + */ + +typedef struct +{ + uint8_t address; + uint8_t data; +} ucf_line_t; + +/** + * @} + * + */ + +#endif /* MEMS_UCF_SHARED_TYPES */ + +/** + * @} + * + */ + +/** @defgroup LSM6DSV32X_Infos + * @{ + * + */ + +/** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ +#define LSM6DSV32X_I2C_ADD_L 0xD5U +#define LSM6DSV32X_I2C_ADD_H 0xD7U + +/** Device Identification (Who am I) **/ +#define LSM6DSV32X_ID 0x70U + +/** + * @} + * + */ + +/** @defgroup bitfields page main + * @{ + * + */ + +#define LSM6DSV32X_FUNC_CFG_ACCESS 0x1U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ois_ctrl_from_ui : 1; + uint8_t spi2_reset : 1; + uint8_t sw_por : 1; + uint8_t fsm_wr_ctrl_en : 1; + uint8_t not_used0 : 2; + uint8_t shub_reg_access : 1; + uint8_t emb_func_reg_access : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_reg_access : 1; + uint8_t shub_reg_access : 1; + uint8_t not_used0 : 2; + uint8_t fsm_wr_ctrl_en : 1; + uint8_t sw_por : 1; + uint8_t spi2_reset : 1; + uint8_t ois_ctrl_from_ui : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_func_cfg_access_t; + +#define LSM6DSV32X_PIN_CTRL 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 5; + uint8_t ibhr_por_en : 1; + uint8_t sdo_pu_en : 1; + uint8_t ois_pu_dis : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ois_pu_dis : 1; + uint8_t sdo_pu_en : 1; + uint8_t ibhr_por_en : 1; + uint8_t not_used0 : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_pin_ctrl_t; + +#define LSM6DSV32X_IF_CFG 0x3U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t i2c_i3c_disable : 1; + uint8_t not_used0 : 1; + uint8_t sim : 1; + uint8_t pp_od : 1; + uint8_t h_lactive : 1; + uint8_t asf_ctrl : 1; + uint8_t shub_pu_en : 1; + uint8_t sda_pu_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sda_pu_en : 1; + uint8_t shub_pu_en : 1; + uint8_t asf_ctrl : 1; + uint8_t h_lactive : 1; + uint8_t pp_od : 1; + uint8_t sim : 1; + uint8_t not_used0 : 1; + uint8_t i2c_i3c_disable : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_if_cfg_t; + +#define LSM6DSV32X_ODR_TRIG_CFG 0x6U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t odr_trig_nodr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t odr_trig_nodr : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_odr_trig_cfg_t; + +#define LSM6DSV32X_FIFO_CTRL1 0x7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wtm : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t wtm : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fifo_ctrl1_t; + +#define LSM6DSV32X_FIFO_CTRL2 0x8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xl_dualc_batch_from_fsm : 1; + uint8_t uncompr_rate : 2; + uint8_t not_used0 : 1; + uint8_t odr_chg_en : 1; + uint8_t not_used1 : 1; + uint8_t fifo_compr_rt_en : 1; + uint8_t stop_on_wtm : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t stop_on_wtm : 1; + uint8_t fifo_compr_rt_en : 1; + uint8_t not_used1 : 1; + uint8_t odr_chg_en : 1; + uint8_t not_used0 : 1; + uint8_t uncompr_rate : 2; + uint8_t xl_dualc_batch_from_fsm : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fifo_ctrl2_t; + +#define LSM6DSV32X_FIFO_CTRL3 0x9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bdr_xl : 4; + uint8_t bdr_gy : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bdr_gy : 4; + uint8_t bdr_xl : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fifo_ctrl3_t; + +#define LSM6DSV32X_FIFO_CTRL4 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_mode : 3; + uint8_t g_eis_fifo_en : 1; + uint8_t odr_t_batch : 2; + uint8_t dec_ts_batch : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dec_ts_batch : 2; + uint8_t odr_t_batch : 2; + uint8_t g_eis_fifo_en : 1; + uint8_t fifo_mode : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fifo_ctrl4_t; + +#define LSM6DSV32X_COUNTER_BDR_REG1 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t cnt_bdr_th : 2; + uint8_t not_used0 : 3; + uint8_t trig_counter_bdr : 2; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t trig_counter_bdr : 2; + uint8_t not_used0 : 3; + uint8_t cnt_bdr_th : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_counter_bdr_reg1_t; + +#define LSM6DSV32X_COUNTER_BDR_REG2 0x0CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t cnt_bdr_th : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t cnt_bdr_th : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_counter_bdr_reg2_t; + +#define LSM6DSV32X_INT1_CTRL 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_drdy_xl : 1; + uint8_t int1_drdy_g : 1; + uint8_t not_used0 : 1; + uint8_t int1_fifo_th : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_fifo_full : 1; + uint8_t int1_cnt_bdr : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t int1_cnt_bdr : 1; + uint8_t int1_fifo_full : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_fifo_th : 1; + uint8_t not_used0 : 1; + uint8_t int1_drdy_g : 1; + uint8_t int1_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_int1_ctrl_t; + +#define LSM6DSV32X_INT2_CTRL 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_drdy_xl : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_g_eis : 1; + uint8_t int2_fifo_th : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_fifo_full : 1; + uint8_t int2_cnt_bdr : 1; + uint8_t int2_emb_func_endop : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_emb_func_endop : 1; + uint8_t int2_cnt_bdr : 1; + uint8_t int2_fifo_full : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_fifo_th : 1; + uint8_t int2_drdy_g_eis : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_int2_ctrl_t; + +#define LSM6DSV32X_WHO_AM_I 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t id : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t id : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_who_am_i_t; + +#define LSM6DSV32X_CTRL1 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t odr_xl : 4; + uint8_t op_mode_xl : 3; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t op_mode_xl : 3; + uint8_t odr_xl : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ctrl1_t; + +#define LSM6DSV32X_CTRL2 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t odr_g : 4; + uint8_t op_mode_g : 3; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t op_mode_g : 3; + uint8_t odr_g : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ctrl2_t; + +#define LSM6DSV32X_CTRL3 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sw_reset : 1; + uint8_t not_used0 : 1; + uint8_t if_inc : 1; + uint8_t not_used1 : 3; + uint8_t bdu : 1; + uint8_t boot : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t boot : 1; + uint8_t bdu : 1; + uint8_t not_used1 : 3; + uint8_t if_inc : 1; + uint8_t not_used0 : 1; + uint8_t sw_reset : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ctrl3_t; + +#define LSM6DSV32X_CTRL4 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_in_lh : 1; + uint8_t drdy_pulsed : 1; + uint8_t int2_drdy_temp : 1; + uint8_t drdy_mask : 1; + uint8_t int2_on_int1 : 1; + uint8_t not_used0 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 3; + uint8_t int2_on_int1 : 1; + uint8_t drdy_mask : 1; + uint8_t int2_drdy_temp : 1; + uint8_t drdy_pulsed : 1; + uint8_t int2_in_lh : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ctrl4_t; + +#define LSM6DSV32X_CTRL5 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int_en_i3c : 1; + uint8_t bus_act_sel : 2; + uint8_t not_used0 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 5; + uint8_t bus_act_sel : 2; + uint8_t int_en_i3c : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ctrl5_t; + +#define LSM6DSV32X_CTRL6 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_g : 4; + uint8_t lpf1_g_bw : 3; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t lpf1_g_bw : 3; + uint8_t fs_g : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ctrl6_t; + +#define LSM6DSV32X_CTRL7 0x16U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t lpf1_g_en : 1; + uint8_t not_used0 : 3; + uint8_t ah_qvar_c_zin : 2; + uint8_t int2_drdy_ah_qvar : 1; + uint8_t ah_qvar_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ah_qvar_en : 1; + uint8_t int2_drdy_ah_qvar : 1; + uint8_t ah_qvar_c_zin : 2; + uint8_t not_used0 : 3; + uint8_t lpf1_g_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ctrl7_t; + +#define LSM6DSV32X_CTRL8 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_xl : 2; + uint8_t not_used0 : 1; + uint8_t xl_dualc_en : 1; + uint8_t not_used1 : 1; + uint8_t hp_lpf2_xl_bw : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t hp_lpf2_xl_bw : 3; + uint8_t not_used1 : 1; + uint8_t xl_dualc_en : 1; + uint8_t not_used0 : 1; + uint8_t fs_xl : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ctrl8_t; + +#define LSM6DSV32X_CTRL9 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t usr_off_on_out : 1; + uint8_t usr_off_w : 1; + uint8_t not_used0 : 1; + uint8_t lpf2_xl_en : 1; + uint8_t hp_slope_xl_en : 1; + uint8_t xl_fastsettl_mode : 1; + uint8_t hp_ref_mode_xl : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t hp_ref_mode_xl : 1; + uint8_t xl_fastsettl_mode : 1; + uint8_t hp_slope_xl_en : 1; + uint8_t lpf2_xl_en : 1; + uint8_t not_used0 : 1; + uint8_t usr_off_w : 1; + uint8_t usr_off_on_out : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ctrl9_t; + +#define LSM6DSV32X_CTRL10 0x19U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t st_xl : 2; + uint8_t st_g : 2; + uint8_t not_used0 : 2; + uint8_t emb_func_debug : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t emb_func_debug : 1; + uint8_t not_used0 : 2; + uint8_t st_g : 2; + uint8_t st_xl : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ctrl10_t; + +#define LSM6DSV32X_CTRL_STATUS 0x1AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t fsm_wr_ctrl_status : 1; + uint8_t not_used1 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 5; + uint8_t fsm_wr_ctrl_status : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ctrl_status_t; + +#define LSM6DSV32X_FIFO_STATUS1 0x1BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t diff_fifo : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t diff_fifo : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fifo_status1_t; + +#define LSM6DSV32X_FIFO_STATUS2 0x1CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t diff_fifo : 1; + uint8_t not_used0 : 2; + uint8_t fifo_ovr_latched : 1; + uint8_t counter_bdr_ia : 1; + uint8_t fifo_full_ia : 1; + uint8_t fifo_ovr_ia : 1; + uint8_t fifo_wtm_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_wtm_ia : 1; + uint8_t fifo_ovr_ia : 1; + uint8_t fifo_full_ia : 1; + uint8_t counter_bdr_ia : 1; + uint8_t fifo_ovr_latched : 1; + uint8_t not_used0 : 2; + uint8_t diff_fifo : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fifo_status2_t; + +#define LSM6DSV32X_ALL_INT_SRC 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ia : 1; + uint8_t wu_ia : 1; + uint8_t tap_ia : 1; + uint8_t not_used0 : 1; + uint8_t d6d_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t shub_ia : 1; + uint8_t emb_func_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_ia : 1; + uint8_t shub_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t d6d_ia : 1; + uint8_t not_used0 : 1; + uint8_t tap_ia : 1; + uint8_t wu_ia : 1; + uint8_t ff_ia : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_all_int_src_t; + +#define LSM6DSV32X_STATUS_REG 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xlda : 1; + uint8_t gda : 1; + uint8_t tda : 1; + uint8_t ah_qvarda : 1; + uint8_t gda_eis : 1; + uint8_t ois_drdy : 1; + uint8_t not_used0 : 1; + uint8_t timestamp_endcount : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp_endcount : 1; + uint8_t not_used0 : 1; + uint8_t ois_drdy : 1; + uint8_t gda_eis : 1; + uint8_t ah_qvarda : 1; + uint8_t tda : 1; + uint8_t gda : 1; + uint8_t xlda : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_status_reg_t; + +#define LSM6DSV32X_OUT_TEMP_L 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_out_temp_l_t; + +#define LSM6DSV32X_OUT_TEMP_H 0x21U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_out_temp_h_t; + +#define LSM6DSV32X_OUTX_L_G 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_outx_l_g_t; + +#define LSM6DSV32X_OUTX_H_G 0x23U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_outx_h_g_t; + +#define LSM6DSV32X_OUTY_L_G 0x24U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_outy_l_g_t; + +#define LSM6DSV32X_OUTY_H_G 0x25U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_outy_h_g_t; + +#define LSM6DSV32X_OUTZ_L_G 0x26U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_outz_l_g_t; + +#define LSM6DSV32X_OUTZ_H_G 0x27U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_g : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_outz_h_g_t; + +#define LSM6DSV32X_OUTX_L_A 0x28U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_outx_l_a_t; + +#define LSM6DSV32X_OUTX_H_A 0x29U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_outx_h_a_t; + +#define LSM6DSV32X_OUTY_L_A 0x2AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_outy_l_a_t; + +#define LSM6DSV32X_OUTY_H_A 0x2BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_outy_h_a_t; + +#define LSM6DSV32X_OUTZ_L_A 0x2CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_outz_l_a_t; + +#define LSM6DSV32X_OUTZ_H_A 0x2DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_a : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_outz_h_a_t; + +#define LSM6DSV32X_UI_OUTX_L_G_OIS_EIS 0x2EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outx_g_ois_eis : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outx_g_ois_eis : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ui_outx_l_g_ois_eis_t; + +#define LSM6DSV32X_UI_OUTX_H_G_OIS_EIS 0x2FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outx_g_ois_eis : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outx_g_ois_eis : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ui_outx_h_g_ois_eis_t; + +#define LSM6DSV32X_UI_OUTY_L_G_OIS_EIS 0x30U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outy_g_ois_eis : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outy_g_ois_eis : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ui_outy_l_g_ois_eis_t; + +#define LSM6DSV32X_UI_OUTY_H_G_OIS_EIS 0x31U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outy_g_ois_eis : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outy_g_ois_eis : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ui_outy_h_g_ois_eis_t; + +#define LSM6DSV32X_UI_OUTZ_L_G_OIS_EIS 0x32U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outz_g_ois_eis : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outz_g_ois_eis : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ui_outz_l_g_ois_eis_t; + +#define LSM6DSV32X_UI_OUTZ_H_G_OIS_EIS 0x33U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outz_g_ois_eis : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outz_g_ois_eis : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ui_outz_h_g_ois_eis_t; + +#define LSM6DSV32X_UI_OUTX_L_A_OIS_DUALC 0x34U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outx_a_ois_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outx_a_ois_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ui_outx_l_a_ois_dualc_t; + +#define LSM6DSV32X_UI_OUTX_H_A_OIS_DUALC 0x35U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outx_a_ois_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outx_a_ois_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ui_outx_h_a_ois_dualc_t; + +#define LSM6DSV32X_UI_OUTY_L_A_OIS_DUALC 0x36U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outy_a_ois_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outy_a_ois_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ui_outy_l_a_ois_dualc_t; + +#define LSM6DSV32X_UI_OUTY_H_A_OIS_DUALC 0x37U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outy_a_ois_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outy_a_ois_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ui_outy_h_a_ois_dualc_t; + +#define LSM6DSV32X_UI_OUTZ_L_A_OIS_DUALC 0x38U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outz_a_ois_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outz_a_ois_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ui_outz_l_a_ois_dualc_t; + +#define LSM6DSV32X_UI_OUTZ_H_A_OIS_DUALC 0x39U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outz_a_ois_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outz_a_ois_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ui_outz_h_a_ois_dualc_t; + +#define LSM6DSV32X_AH_QVAR_OUT_L 0x3AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ah_qvar : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ah_qvar : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ah_qvar_out_l_t; + +#define LSM6DSV32X_AH_QVAR_OUT_H 0x3BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ah_qvar : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ah_qvar : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ah_qvar_out_h_t; + +#define LSM6DSV32X_TIMESTAMP0 0x40U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_timestamp0_t; + +#define LSM6DSV32X_TIMESTAMP1 0x41U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_timestamp1_t; + +#define LSM6DSV32X_TIMESTAMP2 0x42U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_timestamp2_t; + +#define LSM6DSV32X_TIMESTAMP3 0x43U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_timestamp3_t; + +#define LSM6DSV32X_UI_STATUS_REG_OIS 0x44U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xlda_ois : 1; + uint8_t gda_ois : 1; + uint8_t gyro_settling : 1; + uint8_t not_used0 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 5; + uint8_t gyro_settling : 1; + uint8_t gda_ois : 1; + uint8_t xlda_ois : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ui_status_reg_ois_t; + +#define LSM6DSV32X_WAKE_UP_SRC 0x45U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t z_wu : 1; + uint8_t y_wu : 1; + uint8_t x_wu : 1; + uint8_t wu_ia : 1; + uint8_t sleep_state : 1; + uint8_t ff_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t sleep_change_ia : 1; + uint8_t ff_ia : 1; + uint8_t sleep_state : 1; + uint8_t wu_ia : 1; + uint8_t x_wu : 1; + uint8_t y_wu : 1; + uint8_t z_wu : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_wake_up_src_t; + +#define LSM6DSV32X_TAP_SRC 0x46U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t z_tap : 1; + uint8_t y_tap : 1; + uint8_t x_tap : 1; + uint8_t tap_sign : 1; + uint8_t double_tap : 1; + uint8_t single_tap : 1; + uint8_t tap_ia : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t tap_ia : 1; + uint8_t single_tap : 1; + uint8_t double_tap : 1; + uint8_t tap_sign : 1; + uint8_t x_tap : 1; + uint8_t y_tap : 1; + uint8_t z_tap : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_tap_src_t; + +#define LSM6DSV32X_D6D_SRC 0x47U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xl : 1; + uint8_t xh : 1; + uint8_t yl : 1; + uint8_t yh : 1; + uint8_t zl : 1; + uint8_t zh : 1; + uint8_t d6d_ia : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t d6d_ia : 1; + uint8_t zh : 1; + uint8_t zl : 1; + uint8_t yh : 1; + uint8_t yl : 1; + uint8_t xh : 1; + uint8_t xl : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_d6d_src_t; + +#define LSM6DSV32X_STATUS_MASTER_MAINPAGE 0x48U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sens_hub_endop : 1; + uint8_t not_used0 : 2; + uint8_t slave0_nack : 1; + uint8_t slave1_nack : 1; + uint8_t slave2_nack : 1; + uint8_t slave3_nack : 1; + uint8_t wr_once_done : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t wr_once_done : 1; + uint8_t slave3_nack : 1; + uint8_t slave2_nack : 1; + uint8_t slave1_nack : 1; + uint8_t slave0_nack : 1; + uint8_t not_used0 : 2; + uint8_t sens_hub_endop : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_status_master_mainpage_t; + +#define LSM6DSV32X_EMB_FUNC_STATUS_MAINPAGE 0x49U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t is_step_det : 1; + uint8_t is_tilt : 1; + uint8_t is_sigmot : 1; + uint8_t not_used1 : 1; + uint8_t is_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t is_sigmot : 1; + uint8_t is_tilt : 1; + uint8_t is_step_det : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_emb_func_status_mainpage_t; + +#define LSM6DSV32X_FSM_STATUS_MAINPAGE 0x4AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm8 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_status_mainpage_t; + +#define LSM6DSV32X_MLC_STATUS_MAINPAGE 0x4BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_mlc1 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t is_mlc4 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_mlc_status_mainpage_t; + +#define LSM6DSV32X_INTERNAL_FREQ 0x4FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t freq_fine : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t freq_fine : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_internal_freq_t; + +#define LSM6DSV32X_FUNCTIONS_ENABLE 0x50U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t inact_en : 2; + uint8_t not_used0 : 1; + uint8_t dis_rst_lir_all_int : 1; + uint8_t not_used1 : 2; + uint8_t timestamp_en : 1; + uint8_t interrupts_enable : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t interrupts_enable : 1; + uint8_t timestamp_en : 1; + uint8_t not_used1 : 2; + uint8_t dis_rst_lir_all_int : 1; + uint8_t not_used0 : 1; + uint8_t inact_en : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_functions_enable_t; + +#define LSM6DSV32X_DEN 0x51U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t den_xl_g : 1; + uint8_t den_z : 1; + uint8_t den_y : 1; + uint8_t den_x : 1; + uint8_t den_xl_en : 1; + uint8_t lvl2_en : 1; + uint8_t lvl1_en : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t lvl1_en : 1; + uint8_t lvl2_en : 1; + uint8_t den_xl_en : 1; + uint8_t den_x : 1; + uint8_t den_y : 1; + uint8_t den_z : 1; + uint8_t den_xl_g : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_den_t; + +#define LSM6DSV32X_INACTIVITY_DUR 0x54U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t inact_dur : 2; + uint8_t xl_inact_odr : 2; + uint8_t wu_inact_ths_w : 3; + uint8_t sleep_status_on_int : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sleep_status_on_int : 1; + uint8_t wu_inact_ths_w : 3; + uint8_t xl_inact_odr : 2; + uint8_t inact_dur : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_inactivity_dur_t; + +#define LSM6DSV32X_INACTIVITY_THS 0x55U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t inact_ths : 6; + uint8_t not_used0 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 2; + uint8_t inact_ths : 6; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_inactivity_ths_t; + +#define LSM6DSV32X_TAP_CFG0 0x56U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t lir : 1; + uint8_t tap_z_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_x_en : 1; + uint8_t slope_fds : 1; + uint8_t hw_func_mask_xl_settl : 1; + uint8_t low_pass_on_6d : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t low_pass_on_6d : 1; + uint8_t hw_func_mask_xl_settl : 1; + uint8_t slope_fds : 1; + uint8_t tap_x_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_z_en : 1; + uint8_t lir : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_tap_cfg0_t; + +#define LSM6DSV32X_TAP_CFG1 0x57U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths_x : 5; + uint8_t tap_priority : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tap_priority : 3; + uint8_t tap_ths_x : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_tap_cfg1_t; + +#define LSM6DSV32X_TAP_CFG2 0x58U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths_y : 5; + uint8_t not_used0 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 3; + uint8_t tap_ths_y : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_tap_cfg2_t; + +#define LSM6DSV32X_TAP_THS_6D 0x59U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths_z : 5; + uint8_t sixd_ths : 2; + uint8_t d4d_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t d4d_en : 1; + uint8_t sixd_ths : 2; + uint8_t tap_ths_z : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_tap_ths_6d_t; + +#define LSM6DSV32X_TAP_DUR 0x5AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t shock : 2; + uint8_t quiet : 2; + uint8_t dur : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dur : 4; + uint8_t quiet : 2; + uint8_t shock : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_tap_dur_t; + +#define LSM6DSV32X_WAKE_UP_THS 0x5BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wk_ths : 6; + uint8_t usr_off_on_wu : 1; + uint8_t single_double_tap : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t single_double_tap : 1; + uint8_t usr_off_on_wu : 1; + uint8_t wk_ths : 6; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_wake_up_ths_t; + +#define LSM6DSV32X_WAKE_UP_DUR 0x5CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sleep_dur : 4; + uint8_t not_used0 : 1; + uint8_t wake_dur : 2; + uint8_t ff_dur : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 1; + uint8_t wake_dur : 2; + uint8_t not_used0 : 1; + uint8_t sleep_dur : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_wake_up_dur_t; + +#define LSM6DSV32X_FREE_FALL 0x5DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ths : 3; + uint8_t ff_dur : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 5; + uint8_t ff_ths : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_free_fall_t; + +#define LSM6DSV32X_MD1_CFG 0x5EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_shub : 1; + uint8_t int1_emb_func : 1; + uint8_t int1_6d : 1; + uint8_t int1_double_tap : 1; + uint8_t int1_ff : 1; + uint8_t int1_wu : 1; + uint8_t int1_single_tap : 1; + uint8_t int1_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_sleep_change : 1; + uint8_t int1_single_tap : 1; + uint8_t int1_wu : 1; + uint8_t int1_ff : 1; + uint8_t int1_double_tap : 1; + uint8_t int1_6d : 1; + uint8_t int1_emb_func : 1; + uint8_t int1_shub : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_md1_cfg_t; + +#define LSM6DSV32X_MD2_CFG 0x5FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_timestamp : 1; + uint8_t int2_emb_func : 1; + uint8_t int2_6d : 1; + uint8_t int2_double_tap : 1; + uint8_t int2_ff : 1; + uint8_t int2_wu : 1; + uint8_t int2_single_tap : 1; + uint8_t int2_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_sleep_change : 1; + uint8_t int2_single_tap : 1; + uint8_t int2_wu : 1; + uint8_t int2_ff : 1; + uint8_t int2_double_tap : 1; + uint8_t int2_6d : 1; + uint8_t int2_emb_func : 1; + uint8_t int2_timestamp : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_md2_cfg_t; + +#define LSM6DSV32X_HAODR_CFG 0x62U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t haodr_sel : 2; + uint8_t not_used0 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 6; + uint8_t haodr_sel : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_haodr_cfg_t; + +#define LSM6DSV32X_EMB_FUNC_CFG 0x63U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t emb_func_disable : 1; + uint8_t emb_func_irq_mask_xl_settl : 1; + uint8_t emb_func_irq_mask_g_settl : 1; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t emb_func_irq_mask_g_settl : 1; + uint8_t emb_func_irq_mask_xl_settl : 1; + uint8_t emb_func_disable : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_emb_func_cfg_t; + +#define LSM6DSV32X_UI_HANDSHAKE_CTRL 0x64U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_shared_req : 1; + uint8_t ui_shared_ack : 1; + uint8_t not_used0 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 6; + uint8_t ui_shared_ack : 1; + uint8_t ui_shared_req : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ui_handshake_ctrl_t; + +#define LSM6DSV32X_UI_SPI2_SHARED_0 0x65U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_spi2_shared : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_spi2_shared : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ui_spi2_shared_0_t; + +#define LSM6DSV32X_UI_SPI2_SHARED_1 0x66U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_spi2_shared : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_spi2_shared : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ui_spi2_shared_1_t; + +#define LSM6DSV32X_UI_SPI2_SHARED_2 0x67U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_spi2_shared : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_spi2_shared : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ui_spi2_shared_2_t; + +#define LSM6DSV32X_UI_SPI2_SHARED_3 0x68U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_spi2_shared : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_spi2_shared : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ui_spi2_shared_3_t; + +#define LSM6DSV32X_UI_SPI2_SHARED_4 0x69U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_spi2_shared : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_spi2_shared : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ui_spi2_shared_4_t; + +#define LSM6DSV32X_UI_SPI2_SHARED_5 0x6AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_spi2_shared : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_spi2_shared : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ui_spi2_shared_5_t; + +#define LSM6DSV32X_CTRL_EIS 0x6BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_g_eis : 3; + uint8_t g_eis_on_g_ois_out_reg : 1; + uint8_t lpf_g_eis_bw : 1; + uint8_t not_used0 : 1; + uint8_t odr_g_eis : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t odr_g_eis : 2; + uint8_t not_used0 : 1; + uint8_t lpf_g_eis_bw : 1; + uint8_t g_eis_on_g_ois_out_reg : 1; + uint8_t fs_g_eis : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ctrl_eis_t; + +#define LSM6DSV32X_UI_INT_OIS 0x6FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t st_ois_clampdis : 1; + uint8_t not_used1 : 1; + uint8_t drdy_mask_ois : 1; + uint8_t int2_drdy_ois : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_drdy_ois : 1; + uint8_t drdy_mask_ois : 1; + uint8_t not_used1 : 1; + uint8_t st_ois_clampdis : 1; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ui_int_ois_t; + +#define LSM6DSV32X_UI_CTRL1_OIS 0x70U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_read_en : 1; + uint8_t ois_g_en : 1; + uint8_t ois_xl_en : 1; + uint8_t not_used0 : 2; + uint8_t sim_ois : 1; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t sim_ois : 1; + uint8_t not_used0 : 2; + uint8_t ois_xl_en : 1; + uint8_t ois_g_en : 1; + uint8_t spi2_read_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ui_ctrl1_ois_t; + +#define LSM6DSV32X_UI_CTRL2_OIS 0x71U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_g_ois : 3; + uint8_t lpf1_g_ois_bw : 2; + uint8_t not_used0 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 3; + uint8_t lpf1_g_ois_bw : 2; + uint8_t fs_g_ois : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ui_ctrl2_ois_t; + +#define LSM6DSV32X_UI_CTRL3_OIS 0x72U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_xl_ois : 2; + uint8_t not_used0 : 1; + uint8_t lpf_xl_ois_bw : 3; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t lpf_xl_ois_bw : 3; + uint8_t not_used0 : 1; + uint8_t fs_xl_ois : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ui_ctrl3_ois_t; + +#define LSM6DSV32X_X_OFS_USR 0x73U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t x_ofs_usr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t x_ofs_usr : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_x_ofs_usr_t; + +#define LSM6DSV32X_Y_OFS_USR 0x74U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t y_ofs_usr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t y_ofs_usr : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_y_ofs_usr_t; + +#define LSM6DSV32X_Z_OFS_USR 0x75U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t z_ofs_usr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t z_ofs_usr : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_z_ofs_usr_t; + +#define LSM6DSV32X_FIFO_DATA_OUT_TAG 0x78U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t tag_cnt : 2; + uint8_t tag_sensor : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tag_sensor : 5; + uint8_t tag_cnt : 2; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fifo_data_out_tag_t; + +#define LSM6DSV32X_FIFO_DATA_OUT_X_L 0x79U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fifo_data_out_x_l_t; + +#define LSM6DSV32X_FIFO_DATA_OUT_X_H 0x7AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fifo_data_out_x_h_t; + +#define LSM6DSV32X_FIFO_DATA_OUT_Y_L 0x7BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fifo_data_out_y_l_t; + +#define LSM6DSV32X_FIFO_DATA_OUT_Y_H 0x7CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fifo_data_out_y_h_t; + +#define LSM6DSV32X_FIFO_DATA_OUT_Z_L 0x7DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fifo_data_out_z_l_t; + +#define LSM6DSV32X_FIFO_DATA_OUT_Z_H 0x7EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fifo_data_out_z_h_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page spi2 + * @{ + * + */ + +#define LSM6DSV32X_SPI2_WHO_AM_I 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t id : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t id : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_spi2_who_am_i_t; + +#define LSM6DSV32X_SPI2_STATUS_REG_OIS 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xlda : 1; + uint8_t gda : 1; + uint8_t gyro_settling : 1; + uint8_t not_used0 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 5; + uint8_t gyro_settling : 1; + uint8_t gda : 1; + uint8_t xlda : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_spi2_status_reg_ois_t; + +#define LSM6DSV32X_SPI2_OUT_TEMP_L 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_spi2_out_temp_l_t; + +#define LSM6DSV32X_SPI2_OUT_TEMP_H 0x21U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_spi2_out_temp_h_t; + +#define LSM6DSV32X_SPI2_OUTX_L_G_OIS 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outx_g_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outx_g_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_spi2_outx_l_g_ois_t; + +#define LSM6DSV32X_SPI2_OUTX_H_G_OIS 0x23U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outx_g_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outx_g_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_spi2_outx_h_g_ois_t; + +#define LSM6DSV32X_SPI2_OUTY_L_G_OIS 0x24U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outy_g_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outy_g_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_spi2_outy_l_g_ois_t; + +#define LSM6DSV32X_SPI2_OUTY_H_G_OIS 0x25U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outy_g_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outy_g_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_spi2_outy_h_g_ois_t; + +#define LSM6DSV32X_SPI2_OUTZ_L_G_OIS 0x26U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outz_g_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outz_g_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_spi2_outz_l_g_ois_t; + +#define LSM6DSV32X_SPI2_OUTZ_H_G_OIS 0x27U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outz_g_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outz_g_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_spi2_outz_h_g_ois_t; + +#define LSM6DSV32X_SPI2_OUTX_L_A_OIS 0x28U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outx_a_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outx_a_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_spi2_outx_l_a_ois_t; + +#define LSM6DSV32X_SPI2_OUTX_H_A_OIS 0x29U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outx_a_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outx_a_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_spi2_outx_h_a_ois_t; + +#define LSM6DSV32X_SPI2_OUTY_L_A_OIS 0x2AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outy_a_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outy_a_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_spi2_outy_l_a_ois_t; + +#define LSM6DSV32X_SPI2_OUTY_H_A_OIS 0x2BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outy_a_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outy_a_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_spi2_outy_h_a_ois_t; + +#define LSM6DSV32X_SPI2_OUTZ_L_A_OIS 0x2CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outz_a_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outz_a_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_spi2_outz_l_a_ois_t; + +#define LSM6DSV32X_SPI2_OUTZ_H_A_OIS 0x2DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_outz_a_ois : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t spi2_outz_a_ois : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_spi2_outz_h_a_ois_t; + +#define LSM6DSV32X_SPI2_HANDSHAKE_CTRL 0x6EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_shared_ack : 1; + uint8_t spi2_shared_req : 1; + uint8_t not_used0 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 6; + uint8_t spi2_shared_req : 1; + uint8_t spi2_shared_ack : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_spi2_handshake_ctrl_t; + +#define LSM6DSV32X_SPI2_INT_OIS 0x6FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t st_xl_ois : 2; + uint8_t st_g_ois : 2; + uint8_t st_ois_clampdis : 1; + uint8_t not_used0 : 1; + uint8_t drdy_mask_ois : 1; + uint8_t int2_drdy_ois : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_drdy_ois : 1; + uint8_t drdy_mask_ois : 1; + uint8_t not_used0 : 1; + uint8_t st_ois_clampdis : 1; + uint8_t st_g_ois : 2; + uint8_t st_xl_ois : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_spi2_int_ois_t; + +#define LSM6DSV32X_SPI2_CTRL1_OIS 0x70U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t spi2_read_en : 1; + uint8_t ois_g_en : 1; + uint8_t ois_xl_en : 1; + uint8_t not_used0 : 2; + uint8_t sim_ois : 1; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t sim_ois : 1; + uint8_t not_used0 : 2; + uint8_t ois_xl_en : 1; + uint8_t ois_g_en : 1; + uint8_t spi2_read_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_spi2_ctrl1_ois_t; + +#define LSM6DSV32X_SPI2_CTRL2_OIS 0x71U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_g_ois : 3; + uint8_t lpf1_g_ois_bw : 2; + uint8_t not_used0 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 3; + uint8_t lpf1_g_ois_bw : 2; + uint8_t fs_g_ois : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_spi2_ctrl2_ois_t; + +#define LSM6DSV32X_SPI2_CTRL3_OIS 0x72U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_xl_ois : 2; + uint8_t not_used0 : 1; + uint8_t lpf_xl_ois_bw : 3; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t lpf_xl_ois_bw : 3; + uint8_t not_used0 : 1; + uint8_t fs_xl_ois : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_spi2_ctrl3_ois_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page embedded + * @{ + * + */ + +#define LSM6DSV32X_PAGE_SEL 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t page_sel : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_sel : 4; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_page_sel_t; + +#define LSM6DSV32X_EMB_FUNC_EN_A 0x4U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t sflp_game_en : 1; + uint8_t not_used2 : 1; + uint8_t pedo_en : 1; + uint8_t tilt_en : 1; + uint8_t sign_motion_en : 1; + uint8_t not_used1 : 1; + uint8_t mlc_before_fsm_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_before_fsm_en : 1; + uint8_t not_used1 : 1; + uint8_t sign_motion_en : 1; + uint8_t tilt_en : 1; + uint8_t pedo_en : 1; + uint8_t not_used2 : 1; + uint8_t sflp_game_en : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_emb_func_en_a_t; + +#define LSM6DSV32X_EMB_FUNC_EN_B 0x5U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_en : 1; + uint8_t not_used0 : 2; + uint8_t fifo_compr_en : 1; + uint8_t mlc_en : 1; + uint8_t not_used1 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 3; + uint8_t mlc_en : 1; + uint8_t fifo_compr_en : 1; + uint8_t not_used0 : 2; + uint8_t fsm_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_emb_func_en_b_t; + +#define LSM6DSV32X_EMB_FUNC_EXEC_STATUS 0x7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t emb_func_endop : 1; + uint8_t emb_func_exec_ovr : 1; + uint8_t not_used0 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 6; + uint8_t emb_func_exec_ovr : 1; + uint8_t emb_func_endop : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_emb_func_exec_status_t; + +#define LSM6DSV32X_PAGE_ADDRESS 0x8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t page_addr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_addr : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_page_address_t; + +#define LSM6DSV32X_PAGE_VALUE 0x9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t page_value : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_value : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_page_value_t; + +#define LSM6DSV32X_EMB_FUNC_INT1 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t int1_step_detector : 1; + uint8_t int1_tilt : 1; + uint8_t int1_sig_mot : 1; + uint8_t not_used1 : 1; + uint8_t int1_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t int1_sig_mot : 1; + uint8_t int1_tilt : 1; + uint8_t int1_step_detector : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_emb_func_int1_t; + +#define LSM6DSV32X_FSM_INT1 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_fsm1 : 1; + uint8_t int1_fsm2 : 1; + uint8_t int1_fsm3 : 1; + uint8_t int1_fsm4 : 1; + uint8_t int1_fsm5 : 1; + uint8_t int1_fsm6 : 1; + uint8_t int1_fsm7 : 1; + uint8_t int1_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm8 : 1; + uint8_t int1_fsm7 : 1; + uint8_t int1_fsm6 : 1; + uint8_t int1_fsm5 : 1; + uint8_t int1_fsm4 : 1; + uint8_t int1_fsm3 : 1; + uint8_t int1_fsm2 : 1; + uint8_t int1_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_int1_t; + +#define LSM6DSV32X_MLC_INT1 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_mlc1 : 1; + uint8_t int1_mlc2 : 1; + uint8_t int1_mlc3 : 1; + uint8_t int1_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t int1_mlc4 : 1; + uint8_t int1_mlc3 : 1; + uint8_t int1_mlc2 : 1; + uint8_t int1_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_mlc_int1_t; + +#define LSM6DSV32X_EMB_FUNC_INT2 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t int2_step_detector : 1; + uint8_t int2_tilt : 1; + uint8_t int2_sig_mot : 1; + uint8_t not_used1 : 1; + uint8_t int2_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t int2_sig_mot : 1; + uint8_t int2_tilt : 1; + uint8_t int2_step_detector : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_emb_func_int2_t; + +#define LSM6DSV32X_FSM_INT2 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_fsm1 : 1; + uint8_t int2_fsm2 : 1; + uint8_t int2_fsm3 : 1; + uint8_t int2_fsm4 : 1; + uint8_t int2_fsm5 : 1; + uint8_t int2_fsm6 : 1; + uint8_t int2_fsm7 : 1; + uint8_t int2_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm8 : 1; + uint8_t int2_fsm7 : 1; + uint8_t int2_fsm6 : 1; + uint8_t int2_fsm5 : 1; + uint8_t int2_fsm4 : 1; + uint8_t int2_fsm3 : 1; + uint8_t int2_fsm2 : 1; + uint8_t int2_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_int2_t; + +#define LSM6DSV32X_MLC_INT2 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_mlc1 : 1; + uint8_t int2_mlc2 : 1; + uint8_t int2_mlc3 : 1; + uint8_t int2_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t int2_mlc4 : 1; + uint8_t int2_mlc3 : 1; + uint8_t int2_mlc2 : 1; + uint8_t int2_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_mlc_int2_t; + +#define LSM6DSV32X_EMB_FUNC_STATUS 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t is_step_det : 1; + uint8_t is_tilt : 1; + uint8_t is_sigmot : 1; + uint8_t not_used1 : 1; + uint8_t is_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t is_sigmot : 1; + uint8_t is_tilt : 1; + uint8_t is_step_det : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_emb_func_status_t; + +#define LSM6DSV32X_FSM_STATUS 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm8 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_status_t; + +#define LSM6DSV32X_MLC_STATUS 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_mlc1 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t is_mlc4 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_mlc_status_t; + +#define LSM6DSV32X_PAGE_RW 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 5; + uint8_t page_read : 1; + uint8_t page_write : 1; + uint8_t emb_func_lir : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_lir : 1; + uint8_t page_write : 1; + uint8_t page_read : 1; + uint8_t not_used0 : 5; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_page_rw_t; + +#define LSM6DSV32X_EMB_FUNC_FIFO_EN_A 0x44U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t sflp_game_fifo_en : 1; + uint8_t not_used1 : 2; + uint8_t sflp_gravity_fifo_en : 1; + uint8_t sflp_gbias_fifo_en : 1; + uint8_t step_counter_fifo_en : 1; + uint8_t mlc_fifo_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_fifo_en : 1; + uint8_t step_counter_fifo_en : 1; + uint8_t sflp_gbias_fifo_en : 1; + uint8_t sflp_gravity_fifo_en : 1; + uint8_t not_used1 : 2; + uint8_t sflp_game_fifo_en : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_emb_func_fifo_en_a_t; + +#define LSM6DSV32X_EMB_FUNC_FIFO_EN_B 0x45U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t mlc_filter_feature_fifo_en : 1; + uint8_t not_used1 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 6; + uint8_t mlc_filter_feature_fifo_en : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_emb_func_fifo_en_b_t; + +#define LSM6DSV32X_FSM_ENABLE 0x46U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm1_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm8_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm8_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm1_en : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_enable_t; + +#define LSM6DSV32X_FSM_LONG_COUNTER_L 0x48U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_long_counter_l_t; + +#define LSM6DSV32X_FSM_LONG_COUNTER_H 0x49U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_long_counter_h_t; + +#define LSM6DSV32X_INT_ACK_MASK 0x4BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t iack_mask : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t iack_mask : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_int_ack_mask_t; + +#define LSM6DSV32X_FSM_OUTS1 0x4CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm1_n_v : 1; + uint8_t fsm1_p_v : 1; + uint8_t fsm1_n_z : 1; + uint8_t fsm1_p_z : 1; + uint8_t fsm1_n_y : 1; + uint8_t fsm1_p_y : 1; + uint8_t fsm1_n_x : 1; + uint8_t fsm1_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm1_p_x : 1; + uint8_t fsm1_n_x : 1; + uint8_t fsm1_p_y : 1; + uint8_t fsm1_n_y : 1; + uint8_t fsm1_p_z : 1; + uint8_t fsm1_n_z : 1; + uint8_t fsm1_p_v : 1; + uint8_t fsm1_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_outs1_t; + +#define LSM6DSV32X_FSM_OUTS2 0x4DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm2_n_v : 1; + uint8_t fsm2_p_v : 1; + uint8_t fsm2_n_z : 1; + uint8_t fsm2_p_z : 1; + uint8_t fsm2_n_y : 1; + uint8_t fsm2_p_y : 1; + uint8_t fsm2_n_x : 1; + uint8_t fsm2_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm2_p_x : 1; + uint8_t fsm2_n_x : 1; + uint8_t fsm2_p_y : 1; + uint8_t fsm2_n_y : 1; + uint8_t fsm2_p_z : 1; + uint8_t fsm2_n_z : 1; + uint8_t fsm2_p_v : 1; + uint8_t fsm2_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_outs2_t; + +#define LSM6DSV32X_FSM_OUTS3 0x4EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm3_n_v : 1; + uint8_t fsm3_p_v : 1; + uint8_t fsm3_n_z : 1; + uint8_t fsm3_p_z : 1; + uint8_t fsm3_n_y : 1; + uint8_t fsm3_p_y : 1; + uint8_t fsm3_n_x : 1; + uint8_t fsm3_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm3_p_x : 1; + uint8_t fsm3_n_x : 1; + uint8_t fsm3_p_y : 1; + uint8_t fsm3_n_y : 1; + uint8_t fsm3_p_z : 1; + uint8_t fsm3_n_z : 1; + uint8_t fsm3_p_v : 1; + uint8_t fsm3_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_outs3_t; + +#define LSM6DSV32X_FSM_OUTS4 0x4FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm4_n_v : 1; + uint8_t fsm4_p_v : 1; + uint8_t fsm4_n_z : 1; + uint8_t fsm4_p_z : 1; + uint8_t fsm4_n_y : 1; + uint8_t fsm4_p_y : 1; + uint8_t fsm4_n_x : 1; + uint8_t fsm4_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm4_p_x : 1; + uint8_t fsm4_n_x : 1; + uint8_t fsm4_p_y : 1; + uint8_t fsm4_n_y : 1; + uint8_t fsm4_p_z : 1; + uint8_t fsm4_n_z : 1; + uint8_t fsm4_p_v : 1; + uint8_t fsm4_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_outs4_t; + +#define LSM6DSV32X_FSM_OUTS5 0x50U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm5_n_v : 1; + uint8_t fsm5_p_v : 1; + uint8_t fsm5_n_z : 1; + uint8_t fsm5_p_z : 1; + uint8_t fsm5_n_y : 1; + uint8_t fsm5_p_y : 1; + uint8_t fsm5_n_x : 1; + uint8_t fsm5_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm5_p_x : 1; + uint8_t fsm5_n_x : 1; + uint8_t fsm5_p_y : 1; + uint8_t fsm5_n_y : 1; + uint8_t fsm5_p_z : 1; + uint8_t fsm5_n_z : 1; + uint8_t fsm5_p_v : 1; + uint8_t fsm5_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_outs5_t; + +#define LSM6DSV32X_FSM_OUTS6 0x51U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm6_n_v : 1; + uint8_t fsm6_p_v : 1; + uint8_t fsm6_n_z : 1; + uint8_t fsm6_p_z : 1; + uint8_t fsm6_n_y : 1; + uint8_t fsm6_p_y : 1; + uint8_t fsm6_n_x : 1; + uint8_t fsm6_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm6_p_x : 1; + uint8_t fsm6_n_x : 1; + uint8_t fsm6_p_y : 1; + uint8_t fsm6_n_y : 1; + uint8_t fsm6_p_z : 1; + uint8_t fsm6_n_z : 1; + uint8_t fsm6_p_v : 1; + uint8_t fsm6_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_outs6_t; + +#define LSM6DSV32X_FSM_OUTS7 0x52U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm7_n_v : 1; + uint8_t fsm7_p_v : 1; + uint8_t fsm7_n_z : 1; + uint8_t fsm7_p_z : 1; + uint8_t fsm7_n_y : 1; + uint8_t fsm7_p_y : 1; + uint8_t fsm7_n_x : 1; + uint8_t fsm7_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm7_p_x : 1; + uint8_t fsm7_n_x : 1; + uint8_t fsm7_p_y : 1; + uint8_t fsm7_n_y : 1; + uint8_t fsm7_p_z : 1; + uint8_t fsm7_n_z : 1; + uint8_t fsm7_p_v : 1; + uint8_t fsm7_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_outs7_t; + +#define LSM6DSV32X_FSM_OUTS8 0x53U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm8_n_v : 1; + uint8_t fsm8_p_v : 1; + uint8_t fsm8_n_z : 1; + uint8_t fsm8_p_z : 1; + uint8_t fsm8_n_y : 1; + uint8_t fsm8_p_y : 1; + uint8_t fsm8_n_x : 1; + uint8_t fsm8_p_x : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm8_p_x : 1; + uint8_t fsm8_n_x : 1; + uint8_t fsm8_p_y : 1; + uint8_t fsm8_n_y : 1; + uint8_t fsm8_p_z : 1; + uint8_t fsm8_n_z : 1; + uint8_t fsm8_p_v : 1; + uint8_t fsm8_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_outs8_t; + +#define LSM6DSV32X_SFLP_ODR 0x5EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t sflp_game_odr : 3; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t sflp_game_odr : 3; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_sflp_odr_t; + +#define LSM6DSV32X_FSM_ODR 0x5FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t fsm_odr : 3; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t fsm_odr : 3; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_odr_t; + +#define LSM6DSV32X_MLC_ODR 0x60U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t mlc_odr : 3; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t mlc_odr : 3; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_mlc_odr_t; + +#define LSM6DSV32X_STEP_COUNTER_L 0x62U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t step : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_step_counter_l_t; + +#define LSM6DSV32X_STEP_COUNTER_H 0x63U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t step : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_step_counter_h_t; + +#define LSM6DSV32X_EMB_FUNC_SRC 0x64U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t stepcounter_bit_set : 1; + uint8_t step_overflow : 1; + uint8_t step_count_delta_ia : 1; + uint8_t step_detected : 1; + uint8_t not_used1 : 1; + uint8_t pedo_rst_step : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pedo_rst_step : 1; + uint8_t not_used1 : 1; + uint8_t step_detected : 1; + uint8_t step_count_delta_ia : 1; + uint8_t step_overflow : 1; + uint8_t stepcounter_bit_set : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_emb_func_src_t; + +#define LSM6DSV32X_EMB_FUNC_INIT_A 0x66U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t sflp_game_init : 1; + uint8_t not_used2 : 1; + uint8_t step_det_init : 1; + uint8_t tilt_init : 1; + uint8_t sig_mot_init : 1; + uint8_t not_used1 : 1; + uint8_t mlc_before_fsm_init : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_before_fsm_init : 1; + uint8_t not_used1 : 1; + uint8_t sig_mot_init : 1; + uint8_t tilt_init : 1; + uint8_t step_det_init : 1; + uint8_t not_used2 : 1; + uint8_t sflp_game_init : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_emb_func_init_a_t; + +#define LSM6DSV32X_EMB_FUNC_INIT_B 0x67U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_init : 1; + uint8_t not_used0 : 2; + uint8_t fifo_compr_init : 1; + uint8_t mlc_init : 1; + uint8_t not_used1 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 3; + uint8_t mlc_init : 1; + uint8_t fifo_compr_init : 1; + uint8_t not_used0 : 2; + uint8_t fsm_init : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_emb_func_init_b_t; + +#define LSM6DSV32X_MLC1_SRC 0x70U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc1_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc1_src : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_mlc1_src_t; + +#define LSM6DSV32X_MLC2_SRC 0x71U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc2_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc2_src : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_mlc2_src_t; + +#define LSM6DSV32X_MLC3_SRC 0x72U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc3_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc3_src : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_mlc3_src_t; + +#define LSM6DSV32X_MLC4_SRC 0x73U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc4_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc4_src : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_mlc4_src_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page pg0_emb_adv + * @{ + * + */ +#define LSM6DSV32X_EMB_ADV_PG_0 0x000U + +#define LSM6DSV32X_SFLP_GAME_GBIASX_L 0x6EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasx : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_sflp_game_gbiasx_l_t; + +#define LSM6DSV32X_SFLP_GAME_GBIASX_H 0x6FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasx : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_sflp_game_gbiasx_h_t; + +#define LSM6DSV32X_SFLP_GAME_GBIASY_L 0x70U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasy : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_sflp_game_gbiasy_l_t; + +#define LSM6DSV32X_SFLP_GAME_GBIASY_H 0x71U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasy : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_sflp_game_gbiasy_h_t; + +#define LSM6DSV32X_SFLP_GAME_GBIASZ_L 0x72U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_sflp_game_gbiasz_l_t; + +#define LSM6DSV32X_SFLP_GAME_GBIASZ_H 0x73U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_sflp_game_gbiasz_h_t; + +#define LSM6DSV32X_FSM_EXT_SENSITIVITY_L 0xBAU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_s : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_ext_sensitivity_l_t; + +#define LSM6DSV32X_FSM_EXT_SENSITIVITY_H 0xBBU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_s : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_ext_sensitivity_h_t; + +#define LSM6DSV32X_FSM_EXT_OFFX_L 0xC0U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_offx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_offx : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_ext_offx_l_t; + +#define LSM6DSV32X_FSM_EXT_OFFX_H 0xC1U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_offx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_offx : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_ext_offx_h_t; + +#define LSM6DSV32X_FSM_EXT_OFFY_L 0xC2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_offy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_offy : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_ext_offy_l_t; + +#define LSM6DSV32X_FSM_EXT_OFFY_H 0xC3U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_offy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_offy : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_ext_offy_h_t; + +#define LSM6DSV32X_FSM_EXT_OFFZ_L 0xC4U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_offz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_offz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_ext_offz_l_t; + +#define LSM6DSV32X_FSM_EXT_OFFZ_H 0xC5U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_offz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_offz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_ext_offz_h_t; + +#define LSM6DSV32X_FSM_EXT_MATRIX_XX_L 0xC6U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_xx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_xx : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_ext_matrix_xx_l_t; + +#define LSM6DSV32X_FSM_EXT_MATRIX_XX_H 0xC7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_xx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_xx : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_ext_matrix_xx_h_t; + +#define LSM6DSV32X_FSM_EXT_MATRIX_XY_L 0xC8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_xy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_xy : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_ext_matrix_xy_l_t; + +#define LSM6DSV32X_FSM_EXT_MATRIX_XY_H 0xC9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_xy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_xy : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_ext_matrix_xy_h_t; + +#define LSM6DSV32X_FSM_EXT_MATRIX_XZ_L 0xCAU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_xz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_xz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_ext_matrix_xz_l_t; + +#define LSM6DSV32X_FSM_EXT_MATRIX_XZ_H 0xCBU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_xz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_xz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_ext_matrix_xz_h_t; + +#define LSM6DSV32X_FSM_EXT_MATRIX_YY_L 0xCCU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_yy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_yy : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_ext_matrix_yy_l_t; + +#define LSM6DSV32X_FSM_EXT_MATRIX_YY_H 0xCDU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_yy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_yy : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_ext_matrix_yy_h_t; + +#define LSM6DSV32X_FSM_EXT_MATRIX_YZ_L 0xCEU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_yz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_yz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_ext_matrix_yz_l_t; + +#define LSM6DSV32X_FSM_EXT_MATRIX_YZ_H 0xCFU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_yz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_yz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_ext_matrix_yz_h_t; + +#define LSM6DSV32X_FSM_EXT_MATRIX_ZZ_L 0xD0U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_zz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_zz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_ext_matrix_zz_l_t; + +#define LSM6DSV32X_FSM_EXT_MATRIX_ZZ_H 0xD1U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_ext_mat_zz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_ext_mat_zz : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_ext_matrix_zz_h_t; + +#define LSM6DSV32X_EXT_CFG_A 0xD4U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_z_axis : 3; + uint8_t not_used0 : 1; + uint8_t ext_y_axis : 3; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t ext_y_axis : 3; + uint8_t not_used0 : 1; + uint8_t ext_z_axis : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ext_cfg_a_t; + +#define LSM6DSV32X_EXT_CFG_B 0xD5U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_x_axis : 3; + uint8_t not_used0 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 5; + uint8_t ext_x_axis : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ext_cfg_b_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page pg1_emb_adv + * @{ + * + */ +#define LSM6DSV32X_EMB_ADV_PG_1 0x100U + +#define LSM6DSV32X_FSM_LC_TIMEOUT_L 0x7AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc_timeout : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc_timeout : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_lc_timeout_l_t; + +#define LSM6DSV32X_FSM_LC_TIMEOUT_H 0x7BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc_timeout : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc_timeout : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_lc_timeout_h_t; + +#define LSM6DSV32X_FSM_PROGRAMS 0x7CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_n_prog : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_n_prog : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_programs_t; + +#define LSM6DSV32X_FSM_START_ADD_L 0x7EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_start : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_start : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_start_add_l_t; + +#define LSM6DSV32X_FSM_START_ADD_H 0x7FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_start : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_start : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_fsm_start_add_h_t; + +#define LSM6DSV32X_PEDO_CMD_REG 0x83U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t fp_rejection_en : 1; + uint8_t carry_count_en : 1; + uint8_t not_used1 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 4; + uint8_t carry_count_en : 1; + uint8_t fp_rejection_en : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_pedo_cmd_reg_t; + +#define LSM6DSV32X_PEDO_DEB_STEPS_CONF 0x84U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t deb_step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t deb_step : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_pedo_deb_steps_conf_t; + +#define LSM6DSV32X_PEDO_SC_DELTAT_L 0xD0U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t pd_sc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pd_sc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_pedo_sc_deltat_l_t; + +#define LSM6DSV32X_PEDO_SC_DELTAT_H 0xD1U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t pd_sc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pd_sc : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_pedo_sc_deltat_h_t; + +#define LSM6DSV32X_MLC_EXT_SENSITIVITY_L 0xE8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc_ext_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_ext_s : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_mlc_ext_sensitivity_l_t; + +#define LSM6DSV32X_MLC_EXT_SENSITIVITY_H 0xE9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc_ext_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_ext_s : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_mlc_ext_sensitivity_h_t; + +/** @defgroup bitfields page pg2_emb_adv + * @{ + * + */ +#define LSM6DSV32X_EMB_ADV_PG_2 0x200U + +#define LSM6DSV32X_EXT_FORMAT 0x00 +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t ext_format_sel : 1; + uint8_t not_used1 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 5; + uint8_t ext_format_sel : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ext_format_t; + +#define LSM6DSV32X_EXT_3BYTE_SENSITIVITY_L 0x02U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_3byte_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ext_3byte_s : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ext_3byte_sensitivity_l_t; + +#define LSM6DSV32X_EXT_3BYTE_SENSITIVITY_H 0x03U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_3byte_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ext_3byte_s : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ext_3byte_sensitivity_h_t; + +#define LSM6DSV32X_EXT_3BYTE_OFFSET_XL 0x06U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_3byte_off : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ext_3byte_off : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ext_3byte_offset_xl_t; + +#define LSM6DSV32X_EXT_3BYTE_OFFSET_L 0x07U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_3byte_off : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ext_3byte_off : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ext_3byte_offset_l_t; + +#define LSM6DSV32X_EXT_3BYTE_OFFSET_H 0x08U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ext_3byte_off : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ext_3byte_off : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_ext_3byte_offset_h_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page sensor_hub + * @{ + * + */ + +#define LSM6DSV32X_SENSOR_HUB_1 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub1 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub1 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_sensor_hub_1_t; + +#define LSM6DSV32X_SENSOR_HUB_2 0x3U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub2 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub2 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_sensor_hub_2_t; + +#define LSM6DSV32X_SENSOR_HUB_3 0x4U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub3 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub3 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_sensor_hub_3_t; + +#define LSM6DSV32X_SENSOR_HUB_4 0x5U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub4 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub4 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_sensor_hub_4_t; + +#define LSM6DSV32X_SENSOR_HUB_5 0x6U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub5 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub5 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_sensor_hub_5_t; + +#define LSM6DSV32X_SENSOR_HUB_6 0x7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub6 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub6 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_sensor_hub_6_t; + +#define LSM6DSV32X_SENSOR_HUB_7 0x8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub7 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub7 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_sensor_hub_7_t; + +#define LSM6DSV32X_SENSOR_HUB_8 0x9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub8 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub8 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_sensor_hub_8_t; + +#define LSM6DSV32X_SENSOR_HUB_9 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub9 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub9 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_sensor_hub_9_t; + +#define LSM6DSV32X_SENSOR_HUB_10 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub10 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub10 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_sensor_hub_10_t; + +#define LSM6DSV32X_SENSOR_HUB_11 0x0CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub11 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub11 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_sensor_hub_11_t; + +#define LSM6DSV32X_SENSOR_HUB_12 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub12 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub12 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_sensor_hub_12_t; + +#define LSM6DSV32X_SENSOR_HUB_13 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub13 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub13 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_sensor_hub_13_t; + +#define LSM6DSV32X_SENSOR_HUB_14 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub14 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub14 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_sensor_hub_14_t; + +#define LSM6DSV32X_SENSOR_HUB_15 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub15 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub15 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_sensor_hub_15_t; + +#define LSM6DSV32X_SENSOR_HUB_16 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub16 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub16 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_sensor_hub_16_t; + +#define LSM6DSV32X_SENSOR_HUB_17 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub17 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub17 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_sensor_hub_17_t; + +#define LSM6DSV32X_SENSOR_HUB_18 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sensorhub18 : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sensorhub18 : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_sensor_hub_18_t; + +#define LSM6DSV32X_MASTER_CONFIG 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t aux_sens_on : 2; + uint8_t master_on : 1; + uint8_t not_used0 : 1; + uint8_t pass_through_mode : 1; + uint8_t start_config : 1; + uint8_t write_once : 1; + uint8_t rst_master_regs : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t rst_master_regs : 1; + uint8_t write_once : 1; + uint8_t start_config : 1; + uint8_t pass_through_mode : 1; + uint8_t not_used0 : 1; + uint8_t master_on : 1; + uint8_t aux_sens_on : 2; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_master_config_t; + +#define LSM6DSV32X_SLV0_ADD 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t rw_0 : 1; + uint8_t slave0_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave0_add : 7; + uint8_t rw_0 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_slv0_add_t; + +#define LSM6DSV32X_SLV0_SUBADD 0x16U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave0_reg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave0_reg : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_slv0_subadd_t; + +#define LSM6DSV32X_SLV0_CONFIG 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave0_numop : 3; + uint8_t batch_ext_sens_0_en : 1; + uint8_t not_used0 : 1; + uint8_t shub_odr : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t shub_odr : 3; + uint8_t not_used0 : 1; + uint8_t batch_ext_sens_0_en : 1; + uint8_t slave0_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_slv0_config_t; + +#define LSM6DSV32X_SLV1_ADD 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t r_1 : 1; + uint8_t slave1_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave1_add : 7; + uint8_t r_1 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_slv1_add_t; + +#define LSM6DSV32X_SLV1_SUBADD 0x19U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave1_reg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave1_reg : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_slv1_subadd_t; + +#define LSM6DSV32X_SLV1_CONFIG 0x1AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave1_numop : 3; + uint8_t batch_ext_sens_1_en : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t batch_ext_sens_1_en : 1; + uint8_t slave1_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_slv1_config_t; + +#define LSM6DSV32X_SLV2_ADD 0x1BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t r_2 : 1; + uint8_t slave2_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave2_add : 7; + uint8_t r_2 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_slv2_add_t; + +#define LSM6DSV32X_SLV2_SUBADD 0x1CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave2_reg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave2_reg : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_slv2_subadd_t; + +#define LSM6DSV32X_SLV2_CONFIG 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave2_numop : 3; + uint8_t batch_ext_sens_2_en : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t batch_ext_sens_2_en : 1; + uint8_t slave2_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_slv2_config_t; + +#define LSM6DSV32X_SLV3_ADD 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t r_3 : 1; + uint8_t slave3_add : 7; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave3_add : 7; + uint8_t r_3 : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_slv3_add_t; + +#define LSM6DSV32X_SLV3_SUBADD 0x1FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave3_reg : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave3_reg : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_slv3_subadd_t; + +#define LSM6DSV32X_SLV3_CONFIG 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave3_numop : 3; + uint8_t batch_ext_sens_3_en : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t batch_ext_sens_3_en : 1; + uint8_t slave3_numop : 3; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_slv3_config_t; + +#define LSM6DSV32X_DATAWRITE_SLV0 0x21U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t slave0_dataw : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t slave0_dataw : 8; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_datawrite_slv0_t; + +#define LSM6DSV32X_STATUS_MASTER 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sens_hub_endop : 1; + uint8_t not_used0 : 2; + uint8_t slave0_nack : 1; + uint8_t slave1_nack : 1; + uint8_t slave2_nack : 1; + uint8_t slave3_nack : 1; + uint8_t wr_once_done : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t wr_once_done : 1; + uint8_t slave3_nack : 1; + uint8_t slave2_nack : 1; + uint8_t slave1_nack : 1; + uint8_t slave0_nack : 1; + uint8_t not_used0 : 2; + uint8_t sens_hub_endop : 1; +#endif /* DRV_BYTE_ORDER */ +} lsm6dsv32x_status_master_t; + +/** + * @} + * + */ + +/** + * @defgroup LSM6DSV_Register_Union + * @brief This union group all the registers having a bit-field + * description. + * This union is useful but it's not needed by the driver. + * + * REMOVING this union you are compliant with: + * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " + * + * @{ + * + */ +typedef union +{ + lsm6dsv32x_func_cfg_access_t func_cfg_access; + lsm6dsv32x_pin_ctrl_t pin_ctrl; + lsm6dsv32x_if_cfg_t if_cfg; + lsm6dsv32x_odr_trig_cfg_t odr_trig_cfg; + lsm6dsv32x_fifo_ctrl1_t fifo_ctrl1; + lsm6dsv32x_fifo_ctrl2_t fifo_ctrl2; + lsm6dsv32x_fifo_ctrl3_t fifo_ctrl3; + lsm6dsv32x_fifo_ctrl4_t fifo_ctrl4; + lsm6dsv32x_counter_bdr_reg1_t counter_bdr_reg1; + lsm6dsv32x_counter_bdr_reg2_t counter_bdr_reg2; + lsm6dsv32x_int1_ctrl_t int1_ctrl; + lsm6dsv32x_int2_ctrl_t int2_ctrl; + lsm6dsv32x_who_am_i_t who_am_i; + lsm6dsv32x_ctrl1_t ctrl1; + lsm6dsv32x_ctrl2_t ctrl2; + lsm6dsv32x_ctrl3_t ctrl3; + lsm6dsv32x_ctrl4_t ctrl4; + lsm6dsv32x_ctrl5_t ctrl5; + lsm6dsv32x_ctrl6_t ctrl6; + lsm6dsv32x_ctrl7_t ctrl7; + lsm6dsv32x_ctrl8_t ctrl8; + lsm6dsv32x_ctrl9_t ctrl9; + lsm6dsv32x_ctrl10_t ctrl10; + lsm6dsv32x_ctrl_status_t ctrl_status; + lsm6dsv32x_fifo_status1_t fifo_status1; + lsm6dsv32x_fifo_status2_t fifo_status2; + lsm6dsv32x_all_int_src_t all_int_src; + lsm6dsv32x_status_reg_t status_reg; + lsm6dsv32x_out_temp_l_t out_temp_l; + lsm6dsv32x_out_temp_h_t out_temp_h; + lsm6dsv32x_outx_l_g_t outx_l_g; + lsm6dsv32x_outx_h_g_t outx_h_g; + lsm6dsv32x_outy_l_g_t outy_l_g; + lsm6dsv32x_outy_h_g_t outy_h_g; + lsm6dsv32x_outz_l_g_t outz_l_g; + lsm6dsv32x_outz_h_g_t outz_h_g; + lsm6dsv32x_outx_l_a_t outx_l_a; + lsm6dsv32x_outx_h_a_t outx_h_a; + lsm6dsv32x_outy_l_a_t outy_l_a; + lsm6dsv32x_outy_h_a_t outy_h_a; + lsm6dsv32x_outz_l_a_t outz_l_a; + lsm6dsv32x_outz_h_a_t outz_h_a; + lsm6dsv32x_ui_outx_l_g_ois_eis_t ui_outx_l_g_ois_eis; + lsm6dsv32x_ui_outx_h_g_ois_eis_t ui_outx_h_g_ois_eis; + lsm6dsv32x_ui_outy_l_g_ois_eis_t ui_outy_l_g_ois_eis; + lsm6dsv32x_ui_outy_h_g_ois_eis_t ui_outy_h_g_ois_eis; + lsm6dsv32x_ui_outz_l_g_ois_eis_t ui_outz_l_g_ois_eis; + lsm6dsv32x_ui_outz_h_g_ois_eis_t ui_outz_h_g_ois_eis; + lsm6dsv32x_ui_outx_l_a_ois_dualc_t ui_outx_l_a_ois_dualc; + lsm6dsv32x_ui_outx_h_a_ois_dualc_t ui_outx_h_a_ois_dualc; + lsm6dsv32x_ui_outy_l_a_ois_dualc_t ui_outy_l_a_ois_dualc; + lsm6dsv32x_ui_outy_h_a_ois_dualc_t ui_outy_h_a_ois_dualc; + lsm6dsv32x_ui_outz_l_a_ois_dualc_t ui_outz_l_a_ois_dualc; + lsm6dsv32x_ui_outz_h_a_ois_dualc_t ui_outz_h_a_ois_dualc; + lsm6dsv32x_ah_qvar_out_l_t ah_qvar_out_l; + lsm6dsv32x_ah_qvar_out_h_t ah_qvar_out_h; + lsm6dsv32x_timestamp0_t timestamp0; + lsm6dsv32x_timestamp1_t timestamp1; + lsm6dsv32x_timestamp2_t timestamp2; + lsm6dsv32x_timestamp3_t timestamp3; + lsm6dsv32x_ui_status_reg_ois_t ui_status_reg_ois; + lsm6dsv32x_wake_up_src_t wake_up_src; + lsm6dsv32x_tap_src_t tap_src; + lsm6dsv32x_d6d_src_t d6d_src; + lsm6dsv32x_status_master_mainpage_t status_master_mainpage; + lsm6dsv32x_emb_func_status_mainpage_t emb_func_status_mainpage; + lsm6dsv32x_fsm_status_mainpage_t fsm_status_mainpage; + lsm6dsv32x_mlc_status_mainpage_t mlc_status_mainpage; + lsm6dsv32x_internal_freq_t internal_freq; + lsm6dsv32x_functions_enable_t functions_enable; + lsm6dsv32x_den_t den; + lsm6dsv32x_inactivity_dur_t inactivity_dur; + lsm6dsv32x_inactivity_ths_t inactivity_ths; + lsm6dsv32x_tap_cfg0_t tap_cfg0; + lsm6dsv32x_tap_cfg1_t tap_cfg1; + lsm6dsv32x_tap_cfg2_t tap_cfg2; + lsm6dsv32x_tap_ths_6d_t tap_ths_6d; + lsm6dsv32x_tap_dur_t tap_dur; + lsm6dsv32x_wake_up_ths_t wake_up_ths; + lsm6dsv32x_wake_up_dur_t wake_up_dur; + lsm6dsv32x_free_fall_t free_fall; + lsm6dsv32x_md1_cfg_t md1_cfg; + lsm6dsv32x_md2_cfg_t md2_cfg; + lsm6dsv32x_emb_func_cfg_t emb_func_cfg; + lsm6dsv32x_ui_handshake_ctrl_t ui_handshake_ctrl; + lsm6dsv32x_ui_spi2_shared_0_t ui_spi2_shared_0; + lsm6dsv32x_ui_spi2_shared_1_t ui_spi2_shared_1; + lsm6dsv32x_ui_spi2_shared_2_t ui_spi2_shared_2; + lsm6dsv32x_ui_spi2_shared_3_t ui_spi2_shared_3; + lsm6dsv32x_ui_spi2_shared_4_t ui_spi2_shared_4; + lsm6dsv32x_ui_spi2_shared_5_t ui_spi2_shared_5; + lsm6dsv32x_ctrl_eis_t ctrl_eis; + lsm6dsv32x_ui_int_ois_t ui_int_ois; + lsm6dsv32x_ui_ctrl1_ois_t ui_ctrl1_ois; + lsm6dsv32x_ui_ctrl2_ois_t ui_ctrl2_ois; + lsm6dsv32x_ui_ctrl3_ois_t ui_ctrl3_ois; + lsm6dsv32x_x_ofs_usr_t x_ofs_usr; + lsm6dsv32x_y_ofs_usr_t y_ofs_usr; + lsm6dsv32x_z_ofs_usr_t z_ofs_usr; + lsm6dsv32x_fifo_data_out_tag_t fifo_data_out_tag; + lsm6dsv32x_fifo_data_out_x_l_t fifo_data_out_x_l; + lsm6dsv32x_fifo_data_out_x_h_t fifo_data_out_x_h; + lsm6dsv32x_fifo_data_out_y_l_t fifo_data_out_y_l; + lsm6dsv32x_fifo_data_out_y_h_t fifo_data_out_y_h; + lsm6dsv32x_fifo_data_out_z_l_t fifo_data_out_z_l; + lsm6dsv32x_fifo_data_out_z_h_t fifo_data_out_z_h; + lsm6dsv32x_spi2_who_am_i_t spi2_who_am_i; + lsm6dsv32x_spi2_status_reg_ois_t spi2_status_reg_ois; + lsm6dsv32x_spi2_out_temp_l_t spi2_out_temp_l; + lsm6dsv32x_spi2_out_temp_h_t spi2_out_temp_h; + lsm6dsv32x_spi2_outx_l_g_ois_t spi2_outx_l_g_ois; + lsm6dsv32x_spi2_outx_h_g_ois_t spi2_outx_h_g_ois; + lsm6dsv32x_spi2_outy_l_g_ois_t spi2_outy_l_g_ois; + lsm6dsv32x_spi2_outy_h_g_ois_t spi2_outy_h_g_ois; + lsm6dsv32x_spi2_outz_l_g_ois_t spi2_outz_l_g_ois; + lsm6dsv32x_spi2_outz_h_g_ois_t spi2_outz_h_g_ois; + lsm6dsv32x_spi2_outx_l_a_ois_t spi2_outx_l_a_ois; + lsm6dsv32x_spi2_outx_h_a_ois_t spi2_outx_h_a_ois; + lsm6dsv32x_spi2_outy_l_a_ois_t spi2_outy_l_a_ois; + lsm6dsv32x_spi2_outy_h_a_ois_t spi2_outy_h_a_ois; + lsm6dsv32x_spi2_outz_l_a_ois_t spi2_outz_l_a_ois; + lsm6dsv32x_spi2_outz_h_a_ois_t spi2_outz_h_a_ois; + lsm6dsv32x_spi2_handshake_ctrl_t spi2_handshake_ctrl; + lsm6dsv32x_spi2_int_ois_t spi2_int_ois; + lsm6dsv32x_spi2_ctrl1_ois_t spi2_ctrl1_ois; + lsm6dsv32x_spi2_ctrl2_ois_t spi2_ctrl2_ois; + lsm6dsv32x_spi2_ctrl3_ois_t spi2_ctrl3_ois; + lsm6dsv32x_page_sel_t page_sel; + lsm6dsv32x_emb_func_en_a_t emb_func_en_a; + lsm6dsv32x_emb_func_en_b_t emb_func_en_b; + lsm6dsv32x_emb_func_exec_status_t emb_func_exec_status; + lsm6dsv32x_page_address_t page_address; + lsm6dsv32x_page_value_t page_value; + lsm6dsv32x_emb_func_int1_t emb_func_int1; + lsm6dsv32x_fsm_int1_t fsm_int1; + lsm6dsv32x_mlc_int1_t mlc_int1; + lsm6dsv32x_emb_func_int2_t emb_func_int2; + lsm6dsv32x_fsm_int2_t fsm_int2; + lsm6dsv32x_mlc_int2_t mlc_int2; + lsm6dsv32x_emb_func_status_t emb_func_status; + lsm6dsv32x_fsm_status_t fsm_status; + lsm6dsv32x_mlc_status_t mlc_status; + lsm6dsv32x_page_rw_t page_rw; + lsm6dsv32x_emb_func_fifo_en_a_t emb_func_fifo_en_a; + lsm6dsv32x_emb_func_fifo_en_b_t emb_func_fifo_en_b; + lsm6dsv32x_fsm_enable_t fsm_enable; + lsm6dsv32x_fsm_long_counter_l_t fsm_long_counter_l; + lsm6dsv32x_fsm_long_counter_h_t fsm_long_counter_h; + lsm6dsv32x_int_ack_mask_t int_ack_mask; + lsm6dsv32x_fsm_outs1_t fsm_outs1; + lsm6dsv32x_fsm_outs2_t fsm_outs2; + lsm6dsv32x_fsm_outs3_t fsm_outs3; + lsm6dsv32x_fsm_outs4_t fsm_outs4; + lsm6dsv32x_fsm_outs5_t fsm_outs5; + lsm6dsv32x_fsm_outs6_t fsm_outs6; + lsm6dsv32x_fsm_outs7_t fsm_outs7; + lsm6dsv32x_fsm_outs8_t fsm_outs8; + lsm6dsv32x_fsm_odr_t fsm_odr; + lsm6dsv32x_mlc_odr_t mlc_odr; + lsm6dsv32x_step_counter_l_t step_counter_l; + lsm6dsv32x_step_counter_h_t step_counter_h; + lsm6dsv32x_emb_func_src_t emb_func_src; + lsm6dsv32x_emb_func_init_a_t emb_func_init_a; + lsm6dsv32x_emb_func_init_b_t emb_func_init_b; + lsm6dsv32x_mlc1_src_t mlc1_src; + lsm6dsv32x_mlc2_src_t mlc2_src; + lsm6dsv32x_mlc3_src_t mlc3_src; + lsm6dsv32x_mlc4_src_t mlc4_src; + lsm6dsv32x_fsm_ext_sensitivity_l_t fsm_ext_sensitivity_l; + lsm6dsv32x_fsm_ext_sensitivity_h_t fsm_ext_sensitivity_h; + lsm6dsv32x_fsm_ext_offx_l_t fsm_ext_offx_l; + lsm6dsv32x_fsm_ext_offx_h_t fsm_ext_offx_h; + lsm6dsv32x_fsm_ext_offy_l_t fsm_ext_offy_l; + lsm6dsv32x_fsm_ext_offy_h_t fsm_ext_offy_h; + lsm6dsv32x_fsm_ext_offz_l_t fsm_ext_offz_l; + lsm6dsv32x_fsm_ext_offz_h_t fsm_ext_offz_h; + lsm6dsv32x_fsm_ext_matrix_xx_l_t fsm_ext_matrix_xx_l; + lsm6dsv32x_fsm_ext_matrix_xx_h_t fsm_ext_matrix_xx_h; + lsm6dsv32x_fsm_ext_matrix_xy_l_t fsm_ext_matrix_xy_l; + lsm6dsv32x_fsm_ext_matrix_xy_h_t fsm_ext_matrix_xy_h; + lsm6dsv32x_fsm_ext_matrix_xz_l_t fsm_ext_matrix_xz_l; + lsm6dsv32x_fsm_ext_matrix_xz_h_t fsm_ext_matrix_xz_h; + lsm6dsv32x_fsm_ext_matrix_yy_l_t fsm_ext_matrix_yy_l; + lsm6dsv32x_fsm_ext_matrix_yy_h_t fsm_ext_matrix_yy_h; + lsm6dsv32x_fsm_ext_matrix_yz_l_t fsm_ext_matrix_yz_l; + lsm6dsv32x_fsm_ext_matrix_yz_h_t fsm_ext_matrix_yz_h; + lsm6dsv32x_fsm_ext_matrix_zz_l_t fsm_ext_matrix_zz_l; + lsm6dsv32x_fsm_ext_matrix_zz_h_t fsm_ext_matrix_zz_h; + lsm6dsv32x_ext_cfg_a_t ext_cfg_a; + lsm6dsv32x_ext_cfg_b_t ext_cfg_b; + lsm6dsv32x_fsm_lc_timeout_l_t fsm_lc_timeout_l; + lsm6dsv32x_fsm_lc_timeout_h_t fsm_lc_timeout_h; + lsm6dsv32x_fsm_programs_t fsm_programs; + lsm6dsv32x_fsm_start_add_l_t fsm_start_add_l; + lsm6dsv32x_fsm_start_add_h_t fsm_start_add_h; + lsm6dsv32x_pedo_cmd_reg_t pedo_cmd_reg; + lsm6dsv32x_pedo_deb_steps_conf_t pedo_deb_steps_conf; + lsm6dsv32x_pedo_sc_deltat_l_t pedo_sc_deltat_l; + lsm6dsv32x_pedo_sc_deltat_h_t pedo_sc_deltat_h; + lsm6dsv32x_mlc_ext_sensitivity_l_t mlc_ext_sensitivity_l; + lsm6dsv32x_mlc_ext_sensitivity_h_t mlc_ext_sensitivity_h; + lsm6dsv32x_sensor_hub_1_t sensor_hub_1; + lsm6dsv32x_sensor_hub_2_t sensor_hub_2; + lsm6dsv32x_sensor_hub_3_t sensor_hub_3; + lsm6dsv32x_sensor_hub_4_t sensor_hub_4; + lsm6dsv32x_sensor_hub_5_t sensor_hub_5; + lsm6dsv32x_sensor_hub_6_t sensor_hub_6; + lsm6dsv32x_sensor_hub_7_t sensor_hub_7; + lsm6dsv32x_sensor_hub_8_t sensor_hub_8; + lsm6dsv32x_sensor_hub_9_t sensor_hub_9; + lsm6dsv32x_sensor_hub_10_t sensor_hub_10; + lsm6dsv32x_sensor_hub_11_t sensor_hub_11; + lsm6dsv32x_sensor_hub_12_t sensor_hub_12; + lsm6dsv32x_sensor_hub_13_t sensor_hub_13; + lsm6dsv32x_sensor_hub_14_t sensor_hub_14; + lsm6dsv32x_sensor_hub_15_t sensor_hub_15; + lsm6dsv32x_sensor_hub_16_t sensor_hub_16; + lsm6dsv32x_sensor_hub_17_t sensor_hub_17; + lsm6dsv32x_sensor_hub_18_t sensor_hub_18; + lsm6dsv32x_master_config_t master_config; + lsm6dsv32x_slv0_add_t slv0_add; + lsm6dsv32x_slv0_subadd_t slv0_subadd; + lsm6dsv32x_slv0_config_t slv0_config; + lsm6dsv32x_slv1_add_t slv1_add; + lsm6dsv32x_slv1_subadd_t slv1_subadd; + lsm6dsv32x_slv1_config_t slv1_config; + lsm6dsv32x_slv2_add_t slv2_add; + lsm6dsv32x_slv2_subadd_t slv2_subadd; + lsm6dsv32x_slv2_config_t slv2_config; + lsm6dsv32x_slv3_add_t slv3_add; + lsm6dsv32x_slv3_subadd_t slv3_subadd; + lsm6dsv32x_slv3_config_t slv3_config; + lsm6dsv32x_datawrite_slv0_t datawrite_slv0; + lsm6dsv32x_status_master_t status_master; + bitwise_t bitwise; + uint8_t byte; +} lsm6dsv32x_reg_t; + +/** + * @} + * + */ + +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + +int32_t lsm6dsv32x_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); +int32_t lsm6dsv32x_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); + +float_t lsm6dsv32x_from_sflp_to_mg(int16_t lsb); +float_t lsm6dsv32x_from_fs4_to_mg(int16_t lsb); +float_t lsm6dsv32x_from_fs8_to_mg(int16_t lsb); +float_t lsm6dsv32x_from_fs16_to_mg(int16_t lsb); +float_t lsm6dsv32x_from_fs32_to_mg(int16_t lsb); + +float_t lsm6dsv32x_from_fs125_to_mdps(int16_t lsb); +float_t lsm6dsv32x_from_fs500_to_mdps(int16_t lsb); +float_t lsm6dsv32x_from_fs250_to_mdps(int16_t lsb); +float_t lsm6dsv32x_from_fs1000_to_mdps(int16_t lsb); +float_t lsm6dsv32x_from_fs2000_to_mdps(int16_t lsb); +float_t lsm6dsv32x_from_fs4000_to_mdps(int16_t lsb); + +float_t lsm6dsv32x_from_lsb_to_celsius(int16_t lsb); + +float_t lsm6dsv32x_from_lsb_to_nsec(uint32_t lsb); + +float_t lsm6dsv32x_from_lsb_to_mv(int16_t lsb); + +int32_t lsm6dsv32x_xl_offset_on_out_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + float_t z_mg; + float_t y_mg; + float_t x_mg; +} lsm6dsv32x_xl_offset_mg_t; +int32_t lsm6dsv32x_xl_offset_mg_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_xl_offset_mg_t val); +int32_t lsm6dsv32x_xl_offset_mg_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_xl_offset_mg_t *val); + +typedef enum +{ + LSM6DSV32X_READY = 0x0, + LSM6DSV32X_GLOBAL_RST = 0x1, + LSM6DSV32X_RESTORE_CAL_PARAM = 0x2, + LSM6DSV32X_RESTORE_CTRL_REGS = 0x4, +} lsm6dsv32x_reset_t; +int32_t lsm6dsv32x_reset_set(const stmdev_ctx_t *ctx, lsm6dsv32x_reset_t val); +int32_t lsm6dsv32x_reset_get(const stmdev_ctx_t *ctx, lsm6dsv32x_reset_t *val); + +typedef enum +{ + LSM6DSV32X_MAIN_MEM_BANK = 0x0, + LSM6DSV32X_EMBED_FUNC_MEM_BANK = 0x1, + LSM6DSV32X_SENSOR_HUB_MEM_BANK = 0x2, +} lsm6dsv32x_mem_bank_t; +int32_t lsm6dsv32x_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dsv32x_mem_bank_t val); +int32_t lsm6dsv32x_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dsv32x_mem_bank_t *val); + +int32_t lsm6dsv32x_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV32X_ODR_OFF = 0x0, + LSM6DSV32X_ODR_AT_1Hz875 = 0x1, + LSM6DSV32X_ODR_AT_7Hz5 = 0x2, + LSM6DSV32X_ODR_AT_15Hz = 0x3, + LSM6DSV32X_ODR_AT_30Hz = 0x4, + LSM6DSV32X_ODR_AT_60Hz = 0x5, + LSM6DSV32X_ODR_AT_120Hz = 0x6, + LSM6DSV32X_ODR_AT_240Hz = 0x7, + LSM6DSV32X_ODR_AT_480Hz = 0x8, + LSM6DSV32X_ODR_AT_960Hz = 0x9, + LSM6DSV32X_ODR_AT_1920Hz = 0xA, + LSM6DSV32X_ODR_AT_3840Hz = 0xB, + LSM6DSV32X_ODR_AT_7680Hz = 0xC, + LSM6DSV32X_ODR_HA01_AT_15Hz625 = 0x13, + LSM6DSV32X_ODR_HA01_AT_31Hz25 = 0x14, + LSM6DSV32X_ODR_HA01_AT_62Hz5 = 0x15, + LSM6DSV32X_ODR_HA01_AT_125Hz = 0x16, + LSM6DSV32X_ODR_HA01_AT_250Hz = 0x17, + LSM6DSV32X_ODR_HA01_AT_500Hz = 0x18, + LSM6DSV32X_ODR_HA01_AT_1000Hz = 0x19, + LSM6DSV32X_ODR_HA01_AT_2000Hz = 0x1A, + LSM6DSV32X_ODR_HA01_AT_4000Hz = 0x1B, + LSM6DSV32X_ODR_HA01_AT_8000Hz = 0x1C, + LSM6DSV32X_ODR_HA02_AT_12Hz5 = 0x23, + LSM6DSV32X_ODR_HA02_AT_25Hz = 0x24, + LSM6DSV32X_ODR_HA02_AT_50Hz = 0x25, + LSM6DSV32X_ODR_HA02_AT_100Hz = 0x26, + LSM6DSV32X_ODR_HA02_AT_200Hz = 0x27, + LSM6DSV32X_ODR_HA02_AT_400Hz = 0x28, + LSM6DSV32X_ODR_HA02_AT_800Hz = 0x29, + LSM6DSV32X_ODR_HA02_AT_1600Hz = 0x2A, + LSM6DSV32X_ODR_HA02_AT_3200Hz = 0x2B, + LSM6DSV32X_ODR_HA02_AT_6400Hz = 0x2C, +} lsm6dsv32x_data_rate_t; +int32_t lsm6dsv32x_xl_data_rate_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_data_rate_t val); +int32_t lsm6dsv32x_xl_data_rate_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_data_rate_t *val); +int32_t lsm6dsv32x_gy_data_rate_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_data_rate_t val); +int32_t lsm6dsv32x_gy_data_rate_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_data_rate_t *val); + + +typedef enum +{ + LSM6DSV32X_XL_HIGH_PERFORMANCE_MD = 0x0, + LSM6DSV32X_XL_HIGH_ACCURACY_ODR_MD = 0x1, + LSM6DSV32X_XL_ODR_TRIGGERED_MD = 0x3, + LSM6DSV32X_XL_LOW_POWER_2_AVG_MD = 0x4, + LSM6DSV32X_XL_LOW_POWER_4_AVG_MD = 0x5, + LSM6DSV32X_XL_LOW_POWER_8_AVG_MD = 0x6, + LSM6DSV32X_XL_NORMAL_MD = 0x7, +} lsm6dsv32x_xl_mode_t; +int32_t lsm6dsv32x_xl_mode_set(const stmdev_ctx_t *ctx, lsm6dsv32x_xl_mode_t val); +int32_t lsm6dsv32x_xl_mode_get(const stmdev_ctx_t *ctx, lsm6dsv32x_xl_mode_t *val); + +typedef enum +{ + LSM6DSV32X_GY_HIGH_PERFORMANCE_MD = 0x0, + LSM6DSV32X_GY_HIGH_ACCURACY_ODR_MD = 0x1, + LSM6DSV32X_GY_SLEEP_MD = 0x4, + LSM6DSV32X_GY_LOW_POWER_MD = 0x5, +} lsm6dsv32x_gy_mode_t; +int32_t lsm6dsv32x_gy_mode_set(const stmdev_ctx_t *ctx, lsm6dsv32x_gy_mode_t val); +int32_t lsm6dsv32x_gy_mode_get(const stmdev_ctx_t *ctx, lsm6dsv32x_gy_mode_t *val); + +int32_t lsm6dsv32x_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv32x_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv32x_odr_trig_cfg_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_odr_trig_cfg_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV32X_DRDY_LATCHED = 0x0, + LSM6DSV32X_DRDY_PULSED = 0x1, +} lsm6dsv32x_data_ready_mode_t; +int32_t lsm6dsv32x_data_ready_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_data_ready_mode_t val); +int32_t lsm6dsv32x_data_ready_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_data_ready_mode_t *val); + +typedef struct +{ + uint8_t enable : 1; /* interrupt enable */ + uint8_t lir : 1; /* interrupt pulsed or latched */ +} lsm6dsv32x_interrupt_mode_t; +int32_t lsm6dsv32x_interrupt_enable_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_interrupt_mode_t val); +int32_t lsm6dsv32x_interrupt_enable_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_interrupt_mode_t *val); + +typedef enum +{ + LSM6DSV32X_125dps = 0x0, + LSM6DSV32X_250dps = 0x1, + LSM6DSV32X_500dps = 0x2, + LSM6DSV32X_1000dps = 0x3, + LSM6DSV32X_2000dps = 0x4, + LSM6DSV32X_4000dps = 0xc, +} lsm6dsv32x_gy_full_scale_t; +int32_t lsm6dsv32x_gy_full_scale_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_gy_full_scale_t val); +int32_t lsm6dsv32x_gy_full_scale_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_gy_full_scale_t *val); + +typedef enum +{ + LSM6DSV32X_4g = 0x0, + LSM6DSV32X_8g = 0x1, + LSM6DSV32X_16g = 0x2, + LSM6DSV32X_32g = 0x3, +} lsm6dsv32x_xl_full_scale_t; +int32_t lsm6dsv32x_xl_full_scale_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_xl_full_scale_t val); +int32_t lsm6dsv32x_xl_full_scale_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_xl_full_scale_t *val); + +int32_t lsm6dsv32x_xl_dual_channel_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV32X_XL_ST_DISABLE = 0x0, + LSM6DSV32X_XL_ST_POSITIVE = 0x1, + LSM6DSV32X_XL_ST_NEGATIVE = 0x2, +} lsm6dsv32x_xl_self_test_t; +int32_t lsm6dsv32x_xl_self_test_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_xl_self_test_t val); +int32_t lsm6dsv32x_xl_self_test_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_xl_self_test_t *val); + +typedef enum +{ + LSM6DSV32X_OIS_XL_ST_DISABLE = 0x0, + LSM6DSV32X_OIS_XL_ST_POSITIVE = 0x1, + LSM6DSV32X_OIS_XL_ST_NEGATIVE = 0x2, +} lsm6dsv32x_ois_xl_self_test_t; +int32_t lsm6dsv32x_ois_xl_self_test_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_xl_self_test_t val); +int32_t lsm6dsv32x_ois_xl_self_test_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_xl_self_test_t *val); + +typedef enum +{ + LSM6DSV32X_GY_ST_DISABLE = 0x0, + LSM6DSV32X_GY_ST_POSITIVE = 0x1, + LSM6DSV32X_GY_ST_NEGATIVE = 0x2, + +} lsm6dsv32x_gy_self_test_t; +int32_t lsm6dsv32x_gy_self_test_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_gy_self_test_t val); +int32_t lsm6dsv32x_gy_self_test_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_gy_self_test_t *val); + +typedef enum +{ + LSM6DSV32X_OIS_GY_ST_DISABLE = 0x0, + LSM6DSV32X_OIS_GY_ST_POSITIVE = 0x1, + LSM6DSV32X_OIS_GY_ST_NEGATIVE = 0x2, + LSM6DSV32X_OIS_GY_ST_CLAMP_POS = 0x5, + LSM6DSV32X_OIS_GY_ST_CLAMP_NEG = 0x6, + +} lsm6dsv32x_ois_gy_self_test_t; +int32_t lsm6dsv32x_ois_gy_self_test_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_gy_self_test_t val); +int32_t lsm6dsv32x_ois_gy_self_test_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_gy_self_test_t *val); + +typedef struct +{ + uint8_t drdy_xl : 1; + uint8_t drdy_gy : 1; + uint8_t drdy_temp : 1; + uint8_t drdy_ah_qvar : 1; + uint8_t drdy_eis : 1; + uint8_t drdy_ois : 1; + uint8_t gy_settling : 1; + uint8_t timestamp : 1; + uint8_t free_fall : 1; + uint8_t wake_up : 1; + uint8_t wake_up_z : 1; + uint8_t wake_up_y : 1; + uint8_t wake_up_x : 1; + uint8_t single_tap : 1; + uint8_t double_tap : 1; + uint8_t tap_z : 1; + uint8_t tap_y : 1; + uint8_t tap_x : 1; + uint8_t tap_sign : 1; + uint8_t six_d : 1; + uint8_t six_d_xl : 1; + uint8_t six_d_xh : 1; + uint8_t six_d_yl : 1; + uint8_t six_d_yh : 1; + uint8_t six_d_zl : 1; + uint8_t six_d_zh : 1; + uint8_t sleep_change : 1; + uint8_t sleep_state : 1; + uint8_t step_detector : 1; + uint8_t step_count_inc : 1; + uint8_t step_count_overflow : 1; + uint8_t step_on_delta_time : 1; + uint8_t emb_func_stand_by : 1; + uint8_t emb_func_time_exceed : 1; + uint8_t tilt : 1; + uint8_t sig_mot : 1; + uint8_t fsm_lc : 1; + uint8_t fsm1 : 1; + uint8_t fsm2 : 1; + uint8_t fsm3 : 1; + uint8_t fsm4 : 1; + uint8_t fsm5 : 1; + uint8_t fsm6 : 1; + uint8_t fsm7 : 1; + uint8_t fsm8 : 1; + uint8_t mlc1 : 1; + uint8_t mlc2 : 1; + uint8_t mlc3 : 1; + uint8_t mlc4 : 1; + uint8_t sh_endop : 1; + uint8_t sh_slave0_nack : 1; + uint8_t sh_slave1_nack : 1; + uint8_t sh_slave2_nack : 1; + uint8_t sh_slave3_nack : 1; + uint8_t sh_wr_once : 1; + uint8_t fifo_bdr : 1; + uint8_t fifo_full : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_th : 1; +} lsm6dsv32x_all_sources_t; +int32_t lsm6dsv32x_all_sources_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_all_sources_t *val); + +typedef struct +{ + uint8_t drdy_xl : 1; + uint8_t drdy_g : 1; + uint8_t drdy_g_eis : 1; + uint8_t drdy_temp : 1; + uint8_t fifo_th : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_full : 1; + uint8_t cnt_bdr : 1; + uint8_t emb_func_endop : 1; + uint8_t timestamp : 1; + uint8_t shub : 1; + uint8_t emb_func : 1; + uint8_t sixd : 1; + uint8_t single_tap : 1; + uint8_t double_tap : 1; + uint8_t wakeup : 1; + uint8_t freefall : 1; + uint8_t sleep_change : 1; +} lsm6dsv32x_pin_int_route_t; +int32_t lsm6dsv32x_pin_int1_route_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_pin_int_route_t *val); +int32_t lsm6dsv32x_pin_int1_route_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_pin_int_route_t *val); +int32_t lsm6dsv32x_pin_int2_route_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_pin_int_route_t *val); +int32_t lsm6dsv32x_pin_int2_route_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_pin_int_route_t *val); + +typedef struct +{ + uint8_t drdy_xl : 1; + uint8_t drdy_gy : 1; + uint8_t drdy_temp : 1; +} lsm6dsv32x_data_ready_t; +int32_t lsm6dsv32x_flag_data_ready_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_data_ready_t *val); + +int32_t lsm6dsv32x_int_ack_mask_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_int_ack_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv32x_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsv32x_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsv32x_ois_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsv32x_ois_eis_angular_rate_raw_get(const stmdev_ctx_t *ctx, + int16_t *val); + +int32_t lsm6dsv32x_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsv32x_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsv32x_ois_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, + int16_t *val); + +int32_t lsm6dsv32x_ah_qvar_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t lsm6dsv32x_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val); + +int32_t lsm6dsv32x_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len); +int32_t lsm6dsv32x_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, + uint8_t len); + +int32_t lsm6dsv32x_emb_function_dbg_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_emb_function_dbg_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV32X_DEN_ACT_LOW = 0x0, + LSM6DSV32X_DEN_ACT_HIGH = 0x1, +} lsm6dsv32x_den_polarity_t; +int32_t lsm6dsv32x_den_polarity_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_den_polarity_t val); +int32_t lsm6dsv32x_den_polarity_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_den_polarity_t *val); + +typedef struct +{ + uint8_t stamp_in_gy_data : 1; + uint8_t stamp_in_xl_data : 1; + uint8_t den_x : 1; + uint8_t den_y : 1; + uint8_t den_z : 1; + enum + { + LSM6DSV32X_DEN_NOT_DEFINED = 0x00, + LSM6DSV32X_LEVEL_TRIGGER = 0x02, + LSM6DSV32X_LEVEL_LATCHED = 0x03, + } mode; +} lsm6dsv32x_den_conf_t; +int32_t lsm6dsv32x_den_conf_set(const stmdev_ctx_t *ctx, lsm6dsv32x_den_conf_t val); +int32_t lsm6dsv32x_den_conf_get(const stmdev_ctx_t *ctx, lsm6dsv32x_den_conf_t *val); + +typedef enum +{ + LSM6DSV32X_EIS_125dps = 0x0, + LSM6DSV32X_EIS_250dps = 0x1, + LSM6DSV32X_EIS_500dps = 0x2, + LSM6DSV32X_EIS_1000dps = 0x3, + LSM6DSV32X_EIS_2000dps = 0x4, +} lsm6dsv32x_eis_gy_full_scale_t; +int32_t lsm6dsv32x_eis_gy_full_scale_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_eis_gy_full_scale_t val); +int32_t lsm6dsv32x_eis_gy_full_scale_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_eis_gy_full_scale_t *val); + +int32_t lsm6dsv32x_eis_gy_on_spi2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_eis_gy_on_spi2_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV32X_EIS_ODR_OFF = 0x0, + LSM6DSV32X_EIS_1920Hz = 0x1, + LSM6DSV32X_EIS_960Hz = 0x2, +} lsm6dsv32x_gy_eis_data_rate_t; +int32_t lsm6dsv32x_gy_eis_data_rate_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_gy_eis_data_rate_t val); +int32_t lsm6dsv32x_gy_eis_data_rate_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_gy_eis_data_rate_t *val); + +int32_t lsm6dsv32x_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv32x_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV32X_CMP_DISABLE = 0x0, + LSM6DSV32X_CMP_8_TO_1 = 0x1, + LSM6DSV32X_CMP_16_TO_1 = 0x2, + LSM6DSV32X_CMP_32_TO_1 = 0x3, +} lsm6dsv32x_fifo_compress_algo_t; +int32_t lsm6dsv32x_fifo_compress_algo_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_compress_algo_t val); +int32_t lsm6dsv32x_fifo_compress_algo_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_compress_algo_t *val); + +int32_t lsm6dsv32x_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, + uint8_t val); +int32_t lsm6dsv32x_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dsv32x_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, + uint8_t val); +int32_t lsm6dsv32x_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dsv32x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV32X_XL_NOT_BATCHED = 0x0, + LSM6DSV32X_XL_BATCHED_AT_1Hz875 = 0x1, + LSM6DSV32X_XL_BATCHED_AT_7Hz5 = 0x2, + LSM6DSV32X_XL_BATCHED_AT_15Hz = 0x3, + LSM6DSV32X_XL_BATCHED_AT_30Hz = 0x4, + LSM6DSV32X_XL_BATCHED_AT_60Hz = 0x5, + LSM6DSV32X_XL_BATCHED_AT_120Hz = 0x6, + LSM6DSV32X_XL_BATCHED_AT_240Hz = 0x7, + LSM6DSV32X_XL_BATCHED_AT_480Hz = 0x8, + LSM6DSV32X_XL_BATCHED_AT_960Hz = 0x9, + LSM6DSV32X_XL_BATCHED_AT_1920Hz = 0xa, + LSM6DSV32X_XL_BATCHED_AT_3840Hz = 0xb, + LSM6DSV32X_XL_BATCHED_AT_7680Hz = 0xc, +} lsm6dsv32x_fifo_xl_batch_t; +int32_t lsm6dsv32x_fifo_xl_batch_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_xl_batch_t val); +int32_t lsm6dsv32x_fifo_xl_batch_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_xl_batch_t *val); + +typedef enum +{ + LSM6DSV32X_GY_NOT_BATCHED = 0x0, + LSM6DSV32X_GY_BATCHED_AT_1Hz875 = 0x1, + LSM6DSV32X_GY_BATCHED_AT_7Hz5 = 0x2, + LSM6DSV32X_GY_BATCHED_AT_15Hz = 0x3, + LSM6DSV32X_GY_BATCHED_AT_30Hz = 0x4, + LSM6DSV32X_GY_BATCHED_AT_60Hz = 0x5, + LSM6DSV32X_GY_BATCHED_AT_120Hz = 0x6, + LSM6DSV32X_GY_BATCHED_AT_240Hz = 0x7, + LSM6DSV32X_GY_BATCHED_AT_480Hz = 0x8, + LSM6DSV32X_GY_BATCHED_AT_960Hz = 0x9, + LSM6DSV32X_GY_BATCHED_AT_1920Hz = 0xa, + LSM6DSV32X_GY_BATCHED_AT_3840Hz = 0xb, + LSM6DSV32X_GY_BATCHED_AT_7680Hz = 0xc, +} lsm6dsv32x_fifo_gy_batch_t; +int32_t lsm6dsv32x_fifo_gy_batch_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_gy_batch_t val); +int32_t lsm6dsv32x_fifo_gy_batch_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_gy_batch_t *val); + +typedef enum +{ + LSM6DSV32X_BYPASS_MODE = 0x0, + LSM6DSV32X_FIFO_MODE = 0x1, + LSM6DSV32X_STREAM_WTM_TO_FULL_MODE = 0x2, + LSM6DSV32X_STREAM_TO_FIFO_MODE = 0x3, + LSM6DSV32X_BYPASS_TO_STREAM_MODE = 0x4, + LSM6DSV32X_STREAM_MODE = 0x6, + LSM6DSV32X_BYPASS_TO_FIFO_MODE = 0x7, +} lsm6dsv32x_fifo_mode_t; +int32_t lsm6dsv32x_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dsv32x_fifo_mode_t val); +int32_t lsm6dsv32x_fifo_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_mode_t *val); + +int32_t lsm6dsv32x_fifo_gy_eis_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_fifo_gy_eis_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV32X_TEMP_NOT_BATCHED = 0x0, + LSM6DSV32X_TEMP_BATCHED_AT_1Hz875 = 0x1, + LSM6DSV32X_TEMP_BATCHED_AT_15Hz = 0x2, + LSM6DSV32X_TEMP_BATCHED_AT_60Hz = 0x3, +} lsm6dsv32x_fifo_temp_batch_t; +int32_t lsm6dsv32x_fifo_temp_batch_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_temp_batch_t val); +int32_t lsm6dsv32x_fifo_temp_batch_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_temp_batch_t *val); + +typedef enum +{ + LSM6DSV32X_TMSTMP_NOT_BATCHED = 0x0, + LSM6DSV32X_TMSTMP_DEC_1 = 0x1, + LSM6DSV32X_TMSTMP_DEC_8 = 0x2, + LSM6DSV32X_TMSTMP_DEC_32 = 0x3, +} lsm6dsv32x_fifo_timestamp_batch_t; +int32_t lsm6dsv32x_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_timestamp_batch_t val); +int32_t lsm6dsv32x_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_timestamp_batch_t *val); + +int32_t lsm6dsv32x_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx, + uint16_t val); +int32_t lsm6dsv32x_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx, + uint16_t *val); + +typedef enum +{ + LSM6DSV32X_XL_BATCH_EVENT = 0x0, + LSM6DSV32X_GY_BATCH_EVENT = 0x1, + LSM6DSV32X_GY_EIS_BATCH_EVENT = 0x2, +} lsm6dsv32x_fifo_batch_cnt_event_t; +int32_t lsm6dsv32x_fifo_batch_cnt_event_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_batch_cnt_event_t val); +int32_t lsm6dsv32x_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_batch_cnt_event_t *val); + +typedef struct +{ + uint16_t fifo_level : 9; + uint8_t fifo_bdr : 1; + uint8_t fifo_full : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_th : 1; +} lsm6dsv32x_fifo_status_t; + +int32_t lsm6dsv32x_fifo_status_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_status_t *val); + +typedef struct +{ + enum + { + LSM6DSV32X_FIFO_EMPTY = 0x0, + LSM6DSV32X_GY_NC_TAG = 0x1, + LSM6DSV32X_XL_NC_TAG = 0x2, + LSM6DSV32X_TEMPERATURE_TAG = 0x3, + LSM6DSV32X_TIMESTAMP_TAG = 0x4, + LSM6DSV32X_CFG_CHANGE_TAG = 0x5, + LSM6DSV32X_XL_NC_T_2_TAG = 0x6, + LSM6DSV32X_XL_NC_T_1_TAG = 0x7, + LSM6DSV32X_XL_2XC_TAG = 0x8, + LSM6DSV32X_XL_3XC_TAG = 0x9, + LSM6DSV32X_GY_NC_T_2_TAG = 0xA, + LSM6DSV32X_GY_NC_T_1_TAG = 0xB, + LSM6DSV32X_GY_2XC_TAG = 0xC, + LSM6DSV32X_GY_3XC_TAG = 0xD, + LSM6DSV32X_SENSORHUB_SLAVE0_TAG = 0xE, + LSM6DSV32X_SENSORHUB_SLAVE1_TAG = 0xF, + LSM6DSV32X_SENSORHUB_SLAVE2_TAG = 0x10, + LSM6DSV32X_SENSORHUB_SLAVE3_TAG = 0x11, + LSM6DSV32X_STEP_COUNTER_TAG = 0x12, + LSM6DSV32X_SFLP_GAME_ROTATION_VECTOR_TAG = 0x13, + LSM6DSV32X_SFLP_GYROSCOPE_BIAS_TAG = 0x16, + LSM6DSV32X_SFLP_GRAVITY_VECTOR_TAG = 0x17, + LSM6DSV32X_SENSORHUB_NACK_TAG = 0x19, + LSM6DSV32X_MLC_RESULT_TAG = 0x1A, + LSM6DSV32X_MLC_FILTER = 0x1B, + LSM6DSV32X_MLC_FEATURE = 0x1C, + LSM6DSV32X_XL_DUAL_CORE = 0x1D, + LSM6DSV32X_GY_ENHANCED_EIS = 0x1E, + } tag; + uint8_t cnt; + uint8_t data[6]; +} lsm6dsv32x_fifo_out_raw_t; +int32_t lsm6dsv32x_fifo_out_raw_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_out_raw_t *val); + +int32_t lsm6dsv32x_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv32x_fifo_mlc_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_fifo_mlc_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv32x_fifo_mlc_filt_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_fifo_mlc_filt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv32x_fifo_sh_batch_slave_set(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t val); +int32_t lsm6dsv32x_fifo_sh_batch_slave_get(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t *val); + +typedef struct +{ + uint8_t game_rotation : 1; + uint8_t gravity : 1; + uint8_t gbias : 1; +} lsm6dsv32x_fifo_sflp_raw_t; +int32_t lsm6dsv32x_fifo_sflp_batch_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_sflp_raw_t val); +int32_t lsm6dsv32x_fifo_sflp_batch_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fifo_sflp_raw_t *val); + +typedef enum +{ + LSM6DSV32X_AUTO = 0x0, + LSM6DSV32X_ALWAYS_ACTIVE = 0x1, +} lsm6dsv32x_filt_anti_spike_t; +int32_t lsm6dsv32x_filt_anti_spike_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_anti_spike_t val); +int32_t lsm6dsv32x_filt_anti_spike_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_anti_spike_t *val); + +typedef struct +{ + uint8_t drdy : 1; + uint8_t ois_drdy : 1; + uint8_t irq_xl : 1; + uint8_t irq_g : 1; +} lsm6dsv32x_filt_settling_mask_t; +int32_t lsm6dsv32x_filt_settling_mask_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_settling_mask_t val); +int32_t lsm6dsv32x_filt_settling_mask_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_settling_mask_t *val); + +typedef struct +{ + uint8_t ois_drdy : 1; +} lsm6dsv32x_filt_ois_settling_mask_t; +int32_t lsm6dsv32x_filt_ois_settling_mask_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_ois_settling_mask_t val); +int32_t lsm6dsv32x_filt_ois_settling_mask_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_ois_settling_mask_t *val); + +typedef enum +{ + LSM6DSV32X_GY_ULTRA_LIGHT = 0x0, + LSM6DSV32X_GY_VERY_LIGHT = 0x1, + LSM6DSV32X_GY_LIGHT = 0x2, + LSM6DSV32X_GY_MEDIUM = 0x3, + LSM6DSV32X_GY_STRONG = 0x4, + LSM6DSV32X_GY_VERY_STRONG = 0x5, + LSM6DSV32X_GY_AGGRESSIVE = 0x6, + LSM6DSV32X_GY_XTREME = 0x7, +} lsm6dsv32x_filt_gy_lp1_bandwidth_t; +int32_t lsm6dsv32x_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_gy_lp1_bandwidth_t val); +int32_t lsm6dsv32x_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_gy_lp1_bandwidth_t *val); + +int32_t lsm6dsv32x_filt_gy_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV32X_XL_ULTRA_LIGHT = 0x0, + LSM6DSV32X_XL_VERY_LIGHT = 0x1, + LSM6DSV32X_XL_LIGHT = 0x2, + LSM6DSV32X_XL_MEDIUM = 0x3, + LSM6DSV32X_XL_STRONG = 0x4, + LSM6DSV32X_XL_VERY_STRONG = 0x5, + LSM6DSV32X_XL_AGGRESSIVE = 0x6, + LSM6DSV32X_XL_XTREME = 0x7, +} lsm6dsv32x_filt_xl_lp2_bandwidth_t; +int32_t lsm6dsv32x_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_xl_lp2_bandwidth_t val); +int32_t lsm6dsv32x_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_xl_lp2_bandwidth_t *val); + +int32_t lsm6dsv32x_filt_xl_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv32x_filt_xl_hp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv32x_filt_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV32X_HP_MD_NORMAL = 0x0, + LSM6DSV32X_HP_MD_REFERENCE = 0x1, +} lsm6dsv32x_filt_xl_hp_mode_t; +int32_t lsm6dsv32x_filt_xl_hp_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_xl_hp_mode_t val); +int32_t lsm6dsv32x_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_xl_hp_mode_t *val); + +typedef enum +{ + LSM6DSV32X_WK_FEED_SLOPE = 0x0, + LSM6DSV32X_WK_FEED_HIGH_PASS = 0x1, + LSM6DSV32X_WK_FEED_LP_WITH_OFFSET = 0x2, +} lsm6dsv32x_filt_wkup_act_feed_t; +int32_t lsm6dsv32x_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_wkup_act_feed_t val); +int32_t lsm6dsv32x_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_wkup_act_feed_t *val); + +int32_t lsm6dsv32x_mask_trigger_xl_settl_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV32X_SIXD_FEED_ODR_DIV_2 = 0x0, + LSM6DSV32X_SIXD_FEED_LOW_PASS = 0x1, +} lsm6dsv32x_filt_sixd_feed_t; +int32_t lsm6dsv32x_filt_sixd_feed_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_sixd_feed_t val); +int32_t lsm6dsv32x_filt_sixd_feed_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_sixd_feed_t *val); + +typedef enum +{ + LSM6DSV32X_EIS_LP_NORMAL = 0x0, + LSM6DSV32X_EIS_LP_LIGHT = 0x1, +} lsm6dsv32x_filt_gy_eis_lp_bandwidth_t; +int32_t lsm6dsv32x_filt_gy_eis_lp_bandwidth_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_gy_eis_lp_bandwidth_t val); +int32_t lsm6dsv32x_filt_gy_eis_lp_bandwidth_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_gy_eis_lp_bandwidth_t *val); + +typedef enum +{ + LSM6DSV32X_OIS_GY_LP_NORMAL = 0x0, + LSM6DSV32X_OIS_GY_LP_STRONG = 0x1, + LSM6DSV32X_OIS_GY_LP_AGGRESSIVE = 0x2, + LSM6DSV32X_OIS_GY_LP_LIGHT = 0x3, +} lsm6dsv32x_filt_gy_ois_lp_bandwidth_t; +int32_t lsm6dsv32x_filt_gy_ois_lp_bandwidth_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_gy_ois_lp_bandwidth_t val); +int32_t lsm6dsv32x_filt_gy_ois_lp_bandwidth_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_gy_ois_lp_bandwidth_t *val); + +typedef enum +{ + LSM6DSV32X_OIS_XL_LP_ULTRA_LIGHT = 0x0, + LSM6DSV32X_OIS_XL_LP_VERY_LIGHT = 0x1, + LSM6DSV32X_OIS_XL_LP_LIGHT = 0x2, + LSM6DSV32X_OIS_XL_LP_NORMAL = 0x3, + LSM6DSV32X_OIS_XL_LP_STRONG = 0x4, + LSM6DSV32X_OIS_XL_LP_VERY_STRONG = 0x5, + LSM6DSV32X_OIS_XL_LP_AGGRESSIVE = 0x6, + LSM6DSV32X_OIS_XL_LP_XTREME = 0x7, +} lsm6dsv32x_filt_xl_ois_lp_bandwidth_t; +int32_t lsm6dsv32x_filt_xl_ois_lp_bandwidth_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_xl_ois_lp_bandwidth_t val); +int32_t lsm6dsv32x_filt_xl_ois_lp_bandwidth_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_filt_xl_ois_lp_bandwidth_t *val); + +typedef enum +{ + LSM6DSV32X_PROTECT_CTRL_REGS = 0x0, + LSM6DSV32X_WRITE_CTRL_REG = 0x1, +} lsm6dsv32x_fsm_permission_t; +int32_t lsm6dsv32x_fsm_permission_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_fsm_permission_t val); +int32_t lsm6dsv32x_fsm_permission_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fsm_permission_t *val); +int32_t lsm6dsv32x_fsm_permission_status(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t fsm1_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm8_en : 1; +} lsm6dsv32x_fsm_mode_t; +int32_t lsm6dsv32x_fsm_mode_set(const stmdev_ctx_t *ctx, lsm6dsv32x_fsm_mode_t val); +int32_t lsm6dsv32x_fsm_mode_get(const stmdev_ctx_t *ctx, lsm6dsv32x_fsm_mode_t *val); + +int32_t lsm6dsv32x_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv32x_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); + + +typedef struct +{ + uint8_t fsm_outs1; + uint8_t fsm_outs2; + uint8_t fsm_outs3; + uint8_t fsm_outs4; + uint8_t fsm_outs5; + uint8_t fsm_outs6; + uint8_t fsm_outs7; + uint8_t fsm_outs8; +} lsm6dsv32x_fsm_out_t; +int32_t lsm6dsv32x_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dsv32x_fsm_out_t *val); + +typedef enum +{ + LSM6DSV32X_FSM_15Hz = 0x0, + LSM6DSV32X_FSM_30Hz = 0x1, + LSM6DSV32X_FSM_60Hz = 0x2, + LSM6DSV32X_FSM_120Hz = 0x3, + LSM6DSV32X_FSM_240Hz = 0x4, + LSM6DSV32X_FSM_480Hz = 0x5, + LSM6DSV32X_FSM_960Hz = 0x6, +} lsm6dsv32x_fsm_data_rate_t; +int32_t lsm6dsv32x_fsm_data_rate_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_fsm_data_rate_t val); +int32_t lsm6dsv32x_fsm_data_rate_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fsm_data_rate_t *val); + +int32_t lsm6dsv32x_fsm_ext_sens_sensitivity_set(const stmdev_ctx_t *ctx, + uint16_t val); +int32_t lsm6dsv32x_fsm_ext_sens_sensitivity_get(const stmdev_ctx_t *ctx, + uint16_t *val); + +typedef struct +{ + uint16_t z; + uint16_t y; + uint16_t x; +} lsm6dsv32x_xl_fsm_ext_sens_offset_t; +int32_t lsm6dsv32x_fsm_ext_sens_offset_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_xl_fsm_ext_sens_offset_t val); +int32_t lsm6dsv32x_fsm_ext_sens_offset_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_xl_fsm_ext_sens_offset_t *val); + +typedef struct +{ + uint16_t xx; + uint16_t xy; + uint16_t xz; + uint16_t yy; + uint16_t yz; + uint16_t zz; +} lsm6dsv32x_xl_fsm_ext_sens_matrix_t; +int32_t lsm6dsv32x_fsm_ext_sens_matrix_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_xl_fsm_ext_sens_matrix_t val); +int32_t lsm6dsv32x_fsm_ext_sens_matrix_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_xl_fsm_ext_sens_matrix_t *val); + +typedef enum +{ + LSM6DSV32X_Z_EQ_Y = 0x0, + LSM6DSV32X_Z_EQ_MIN_Y = 0x1, + LSM6DSV32X_Z_EQ_X = 0x2, + LSM6DSV32X_Z_EQ_MIN_X = 0x3, + LSM6DSV32X_Z_EQ_MIN_Z = 0x4, + LSM6DSV32X_Z_EQ_Z = 0x5, +} lsm6dsv32x_fsm_ext_sens_z_orient_t; +int32_t lsm6dsv32x_fsm_ext_sens_z_orient_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_fsm_ext_sens_z_orient_t val); +int32_t lsm6dsv32x_fsm_ext_sens_z_orient_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fsm_ext_sens_z_orient_t *val); + +typedef enum +{ + LSM6DSV32X_Y_EQ_Y = 0x0, + LSM6DSV32X_Y_EQ_MIN_Y = 0x1, + LSM6DSV32X_Y_EQ_X = 0x2, + LSM6DSV32X_Y_EQ_MIN_X = 0x3, + LSM6DSV32X_Y_EQ_MIN_Z = 0x4, + LSM6DSV32X_Y_EQ_Z = 0x5, +} lsm6dsv32x_fsm_ext_sens_y_orient_t; +int32_t lsm6dsv32x_fsm_ext_sens_y_orient_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_fsm_ext_sens_y_orient_t val); +int32_t lsm6dsv32x_fsm_ext_sens_y_orient_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fsm_ext_sens_y_orient_t *val); + +typedef enum +{ + LSM6DSV32X_X_EQ_Y = 0x0, + LSM6DSV32X_X_EQ_MIN_Y = 0x1, + LSM6DSV32X_X_EQ_X = 0x2, + LSM6DSV32X_X_EQ_MIN_X = 0x3, + LSM6DSV32X_X_EQ_MIN_Z = 0x4, + LSM6DSV32X_X_EQ_Z = 0x5, +} lsm6dsv32x_fsm_ext_sens_x_orient_t; +int32_t lsm6dsv32x_fsm_ext_sens_x_orient_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_fsm_ext_sens_x_orient_t val); +int32_t lsm6dsv32x_fsm_ext_sens_x_orient_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_fsm_ext_sens_x_orient_t *val); + +int32_t lsm6dsv32x_fsm_long_cnt_timeout_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv32x_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lsm6dsv32x_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv32x_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv32x_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lsm6dsv32x_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV32X_156_mg = 0x0, + LSM6DSV32X_219_mg = 0x1, + LSM6DSV32X_250_mg = 0x2, + LSM6DSV32X_312_mg = 0x3, + LSM6DSV32X_344_mg = 0x4, + LSM6DSV32X_406_mg = 0x5, + LSM6DSV32X_469_mg = 0x6, + LSM6DSV32X_500_mg = 0x7, +} lsm6dsv32x_ff_thresholds_t; +int32_t lsm6dsv32x_ff_thresholds_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_ff_thresholds_t val); +int32_t lsm6dsv32x_ff_thresholds_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_ff_thresholds_t *val); + +typedef enum +{ + LSM6DSV32X_MLC_OFF = 0x0, + LSM6DSV32X_MLC_ON = 0x1, + LSM6DSV32X_MLC_ON_BEFORE_FSM = 0x2, +} lsm6dsv32x_mlc_mode_t; +int32_t lsm6dsv32x_mlc_set(const stmdev_ctx_t *ctx, lsm6dsv32x_mlc_mode_t val); +int32_t lsm6dsv32x_mlc_get(const stmdev_ctx_t *ctx, lsm6dsv32x_mlc_mode_t *val); + +typedef enum +{ + LSM6DSV32X_MLC_15Hz = 0x0, + LSM6DSV32X_MLC_30Hz = 0x1, + LSM6DSV32X_MLC_60Hz = 0x2, + LSM6DSV32X_MLC_120Hz = 0x3, + LSM6DSV32X_MLC_240Hz = 0x4, + LSM6DSV32X_MLC_480Hz = 0x5, + LSM6DSV32X_MLC_960Hz = 0x6, +} lsm6dsv32x_mlc_data_rate_t; +int32_t lsm6dsv32x_mlc_data_rate_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_mlc_data_rate_t val); +int32_t lsm6dsv32x_mlc_data_rate_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_mlc_data_rate_t *val); + +typedef struct +{ + uint8_t mlc1_src; + uint8_t mlc2_src; + uint8_t mlc3_src; + uint8_t mlc4_src; +} lsm6dsv32x_mlc_out_t; +int32_t lsm6dsv32x_mlc_out_get(const stmdev_ctx_t *ctx, lsm6dsv32x_mlc_out_t *val); + +int32_t lsm6dsv32x_mlc_ext_sens_sensitivity_set(const stmdev_ctx_t *ctx, + uint16_t val); +int32_t lsm6dsv32x_mlc_ext_sens_sensitivity_get(const stmdev_ctx_t *ctx, + uint16_t *val); + +typedef enum +{ + LSM6DSV32X_OIS_CTRL_FROM_OIS = 0x0, + LSM6DSV32X_OIS_CTRL_FROM_UI = 0x1, +} lsm6dsv32x_ois_ctrl_mode_t; +int32_t lsm6dsv32x_ois_ctrl_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_ctrl_mode_t val); +int32_t lsm6dsv32x_ois_ctrl_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_ctrl_mode_t *val); + +int32_t lsm6dsv32x_ois_reset_set(const stmdev_ctx_t *ctx, int8_t val); +int32_t lsm6dsv32x_ois_reset_get(const stmdev_ctx_t *ctx, int8_t *val); + +int32_t lsm6dsv32x_ois_interface_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_ois_interface_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t ack : 1; + uint8_t req : 1; +} lsm6dsv32x_ois_handshake_t; +int32_t lsm6dsv32x_ois_handshake_from_ui_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_handshake_t val); +int32_t lsm6dsv32x_ois_handshake_from_ui_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_handshake_t *val); +int32_t lsm6dsv32x_ois_handshake_from_ois_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_handshake_t val); +int32_t lsm6dsv32x_ois_handshake_from_ois_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_handshake_t *val); + +int32_t lsm6dsv32x_ois_shared_set(const stmdev_ctx_t *ctx, uint8_t val[6]); +int32_t lsm6dsv32x_ois_shared_get(const stmdev_ctx_t *ctx, uint8_t val[6]); + +int32_t lsm6dsv32x_ois_on_spi2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_ois_on_spi2_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t gy : 1; + uint8_t xl : 1; +} lsm6dsv32x_ois_chain_t; +int32_t lsm6dsv32x_ois_chain_set(const stmdev_ctx_t *ctx, lsm6dsv32x_ois_chain_t val); +int32_t lsm6dsv32x_ois_chain_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_chain_t *val); + +typedef enum +{ + LSM6DSV32X_OIS_125dps = 0x0, + LSM6DSV32X_OIS_250dps = 0x1, + LSM6DSV32X_OIS_500dps = 0x2, + LSM6DSV32X_OIS_1000dps = 0x3, + LSM6DSV32X_OIS_2000dps = 0x4, +} lsm6dsv32x_ois_gy_full_scale_t; +int32_t lsm6dsv32x_ois_gy_full_scale_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_gy_full_scale_t val); +int32_t lsm6dsv32x_ois_gy_full_scale_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_gy_full_scale_t *val); + +typedef enum +{ + LSM6DSV32X_OIS_4g = 0x0, + LSM6DSV32X_OIS_8g = 0x1, + LSM6DSV32X_OIS_16g = 0x2, + LSM6DSV32X_OIS_32g = 0x3, +} lsm6dsv32x_ois_xl_full_scale_t; +int32_t lsm6dsv32x_ois_xl_full_scale_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_xl_full_scale_t val); +int32_t lsm6dsv32x_ois_xl_full_scale_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_ois_xl_full_scale_t *val); + +typedef enum +{ + LSM6DSV32X_DEG_80 = 0x0, + LSM6DSV32X_DEG_70 = 0x1, + LSM6DSV32X_DEG_60 = 0x2, + LSM6DSV32X_DEG_50 = 0x3, +} lsm6dsv32x_6d_threshold_t; +int32_t lsm6dsv32x_6d_threshold_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_6d_threshold_t val); +int32_t lsm6dsv32x_6d_threshold_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_6d_threshold_t *val); + +int32_t lsm6dsv32x_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV32X_2400MOhm = 0x0, + LSM6DSV32X_730MOhm = 0x1, + LSM6DSV32X_300MOhm = 0x2, + LSM6DSV32X_255MOhm = 0x3, +} lsm6dsv32x_ah_qvar_zin_t; +int32_t lsm6dsv32x_ah_qvar_zin_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_ah_qvar_zin_t val); +int32_t lsm6dsv32x_ah_qvar_zin_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_ah_qvar_zin_t *val); + +typedef struct +{ + uint8_t ah_qvar_en : 1; +} lsm6dsv32x_ah_qvar_mode_t; +int32_t lsm6dsv32x_ah_qvar_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_ah_qvar_mode_t val); +int32_t lsm6dsv32x_ah_qvar_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_ah_qvar_mode_t *val); + +typedef enum +{ + LSM6DSV32X_SW_RST_DYN_ADDRESS_RST = 0x0, + LSM6DSV32X_I3C_GLOBAL_RST = 0x1, +} lsm6dsv32x_i3c_reset_mode_t; +int32_t lsm6dsv32x_i3c_reset_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_i3c_reset_mode_t val); +int32_t lsm6dsv32x_i3c_reset_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_i3c_reset_mode_t *val); + +int32_t lsm6dsv32x_i3c_int_en_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_i3c_int_en_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV32X_IBI_2us = 0x0, + LSM6DSV32X_IBI_50us = 0x1, + LSM6DSV32X_IBI_1ms = 0x2, + LSM6DSV32X_IBI_25ms = 0x3, +} lsm6dsv32x_i3c_ibi_time_t; +int32_t lsm6dsv32x_i3c_ibi_time_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_i3c_ibi_time_t val); +int32_t lsm6dsv32x_i3c_ibi_time_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_i3c_ibi_time_t *val); + +int32_t lsm6dsv32x_sh_master_interface_pull_up_set(const stmdev_ctx_t *ctx, + uint8_t val); +int32_t lsm6dsv32x_sh_master_interface_pull_up_get(const stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6dsv32x_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, + uint8_t len); + +typedef enum +{ + LSM6DSV32X_SLV_0 = 0x0, + LSM6DSV32X_SLV_0_1 = 0x1, + LSM6DSV32X_SLV_0_1_2 = 0x2, + LSM6DSV32X_SLV_0_1_2_3 = 0x3, +} lsm6dsv32x_sh_slave_connected_t; +int32_t lsm6dsv32x_sh_slave_connected_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_sh_slave_connected_t val); +int32_t lsm6dsv32x_sh_slave_connected_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_sh_slave_connected_t *val); + +int32_t lsm6dsv32x_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv32x_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV32X_SH_TRG_XL_GY_DRDY = 0x0, + LSM6DSV32X_SH_TRIG_INT2 = 0x1, +} lsm6dsv32x_sh_syncro_mode_t; +int32_t lsm6dsv32x_sh_syncro_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_sh_syncro_mode_t val); +int32_t lsm6dsv32x_sh_syncro_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_sh_syncro_mode_t *val); + +typedef enum +{ + LSM6DSV32X_EACH_SH_CYCLE = 0x0, + LSM6DSV32X_ONLY_FIRST_CYCLE = 0x1, +} lsm6dsv32x_sh_write_mode_t; +int32_t lsm6dsv32x_sh_write_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_sh_write_mode_t val); +int32_t lsm6dsv32x_sh_write_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_sh_write_mode_t *val); + +int32_t lsm6dsv32x_sh_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t slv0_add; + uint8_t slv0_subadd; + uint8_t slv0_data; +} lsm6dsv32x_sh_cfg_write_t; +int32_t lsm6dsv32x_sh_cfg_write(const stmdev_ctx_t *ctx, + lsm6dsv32x_sh_cfg_write_t *val); +typedef enum +{ + LSM6DSV32X_SH_15Hz = 0x1, + LSM6DSV32X_SH_30Hz = 0x2, + LSM6DSV32X_SH_60Hz = 0x3, + LSM6DSV32X_SH_120Hz = 0x4, + LSM6DSV32X_SH_240Hz = 0x5, + LSM6DSV32X_SH_480Hz = 0x6, +} lsm6dsv32x_sh_data_rate_t; +int32_t lsm6dsv32x_sh_data_rate_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_sh_data_rate_t val); +int32_t lsm6dsv32x_sh_data_rate_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_sh_data_rate_t *val); + +typedef struct +{ + uint8_t slv_add; + uint8_t slv_subadd; + uint8_t slv_len; +} lsm6dsv32x_sh_cfg_read_t; +int32_t lsm6dsv32x_sh_slv_cfg_read(const stmdev_ctx_t *ctx, uint8_t idx, + lsm6dsv32x_sh_cfg_read_t *val); + +int32_t lsm6dsv32x_sh_status_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_status_master_t *val); + +int32_t lsm6dsv32x_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV32X_I2C_I3C_ENABLE = 0x0, + LSM6DSV32X_I2C_I3C_DISABLE = 0x1, +} lsm6dsv32x_ui_i2c_i3c_mode_t; +int32_t lsm6dsv32x_ui_i2c_i3c_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_ui_i2c_i3c_mode_t val); +int32_t lsm6dsv32x_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_ui_i2c_i3c_mode_t *val); + +typedef enum +{ + LSM6DSV32X_SPI_4_WIRE = 0x0, + LSM6DSV32X_SPI_3_WIRE = 0x1, +} lsm6dsv32x_spi_mode_t; +int32_t lsm6dsv32x_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsv32x_spi_mode_t val); +int32_t lsm6dsv32x_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsv32x_spi_mode_t *val); + +int32_t lsm6dsv32x_ui_sda_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV32X_SPI2_4_WIRE = 0x0, + LSM6DSV32X_SPI2_3_WIRE = 0x1, +} lsm6dsv32x_spi2_mode_t; +int32_t lsm6dsv32x_spi2_mode_set(const stmdev_ctx_t *ctx, lsm6dsv32x_spi2_mode_t val); +int32_t lsm6dsv32x_spi2_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_spi2_mode_t *val); + +int32_t lsm6dsv32x_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t step_counter_enable : 1; + uint8_t false_step_rej : 1; +} lsm6dsv32x_stpcnt_mode_t; +int32_t lsm6dsv32x_stpcnt_mode_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_stpcnt_mode_t val); +int32_t lsm6dsv32x_stpcnt_mode_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_stpcnt_mode_t *val); + +int32_t lsm6dsv32x_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lsm6dsv32x_stpcnt_rst_step_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv32x_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv32x_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv32x_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lsm6dsv32x_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + float_t gbias_x; /* dps */ + float_t gbias_y; /* dps */ + float_t gbias_z; /* dps */ +} lsm6dsv32x_sflp_gbias_t; +int32_t lsm6dsv32x_sflp_game_gbias_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_sflp_gbias_t *val); + +typedef enum +{ + LSM6DSV32X_SFLP_15Hz = 0x0, + LSM6DSV32X_SFLP_30Hz = 0x1, + LSM6DSV32X_SFLP_60Hz = 0x2, + LSM6DSV32X_SFLP_120Hz = 0x3, + LSM6DSV32X_SFLP_240Hz = 0x4, + LSM6DSV32X_SFLP_480Hz = 0x5, +} lsm6dsv32x_sflp_data_rate_t; +int32_t lsm6dsv32x_sflp_data_rate_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_sflp_data_rate_t val); +int32_t lsm6dsv32x_sflp_data_rate_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_sflp_data_rate_t *val); + +typedef struct +{ + uint8_t tap_x_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_z_en : 1; +} lsm6dsv32x_tap_detection_t; +int32_t lsm6dsv32x_tap_detection_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_tap_detection_t val); +int32_t lsm6dsv32x_tap_detection_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_tap_detection_t *val); + +typedef struct +{ + uint8_t x : 5; + uint8_t y : 5; + uint8_t z : 5; +} lsm6dsv32x_tap_thresholds_t; +int32_t lsm6dsv32x_tap_thresholds_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_tap_thresholds_t val); +int32_t lsm6dsv32x_tap_thresholds_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_tap_thresholds_t *val); + +typedef enum +{ + LSM6DSV32X_XYZ = 0x0, + LSM6DSV32X_YXZ = 0x1, + LSM6DSV32X_XZY = 0x2, + LSM6DSV32X_ZYX = 0x3, + LSM6DSV32X_YZX = 0x5, + LSM6DSV32X_ZXY = 0x6, +} lsm6dsv32x_tap_axis_priority_t; +int32_t lsm6dsv32x_tap_axis_priority_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_tap_axis_priority_t val); +int32_t lsm6dsv32x_tap_axis_priority_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_tap_axis_priority_t *val); + +typedef struct +{ + uint8_t shock : 2; + uint8_t quiet : 2; + uint8_t tap_gap : 4; +} lsm6dsv32x_tap_time_windows_t; +int32_t lsm6dsv32x_tap_time_windows_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_tap_time_windows_t val); +int32_t lsm6dsv32x_tap_time_windows_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_tap_time_windows_t *val); + +typedef enum +{ + LSM6DSV32X_ONLY_SINGLE = 0x0, + LSM6DSV32X_BOTH_SINGLE_DOUBLE = 0x1, +} lsm6dsv32x_tap_mode_t; +int32_t lsm6dsv32x_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dsv32x_tap_mode_t val); +int32_t lsm6dsv32x_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dsv32x_tap_mode_t *val); + +int32_t lsm6dsv32x_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6dsv32x_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); + +int32_t lsm6dsv32x_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv32x_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + LSM6DSV32X_XL_AND_GY_NOT_AFFECTED = 0x0, + LSM6DSV32X_XL_LOW_POWER_GY_NOT_AFFECTED = 0x1, + LSM6DSV32X_XL_LOW_POWER_GY_SLEEP = 0x2, + LSM6DSV32X_XL_LOW_POWER_GY_POWER_DOWN = 0x3, +} lsm6dsv32x_act_mode_t; +int32_t lsm6dsv32x_act_mode_set(const stmdev_ctx_t *ctx, lsm6dsv32x_act_mode_t val); +int32_t lsm6dsv32x_act_mode_get(const stmdev_ctx_t *ctx, lsm6dsv32x_act_mode_t *val); + +typedef enum +{ + LSM6DSV32X_SLEEP_TO_ACT_AT_1ST_SAMPLE = 0x0, + LSM6DSV32X_SLEEP_TO_ACT_AT_2ND_SAMPLE = 0x1, + LSM6DSV32X_SLEEP_TO_ACT_AT_3RD_SAMPLE = 0x2, + LSM6DSV32X_SLEEP_TO_ACT_AT_4th_SAMPLE = 0x3, +} lsm6dsv32x_act_from_sleep_to_act_dur_t; +int32_t lsm6dsv32x_act_from_sleep_to_act_dur_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_act_from_sleep_to_act_dur_t val); +int32_t lsm6dsv32x_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_act_from_sleep_to_act_dur_t *val); + +typedef enum +{ + LSM6DSV32X_1Hz875 = 0x0, + LSM6DSV32X_15Hz = 0x1, + LSM6DSV32X_30Hz = 0x2, + LSM6DSV32X_60Hz = 0x3, +} lsm6dsv32x_act_sleep_xl_odr_t; +int32_t lsm6dsv32x_act_sleep_xl_odr_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_act_sleep_xl_odr_t val); +int32_t lsm6dsv32x_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_act_sleep_xl_odr_t *val); + +typedef struct +{ + lsm6dsv32x_inactivity_dur_t inactivity_cfg; + uint8_t inactivity_ths; + uint8_t threshold; + uint8_t duration; +} lsm6dsv32x_act_thresholds_t; +int32_t lsm6dsv32x_act_thresholds_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_act_thresholds_t *val); +int32_t lsm6dsv32x_act_thresholds_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_act_thresholds_t *val); + +typedef struct +{ + uint8_t shock : 2; + uint8_t quiet : 4; +} lsm6dsv32x_act_wkup_time_windows_t; +int32_t lsm6dsv32x_act_wkup_time_windows_set(const stmdev_ctx_t *ctx, + lsm6dsv32x_act_wkup_time_windows_t val); +int32_t lsm6dsv32x_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, + lsm6dsv32x_act_wkup_time_windows_t *val); + +/** + * @} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /*LSM6DSV32X_DRIVER_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/lsm6dsv_STdC/driver/lsm6dsv_reg.c b/sensor/stmemsc/lsm6dsv_STdC/driver/lsm6dsv_reg.c index 1b1f6b9c..0f0ba0cc 100644 --- a/sensor/stmemsc/lsm6dsv_STdC/driver/lsm6dsv_reg.c +++ b/sensor/stmemsc/lsm6dsv_STdC/driver/lsm6dsv_reg.c @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2022 STMicroelectronics. + *

© Copyright (c) 2024 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm6dsv_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm6dsv_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lsm6dsv_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm6dsv_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm6dsv_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -195,7 +205,7 @@ float_t lsm6dsv_from_lsb_to_nsec(uint32_t lsb) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_xl_offset_on_out_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_xl_offset_on_out_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_ctrl9_t ctrl9; int32_t ret; @@ -218,7 +228,7 @@ int32_t lsm6dsv_xl_offset_on_out_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_xl_offset_on_out_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_ctrl9_t ctrl9; int32_t ret; @@ -237,7 +247,7 @@ int32_t lsm6dsv_xl_offset_on_out_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_xl_offset_mg_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_xl_offset_mg_set(const stmdev_ctx_t *ctx, lsm6dsv_xl_offset_mg_t val) { lsm6dsv_z_ofs_usr_t z_ofs_usr; @@ -250,7 +260,10 @@ int32_t lsm6dsv_xl_offset_mg_set(stmdev_ctx_t *ctx, ret = lsm6dsv_read_reg(ctx, LSM6DSV_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); ret += lsm6dsv_read_reg(ctx, LSM6DSV_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); ret += lsm6dsv_read_reg(ctx, LSM6DSV_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } if ((val.x_mg < (0.0078125f * 127.0f)) && (val.x_mg > (0.0078125f * -127.0f)) && @@ -307,7 +320,7 @@ int32_t lsm6dsv_xl_offset_mg_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_xl_offset_mg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_xl_offset_mg_get(const stmdev_ctx_t *ctx, lsm6dsv_xl_offset_mg_t *val) { lsm6dsv_z_ofs_usr_t z_ofs_usr; @@ -320,7 +333,10 @@ int32_t lsm6dsv_xl_offset_mg_get(stmdev_ctx_t *ctx, ret += lsm6dsv_read_reg(ctx, LSM6DSV_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); ret += lsm6dsv_read_reg(ctx, LSM6DSV_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); ret += lsm6dsv_read_reg(ctx, LSM6DSV_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } if (ctrl9.usr_off_w == PROPERTY_DISABLE) { @@ -351,7 +367,7 @@ int32_t lsm6dsv_xl_offset_mg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_reset_set(stmdev_ctx_t *ctx, lsm6dsv_reset_t val) +int32_t lsm6dsv_reset_set(const stmdev_ctx_t *ctx, lsm6dsv_reset_t val) { lsm6dsv_func_cfg_access_t func_cfg_access; lsm6dsv_ctrl3_t ctrl3; @@ -359,7 +375,10 @@ int32_t lsm6dsv_reset_set(stmdev_ctx_t *ctx, lsm6dsv_reset_t val) ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL3, (uint8_t *)&ctrl3, 1); ret += lsm6dsv_read_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ctrl3.boot = ((uint8_t)val & 0x04U) >> 2; ctrl3.sw_reset = ((uint8_t)val & 0x02U) >> 1; @@ -379,7 +398,7 @@ int32_t lsm6dsv_reset_set(stmdev_ctx_t *ctx, lsm6dsv_reset_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_reset_get(stmdev_ctx_t *ctx, lsm6dsv_reset_t *val) +int32_t lsm6dsv_reset_get(const stmdev_ctx_t *ctx, lsm6dsv_reset_t *val) { lsm6dsv_func_cfg_access_t func_cfg_access; lsm6dsv_ctrl3_t ctrl3; @@ -387,7 +406,10 @@ int32_t lsm6dsv_reset_get(stmdev_ctx_t *ctx, lsm6dsv_reset_t *val) ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL3, (uint8_t *)&ctrl3, 1); ret += lsm6dsv_read_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch ((ctrl3.sw_reset << 2) + (ctrl3.boot << 1) + func_cfg_access.sw_por) { @@ -423,13 +445,16 @@ int32_t lsm6dsv_reset_get(stmdev_ctx_t *ctx, lsm6dsv_reset_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsv_mem_bank_t val) +int32_t lsm6dsv_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dsv_mem_bank_t val) { lsm6dsv_func_cfg_access_t func_cfg_access; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } func_cfg_access.shub_reg_access = ((uint8_t)val & 0x02U) >> 1; func_cfg_access.emb_func_reg_access = (uint8_t)val & 0x01U; @@ -446,13 +471,16 @@ int32_t lsm6dsv_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsv_mem_bank_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_mem_bank_get(stmdev_ctx_t *ctx, lsm6dsv_mem_bank_t *val) +int32_t lsm6dsv_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dsv_mem_bank_t *val) { lsm6dsv_func_cfg_access_t func_cfg_access; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch ((func_cfg_access.shub_reg_access << 1) + func_cfg_access.emb_func_reg_access) { @@ -485,7 +513,7 @@ int32_t lsm6dsv_mem_bank_get(stmdev_ctx_t *ctx, lsm6dsv_mem_bank_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_device_id_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -502,7 +530,7 @@ int32_t lsm6dsv_device_id_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv_data_rate_t val) { lsm6dsv_ctrl1_t ctrl1; @@ -511,11 +539,17 @@ int32_t lsm6dsv_xl_data_rate_set(stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL1, (uint8_t *)&ctrl1, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ctrl1.odr_xl = (uint8_t)val & 0x0Fu; ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL1, (uint8_t *)&ctrl1, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } sel = ((uint8_t)val >> 4) & 0xFU; if (sel != 0U) @@ -536,7 +570,7 @@ int32_t lsm6dsv_xl_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv_data_rate_t *val) { lsm6dsv_ctrl1_t ctrl1; @@ -546,7 +580,10 @@ int32_t lsm6dsv_xl_data_rate_get(stmdev_ctx_t *ctx, ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL1, (uint8_t *)&ctrl1, 1); ret += lsm6dsv_read_reg(ctx, LSM6DSV_HAODR_CFG, (uint8_t *)&haodr, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } sel = haodr.haodr_sel; @@ -565,152 +602,162 @@ int32_t lsm6dsv_xl_data_rate_get(stmdev_ctx_t *ctx, break; case LSM6DSV_ODR_AT_15Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV_ODR_AT_15Hz; - break; - case 1: - *val = LSM6DSV_ODR_HA01_AT_15Hz625; - break; - case 2: - *val = LSM6DSV_ODR_HA02_AT_12Hz5; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV_ODR_AT_15Hz; + break; + case 1: + *val = LSM6DSV_ODR_HA01_AT_15Hz625; + break; + case 2: + *val = LSM6DSV_ODR_HA02_AT_12Hz5; + break; } break; case LSM6DSV_ODR_AT_30Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV_ODR_AT_30Hz; - break; - case 1: - *val = LSM6DSV_ODR_HA01_AT_31Hz25; - break; - case 2: - *val = LSM6DSV_ODR_HA02_AT_25Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV_ODR_AT_30Hz; + break; + case 1: + *val = LSM6DSV_ODR_HA01_AT_31Hz25; + break; + case 2: + *val = LSM6DSV_ODR_HA02_AT_25Hz; + break; } break; case LSM6DSV_ODR_AT_60Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV_ODR_AT_60Hz; - break; - case 1: - *val = LSM6DSV_ODR_HA01_AT_62Hz5; - break; - case 2: - *val = LSM6DSV_ODR_HA02_AT_50Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV_ODR_AT_60Hz; + break; + case 1: + *val = LSM6DSV_ODR_HA01_AT_62Hz5; + break; + case 2: + *val = LSM6DSV_ODR_HA02_AT_50Hz; + break; } break; case LSM6DSV_ODR_AT_120Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV_ODR_AT_120Hz; - break; - case 1: - *val = LSM6DSV_ODR_HA01_AT_125Hz; - break; - case 2: - *val = LSM6DSV_ODR_HA02_AT_100Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV_ODR_AT_120Hz; + break; + case 1: + *val = LSM6DSV_ODR_HA01_AT_125Hz; + break; + case 2: + *val = LSM6DSV_ODR_HA02_AT_100Hz; + break; } break; case LSM6DSV_ODR_AT_240Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV_ODR_AT_240Hz; - break; - case 1: - *val = LSM6DSV_ODR_HA01_AT_250Hz; - break; - case 2: - *val = LSM6DSV_ODR_HA02_AT_200Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV_ODR_AT_240Hz; + break; + case 1: + *val = LSM6DSV_ODR_HA01_AT_250Hz; + break; + case 2: + *val = LSM6DSV_ODR_HA02_AT_200Hz; + break; } break; case LSM6DSV_ODR_AT_480Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV_ODR_AT_480Hz; - break; - case 1: - *val = LSM6DSV_ODR_HA01_AT_500Hz; - break; - case 2: - *val = LSM6DSV_ODR_HA02_AT_400Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV_ODR_AT_480Hz; + break; + case 1: + *val = LSM6DSV_ODR_HA01_AT_500Hz; + break; + case 2: + *val = LSM6DSV_ODR_HA02_AT_400Hz; + break; } break; case LSM6DSV_ODR_AT_960Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV_ODR_AT_960Hz; - break; - case 1: - *val = LSM6DSV_ODR_HA01_AT_1000Hz; - break; - case 2: - *val = LSM6DSV_ODR_HA02_AT_800Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV_ODR_AT_960Hz; + break; + case 1: + *val = LSM6DSV_ODR_HA01_AT_1000Hz; + break; + case 2: + *val = LSM6DSV_ODR_HA02_AT_800Hz; + break; } break; case LSM6DSV_ODR_AT_1920Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV_ODR_AT_1920Hz; - break; - case 1: - *val = LSM6DSV_ODR_HA01_AT_2000Hz; - break; - case 2: - *val = LSM6DSV_ODR_HA02_AT_1600Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV_ODR_AT_1920Hz; + break; + case 1: + *val = LSM6DSV_ODR_HA01_AT_2000Hz; + break; + case 2: + *val = LSM6DSV_ODR_HA02_AT_1600Hz; + break; } break; case LSM6DSV_ODR_AT_3840Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV_ODR_AT_3840Hz; - break; - case 1: - *val = LSM6DSV_ODR_HA01_AT_4000Hz; - break; - case 2: - *val = LSM6DSV_ODR_HA02_AT_3200Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV_ODR_AT_3840Hz; + break; + case 1: + *val = LSM6DSV_ODR_HA01_AT_4000Hz; + break; + case 2: + *val = LSM6DSV_ODR_HA02_AT_3200Hz; + break; } break; case LSM6DSV_ODR_AT_7680Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV_ODR_AT_7680Hz; - break; - case 1: - *val = LSM6DSV_ODR_HA01_AT_8000Hz; - break; - case 2: - *val = LSM6DSV_ODR_HA02_AT_6400Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV_ODR_AT_7680Hz; + break; + case 1: + *val = LSM6DSV_ODR_HA01_AT_8000Hz; + break; + case 2: + *val = LSM6DSV_ODR_HA02_AT_6400Hz; + break; } break; @@ -730,7 +777,7 @@ int32_t lsm6dsv_xl_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_xl_mode_set(stmdev_ctx_t *ctx, lsm6dsv_xl_mode_t val) +int32_t lsm6dsv_xl_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_xl_mode_t val) { lsm6dsv_ctrl1_t ctrl1; int32_t ret; @@ -754,13 +801,16 @@ int32_t lsm6dsv_xl_mode_set(stmdev_ctx_t *ctx, lsm6dsv_xl_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_xl_mode_get(stmdev_ctx_t *ctx, lsm6dsv_xl_mode_t *val) +int32_t lsm6dsv_xl_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_xl_mode_t *val) { lsm6dsv_ctrl1_t ctrl1; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL1, (uint8_t *)&ctrl1, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl1.op_mode_xl) { @@ -808,7 +858,7 @@ int32_t lsm6dsv_xl_mode_get(stmdev_ctx_t *ctx, lsm6dsv_xl_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_gy_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv_data_rate_t val) { lsm6dsv_ctrl2_t ctrl2; @@ -817,9 +867,13 @@ int32_t lsm6dsv_gy_data_rate_set(stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL2, (uint8_t *)&ctrl2, 1); + ctrl2.odr_g = (uint8_t)val & 0x0Fu; ret += lsm6dsv_write_reg(ctx, LSM6DSV_CTRL2, (uint8_t *)&ctrl2, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } sel = ((uint8_t)val >> 4) & 0xFU; if (sel != 0U) @@ -840,7 +894,7 @@ int32_t lsm6dsv_gy_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv_data_rate_t *val) { lsm6dsv_ctrl2_t ctrl2; @@ -850,7 +904,10 @@ int32_t lsm6dsv_gy_data_rate_get(stmdev_ctx_t *ctx, ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL2, (uint8_t *)&ctrl2, 1); ret += lsm6dsv_read_reg(ctx, LSM6DSV_HAODR_CFG, (uint8_t *)&haodr, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } sel = haodr.haodr_sel; @@ -869,152 +926,162 @@ int32_t lsm6dsv_gy_data_rate_get(stmdev_ctx_t *ctx, break; case LSM6DSV_ODR_AT_15Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV_ODR_AT_15Hz; - break; - case 1: - *val = LSM6DSV_ODR_HA01_AT_15Hz625; - break; - case 2: - *val = LSM6DSV_ODR_HA02_AT_12Hz5; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV_ODR_AT_15Hz; + break; + case 1: + *val = LSM6DSV_ODR_HA01_AT_15Hz625; + break; + case 2: + *val = LSM6DSV_ODR_HA02_AT_12Hz5; + break; } break; case LSM6DSV_ODR_AT_30Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV_ODR_AT_30Hz; - break; - case 1: - *val = LSM6DSV_ODR_HA01_AT_31Hz25; - break; - case 2: - *val = LSM6DSV_ODR_HA02_AT_25Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV_ODR_AT_30Hz; + break; + case 1: + *val = LSM6DSV_ODR_HA01_AT_31Hz25; + break; + case 2: + *val = LSM6DSV_ODR_HA02_AT_25Hz; + break; } break; case LSM6DSV_ODR_AT_60Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV_ODR_AT_60Hz; - break; - case 1: - *val = LSM6DSV_ODR_HA01_AT_62Hz5; - break; - case 2: - *val = LSM6DSV_ODR_HA02_AT_50Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV_ODR_AT_60Hz; + break; + case 1: + *val = LSM6DSV_ODR_HA01_AT_62Hz5; + break; + case 2: + *val = LSM6DSV_ODR_HA02_AT_50Hz; + break; } break; case LSM6DSV_ODR_AT_120Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV_ODR_AT_120Hz; - break; - case 1: - *val = LSM6DSV_ODR_HA01_AT_125Hz; - break; - case 2: - *val = LSM6DSV_ODR_HA02_AT_100Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV_ODR_AT_120Hz; + break; + case 1: + *val = LSM6DSV_ODR_HA01_AT_125Hz; + break; + case 2: + *val = LSM6DSV_ODR_HA02_AT_100Hz; + break; } break; case LSM6DSV_ODR_AT_240Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV_ODR_AT_240Hz; - break; - case 1: - *val = LSM6DSV_ODR_HA01_AT_250Hz; - break; - case 2: - *val = LSM6DSV_ODR_HA02_AT_200Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV_ODR_AT_240Hz; + break; + case 1: + *val = LSM6DSV_ODR_HA01_AT_250Hz; + break; + case 2: + *val = LSM6DSV_ODR_HA02_AT_200Hz; + break; } break; case LSM6DSV_ODR_AT_480Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV_ODR_AT_480Hz; - break; - case 1: - *val = LSM6DSV_ODR_HA01_AT_500Hz; - break; - case 2: - *val = LSM6DSV_ODR_HA02_AT_400Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV_ODR_AT_480Hz; + break; + case 1: + *val = LSM6DSV_ODR_HA01_AT_500Hz; + break; + case 2: + *val = LSM6DSV_ODR_HA02_AT_400Hz; + break; } break; case LSM6DSV_ODR_AT_960Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV_ODR_AT_960Hz; - break; - case 1: - *val = LSM6DSV_ODR_HA01_AT_1000Hz; - break; - case 2: - *val = LSM6DSV_ODR_HA02_AT_800Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV_ODR_AT_960Hz; + break; + case 1: + *val = LSM6DSV_ODR_HA01_AT_1000Hz; + break; + case 2: + *val = LSM6DSV_ODR_HA02_AT_800Hz; + break; } break; case LSM6DSV_ODR_AT_1920Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV_ODR_AT_1920Hz; - break; - case 1: - *val = LSM6DSV_ODR_HA01_AT_2000Hz; - break; - case 2: - *val = LSM6DSV_ODR_HA02_AT_1600Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV_ODR_AT_1920Hz; + break; + case 1: + *val = LSM6DSV_ODR_HA01_AT_2000Hz; + break; + case 2: + *val = LSM6DSV_ODR_HA02_AT_1600Hz; + break; } break; case LSM6DSV_ODR_AT_3840Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV_ODR_AT_3840Hz; - break; - case 1: - *val = LSM6DSV_ODR_HA01_AT_4000Hz; - break; - case 2: - *val = LSM6DSV_ODR_HA02_AT_3200Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV_ODR_AT_3840Hz; + break; + case 1: + *val = LSM6DSV_ODR_HA01_AT_4000Hz; + break; + case 2: + *val = LSM6DSV_ODR_HA02_AT_3200Hz; + break; } break; case LSM6DSV_ODR_AT_7680Hz: - switch (sel) { - default: - case 0: - *val = LSM6DSV_ODR_AT_7680Hz; - break; - case 1: - *val = LSM6DSV_ODR_HA01_AT_8000Hz; - break; - case 2: - *val = LSM6DSV_ODR_HA02_AT_6400Hz; - break; + switch (sel) + { + default: + case 0: + *val = LSM6DSV_ODR_AT_7680Hz; + break; + case 1: + *val = LSM6DSV_ODR_HA01_AT_8000Hz; + break; + case 2: + *val = LSM6DSV_ODR_HA02_AT_6400Hz; + break; } break; @@ -1034,7 +1101,7 @@ int32_t lsm6dsv_gy_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_gy_mode_set(stmdev_ctx_t *ctx, lsm6dsv_gy_mode_t val) +int32_t lsm6dsv_gy_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_gy_mode_t val) { lsm6dsv_ctrl2_t ctrl2; int32_t ret; @@ -1057,13 +1124,16 @@ int32_t lsm6dsv_gy_mode_set(stmdev_ctx_t *ctx, lsm6dsv_gy_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_gy_mode_get(stmdev_ctx_t *ctx, lsm6dsv_gy_mode_t *val) +int32_t lsm6dsv_gy_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_gy_mode_t *val) { lsm6dsv_ctrl2_t ctrl2; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL2, (uint8_t *)&ctrl2, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl2.op_mode_g) { @@ -1099,7 +1169,7 @@ int32_t lsm6dsv_gy_mode_get(stmdev_ctx_t *ctx, lsm6dsv_gy_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_ctrl3_t ctrl3; int32_t ret; @@ -1122,7 +1192,7 @@ int32_t lsm6dsv_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_ctrl3_t ctrl3; int32_t ret; @@ -1141,7 +1211,7 @@ int32_t lsm6dsv_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_ctrl3_t ctrl3; int32_t ret; @@ -1165,7 +1235,7 @@ int32_t lsm6dsv_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_ctrl3_t ctrl3; int32_t ret; @@ -1184,12 +1254,13 @@ int32_t lsm6dsv_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_odr_trig_cfg_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_odr_trig_cfg_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_odr_trig_cfg_t odr_trig; int32_t ret; - if (val >= 1U && val <= 3U) { + if (val >= 1U && val <= 3U) + { return -1; } @@ -1212,7 +1283,7 @@ int32_t lsm6dsv_odr_trig_cfg_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_odr_trig_cfg_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_odr_trig_cfg_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_odr_trig_cfg_t odr_trig; int32_t ret; @@ -1231,7 +1302,7 @@ int32_t lsm6dsv_odr_trig_cfg_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_data_ready_mode_t val) { lsm6dsv_ctrl4_t ctrl4; @@ -1256,7 +1327,7 @@ int32_t lsm6dsv_data_ready_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_data_ready_mode_t *val) { lsm6dsv_ctrl4_t ctrl4; @@ -1290,7 +1361,7 @@ int32_t lsm6dsv_data_ready_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_interrupt_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_interrupt_enable_set(const stmdev_ctx_t *ctx, lsm6dsv_interrupt_mode_t val) { lsm6dsv_tap_cfg0_t cfg; @@ -1300,7 +1371,10 @@ int32_t lsm6dsv_interrupt_enable_set(stmdev_ctx_t *ctx, ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); func.interrupts_enable = val.enable; ret += lsm6dsv_write_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&cfg, 1); cfg.lir = val.lir; @@ -1317,7 +1391,7 @@ int32_t lsm6dsv_interrupt_enable_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_interrupt_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_interrupt_enable_get(const stmdev_ctx_t *ctx, lsm6dsv_interrupt_mode_t *val) { lsm6dsv_tap_cfg0_t cfg; @@ -1326,7 +1400,10 @@ int32_t lsm6dsv_interrupt_enable_get(stmdev_ctx_t *ctx, ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&func, 1); ret += lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&cfg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->enable = func.interrupts_enable; val->lir = cfg.lir; @@ -1342,7 +1419,7 @@ int32_t lsm6dsv_interrupt_enable_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsv_gy_full_scale_t val) { lsm6dsv_ctrl6_t ctrl6; @@ -1367,14 +1444,17 @@ int32_t lsm6dsv_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsv_gy_full_scale_t *val) { lsm6dsv_ctrl6_t ctrl6; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL6, (uint8_t *)&ctrl6, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl6.fs_g) { @@ -1414,11 +1494,11 @@ int32_t lsm6dsv_gy_full_scale_get(stmdev_ctx_t *ctx, * @brief Accelerometer full-scale selection.[set] * * @param ctx read / write interface definitions - * @param val 2g, 4g, 8g, 16g, + * @param val lsm6dsv_xl_full_scale_t * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsv_xl_full_scale_t val) { lsm6dsv_ctrl8_t ctrl8; @@ -1439,18 +1519,21 @@ int32_t lsm6dsv_xl_full_scale_set(stmdev_ctx_t *ctx, * @brief Accelerometer full-scale selection.[get] * * @param ctx read / write interface definitions - * @param val 2g, 4g, 8g, 16g, + * @param val lsm6dsv_xl_full_scale_t * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsv_xl_full_scale_t *val) { lsm6dsv_ctrl8_t ctrl8; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL8, (uint8_t *)&ctrl8, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl8.fs_xl) { @@ -1486,7 +1569,7 @@ int32_t lsm6dsv_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_xl_dual_channel_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_xl_dual_channel_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_ctrl8_t ctrl8; int32_t ret; @@ -1510,7 +1593,7 @@ int32_t lsm6dsv_xl_dual_channel_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_xl_dual_channel_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_ctrl8_t ctrl8; int32_t ret; @@ -1529,7 +1612,8 @@ int32_t lsm6dsv_xl_dual_channel_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_xl_self_test_set(stmdev_ctx_t *ctx, lsm6dsv_xl_self_test_t val) +int32_t lsm6dsv_xl_self_test_set(const stmdev_ctx_t *ctx, + lsm6dsv_xl_self_test_t val) { lsm6dsv_ctrl10_t ctrl10; int32_t ret; @@ -1553,13 +1637,17 @@ int32_t lsm6dsv_xl_self_test_set(stmdev_ctx_t *ctx, lsm6dsv_xl_self_test_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_xl_self_test_get(stmdev_ctx_t *ctx, lsm6dsv_xl_self_test_t *val) +int32_t lsm6dsv_xl_self_test_get(const stmdev_ctx_t *ctx, + lsm6dsv_xl_self_test_t *val) { lsm6dsv_ctrl10_t ctrl10; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL10, (uint8_t *)&ctrl10, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl10.st_xl) { @@ -1591,7 +1679,8 @@ int32_t lsm6dsv_xl_self_test_get(stmdev_ctx_t *ctx, lsm6dsv_xl_self_test_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_gy_self_test_set(stmdev_ctx_t *ctx, lsm6dsv_gy_self_test_t val) +int32_t lsm6dsv_gy_self_test_set(const stmdev_ctx_t *ctx, + lsm6dsv_gy_self_test_t val) { lsm6dsv_ctrl10_t ctrl10; int32_t ret; @@ -1615,13 +1704,17 @@ int32_t lsm6dsv_gy_self_test_set(stmdev_ctx_t *ctx, lsm6dsv_gy_self_test_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_gy_self_test_get(stmdev_ctx_t *ctx, lsm6dsv_gy_self_test_t *val) +int32_t lsm6dsv_gy_self_test_get(const stmdev_ctx_t *ctx, + lsm6dsv_gy_self_test_t *val) { lsm6dsv_ctrl10_t ctrl10; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL10, (uint8_t *)&ctrl10, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl10.st_g) { @@ -1653,7 +1746,7 @@ int32_t lsm6dsv_gy_self_test_get(stmdev_ctx_t *ctx, lsm6dsv_gy_self_test_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ois_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dsv_ois_xl_self_test_t val) { lsm6dsv_spi2_int_ois_t spi2_int_ois; @@ -1678,14 +1771,17 @@ int32_t lsm6dsv_ois_xl_self_test_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ois_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dsv_ois_xl_self_test_t *val) { lsm6dsv_spi2_int_ois_t spi2_int_ois; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (spi2_int_ois.st_xl_ois) { @@ -1717,7 +1813,7 @@ int32_t lsm6dsv_ois_xl_self_test_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ois_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dsv_ois_gy_self_test_t val) { lsm6dsv_spi2_int_ois_t spi2_int_ois; @@ -1743,14 +1839,17 @@ int32_t lsm6dsv_ois_gy_self_test_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ois_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dsv_ois_gy_self_test_t *val) { lsm6dsv_spi2_int_ois_t spi2_int_ois; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (spi2_int_ois.st_g_ois) { @@ -1759,11 +1858,13 @@ int32_t lsm6dsv_ois_gy_self_test_get(stmdev_ctx_t *ctx, break; case LSM6DSV_OIS_GY_ST_POSITIVE: - *val = (spi2_int_ois.st_ois_clampdis == 1U) ? LSM6DSV_OIS_GY_ST_CLAMP_POS : LSM6DSV_OIS_GY_ST_POSITIVE; + *val = (spi2_int_ois.st_ois_clampdis == 1U) ? LSM6DSV_OIS_GY_ST_CLAMP_POS : + LSM6DSV_OIS_GY_ST_POSITIVE; break; case LSM6DSV_OIS_GY_ST_NEGATIVE: - *val = (spi2_int_ois.st_ois_clampdis == 1U) ? LSM6DSV_OIS_GY_ST_CLAMP_NEG : LSM6DSV_OIS_GY_ST_NEGATIVE; + *val = (spi2_int_ois.st_ois_clampdis == 1U) ? LSM6DSV_OIS_GY_ST_CLAMP_NEG : + LSM6DSV_OIS_GY_ST_NEGATIVE; break; default: @@ -1790,15 +1891,24 @@ int32_t lsm6dsv_ois_gy_self_test_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsv_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm6dsv_pin_int_route_t *val) { lsm6dsv_int1_ctrl_t int1_ctrl; lsm6dsv_md1_cfg_t md1_cfg; int32_t ret; + /* not available on INT1 */ + if (val->drdy_temp == 1) + { + return -1; + } + ret = lsm6dsv_read_reg(ctx, LSM6DSV_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } int1_ctrl.int1_drdy_xl = val->drdy_xl; int1_ctrl.int1_drdy_g = val->drdy_g; @@ -1808,10 +1918,16 @@ int32_t lsm6dsv_pin_int1_route_set(stmdev_ctx_t *ctx, int1_ctrl.int1_cnt_bdr = val->cnt_bdr; ret = lsm6dsv_write_reg(ctx, LSM6DSV_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv_read_reg(ctx, LSM6DSV_MD1_CFG, (uint8_t *)&md1_cfg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } md1_cfg.int1_shub = val->shub; md1_cfg.int1_emb_func = val->emb_func; @@ -1835,7 +1951,7 @@ int32_t lsm6dsv_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsv_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm6dsv_pin_int_route_t *val) { lsm6dsv_int1_ctrl_t int1_ctrl; @@ -1843,7 +1959,10 @@ int32_t lsm6dsv_pin_int1_route_get(stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->drdy_xl = int1_ctrl.int1_drdy_xl; val->drdy_g = int1_ctrl.int1_drdy_g; @@ -1853,7 +1972,10 @@ int32_t lsm6dsv_pin_int1_route_get(stmdev_ctx_t *ctx, val->cnt_bdr = int1_ctrl.int1_cnt_bdr; ret = lsm6dsv_read_reg(ctx, LSM6DSV_MD1_CFG, (uint8_t *)&md1_cfg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->shub = md1_cfg.int1_shub; val->emb_func = md1_cfg.int1_emb_func; @@ -1875,15 +1997,19 @@ int32_t lsm6dsv_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsv_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm6dsv_pin_int_route_t *val) { lsm6dsv_int2_ctrl_t int2_ctrl; + lsm6dsv_ctrl4_t ctrl4; lsm6dsv_md2_cfg_t md2_cfg; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } int2_ctrl.int2_drdy_xl = val->drdy_xl; int2_ctrl.int2_drdy_g = val->drdy_g; @@ -1895,10 +2021,24 @@ int32_t lsm6dsv_pin_int2_route_set(stmdev_ctx_t *ctx, int2_ctrl.int2_emb_func_endop = val->emb_func_endop; ret = lsm6dsv_write_reg(ctx, LSM6DSV_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1); + ctrl4.int2_drdy_temp = val->drdy_temp; + ret += lsm6dsv_write_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } ret = lsm6dsv_read_reg(ctx, LSM6DSV_MD2_CFG, (uint8_t *)&md2_cfg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } md2_cfg.int2_timestamp = val->timestamp; md2_cfg.int2_emb_func = val->emb_func; @@ -1922,15 +2062,19 @@ int32_t lsm6dsv_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm6dsv_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_pin_int2_route_get(const stmdev_ctx_t *ctx, lsm6dsv_pin_int_route_t *val) { lsm6dsv_int2_ctrl_t int2_ctrl; + lsm6dsv_ctrl4_t ctrl4; lsm6dsv_md2_cfg_t md2_cfg; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->drdy_xl = int2_ctrl.int2_drdy_xl; val->drdy_g = int2_ctrl.int2_drdy_g; @@ -1941,8 +2085,19 @@ int32_t lsm6dsv_pin_int2_route_get(stmdev_ctx_t *ctx, val->drdy_g_eis = int2_ctrl.int2_drdy_g_eis; val->emb_func_endop = int2_ctrl.int2_emb_func_endop; + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret != 0) + { + return ret; + } + + val->drdy_temp = ctrl4.int2_drdy_temp; + ret = lsm6dsv_read_reg(ctx, LSM6DSV_MD2_CFG, (uint8_t *)&md2_cfg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->timestamp = md2_cfg.int2_timestamp; val->emb_func = md2_cfg.int2_emb_func; @@ -1969,7 +2124,8 @@ int32_t lsm6dsv_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_all_sources_get(stmdev_ctx_t *ctx, lsm6dsv_all_sources_t *val) +int32_t lsm6dsv_all_sources_get(const stmdev_ctx_t *ctx, + lsm6dsv_all_sources_t *val) { lsm6dsv_emb_func_status_mainpage_t emb_func_status_mainpage; lsm6dsv_emb_func_exec_status_t emb_func_exec_status; @@ -1984,16 +2140,22 @@ int32_t lsm6dsv_all_sources_get(stmdev_ctx_t *ctx, lsm6dsv_all_sources_t *val) lsm6dsv_tap_src_t tap_src; lsm6dsv_ui_status_reg_ois_t status_reg_ois; lsm6dsv_status_master_t status_shub; - uint8_t buff[7]; + uint8_t buff[8]; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); functions_enable.dis_rst_lir_all_int = PROPERTY_ENABLE; ret += lsm6dsv_write_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_STATUS1, (uint8_t *)&buff, 4); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } bytecpy((uint8_t *)&fifo_status2, &buff[1]); bytecpy((uint8_t *)&all_int_src, &buff[2]); @@ -2018,17 +2180,23 @@ int32_t lsm6dsv_all_sources_get(stmdev_ctx_t *ctx, lsm6dsv_all_sources_t *val) ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); functions_enable.dis_rst_lir_all_int = PROPERTY_DISABLE; ret += lsm6dsv_write_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_STATUS_REG_OIS, (uint8_t *)&buff, 8); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } bytecpy((uint8_t *)&status_reg_ois, &buff[0]); bytecpy((uint8_t *)&wake_up_src, &buff[1]); bytecpy((uint8_t *)&tap_src, &buff[2]); bytecpy((uint8_t *)&d6d_src, &buff[3]); - bytecpy((uint8_t *)&emb_func_status_mainpage, &buff[4]); - bytecpy((uint8_t *)&fsm_status_mainpage, &buff[5]); + bytecpy((uint8_t *)&emb_func_status_mainpage, &buff[5]); + bytecpy((uint8_t *)&fsm_status_mainpage, &buff[6]); val->gy_settling = status_reg_ois.gyro_settling; val->sleep_change = wake_up_src.sleep_change_ia; @@ -2065,14 +2233,15 @@ int32_t lsm6dsv_all_sources_get(stmdev_ctx_t *ctx, lsm6dsv_all_sources_t *val) val->fsm7 = fsm_status_mainpage.is_fsm7; val->fsm8 = fsm_status_mainpage.is_fsm8; - - /* embedded func */ ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); ret += lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, 1); ret += lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->emb_func_stand_by = emb_func_exec_status.emb_func_endop; val->emb_func_time_exceed = emb_func_exec_status.emb_func_exec_ovr; @@ -2084,7 +2253,10 @@ int32_t lsm6dsv_all_sources_get(stmdev_ctx_t *ctx, lsm6dsv_all_sources_t *val) /* sensor hub */ ret = lsm6dsv_read_reg(ctx, LSM6DSV_STATUS_MASTER_MAINPAGE, (uint8_t *)&status_shub, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->sh_endop = status_shub.sens_hub_endop; val->sh_wr_once = status_shub.wr_once_done; @@ -2096,14 +2268,17 @@ int32_t lsm6dsv_all_sources_get(stmdev_ctx_t *ctx, lsm6dsv_all_sources_t *val) return ret; } -int32_t lsm6dsv_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_flag_data_ready_get(const stmdev_ctx_t *ctx, lsm6dsv_data_ready_t *val) { lsm6dsv_status_reg_t status; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_STATUS_REG, (uint8_t *)&status, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->drdy_xl = status.xlda; val->drdy_gy = status.gda; @@ -2120,7 +2295,7 @@ int32_t lsm6dsv_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_int_ack_mask_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_int_ack_mask_set(const stmdev_ctx_t *ctx, uint8_t val) { int32_t ret; @@ -2137,7 +2312,7 @@ int32_t lsm6dsv_int_ack_mask_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_int_ack_mask_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_int_ack_mask_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -2154,13 +2329,16 @@ int32_t lsm6dsv_int_ack_mask_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsv_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_OUT_TEMP_L, &buff[0], 2); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } *val = (int16_t)buff[1]; *val = (*val * 256) + (int16_t)buff[0]; @@ -2176,13 +2354,16 @@ int32_t lsm6dsv_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsv_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_OUTX_L_G, &buff[0], 6); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; @@ -2202,13 +2383,16 @@ int32_t lsm6dsv_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ois_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsv_ois_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_SPI2_OUTX_L_G_OIS, &buff[0], 6); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val[0] = (int16_t)buff[1]; val[0] = (*val * 256) + (int16_t)buff[0]; @@ -2228,13 +2412,16 @@ int32_t lsm6dsv_ois_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ois_eis_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsv_ois_eis_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_OUTX_L_G_OIS_EIS, &buff[0], 6); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val[0] = (int16_t)buff[1]; val[0] = (*val * 256) + (int16_t)buff[0]; @@ -2254,13 +2441,16 @@ int32_t lsm6dsv_ois_eis_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsv_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_OUTX_L_A, &buff[0], 6); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; @@ -2280,13 +2470,16 @@ int32_t lsm6dsv_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_dual_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm6dsv_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_OUTX_L_A_OIS_DUALC, &buff[0], 6); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val[0] = (int16_t)buff[1]; val[0] = (val[0] * 256) + (int16_t)buff[0]; @@ -2306,7 +2499,7 @@ int32_t lsm6dsv_dual_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_odr_cal_reg_get(stmdev_ctx_t *ctx, int8_t *val) +int32_t lsm6dsv_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val) { lsm6dsv_internal_freq_t internal_freq; int32_t ret; @@ -2325,7 +2518,7 @@ int32_t lsm6dsv_odr_cal_reg_get(stmdev_ctx_t *ctx, int8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dsv_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len) { lsm6dsv_page_address_t page_address; @@ -2340,32 +2533,47 @@ int32_t lsm6dsv_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, lsb = (uint8_t)address & 0xFFU; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } /* set page write */ ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1); page_rw.page_read = PROPERTY_DISABLE; page_rw.page_write = PROPERTY_ENABLE; ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } /* select page */ ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1); page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } /* set page addr */ page_address.page_addr = lsb; ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_ADDRESS, (uint8_t *)&page_address, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } for (i = 0; ((i < len) && (ret == 0)); i++) { ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_VALUE, &buf[i], 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } lsb++; @@ -2374,19 +2582,28 @@ int32_t lsm6dsv_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, { msb++; ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } } } page_sel.page_sel = 0; page_sel.not_used0 = 1;// Default value ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } /* unset page write */ ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1); @@ -2415,7 +2632,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, +int32_t lsm6dsv_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len) { lsm6dsv_page_address_t page_address; @@ -2430,32 +2647,47 @@ int32_t lsm6dsv_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, lsb = (uint8_t)address & 0xFFU; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } /* set page write */ ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1); page_rw.page_read = PROPERTY_ENABLE; page_rw.page_write = PROPERTY_DISABLE; ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } /* select page */ ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1); page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } /* set page addr */ page_address.page_addr = lsb; ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_ADDRESS, (uint8_t *)&page_address, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } for (i = 0; ((i < len) && (ret == 0)); i++) { ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_VALUE, &buf[i], 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } lsb++; @@ -2464,19 +2696,28 @@ int32_t lsm6dsv_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, { msb++; ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } page_sel.page_sel = msb; page_sel.not_used0 = 1; // Default value ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } } } page_sel.page_sel = 0; page_sel.not_used0 = 1;// Default value ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } /* unset page write */ ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1); @@ -2498,7 +2739,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_emb_function_dbg_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_emb_function_dbg_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_ctrl10_t ctrl10; int32_t ret; @@ -2522,13 +2763,16 @@ int32_t lsm6dsv_emb_function_dbg_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_emb_function_dbg_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_emb_function_dbg_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_ctrl10_t ctrl10; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL10, (uint8_t *)&ctrl10, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } *val = ctrl10.emb_func_debug; @@ -2556,7 +2800,8 @@ int32_t lsm6dsv_emb_function_dbg_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_den_polarity_set(stmdev_ctx_t *ctx, lsm6dsv_den_polarity_t val) +int32_t lsm6dsv_den_polarity_set(const stmdev_ctx_t *ctx, + lsm6dsv_den_polarity_t val) { lsm6dsv_ctrl4_t ctrl4; int32_t ret; @@ -2580,13 +2825,17 @@ int32_t lsm6dsv_den_polarity_set(stmdev_ctx_t *ctx, lsm6dsv_den_polarity_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_den_polarity_get(stmdev_ctx_t *ctx, lsm6dsv_den_polarity_t *val) +int32_t lsm6dsv_den_polarity_get(const stmdev_ctx_t *ctx, + lsm6dsv_den_polarity_t *val) { lsm6dsv_ctrl4_t ctrl4; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl4.int2_in_lh) { @@ -2614,13 +2863,16 @@ int32_t lsm6dsv_den_polarity_get(stmdev_ctx_t *ctx, lsm6dsv_den_polarity_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_den_conf_set(stmdev_ctx_t *ctx, lsm6dsv_den_conf_t val) +int32_t lsm6dsv_den_conf_set(const stmdev_ctx_t *ctx, lsm6dsv_den_conf_t val) { lsm6dsv_den_t den; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_DEN, (uint8_t *)&den, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } den.den_z = val.den_z; den.den_y = val.den_y; @@ -2669,19 +2921,22 @@ int32_t lsm6dsv_den_conf_set(stmdev_ctx_t *ctx, lsm6dsv_den_conf_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_den_conf_get(stmdev_ctx_t *ctx, lsm6dsv_den_conf_t *val) +int32_t lsm6dsv_den_conf_get(const stmdev_ctx_t *ctx, lsm6dsv_den_conf_t *val) { lsm6dsv_den_t den; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_DEN, (uint8_t *)&den, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->den_z = den.den_z; val->den_y = den.den_y; val->den_x = den.den_x; - if ((den.den_z | den.den_z | den.den_z) == PROPERTY_ENABLE) + if ((den.den_x | den.den_y | den.den_z) == PROPERTY_ENABLE) { if (den.den_xl_g == PROPERTY_DISABLE && den.den_xl_en == PROPERTY_ENABLE) { @@ -2743,7 +2998,7 @@ int32_t lsm6dsv_den_conf_get(stmdev_ctx_t *ctx, lsm6dsv_den_conf_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_eis_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_eis_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsv_eis_gy_full_scale_t val) { lsm6dsv_ctrl_eis_t ctrl_eis; @@ -2768,14 +3023,17 @@ int32_t lsm6dsv_eis_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_eis_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_eis_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsv_eis_gy_full_scale_t *val) { lsm6dsv_ctrl_eis_t ctrl_eis; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl_eis.fs_g_eis) { @@ -2814,7 +3072,7 @@ int32_t lsm6dsv_eis_gy_full_scale_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_eis_gy_on_spi2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_eis_gy_on_spi2_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_ctrl_eis_t ctrl_eis; int32_t ret; @@ -2838,7 +3096,7 @@ int32_t lsm6dsv_eis_gy_on_spi2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_eis_gy_on_spi2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_eis_gy_on_spi2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_ctrl_eis_t ctrl_eis; int32_t ret; @@ -2857,7 +3115,7 @@ int32_t lsm6dsv_eis_gy_on_spi2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_gy_eis_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_gy_eis_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv_gy_eis_data_rate_t val) { lsm6dsv_ctrl_eis_t ctrl_eis; @@ -2882,14 +3140,17 @@ int32_t lsm6dsv_gy_eis_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_gy_eis_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_gy_eis_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv_gy_eis_data_rate_t *val) { lsm6dsv_ctrl_eis_t ctrl_eis; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl_eis.odr_g_eis) { @@ -2933,7 +3194,7 @@ int32_t lsm6dsv_gy_eis_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_fifo_ctrl1_t fifo_ctrl1; int32_t ret; @@ -2957,7 +3218,7 @@ int32_t lsm6dsv_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_fifo_ctrl1_t fifo_ctrl1; int32_t ret; @@ -2976,7 +3237,7 @@ int32_t lsm6dsv_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_xl_dual_fsm_batch_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -2999,7 +3260,7 @@ int32_t lsm6dsv_fifo_xl_dual_fsm_batch_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_xl_dual_fsm_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -3018,7 +3279,7 @@ int32_t lsm6dsv_fifo_xl_dual_fsm_batch_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_compress_algo_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_compress_algo_set(const stmdev_ctx_t *ctx, lsm6dsv_fifo_compress_algo_t val) { lsm6dsv_fifo_ctrl2_t fifo_ctrl2; @@ -3042,14 +3303,17 @@ int32_t lsm6dsv_fifo_compress_algo_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_compress_algo_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_compress_algo_get(const stmdev_ctx_t *ctx, lsm6dsv_fifo_compress_algo_t *val) { lsm6dsv_fifo_ctrl2_t fifo_ctrl2; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (fifo_ctrl2.uncompr_rate) { @@ -3084,7 +3348,7 @@ int32_t lsm6dsv_fifo_compress_algo_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -3107,7 +3371,8 @@ int32_t lsm6dsv_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, + uint8_t *val) { lsm6dsv_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -3126,7 +3391,8 @@ int32_t lsm6dsv_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_compress_algo_real_time_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, + uint8_t val) { lsm6dsv_emb_func_en_b_t emb_func_en_b; lsm6dsv_fifo_ctrl2_t fifo_ctrl2; @@ -3136,10 +3402,16 @@ int32_t lsm6dsv_fifo_compress_algo_real_time_set(stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); fifo_ctrl2.fifo_compr_rt_en = val; ret += lsm6dsv_write_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); emb_func_en_b.fifo_compr_en = val; @@ -3157,7 +3429,7 @@ int32_t lsm6dsv_fifo_compress_algo_real_time_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_compress_algo_real_time_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_fifo_ctrl2_t fifo_ctrl2; @@ -3178,7 +3450,7 @@ int32_t lsm6dsv_fifo_compress_algo_real_time_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -3201,7 +3473,7 @@ int32_t lsm6dsv_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_fifo_ctrl2_t fifo_ctrl2; int32_t ret; @@ -3220,7 +3492,7 @@ int32_t lsm6dsv_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_xl_batch_set(const stmdev_ctx_t *ctx, lsm6dsv_fifo_xl_batch_t val) { lsm6dsv_fifo_ctrl3_t fifo_ctrl3; @@ -3244,14 +3516,17 @@ int32_t lsm6dsv_fifo_xl_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_xl_batch_get(const stmdev_ctx_t *ctx, lsm6dsv_fifo_xl_batch_t *val) { lsm6dsv_fifo_ctrl3_t fifo_ctrl3; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (fifo_ctrl3.bdr_xl) { @@ -3323,7 +3598,7 @@ int32_t lsm6dsv_fifo_xl_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_gy_batch_set(const stmdev_ctx_t *ctx, lsm6dsv_fifo_gy_batch_t val) { lsm6dsv_fifo_ctrl3_t fifo_ctrl3; @@ -3347,14 +3622,17 @@ int32_t lsm6dsv_fifo_gy_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_gy_batch_get(const stmdev_ctx_t *ctx, lsm6dsv_fifo_gy_batch_t *val) { lsm6dsv_fifo_ctrl3_t fifo_ctrl3; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (fifo_ctrl3.bdr_gy) { @@ -3426,7 +3704,7 @@ int32_t lsm6dsv_fifo_gy_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_mode_set(stmdev_ctx_t *ctx, lsm6dsv_fifo_mode_t val) +int32_t lsm6dsv_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_fifo_mode_t val) { lsm6dsv_fifo_ctrl4_t fifo_ctrl4; int32_t ret; @@ -3449,13 +3727,16 @@ int32_t lsm6dsv_fifo_mode_set(stmdev_ctx_t *ctx, lsm6dsv_fifo_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_mode_get(stmdev_ctx_t *ctx, lsm6dsv_fifo_mode_t *val) +int32_t lsm6dsv_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_fifo_mode_t *val) { lsm6dsv_fifo_ctrl4_t fifo_ctrl4; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (fifo_ctrl4.fifo_mode) { @@ -3502,7 +3783,7 @@ int32_t lsm6dsv_fifo_mode_get(stmdev_ctx_t *ctx, lsm6dsv_fifo_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_gy_eis_batch_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_fifo_gy_eis_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_fifo_ctrl4_t fifo_ctrl4; int32_t ret; @@ -3525,7 +3806,7 @@ int32_t lsm6dsv_fifo_gy_eis_batch_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_gy_eis_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_fifo_gy_eis_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_fifo_ctrl4_t fifo_ctrl4; int32_t ret; @@ -3544,7 +3825,7 @@ int32_t lsm6dsv_fifo_gy_eis_batch_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_temp_batch_set(const stmdev_ctx_t *ctx, lsm6dsv_fifo_temp_batch_t val) { lsm6dsv_fifo_ctrl4_t fifo_ctrl4; @@ -3568,14 +3849,17 @@ int32_t lsm6dsv_fifo_temp_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_temp_batch_get(const stmdev_ctx_t *ctx, lsm6dsv_fifo_temp_batch_t *val) { lsm6dsv_fifo_ctrl4_t fifo_ctrl4; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (fifo_ctrl4.odr_t_batch) { @@ -3610,7 +3894,7 @@ int32_t lsm6dsv_fifo_temp_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_timestamp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx, lsm6dsv_fifo_timestamp_batch_t val) { lsm6dsv_fifo_ctrl4_t fifo_ctrl4; @@ -3634,14 +3918,17 @@ int32_t lsm6dsv_fifo_timestamp_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_timestamp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, lsm6dsv_fifo_timestamp_batch_t *val) { lsm6dsv_fifo_ctrl4_t fifo_ctrl4; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (fifo_ctrl4.dec_ts_batch) { @@ -3677,15 +3964,22 @@ int32_t lsm6dsv_fifo_timestamp_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_batch_counter_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { - uint8_t buff[2]; + lsm6dsv_counter_bdr_reg1_t counter_bdr_reg1; + lsm6dsv_counter_bdr_reg2_t counter_bdr_reg2; int32_t ret; - buff[1] = (uint8_t)(val / 256U); - buff[0] = (uint8_t)(val - (buff[1] * 256U)); - ret = lsm6dsv_write_reg(ctx, LSM6DSV_COUNTER_BDR_REG1, (uint8_t *)&buff[0], 2); + ret = lsm6dsv_read_reg(ctx, LSM6DSV_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + + if (ret == 0) + { + counter_bdr_reg2.cnt_bdr_th = (uint8_t)val & 0xFFU; + counter_bdr_reg1.cnt_bdr_th = (uint8_t)(val >> 8) & 0x3U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + ret += lsm6dsv_write_reg(ctx, LSM6DSV_COUNTER_BDR_REG2, (uint8_t *)&counter_bdr_reg2, 1); + } return ret; } @@ -3698,17 +3992,20 @@ int32_t lsm6dsv_fifo_batch_counter_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_COUNTER_BDR_REG1, &buff[0], 2); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } - *val = buff[1]; - *val = (*val * 256U) + buff[0]; + *val = (uint16_t)buff[0] & 0x3U; + *val = (*val * 256U) + (uint16_t)buff[1]; return ret; } @@ -3721,7 +4018,7 @@ int32_t lsm6dsv_fifo_batch_counter_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_batch_cnt_event_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_batch_cnt_event_set(const stmdev_ctx_t *ctx, lsm6dsv_fifo_batch_cnt_event_t val) { lsm6dsv_counter_bdr_reg1_t counter_bdr_reg1; @@ -3745,14 +4042,17 @@ int32_t lsm6dsv_fifo_batch_cnt_event_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_batch_cnt_event_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx, lsm6dsv_fifo_batch_cnt_event_t *val) { lsm6dsv_counter_bdr_reg1_t counter_bdr_reg1; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (counter_bdr_reg1.trig_counter_bdr) { @@ -3776,7 +4076,7 @@ int32_t lsm6dsv_fifo_batch_cnt_event_get(stmdev_ctx_t *ctx, return ret; } -int32_t lsm6dsv_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_status_get(const stmdev_ctx_t *ctx, lsm6dsv_fifo_status_t *val) { uint8_t buff[2]; @@ -3784,7 +4084,10 @@ int32_t lsm6dsv_fifo_status_get(stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_STATUS1, (uint8_t *)&buff[0], 2); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } bytecpy((uint8_t *)&status, &buff[1]); @@ -3804,18 +4107,11 @@ int32_t lsm6dsv_fifo_status_get(stmdev_ctx_t *ctx, * @brief FIFO data output[get] * * @param ctx read / write interface definitions - * @param val FIFO_EMPTY, GY_NC_TAG, XL_NC_TAG, TIMESTAMP_TAG, - TEMPERATURE_TAG, CFG_CHANGE_TAG, XL_NC_T_2_TAG, - XL_NC_T_1_TAG, XL_2XC_TAG, XL_3XC_TAG, GY_NC_T_2_TAG, - GY_NC_T_1_TAG, GY_2XC_TAG, GY_3XC_TAG, SENSORHUB_SLAVE0_TAG, - SENSORHUB_SLAVE1_TAG, SENSORHUB_SLAVE2_TAG, SENSORHUB_SLAVE3_TAG, - STEP_COUNTER_TAG, SFLP_GAME_ROTATION_VECTOR_TAG, SFLP_GYROSCOPE_BIAS_TAG, - SFLP_GRAVITY_VECTOR_TAG, SENSORHUB_NACK_TAG, XL_DUAL_CORE, - GY_ENHANCED_EIS, + * @param val lsm6dsv_fifo_out_raw_t * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_out_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_out_raw_get(const stmdev_ctx_t *ctx, lsm6dsv_fifo_out_raw_t *val) { lsm6dsv_fifo_data_out_tag_t fifo_data_out_tag; @@ -3823,7 +4119,10 @@ int32_t lsm6dsv_fifo_out_raw_get(stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_DATA_OUT_TAG, buff, 7); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } bytecpy((uint8_t *)&fifo_data_out_tag, &buff[0]); @@ -3954,13 +4253,16 @@ int32_t lsm6dsv_fifo_out_raw_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_stpcnt_batch_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_emb_func_fifo_en_a_t emb_func_fifo_en_a; int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); emb_func_fifo_en_a.step_counter_fifo_en = val; @@ -3979,13 +4281,16 @@ int32_t lsm6dsv_fifo_stpcnt_batch_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_stpcnt_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_emb_func_fifo_en_a_t emb_func_fifo_en_a; int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret += lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); *val = emb_func_fifo_en_a.step_counter_fifo_en; @@ -4003,17 +4308,20 @@ int32_t lsm6dsv_fifo_stpcnt_batch_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_sh_batch_slave_set(stmdev_ctx_t *ctx, uint8_t idx, uint8_t val) +int32_t lsm6dsv_fifo_sh_batch_slave_set(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t val) { lsm6dsv_slv0_config_t slv_config; int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } - ret = lsm6dsv_read_reg(ctx, LSM6DSV_SLV0_CONFIG + idx*3U, (uint8_t *)&slv_config, 1); + ret = lsm6dsv_read_reg(ctx, LSM6DSV_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1); slv_config.batch_ext_sens_0_en = val; - ret += lsm6dsv_write_reg(ctx, LSM6DSV_SLV0_CONFIG + idx*3U, (uint8_t *)&slv_config, 1); + ret += lsm6dsv_write_reg(ctx, LSM6DSV_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1); ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); @@ -4028,15 +4336,18 @@ int32_t lsm6dsv_fifo_sh_batch_slave_set(stmdev_ctx_t *ctx, uint8_t idx, uint8_t * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_sh_batch_slave_get(stmdev_ctx_t *ctx, uint8_t idx, uint8_t *val) +int32_t lsm6dsv_fifo_sh_batch_slave_get(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t *val) { lsm6dsv_slv0_config_t slv_config; int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } - ret = lsm6dsv_read_reg(ctx, LSM6DSV_SLV0_CONFIG + idx*3U, (uint8_t *)&slv_config, 1); + ret = lsm6dsv_read_reg(ctx, LSM6DSV_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1); *val = slv_config.batch_ext_sens_0_en; ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); @@ -4052,8 +4363,8 @@ int32_t lsm6dsv_fifo_sh_batch_slave_get(stmdev_ctx_t *ctx, uint8_t idx, uint8_t * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_sflp_batch_set(stmdev_ctx_t *ctx, - lsm6dsv_fifo_sflp_raw_t val) +int32_t lsm6dsv_fifo_sflp_batch_set(const stmdev_ctx_t *ctx, + lsm6dsv_fifo_sflp_raw_t val) { lsm6dsv_emb_func_fifo_en_a_t emb_func_fifo_en_a; int32_t ret; @@ -4066,7 +4377,7 @@ int32_t lsm6dsv_fifo_sflp_batch_set(stmdev_ctx_t *ctx, emb_func_fifo_en_a.sflp_gravity_fifo_en = val.gravity; emb_func_fifo_en_a.sflp_gbias_fifo_en = val.gbias; ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_FIFO_EN_A, - (uint8_t *)&emb_func_fifo_en_a, 1); + (uint8_t *)&emb_func_fifo_en_a, 1); } ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); @@ -4082,8 +4393,8 @@ int32_t lsm6dsv_fifo_sflp_batch_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fifo_sflp_batch_get(stmdev_ctx_t *ctx, - lsm6dsv_fifo_sflp_raw_t *val) +int32_t lsm6dsv_fifo_sflp_batch_get(const stmdev_ctx_t *ctx, + lsm6dsv_fifo_sflp_raw_t *val) { lsm6dsv_emb_func_fifo_en_a_t emb_func_fifo_en_a; int32_t ret; @@ -4124,7 +4435,7 @@ int32_t lsm6dsv_fifo_sflp_batch_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_anti_spike_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_anti_spike_set(const stmdev_ctx_t *ctx, lsm6dsv_filt_anti_spike_t val) { lsm6dsv_if_cfg_t if_cfg; @@ -4149,14 +4460,17 @@ int32_t lsm6dsv_filt_anti_spike_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_anti_spike_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_anti_spike_get(const stmdev_ctx_t *ctx, lsm6dsv_filt_anti_spike_t *val) { lsm6dsv_if_cfg_t if_cfg; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (if_cfg.asf_ctrl) { @@ -4184,7 +4498,7 @@ int32_t lsm6dsv_filt_anti_spike_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_settling_mask_set(const stmdev_ctx_t *ctx, lsm6dsv_filt_settling_mask_t val) { lsm6dsv_emb_func_cfg_t emb_func_cfg; @@ -4195,13 +4509,19 @@ int32_t lsm6dsv_filt_settling_mask_set(stmdev_ctx_t *ctx, ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1); ctrl4.drdy_mask = val.drdy; ret += lsm6dsv_write_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); emb_func_cfg.emb_func_irq_mask_xl_settl = val.irq_xl; emb_func_cfg.emb_func_irq_mask_g_settl = val.irq_g; ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1); ui_int_ois.drdy_mask_ois = val.ois_drdy; @@ -4218,7 +4538,7 @@ int32_t lsm6dsv_filt_settling_mask_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_settling_mask_get(const stmdev_ctx_t *ctx, lsm6dsv_filt_settling_mask_t *val) { lsm6dsv_emb_func_cfg_t emb_func_cfg; @@ -4245,7 +4565,7 @@ int32_t lsm6dsv_filt_settling_mask_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_ois_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_ois_settling_mask_set(const stmdev_ctx_t *ctx, lsm6dsv_filt_ois_settling_mask_t val) { lsm6dsv_spi2_int_ois_t spi2_int_ois; @@ -4270,7 +4590,7 @@ int32_t lsm6dsv_filt_ois_settling_mask_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_ois_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_ois_settling_mask_get(const stmdev_ctx_t *ctx, lsm6dsv_filt_ois_settling_mask_t *val) { @@ -4291,7 +4611,7 @@ int32_t lsm6dsv_filt_ois_settling_mask_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsv_filt_gy_lp1_bandwidth_t val) { lsm6dsv_ctrl6_t ctrl6; @@ -4315,14 +4635,17 @@ int32_t lsm6dsv_filt_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsv_filt_gy_lp1_bandwidth_t *val) { lsm6dsv_ctrl6_t ctrl6; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL6, (uint8_t *)&ctrl6, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl6.lpf1_g_bw) { @@ -4374,7 +4697,7 @@ int32_t lsm6dsv_filt_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_gy_lp1_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_filt_gy_lp1_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_ctrl7_t ctrl7; int32_t ret; @@ -4398,7 +4721,7 @@ int32_t lsm6dsv_filt_gy_lp1_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_gy_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_ctrl7_t ctrl7; int32_t ret; @@ -4417,7 +4740,7 @@ int32_t lsm6dsv_filt_gy_lp1_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsv_filt_xl_lp2_bandwidth_t val) { lsm6dsv_ctrl8_t ctrl8; @@ -4441,14 +4764,17 @@ int32_t lsm6dsv_filt_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsv_filt_xl_lp2_bandwidth_t *val) { lsm6dsv_ctrl8_t ctrl8; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL8, (uint8_t *)&ctrl8, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl8.hp_lpf2_xl_bw) { @@ -4500,7 +4826,7 @@ int32_t lsm6dsv_filt_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_xl_lp2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_filt_xl_lp2_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_ctrl9_t ctrl9; int32_t ret; @@ -4523,7 +4849,7 @@ int32_t lsm6dsv_filt_xl_lp2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_xl_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_ctrl9_t ctrl9; int32_t ret; @@ -4542,7 +4868,7 @@ int32_t lsm6dsv_filt_xl_lp2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_xl_hp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_filt_xl_hp_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_ctrl9_t ctrl9; int32_t ret; @@ -4565,7 +4891,7 @@ int32_t lsm6dsv_filt_xl_hp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_xl_hp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_ctrl9_t ctrl9; int32_t ret; @@ -4584,7 +4910,7 @@ int32_t lsm6dsv_filt_xl_hp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_filt_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_ctrl9_t ctrl9; int32_t ret; @@ -4607,7 +4933,7 @@ int32_t lsm6dsv_filt_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_ctrl9_t ctrl9; int32_t ret; @@ -4626,7 +4952,7 @@ int32_t lsm6dsv_filt_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_xl_hp_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_xl_hp_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_filt_xl_hp_mode_t val) { lsm6dsv_ctrl9_t ctrl9; @@ -4650,14 +4976,17 @@ int32_t lsm6dsv_filt_xl_hp_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_xl_hp_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_filt_xl_hp_mode_t *val) { lsm6dsv_ctrl9_t ctrl9; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl9.hp_ref_mode_xl) { @@ -4685,7 +5014,7 @@ int32_t lsm6dsv_filt_xl_hp_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_wkup_act_feed_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx, lsm6dsv_filt_wkup_act_feed_t val) { lsm6dsv_wake_up_ths_t wake_up_ths; @@ -4694,11 +5023,17 @@ int32_t lsm6dsv_filt_wkup_act_feed_set(stmdev_ctx_t *ctx, ret = lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); ret += lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } tap_cfg0.slope_fds = (uint8_t)val & 0x01U; ret = lsm6dsv_write_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } wake_up_ths.usr_off_on_wu = ((uint8_t)val & 0x02U) >> 1; ret = lsm6dsv_write_reg(ctx, LSM6DSV_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); @@ -4714,7 +5049,7 @@ int32_t lsm6dsv_filt_wkup_act_feed_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_wkup_act_feed_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx, lsm6dsv_filt_wkup_act_feed_t *val) { lsm6dsv_wake_up_ths_t wake_up_ths; @@ -4723,7 +5058,10 @@ int32_t lsm6dsv_filt_wkup_act_feed_get(stmdev_ctx_t *ctx, ret = lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); ret += lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch ((wake_up_ths.usr_off_on_wu << 1) + tap_cfg0.slope_fds) { @@ -4755,7 +5093,7 @@ int32_t lsm6dsv_filt_wkup_act_feed_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_mask_trigger_xl_settl_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_mask_trigger_xl_settl_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_tap_cfg0_t tap_cfg0; int32_t ret; @@ -4779,7 +5117,7 @@ int32_t lsm6dsv_mask_trigger_xl_settl_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_mask_trigger_xl_settl_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_tap_cfg0_t tap_cfg0; int32_t ret; @@ -4798,7 +5136,7 @@ int32_t lsm6dsv_mask_trigger_xl_settl_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_sixd_feed_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_sixd_feed_set(const stmdev_ctx_t *ctx, lsm6dsv_filt_sixd_feed_t val) { lsm6dsv_tap_cfg0_t tap_cfg0; @@ -4823,14 +5161,17 @@ int32_t lsm6dsv_filt_sixd_feed_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_sixd_feed_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_sixd_feed_get(const stmdev_ctx_t *ctx, lsm6dsv_filt_sixd_feed_t *val) { lsm6dsv_tap_cfg0_t tap_cfg0; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (tap_cfg0.low_pass_on_6d) { @@ -4858,7 +5199,7 @@ int32_t lsm6dsv_filt_sixd_feed_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_gy_eis_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_gy_eis_lp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsv_filt_gy_eis_lp_bandwidth_t val) { lsm6dsv_ctrl_eis_t ctrl_eis; @@ -4883,14 +5224,17 @@ int32_t lsm6dsv_filt_gy_eis_lp_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_gy_eis_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_gy_eis_lp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsv_filt_gy_eis_lp_bandwidth_t *val) { lsm6dsv_ctrl_eis_t ctrl_eis; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl_eis.lpf_g_eis_bw) { @@ -4918,7 +5262,7 @@ int32_t lsm6dsv_filt_gy_eis_lp_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_gy_ois_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_gy_ois_lp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsv_filt_gy_ois_lp_bandwidth_t val) { lsm6dsv_ui_ctrl2_ois_t ui_ctrl2_ois; @@ -4943,7 +5287,7 @@ int32_t lsm6dsv_filt_gy_ois_lp_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_gy_ois_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_gy_ois_lp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsv_filt_gy_ois_lp_bandwidth_t *val) { @@ -4951,7 +5295,10 @@ int32_t lsm6dsv_filt_gy_ois_lp_bandwidth_get(stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ui_ctrl2_ois.lpf1_g_ois_bw) { @@ -4987,7 +5334,7 @@ int32_t lsm6dsv_filt_gy_ois_lp_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_xl_ois_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_xl_ois_lp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsv_filt_xl_ois_lp_bandwidth_t val) { lsm6dsv_ui_ctrl3_ois_t ui_ctrl3_ois; @@ -5012,14 +5359,17 @@ int32_t lsm6dsv_filt_xl_ois_lp_bandwidth_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_filt_xl_ois_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_xl_ois_lp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsv_filt_xl_ois_lp_bandwidth_t *val) { lsm6dsv_ui_ctrl3_ois_t ui_ctrl3_ois; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ui_ctrl3_ois.lpf_xl_ois_bw) { @@ -5084,7 +5434,7 @@ int32_t lsm6dsv_filt_xl_ois_lp_bandwidth_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_permission_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_permission_set(const stmdev_ctx_t *ctx, lsm6dsv_fsm_permission_t val) { lsm6dsv_func_cfg_access_t func_cfg_access; @@ -5109,14 +5459,17 @@ int32_t lsm6dsv_fsm_permission_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_permission_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_permission_get(const stmdev_ctx_t *ctx, lsm6dsv_fsm_permission_t *val) { lsm6dsv_func_cfg_access_t func_cfg_access; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (func_cfg_access.fsm_wr_ctrl_en) { @@ -5144,7 +5497,7 @@ int32_t lsm6dsv_fsm_permission_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_permission_status(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_fsm_permission_status(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_ctrl_status_t ctrl_status; int32_t ret; @@ -5164,21 +5517,27 @@ int32_t lsm6dsv_fsm_permission_status(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_mode_set(stmdev_ctx_t *ctx, lsm6dsv_fsm_mode_t val) +int32_t lsm6dsv_fsm_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_fsm_mode_t val) { lsm6dsv_emb_func_en_b_t emb_func_en_b; lsm6dsv_fsm_enable_t fsm_enable; int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); ret += lsm6dsv_read_reg(ctx, LSM6DSV_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } - if ((val.fsm1_en | val.fsm2_en | val.fsm1_en | val.fsm1_en - | val.fsm1_en | val.fsm2_en | val.fsm1_en | val.fsm1_en) == PROPERTY_ENABLE) + if ((val.fsm1_en | val.fsm2_en | val.fsm3_en | val.fsm4_en + | val.fsm5_en | val.fsm6_en | val.fsm7_en | val.fsm8_en) == PROPERTY_ENABLE) { emb_func_en_b.fsm_en = PROPERTY_ENABLE; } @@ -5213,7 +5572,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_mode_get(stmdev_ctx_t *ctx, lsm6dsv_fsm_mode_t *val) +int32_t lsm6dsv_fsm_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_fsm_mode_t *val) { lsm6dsv_fsm_enable_t fsm_enable; int32_t ret; @@ -5221,7 +5580,10 @@ int32_t lsm6dsv_fsm_mode_get(stmdev_ctx_t *ctx, lsm6dsv_fsm_mode_t *val) ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); ret += lsm6dsv_read_reg(ctx, LSM6DSV_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->fsm1_en = fsm_enable.fsm1_en; val->fsm2_en = fsm_enable.fsm2_en; @@ -5243,7 +5605,7 @@ int32_t lsm6dsv_fsm_mode_get(stmdev_ctx_t *ctx, lsm6dsv_fsm_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsv_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -5266,7 +5628,7 @@ int32_t lsm6dsv_fsm_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsv_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -5274,7 +5636,10 @@ int32_t lsm6dsv_fsm_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); ret += lsm6dsv_read_reg(ctx, LSM6DSV_FSM_LONG_COUNTER_L, &buff[0], 2); ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -5290,7 +5655,7 @@ int32_t lsm6dsv_fsm_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsv_fsm_out_t *val) +int32_t lsm6dsv_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dsv_fsm_out_t *val) { int32_t ret; @@ -5309,7 +5674,7 @@ int32_t lsm6dsv_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsv_fsm_out_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv_fsm_data_rate_t val) { lsm6dsv_fsm_odr_t fsm_odr; @@ -5317,7 +5682,10 @@ int32_t lsm6dsv_fsm_data_rate_set(stmdev_ctx_t *ctx, ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); ret += lsm6dsv_read_reg(ctx, LSM6DSV_FSM_ODR, (uint8_t *)&fsm_odr, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } fsm_odr.fsm_odr = (uint8_t)val & 0x07U; ret = lsm6dsv_write_reg(ctx, LSM6DSV_FSM_ODR, (uint8_t *)&fsm_odr, 1); @@ -5336,7 +5704,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv_fsm_data_rate_t *val) { lsm6dsv_fsm_odr_t fsm_odr; @@ -5345,7 +5713,10 @@ int32_t lsm6dsv_fsm_data_rate_get(stmdev_ctx_t *ctx, ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); ret += lsm6dsv_read_reg(ctx, LSM6DSV_FSM_ODR, (uint8_t *)&fsm_odr, 1); ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (fsm_odr.fsm_odr) { @@ -5393,6 +5764,13 @@ int32_t lsm6dsv_fsm_data_rate_get(stmdev_ctx_t *ctx, * * Released under BSD-3-Clause License */ + +#define NPY_HALF_GENERATE_OVERFLOW 0 /* do not trigger FP overflow */ +#define NPY_HALF_GENERATE_UNDERFLOW 0 /* do not trigger FP underflow */ +#ifndef NPY_HALF_ROUND_TIES_TO_EVEN +#define NPY_HALF_ROUND_TIES_TO_EVEN 1 +#endif + static uint16_t npy_floatbits_to_halfbits(uint32_t f) { uint32_t f_exp, f_sig; @@ -5552,8 +5930,8 @@ static uint16_t npy_float_to_half(float_t f) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_sflp_game_gbias_set(stmdev_ctx_t *ctx, - lsm6dsv_sflp_gbias_t *val) +int32_t lsm6dsv_sflp_game_gbias_set(const stmdev_ctx_t *ctx, + lsm6dsv_sflp_gbias_t *val) { lsm6dsv_sflp_data_rate_t sflp_odr; lsm6dsv_emb_func_exec_status_t emb_func_sts; @@ -5573,7 +5951,10 @@ int32_t lsm6dsv_sflp_game_gbias_set(stmdev_ctx_t *ctx, int32_t ret; ret = lsm6dsv_sflp_data_rate_get(ctx, &sflp_odr); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } /* Calculate k factor */ switch (sflp_odr) @@ -5624,7 +6005,7 @@ int32_t lsm6dsv_sflp_game_gbias_set(stmdev_ctx_t *ctx, do { ret += lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EXEC_STATUS, - (uint8_t *)&emb_func_sts, 1); + (uint8_t *)&emb_func_sts, 1); } while (emb_func_sts.emb_func_endop != 1U); ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); @@ -5637,7 +6018,7 @@ int32_t lsm6dsv_sflp_game_gbias_set(stmdev_ctx_t *ctx, ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); emb_func_en_saved[0] |= 0x02U; /* force SFLP GAME en */ ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, emb_func_en_saved, - 2); + 2); ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); ret += lsm6dsv_xl_full_scale_get(ctx, &xl_fs); @@ -5657,22 +6038,22 @@ int32_t lsm6dsv_sflp_game_gbias_set(stmdev_ctx_t *ctx, data_tmp = (int32_t)xl_data[i]; data_tmp <<= xl_fs; // shift based on current fs ret += lsm6dsv_write_reg(ctx, LSM6DSV_SENSOR_HUB_1 + 3U * i, - &data_ptr[j++], 1); + &data_ptr[j++], 1); ret += lsm6dsv_write_reg(ctx, LSM6DSV_SENSOR_HUB_2 + 3U * i, - &data_ptr[j++], 1); + &data_ptr[j++], 1); ret += lsm6dsv_write_reg(ctx, LSM6DSV_SENSOR_HUB_3 + 3U * i, &data_ptr[j], - 1); + 1); } for (i = 0; i < 3U; i++) { j = 0; data_tmp = 0; ret += lsm6dsv_write_reg(ctx, LSM6DSV_SENSOR_HUB_10 + 3U * i, - &data_ptr[j++], 1); + &data_ptr[j++], 1); ret += lsm6dsv_write_reg(ctx, LSM6DSV_SENSOR_HUB_11 + 3U * i, - &data_ptr[j++], 1); + &data_ptr[j++], 1); ret += lsm6dsv_write_reg(ctx, LSM6DSV_SENSOR_HUB_12 + 3U * i, &data_ptr[j], - 1); + 1); } ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); @@ -5682,13 +6063,13 @@ int32_t lsm6dsv_sflp_game_gbias_set(stmdev_ctx_t *ctx, do { ret += lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EXEC_STATUS, - (uint8_t *)&emb_func_sts, 1); + (uint8_t *)&emb_func_sts, 1); } while (emb_func_sts.emb_func_endop != 1U); ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); /* write gbias in embedded advanced features registers */ ret += lsm6dsv_ln_pg_write(ctx, LSM6DSV_SFLP_GAME_GBIASX_L, - (uint8_t *)gbias_hf, 6); + (uint8_t *)gbias_hf, 6); /* reload previous sensor configuration */ ret += lsm6dsv_write_reg(ctx, LSM6DSV_CTRL1, conf_saved, 2); @@ -5711,7 +6092,7 @@ int32_t lsm6dsv_sflp_game_gbias_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_ext_sens_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsv_fsm_ext_sens_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; @@ -5731,13 +6112,17 @@ int32_t lsm6dsv_fsm_ext_sens_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_ext_sens_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsv_fsm_ext_sens_sensitivity_get(const stmdev_ctx_t *ctx, + uint16_t *val) { uint8_t buff[2]; int32_t ret; ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_FSM_EXT_SENSITIVITY_L, &buff[0], 2); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -5753,7 +6138,7 @@ int32_t lsm6dsv_fsm_ext_sens_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_ext_sens_offset_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_ext_sens_offset_set(const stmdev_ctx_t *ctx, lsm6dsv_xl_fsm_ext_sens_offset_t val) { uint8_t buff[6]; @@ -5778,14 +6163,17 @@ int32_t lsm6dsv_fsm_ext_sens_offset_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_ext_sens_offset_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_ext_sens_offset_get(const stmdev_ctx_t *ctx, lsm6dsv_xl_fsm_ext_sens_offset_t *val) { uint8_t buff[6]; int32_t ret; ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_FSM_EXT_OFFX_L, &buff[0], 6); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->x = buff[1]; val->x = (val->x * 256U) + buff[0]; @@ -5805,7 +6193,7 @@ int32_t lsm6dsv_fsm_ext_sens_offset_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_ext_sens_matrix_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_ext_sens_matrix_set(const stmdev_ctx_t *ctx, lsm6dsv_xl_fsm_ext_sens_matrix_t val) { uint8_t buff[12]; @@ -5836,14 +6224,17 @@ int32_t lsm6dsv_fsm_ext_sens_matrix_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_ext_sens_matrix_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_ext_sens_matrix_get(const stmdev_ctx_t *ctx, lsm6dsv_xl_fsm_ext_sens_matrix_t *val) { uint8_t buff[12]; int32_t ret; ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_FSM_EXT_MATRIX_XX_L, &buff[0], 12); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->xx = buff[1]; val->xx = (val->xx * 256U) + buff[0]; @@ -5869,7 +6260,7 @@ int32_t lsm6dsv_fsm_ext_sens_matrix_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_ext_sens_z_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_ext_sens_z_orient_set(const stmdev_ctx_t *ctx, lsm6dsv_fsm_ext_sens_z_orient_t val) { lsm6dsv_ext_cfg_a_t ext_cfg_a; @@ -5890,14 +6281,17 @@ int32_t lsm6dsv_fsm_ext_sens_z_orient_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_ext_sens_z_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_ext_sens_z_orient_get(const stmdev_ctx_t *ctx, lsm6dsv_fsm_ext_sens_z_orient_t *val) { lsm6dsv_ext_cfg_a_t ext_cfg_a; int32_t ret; ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ext_cfg_a.ext_z_axis) { @@ -5941,7 +6335,7 @@ int32_t lsm6dsv_fsm_ext_sens_z_orient_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_ext_sens_y_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_ext_sens_y_orient_set(const stmdev_ctx_t *ctx, lsm6dsv_fsm_ext_sens_y_orient_t val) { lsm6dsv_ext_cfg_a_t ext_cfg_a; @@ -5965,14 +6359,17 @@ int32_t lsm6dsv_fsm_ext_sens_y_orient_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_ext_sens_y_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_ext_sens_y_orient_get(const stmdev_ctx_t *ctx, lsm6dsv_fsm_ext_sens_y_orient_t *val) { lsm6dsv_ext_cfg_a_t ext_cfg_a; int32_t ret; ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ext_cfg_a.ext_y_axis) { @@ -6016,7 +6413,7 @@ int32_t lsm6dsv_fsm_ext_sens_y_orient_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_ext_sens_x_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_ext_sens_x_orient_set(const stmdev_ctx_t *ctx, lsm6dsv_fsm_ext_sens_x_orient_t val) { lsm6dsv_ext_cfg_b_t ext_cfg_b; @@ -6040,14 +6437,17 @@ int32_t lsm6dsv_fsm_ext_sens_x_orient_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_ext_sens_x_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_ext_sens_x_orient_get(const stmdev_ctx_t *ctx, lsm6dsv_fsm_ext_sens_x_orient_t *val) { lsm6dsv_ext_cfg_b_t ext_cfg_b; int32_t ret; ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EXT_CFG_B, (uint8_t *)&ext_cfg_b, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ext_cfg_b.ext_x_axis) { @@ -6091,14 +6491,15 @@ int32_t lsm6dsv_fsm_ext_sens_x_orient_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_long_cnt_timeout_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsv_fsm_long_cnt_timeout_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; buff[1] = (uint8_t)(val / 256U); buff[0] = (uint8_t)(val - (buff[1] * 256U)); - ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_FSM_LC_TIMEOUT_L, (uint8_t *)&buff[0], 2); + ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_FSM_LC_TIMEOUT_L, (uint8_t *)&buff[0], + 2); return ret; } @@ -6111,13 +6512,16 @@ int32_t lsm6dsv_fsm_long_cnt_timeout_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_long_cnt_timeout_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsv_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_FSM_LC_TIMEOUT_L, &buff[0], 2); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -6133,16 +6537,18 @@ int32_t lsm6dsv_fsm_long_cnt_timeout_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_fsm_programs_t fsm_programs; int32_t ret; - ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_FSM_PROGRAMS, (uint8_t *)&fsm_programs, + 1); if (ret == 0) { fsm_programs.fsm_n_prog = val; - ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_FSM_PROGRAMS, + (uint8_t *)&fsm_programs, 1); } return ret; @@ -6156,12 +6562,13 @@ int32_t lsm6dsv_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_fsm_programs_t fsm_programs; int32_t ret; - ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_FSM_PROGRAMS, (uint8_t *)&fsm_programs, + 1); *val = fsm_programs.fsm_n_prog; return ret; @@ -6175,14 +6582,15 @@ int32_t lsm6dsv_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsv_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; buff[1] = (uint8_t)(val / 256U); buff[0] = (uint8_t)(val - (buff[1] * 256U)); - ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_FSM_START_ADD_L, (uint8_t *)&buff[0], 2); + ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_FSM_START_ADD_L, (uint8_t *)&buff[0], + 2); return ret; } @@ -6195,13 +6603,16 @@ int32_t lsm6dsv_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsv_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_FSM_START_ADD_L, &buff[0], 2); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -6230,7 +6641,7 @@ int32_t lsm6dsv_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ff_time_windows_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_wake_up_dur_t wake_up_dur; lsm6dsv_free_fall_t free_fall; @@ -6239,7 +6650,10 @@ int32_t lsm6dsv_ff_time_windows_set(stmdev_ctx_t *ctx, uint8_t val) ret = lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5; ret += lsm6dsv_write_reg(ctx, LSM6DSV_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv_read_reg(ctx, LSM6DSV_FREE_FALL, (uint8_t *)&free_fall, 1); free_fall.ff_dur = (uint8_t)val & 0x1FU; @@ -6256,7 +6670,7 @@ int32_t lsm6dsv_ff_time_windows_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ff_time_windows_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_wake_up_dur_t wake_up_dur; lsm6dsv_free_fall_t free_fall; @@ -6278,7 +6692,7 @@ int32_t lsm6dsv_ff_time_windows_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ff_thresholds_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ff_thresholds_set(const stmdev_ctx_t *ctx, lsm6dsv_ff_thresholds_t val) { lsm6dsv_free_fall_t free_fall; @@ -6302,14 +6716,17 @@ int32_t lsm6dsv_ff_thresholds_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ff_thresholds_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ff_thresholds_get(const stmdev_ctx_t *ctx, lsm6dsv_ff_thresholds_t *val) { lsm6dsv_free_fall_t free_fall; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_FREE_FALL, (uint8_t *)&free_fall, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (free_fall.ff_ths) { @@ -6349,6 +6766,7 @@ int32_t lsm6dsv_ff_thresholds_get(stmdev_ctx_t *ctx, *val = LSM6DSV_156_mg; break; } + return ret; } @@ -6373,7 +6791,7 @@ int32_t lsm6dsv_ff_thresholds_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ois_ctrl_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_ctrl_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_ois_ctrl_mode_t val) { lsm6dsv_func_cfg_access_t func_cfg_access; @@ -6397,14 +6815,17 @@ int32_t lsm6dsv_ois_ctrl_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ois_ctrl_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_ctrl_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_ois_ctrl_mode_t *val) { lsm6dsv_func_cfg_access_t func_cfg_access; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (func_cfg_access.ois_ctrl_from_ui) { @@ -6432,7 +6853,7 @@ int32_t lsm6dsv_ois_ctrl_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ois_reset_set(stmdev_ctx_t *ctx, int8_t val) +int32_t lsm6dsv_ois_reset_set(const stmdev_ctx_t *ctx, int8_t val) { lsm6dsv_func_cfg_access_t func_cfg_access; int32_t ret; @@ -6455,7 +6876,7 @@ int32_t lsm6dsv_ois_reset_set(stmdev_ctx_t *ctx, int8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ois_reset_get(stmdev_ctx_t *ctx, int8_t *val) +int32_t lsm6dsv_ois_reset_get(const stmdev_ctx_t *ctx, int8_t *val) { lsm6dsv_func_cfg_access_t func_cfg_access; int32_t ret; @@ -6474,7 +6895,7 @@ int32_t lsm6dsv_ois_reset_get(stmdev_ctx_t *ctx, int8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ois_interface_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_ois_interface_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_pin_ctrl_t pin_ctrl; int32_t ret; @@ -6497,7 +6918,7 @@ int32_t lsm6dsv_ois_interface_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ois_interface_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_ois_interface_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_pin_ctrl_t pin_ctrl; int32_t ret; @@ -6516,7 +6937,7 @@ int32_t lsm6dsv_ois_interface_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ois_handshake_from_ui_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_handshake_from_ui_set(const stmdev_ctx_t *ctx, lsm6dsv_ois_handshake_t val) { lsm6dsv_ui_handshake_ctrl_t ui_handshake_ctrl; @@ -6541,14 +6962,17 @@ int32_t lsm6dsv_ois_handshake_from_ui_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ois_handshake_from_ui_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_handshake_from_ui_get(const stmdev_ctx_t *ctx, lsm6dsv_ois_handshake_t *val) { lsm6dsv_ui_handshake_ctrl_t ui_handshake_ctrl; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_HANDSHAKE_CTRL, (uint8_t *)&ui_handshake_ctrl, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->ack = ui_handshake_ctrl.ui_shared_ack; val->req = ui_handshake_ctrl.ui_shared_req; @@ -6564,7 +6988,7 @@ int32_t lsm6dsv_ois_handshake_from_ui_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ois_handshake_from_ois_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_handshake_from_ois_set(const stmdev_ctx_t *ctx, lsm6dsv_ois_handshake_t val) { lsm6dsv_spi2_handshake_ctrl_t spi2_handshake_ctrl; @@ -6589,14 +7013,17 @@ int32_t lsm6dsv_ois_handshake_from_ois_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ois_handshake_from_ois_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_handshake_from_ois_get(const stmdev_ctx_t *ctx, lsm6dsv_ois_handshake_t *val) { lsm6dsv_spi2_handshake_ctrl_t spi2_handshake_ctrl; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_SPI2_HANDSHAKE_CTRL, (uint8_t *)&spi2_handshake_ctrl, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->ack = spi2_handshake_ctrl.spi2_shared_ack; val->req = spi2_handshake_ctrl.spi2_shared_req; @@ -6612,7 +7039,7 @@ int32_t lsm6dsv_ois_handshake_from_ois_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ois_shared_set(stmdev_ctx_t *ctx, uint8_t val[6]) +int32_t lsm6dsv_ois_shared_set(const stmdev_ctx_t *ctx, uint8_t val[6]) { int32_t ret; @@ -6629,7 +7056,7 @@ int32_t lsm6dsv_ois_shared_set(stmdev_ctx_t *ctx, uint8_t val[6]) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ois_shared_get(stmdev_ctx_t *ctx, uint8_t val[6]) +int32_t lsm6dsv_ois_shared_get(const stmdev_ctx_t *ctx, uint8_t val[6]) { int32_t ret; @@ -6646,7 +7073,7 @@ int32_t lsm6dsv_ois_shared_get(stmdev_ctx_t *ctx, uint8_t val[6]) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ois_on_spi2_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_ois_on_spi2_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_ui_ctrl1_ois_t ui_ctrl1_ois; int32_t ret; @@ -6669,7 +7096,7 @@ int32_t lsm6dsv_ois_on_spi2_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ois_on_spi2_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_ois_on_spi2_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_ui_ctrl1_ois_t ui_ctrl1_ois; int32_t ret; @@ -6688,7 +7115,7 @@ int32_t lsm6dsv_ois_on_spi2_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ois_chain_set(stmdev_ctx_t *ctx, lsm6dsv_ois_chain_t val) +int32_t lsm6dsv_ois_chain_set(const stmdev_ctx_t *ctx, lsm6dsv_ois_chain_t val) { lsm6dsv_ui_ctrl1_ois_t ui_ctrl1_ois; int32_t ret; @@ -6712,13 +7139,16 @@ int32_t lsm6dsv_ois_chain_set(stmdev_ctx_t *ctx, lsm6dsv_ois_chain_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ois_chain_get(stmdev_ctx_t *ctx, lsm6dsv_ois_chain_t *val) +int32_t lsm6dsv_ois_chain_get(const stmdev_ctx_t *ctx, lsm6dsv_ois_chain_t *val) { lsm6dsv_ui_ctrl1_ois_t ui_ctrl1_ois; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->gy = ui_ctrl1_ois.ois_g_en; val->xl = ui_ctrl1_ois.ois_xl_en; @@ -6734,7 +7164,7 @@ int32_t lsm6dsv_ois_chain_get(stmdev_ctx_t *ctx, lsm6dsv_ois_chain_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ois_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsv_ois_gy_full_scale_t val) { lsm6dsv_ui_ctrl2_ois_t ui_ctrl2_ois; @@ -6758,14 +7188,17 @@ int32_t lsm6dsv_ois_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ois_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsv_ois_gy_full_scale_t *val) { lsm6dsv_ui_ctrl2_ois_t ui_ctrl2_ois; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ui_ctrl2_ois.fs_g_ois) { @@ -6801,11 +7234,11 @@ int32_t lsm6dsv_ois_gy_full_scale_get(stmdev_ctx_t *ctx, * @brief Selects accelerometer OIS channel full-scale.[set] * * @param ctx read / write interface definitions - * @param val OIS_2g, OIS_4g, OIS_8g, OIS_16g, + * @param val lsm6dsv_ois_xl_full_scale_t * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ois_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsv_ois_xl_full_scale_t val) { lsm6dsv_ui_ctrl3_ois_t ui_ctrl3_ois; @@ -6825,18 +7258,21 @@ int32_t lsm6dsv_ois_xl_full_scale_set(stmdev_ctx_t *ctx, * @brief Selects accelerometer OIS channel full-scale.[get] * * @param ctx read / write interface definitions - * @param val OIS_2g, OIS_4g, OIS_8g, OIS_16g, + * @param val lsm6dsv_ois_xl_full_scale_t * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ois_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsv_ois_xl_full_scale_t *val) { lsm6dsv_ui_ctrl3_ois_t ui_ctrl3_ois; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ui_ctrl3_ois.fs_xl_ois) { @@ -6885,7 +7321,8 @@ int32_t lsm6dsv_ois_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_6d_threshold_set(stmdev_ctx_t *ctx, lsm6dsv_6d_threshold_t val) +int32_t lsm6dsv_6d_threshold_set(const stmdev_ctx_t *ctx, + lsm6dsv_6d_threshold_t val) { lsm6dsv_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -6908,13 +7345,17 @@ int32_t lsm6dsv_6d_threshold_set(stmdev_ctx_t *ctx, lsm6dsv_6d_threshold_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_6d_threshold_get(stmdev_ctx_t *ctx, lsm6dsv_6d_threshold_t *val) +int32_t lsm6dsv_6d_threshold_get(const stmdev_ctx_t *ctx, + lsm6dsv_6d_threshold_t *val) { lsm6dsv_tap_ths_6d_t tap_ths_6d; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (tap_ths_6d.sixd_ths) { @@ -6950,7 +7391,7 @@ int32_t lsm6dsv_6d_threshold_get(stmdev_ctx_t *ctx, lsm6dsv_6d_threshold_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -6973,7 +7414,7 @@ int32_t lsm6dsv_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_tap_ths_6d_t tap_ths_6d; int32_t ret; @@ -7005,7 +7446,7 @@ int32_t lsm6dsv_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_i3c_reset_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_i3c_reset_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_i3c_reset_mode_t val) { lsm6dsv_pin_ctrl_t pin_ctrl; @@ -7029,14 +7470,17 @@ int32_t lsm6dsv_i3c_reset_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_i3c_reset_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_i3c_reset_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_i3c_reset_mode_t *val) { lsm6dsv_pin_ctrl_t pin_ctrl; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (pin_ctrl.ibhr_por_en) { @@ -7056,6 +7500,48 @@ int32_t lsm6dsv_i3c_reset_mode_get(stmdev_ctx_t *ctx, return ret; } +/** + * @brief Enable/Disable INT pin when I3C is used.[set] + * + * @param ctx read / write interface definitions + * @param val 0: disabled, 1: enabled + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_i3c_int_en_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6dsv_ctrl5_t ctrl5; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret == 0) + { + ctrl5.int_en_i3c = (uint8_t)val & 0x01U; + ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL5, (uint8_t *)&ctrl5, 1); + } + + return ret; +} + +/** + * @brief Enable/Disable INT pin when I3C is used.[get] + * + * @param ctx read / write interface definitions + * @param val 0: disabled, 1: enabled + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6dsv_i3c_int_en_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6dsv_ctrl5_t ctrl5; + int32_t ret; + + ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL5, (uint8_t *)&ctrl5, 1); + *val = ctrl5.int_en_i3c; + + return ret; +} + /** * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[set] * @@ -7064,7 +7550,8 @@ int32_t lsm6dsv_i3c_reset_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_i3c_ibi_time_set(stmdev_ctx_t *ctx, lsm6dsv_i3c_ibi_time_t val) +int32_t lsm6dsv_i3c_ibi_time_set(const stmdev_ctx_t *ctx, + lsm6dsv_i3c_ibi_time_t val) { lsm6dsv_ctrl5_t ctrl5; int32_t ret; @@ -7087,13 +7574,17 @@ int32_t lsm6dsv_i3c_ibi_time_set(stmdev_ctx_t *ctx, lsm6dsv_i3c_ibi_time_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_i3c_ibi_time_get(stmdev_ctx_t *ctx, lsm6dsv_i3c_ibi_time_t *val) +int32_t lsm6dsv_i3c_ibi_time_get(const stmdev_ctx_t *ctx, + lsm6dsv_i3c_ibi_time_t *val) { lsm6dsv_ctrl5_t ctrl5; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL5, (uint8_t *)&ctrl5, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ctrl5.bus_act_sel) { @@ -7142,7 +7633,8 @@ int32_t lsm6dsv_i3c_ibi_time_get(stmdev_ctx_t *ctx, lsm6dsv_i3c_ibi_time_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_sh_master_interface_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_sh_master_interface_pull_up_set(const stmdev_ctx_t *ctx, + uint8_t val) { lsm6dsv_if_cfg_t if_cfg; int32_t ret; @@ -7165,7 +7657,8 @@ int32_t lsm6dsv_sh_master_interface_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_sh_master_interface_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_sh_master_interface_pull_up_get(const stmdev_ctx_t *ctx, + uint8_t *val) { lsm6dsv_if_cfg_t if_cfg; int32_t ret; @@ -7184,7 +7677,7 @@ int32_t lsm6dsv_sh_master_interface_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val, +int32_t lsm6dsv_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, uint8_t len) { int32_t ret; @@ -7204,7 +7697,7 @@ int32_t lsm6dsv_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_sh_slave_connected_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_sh_slave_connected_set(const stmdev_ctx_t *ctx, lsm6dsv_sh_slave_connected_t val) { lsm6dsv_master_config_t master_config; @@ -7212,7 +7705,10 @@ int32_t lsm6dsv_sh_slave_connected_set(stmdev_ctx_t *ctx, ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } master_config.aux_sens_on = (uint8_t)val & 0x3U; ret = lsm6dsv_write_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); @@ -7231,7 +7727,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_sh_slave_connected_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_sh_slave_connected_get(const stmdev_ctx_t *ctx, lsm6dsv_sh_slave_connected_t *val) { lsm6dsv_master_config_t master_config; @@ -7240,7 +7736,10 @@ int32_t lsm6dsv_sh_slave_connected_get(stmdev_ctx_t *ctx, ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (master_config.aux_sens_on) { @@ -7276,14 +7775,17 @@ int32_t lsm6dsv_sh_slave_connected_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_master_config_t master_config; int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } master_config.master_on = val; ret = lsm6dsv_write_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); @@ -7302,7 +7804,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_master_config_t master_config; int32_t ret; @@ -7325,14 +7827,17 @@ int32_t lsm6dsv_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_master_config_t master_config; int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } master_config.pass_through_mode = val; ret = lsm6dsv_write_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); @@ -7351,7 +7856,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_master_config_t master_config; int32_t ret; @@ -7374,7 +7879,7 @@ int32_t lsm6dsv_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_sh_syncro_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_sh_syncro_mode_t val) { lsm6dsv_master_config_t master_config; @@ -7382,7 +7887,10 @@ int32_t lsm6dsv_sh_syncro_mode_set(stmdev_ctx_t *ctx, ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } master_config.start_config = (uint8_t)val & 0x01U; ret = lsm6dsv_write_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); @@ -7401,7 +7909,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_sh_syncro_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_sh_syncro_mode_t *val) { lsm6dsv_master_config_t master_config; @@ -7410,7 +7918,10 @@ int32_t lsm6dsv_sh_syncro_mode_get(stmdev_ctx_t *ctx, ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (master_config.start_config) { @@ -7438,7 +7949,7 @@ int32_t lsm6dsv_sh_syncro_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_sh_write_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_sh_write_mode_t val) { lsm6dsv_master_config_t master_config; @@ -7446,7 +7957,10 @@ int32_t lsm6dsv_sh_write_mode_set(stmdev_ctx_t *ctx, ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } master_config.write_once = (uint8_t)val & 0x01U; ret = lsm6dsv_write_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); @@ -7465,7 +7979,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_sh_write_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_sh_write_mode_t *val) { lsm6dsv_master_config_t master_config; @@ -7474,7 +7988,10 @@ int32_t lsm6dsv_sh_write_mode_get(stmdev_ctx_t *ctx, ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (master_config.write_once) { @@ -7502,14 +8019,17 @@ int32_t lsm6dsv_sh_write_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_sh_reset_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_sh_reset_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_master_config_t master_config; int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } master_config.rst_master_regs = val; ret = lsm6dsv_write_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1); @@ -7528,7 +8048,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_master_config_t master_config; int32_t ret; @@ -7554,26 +8074,35 @@ int32_t lsm6dsv_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t lsm6dsv_sh_cfg_write(const stmdev_ctx_t *ctx, lsm6dsv_sh_cfg_write_t *val) { lsm6dsv_slv0_add_t reg; int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } reg.slave0_add = val->slv0_add; reg.rw_0 = 0; ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV0_ADD, (uint8_t *)®, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV0_SUBADD, - &(val->slv0_subadd), 1); - if (ret != 0) { goto exit; } + &(val->slv0_subadd), 1); + if (ret != 0) + { + goto exit; + } ret = lsm6dsv_write_reg(ctx, LSM6DSV_DATAWRITE_SLV0, - &(val->slv0_data), 1); + &(val->slv0_data), 1); exit: ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); @@ -7589,14 +8118,18 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_sh_data_rate_set(stmdev_ctx_t *ctx, lsm6dsv_sh_data_rate_t val) +int32_t lsm6dsv_sh_data_rate_set(const stmdev_ctx_t *ctx, + lsm6dsv_sh_data_rate_t val) { lsm6dsv_slv0_config_t slv0_config; int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); ret += lsm6dsv_read_reg(ctx, LSM6DSV_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } slv0_config.shub_odr = (uint8_t)val & 0x07U; ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); @@ -7615,7 +8148,8 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_sh_data_rate_get(stmdev_ctx_t *ctx, lsm6dsv_sh_data_rate_t *val) +int32_t lsm6dsv_sh_data_rate_get(const stmdev_ctx_t *ctx, + lsm6dsv_sh_data_rate_t *val) { lsm6dsv_slv0_config_t slv0_config; int32_t ret; @@ -7623,7 +8157,10 @@ int32_t lsm6dsv_sh_data_rate_get(stmdev_ctx_t *ctx, lsm6dsv_sh_data_rate_t *val) ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); ret += lsm6dsv_read_reg(ctx, LSM6DSV_SLV0_CONFIG, (uint8_t *)&slv0_config, 1); ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (slv0_config.shub_odr) { @@ -7670,33 +8207,45 @@ int32_t lsm6dsv_sh_data_rate_get(stmdev_ctx_t *ctx, lsm6dsv_sh_data_rate_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_sh_slv_cfg_read(stmdev_ctx_t *ctx, uint8_t idx, - lsm6dsv_sh_cfg_read_t *val) +int32_t lsm6dsv_sh_slv_cfg_read(const stmdev_ctx_t *ctx, uint8_t idx, + lsm6dsv_sh_cfg_read_t *val) { lsm6dsv_slv0_add_t slv_add; lsm6dsv_slv0_config_t slv_config; int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } slv_add.slave0_add = val->slv_add; slv_add.rw_0 = 1; - ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV0_ADD + idx*3U, - (uint8_t *)&slv_add, 1); - if (ret != 0) { goto exit; } + ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV0_ADD + idx * 3U, + (uint8_t *)&slv_add, 1); + if (ret != 0) + { + goto exit; + } - ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV0_SUBADD + idx*3U, - &(val->slv_subadd), 1); - if (ret != 0) { goto exit; } + ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV0_SUBADD + idx * 3U, + &(val->slv_subadd), 1); + if (ret != 0) + { + goto exit; + } - ret = lsm6dsv_read_reg(ctx, LSM6DSV_SLV0_CONFIG + idx*3U, - (uint8_t *)&slv_config, 1); - if (ret != 0) { goto exit; } + ret = lsm6dsv_read_reg(ctx, LSM6DSV_SLV0_CONFIG + idx * 3U, + (uint8_t *)&slv_config, 1); + if (ret != 0) + { + goto exit; + } slv_config.slave0_numop = val->slv_len; - ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV0_CONFIG + idx*3U, - (uint8_t *)&slv_config, 1); + ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV0_CONFIG + idx * 3U, + (uint8_t *)&slv_config, 1); exit: ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); @@ -7712,7 +8261,7 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_sh_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_sh_status_get(const stmdev_ctx_t *ctx, lsm6dsv_status_master_t *val) { int32_t ret; @@ -7743,7 +8292,7 @@ int32_t lsm6dsv_sh_status_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_pin_ctrl_t pin_ctrl; int32_t ret; @@ -7766,7 +8315,7 @@ int32_t lsm6dsv_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_pin_ctrl_t pin_ctrl; int32_t ret; @@ -7785,7 +8334,7 @@ int32_t lsm6dsv_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ui_i2c_i3c_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ui_i2c_i3c_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_ui_i2c_i3c_mode_t val) { lsm6dsv_if_cfg_t if_cfg; @@ -7809,14 +8358,17 @@ int32_t lsm6dsv_ui_i2c_i3c_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ui_i2c_i3c_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_ui_i2c_i3c_mode_t *val) { lsm6dsv_if_cfg_t if_cfg; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (if_cfg.i2c_i3c_disable) { @@ -7844,7 +8396,7 @@ int32_t lsm6dsv_ui_i2c_i3c_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsv_spi_mode_t val) +int32_t lsm6dsv_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_spi_mode_t val) { lsm6dsv_if_cfg_t if_cfg; int32_t ret; @@ -7867,13 +8419,16 @@ int32_t lsm6dsv_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsv_spi_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsv_spi_mode_t *val) +int32_t lsm6dsv_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_spi_mode_t *val) { lsm6dsv_if_cfg_t if_cfg; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (if_cfg.sim) { @@ -7901,7 +8456,7 @@ int32_t lsm6dsv_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsv_spi_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ui_sda_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_ui_sda_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_if_cfg_t if_cfg; int32_t ret; @@ -7924,7 +8479,7 @@ int32_t lsm6dsv_ui_sda_pull_up_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_ui_sda_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_if_cfg_t if_cfg; int32_t ret; @@ -7943,7 +8498,7 @@ int32_t lsm6dsv_ui_sda_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_spi2_mode_set(stmdev_ctx_t *ctx, lsm6dsv_spi2_mode_t val) +int32_t lsm6dsv_spi2_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_spi2_mode_t val) { lsm6dsv_ui_ctrl1_ois_t ui_ctrl1_ois; int32_t ret; @@ -7966,13 +8521,16 @@ int32_t lsm6dsv_spi2_mode_set(stmdev_ctx_t *ctx, lsm6dsv_spi2_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_spi2_mode_get(stmdev_ctx_t *ctx, lsm6dsv_spi2_mode_t *val) +int32_t lsm6dsv_spi2_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_spi2_mode_t *val) { lsm6dsv_ui_ctrl1_ois_t ui_ctrl1_ois; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (ui_ctrl1_ois.sim_ois) { @@ -8014,13 +8572,16 @@ int32_t lsm6dsv_spi2_mode_get(stmdev_ctx_t *ctx, lsm6dsv_spi2_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_emb_func_en_a_t emb_func_en_a; int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); emb_func_en_a.sign_motion_en = val; @@ -8039,13 +8600,16 @@ int32_t lsm6dsv_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_emb_func_en_a_t emb_func_en_a; int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); *val = emb_func_en_a.sign_motion_en; @@ -8075,19 +8639,28 @@ int32_t lsm6dsv_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_stpcnt_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_stpcnt_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_stpcnt_mode_t val) { lsm6dsv_emb_func_en_a_t emb_func_en_a; int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + if (ret != 0) + { + goto exit; + } + emb_func_en_a.pedo_en = val.step_counter_enable; ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); +exit: ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); return ret; @@ -8101,7 +8674,7 @@ int32_t lsm6dsv_stpcnt_mode_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_stpcnt_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_stpcnt_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_stpcnt_mode_t *val) { lsm6dsv_emb_func_en_a_t emb_func_en_a; @@ -8110,7 +8683,10 @@ int32_t lsm6dsv_stpcnt_mode_get(stmdev_ctx_t *ctx, ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); ret += lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } return ret; } @@ -8123,7 +8699,7 @@ int32_t lsm6dsv_stpcnt_mode_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsv_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -8131,7 +8707,10 @@ int32_t lsm6dsv_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val) ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); ret += lsm6dsv_read_reg(ctx, LSM6DSV_STEP_COUNTER_L, &buff[0], 2); ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -8147,16 +8726,22 @@ int32_t lsm6dsv_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_stpcnt_rst_step_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_stpcnt_rst_step_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_emb_func_src_t emb_func_src; int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } emb_func_src.pedo_rst_step = val; ret = lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); @@ -8175,13 +8760,16 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_stpcnt_rst_step_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_emb_func_src_t emb_func_src; int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); *val = emb_func_src.pedo_rst_step; @@ -8199,16 +8787,18 @@ int32_t lsm6dsv_stpcnt_rst_step_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_pedo_deb_steps_conf_t pedo_deb_steps_conf; int32_t ret; - ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_PEDO_DEB_STEPS_CONF, + (uint8_t *)&pedo_deb_steps_conf, 1); if (ret == 0) { pedo_deb_steps_conf.deb_step = val; - ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_PEDO_DEB_STEPS_CONF, + (uint8_t *)&pedo_deb_steps_conf, 1); } return ret; @@ -8222,12 +8812,13 @@ int32_t lsm6dsv_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_pedo_deb_steps_conf_t pedo_deb_steps_conf; int32_t ret; - ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1); + ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_PEDO_DEB_STEPS_CONF, + (uint8_t *)&pedo_deb_steps_conf, 1); *val = pedo_deb_steps_conf.deb_step; return ret; @@ -8241,14 +8832,15 @@ int32_t lsm6dsv_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm6dsv_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val) { uint8_t buff[2]; int32_t ret; buff[1] = (uint8_t)(val / 256U); buff[0] = (uint8_t)(val - (buff[1] * 256U)); - ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_PEDO_SC_DELTAT_L, (uint8_t *)&buff[0], 2); + ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_PEDO_SC_DELTAT_L, (uint8_t *)&buff[0], + 2); return ret; } @@ -8261,13 +8853,16 @@ int32_t lsm6dsv_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm6dsv_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_PEDO_SC_DELTAT_L, &buff[0], 2); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } *val = buff[1]; *val = (*val * 256U) + buff[0]; @@ -8295,20 +8890,26 @@ int32_t lsm6dsv_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_sflp_game_rotation_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_emb_func_en_a_t emb_func_en_a; int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } emb_func_en_a.sflp_game_en = val; ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, - (uint8_t *)&emb_func_en_a, 1); + (uint8_t *)&emb_func_en_a, 1); exit: ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); @@ -8324,13 +8925,16 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_sflp_game_rotation_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_emb_func_en_a_t emb_func_en_a; int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); *val = emb_func_en_a.sflp_game_en; @@ -8348,17 +8952,23 @@ int32_t lsm6dsv_sflp_game_rotation_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_sflp_data_rate_set(stmdev_ctx_t *ctx, - lsm6dsv_sflp_data_rate_t val) +int32_t lsm6dsv_sflp_data_rate_set(const stmdev_ctx_t *ctx, + lsm6dsv_sflp_data_rate_t val) { lsm6dsv_sflp_odr_t sflp_odr; int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv_read_reg(ctx, LSM6DSV_SFLP_ODR, (uint8_t *)&sflp_odr, 1); - if (ret != 0) { goto exit; } + if (ret != 0) + { + goto exit; + } sflp_odr.sflp_game_odr = (uint8_t)val & 0x07U; ret += lsm6dsv_write_reg(ctx, LSM6DSV_SFLP_ODR, (uint8_t *)&sflp_odr, 1); @@ -8377,8 +8987,8 @@ exit: * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_sflp_data_rate_get(stmdev_ctx_t *ctx, - lsm6dsv_sflp_data_rate_t *val) +int32_t lsm6dsv_sflp_data_rate_get(const stmdev_ctx_t *ctx, + lsm6dsv_sflp_data_rate_t *val) { lsm6dsv_sflp_odr_t sflp_odr; int32_t ret; @@ -8386,7 +8996,10 @@ int32_t lsm6dsv_sflp_data_rate_get(stmdev_ctx_t *ctx, ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); ret += lsm6dsv_read_reg(ctx, LSM6DSV_SFLP_ODR, (uint8_t *)&sflp_odr, 1); ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (sflp_odr.sflp_game_odr) { @@ -8443,7 +9056,7 @@ int32_t lsm6dsv_sflp_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_tap_detection_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_tap_detection_set(const stmdev_ctx_t *ctx, lsm6dsv_tap_detection_t val) { lsm6dsv_tap_cfg0_t tap_cfg0; @@ -8469,14 +9082,17 @@ int32_t lsm6dsv_tap_detection_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_tap_detection_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_tap_detection_get(const stmdev_ctx_t *ctx, lsm6dsv_tap_detection_t *val) { lsm6dsv_tap_cfg0_t tap_cfg0; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->tap_x_en = tap_cfg0.tap_x_en; val->tap_y_en = tap_cfg0.tap_y_en; @@ -8493,7 +9109,7 @@ int32_t lsm6dsv_tap_detection_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_tap_thresholds_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_tap_thresholds_set(const stmdev_ctx_t *ctx, lsm6dsv_tap_thresholds_t val) { lsm6dsv_tap_ths_6d_t tap_ths_6d; @@ -8504,7 +9120,10 @@ int32_t lsm6dsv_tap_thresholds_set(stmdev_ctx_t *ctx, ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); ret += lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); ret += lsm6dsv_read_reg(ctx, LSM6DSV_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } tap_cfg1.tap_ths_x = val.x; tap_cfg2.tap_ths_y = val.y; @@ -8525,7 +9144,7 @@ int32_t lsm6dsv_tap_thresholds_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_tap_thresholds_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_tap_thresholds_get(const stmdev_ctx_t *ctx, lsm6dsv_tap_thresholds_t *val) { lsm6dsv_tap_ths_6d_t tap_ths_6d; @@ -8536,7 +9155,10 @@ int32_t lsm6dsv_tap_thresholds_get(stmdev_ctx_t *ctx, ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); ret += lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); ret += lsm6dsv_read_reg(ctx, LSM6DSV_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->x = tap_cfg1.tap_ths_x; val->y = tap_cfg2.tap_ths_y; @@ -8553,7 +9175,7 @@ int32_t lsm6dsv_tap_thresholds_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_tap_axis_priority_set(const stmdev_ctx_t *ctx, lsm6dsv_tap_axis_priority_t val) { lsm6dsv_tap_cfg1_t tap_cfg1; @@ -8577,14 +9199,17 @@ int32_t lsm6dsv_tap_axis_priority_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_tap_axis_priority_get(const stmdev_ctx_t *ctx, lsm6dsv_tap_axis_priority_t *val) { lsm6dsv_tap_cfg1_t tap_cfg1; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (tap_cfg1.tap_priority) { @@ -8628,7 +9253,7 @@ int32_t lsm6dsv_tap_axis_priority_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_tap_time_windows_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_tap_time_windows_set(const stmdev_ctx_t *ctx, lsm6dsv_tap_time_windows_t val) { lsm6dsv_tap_dur_t tap_dur; @@ -8654,14 +9279,17 @@ int32_t lsm6dsv_tap_time_windows_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_tap_time_windows_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_tap_time_windows_get(const stmdev_ctx_t *ctx, lsm6dsv_tap_time_windows_t *val) { lsm6dsv_tap_dur_t tap_dur; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_DUR, (uint8_t *)&tap_dur, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->shock = tap_dur.shock; val->quiet = tap_dur.quiet; @@ -8678,7 +9306,7 @@ int32_t lsm6dsv_tap_time_windows_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_tap_mode_set(stmdev_ctx_t *ctx, lsm6dsv_tap_mode_t val) +int32_t lsm6dsv_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_tap_mode_t val) { lsm6dsv_wake_up_ths_t wake_up_ths; int32_t ret; @@ -8701,13 +9329,16 @@ int32_t lsm6dsv_tap_mode_set(stmdev_ctx_t *ctx, lsm6dsv_tap_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_tap_mode_get(stmdev_ctx_t *ctx, lsm6dsv_tap_mode_t *val) +int32_t lsm6dsv_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_tap_mode_t *val) { lsm6dsv_wake_up_ths_t wake_up_ths; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (wake_up_ths.single_double_tap) { @@ -8748,13 +9379,16 @@ int32_t lsm6dsv_tap_mode_get(stmdev_ctx_t *ctx, lsm6dsv_tap_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_emb_func_en_a_t emb_func_en_a; int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); emb_func_en_a.tilt_en = val; @@ -8773,13 +9407,16 @@ int32_t lsm6dsv_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_emb_func_en_a_t emb_func_en_a; int32_t ret; ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); *val = emb_func_en_a.tilt_en; @@ -8810,13 +9447,16 @@ int32_t lsm6dsv_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) +int32_t lsm6dsv_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) { uint8_t buff[4]; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_TIMESTAMP0, &buff[0], 4); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } *val = buff[3]; *val = (*val * 256U) + buff[2]; @@ -8834,7 +9474,7 @@ int32_t lsm6dsv_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm6dsv_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm6dsv_functions_enable_t functions_enable; int32_t ret; @@ -8857,7 +9497,7 @@ int32_t lsm6dsv_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm6dsv_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm6dsv_functions_enable_t functions_enable; int32_t ret; @@ -8889,7 +9529,7 @@ int32_t lsm6dsv_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_act_mode_set(stmdev_ctx_t *ctx, lsm6dsv_act_mode_t val) +int32_t lsm6dsv_act_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_act_mode_t val) { lsm6dsv_functions_enable_t functions_enable; int32_t ret; @@ -8912,13 +9552,16 @@ int32_t lsm6dsv_act_mode_set(stmdev_ctx_t *ctx, lsm6dsv_act_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_act_mode_get(stmdev_ctx_t *ctx, lsm6dsv_act_mode_t *val) +int32_t lsm6dsv_act_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_act_mode_t *val) { lsm6dsv_functions_enable_t functions_enable; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (functions_enable.inact_en) { @@ -8954,7 +9597,7 @@ int32_t lsm6dsv_act_mode_get(stmdev_ctx_t *ctx, lsm6dsv_act_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_act_from_sleep_to_act_dur_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_act_from_sleep_to_act_dur_set(const stmdev_ctx_t *ctx, lsm6dsv_act_from_sleep_to_act_dur_t val) { lsm6dsv_inactivity_dur_t inactivity_dur; @@ -8978,14 +9621,17 @@ int32_t lsm6dsv_act_from_sleep_to_act_dur_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_act_from_sleep_to_act_dur_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx, lsm6dsv_act_from_sleep_to_act_dur_t *val) { lsm6dsv_inactivity_dur_t inactivity_dur; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (inactivity_dur.inact_dur) { @@ -9021,7 +9667,7 @@ int32_t lsm6dsv_act_from_sleep_to_act_dur_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_act_sleep_xl_odr_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_act_sleep_xl_odr_set(const stmdev_ctx_t *ctx, lsm6dsv_act_sleep_xl_odr_t val) { lsm6dsv_inactivity_dur_t inactivity_dur; @@ -9045,14 +9691,17 @@ int32_t lsm6dsv_act_sleep_xl_odr_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_act_sleep_xl_odr_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx, lsm6dsv_act_sleep_xl_odr_t *val) { lsm6dsv_inactivity_dur_t inactivity_dur; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } switch (inactivity_dur.xl_inact_odr) { @@ -9088,7 +9737,7 @@ int32_t lsm6dsv_act_sleep_xl_odr_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_act_thresholds_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_act_thresholds_set(const stmdev_ctx_t *ctx, lsm6dsv_act_thresholds_t *val) { lsm6dsv_inactivity_ths_t inactivity_ths; @@ -9101,7 +9750,10 @@ int32_t lsm6dsv_act_thresholds_set(stmdev_ctx_t *ctx, ret += lsm6dsv_read_reg(ctx, LSM6DSV_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); ret += lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); ret += lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } inactivity_dur.wu_inact_ths_w = val->inactivity_cfg.wu_inact_ths_w; inactivity_dur.xl_inact_odr = val->inactivity_cfg.xl_inact_odr; @@ -9127,7 +9779,7 @@ int32_t lsm6dsv_act_thresholds_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_act_thresholds_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_act_thresholds_get(const stmdev_ctx_t *ctx, lsm6dsv_act_thresholds_t *val) { lsm6dsv_inactivity_dur_t inactivity_dur; @@ -9140,7 +9792,10 @@ int32_t lsm6dsv_act_thresholds_get(stmdev_ctx_t *ctx, ret += lsm6dsv_read_reg(ctx, LSM6DSV_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); ret += lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); ret += lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->inactivity_cfg.wu_inact_ths_w = inactivity_dur.wu_inact_ths_w; val->inactivity_cfg.xl_inact_odr = inactivity_dur.xl_inact_odr; @@ -9161,7 +9816,7 @@ int32_t lsm6dsv_act_thresholds_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_act_wkup_time_windows_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_act_wkup_time_windows_set(const stmdev_ctx_t *ctx, lsm6dsv_act_wkup_time_windows_t val) { lsm6dsv_wake_up_dur_t wake_up_dur; @@ -9186,14 +9841,17 @@ int32_t lsm6dsv_act_wkup_time_windows_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t lsm6dsv_act_wkup_time_windows_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, lsm6dsv_act_wkup_time_windows_t *val) { lsm6dsv_wake_up_dur_t wake_up_dur; int32_t ret; ret = lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); - if (ret != 0) { return ret; } + if (ret != 0) + { + return ret; + } val->shock = wake_up_dur.wake_dur; val->quiet = wake_up_dur.sleep_dur; diff --git a/sensor/stmemsc/lsm6dsv_STdC/driver/lsm6dsv_reg.h b/sensor/stmemsc/lsm6dsv_STdC/driver/lsm6dsv_reg.h index 8359f815..7c0eda4f 100644 --- a/sensor/stmemsc/lsm6dsv_STdC/driver/lsm6dsv_reg.h +++ b/sensor/stmemsc/lsm6dsv_STdC/driver/lsm6dsv_reg.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2022 STMicroelectronics. + *

© Copyright (c) 2024 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -2941,11 +2941,6 @@ typedef struct #endif /* DRV_BYTE_ORDER */ } lsm6dsv_pedo_sc_deltat_h_t; -/** - * @} - * - */ - /** @defgroup bitfields page pg2_emb_adv * @{ * @@ -3667,10 +3662,10 @@ typedef union * them with a custom implementation. */ -int32_t lsm6dsv_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm6dsv_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lsm6dsv_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm6dsv_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -3691,8 +3686,8 @@ float_t lsm6dsv_from_lsb_to_celsius(int16_t lsb); float_t lsm6dsv_from_lsb_to_nsec(uint32_t lsb); -int32_t lsm6dsv_xl_offset_on_out_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_xl_offset_on_out_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_xl_offset_on_out_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -3700,9 +3695,9 @@ typedef struct float_t y_mg; float_t x_mg; } lsm6dsv_xl_offset_mg_t; -int32_t lsm6dsv_xl_offset_mg_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_xl_offset_mg_set(const stmdev_ctx_t *ctx, lsm6dsv_xl_offset_mg_t val); -int32_t lsm6dsv_xl_offset_mg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_xl_offset_mg_get(const stmdev_ctx_t *ctx, lsm6dsv_xl_offset_mg_t *val); typedef enum @@ -3712,8 +3707,8 @@ typedef enum LSM6DSV_RESTORE_CAL_PARAM = 0x2, LSM6DSV_RESTORE_CTRL_REGS = 0x4, } lsm6dsv_reset_t; -int32_t lsm6dsv_reset_set(stmdev_ctx_t *ctx, lsm6dsv_reset_t val); -int32_t lsm6dsv_reset_get(stmdev_ctx_t *ctx, lsm6dsv_reset_t *val); +int32_t lsm6dsv_reset_set(const stmdev_ctx_t *ctx, lsm6dsv_reset_t val); +int32_t lsm6dsv_reset_get(const stmdev_ctx_t *ctx, lsm6dsv_reset_t *val); typedef enum { @@ -3721,10 +3716,10 @@ typedef enum LSM6DSV_EMBED_FUNC_MEM_BANK = 0x1, LSM6DSV_SENSOR_HUB_MEM_BANK = 0x2, } lsm6dsv_mem_bank_t; -int32_t lsm6dsv_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsv_mem_bank_t val); -int32_t lsm6dsv_mem_bank_get(stmdev_ctx_t *ctx, lsm6dsv_mem_bank_t *val); +int32_t lsm6dsv_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dsv_mem_bank_t val); +int32_t lsm6dsv_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dsv_mem_bank_t *val); -int32_t lsm6dsv_device_id_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3762,13 +3757,13 @@ typedef enum LSM6DSV_ODR_HA02_AT_3200Hz = 0x2B, LSM6DSV_ODR_HA02_AT_6400Hz = 0x2C, } lsm6dsv_data_rate_t; -int32_t lsm6dsv_xl_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_xl_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv_data_rate_t val); -int32_t lsm6dsv_xl_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_xl_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv_data_rate_t *val); -int32_t lsm6dsv_gy_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_gy_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv_data_rate_t val); -int32_t lsm6dsv_gy_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_gy_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv_data_rate_t *val); @@ -3782,8 +3777,8 @@ typedef enum LSM6DSV_XL_LOW_POWER_8_AVG_MD = 0x6, LSM6DSV_XL_NORMAL_MD = 0x7, } lsm6dsv_xl_mode_t; -int32_t lsm6dsv_xl_mode_set(stmdev_ctx_t *ctx, lsm6dsv_xl_mode_t val); -int32_t lsm6dsv_xl_mode_get(stmdev_ctx_t *ctx, lsm6dsv_xl_mode_t *val); +int32_t lsm6dsv_xl_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_xl_mode_t val); +int32_t lsm6dsv_xl_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_xl_mode_t *val); typedef enum { @@ -3792,26 +3787,26 @@ typedef enum LSM6DSV_GY_SLEEP_MD = 0x4, LSM6DSV_GY_LOW_POWER_MD = 0x5, } lsm6dsv_gy_mode_t; -int32_t lsm6dsv_gy_mode_set(stmdev_ctx_t *ctx, lsm6dsv_gy_mode_t val); -int32_t lsm6dsv_gy_mode_get(stmdev_ctx_t *ctx, lsm6dsv_gy_mode_t *val); +int32_t lsm6dsv_gy_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_gy_mode_t val); +int32_t lsm6dsv_gy_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_gy_mode_t *val); -int32_t lsm6dsv_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv_odr_trig_cfg_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_odr_trig_cfg_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_odr_trig_cfg_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_odr_trig_cfg_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSV_DRDY_LATCHED = 0x0, LSM6DSV_DRDY_PULSED = 0x1, } lsm6dsv_data_ready_mode_t; -int32_t lsm6dsv_data_ready_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_data_ready_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_data_ready_mode_t val); -int32_t lsm6dsv_data_ready_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_data_ready_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_data_ready_mode_t *val); typedef struct @@ -3819,9 +3814,9 @@ typedef struct uint8_t enable : 1; /* interrupt enable */ uint8_t lir : 1; /* interrupt pulsed or latched */ } lsm6dsv_interrupt_mode_t; -int32_t lsm6dsv_interrupt_enable_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_interrupt_enable_set(const stmdev_ctx_t *ctx, lsm6dsv_interrupt_mode_t val); -int32_t lsm6dsv_interrupt_enable_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_interrupt_enable_get(const stmdev_ctx_t *ctx, lsm6dsv_interrupt_mode_t *val); typedef enum @@ -3833,9 +3828,9 @@ typedef enum LSM6DSV_2000dps = 0x4, LSM6DSV_4000dps = 0xc, } lsm6dsv_gy_full_scale_t; -int32_t lsm6dsv_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsv_gy_full_scale_t val); -int32_t lsm6dsv_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsv_gy_full_scale_t *val); typedef enum @@ -3845,13 +3840,13 @@ typedef enum LSM6DSV_8g = 0x2, LSM6DSV_16g = 0x3, } lsm6dsv_xl_full_scale_t; -int32_t lsm6dsv_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsv_xl_full_scale_t val); -int32_t lsm6dsv_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsv_xl_full_scale_t *val); -int32_t lsm6dsv_xl_dual_channel_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_xl_dual_channel_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_xl_dual_channel_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -3859,9 +3854,9 @@ typedef enum LSM6DSV_XL_ST_POSITIVE = 0x1, LSM6DSV_XL_ST_NEGATIVE = 0x2, } lsm6dsv_xl_self_test_t; -int32_t lsm6dsv_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dsv_xl_self_test_t val); -int32_t lsm6dsv_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dsv_xl_self_test_t *val); typedef enum @@ -3870,9 +3865,9 @@ typedef enum LSM6DSV_OIS_XL_ST_POSITIVE = 0x1, LSM6DSV_OIS_XL_ST_NEGATIVE = 0x2, } lsm6dsv_ois_xl_self_test_t; -int32_t lsm6dsv_ois_xl_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_xl_self_test_set(const stmdev_ctx_t *ctx, lsm6dsv_ois_xl_self_test_t val); -int32_t lsm6dsv_ois_xl_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_xl_self_test_get(const stmdev_ctx_t *ctx, lsm6dsv_ois_xl_self_test_t *val); typedef enum @@ -3882,9 +3877,9 @@ typedef enum LSM6DSV_GY_ST_NEGATIVE = 0x2, } lsm6dsv_gy_self_test_t; -int32_t lsm6dsv_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dsv_gy_self_test_t val); -int32_t lsm6dsv_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dsv_gy_self_test_t *val); typedef enum @@ -3896,9 +3891,9 @@ typedef enum LSM6DSV_OIS_GY_ST_CLAMP_NEG = 0x6, } lsm6dsv_ois_gy_self_test_t; -int32_t lsm6dsv_ois_gy_self_test_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_gy_self_test_set(const stmdev_ctx_t *ctx, lsm6dsv_ois_gy_self_test_t val); -int32_t lsm6dsv_ois_gy_self_test_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_gy_self_test_get(const stmdev_ctx_t *ctx, lsm6dsv_ois_gy_self_test_t *val); typedef struct @@ -3958,7 +3953,7 @@ typedef struct uint8_t fifo_ovr : 1; uint8_t fifo_th : 1; } lsm6dsv_all_sources_t; -int32_t lsm6dsv_all_sources_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_all_sources_get(const stmdev_ctx_t *ctx, lsm6dsv_all_sources_t *val); typedef struct @@ -3966,6 +3961,7 @@ typedef struct uint8_t drdy_xl : 1; uint8_t drdy_g : 1; uint8_t drdy_g_eis : 1; + uint8_t drdy_temp : 1; uint8_t fifo_th : 1; uint8_t fifo_ovr : 1; uint8_t fifo_full : 1; @@ -3981,13 +3977,13 @@ typedef struct uint8_t freefall : 1; uint8_t sleep_change : 1; } lsm6dsv_pin_int_route_t; -int32_t lsm6dsv_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm6dsv_pin_int_route_t *val); -int32_t lsm6dsv_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm6dsv_pin_int_route_t *val); -int32_t lsm6dsv_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm6dsv_pin_int_route_t *val); -int32_t lsm6dsv_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_pin_int2_route_get(const stmdev_ctx_t *ctx, lsm6dsv_pin_int_route_t *val); typedef struct @@ -3996,46 +3992,46 @@ typedef struct uint8_t drdy_gy : 1; uint8_t drdy_temp : 1; } lsm6dsv_data_ready_t; -int32_t lsm6dsv_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_flag_data_ready_get(const stmdev_ctx_t *ctx, lsm6dsv_data_ready_t *val); -int32_t lsm6dsv_int_ack_mask_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_int_ack_mask_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_int_ack_mask_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_int_ack_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsv_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsv_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsv_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsv_ois_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsv_ois_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsv_ois_eis_angular_rate_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_eis_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsv_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsv_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsv_dual_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm6dsv_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsv_ois_dual_acceleration_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm6dsv_odr_cal_reg_get(stmdev_ctx_t *ctx, int8_t *val); +int32_t lsm6dsv_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val); -int32_t lsm6dsv_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, +int32_t lsm6dsv_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); -int32_t lsm6dsv_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, +int32_t lsm6dsv_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, uint8_t len); -int32_t lsm6dsv_emb_function_dbg_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_emb_function_dbg_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_emb_function_dbg_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_emb_function_dbg_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSV_DEN_ACT_LOW = 0x0, LSM6DSV_DEN_ACT_HIGH = 0x1, } lsm6dsv_den_polarity_t; -int32_t lsm6dsv_den_polarity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_den_polarity_set(const stmdev_ctx_t *ctx, lsm6dsv_den_polarity_t val); -int32_t lsm6dsv_den_polarity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_den_polarity_get(const stmdev_ctx_t *ctx, lsm6dsv_den_polarity_t *val); typedef struct @@ -4052,8 +4048,8 @@ typedef struct LSM6DSV_LEVEL_LATCHED = 0x03, } mode; } lsm6dsv_den_conf_t; -int32_t lsm6dsv_den_conf_set(stmdev_ctx_t *ctx, lsm6dsv_den_conf_t val); -int32_t lsm6dsv_den_conf_get(stmdev_ctx_t *ctx, lsm6dsv_den_conf_t *val); +int32_t lsm6dsv_den_conf_set(const stmdev_ctx_t *ctx, lsm6dsv_den_conf_t val); +int32_t lsm6dsv_den_conf_get(const stmdev_ctx_t *ctx, lsm6dsv_den_conf_t *val); typedef enum { @@ -4063,13 +4059,13 @@ typedef enum LSM6DSV_EIS_1000dps = 0x3, LSM6DSV_EIS_2000dps = 0x4, } lsm6dsv_eis_gy_full_scale_t; -int32_t lsm6dsv_eis_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_eis_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsv_eis_gy_full_scale_t val); -int32_t lsm6dsv_eis_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_eis_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsv_eis_gy_full_scale_t *val); -int32_t lsm6dsv_eis_gy_on_spi2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_eis_gy_on_spi2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_eis_gy_on_spi2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_eis_gy_on_spi2_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -4077,16 +4073,16 @@ typedef enum LSM6DSV_EIS_1920Hz = 0x1, LSM6DSV_EIS_960Hz = 0x2, } lsm6dsv_gy_eis_data_rate_t; -int32_t lsm6dsv_gy_eis_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_gy_eis_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv_gy_eis_data_rate_t val); -int32_t lsm6dsv_gy_eis_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_gy_eis_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv_gy_eis_data_rate_t *val); -int32_t lsm6dsv_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv_fifo_xl_dual_fsm_batch_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_fifo_xl_dual_fsm_batch_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -4095,23 +4091,23 @@ typedef enum LSM6DSV_CMP_16_TO_1 = 0x2, LSM6DSV_CMP_32_TO_1 = 0x3, } lsm6dsv_fifo_compress_algo_t; -int32_t lsm6dsv_fifo_compress_algo_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_compress_algo_set(const stmdev_ctx_t *ctx, lsm6dsv_fifo_compress_algo_t val); -int32_t lsm6dsv_fifo_compress_algo_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_compress_algo_get(const stmdev_ctx_t *ctx, lsm6dsv_fifo_compress_algo_t *val); -int32_t lsm6dsv_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv_fifo_compress_algo_real_time_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_fifo_compress_algo_real_time_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -4129,9 +4125,9 @@ typedef enum LSM6DSV_XL_BATCHED_AT_3840Hz = 0xb, LSM6DSV_XL_BATCHED_AT_7680Hz = 0xc, } lsm6dsv_fifo_xl_batch_t; -int32_t lsm6dsv_fifo_xl_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_xl_batch_set(const stmdev_ctx_t *ctx, lsm6dsv_fifo_xl_batch_t val); -int32_t lsm6dsv_fifo_xl_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_xl_batch_get(const stmdev_ctx_t *ctx, lsm6dsv_fifo_xl_batch_t *val); typedef enum @@ -4150,9 +4146,9 @@ typedef enum LSM6DSV_GY_BATCHED_AT_3840Hz = 0xb, LSM6DSV_GY_BATCHED_AT_7680Hz = 0xc, } lsm6dsv_fifo_gy_batch_t; -int32_t lsm6dsv_fifo_gy_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_gy_batch_set(const stmdev_ctx_t *ctx, lsm6dsv_fifo_gy_batch_t val); -int32_t lsm6dsv_fifo_gy_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_gy_batch_get(const stmdev_ctx_t *ctx, lsm6dsv_fifo_gy_batch_t *val); typedef enum @@ -4165,12 +4161,12 @@ typedef enum LSM6DSV_STREAM_MODE = 0x6, LSM6DSV_BYPASS_TO_FIFO_MODE = 0x7, } lsm6dsv_fifo_mode_t; -int32_t lsm6dsv_fifo_mode_set(stmdev_ctx_t *ctx, lsm6dsv_fifo_mode_t val); -int32_t lsm6dsv_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_fifo_mode_t val); +int32_t lsm6dsv_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_fifo_mode_t *val); -int32_t lsm6dsv_fifo_gy_eis_batch_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_fifo_gy_eis_batch_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_fifo_gy_eis_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_fifo_gy_eis_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -4179,9 +4175,9 @@ typedef enum LSM6DSV_TEMP_BATCHED_AT_15Hz = 0x2, LSM6DSV_TEMP_BATCHED_AT_60Hz = 0x3, } lsm6dsv_fifo_temp_batch_t; -int32_t lsm6dsv_fifo_temp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_temp_batch_set(const stmdev_ctx_t *ctx, lsm6dsv_fifo_temp_batch_t val); -int32_t lsm6dsv_fifo_temp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_temp_batch_get(const stmdev_ctx_t *ctx, lsm6dsv_fifo_temp_batch_t *val); typedef enum @@ -4191,14 +4187,14 @@ typedef enum LSM6DSV_TMSTMP_DEC_8 = 0x2, LSM6DSV_TMSTMP_DEC_32 = 0x3, } lsm6dsv_fifo_timestamp_batch_t; -int32_t lsm6dsv_fifo_timestamp_batch_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx, lsm6dsv_fifo_timestamp_batch_t val); -int32_t lsm6dsv_fifo_timestamp_batch_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, lsm6dsv_fifo_timestamp_batch_t *val); -int32_t lsm6dsv_fifo_batch_counter_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsv_fifo_batch_counter_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum @@ -4207,9 +4203,9 @@ typedef enum LSM6DSV_GY_BATCH_EVENT = 0x1, LSM6DSV_GY_EIS_BATCH_EVENT = 0x2, } lsm6dsv_fifo_batch_cnt_event_t; -int32_t lsm6dsv_fifo_batch_cnt_event_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_batch_cnt_event_set(const stmdev_ctx_t *ctx, lsm6dsv_fifo_batch_cnt_event_t val); -int32_t lsm6dsv_fifo_batch_cnt_event_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx, lsm6dsv_fifo_batch_cnt_event_t *val); typedef struct @@ -4221,7 +4217,7 @@ typedef struct uint8_t fifo_th : 1; } lsm6dsv_fifo_status_t; -int32_t lsm6dsv_fifo_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_status_get(const stmdev_ctx_t *ctx, lsm6dsv_fifo_status_t *val); typedef struct @@ -4257,14 +4253,14 @@ typedef struct uint8_t cnt; uint8_t data[6]; } lsm6dsv_fifo_out_raw_t; -int32_t lsm6dsv_fifo_out_raw_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fifo_out_raw_get(const stmdev_ctx_t *ctx, lsm6dsv_fifo_out_raw_t *val); -int32_t lsm6dsv_fifo_stpcnt_batch_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_fifo_stpcnt_batch_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv_fifo_sh_batch_slave_set(stmdev_ctx_t *ctx, uint8_t idx, uint8_t val); -int32_t lsm6dsv_fifo_sh_batch_slave_get(stmdev_ctx_t *ctx, uint8_t idx, uint8_t *val); +int32_t lsm6dsv_fifo_sh_batch_slave_set(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t val); +int32_t lsm6dsv_fifo_sh_batch_slave_get(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t *val); typedef struct { @@ -4272,19 +4268,19 @@ typedef struct uint8_t gravity : 1; uint8_t gbias : 1; } lsm6dsv_fifo_sflp_raw_t; -int32_t lsm6dsv_fifo_sflp_batch_set(stmdev_ctx_t *ctx, - lsm6dsv_fifo_sflp_raw_t val); -int32_t lsm6dsv_fifo_sflp_batch_get(stmdev_ctx_t *ctx, - lsm6dsv_fifo_sflp_raw_t *val); +int32_t lsm6dsv_fifo_sflp_batch_set(const stmdev_ctx_t *ctx, + lsm6dsv_fifo_sflp_raw_t val); +int32_t lsm6dsv_fifo_sflp_batch_get(const stmdev_ctx_t *ctx, + lsm6dsv_fifo_sflp_raw_t *val); typedef enum { LSM6DSV_AUTO = 0x0, LSM6DSV_ALWAYS_ACTIVE = 0x1, } lsm6dsv_filt_anti_spike_t; -int32_t lsm6dsv_filt_anti_spike_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_anti_spike_set(const stmdev_ctx_t *ctx, lsm6dsv_filt_anti_spike_t val); -int32_t lsm6dsv_filt_anti_spike_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_anti_spike_get(const stmdev_ctx_t *ctx, lsm6dsv_filt_anti_spike_t *val); typedef struct @@ -4294,18 +4290,18 @@ typedef struct uint8_t irq_xl : 1; uint8_t irq_g : 1; } lsm6dsv_filt_settling_mask_t; -int32_t lsm6dsv_filt_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_settling_mask_set(const stmdev_ctx_t *ctx, lsm6dsv_filt_settling_mask_t val); -int32_t lsm6dsv_filt_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_settling_mask_get(const stmdev_ctx_t *ctx, lsm6dsv_filt_settling_mask_t *val); typedef struct { uint8_t ois_drdy : 1; } lsm6dsv_filt_ois_settling_mask_t; -int32_t lsm6dsv_filt_ois_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_ois_settling_mask_set(const stmdev_ctx_t *ctx, lsm6dsv_filt_ois_settling_mask_t val); -int32_t lsm6dsv_filt_ois_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_ois_settling_mask_get(const stmdev_ctx_t *ctx, lsm6dsv_filt_ois_settling_mask_t *val); typedef enum @@ -4319,13 +4315,13 @@ typedef enum LSM6DSV_GY_AGGRESSIVE = 0x6, LSM6DSV_GY_XTREME = 0x7, } lsm6dsv_filt_gy_lp1_bandwidth_t; -int32_t lsm6dsv_filt_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsv_filt_gy_lp1_bandwidth_t val); -int32_t lsm6dsv_filt_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsv_filt_gy_lp1_bandwidth_t *val); -int32_t lsm6dsv_filt_gy_lp1_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_filt_gy_lp1_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_filt_gy_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -4338,28 +4334,28 @@ typedef enum LSM6DSV_XL_AGGRESSIVE = 0x6, LSM6DSV_XL_XTREME = 0x7, } lsm6dsv_filt_xl_lp2_bandwidth_t; -int32_t lsm6dsv_filt_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsv_filt_xl_lp2_bandwidth_t val); -int32_t lsm6dsv_filt_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsv_filt_xl_lp2_bandwidth_t *val); -int32_t lsm6dsv_filt_xl_lp2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_filt_xl_lp2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_filt_xl_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv_filt_xl_hp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_filt_xl_hp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_filt_xl_hp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv_filt_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_filt_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_filt_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSV_HP_MD_NORMAL = 0x0, LSM6DSV_HP_MD_REFERENCE = 0x1, } lsm6dsv_filt_xl_hp_mode_t; -int32_t lsm6dsv_filt_xl_hp_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_xl_hp_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_filt_xl_hp_mode_t val); -int32_t lsm6dsv_filt_xl_hp_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_filt_xl_hp_mode_t *val); typedef enum @@ -4368,22 +4364,22 @@ typedef enum LSM6DSV_WK_FEED_HIGH_PASS = 0x1, LSM6DSV_WK_FEED_LP_WITH_OFFSET = 0x2, } lsm6dsv_filt_wkup_act_feed_t; -int32_t lsm6dsv_filt_wkup_act_feed_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx, lsm6dsv_filt_wkup_act_feed_t val); -int32_t lsm6dsv_filt_wkup_act_feed_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx, lsm6dsv_filt_wkup_act_feed_t *val); -int32_t lsm6dsv_mask_trigger_xl_settl_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_mask_trigger_xl_settl_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_mask_trigger_xl_settl_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSV_SIXD_FEED_ODR_DIV_2 = 0x0, LSM6DSV_SIXD_FEED_LOW_PASS = 0x1, } lsm6dsv_filt_sixd_feed_t; -int32_t lsm6dsv_filt_sixd_feed_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_sixd_feed_set(const stmdev_ctx_t *ctx, lsm6dsv_filt_sixd_feed_t val); -int32_t lsm6dsv_filt_sixd_feed_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_sixd_feed_get(const stmdev_ctx_t *ctx, lsm6dsv_filt_sixd_feed_t *val); typedef enum @@ -4391,9 +4387,9 @@ typedef enum LSM6DSV_EIS_LP_NORMAL = 0x0, LSM6DSV_EIS_LP_LIGHT = 0x1, } lsm6dsv_filt_gy_eis_lp_bandwidth_t; -int32_t lsm6dsv_filt_gy_eis_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_gy_eis_lp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsv_filt_gy_eis_lp_bandwidth_t val); -int32_t lsm6dsv_filt_gy_eis_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_gy_eis_lp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsv_filt_gy_eis_lp_bandwidth_t *val); typedef enum @@ -4403,9 +4399,9 @@ typedef enum LSM6DSV_OIS_GY_LP_AGGRESSIVE = 0x2, LSM6DSV_OIS_GY_LP_LIGHT = 0x3, } lsm6dsv_filt_gy_ois_lp_bandwidth_t; -int32_t lsm6dsv_filt_gy_ois_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_gy_ois_lp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsv_filt_gy_ois_lp_bandwidth_t val); -int32_t lsm6dsv_filt_gy_ois_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_gy_ois_lp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsv_filt_gy_ois_lp_bandwidth_t *val); typedef enum @@ -4419,9 +4415,9 @@ typedef enum LSM6DSV_OIS_XL_LP_AGGRESSIVE = 0x6, LSM6DSV_OIS_XL_LP_XTREME = 0x7, } lsm6dsv_filt_xl_ois_lp_bandwidth_t; -int32_t lsm6dsv_filt_xl_ois_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_xl_ois_lp_bandwidth_set(const stmdev_ctx_t *ctx, lsm6dsv_filt_xl_ois_lp_bandwidth_t val); -int32_t lsm6dsv_filt_xl_ois_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_filt_xl_ois_lp_bandwidth_get(const stmdev_ctx_t *ctx, lsm6dsv_filt_xl_ois_lp_bandwidth_t *val); typedef enum @@ -4429,11 +4425,11 @@ typedef enum LSM6DSV_PROTECT_CTRL_REGS = 0x0, LSM6DSV_WRITE_CTRL_REG = 0x1, } lsm6dsv_fsm_permission_t; -int32_t lsm6dsv_fsm_permission_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_permission_set(const stmdev_ctx_t *ctx, lsm6dsv_fsm_permission_t val); -int32_t lsm6dsv_fsm_permission_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_permission_get(const stmdev_ctx_t *ctx, lsm6dsv_fsm_permission_t *val); -int32_t lsm6dsv_fsm_permission_status(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_fsm_permission_status(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -4446,11 +4442,11 @@ typedef struct uint8_t fsm7_en : 1; uint8_t fsm8_en : 1; } lsm6dsv_fsm_mode_t; -int32_t lsm6dsv_fsm_mode_set(stmdev_ctx_t *ctx, lsm6dsv_fsm_mode_t val); -int32_t lsm6dsv_fsm_mode_get(stmdev_ctx_t *ctx, lsm6dsv_fsm_mode_t *val); +int32_t lsm6dsv_fsm_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_fsm_mode_t val); +int32_t lsm6dsv_fsm_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_fsm_mode_t *val); -int32_t lsm6dsv_fsm_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsv_fsm_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsv_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef struct @@ -4464,7 +4460,7 @@ typedef struct uint8_t fsm_outs7; uint8_t fsm_outs8; } lsm6dsv_fsm_out_t; -int32_t lsm6dsv_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsv_fsm_out_t *val); +int32_t lsm6dsv_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dsv_fsm_out_t *val); typedef enum { @@ -4476,14 +4472,14 @@ typedef enum LSM6DSV_FSM_480Hz = 0x5, LSM6DSV_FSM_960Hz = 0x6, } lsm6dsv_fsm_data_rate_t; -int32_t lsm6dsv_fsm_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv_fsm_data_rate_t val); -int32_t lsm6dsv_fsm_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv_fsm_data_rate_t *val); -int32_t lsm6dsv_fsm_ext_sens_sensitivity_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_ext_sens_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsv_fsm_ext_sens_sensitivity_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_ext_sens_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef struct @@ -4492,9 +4488,9 @@ typedef struct uint16_t y; uint16_t x; } lsm6dsv_xl_fsm_ext_sens_offset_t; -int32_t lsm6dsv_fsm_ext_sens_offset_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_ext_sens_offset_set(const stmdev_ctx_t *ctx, lsm6dsv_xl_fsm_ext_sens_offset_t val); -int32_t lsm6dsv_fsm_ext_sens_offset_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_ext_sens_offset_get(const stmdev_ctx_t *ctx, lsm6dsv_xl_fsm_ext_sens_offset_t *val); typedef struct @@ -4506,9 +4502,9 @@ typedef struct uint16_t yz; uint16_t zz; } lsm6dsv_xl_fsm_ext_sens_matrix_t; -int32_t lsm6dsv_fsm_ext_sens_matrix_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_ext_sens_matrix_set(const stmdev_ctx_t *ctx, lsm6dsv_xl_fsm_ext_sens_matrix_t val); -int32_t lsm6dsv_fsm_ext_sens_matrix_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_ext_sens_matrix_get(const stmdev_ctx_t *ctx, lsm6dsv_xl_fsm_ext_sens_matrix_t *val); typedef enum @@ -4520,9 +4516,9 @@ typedef enum LSM6DSV_Z_EQ_MIN_Z = 0x4, LSM6DSV_Z_EQ_Z = 0x5, } lsm6dsv_fsm_ext_sens_z_orient_t; -int32_t lsm6dsv_fsm_ext_sens_z_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_ext_sens_z_orient_set(const stmdev_ctx_t *ctx, lsm6dsv_fsm_ext_sens_z_orient_t val); -int32_t lsm6dsv_fsm_ext_sens_z_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_ext_sens_z_orient_get(const stmdev_ctx_t *ctx, lsm6dsv_fsm_ext_sens_z_orient_t *val); typedef enum @@ -4534,9 +4530,9 @@ typedef enum LSM6DSV_Y_EQ_MIN_Z = 0x4, LSM6DSV_Y_EQ_Z = 0x5, } lsm6dsv_fsm_ext_sens_y_orient_t; -int32_t lsm6dsv_fsm_ext_sens_y_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_ext_sens_y_orient_set(const stmdev_ctx_t *ctx, lsm6dsv_fsm_ext_sens_y_orient_t val); -int32_t lsm6dsv_fsm_ext_sens_y_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_ext_sens_y_orient_get(const stmdev_ctx_t *ctx, lsm6dsv_fsm_ext_sens_y_orient_t *val); typedef enum @@ -4548,22 +4544,22 @@ typedef enum LSM6DSV_X_EQ_MIN_Z = 0x4, LSM6DSV_X_EQ_Z = 0x5, } lsm6dsv_fsm_ext_sens_x_orient_t; -int32_t lsm6dsv_fsm_ext_sens_x_orient_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_ext_sens_x_orient_set(const stmdev_ctx_t *ctx, lsm6dsv_fsm_ext_sens_x_orient_t val); -int32_t lsm6dsv_fsm_ext_sens_x_orient_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_fsm_ext_sens_x_orient_get(const stmdev_ctx_t *ctx, lsm6dsv_fsm_ext_sens_x_orient_t *val); -int32_t lsm6dsv_fsm_long_cnt_timeout_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsv_fsm_long_cnt_timeout_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsv_fsm_long_cnt_timeout_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsv_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsv_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsv_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsv_ff_time_windows_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_ff_time_windows_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -4576,9 +4572,9 @@ typedef enum LSM6DSV_469_mg = 0x6, LSM6DSV_500_mg = 0x7, } lsm6dsv_ff_thresholds_t; -int32_t lsm6dsv_ff_thresholds_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ff_thresholds_set(const stmdev_ctx_t *ctx, lsm6dsv_ff_thresholds_t val); -int32_t lsm6dsv_ff_thresholds_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ff_thresholds_get(const stmdev_ctx_t *ctx, lsm6dsv_ff_thresholds_t *val); typedef enum @@ -4586,44 +4582,44 @@ typedef enum LSM6DSV_OIS_CTRL_FROM_OIS = 0x0, LSM6DSV_OIS_CTRL_FROM_UI = 0x1, } lsm6dsv_ois_ctrl_mode_t; -int32_t lsm6dsv_ois_ctrl_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_ctrl_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_ois_ctrl_mode_t val); -int32_t lsm6dsv_ois_ctrl_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_ctrl_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_ois_ctrl_mode_t *val); -int32_t lsm6dsv_ois_reset_set(stmdev_ctx_t *ctx, int8_t val); -int32_t lsm6dsv_ois_reset_get(stmdev_ctx_t *ctx, int8_t *val); +int32_t lsm6dsv_ois_reset_set(const stmdev_ctx_t *ctx, int8_t val); +int32_t lsm6dsv_ois_reset_get(const stmdev_ctx_t *ctx, int8_t *val); -int32_t lsm6dsv_ois_interface_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_ois_interface_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_ois_interface_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_ois_interface_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { uint8_t ack : 1; uint8_t req : 1; } lsm6dsv_ois_handshake_t; -int32_t lsm6dsv_ois_handshake_from_ui_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_handshake_from_ui_set(const stmdev_ctx_t *ctx, lsm6dsv_ois_handshake_t val); -int32_t lsm6dsv_ois_handshake_from_ui_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_handshake_from_ui_get(const stmdev_ctx_t *ctx, lsm6dsv_ois_handshake_t *val); -int32_t lsm6dsv_ois_handshake_from_ois_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_handshake_from_ois_set(const stmdev_ctx_t *ctx, lsm6dsv_ois_handshake_t val); -int32_t lsm6dsv_ois_handshake_from_ois_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_handshake_from_ois_get(const stmdev_ctx_t *ctx, lsm6dsv_ois_handshake_t *val); -int32_t lsm6dsv_ois_shared_set(stmdev_ctx_t *ctx, uint8_t val[6]); -int32_t lsm6dsv_ois_shared_get(stmdev_ctx_t *ctx, uint8_t val[6]); +int32_t lsm6dsv_ois_shared_set(const stmdev_ctx_t *ctx, uint8_t val[6]); +int32_t lsm6dsv_ois_shared_get(const stmdev_ctx_t *ctx, uint8_t val[6]); -int32_t lsm6dsv_ois_on_spi2_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_ois_on_spi2_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_ois_on_spi2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_ois_on_spi2_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { uint8_t gy : 1; uint8_t xl : 1; } lsm6dsv_ois_chain_t; -int32_t lsm6dsv_ois_chain_set(stmdev_ctx_t *ctx, lsm6dsv_ois_chain_t val); -int32_t lsm6dsv_ois_chain_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_chain_set(const stmdev_ctx_t *ctx, lsm6dsv_ois_chain_t val); +int32_t lsm6dsv_ois_chain_get(const stmdev_ctx_t *ctx, lsm6dsv_ois_chain_t *val); typedef enum @@ -4634,9 +4630,9 @@ typedef enum LSM6DSV_OIS_1000dps = 0x3, LSM6DSV_OIS_2000dps = 0x4, } lsm6dsv_ois_gy_full_scale_t; -int32_t lsm6dsv_ois_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsv_ois_gy_full_scale_t val); -int32_t lsm6dsv_ois_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsv_ois_gy_full_scale_t *val); typedef enum @@ -4646,9 +4642,9 @@ typedef enum LSM6DSV_OIS_8g = 0x2, LSM6DSV_OIS_16g = 0x3, } lsm6dsv_ois_xl_full_scale_t; -int32_t lsm6dsv_ois_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm6dsv_ois_xl_full_scale_t val); -int32_t lsm6dsv_ois_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ois_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm6dsv_ois_xl_full_scale_t *val); typedef enum @@ -4658,24 +4654,27 @@ typedef enum LSM6DSV_DEG_60 = 0x2, LSM6DSV_DEG_50 = 0x3, } lsm6dsv_6d_threshold_t; -int32_t lsm6dsv_6d_threshold_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_6d_threshold_set(const stmdev_ctx_t *ctx, lsm6dsv_6d_threshold_t val); -int32_t lsm6dsv_6d_threshold_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_6d_threshold_get(const stmdev_ctx_t *ctx, lsm6dsv_6d_threshold_t *val); -int32_t lsm6dsv_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSV_SW_RST_DYN_ADDRESS_RST = 0x0, LSM6DSV_I3C_GLOBAL_RST = 0x1, } lsm6dsv_i3c_reset_mode_t; -int32_t lsm6dsv_i3c_reset_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_i3c_reset_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_i3c_reset_mode_t val); -int32_t lsm6dsv_i3c_reset_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_i3c_reset_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_i3c_reset_mode_t *val); +int32_t lsm6dsv_i3c_int_en_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_i3c_int_en_get(const stmdev_ctx_t *ctx, uint8_t *val); + typedef enum { LSM6DSV_IBI_2us = 0x0, @@ -4683,17 +4682,17 @@ typedef enum LSM6DSV_IBI_1ms = 0x2, LSM6DSV_IBI_25ms = 0x3, } lsm6dsv_i3c_ibi_time_t; -int32_t lsm6dsv_i3c_ibi_time_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_i3c_ibi_time_set(const stmdev_ctx_t *ctx, lsm6dsv_i3c_ibi_time_t val); -int32_t lsm6dsv_i3c_ibi_time_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_i3c_ibi_time_get(const stmdev_ctx_t *ctx, lsm6dsv_i3c_ibi_time_t *val); -int32_t lsm6dsv_sh_master_interface_pull_up_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_sh_master_interface_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_sh_master_interface_pull_up_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_sh_master_interface_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val, +int32_t lsm6dsv_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, uint8_t len); typedef enum @@ -4703,25 +4702,25 @@ typedef enum LSM6DSV_SLV_0_1_2 = 0x2, LSM6DSV_SLV_0_1_2_3 = 0x3, } lsm6dsv_sh_slave_connected_t; -int32_t lsm6dsv_sh_slave_connected_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_sh_slave_connected_set(const stmdev_ctx_t *ctx, lsm6dsv_sh_slave_connected_t val); -int32_t lsm6dsv_sh_slave_connected_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_sh_slave_connected_get(const stmdev_ctx_t *ctx, lsm6dsv_sh_slave_connected_t *val); -int32_t lsm6dsv_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSV_SH_TRG_XL_GY_DRDY = 0x0, LSM6DSV_SH_TRIG_INT2 = 0x1, } lsm6dsv_sh_syncro_mode_t; -int32_t lsm6dsv_sh_syncro_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_sh_syncro_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_sh_syncro_mode_t val); -int32_t lsm6dsv_sh_syncro_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_sh_syncro_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_sh_syncro_mode_t *val); typedef enum @@ -4729,13 +4728,13 @@ typedef enum LSM6DSV_EACH_SH_CYCLE = 0x0, LSM6DSV_ONLY_FIRST_CYCLE = 0x1, } lsm6dsv_sh_write_mode_t; -int32_t lsm6dsv_sh_write_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_sh_write_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_sh_write_mode_t val); -int32_t lsm6dsv_sh_write_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_sh_write_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_sh_write_mode_t *val); -int32_t lsm6dsv_sh_reset_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_sh_reset_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -4743,7 +4742,7 @@ typedef struct uint8_t slv0_subadd; uint8_t slv0_data; } lsm6dsv_sh_cfg_write_t; -int32_t lsm6dsv_sh_cfg_write(stmdev_ctx_t *ctx, +int32_t lsm6dsv_sh_cfg_write(const stmdev_ctx_t *ctx, lsm6dsv_sh_cfg_write_t *val); typedef enum { @@ -4754,9 +4753,9 @@ typedef enum LSM6DSV_SH_240Hz = 0x5, LSM6DSV_SH_480Hz = 0x6, } lsm6dsv_sh_data_rate_t; -int32_t lsm6dsv_sh_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_sh_data_rate_set(const stmdev_ctx_t *ctx, lsm6dsv_sh_data_rate_t val); -int32_t lsm6dsv_sh_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_sh_data_rate_get(const stmdev_ctx_t *ctx, lsm6dsv_sh_data_rate_t *val); typedef struct @@ -4765,23 +4764,23 @@ typedef struct uint8_t slv_subadd; uint8_t slv_len; } lsm6dsv_sh_cfg_read_t; -int32_t lsm6dsv_sh_slv_cfg_read(stmdev_ctx_t *ctx, uint8_t idx, - lsm6dsv_sh_cfg_read_t *val); +int32_t lsm6dsv_sh_slv_cfg_read(const stmdev_ctx_t *ctx, uint8_t idx, + lsm6dsv_sh_cfg_read_t *val); -int32_t lsm6dsv_sh_status_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_sh_status_get(const stmdev_ctx_t *ctx, lsm6dsv_status_master_t *val); -int32_t lsm6dsv_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSV_I2C_I3C_ENABLE = 0x0, LSM6DSV_I2C_I3C_DISABLE = 0x1, } lsm6dsv_ui_i2c_i3c_mode_t; -int32_t lsm6dsv_ui_i2c_i3c_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ui_i2c_i3c_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_ui_i2c_i3c_mode_t val); -int32_t lsm6dsv_ui_i2c_i3c_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_ui_i2c_i3c_mode_t *val); typedef enum @@ -4789,46 +4788,46 @@ typedef enum LSM6DSV_SPI_4_WIRE = 0x0, LSM6DSV_SPI_3_WIRE = 0x1, } lsm6dsv_spi_mode_t; -int32_t lsm6dsv_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsv_spi_mode_t val); -int32_t lsm6dsv_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsv_spi_mode_t *val); +int32_t lsm6dsv_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_spi_mode_t val); +int32_t lsm6dsv_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_spi_mode_t *val); -int32_t lsm6dsv_ui_sda_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_ui_sda_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_ui_sda_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM6DSV_SPI2_4_WIRE = 0x0, LSM6DSV_SPI2_3_WIRE = 0x1, } lsm6dsv_spi2_mode_t; -int32_t lsm6dsv_spi2_mode_set(stmdev_ctx_t *ctx, lsm6dsv_spi2_mode_t val); -int32_t lsm6dsv_spi2_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_spi2_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_spi2_mode_t val); +int32_t lsm6dsv_spi2_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_spi2_mode_t *val); -int32_t lsm6dsv_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { uint8_t step_counter_enable : 1; } lsm6dsv_stpcnt_mode_t; -int32_t lsm6dsv_stpcnt_mode_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_stpcnt_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_stpcnt_mode_t val); -int32_t lsm6dsv_stpcnt_mode_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_stpcnt_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_stpcnt_mode_t *val); -int32_t lsm6dsv_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsv_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsv_stpcnt_rst_step_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_stpcnt_rst_step_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_stpcnt_rst_step_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm6dsv_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm6dsv_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6dsv_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm6dsv_sflp_game_rotation_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_sflp_game_rotation_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -4836,8 +4835,8 @@ typedef struct float_t gbias_y; /* dps */ float_t gbias_z; /* dps */ } lsm6dsv_sflp_gbias_t; -int32_t lsm6dsv_sflp_game_gbias_set(stmdev_ctx_t *ctx, - lsm6dsv_sflp_gbias_t *val); +int32_t lsm6dsv_sflp_game_gbias_set(const stmdev_ctx_t *ctx, + lsm6dsv_sflp_gbias_t *val); typedef enum { @@ -4848,10 +4847,10 @@ typedef enum LSM6DSV_SFLP_240Hz = 0x4, LSM6DSV_SFLP_480Hz = 0x5, } lsm6dsv_sflp_data_rate_t; -int32_t lsm6dsv_sflp_data_rate_set(stmdev_ctx_t *ctx, - lsm6dsv_sflp_data_rate_t val); -int32_t lsm6dsv_sflp_data_rate_get(stmdev_ctx_t *ctx, - lsm6dsv_sflp_data_rate_t *val); +int32_t lsm6dsv_sflp_data_rate_set(const stmdev_ctx_t *ctx, + lsm6dsv_sflp_data_rate_t val); +int32_t lsm6dsv_sflp_data_rate_get(const stmdev_ctx_t *ctx, + lsm6dsv_sflp_data_rate_t *val); typedef struct { @@ -4859,9 +4858,9 @@ typedef struct uint8_t tap_y_en : 1; uint8_t tap_z_en : 1; } lsm6dsv_tap_detection_t; -int32_t lsm6dsv_tap_detection_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_tap_detection_set(const stmdev_ctx_t *ctx, lsm6dsv_tap_detection_t val); -int32_t lsm6dsv_tap_detection_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_tap_detection_get(const stmdev_ctx_t *ctx, lsm6dsv_tap_detection_t *val); typedef struct @@ -4870,9 +4869,9 @@ typedef struct uint8_t y : 5; uint8_t z : 5; } lsm6dsv_tap_thresholds_t; -int32_t lsm6dsv_tap_thresholds_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_tap_thresholds_set(const stmdev_ctx_t *ctx, lsm6dsv_tap_thresholds_t val); -int32_t lsm6dsv_tap_thresholds_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_tap_thresholds_get(const stmdev_ctx_t *ctx, lsm6dsv_tap_thresholds_t *val); typedef enum @@ -4884,9 +4883,9 @@ typedef enum LSM6DSV_YZX = 0x5, LSM6DSV_ZXY = 0x6, } lsm6dsv_tap_axis_priority_t; -int32_t lsm6dsv_tap_axis_priority_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_tap_axis_priority_set(const stmdev_ctx_t *ctx, lsm6dsv_tap_axis_priority_t val); -int32_t lsm6dsv_tap_axis_priority_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_tap_axis_priority_get(const stmdev_ctx_t *ctx, lsm6dsv_tap_axis_priority_t *val); typedef struct @@ -4895,9 +4894,9 @@ typedef struct uint8_t quiet : 2; uint8_t tap_gap : 4; } lsm6dsv_tap_time_windows_t; -int32_t lsm6dsv_tap_time_windows_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_tap_time_windows_set(const stmdev_ctx_t *ctx, lsm6dsv_tap_time_windows_t val); -int32_t lsm6dsv_tap_time_windows_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_tap_time_windows_get(const stmdev_ctx_t *ctx, lsm6dsv_tap_time_windows_t *val); typedef enum @@ -4905,16 +4904,16 @@ typedef enum LSM6DSV_ONLY_SINGLE = 0x0, LSM6DSV_BOTH_SINGLE_DOUBLE = 0x1, } lsm6dsv_tap_mode_t; -int32_t lsm6dsv_tap_mode_set(stmdev_ctx_t *ctx, lsm6dsv_tap_mode_t val); -int32_t lsm6dsv_tap_mode_get(stmdev_ctx_t *ctx, lsm6dsv_tap_mode_t *val); +int32_t lsm6dsv_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_tap_mode_t val); +int32_t lsm6dsv_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_tap_mode_t *val); -int32_t lsm6dsv_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm6dsv_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); +int32_t lsm6dsv_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); -int32_t lsm6dsv_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm6dsv_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm6dsv_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6dsv_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -4923,8 +4922,8 @@ typedef enum LSM6DSV_XL_LOW_POWER_GY_SLEEP = 0x2, LSM6DSV_XL_LOW_POWER_GY_POWER_DOWN = 0x3, } lsm6dsv_act_mode_t; -int32_t lsm6dsv_act_mode_set(stmdev_ctx_t *ctx, lsm6dsv_act_mode_t val); -int32_t lsm6dsv_act_mode_get(stmdev_ctx_t *ctx, lsm6dsv_act_mode_t *val); +int32_t lsm6dsv_act_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_act_mode_t val); +int32_t lsm6dsv_act_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_act_mode_t *val); typedef enum { @@ -4933,9 +4932,9 @@ typedef enum LSM6DSV_SLEEP_TO_ACT_AT_3RD_SAMPLE = 0x2, LSM6DSV_SLEEP_TO_ACT_AT_4th_SAMPLE = 0x3, } lsm6dsv_act_from_sleep_to_act_dur_t; -int32_t lsm6dsv_act_from_sleep_to_act_dur_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_act_from_sleep_to_act_dur_set(const stmdev_ctx_t *ctx, lsm6dsv_act_from_sleep_to_act_dur_t val); -int32_t lsm6dsv_act_from_sleep_to_act_dur_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx, lsm6dsv_act_from_sleep_to_act_dur_t *val); typedef enum @@ -4945,9 +4944,9 @@ typedef enum LSM6DSV_30Hz = 0x2, LSM6DSV_60Hz = 0x3, } lsm6dsv_act_sleep_xl_odr_t; -int32_t lsm6dsv_act_sleep_xl_odr_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_act_sleep_xl_odr_set(const stmdev_ctx_t *ctx, lsm6dsv_act_sleep_xl_odr_t val); -int32_t lsm6dsv_act_sleep_xl_odr_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx, lsm6dsv_act_sleep_xl_odr_t *val); typedef struct @@ -4957,9 +4956,9 @@ typedef struct uint8_t threshold; uint8_t duration; } lsm6dsv_act_thresholds_t; -int32_t lsm6dsv_act_thresholds_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_act_thresholds_set(const stmdev_ctx_t *ctx, lsm6dsv_act_thresholds_t *val); -int32_t lsm6dsv_act_thresholds_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_act_thresholds_get(const stmdev_ctx_t *ctx, lsm6dsv_act_thresholds_t *val); typedef struct @@ -4967,9 +4966,9 @@ typedef struct uint8_t shock : 2; uint8_t quiet : 4; } lsm6dsv_act_wkup_time_windows_t; -int32_t lsm6dsv_act_wkup_time_windows_set(stmdev_ctx_t *ctx, +int32_t lsm6dsv_act_wkup_time_windows_set(const stmdev_ctx_t *ctx, lsm6dsv_act_wkup_time_windows_t val); -int32_t lsm6dsv_act_wkup_time_windows_get(stmdev_ctx_t *ctx, +int32_t lsm6dsv_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, lsm6dsv_act_wkup_time_windows_t *val); /** diff --git a/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.c b/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.c index 2a715b51..0b98deee 100644 --- a/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.c +++ b/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm9ds1_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm9ds1_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak lsm9ds1_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak lsm9ds1_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak lsm9ds1_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -171,7 +181,7 @@ float_t lsm9ds1_from_lsb_to_celsius(int16_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm9ds1_gy_fs_t val) { lsm9ds1_ctrl_reg1_g_t ctrl_reg1_g; @@ -198,7 +208,7 @@ int32_t lsm9ds1_gy_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_fs_t *val) { lsm9ds1_ctrl_reg1_g_t ctrl_reg1_g; @@ -238,7 +248,7 @@ int32_t lsm9ds1_gy_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_imu_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_imu_data_rate_set(const stmdev_ctx_t *ctx, lsm9ds1_imu_odr_t val) { lsm9ds1_ctrl_reg1_g_t ctrl_reg1_g; @@ -294,7 +304,7 @@ int32_t lsm9ds1_imu_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_imu_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_imu_data_rate_get(const stmdev_ctx_t *ctx, lsm9ds1_imu_odr_t *val) { lsm9ds1_ctrl_reg1_g_t ctrl_reg1_g; @@ -436,7 +446,7 @@ int32_t lsm9ds1_imu_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_orient_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_orient_set(const stmdev_ctx_t *ctx, lsm9ds1_gy_orient_t val) { lsm9ds1_orient_cfg_g_t orient_cfg_g; @@ -466,7 +476,7 @@ int32_t lsm9ds1_gy_orient_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_orient_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_orient_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_orient_t *val) { lsm9ds1_orient_cfg_g_t orient_cfg_g; @@ -490,7 +500,7 @@ int32_t lsm9ds1_gy_orient_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm9ds1_status_reg_t status_reg; @@ -511,7 +521,7 @@ int32_t lsm9ds1_xl_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm9ds1_status_reg_t status_reg; @@ -532,7 +542,7 @@ int32_t lsm9ds1_gy_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm9ds1_status_reg_t status_reg; @@ -553,7 +563,7 @@ int32_t lsm9ds1_temp_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_axis_set(stmdev_ctx_t *ctx, lsm9ds1_gy_axis_t val) +int32_t lsm9ds1_gy_axis_set(const stmdev_ctx_t *ctx, lsm9ds1_gy_axis_t val) { lsm9ds1_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -579,7 +589,7 @@ int32_t lsm9ds1_gy_axis_set(stmdev_ctx_t *ctx, lsm9ds1_gy_axis_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_axis_get(stmdev_ctx_t *ctx, lsm9ds1_gy_axis_t *val) +int32_t lsm9ds1_gy_axis_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_axis_t *val) { lsm9ds1_ctrl_reg4_t ctrl_reg4; int32_t ret; @@ -600,7 +610,7 @@ int32_t lsm9ds1_gy_axis_get(stmdev_ctx_t *ctx, lsm9ds1_gy_axis_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_xl_axis_set(stmdev_ctx_t *ctx, lsm9ds1_xl_axis_t val) +int32_t lsm9ds1_xl_axis_set(const stmdev_ctx_t *ctx, lsm9ds1_xl_axis_t val) { lsm9ds1_ctrl_reg5_xl_t ctrl_reg5_xl; int32_t ret; @@ -628,7 +638,7 @@ int32_t lsm9ds1_xl_axis_set(stmdev_ctx_t *ctx, lsm9ds1_xl_axis_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_xl_axis_get(stmdev_ctx_t *ctx, lsm9ds1_xl_axis_t *val) +int32_t lsm9ds1_xl_axis_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_axis_t *val) { lsm9ds1_ctrl_reg5_xl_t ctrl_reg5_xl; int32_t ret; @@ -650,7 +660,7 @@ int32_t lsm9ds1_xl_axis_get(stmdev_ctx_t *ctx, lsm9ds1_xl_axis_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_xl_decimation_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_decimation_set(const stmdev_ctx_t *ctx, lsm9ds1_dec_t val) { lsm9ds1_ctrl_reg5_xl_t ctrl_reg5_xl; @@ -677,7 +687,7 @@ int32_t lsm9ds1_xl_decimation_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_xl_decimation_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_decimation_get(const stmdev_ctx_t *ctx, lsm9ds1_dec_t *val) { lsm9ds1_ctrl_reg5_xl_t ctrl_reg5_xl; @@ -720,7 +730,7 @@ int32_t lsm9ds1_xl_decimation_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm9ds1_xl_fs_t val) { lsm9ds1_ctrl_reg6_xl_t ctrl_reg6_xl; @@ -747,7 +757,7 @@ int32_t lsm9ds1_xl_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_fs_t *val) { lsm9ds1_ctrl_reg6_xl_t ctrl_reg6_xl; @@ -791,7 +801,7 @@ int32_t lsm9ds1_xl_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_block_data_update_set(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_block_data_update_set(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, uint8_t val) { lsm9ds1_ctrl_reg8_t ctrl_reg8; @@ -834,7 +844,7 @@ int32_t lsm9ds1_block_data_update_set(stmdev_ctx_t *ctx_mag, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_block_data_update_get(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_block_data_update_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, uint8_t *val) { lsm9ds1_ctrl_reg8_t ctrl_reg8; @@ -864,7 +874,7 @@ int32_t lsm9ds1_block_data_update_get(stmdev_ctx_t *ctx_mag, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm9ds1_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -890,7 +900,7 @@ int32_t lsm9ds1_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm9ds1_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -914,7 +924,7 @@ int32_t lsm9ds1_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_mag_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_mag_data_rate_set(const stmdev_ctx_t *ctx, lsm9ds1_mag_data_rate_t val) { lsm9ds1_ctrl_reg1_m_t ctrl_reg1_m; @@ -972,7 +982,7 @@ int32_t lsm9ds1_mag_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_mag_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_mag_data_rate_get(const stmdev_ctx_t *ctx, lsm9ds1_mag_data_rate_t *val) { lsm9ds1_ctrl_reg1_m_t ctrl_reg1_m; @@ -1159,7 +1169,7 @@ int32_t lsm9ds1_mag_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_mag_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_mag_full_scale_set(const stmdev_ctx_t *ctx, lsm9ds1_mag_fs_t val) { lsm9ds1_ctrl_reg2_m_t ctrl_reg2_m; @@ -1186,7 +1196,7 @@ int32_t lsm9ds1_mag_full_scale_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_mag_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_mag_full_scale_get(const stmdev_ctx_t *ctx, lsm9ds1_mag_fs_t *val) { lsm9ds1_ctrl_reg2_m_t ctrl_reg2_m; @@ -1229,7 +1239,7 @@ int32_t lsm9ds1_mag_full_scale_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_mag_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_mag_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm9ds1_status_reg_m_t status_reg_m; @@ -1263,7 +1273,7 @@ int32_t lsm9ds1_mag_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm9ds1_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1284,7 +1294,7 @@ int32_t lsm9ds1_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm9ds1_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1309,7 +1319,7 @@ int32_t lsm9ds1_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm9ds1_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1334,7 +1344,7 @@ int32_t lsm9ds1_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t lsm9ds1_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[6]; int32_t ret; @@ -1358,7 +1368,7 @@ int32_t lsm9ds1_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_magnetic_overflow_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm9ds1_magnetic_overflow_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm9ds1_int_src_m_t int_src_m; int32_t ret; @@ -1390,7 +1400,7 @@ int32_t lsm9ds1_magnetic_overflow_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_dev_id_get(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_dev_id_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_id_t *buff) { @@ -1417,7 +1427,7 @@ int32_t lsm9ds1_dev_id_get(stmdev_ctx_t *ctx_mag, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_dev_status_get(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_dev_status_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_status_t *val) { @@ -1444,7 +1454,7 @@ int32_t lsm9ds1_dev_status_get(stmdev_ctx_t *ctx_mag, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_dev_reset_set(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_dev_reset_set(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, uint8_t val) { @@ -1487,7 +1497,7 @@ int32_t lsm9ds1_dev_reset_set(stmdev_ctx_t *ctx_mag, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_dev_reset_get(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_dev_reset_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, uint8_t *val) { @@ -1517,7 +1527,7 @@ int32_t lsm9ds1_dev_reset_get(stmdev_ctx_t *ctx_mag, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_dev_data_format_set(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_dev_data_format_set(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_ble_t val) { @@ -1560,7 +1570,7 @@ int32_t lsm9ds1_dev_data_format_set(stmdev_ctx_t *ctx_mag, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_dev_data_format_get(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_dev_data_format_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_ble_t *val) { @@ -1604,7 +1614,7 @@ int32_t lsm9ds1_dev_data_format_get(stmdev_ctx_t *ctx_mag, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_dev_boot_set(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_dev_boot_set(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, uint8_t val) { @@ -1647,7 +1657,7 @@ int32_t lsm9ds1_dev_boot_set(stmdev_ctx_t *ctx_mag, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_dev_boot_get(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_dev_boot_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, uint8_t *val) { @@ -1689,7 +1699,7 @@ int32_t lsm9ds1_dev_boot_get(stmdev_ctx_t *ctx_mag, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_filter_reference_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_filter_reference_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1707,7 +1717,7 @@ int32_t lsm9ds1_gy_filter_reference_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_filter_reference_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_filter_reference_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -1725,7 +1735,7 @@ int32_t lsm9ds1_gy_filter_reference_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_filter_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_filter_lp_bandwidth_set(const stmdev_ctx_t *ctx, lsm9ds1_gy_lp_bw_t val) { lsm9ds1_ctrl_reg1_g_t ctrl_reg1_g; @@ -1752,7 +1762,7 @@ int32_t lsm9ds1_gy_filter_lp_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_filter_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_filter_lp_bandwidth_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_lp_bw_t *val) { lsm9ds1_ctrl_reg1_g_t ctrl_reg1_g; @@ -1795,7 +1805,7 @@ int32_t lsm9ds1_gy_filter_lp_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_filter_out_path_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_filter_out_path_set(const stmdev_ctx_t *ctx, lsm9ds1_gy_out_path_t val) { lsm9ds1_ctrl_reg2_g_t ctrl_reg2_g; @@ -1836,7 +1846,7 @@ int32_t lsm9ds1_gy_filter_out_path_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_filter_out_path_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_filter_out_path_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_out_path_t *val) { lsm9ds1_ctrl_reg2_g_t ctrl_reg2_g; @@ -1886,7 +1896,7 @@ int32_t lsm9ds1_gy_filter_out_path_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_filter_int_path_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_filter_int_path_set(const stmdev_ctx_t *ctx, lsm9ds1_gy_int_path_t val) { lsm9ds1_ctrl_reg2_g_t ctrl_reg2_g; @@ -1927,7 +1937,7 @@ int32_t lsm9ds1_gy_filter_int_path_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_filter_int_path_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_filter_int_path_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_int_path_t *val) { lsm9ds1_ctrl_reg2_g_t ctrl_reg2_g; @@ -1977,7 +1987,7 @@ int32_t lsm9ds1_gy_filter_int_path_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_filter_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_filter_hp_bandwidth_set(const stmdev_ctx_t *ctx, lsm9ds1_gy_hp_bw_t val) { lsm9ds1_ctrl_reg3_g_t ctrl_reg3_g; @@ -2004,7 +2014,7 @@ int32_t lsm9ds1_gy_filter_hp_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_filter_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_filter_hp_bandwidth_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_hp_bw_t *val) { lsm9ds1_ctrl_reg3_g_t ctrl_reg3_g; @@ -2071,7 +2081,7 @@ int32_t lsm9ds1_gy_filter_hp_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_xl_filter_aalias_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_filter_aalias_bandwidth_set(const stmdev_ctx_t *ctx, lsm9ds1_xl_aa_bw_t val) { lsm9ds1_ctrl_reg6_xl_t ctrl_reg6_xl; @@ -2099,7 +2109,7 @@ int32_t lsm9ds1_xl_filter_aalias_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_xl_filter_aalias_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_filter_aalias_bandwidth_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_aa_bw_t *val) { lsm9ds1_ctrl_reg6_xl_t ctrl_reg6_xl; @@ -2146,7 +2156,7 @@ int32_t lsm9ds1_xl_filter_aalias_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_xl_filter_int_path_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_filter_int_path_set(const stmdev_ctx_t *ctx, lsm9ds1_xl_hp_path_t val) { lsm9ds1_ctrl_reg7_xl_t ctrl_reg7_xl; @@ -2173,7 +2183,7 @@ int32_t lsm9ds1_xl_filter_int_path_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_xl_filter_int_path_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_filter_int_path_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_hp_path_t *val) { lsm9ds1_ctrl_reg7_xl_t ctrl_reg7_xl; @@ -2208,7 +2218,7 @@ int32_t lsm9ds1_xl_filter_int_path_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_xl_filter_out_path_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_filter_out_path_set(const stmdev_ctx_t *ctx, lsm9ds1_xl_out_path_t val) { lsm9ds1_ctrl_reg7_xl_t ctrl_reg7_xl; @@ -2235,7 +2245,7 @@ int32_t lsm9ds1_xl_filter_out_path_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_xl_filter_out_path_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_filter_out_path_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_out_path_t *val) { lsm9ds1_ctrl_reg7_xl_t ctrl_reg7_xl; @@ -2271,7 +2281,7 @@ int32_t lsm9ds1_xl_filter_out_path_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_xl_filter_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_filter_lp_bandwidth_set(const stmdev_ctx_t *ctx, lsm9ds1_xl_lp_bw_t val) { lsm9ds1_ctrl_reg7_xl_t ctrl_reg7_xl; @@ -2300,7 +2310,7 @@ int32_t lsm9ds1_xl_filter_lp_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_xl_filter_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_filter_lp_bandwidth_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_lp_bw_t *val) { lsm9ds1_ctrl_reg7_xl_t ctrl_reg7_xl; @@ -2348,7 +2358,7 @@ int32_t lsm9ds1_xl_filter_lp_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_xl_filter_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_filter_hp_bandwidth_set(const stmdev_ctx_t *ctx, lsm9ds1_xl_hp_bw_t val) { lsm9ds1_ctrl_reg7_xl_t ctrl_reg7_xl; @@ -2376,7 +2386,7 @@ int32_t lsm9ds1_xl_filter_hp_bandwidth_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_xl_filter_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_filter_hp_bandwidth_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_hp_bw_t *val) { lsm9ds1_ctrl_reg7_xl_t ctrl_reg7_xl; @@ -2419,7 +2429,7 @@ int32_t lsm9ds1_xl_filter_hp_bandwidth_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm9ds1_ctrl_reg9_t ctrl_reg9; @@ -2444,7 +2454,7 @@ int32_t lsm9ds1_filter_settling_mask_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm9ds1_ctrl_reg9_t ctrl_reg9; @@ -2478,7 +2488,7 @@ int32_t lsm9ds1_filter_settling_mask_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm9ds1_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm9ds1_ctrl_reg8_t ctrl_reg8; int32_t ret; @@ -2503,7 +2513,7 @@ int32_t lsm9ds1_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm9ds1_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm9ds1_ctrl_reg8_t ctrl_reg8; int32_t ret; @@ -2523,7 +2533,7 @@ int32_t lsm9ds1_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_spi_mode_set(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_spi_mode_set(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_sim_t val) { @@ -2566,7 +2576,7 @@ int32_t lsm9ds1_spi_mode_set(stmdev_ctx_t *ctx_mag, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_spi_mode_get(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_spi_mode_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_sim_t *val) { @@ -2610,7 +2620,7 @@ int32_t lsm9ds1_spi_mode_get(stmdev_ctx_t *ctx_mag, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_i2c_interface_set(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_i2c_interface_set(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_i2c_dis_t val) { @@ -2653,7 +2663,7 @@ int32_t lsm9ds1_i2c_interface_set(stmdev_ctx_t *ctx_mag, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_i2c_interface_get(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_i2c_interface_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_i2c_dis_t *val) { @@ -2709,7 +2719,7 @@ int32_t lsm9ds1_i2c_interface_get(stmdev_ctx_t *ctx_mag, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_pin_logic_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_pin_logic_set(const stmdev_ctx_t *ctx, lsm9ds1_pin_logic_t val) { lsm9ds1_int_gen_cfg_xl_t int_gen_cfg_xl; @@ -2750,7 +2760,7 @@ int32_t lsm9ds1_pin_logic_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_pin_logic_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_pin_logic_get(const stmdev_ctx_t *ctx, lsm9ds1_pin_logic_t *val) { lsm9ds1_int_gen_cfg_xl_t int_gen_cfg_xl; @@ -2792,7 +2802,7 @@ int32_t lsm9ds1_pin_logic_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm9ds1_pin_int1_route_t val) { lsm9ds1_int1_ctrl_t int1_ctrl; @@ -2824,7 +2834,7 @@ int32_t lsm9ds1_pin_int1_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm9ds1_pin_int1_route_t *val) { lsm9ds1_int1_ctrl_t int1_ctrl; @@ -2851,7 +2861,7 @@ int32_t lsm9ds1_pin_int1_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm9ds1_pin_int2_route_t val) { lsm9ds1_int2_ctrl_t int2_ctrl; @@ -2882,7 +2892,7 @@ int32_t lsm9ds1_pin_int2_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_pin_int2_route_get(const stmdev_ctx_t *ctx, lsm9ds1_pin_int2_route_t *val) { lsm9ds1_int2_ctrl_t int2_ctrl; @@ -2909,7 +2919,7 @@ int32_t lsm9ds1_pin_int2_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_pin_notification_set(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_pin_notification_set(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_lir_t val) { @@ -2966,7 +2976,7 @@ int32_t lsm9ds1_pin_notification_set(stmdev_ctx_t *ctx_mag, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_pin_notification_get(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_pin_notification_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_lir_t *val) { @@ -3015,7 +3025,7 @@ int32_t lsm9ds1_pin_notification_get(stmdev_ctx_t *ctx_mag, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_pin_mode_set(stmdev_ctx_t *ctx, lsm9ds1_pp_od_t val) +int32_t lsm9ds1_pin_mode_set(const stmdev_ctx_t *ctx, lsm9ds1_pp_od_t val) { lsm9ds1_ctrl_reg8_t ctrl_reg8; int32_t ret; @@ -3039,7 +3049,7 @@ int32_t lsm9ds1_pin_mode_set(stmdev_ctx_t *ctx, lsm9ds1_pp_od_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_pin_mode_get(stmdev_ctx_t *ctx, lsm9ds1_pp_od_t *val) +int32_t lsm9ds1_pin_mode_get(const stmdev_ctx_t *ctx, lsm9ds1_pp_od_t *val) { lsm9ds1_ctrl_reg8_t ctrl_reg8; int32_t ret; @@ -3072,7 +3082,7 @@ int32_t lsm9ds1_pin_mode_get(stmdev_ctx_t *ctx, lsm9ds1_pp_od_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_pin_int_m_route_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_pin_int_m_route_set(const stmdev_ctx_t *ctx, lsm9ds1_pin_m_route_t val) { lsm9ds1_int_cfg_m_t int_cfg_m; @@ -3097,7 +3107,7 @@ int32_t lsm9ds1_pin_int_m_route_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_pin_int_m_route_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_pin_int_m_route_get(const stmdev_ctx_t *ctx, lsm9ds1_pin_m_route_t *val) { lsm9ds1_int_cfg_m_t int_cfg_m; @@ -3118,7 +3128,7 @@ int32_t lsm9ds1_pin_int_m_route_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_pin_polarity_set(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_pin_polarity_set(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_polarity_t val) { @@ -3161,7 +3171,7 @@ int32_t lsm9ds1_pin_polarity_set(stmdev_ctx_t *ctx_mag, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_pin_polarity_get(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_pin_polarity_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_polarity_t *val) { @@ -3218,7 +3228,7 @@ int32_t lsm9ds1_pin_polarity_get(stmdev_ctx_t *ctx_mag, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_xl_trshld_axis_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_trshld_axis_set(const stmdev_ctx_t *ctx, lsm9ds1_xl_trshld_en_t val) { lsm9ds1_int_gen_cfg_xl_t int_gen_cfg_xl; @@ -3251,7 +3261,7 @@ int32_t lsm9ds1_xl_trshld_axis_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_xl_trshld_axis_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_trshld_axis_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_trshld_en_t *val) { lsm9ds1_int_gen_cfg_xl_t int_gen_cfg_xl; @@ -3277,7 +3287,7 @@ int32_t lsm9ds1_xl_trshld_axis_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_xl_trshld_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm9ds1_xl_trshld_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -3294,7 +3304,7 @@ int32_t lsm9ds1_xl_trshld_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_xl_trshld_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm9ds1_xl_trshld_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -3311,7 +3321,7 @@ int32_t lsm9ds1_xl_trshld_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_xl_trshld_min_sample_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_trshld_min_sample_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm9ds1_int_gen_dur_xl_t int_gen_dur_xl; @@ -3349,7 +3359,7 @@ int32_t lsm9ds1_xl_trshld_min_sample_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_xl_trshld_min_sample_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_trshld_min_sample_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm9ds1_int_gen_dur_xl_t int_gen_dur_xl; @@ -3370,7 +3380,7 @@ int32_t lsm9ds1_xl_trshld_min_sample_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_trshld_src_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_trshld_src_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_trshld_src_t *val) { lsm9ds1_int_gen_src_g_t int_gen_src_g; @@ -3397,7 +3407,7 @@ int32_t lsm9ds1_gy_trshld_src_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_xl_trshld_src_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_trshld_src_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_trshld_src_t *val) { lsm9ds1_int_gen_src_xl_t int_gen_src_xl; @@ -3425,7 +3435,7 @@ int32_t lsm9ds1_xl_trshld_src_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_trshld_axis_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_trshld_axis_set(const stmdev_ctx_t *ctx, lsm9ds1_gy_trshld_en_t val) { lsm9ds1_int_gen_cfg_g_t int_gen_cfg_g; @@ -3458,7 +3468,7 @@ int32_t lsm9ds1_gy_trshld_axis_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_trshld_axis_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_trshld_axis_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_trshld_en_t *val) { lsm9ds1_int_gen_cfg_g_t int_gen_cfg_g; @@ -3484,7 +3494,7 @@ int32_t lsm9ds1_gy_trshld_axis_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_trshld_mode_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_trshld_mode_set(const stmdev_ctx_t *ctx, lsm9ds1_dcrm_g_t val) { lsm9ds1_int_gen_ths_xh_g_t int_gen_ths_xh_g; @@ -3511,7 +3521,7 @@ int32_t lsm9ds1_gy_trshld_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_trshld_mode_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_trshld_mode_get(const stmdev_ctx_t *ctx, lsm9ds1_dcrm_g_t *val) { lsm9ds1_int_gen_ths_xh_g_t int_gen_ths_xh_g; @@ -3546,7 +3556,7 @@ int32_t lsm9ds1_gy_trshld_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_trshld_x_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm9ds1_gy_trshld_x_set(const stmdev_ctx_t *ctx, uint16_t val) { lsm9ds1_int_gen_ths_xh_g_t int_gen_ths_xh_g; lsm9ds1_int_gen_ths_xl_g_t int_gen_ths_xl_g; @@ -3586,7 +3596,7 @@ int32_t lsm9ds1_gy_trshld_x_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_trshld_x_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm9ds1_gy_trshld_x_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm9ds1_int_gen_ths_xh_g_t int_gen_ths_xh_g; lsm9ds1_int_gen_ths_xl_g_t int_gen_ths_xl_g; @@ -3617,7 +3627,7 @@ int32_t lsm9ds1_gy_trshld_x_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_trshld_y_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm9ds1_gy_trshld_y_set(const stmdev_ctx_t *ctx, uint16_t val) { lsm9ds1_int_gen_ths_yh_g_t int_gen_ths_yh_g; lsm9ds1_int_gen_ths_yl_g_t int_gen_ths_yl_g; @@ -3657,7 +3667,7 @@ int32_t lsm9ds1_gy_trshld_y_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_trshld_y_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm9ds1_gy_trshld_y_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm9ds1_int_gen_ths_yh_g_t int_gen_ths_yh_g; lsm9ds1_int_gen_ths_yl_g_t int_gen_ths_yl_g; @@ -3687,7 +3697,7 @@ int32_t lsm9ds1_gy_trshld_y_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_trshld_z_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t lsm9ds1_gy_trshld_z_set(const stmdev_ctx_t *ctx, uint16_t val) { lsm9ds1_int_gen_ths_zh_g_t int_gen_ths_zh_g; lsm9ds1_int_gen_ths_zl_g_t int_gen_ths_zl_g; @@ -3727,7 +3737,7 @@ int32_t lsm9ds1_gy_trshld_z_set(stmdev_ctx_t *ctx, uint16_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_trshld_z_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t lsm9ds1_gy_trshld_z_get(const stmdev_ctx_t *ctx, uint16_t *val) { lsm9ds1_int_gen_ths_zh_g_t int_gen_ths_zh_g; lsm9ds1_int_gen_ths_zl_g_t int_gen_ths_zl_g; @@ -3757,7 +3767,7 @@ int32_t lsm9ds1_gy_trshld_z_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_trshld_min_sample_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_trshld_min_sample_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm9ds1_int_gen_dur_g_t int_gen_dur_g; @@ -3794,7 +3804,7 @@ int32_t lsm9ds1_gy_trshld_min_sample_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_trshld_min_sample_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_trshld_min_sample_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm9ds1_int_gen_dur_g_t int_gen_dur_g; @@ -3815,7 +3825,7 @@ int32_t lsm9ds1_gy_trshld_min_sample_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_mag_trshld_axis_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_mag_trshld_axis_set(const stmdev_ctx_t *ctx, lsm9ds1_mag_trshld_axis_t val) { lsm9ds1_int_cfg_m_t int_cfg_m; @@ -3842,7 +3852,7 @@ int32_t lsm9ds1_mag_trshld_axis_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_mag_trshld_axis_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_mag_trshld_axis_get(const stmdev_ctx_t *ctx, lsm9ds1_mag_trshld_axis_t *val) { lsm9ds1_int_cfg_m_t int_cfg_m; @@ -3864,7 +3874,7 @@ int32_t lsm9ds1_mag_trshld_axis_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_mag_trshld_src_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_mag_trshld_src_get(const stmdev_ctx_t *ctx, lsm9ds1_mag_trshld_src_t *val) { lsm9ds1_int_src_m_t int_src_m; @@ -3890,7 +3900,7 @@ int32_t lsm9ds1_mag_trshld_src_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_mag_trshld_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm9ds1_mag_trshld_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm9ds1_int_ths_l_m_t int_ths_l_m; lsm9ds1_int_ths_h_m_t int_ths_h_m; @@ -3933,7 +3943,7 @@ int32_t lsm9ds1_mag_trshld_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm9ds1_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm9ds1_act_ths_t act_ths; int32_t ret; @@ -3957,7 +3967,7 @@ int32_t lsm9ds1_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm9ds1_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm9ds1_act_ths_t act_ths; int32_t ret; @@ -3976,7 +3986,7 @@ int32_t lsm9ds1_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_act_mode_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_act_mode_set(const stmdev_ctx_t *ctx, lsm9ds1_act_mode_t val) { lsm9ds1_act_ths_t act_ths; @@ -4013,7 +4023,7 @@ int32_t lsm9ds1_act_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_act_mode_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_act_mode_get(const stmdev_ctx_t *ctx, lsm9ds1_act_mode_t *val) { lsm9ds1_act_ths_t act_ths; @@ -4053,7 +4063,7 @@ int32_t lsm9ds1_act_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_act_duration_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm9ds1_act_duration_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -4070,7 +4080,7 @@ int32_t lsm9ds1_act_duration_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_act_duration_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm9ds1_act_duration_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -4087,7 +4097,7 @@ int32_t lsm9ds1_act_duration_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_act_src_get(stmdev_ctx_t *ctx, lsm9ds1_inact_t *val) +int32_t lsm9ds1_act_src_get(const stmdev_ctx_t *ctx, lsm9ds1_inact_t *val) { lsm9ds1_status_reg_t status_reg; int32_t ret; @@ -4134,7 +4144,7 @@ int32_t lsm9ds1_act_src_get(stmdev_ctx_t *ctx, lsm9ds1_inact_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_6d_mode_set(stmdev_ctx_t *ctx, lsm9ds1_6d_mode_t val) +int32_t lsm9ds1_6d_mode_set(const stmdev_ctx_t *ctx, lsm9ds1_6d_mode_t val) { lsm9ds1_int_gen_cfg_xl_t int_gen_cfg_xl; lsm9ds1_ctrl_reg4_t ctrl_reg4; @@ -4175,7 +4185,7 @@ int32_t lsm9ds1_6d_mode_set(stmdev_ctx_t *ctx, lsm9ds1_6d_mode_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_6d_mode_get(stmdev_ctx_t *ctx, lsm9ds1_6d_mode_t *val) +int32_t lsm9ds1_6d_mode_get(const stmdev_ctx_t *ctx, lsm9ds1_6d_mode_t *val) { lsm9ds1_int_gen_cfg_xl_t int_gen_cfg_xl; lsm9ds1_ctrl_reg4_t ctrl_reg4; @@ -4229,7 +4239,7 @@ int32_t lsm9ds1_6d_mode_get(stmdev_ctx_t *ctx, lsm9ds1_6d_mode_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm9ds1_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -4246,7 +4256,7 @@ int32_t lsm9ds1_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t lsm9ds1_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -4263,7 +4273,7 @@ int32_t lsm9ds1_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_6d_src_get(stmdev_ctx_t *ctx, lsm9ds1_6d_src_t *val) +int32_t lsm9ds1_6d_src_get(const stmdev_ctx_t *ctx, lsm9ds1_6d_src_t *val) { lsm9ds1_int_gen_src_xl_t int_gen_src_xl; int32_t ret; @@ -4303,7 +4313,7 @@ int32_t lsm9ds1_6d_src_get(stmdev_ctx_t *ctx, lsm9ds1_6d_src_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm9ds1_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm9ds1_ctrl_reg9_t ctrl_reg9; int32_t ret; @@ -4328,7 +4338,7 @@ int32_t lsm9ds1_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm9ds1_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm9ds1_ctrl_reg9_t ctrl_reg9; int32_t ret; @@ -4347,7 +4357,7 @@ int32_t lsm9ds1_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_fifo_mode_set(const stmdev_ctx_t *ctx, lsm9ds1_fifo_md_t val) { lsm9ds1_ctrl_reg9_t ctrl_reg9; @@ -4384,7 +4394,7 @@ int32_t lsm9ds1_fifo_mode_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_fifo_mode_get(const stmdev_ctx_t *ctx, lsm9ds1_fifo_md_t *val) { lsm9ds1_ctrl_reg9_t ctrl_reg9; @@ -4440,7 +4450,7 @@ int32_t lsm9ds1_fifo_mode_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm9ds1_fifo_temp_batch_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm9ds1_ctrl_reg9_t ctrl_reg9; int32_t ret; @@ -4464,7 +4474,7 @@ int32_t lsm9ds1_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm9ds1_fifo_temp_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm9ds1_ctrl_reg9_t ctrl_reg9; int32_t ret; @@ -4483,7 +4493,7 @@ int32_t lsm9ds1_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm9ds1_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm9ds1_fifo_ctrl_t fifo_ctrl; int32_t ret; @@ -4507,7 +4517,7 @@ int32_t lsm9ds1_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm9ds1_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm9ds1_fifo_ctrl_t fifo_ctrl; int32_t ret; @@ -4526,7 +4536,7 @@ int32_t lsm9ds1_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm9ds1_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm9ds1_fifo_src_t fifo_src; int32_t ret; @@ -4545,7 +4555,7 @@ int32_t lsm9ds1_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm9ds1_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm9ds1_fifo_src_t fifo_src; int32_t ret; @@ -4564,7 +4574,7 @@ int32_t lsm9ds1_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm9ds1_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm9ds1_fifo_src_t fifo_src; int32_t ret; @@ -4583,7 +4593,7 @@ int32_t lsm9ds1_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm9ds1_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm9ds1_fifo_src_t fifo_src; int32_t ret; @@ -4615,7 +4625,7 @@ int32_t lsm9ds1_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_xl_self_test_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm9ds1_xl_self_test_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm9ds1_ctrl_reg10_t ctrl_reg10; int32_t ret; @@ -4641,7 +4651,7 @@ int32_t lsm9ds1_xl_self_test_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_xl_self_test_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm9ds1_xl_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm9ds1_ctrl_reg10_t ctrl_reg10; int32_t ret; @@ -4661,7 +4671,7 @@ int32_t lsm9ds1_xl_self_test_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_self_test_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm9ds1_gy_self_test_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm9ds1_ctrl_reg10_t ctrl_reg10; int32_t ret; @@ -4687,7 +4697,7 @@ int32_t lsm9ds1_gy_self_test_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_gy_self_test_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm9ds1_gy_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm9ds1_ctrl_reg10_t ctrl_reg10; int32_t ret; @@ -4707,7 +4717,7 @@ int32_t lsm9ds1_gy_self_test_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_mag_self_test_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t lsm9ds1_mag_self_test_set(const stmdev_ctx_t *ctx, uint8_t val) { lsm9ds1_ctrl_reg1_m_t ctrl_reg1_m; int32_t ret; @@ -4733,7 +4743,7 @@ int32_t lsm9ds1_mag_self_test_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t lsm9ds1_mag_self_test_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t lsm9ds1_mag_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val) { lsm9ds1_ctrl_reg1_m_t ctrl_reg1_m; int32_t ret; diff --git a/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.h b/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.h index 925c51fd..2dba240e 100644 --- a/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.h +++ b/sensor/stmemsc/lsm9ds1_STdC/driver/lsm9ds1_reg.h @@ -957,10 +957,10 @@ typedef union * them with a custom implementation. */ -int32_t lsm9ds1_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm9ds1_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t lsm9ds1_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t lsm9ds1_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -986,9 +986,9 @@ typedef enum LSM9DS1_500dps = 1, LSM9DS1_2000dps = 3, } lsm9ds1_gy_fs_t; -int32_t lsm9ds1_gy_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_full_scale_set(const stmdev_ctx_t *ctx, lsm9ds1_gy_fs_t val); -int32_t lsm9ds1_gy_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_full_scale_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_fs_t *val); typedef enum @@ -1019,9 +1019,9 @@ typedef enum LSM9DS1_IMU_59Hz5_LP = 0xA2, LSM9DS1_IMU_119Hz_LP = 0xB3, } lsm9ds1_imu_odr_t; -int32_t lsm9ds1_imu_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_imu_data_rate_set(const stmdev_ctx_t *ctx, lsm9ds1_imu_odr_t val); -int32_t lsm9ds1_imu_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_imu_data_rate_get(const stmdev_ctx_t *ctx, lsm9ds1_imu_odr_t *val); typedef struct @@ -1031,18 +1031,18 @@ typedef struct uint8_t signy_g : 1; /*(0: positive; 1: negative)*/ uint8_t signx_g : 1; /*(0: positive; 1: negative)*/ } lsm9ds1_gy_orient_t; -int32_t lsm9ds1_gy_orient_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_orient_set(const stmdev_ctx_t *ctx, lsm9ds1_gy_orient_t val); -int32_t lsm9ds1_gy_orient_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_orient_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_orient_t *val); -int32_t lsm9ds1_xl_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm9ds1_gy_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm9ds1_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct @@ -1051,8 +1051,8 @@ typedef struct uint8_t yen_g : 1; uint8_t zen_g : 1; } lsm9ds1_gy_axis_t; -int32_t lsm9ds1_gy_axis_set(stmdev_ctx_t *ctx, lsm9ds1_gy_axis_t val); -int32_t lsm9ds1_gy_axis_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_axis_set(const stmdev_ctx_t *ctx, lsm9ds1_gy_axis_t val); +int32_t lsm9ds1_gy_axis_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_axis_t *val); typedef struct @@ -1061,8 +1061,8 @@ typedef struct uint8_t yen_xl : 1; uint8_t zen_xl : 1; } lsm9ds1_xl_axis_t; -int32_t lsm9ds1_xl_axis_set(stmdev_ctx_t *ctx, lsm9ds1_xl_axis_t val); -int32_t lsm9ds1_xl_axis_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_axis_set(const stmdev_ctx_t *ctx, lsm9ds1_xl_axis_t val); +int32_t lsm9ds1_xl_axis_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_axis_t *val); typedef enum @@ -1072,9 +1072,9 @@ typedef enum LSM9DS1_EVERY_4_SAMPLES = 2, LSM9DS1_EVERY_8_SAMPLES = 3, } lsm9ds1_dec_t; -int32_t lsm9ds1_xl_decimation_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_decimation_set(const stmdev_ctx_t *ctx, lsm9ds1_dec_t val); -int32_t lsm9ds1_xl_decimation_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_decimation_get(const stmdev_ctx_t *ctx, lsm9ds1_dec_t *val); typedef enum @@ -1084,18 +1084,18 @@ typedef enum LSM9DS1_4g = 2, LSM9DS1_8g = 3, } lsm9ds1_xl_fs_t; -int32_t lsm9ds1_xl_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_full_scale_set(const stmdev_ctx_t *ctx, lsm9ds1_xl_fs_t val); -int32_t lsm9ds1_xl_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_full_scale_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_fs_t *val); -int32_t lsm9ds1_block_data_update_set(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_block_data_update_set(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, uint8_t val); -int32_t lsm9ds1_block_data_update_get(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_block_data_update_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, uint8_t *val); -int32_t lsm9ds1_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm9ds1_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm9ds1_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm9ds1_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val); typedef enum { @@ -1138,9 +1138,9 @@ typedef enum LSM9DS1_MAG_LP_1000Hz = 0x08, LSM9DS1_MAG_ONE_SHOT = 0x70, } lsm9ds1_mag_data_rate_t; -int32_t lsm9ds1_mag_data_rate_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_mag_data_rate_set(const stmdev_ctx_t *ctx, lsm9ds1_mag_data_rate_t val); -int32_t lsm9ds1_mag_data_rate_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_mag_data_rate_get(const stmdev_ctx_t *ctx, lsm9ds1_mag_data_rate_t *val); typedef enum @@ -1150,23 +1150,23 @@ typedef enum LSM9DS1_12Ga = 2, LSM9DS1_16Ga = 3, } lsm9ds1_mag_fs_t; -int32_t lsm9ds1_mag_full_scale_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_mag_full_scale_set(const stmdev_ctx_t *ctx, lsm9ds1_mag_fs_t val); -int32_t lsm9ds1_mag_full_scale_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_mag_full_scale_get(const stmdev_ctx_t *ctx, lsm9ds1_mag_fs_t *val); -int32_t lsm9ds1_mag_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_mag_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm9ds1_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm9ds1_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm9ds1_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm9ds1_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm9ds1_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm9ds1_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm9ds1_magnetic_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t lsm9ds1_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t lsm9ds1_magnetic_overflow_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_magnetic_overflow_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct @@ -1174,7 +1174,7 @@ typedef struct uint8_t imu; uint8_t mag; } lsm9ds1_id_t; -int32_t lsm9ds1_dev_id_get(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_dev_id_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_id_t *buff); @@ -1183,14 +1183,14 @@ typedef struct lsm9ds1_status_reg_m_t status_mag; lsm9ds1_status_reg_t status_imu; } lsm9ds1_status_t; -int32_t lsm9ds1_dev_status_get(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_dev_status_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_status_t *val); -int32_t lsm9ds1_dev_reset_set(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_dev_reset_set(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, uint8_t val); -int32_t lsm9ds1_dev_reset_get(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_dev_reset_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, uint8_t *val); @@ -1199,23 +1199,23 @@ typedef enum LSM9DS1_LSB_LOW_ADDRESS = 0, LSM9DS1_MSB_LOW_ADDRESS = 1, } lsm9ds1_ble_t; -int32_t lsm9ds1_dev_data_format_set(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_dev_data_format_set(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_ble_t val); -int32_t lsm9ds1_dev_data_format_get(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_dev_data_format_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_ble_t *val); -int32_t lsm9ds1_dev_boot_set(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_dev_boot_set(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, uint8_t val); -int32_t lsm9ds1_dev_boot_get(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_dev_boot_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, uint8_t *val); -int32_t lsm9ds1_gy_filter_reference_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_filter_reference_set(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm9ds1_gy_filter_reference_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_filter_reference_get(const stmdev_ctx_t *ctx, uint8_t *buff); typedef enum @@ -1225,9 +1225,9 @@ typedef enum LSM9DS1_LP_LIGHT = 2, LSM9DS1_LP_ULTRA_LIGHT = 3, } lsm9ds1_gy_lp_bw_t; -int32_t lsm9ds1_gy_filter_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_filter_lp_bandwidth_set(const stmdev_ctx_t *ctx, lsm9ds1_gy_lp_bw_t val); -int32_t lsm9ds1_gy_filter_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_filter_lp_bandwidth_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_lp_bw_t *val); typedef enum @@ -1237,9 +1237,9 @@ typedef enum LSM9DS1_LPF1_LPF2_OUT = 0x02, LSM9DS1_LPF1_HPF_LPF2_OUT = 0x12, } lsm9ds1_gy_out_path_t; -int32_t lsm9ds1_gy_filter_out_path_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_filter_out_path_set(const stmdev_ctx_t *ctx, lsm9ds1_gy_out_path_t val); -int32_t lsm9ds1_gy_filter_out_path_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_filter_out_path_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_out_path_t *val); typedef enum @@ -1249,9 +1249,9 @@ typedef enum LSM9DS1_LPF1_LPF2_INT = 0x02, LSM9DS1_LPF1_HPF_LPF2_INT = 0x12, } lsm9ds1_gy_int_path_t; -int32_t lsm9ds1_gy_filter_int_path_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_filter_int_path_set(const stmdev_ctx_t *ctx, lsm9ds1_gy_int_path_t val); -int32_t lsm9ds1_gy_filter_int_path_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_filter_int_path_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_int_path_t *val); typedef enum @@ -1267,9 +1267,9 @@ typedef enum LSM9DS1_HP_LIGHT = 8, LSM9DS1_HP_ULTRA_LIGHT = 9, } lsm9ds1_gy_hp_bw_t; -int32_t lsm9ds1_gy_filter_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_filter_hp_bandwidth_set(const stmdev_ctx_t *ctx, lsm9ds1_gy_hp_bw_t val); -int32_t lsm9ds1_gy_filter_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_filter_hp_bandwidth_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_hp_bw_t *val); typedef enum @@ -1280,18 +1280,18 @@ typedef enum LSM9DS1_105Hz = 0x12, LSM9DS1_50Hz = 0x13, } lsm9ds1_xl_aa_bw_t; -int32_t lsm9ds1_xl_filter_aalias_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_filter_aalias_bandwidth_set(const stmdev_ctx_t *ctx, lsm9ds1_xl_aa_bw_t val); -int32_t lsm9ds1_xl_filter_aalias_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_filter_aalias_bandwidth_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_aa_bw_t *val); typedef enum { LSM9DS1_HP_DIS = 0, LSM9DS1_HP_EN = 1, } lsm9ds1_xl_hp_path_t; -int32_t lsm9ds1_xl_filter_int_path_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_filter_int_path_set(const stmdev_ctx_t *ctx, lsm9ds1_xl_hp_path_t val); -int32_t lsm9ds1_xl_filter_int_path_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_filter_int_path_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_hp_path_t *val); typedef enum @@ -1299,9 +1299,9 @@ typedef enum LSM9DS1_LP_OUT = 0, LSM9DS1_HP_OUT = 1, } lsm9ds1_xl_out_path_t; -int32_t lsm9ds1_xl_filter_out_path_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_filter_out_path_set(const stmdev_ctx_t *ctx, lsm9ds1_xl_out_path_t val); -int32_t lsm9ds1_xl_filter_out_path_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_filter_out_path_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_out_path_t *val); typedef enum @@ -1312,9 +1312,9 @@ typedef enum LSM9DS1_LP_ODR_DIV_9 = 0x12, LSM9DS1_LP_ODR_DIV_400 = 0x13, } lsm9ds1_xl_lp_bw_t; -int32_t lsm9ds1_xl_filter_lp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_filter_lp_bandwidth_set(const stmdev_ctx_t *ctx, lsm9ds1_xl_lp_bw_t val); -int32_t lsm9ds1_xl_filter_lp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_filter_lp_bandwidth_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_lp_bw_t *val); typedef enum @@ -1324,28 +1324,28 @@ typedef enum LSM9DS1_HP_ODR_DIV_9 = 2, LSM9DS1_HP_ODR_DIV_400 = 3, } lsm9ds1_xl_hp_bw_t; -int32_t lsm9ds1_xl_filter_hp_bandwidth_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_filter_hp_bandwidth_set(const stmdev_ctx_t *ctx, lsm9ds1_xl_hp_bw_t val); -int32_t lsm9ds1_xl_filter_hp_bandwidth_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_filter_hp_bandwidth_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_hp_bw_t *val); -int32_t lsm9ds1_filter_settling_mask_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm9ds1_filter_settling_mask_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm9ds1_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm9ds1_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm9ds1_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm9ds1_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM9DS1_SPI_4_WIRE = 0, LSM9DS1_SPI_3_WIRE = 1, } lsm9ds1_sim_t; -int32_t lsm9ds1_spi_mode_set(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_spi_mode_set(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_sim_t val); -int32_t lsm9ds1_spi_mode_get(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_spi_mode_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_sim_t *val); @@ -1354,10 +1354,10 @@ typedef enum LSM9DS1_I2C_ENABLE = 0, LSM9DS1_I2C_DISABLE = 1, } lsm9ds1_i2c_dis_t; -int32_t lsm9ds1_i2c_interface_set(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_i2c_interface_set(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_i2c_dis_t val); -int32_t lsm9ds1_i2c_interface_get(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_i2c_interface_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_i2c_dis_t *val); @@ -1366,9 +1366,9 @@ typedef enum LSM9DS1_LOGIC_OR = 0, LSM9DS1_LOGIC_AND = 1, } lsm9ds1_pin_logic_t; -int32_t lsm9ds1_pin_logic_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_pin_logic_set(const stmdev_ctx_t *ctx, lsm9ds1_pin_logic_t val); -int32_t lsm9ds1_pin_logic_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_pin_logic_get(const stmdev_ctx_t *ctx, lsm9ds1_pin_logic_t *val); typedef struct @@ -1382,9 +1382,9 @@ typedef struct uint8_t int1_ig_xl : 1; uint8_t int1_ig_g : 1; } lsm9ds1_pin_int1_route_t; -int32_t lsm9ds1_pin_int1_route_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_pin_int1_route_set(const stmdev_ctx_t *ctx, lsm9ds1_pin_int1_route_t val); -int32_t lsm9ds1_pin_int1_route_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_pin_int1_route_get(const stmdev_ctx_t *ctx, lsm9ds1_pin_int1_route_t *val); typedef struct { @@ -1396,9 +1396,9 @@ typedef struct uint8_t int2_fss5 : 1; uint8_t int2_inact : 1; } lsm9ds1_pin_int2_route_t; -int32_t lsm9ds1_pin_int2_route_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_pin_int2_route_set(const stmdev_ctx_t *ctx, lsm9ds1_pin_int2_route_t val); -int32_t lsm9ds1_pin_int2_route_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_pin_int2_route_get(const stmdev_ctx_t *ctx, lsm9ds1_pin_int2_route_t *val); typedef enum @@ -1406,10 +1406,10 @@ typedef enum LSM9DS1_INT_PULSED = 0, LSM9DS1_INT_LATCHED = 1, } lsm9ds1_lir_t; -int32_t lsm9ds1_pin_notification_set(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_pin_notification_set(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_lir_t val); -int32_t lsm9ds1_pin_notification_get(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_pin_notification_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_lir_t *val); @@ -1418,26 +1418,26 @@ typedef enum LSM9DS1_PUSH_PULL = 0, LSM9DS1_OPEN_DRAIN = 1, } lsm9ds1_pp_od_t; -int32_t lsm9ds1_pin_mode_set(stmdev_ctx_t *ctx, lsm9ds1_pp_od_t val); -int32_t lsm9ds1_pin_mode_get(stmdev_ctx_t *ctx, lsm9ds1_pp_od_t *val); +int32_t lsm9ds1_pin_mode_set(const stmdev_ctx_t *ctx, lsm9ds1_pp_od_t val); +int32_t lsm9ds1_pin_mode_get(const stmdev_ctx_t *ctx, lsm9ds1_pp_od_t *val); typedef struct { uint8_t ien : 1; } lsm9ds1_pin_m_route_t; -int32_t lsm9ds1_pin_int_m_route_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_pin_int_m_route_set(const stmdev_ctx_t *ctx, lsm9ds1_pin_m_route_t val); -int32_t lsm9ds1_pin_int_m_route_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_pin_int_m_route_get(const stmdev_ctx_t *ctx, lsm9ds1_pin_m_route_t *val); typedef enum { LSM9DS1_ACTIVE_LOW = 0, LSM9DS1_ACTIVE_HIGH = 1, } lsm9ds1_polarity_t; -int32_t lsm9ds1_pin_polarity_set(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_pin_polarity_set(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_polarity_t val); -int32_t lsm9ds1_pin_polarity_get(stmdev_ctx_t *ctx_mag, +int32_t lsm9ds1_pin_polarity_get(const stmdev_ctx_t *ctx_mag, stmdev_ctx_t *ctx_imu, lsm9ds1_polarity_t *val); @@ -1450,17 +1450,17 @@ typedef struct uint8_t zlie_xl : 1; uint8_t zhie_xl : 1; } lsm9ds1_xl_trshld_en_t; -int32_t lsm9ds1_xl_trshld_axis_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_trshld_axis_set(const stmdev_ctx_t *ctx, lsm9ds1_xl_trshld_en_t val); -int32_t lsm9ds1_xl_trshld_axis_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_trshld_axis_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_trshld_en_t *val); -int32_t lsm9ds1_xl_trshld_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm9ds1_xl_trshld_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm9ds1_xl_trshld_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm9ds1_xl_trshld_get(const stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm9ds1_xl_trshld_min_sample_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_trshld_min_sample_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm9ds1_xl_trshld_min_sample_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_trshld_min_sample_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct @@ -1473,7 +1473,7 @@ typedef struct uint8_t zh_g : 1; uint8_t ia_g : 1; } lsm9ds1_gy_trshld_src_t; -int32_t lsm9ds1_gy_trshld_src_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_trshld_src_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_trshld_src_t *val); typedef struct @@ -1486,7 +1486,7 @@ typedef struct uint8_t zh_xl : 1; uint8_t ia_xl : 1; } lsm9ds1_xl_trshld_src_t; -int32_t lsm9ds1_xl_trshld_src_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_xl_trshld_src_get(const stmdev_ctx_t *ctx, lsm9ds1_xl_trshld_src_t *val); typedef struct @@ -1498,9 +1498,9 @@ typedef struct uint8_t zlie_g : 1; uint8_t zhie_g : 1; } lsm9ds1_gy_trshld_en_t; -int32_t lsm9ds1_gy_trshld_axis_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_trshld_axis_set(const stmdev_ctx_t *ctx, lsm9ds1_gy_trshld_en_t val); -int32_t lsm9ds1_gy_trshld_axis_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_trshld_axis_get(const stmdev_ctx_t *ctx, lsm9ds1_gy_trshld_en_t *val); typedef enum @@ -1508,23 +1508,23 @@ typedef enum LSM9DS1_RESET_MODE = 0, LSM9DS1_DECREMENT_MODE = 1, } lsm9ds1_dcrm_g_t; -int32_t lsm9ds1_gy_trshld_mode_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_trshld_mode_set(const stmdev_ctx_t *ctx, lsm9ds1_dcrm_g_t val); -int32_t lsm9ds1_gy_trshld_mode_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_trshld_mode_get(const stmdev_ctx_t *ctx, lsm9ds1_dcrm_g_t *val); -int32_t lsm9ds1_gy_trshld_x_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm9ds1_gy_trshld_x_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm9ds1_gy_trshld_x_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm9ds1_gy_trshld_x_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm9ds1_gy_trshld_y_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm9ds1_gy_trshld_y_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm9ds1_gy_trshld_y_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm9ds1_gy_trshld_y_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm9ds1_gy_trshld_z_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t lsm9ds1_gy_trshld_z_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t lsm9ds1_gy_trshld_z_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm9ds1_gy_trshld_z_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t lsm9ds1_gy_trshld_min_sample_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_trshld_min_sample_set(const stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm9ds1_gy_trshld_min_sample_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_gy_trshld_min_sample_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct @@ -1533,9 +1533,9 @@ typedef struct uint8_t yien : 1; uint8_t xien : 1; } lsm9ds1_mag_trshld_axis_t; -int32_t lsm9ds1_mag_trshld_axis_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_mag_trshld_axis_set(const stmdev_ctx_t *ctx, lsm9ds1_mag_trshld_axis_t val); -int32_t lsm9ds1_mag_trshld_axis_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_mag_trshld_axis_get(const stmdev_ctx_t *ctx, lsm9ds1_mag_trshld_axis_t *val); typedef struct { @@ -1547,34 +1547,34 @@ typedef struct uint8_t pth_y : 1; uint8_t pth_x : 1; } lsm9ds1_mag_trshld_src_t; -int32_t lsm9ds1_mag_trshld_src_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_mag_trshld_src_get(const stmdev_ctx_t *ctx, lsm9ds1_mag_trshld_src_t *val); -int32_t lsm9ds1_mag_trshld_set(stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm9ds1_mag_trshld_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm9ds1_mag_trshld_set(const stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm9ds1_mag_trshld_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm9ds1_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm9ds1_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm9ds1_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm9ds1_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { LSM9DS1_GYRO_POWER_DOWN = 0, LSM9DS1_GYRO_SLEEP = 1, } lsm9ds1_act_mode_t; -int32_t lsm9ds1_act_mode_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_act_mode_set(const stmdev_ctx_t *ctx, lsm9ds1_act_mode_t val); -int32_t lsm9ds1_act_mode_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_act_mode_get(const stmdev_ctx_t *ctx, lsm9ds1_act_mode_t *val); -int32_t lsm9ds1_act_duration_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm9ds1_act_duration_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm9ds1_act_duration_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm9ds1_act_duration_get(const stmdev_ctx_t *ctx, uint8_t *buff); typedef enum { LSM9DS1_ACTIVITY = 0, LSM9DS1_INACTIVITY = 1, } lsm9ds1_inact_t; -int32_t lsm9ds1_act_src_get(stmdev_ctx_t *ctx, lsm9ds1_inact_t *val); +int32_t lsm9ds1_act_src_get(const stmdev_ctx_t *ctx, lsm9ds1_inact_t *val); typedef enum { @@ -1584,12 +1584,12 @@ typedef enum LSM9DS1_6D_POS_RECO = 0x03, LSM9DS1_4D_POS_RECO = 0x07, } lsm9ds1_6d_mode_t; -int32_t lsm9ds1_6d_mode_set(stmdev_ctx_t *ctx, lsm9ds1_6d_mode_t val); -int32_t lsm9ds1_6d_mode_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_6d_mode_set(const stmdev_ctx_t *ctx, lsm9ds1_6d_mode_t val); +int32_t lsm9ds1_6d_mode_get(const stmdev_ctx_t *ctx, lsm9ds1_6d_mode_t *val); -int32_t lsm9ds1_6d_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff); -int32_t lsm9ds1_6d_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm9ds1_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm9ds1_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *buff); typedef struct { @@ -1601,10 +1601,10 @@ typedef struct uint8_t zh_xl : 1; uint8_t ia_xl : 1; } lsm9ds1_6d_src_t; -int32_t lsm9ds1_6d_src_get(stmdev_ctx_t *ctx, lsm9ds1_6d_src_t *val); +int32_t lsm9ds1_6d_src_get(const stmdev_ctx_t *ctx, lsm9ds1_6d_src_t *val); -int32_t lsm9ds1_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm9ds1_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm9ds1_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm9ds1_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -1615,33 +1615,33 @@ typedef enum LSM9DS1_BYPASS_TO_STREAM_MODE = 0x14, LSM9DS1_STREAM_MODE = 0x16, } lsm9ds1_fifo_md_t; -int32_t lsm9ds1_fifo_mode_set(stmdev_ctx_t *ctx, +int32_t lsm9ds1_fifo_mode_set(const stmdev_ctx_t *ctx, lsm9ds1_fifo_md_t val); -int32_t lsm9ds1_fifo_mode_get(stmdev_ctx_t *ctx, +int32_t lsm9ds1_fifo_mode_get(const stmdev_ctx_t *ctx, lsm9ds1_fifo_md_t *val); -int32_t lsm9ds1_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm9ds1_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm9ds1_fifo_temp_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm9ds1_fifo_temp_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm9ds1_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm9ds1_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm9ds1_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm9ds1_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm9ds1_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm9ds1_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm9ds1_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm9ds1_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm9ds1_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm9ds1_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm9ds1_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm9ds1_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm9ds1_xl_self_test_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm9ds1_xl_self_test_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm9ds1_xl_self_test_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm9ds1_xl_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm9ds1_gy_self_test_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm9ds1_gy_self_test_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm9ds1_gy_self_test_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm9ds1_gy_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t lsm9ds1_mag_self_test_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t lsm9ds1_mag_self_test_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t lsm9ds1_mag_self_test_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm9ds1_mag_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val); /** *@} * diff --git a/sensor/stmemsc/st1vafe6ax_STdC/driver/st1vafe6ax_reg.c b/sensor/stmemsc/st1vafe6ax_STdC/driver/st1vafe6ax_reg.c new file mode 100644 index 00000000..8d2e1f68 --- /dev/null +++ b/sensor/stmemsc/st1vafe6ax_STdC/driver/st1vafe6ax_reg.c @@ -0,0 +1,7948 @@ +/** + ****************************************************************************** + * @file st1vafe6ax_reg.c + * @author Sensors Software Solution Team + * @brief ST1VAFE6AX driver file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2024 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "st1vafe6ax_reg.h" + +/** + * @defgroup ST1VAFE6AX + * @brief This file provides a set of functions needed to drive the + * st1vafe6ax enhanced inertial module. + * @{ + * + */ + +/** + * @defgroup Interfaces functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +/** + * @brief Read generic device register + * + * @param ctx communication interface handler.(ptr) + * @param reg first register address to read. + * @param data buffer for data read.(ptr) + * @param len number of consecutive register to read. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak st1vafe6ax_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) +{ + int32_t ret; + + if (ctx == NULL) + { + return -1; + } + + ret = ctx->read_reg(ctx->handle, reg, data, len); + + return ret; +} + +/** + * @brief Write generic device register + * + * @param ctx communication interface handler.(ptr) + * @param reg first register address to write. + * @param data the buffer contains data to be written.(ptr) + * @param len number of consecutive register to write. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t __weak st1vafe6ax_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len) +{ + int32_t ret; + + if (ctx == NULL) + { + return -1; + } + + ret = ctx->write_reg(ctx->handle, reg, data, len); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Private functions + * @brief Section collect all the utility functions needed by APIs. + * @{ + * + */ + +static void bytecpy(uint8_t *target, uint8_t *source) +{ + if ((target != NULL) && (source != NULL)) + { + *target = *source; + } +} + +/** + * @} + * + */ + +/** + * @defgroup Sensitivity + * @brief These functions convert raw-data into engineering units. + * @{ + * + */ +float_t st1vafe6ax_from_sflp_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.061f; +} + +float_t st1vafe6ax_from_fs2_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.061f; +} + +float_t st1vafe6ax_from_fs4_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.122f; +} + +float_t st1vafe6ax_from_fs8_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.244f; +} + +float_t st1vafe6ax_from_fs16_to_mg(int16_t lsb) +{ + return ((float_t)lsb) * 0.488f; +} + +float_t st1vafe6ax_from_fs125_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 4.375f; +} + +float_t st1vafe6ax_from_fs250_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 8.750f; +} + +float_t st1vafe6ax_from_fs500_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 17.50f; +} + +float_t st1vafe6ax_from_fs1000_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 35.0f; +} + +float_t st1vafe6ax_from_fs2000_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 70.0f; +} + +float_t st1vafe6ax_from_fs4000_to_mdps(int16_t lsb) +{ + return ((float_t)lsb) * 140.0f; +} + +float_t st1vafe6ax_from_lsb_to_celsius(int16_t lsb) +{ + return (((float_t)lsb / 256.0f) + 25.0f); +} + +uint64_t st1vafe6ax_from_lsb_to_nsec(uint32_t lsb) +{ + return ((uint64_t)lsb * 21750); +} + +float_t st1vafe6ax_from_lsb_to_mv(int16_t lsb) +{ + return ((float_t)lsb) / 78.0f; +} + +/** + * @} + * + */ + +/** + * @defgroup Common + * @brief This section groups common useful functions. + * + */ + +/** + * @brief Reset of the device.[set] + * + * @param ctx read / write interface definitions + * @param val Reset of the device. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_reset_set(const stmdev_ctx_t *ctx, st1vafe6ax_reset_t val) +{ + st1vafe6ax_func_cfg_access_t func_cfg_access; + st1vafe6ax_ctrl3_t ctrl3; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + ctrl3.boot = ((uint8_t)val & 0x04U) >> 2; + ctrl3.sw_reset = ((uint8_t)val & 0x02U) >> 1; + func_cfg_access.sw_por = (uint8_t)val & 0x01U; + + if (ret == 0) + { + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL3, (uint8_t *)&ctrl3, 1); + } + if (ret == 0) + { + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Global reset of the device.[get] + * + * @param ctx read / write interface definitions + * @param val Global reset of the device. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_reset_get(const stmdev_ctx_t *ctx, st1vafe6ax_reset_t *val) +{ + st1vafe6ax_func_cfg_access_t func_cfg_access; + st1vafe6ax_ctrl3_t ctrl3; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + switch ((ctrl3.sw_reset << 2) + (ctrl3.boot << 1) + func_cfg_access.sw_por) + { + case ST1VAFE6AX_READY: + *val = ST1VAFE6AX_READY; + break; + + case ST1VAFE6AX_GLOBAL_RST: + *val = ST1VAFE6AX_GLOBAL_RST; + break; + + case ST1VAFE6AX_RESTORE_CAL_PARAM: + *val = ST1VAFE6AX_RESTORE_CAL_PARAM; + break; + + case ST1VAFE6AX_RESTORE_CTRL_REGS: + *val = ST1VAFE6AX_RESTORE_CTRL_REGS; + break; + + default: + *val = ST1VAFE6AX_GLOBAL_RST; + break; + } + return ret; +} + +/** + * @brief Change memory bank.[set] + * + * @param ctx read / write interface definitions + * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_mem_bank_set(const stmdev_ctx_t *ctx, st1vafe6ax_mem_bank_t val) +{ + st1vafe6ax_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret == 0) + { + func_cfg_access.emb_func_reg_access = (uint8_t)val & 0x01U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Change memory bank.[get] + * + * @param ctx read / write interface definitions + * @param val MAIN_MEM_BANK, SENSOR_HUB_MEM_BANK, EMBED_FUNC_MEM_BANK, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_mem_bank_get(const stmdev_ctx_t *ctx, st1vafe6ax_mem_bank_t *val) +{ + st1vafe6ax_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + + switch (func_cfg_access.emb_func_reg_access) + { + case ST1VAFE6AX_MAIN_MEM_BANK: + *val = ST1VAFE6AX_MAIN_MEM_BANK; + break; + + case ST1VAFE6AX_EMBED_FUNC_MEM_BANK: + *val = ST1VAFE6AX_EMBED_FUNC_MEM_BANK; + break; + + default: + *val = ST1VAFE6AX_MAIN_MEM_BANK; + break; + } + return ret; +} + +/** + * @brief Device ID.[get] + * + * @param ctx read / write interface definitions + * @param val Device ID. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + st1vafe6ax_who_am_i_t who_am_i; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_WHO_AM_I, (uint8_t *)&who_am_i, 1); + *val = who_am_i.id; + + return ret; +} + +/** + * @brief Accelerometer output data rate (ODR) selection.[set] + * + * @param ctx read / write interface definitions + * @param val st1vafe6ax_xl_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_xl_data_rate_set(const stmdev_ctx_t *ctx, + st1vafe6ax_xl_data_rate_t val) +{ + st1vafe6ax_ctrl1_t ctrl1; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL1, (uint8_t *)&ctrl1, 1); + if (ret == 0) + { + ctrl1.odr_xl = (uint8_t)val & 0xFU; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL1, (uint8_t *)&ctrl1, 1); + } + + return ret; +} + +/** + * @brief Accelerometer output data rate (ODR) selection.[get] + * + * @param ctx read / write interface definitions + * @param val st1vafe6ax_xl_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_xl_data_rate_get(const stmdev_ctx_t *ctx, + st1vafe6ax_xl_data_rate_t *val) +{ + st1vafe6ax_ctrl1_t ctrl1; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL1, (uint8_t *)&ctrl1, 1); + + switch (ctrl1.odr_xl) + { + case ST1VAFE6AX_XL_ODR_OFF: + *val = ST1VAFE6AX_XL_ODR_OFF; + break; + + case ST1VAFE6AX_XL_ODR_AT_1Hz875: + *val = ST1VAFE6AX_XL_ODR_AT_1Hz875; + break; + + case ST1VAFE6AX_XL_ODR_AT_7Hz5: + *val = ST1VAFE6AX_XL_ODR_AT_7Hz5; + break; + + case ST1VAFE6AX_XL_ODR_AT_15Hz: + *val = ST1VAFE6AX_XL_ODR_AT_15Hz; + break; + + case ST1VAFE6AX_XL_ODR_AT_30Hz: + *val = ST1VAFE6AX_XL_ODR_AT_30Hz; + break; + + case ST1VAFE6AX_XL_ODR_AT_60Hz: + *val = ST1VAFE6AX_XL_ODR_AT_60Hz; + break; + + case ST1VAFE6AX_XL_ODR_AT_120Hz: + *val = ST1VAFE6AX_XL_ODR_AT_120Hz; + break; + + case ST1VAFE6AX_XL_ODR_AT_240Hz: + *val = ST1VAFE6AX_XL_ODR_AT_240Hz; + break; + + case ST1VAFE6AX_XL_ODR_AT_480Hz: + *val = ST1VAFE6AX_XL_ODR_AT_480Hz; + break; + + case ST1VAFE6AX_XL_ODR_AT_960Hz: + *val = ST1VAFE6AX_XL_ODR_AT_960Hz; + break; + + case ST1VAFE6AX_XL_ODR_AT_1920Hz: + *val = ST1VAFE6AX_XL_ODR_AT_1920Hz; + break; + + case ST1VAFE6AX_XL_ODR_AT_3840Hz: + *val = ST1VAFE6AX_XL_ODR_AT_3840Hz; + break; + + default: + *val = ST1VAFE6AX_XL_ODR_OFF; + break; + } + return ret; +} + +/** + * @brief Accelerometer operating mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val st1vafe6ax_xl_mode_t struct + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_xl_mode_set(const stmdev_ctx_t *ctx, st1vafe6ax_xl_mode_t val) +{ + st1vafe6ax_ctrl1_t ctrl1; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL1, (uint8_t *)&ctrl1, 1); + + if (ret == 0) + { + ctrl1.op_mode_xl = (uint8_t)val & 0x07U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL1, (uint8_t *)&ctrl1, 1); + } + + return ret; +} + +/** + * @brief Accelerometer operating mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val st1vafe6ax_xl_mode_t struct + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_xl_mode_get(const stmdev_ctx_t *ctx, st1vafe6ax_xl_mode_t *val) +{ + st1vafe6ax_ctrl1_t ctrl1; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL1, (uint8_t *)&ctrl1, 1); + + switch (ctrl1.op_mode_xl) + { + case ST1VAFE6AX_XL_HIGH_PERFORMANCE_MD: + *val = ST1VAFE6AX_XL_HIGH_PERFORMANCE_MD; + break; + + case ST1VAFE6AX_XL_HIGH_PERFORMANCE_2_MD: + *val = ST1VAFE6AX_XL_HIGH_PERFORMANCE_2_MD; + break; + + case ST1VAFE6AX_XL_LOW_POWER_2_AVG_MD: + *val = ST1VAFE6AX_XL_LOW_POWER_2_AVG_MD; + break; + + case ST1VAFE6AX_XL_LOW_POWER_4_AVG_MD: + *val = ST1VAFE6AX_XL_LOW_POWER_4_AVG_MD; + break; + + case ST1VAFE6AX_XL_LOW_POWER_8_AVG_MD: + *val = ST1VAFE6AX_XL_LOW_POWER_8_AVG_MD; + break; + + default: + *val = ST1VAFE6AX_XL_HIGH_PERFORMANCE_MD; + break; + } + return ret; +} + +/** + * @brief Gyroscope output data rate (ODR) selection.[set] + * + * @param ctx read / write interface definitions + * @param val st1vafe6ax_gy_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_gy_data_rate_set(const stmdev_ctx_t *ctx, + st1vafe6ax_gy_data_rate_t val) +{ + st1vafe6ax_ctrl2_t ctrl2; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL2, (uint8_t *)&ctrl2, 1); + + if (ret == 0) + { + ctrl2.odr_g = (uint8_t)val & 0xFU; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL2, (uint8_t *)&ctrl2, 1); + } + + return ret; +} + +/** + * @brief Gyroscope output data rate (ODR) selection.[get] + * + * @param ctx read / write interface definitions + * @param val st1vafe6ax_gy_data_rate_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_gy_data_rate_get(const stmdev_ctx_t *ctx, + st1vafe6ax_gy_data_rate_t *val) +{ + st1vafe6ax_ctrl2_t ctrl2; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL2, (uint8_t *)&ctrl2, 1); + + switch (ctrl2.odr_g) + { + case ST1VAFE6AX_GY_ODR_OFF: + *val = ST1VAFE6AX_GY_ODR_OFF; + break; + + case ST1VAFE6AX_GY_ODR_AT_7Hz5: + *val = ST1VAFE6AX_GY_ODR_AT_7Hz5; + break; + + case ST1VAFE6AX_GY_ODR_AT_15Hz: + *val = ST1VAFE6AX_GY_ODR_AT_15Hz; + break; + + case ST1VAFE6AX_GY_ODR_AT_30Hz: + *val = ST1VAFE6AX_GY_ODR_AT_30Hz; + break; + + case ST1VAFE6AX_GY_ODR_AT_60Hz: + *val = ST1VAFE6AX_GY_ODR_AT_60Hz; + break; + + case ST1VAFE6AX_GY_ODR_AT_120Hz: + *val = ST1VAFE6AX_GY_ODR_AT_120Hz; + break; + + case ST1VAFE6AX_GY_ODR_AT_240Hz: + *val = ST1VAFE6AX_GY_ODR_AT_240Hz; + break; + + case ST1VAFE6AX_GY_ODR_AT_480Hz: + *val = ST1VAFE6AX_GY_ODR_AT_480Hz; + break; + + case ST1VAFE6AX_GY_ODR_AT_960Hz: + *val = ST1VAFE6AX_GY_ODR_AT_960Hz; + break; + + case ST1VAFE6AX_GY_ODR_AT_1920Hz: + *val = ST1VAFE6AX_GY_ODR_AT_1920Hz; + break; + + case ST1VAFE6AX_GY_ODR_AT_3840Hz: + *val = ST1VAFE6AX_GY_ODR_AT_3840Hz; + break; + + default: + *val = ST1VAFE6AX_GY_ODR_OFF; + break; + } + return ret; +} + +/** + * @brief Gyroscope operating mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURANCY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_gy_mode_set(const stmdev_ctx_t *ctx, st1vafe6ax_gy_mode_t val) +{ + st1vafe6ax_ctrl2_t ctrl2; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL2, (uint8_t *)&ctrl2, 1); + if (ret == 0) + { + ctrl2.op_mode_g = (uint8_t)val & 0x07U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL2, (uint8_t *)&ctrl2, 1); + } + + return ret; +} + +/** + * @brief Gyroscope operating mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURANCY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_gy_mode_get(const stmdev_ctx_t *ctx, st1vafe6ax_gy_mode_t *val) +{ + st1vafe6ax_ctrl2_t ctrl2; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL2, (uint8_t *)&ctrl2, 1); + switch (ctrl2.op_mode_g) + { + case ST1VAFE6AX_GY_HIGH_PERFORMANCE_MD: + *val = ST1VAFE6AX_GY_HIGH_PERFORMANCE_MD; + break; + + case ST1VAFE6AX_GY_SLEEP_MD: + *val = ST1VAFE6AX_GY_SLEEP_MD; + break; + + case ST1VAFE6AX_GY_LOW_POWER_MD: + *val = ST1VAFE6AX_GY_LOW_POWER_MD; + break; + + default: + *val = ST1VAFE6AX_GY_HIGH_PERFORMANCE_MD; + break; + } + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[set] + * + * @param ctx read / write interface definitions + * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + st1vafe6ax_ctrl3_t ctrl3; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL3, (uint8_t *)&ctrl3, 1); + if (ret == 0) + { + ctrl3.if_inc = val; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL3, (uint8_t *)&ctrl3, 1); + } + + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[get] + * + * @param ctx read / write interface definitions + * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + st1vafe6ax_ctrl3_t ctrl3; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL3, (uint8_t *)&ctrl3, 1); + *val = ctrl3.if_inc; + + + return ret; +} + +/** + * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [set] + * + * @param ctx read / write interface definitions + * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + st1vafe6ax_ctrl3_t ctrl3; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL3, (uint8_t *)&ctrl3, 1); + + if (ret == 0) + { + ctrl3.bdu = val; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL3, (uint8_t *)&ctrl3, 1); + } + + return ret; +} + +/** + * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [get] + * + * @param ctx read / write interface definitions + * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + st1vafe6ax_ctrl3_t ctrl3; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL3, (uint8_t *)&ctrl3, 1); + *val = ctrl3.bdu; + + return ret; +} + +/** + * @brief Enables pulsed data-ready mode (~75 us).[set] + * + * @param ctx read / write interface definitions + * @param val DRDY_LATCHED, DRDY_PULSED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_data_ready_mode_set(const stmdev_ctx_t *ctx, + st1vafe6ax_data_ready_mode_t val) +{ + st1vafe6ax_ctrl4_t ctrl4; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL4, (uint8_t *)&ctrl4, 1); + + if (ret == 0) + { + ctrl4.drdy_pulsed = (uint8_t)val & 0x1U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL4, (uint8_t *)&ctrl4, 1); + } + + return ret; +} + +/** + * @brief Enables pulsed data-ready mode (~75 us).[get] + * + * @param ctx read / write interface definitions + * @param val DRDY_LATCHED, DRDY_PULSED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_data_ready_mode_get(const stmdev_ctx_t *ctx, + st1vafe6ax_data_ready_mode_t *val) +{ + st1vafe6ax_ctrl4_t ctrl4; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL4, (uint8_t *)&ctrl4, 1); + + switch (ctrl4.drdy_pulsed) + { + case ST1VAFE6AX_DRDY_LATCHED: + *val = ST1VAFE6AX_DRDY_LATCHED; + break; + + case ST1VAFE6AX_DRDY_PULSED: + *val = ST1VAFE6AX_DRDY_PULSED; + break; + + default: + *val = ST1VAFE6AX_DRDY_LATCHED; + break; + } + return ret; +} + +/** + * @brief Gyroscope full-scale selection[set] + * + * @param ctx read / write interface definitions + * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_gy_full_scale_set(const stmdev_ctx_t *ctx, + st1vafe6ax_gy_full_scale_t val) +{ + st1vafe6ax_ctrl6_t ctrl6; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL6, (uint8_t *)&ctrl6, 1); + + if (ret == 0) + { + ctrl6.fs_g = (uint8_t)val & 0xFU; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL6, (uint8_t *)&ctrl6, 1); + } + + return ret; +} + +/** + * @brief Gyroscope full-scale selection[get] + * + * @param ctx read / write interface definitions + * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_gy_full_scale_get(const stmdev_ctx_t *ctx, + st1vafe6ax_gy_full_scale_t *val) +{ + st1vafe6ax_ctrl6_t ctrl6; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL6, (uint8_t *)&ctrl6, 1); + + switch (ctrl6.fs_g) + { + case ST1VAFE6AX_125dps: + *val = ST1VAFE6AX_125dps; + break; + + case ST1VAFE6AX_250dps: + *val = ST1VAFE6AX_250dps; + break; + + case ST1VAFE6AX_500dps: + *val = ST1VAFE6AX_500dps; + break; + + case ST1VAFE6AX_1000dps: + *val = ST1VAFE6AX_1000dps; + break; + + case ST1VAFE6AX_2000dps: + *val = ST1VAFE6AX_2000dps; + break; + + case ST1VAFE6AX_4000dps: + *val = ST1VAFE6AX_4000dps; + break; + + default: + *val = ST1VAFE6AX_125dps; + break; + } + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[set] + * + * @param ctx read / write interface definitions + * @param val 2g, 4g, 8g, 16g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_xl_full_scale_set(const stmdev_ctx_t *ctx, + st1vafe6ax_xl_full_scale_t val) +{ + st1vafe6ax_ctrl8_t ctrl8; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL8, (uint8_t *)&ctrl8, 1); + + if (ret == 0) + { + ctrl8.fs_xl = (uint8_t)val & 0x3U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL8, (uint8_t *)&ctrl8, 1); + } + + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[get] + * + * @param ctx read / write interface definitions + * @param val 2g, 4g, 8g, 16g, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_xl_full_scale_get(const stmdev_ctx_t *ctx, + st1vafe6ax_xl_full_scale_t *val) +{ + st1vafe6ax_ctrl8_t ctrl8; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL8, (uint8_t *)&ctrl8, 1); + + switch (ctrl8.fs_xl) + { + case ST1VAFE6AX_2g: + *val = ST1VAFE6AX_2g; + break; + + case ST1VAFE6AX_4g: + *val = ST1VAFE6AX_4g; + break; + + case ST1VAFE6AX_8g: + *val = ST1VAFE6AX_8g; + break; + + default: + *val = ST1VAFE6AX_2g; + break; + } + return ret; +} + +/** + * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[set] + * + * @param ctx read / write interface definitions + * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_xl_dual_channel_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + st1vafe6ax_ctrl8_t ctrl8; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL8, (uint8_t *)&ctrl8, 1); + + if (ret == 0) + { + ctrl8.xl_dualc_en = val; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL8, (uint8_t *)&ctrl8, 1); + } + + return ret; +} + +/** + * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[get] + * + * @param ctx read / write interface definitions + * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + st1vafe6ax_ctrl8_t ctrl8; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL8, (uint8_t *)&ctrl8, 1); + *val = ctrl8.xl_dualc_en; + + return ret; +} + +/** + * @brief Accelerometer self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_xl_self_test_set(const stmdev_ctx_t *ctx, + st1vafe6ax_xl_self_test_t val) +{ + st1vafe6ax_ctrl10_t ctrl10; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL10, (uint8_t *)&ctrl10, 1); + + if (ret == 0) + { + ctrl10.st_xl = (uint8_t)val & 0x3U; + ctrl10.xl_st_offset = ((uint8_t)val & 0x04U) >> 2; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL10, (uint8_t *)&ctrl10, 1); + } + + return ret; +} + +/** + * @brief Accelerometer self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_xl_self_test_get(const stmdev_ctx_t *ctx, + st1vafe6ax_xl_self_test_t *val) +{ + st1vafe6ax_ctrl10_t ctrl10; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL10, (uint8_t *)&ctrl10, 1); + + //switch (ctrl10.xl_st_offset) + switch (ctrl10.st_xl) + { + case ST1VAFE6AX_XL_ST_DISABLE: + *val = ST1VAFE6AX_XL_ST_DISABLE; + break; + + case ST1VAFE6AX_XL_ST_POSITIVE: + *val = ST1VAFE6AX_XL_ST_POSITIVE; + break; + + case ST1VAFE6AX_XL_ST_NEGATIVE: + *val = ST1VAFE6AX_XL_ST_NEGATIVE; + break; + + default: + *val = ST1VAFE6AX_XL_ST_DISABLE; + break; + } + return ret; +} + +/** + * @brief Gyroscope self-test selection.[set] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_gy_self_test_set(const stmdev_ctx_t *ctx, + st1vafe6ax_gy_self_test_t val) +{ + st1vafe6ax_ctrl10_t ctrl10; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL10, (uint8_t *)&ctrl10, 1); + + if (ret == 0) + { + ctrl10.st_g = (uint8_t)val & 0x3U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL10, (uint8_t *)&ctrl10, 1); + } + + return ret; +} + +/** + * @brief Gyroscope self-test selection.[get] + * + * @param ctx read / write interface definitions + * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_gy_self_test_get(const stmdev_ctx_t *ctx, + st1vafe6ax_gy_self_test_t *val) +{ + st1vafe6ax_ctrl10_t ctrl10; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL10, (uint8_t *)&ctrl10, 1); + + switch (ctrl10.st_g) + { + case ST1VAFE6AX_GY_ST_DISABLE: + *val = ST1VAFE6AX_GY_ST_DISABLE; + break; + + case ST1VAFE6AX_GY_ST_POSITIVE: + *val = ST1VAFE6AX_GY_ST_POSITIVE; + break; + + case ST1VAFE6AX_GY_ST_NEGATIVE: + *val = ST1VAFE6AX_GY_ST_NEGATIVE; + break; + + default: + *val = ST1VAFE6AX_GY_ST_DISABLE; + break; + } + return ret; +} + +/** + * @brief Get the status of all the interrupt sources.[get] + * + * @param ctx read / write interface definitions + * @param val Get the status of all the interrupt sources. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_all_sources_get(const stmdev_ctx_t *ctx, + st1vafe6ax_all_sources_t *val) +{ + st1vafe6ax_emb_func_status_mainpage_t emb_func_status_mainpage; + st1vafe6ax_emb_func_exec_status_t emb_func_exec_status; + st1vafe6ax_fsm_status_mainpage_t fsm_status_mainpage; + st1vafe6ax_mlc_status_mainpage_t mlc_status_mainpage; + st1vafe6ax_functions_enable_t functions_enable; + st1vafe6ax_emb_func_src_t emb_func_src; + st1vafe6ax_fifo_status2_t fifo_status2; + st1vafe6ax_all_int_src_t all_int_src; + st1vafe6ax_wake_up_src_t wake_up_src; + st1vafe6ax_status_reg_t status_reg; + st1vafe6ax_d6d_src_t d6d_src; + st1vafe6ax_tap_src_t tap_src; + uint8_t buff[7]; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret == 0) + { + functions_enable.dis_rst_lir_all_int = PROPERTY_ENABLE; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_STATUS1, (uint8_t *)&buff, 4); + } + bytecpy((uint8_t *)&fifo_status2, &buff[1]); + bytecpy((uint8_t *)&all_int_src, &buff[2]); + bytecpy((uint8_t *)&status_reg, &buff[3]); + + val->fifo_ovr = fifo_status2.fifo_ovr_ia; + val->fifo_bdr = fifo_status2.counter_bdr_ia; + val->fifo_full = fifo_status2.fifo_full_ia; + val->fifo_th = fifo_status2.fifo_wtm_ia; + + val->free_fall = all_int_src.ff_ia; + val->wake_up = all_int_src.wu_ia; + val->six_d = all_int_src.d6d_ia; + + val->drdy_xl = status_reg.xlda; + val->drdy_gy = status_reg.gda; + val->drdy_temp = status_reg.tda; + val->drdy_ah_bio = status_reg.ah_bioda; + val->timestamp = status_reg.timestamp_endcount; + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + if (ret == 0) + { + functions_enable.dis_rst_lir_all_int = PROPERTY_DISABLE; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_WAKE_UP_SRC, (uint8_t *)&buff, 7); + } + + if (ret == 0) + { + bytecpy((uint8_t *)&wake_up_src, &buff[0]); + bytecpy((uint8_t *)&tap_src, &buff[1]); + bytecpy((uint8_t *)&d6d_src, &buff[2]); + bytecpy((uint8_t *)&emb_func_status_mainpage, &buff[4]); + bytecpy((uint8_t *)&fsm_status_mainpage, &buff[5]); + bytecpy((uint8_t *)&mlc_status_mainpage, &buff[6]); + + val->sleep_change = wake_up_src.sleep_change_ia; + val->wake_up_x = wake_up_src.x_wu; + val->wake_up_y = wake_up_src.y_wu; + val->wake_up_z = wake_up_src.z_wu; + val->sleep_state = wake_up_src.sleep_state; + + val->tap_x = tap_src.x_tap; + val->tap_y = tap_src.y_tap; + val->tap_z = tap_src.z_tap; + val->tap_sign = tap_src.tap_sign; + val->double_tap = tap_src.double_tap; + val->single_tap = tap_src.single_tap; + + val->six_d_zl = d6d_src.zl; + val->six_d_zh = d6d_src.zh; + val->six_d_yl = d6d_src.yl; + val->six_d_yh = d6d_src.yh; + val->six_d_xl = d6d_src.xl; + val->six_d_xh = d6d_src.xh; + + val->step_detector = emb_func_status_mainpage.is_step_det; + val->tilt = emb_func_status_mainpage.is_tilt; + val->sig_mot = emb_func_status_mainpage.is_sigmot; + val->fsm_lc = emb_func_status_mainpage.is_fsm_lc; + + val->fsm1 = fsm_status_mainpage.is_fsm1; + val->fsm2 = fsm_status_mainpage.is_fsm2; + val->fsm3 = fsm_status_mainpage.is_fsm3; + val->fsm4 = fsm_status_mainpage.is_fsm4; + val->fsm5 = fsm_status_mainpage.is_fsm5; + val->fsm6 = fsm_status_mainpage.is_fsm6; + val->fsm7 = fsm_status_mainpage.is_fsm7; + val->fsm8 = fsm_status_mainpage.is_fsm8; + + val->mlc1 = mlc_status_mainpage.is_mlc1; + val->mlc2 = mlc_status_mainpage.is_mlc2; + val->mlc3 = mlc_status_mainpage.is_mlc3; + val->mlc4 = mlc_status_mainpage.is_mlc4; + } + + + if (ret == 0) + { + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, + 1); + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + val->emb_func_stand_by = emb_func_exec_status.emb_func_endop; + val->emb_func_time_exceed = emb_func_exec_status.emb_func_exec_ovr; + val->step_count_inc = emb_func_src.stepcounter_bit_set; + val->step_count_overflow = emb_func_src.step_overflow; + val->step_on_delta_time = emb_func_src.step_count_delta_ia; + + val->step_detector = emb_func_src.step_detected; + + return ret; +} + +int32_t st1vafe6ax_flag_data_ready_get(const stmdev_ctx_t *ctx, + st1vafe6ax_data_ready_t *val) +{ + st1vafe6ax_status_reg_t status; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_STATUS_REG, (uint8_t *)&status, 1); + val->drdy_xl = status.xlda; + val->drdy_gy = status.gda; + val->drdy_temp = status.tda; + val->drdy_ah_bio = status.ah_bioda; + + return ret; +} + +/** + * @brief Temperature data output register[get] + * + * @param ctx read / write interface definitions + * @param val Temperature data output register + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_OUT_TEMP_L, &buff[0], 2); + *val = (int16_t)buff[1]; + *val = (*val * 256) + (int16_t)buff[0]; + + return ret; +} + +/** + * @brief Angular rate sensor.[get] + * + * @param ctx read / write interface definitions + * @param val Angular rate sensor. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_OUTX_L_G, &buff[0], 6); + val[0] = (int16_t)buff[1]; + val[0] = (val[0] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[2] = (int16_t)buff[5]; + val[2] = (val[2] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Linear acceleration sensor.[get] + * + * @param ctx read / write interface definitions + * @param val Linear acceleration sensor. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_OUTZ_L_A, &buff[0], 6); + val[2] = (int16_t)buff[1]; + val[2] = (val[2] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[0] = (int16_t)buff[5]; + val[0] = (val[0] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Linear acceleration sensor for Dual channel mode.[get] + * + * @param ctx read / write interface definitions + * @param val Linear acceleration sensor or Dual channel mode. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[6]; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_UI_OUTZ_L_A_DUALC, &buff[0], 6); + val[2] = (int16_t)buff[1]; + val[2] = (val[2] * 256) + (int16_t)buff[0]; + val[1] = (int16_t)buff[3]; + val[1] = (val[1] * 256) + (int16_t)buff[2]; + val[0] = (int16_t)buff[5]; + val[0] = (val[0] * 256) + (int16_t)buff[4]; + + return ret; +} + +/** + * @brief Bio data output register.[get] + * + * @param ctx read / write interface definitions + * @param val Bio data output register. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_ah_bio_raw_get(const stmdev_ctx_t *ctx, int16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_AH_BIO_OUT_L, &buff[0], 2); + *val = (int16_t)buff[1]; + *val = (*val * 256) + (int16_t)buff[0]; + + return ret; +} + +/** + * @brief Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement.[get] + * + * @param ctx read / write interface definitions + * @param val Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val) +{ + st1vafe6ax_internal_freq_t internal_freq; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INTERNAL_FREQ, (uint8_t *)&internal_freq, 1); + *val = (int8_t)internal_freq.freq_fine; + + return ret; +} + +/** + * @brief Write buffer in a page.[set] + * + * @param ctx read / write interface definitions + * @param val Write buffer in a page. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len) +{ + st1vafe6ax_page_address_t page_address; + st1vafe6ax_page_sel_t page_sel; + st1vafe6ax_page_rw_t page_rw; + uint8_t msb; + uint8_t lsb; + int32_t ret; + uint8_t i ; + + msb = ((uint8_t)(address >> 8) & 0x0FU); + lsb = (uint8_t)address & 0xFFU; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + + /* set page write */ + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_ENABLE; + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); + + /* select page */ + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_SEL, (uint8_t *)&page_sel, 1); + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + + /* set page addr */ + page_address.page_addr = lsb; + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + + for (i = 0; ((i < len) && (ret == 0)); i++) + { + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_VALUE, &buf[i], 1); + lsb++; + + /* Check if page wrap */ + if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) + { + msb++; + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_SEL, (uint8_t *)&page_sel, 1); + + if (ret == 0) + { + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + } + } + } + + page_sel.page_sel = 0; + page_sel.not_used0 = 1;// Default value + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + + /* unset page write */ + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Read buffer in a page.[set] + * + * @param ctx read / write interface definitions + * @param val Write buffer in a page. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len) +{ + st1vafe6ax_page_address_t page_address; + st1vafe6ax_page_sel_t page_sel; + st1vafe6ax_page_rw_t page_rw; + uint8_t msb; + uint8_t lsb; + int32_t ret; + uint8_t i ; + + msb = ((uint8_t)(address >> 8) & 0x0FU); + lsb = (uint8_t)address & 0xFFU; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + + /* set page write */ + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_ENABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); + + /* select page */ + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_SEL, (uint8_t *)&page_sel, 1); + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + + /* set page addr */ + page_address.page_addr = lsb; + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_ADDRESS, + (uint8_t *)&page_address, 1); + + for (i = 0; ((i < len) && (ret == 0)); i++) + { + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_VALUE, &buf[i], 1); + lsb++; + + /* Check if page wrap */ + if (((lsb & 0xFFU) == 0x00U) && (ret == 0)) + { + msb++; + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_SEL, (uint8_t *)&page_sel, 1); + + if (ret == 0) + { + page_sel.page_sel = msb; + page_sel.not_used0 = 1; // Default value + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + } + } + } + + page_sel.page_sel = 0; + page_sel.not_used0 = 1;// Default value + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_SEL, (uint8_t *)&page_sel, + 1); + + /* unset page write */ + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); + page_rw.page_read = PROPERTY_DISABLE; + page_rw.page_write = PROPERTY_DISABLE; + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Timestamp + * @brief This section groups all the functions that manage the + * timestamp generation. + * @{ + * + */ + +/** + * @brief Enables timestamp counter.[set] + * + * @param ctx read / write interface definitions + * @param val Enables timestamp counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + st1vafe6ax_functions_enable_t functions_enable; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret == 0) + { + functions_enable.timestamp_en = val; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + return ret; +} + +/** + * @brief Enables timestamp counter.[get] + * + * @param ctx read / write interface definitions + * @param val Enables timestamp counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + st1vafe6ax_functions_enable_t functions_enable; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + *val = functions_enable.timestamp_en; + + return ret; +} + +/** + * @brief Timestamp data output.[get] + * + * @param ctx read / write interface definitions + * @param val Timestamp data output. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val) +{ + uint8_t buff[4]; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TIMESTAMP0, &buff[0], 4); + *val = buff[3]; + *val = (*val * 256U) + buff[2]; + *val = (*val * 256U) + buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Filters + * @brief This section group all the functions concerning the + * filters configuration + * @{ + * + */ + +/** + * @brief Protocol anti-spike filters.[set] + * + * @param ctx read / write interface definitions + * @param val AUTO, ALWAYS_ACTIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_filt_anti_spike_set(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_anti_spike_t val) +{ + st1vafe6ax_if_cfg_t if_cfg; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_IF_CFG, (uint8_t *)&if_cfg, 1); + + if (ret == 0) + { + if_cfg.asf_ctrl = (uint8_t)val & 0x01U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Protocol anti-spike filters.[get] + * + * @param ctx read / write interface definitions + * @param val AUTO, ALWAYS_ACTIVE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_filt_anti_spike_get(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_anti_spike_t *val) +{ + st1vafe6ax_if_cfg_t if_cfg; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_IF_CFG, (uint8_t *)&if_cfg, 1); + switch (if_cfg.asf_ctrl) + { + case ST1VAFE6AX_AUTO: + *val = ST1VAFE6AX_AUTO; + break; + + case ST1VAFE6AX_ALWAYS_ACTIVE: + *val = ST1VAFE6AX_ALWAYS_ACTIVE; + break; + + default: + *val = ST1VAFE6AX_AUTO; + break; + } + return ret; +} + +/** + * @brief It masks DRDY and Interrupts RQ until filter settling ends.[set] + * + * @param ctx read / write interface definitions + * @param val It masks DRDY and Interrupts RQ until filter settling ends. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_filt_settling_mask_set(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_settling_mask_t val) +{ + st1vafe6ax_emb_func_cfg_t emb_func_cfg; + st1vafe6ax_ctrl4_t ctrl4; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL4, (uint8_t *)&ctrl4, 1); + + if (ret == 0) + { + ctrl4.drdy_mask = val.drdy; + + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL4, (uint8_t *)&ctrl4, 1); + } + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + } + + if (ret == 0) + { + emb_func_cfg.emb_func_irq_mask_xl_settl = val.irq_xl; + emb_func_cfg.emb_func_irq_mask_g_settl = val.irq_g; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + } + + return ret; +} + +/** + * @brief It masks DRDY and Interrupts RQ until filter settling ends.[get] + * + * @param ctx read / write interface definitions + * @param val It masks DRDY and Interrupts RQ until filter settling ends. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_filt_settling_mask_get(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_settling_mask_t *val) +{ + st1vafe6ax_emb_func_cfg_t emb_func_cfg; + st1vafe6ax_ctrl4_t ctrl4; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL4, (uint8_t *)&ctrl4, 1); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1); + } + + val->drdy = ctrl4.drdy_mask; + val->irq_xl = emb_func_cfg.emb_func_irq_mask_xl_settl; + val->irq_g = emb_func_cfg.emb_func_irq_mask_g_settl; + + return ret; +} + +/** + * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[set] + * + * @param ctx read / write interface definitions + * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_gy_lp1_bandwidth_t val) +{ + st1vafe6ax_ctrl6_t ctrl6; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL6, (uint8_t *)&ctrl6, 1); + if (ret == 0) + { + ctrl6.lpf1_g_bw = (uint8_t)val & 0x7U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL6, (uint8_t *)&ctrl6, 1); + } + + return ret; +} + +/** + * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[get] + * + * @param ctx read / write interface definitions + * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_gy_lp1_bandwidth_t *val) +{ + st1vafe6ax_ctrl6_t ctrl6; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL6, (uint8_t *)&ctrl6, 1); + + switch (ctrl6.lpf1_g_bw) + { + case ST1VAFE6AX_GY_ULTRA_LIGHT: + *val = ST1VAFE6AX_GY_ULTRA_LIGHT; + break; + + case ST1VAFE6AX_GY_VERY_LIGHT: + *val = ST1VAFE6AX_GY_VERY_LIGHT; + break; + + case ST1VAFE6AX_GY_LIGHT: + *val = ST1VAFE6AX_GY_LIGHT; + break; + + case ST1VAFE6AX_GY_MEDIUM: + *val = ST1VAFE6AX_GY_MEDIUM; + break; + + case ST1VAFE6AX_GY_STRONG: + *val = ST1VAFE6AX_GY_STRONG; + break; + + case ST1VAFE6AX_GY_VERY_STRONG: + *val = ST1VAFE6AX_GY_VERY_STRONG; + break; + + case ST1VAFE6AX_GY_AGGRESSIVE: + *val = ST1VAFE6AX_GY_AGGRESSIVE; + break; + + case ST1VAFE6AX_GY_XTREME: + *val = ST1VAFE6AX_GY_XTREME; + break; + + default: + *val = ST1VAFE6AX_GY_ULTRA_LIGHT; + break; + } + return ret; +} + +/** + * @brief It enables gyroscope digital LPF1 filter.[set] + * + * @param ctx read / write interface definitions + * @param val It enables gyroscope digital LPF1 filter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_filt_gy_lp1_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + st1vafe6ax_ctrl7_t ctrl7; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL7, (uint8_t *)&ctrl7, 1); + + if (ret == 0) + { + ctrl7.lpf1_g_en = val; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL7, (uint8_t *)&ctrl7, 1); + } + + return ret; +} + +/** + * @brief It enables gyroscope digital LPF1 filter.[get] + * + * @param ctx read / write interface definitions + * @param val It enables gyroscope digital LPF1 filter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + st1vafe6ax_ctrl7_t ctrl7; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL7, (uint8_t *)&ctrl7, 1); + *val = ctrl7.lpf1_g_en; + + return ret; +} + +/** + * @brief Bio filter configuration.[set] + * + * @param ctx read / write interface definitions + * @param val Bio filter configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_filt_ah_bio_conf_set(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_ah_bio_conf_t val) +{ + st1vafe6ax_ctrl9_t ctrl9; + st1vafe6ax_ctrl8_t ctrl8; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + } + + ctrl8.ah_bio_hpf = val.hpf; + ctrl9.ah_bio_lpf = val.lpf; + + if (ret == 0) + { + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL8, (uint8_t *)&ctrl8, 1); + } + if (ret == 0) + { + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Bio filter configuration.[get] + * + * @param ctx read / write interface definitions + * @param val Bio filter configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_filt_ah_bio_conf_get(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_ah_bio_conf_t *val) +{ + st1vafe6ax_ctrl8_t ctrl8; + st1vafe6ax_ctrl9_t ctrl9; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + } + + val->lpf = ctrl9.ah_bio_lpf; + val->hpf = ctrl8.ah_bio_hpf; + + return ret; +} + +/** + * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[set] + * + * @param ctx read / write interface definitions + * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_xl_lp2_bandwidth_t val) +{ + st1vafe6ax_ctrl8_t ctrl8; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL8, (uint8_t *)&ctrl8, 1); + if (ret == 0) + { + ctrl8.hp_lpf2_xl_bw = (uint8_t)val & 0x7U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL8, (uint8_t *)&ctrl8, 1); + } + + return ret; +} + +/** + * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[get] + * + * @param ctx read / write interface definitions + * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_xl_lp2_bandwidth_t *val) +{ + st1vafe6ax_ctrl8_t ctrl8; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL8, (uint8_t *)&ctrl8, 1); + switch (ctrl8.hp_lpf2_xl_bw) + { + case ST1VAFE6AX_XL_ULTRA_LIGHT: + *val = ST1VAFE6AX_XL_ULTRA_LIGHT; + break; + + case ST1VAFE6AX_XL_VERY_LIGHT: + *val = ST1VAFE6AX_XL_VERY_LIGHT; + break; + + case ST1VAFE6AX_XL_LIGHT: + *val = ST1VAFE6AX_XL_LIGHT; + break; + + case ST1VAFE6AX_XL_MEDIUM: + *val = ST1VAFE6AX_XL_MEDIUM; + break; + + case ST1VAFE6AX_XL_STRONG: + *val = ST1VAFE6AX_XL_STRONG; + break; + + case ST1VAFE6AX_XL_VERY_STRONG: + *val = ST1VAFE6AX_XL_VERY_STRONG; + break; + + case ST1VAFE6AX_XL_AGGRESSIVE: + *val = ST1VAFE6AX_XL_AGGRESSIVE; + break; + + case ST1VAFE6AX_XL_XTREME: + *val = ST1VAFE6AX_XL_XTREME; + break; + + default: + *val = ST1VAFE6AX_XL_ULTRA_LIGHT; + break; + } + return ret; +} + +/** + * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[set] + * + * @param ctx read / write interface definitions + * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_filt_xl_lp2_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + st1vafe6ax_ctrl9_t ctrl9; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.lpf2_xl_en = val; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[get] + * + * @param ctx read / write interface definitions + * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + st1vafe6ax_ctrl9_t ctrl9; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.lpf2_xl_en; + + return ret; +} + +/** + * @brief Accelerometer slope filter / high-pass filter selection.[set] + * + * @param ctx read / write interface definitions + * @param val Accelerometer slope filter / high-pass filter selection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_filt_xl_hp_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + st1vafe6ax_ctrl9_t ctrl9; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.hp_slope_xl_en = val; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Accelerometer slope filter / high-pass filter selection.[get] + * + * @param ctx read / write interface definitions + * @param val Accelerometer slope filter / high-pass filter selection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + st1vafe6ax_ctrl9_t ctrl9; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.hp_slope_xl_en; + + return ret; +} + +/** + * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[set] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_filt_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + st1vafe6ax_ctrl9_t ctrl9; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.xl_fastsettl_mode = val; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[get] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + st1vafe6ax_ctrl9_t ctrl9; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.xl_fastsettl_mode; + + return ret; +} + +/** + * @brief Accelerometer high-pass filter mode.[set] + * + * @param ctx read / write interface definitions + * @param val HP_MD_NORMAL, HP_MD_REFERENCE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_filt_xl_hp_mode_set(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_xl_hp_mode_t val) +{ + st1vafe6ax_ctrl9_t ctrl9; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.hp_ref_mode_xl = (uint8_t)val & 0x01U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Accelerometer high-pass filter mode.[get] + * + * @param ctx read / write interface definitions + * @param val HP_MD_NORMAL, HP_MD_REFERENCE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_xl_hp_mode_t *val) +{ + st1vafe6ax_ctrl9_t ctrl9; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + switch (ctrl9.hp_ref_mode_xl) + { + case ST1VAFE6AX_HP_MD_NORMAL: + *val = ST1VAFE6AX_HP_MD_NORMAL; + break; + + case ST1VAFE6AX_HP_MD_REFERENCE: + *val = ST1VAFE6AX_HP_MD_REFERENCE; + break; + + default: + *val = ST1VAFE6AX_HP_MD_NORMAL; + break; + } + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[set] + * + * @param ctx read / write interface definitions + * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_wkup_act_feed_t val) +{ + st1vafe6ax_wake_up_ths_t wake_up_ths; + st1vafe6ax_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + tap_cfg0.slope_fds = (uint8_t)val & 0x01U; + wake_up_ths.usr_off_on_wu = ((uint8_t)val & 0x02U) >> 1; + + if (ret == 0) + { + + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + if (ret == 0) + { + + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[get] + * + * @param ctx read / write interface definitions + * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_wkup_act_feed_t *val) +{ + st1vafe6ax_wake_up_ths_t wake_up_ths; + st1vafe6ax_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + switch ((wake_up_ths.usr_off_on_wu << 1) + tap_cfg0.slope_fds) + { + case ST1VAFE6AX_WK_FEED_SLOPE: + *val = ST1VAFE6AX_WK_FEED_SLOPE; + break; + + case ST1VAFE6AX_WK_FEED_HIGH_PASS: + *val = ST1VAFE6AX_WK_FEED_HIGH_PASS; + break; + + case ST1VAFE6AX_WK_FEED_LP_WITH_OFFSET: + *val = ST1VAFE6AX_WK_FEED_LP_WITH_OFFSET; + break; + + default: + *val = ST1VAFE6AX_WK_FEED_SLOPE; + break; + } + return ret; +} + +/** + * @brief Mask hw function triggers when xl is settling.[set] + * + * @param ctx read / write interface definitions + * @param val 0 or 1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_mask_trigger_xl_settl_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + st1vafe6ax_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + + if (ret == 0) + { + tap_cfg0.hw_func_mask_xl_settl = val & 0x01U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + return ret; +} + +/** + * @brief Mask hw function triggers when xl is settling.[get] + * + * @param ctx read / write interface definitions + * @param val 0 or 1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + st1vafe6ax_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + *val = tap_cfg0.hw_func_mask_xl_settl; + + return ret; +} + + +/** + * @brief LPF2 filter on 6D (sixd) function selection.[set] + * + * @param ctx read / write interface definitions + * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_filt_sixd_feed_set(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_sixd_feed_t val) +{ + st1vafe6ax_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret == 0) + { + tap_cfg0.low_pass_on_6d = (uint8_t)val & 0x01U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + return ret; +} + +/** + * @brief LPF2 filter on 6D (sixd) function selection.[get] + * + * @param ctx read / write interface definitions + * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_filt_sixd_feed_get(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_sixd_feed_t *val) +{ + st1vafe6ax_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + switch (tap_cfg0.low_pass_on_6d) + { + case ST1VAFE6AX_SIXD_FEED_ODR_DIV_2: + *val = ST1VAFE6AX_SIXD_FEED_ODR_DIV_2; + break; + + case ST1VAFE6AX_SIXD_FEED_LOW_PASS: + *val = ST1VAFE6AX_SIXD_FEED_LOW_PASS; + break; + + default: + *val = ST1VAFE6AX_SIXD_FEED_ODR_DIV_2; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Serial interfaces + * @brief This section groups all the functions concerning + * serial interfaces management (not auxiliary) + * @{ + * + */ + +/** + * @brief Enables pull-up on SDO pin of UI (User Interface).[set] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDO pin of UI (User Interface). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + st1vafe6ax_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret == 0) + { + pin_ctrl.sdo_pu_en = val; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Enables pull-up on SDO pin of UI (User Interface).[get] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDO pin of UI (User Interface). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + st1vafe6ax_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + *val = pin_ctrl.sdo_pu_en; + + return ret; +} + +/** + * @brief Disables I2C and I3C on UI (User Interface).[set] + * + * @param ctx read / write interface definitions + * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_ui_i2c_i3c_mode_set(const stmdev_ctx_t *ctx, + st1vafe6ax_ui_i2c_i3c_mode_t val) +{ + st1vafe6ax_if_cfg_t if_cfg; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.i2c_i3c_disable = (uint8_t)val & 0x01U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Disables I2C and I3C on UI (User Interface).[get] + * + * @param ctx read / write interface definitions + * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx, + st1vafe6ax_ui_i2c_i3c_mode_t *val) +{ + st1vafe6ax_if_cfg_t if_cfg; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_IF_CFG, (uint8_t *)&if_cfg, 1); + switch (if_cfg.i2c_i3c_disable) + { + case ST1VAFE6AX_I2C_I3C_ENABLE: + *val = ST1VAFE6AX_I2C_I3C_ENABLE; + break; + + case ST1VAFE6AX_I2C_I3C_DISABLE: + *val = ST1VAFE6AX_I2C_I3C_DISABLE; + break; + + default: + *val = ST1VAFE6AX_I2C_I3C_ENABLE; + break; + } + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val SPI_4_WIRE, SPI_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_spi_mode_set(const stmdev_ctx_t *ctx, st1vafe6ax_spi_mode_t val) +{ + st1vafe6ax_if_cfg_t if_cfg; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.sim = (uint8_t)val & 0x01U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val SPI_4_WIRE, SPI_3_WIRE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_spi_mode_get(const stmdev_ctx_t *ctx, st1vafe6ax_spi_mode_t *val) +{ + st1vafe6ax_if_cfg_t if_cfg; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_IF_CFG, (uint8_t *)&if_cfg, 1); + switch (if_cfg.sim) + { + case ST1VAFE6AX_SPI_4_WIRE: + *val = ST1VAFE6AX_SPI_4_WIRE; + break; + + case ST1VAFE6AX_SPI_3_WIRE: + *val = ST1VAFE6AX_SPI_3_WIRE; + break; + + default: + *val = ST1VAFE6AX_SPI_4_WIRE; + break; + } + return ret; +} + +/** + * @brief Enables pull-up on SDA pin.[set] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDA pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_ui_sda_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + st1vafe6ax_if_cfg_t if_cfg; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.sda_pu_en = (uint8_t)val & 0x01U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Enables pull-up on SDA pin.[get] + * + * @param ctx read / write interface definitions + * @param val Enables pull-up on SDA pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + st1vafe6ax_if_cfg_t if_cfg; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_IF_CFG, (uint8_t *)&if_cfg, 1); + *val = if_cfg.sda_pu_en; + + return ret; +} + +/** + * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[set] + * + * @param ctx read / write interface definitions + * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_i3c_ibi_time_set(const stmdev_ctx_t *ctx, + st1vafe6ax_i3c_ibi_time_t val) +{ + st1vafe6ax_ctrl5_t ctrl5; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret == 0) + { + ctrl5.bus_act_sel = (uint8_t)val & 0x03U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL5, (uint8_t *)&ctrl5, 1); + } + + return ret; +} + +/** + * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[get] + * + * @param ctx read / write interface definitions + * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_i3c_ibi_time_get(const stmdev_ctx_t *ctx, + st1vafe6ax_i3c_ibi_time_t *val) +{ + st1vafe6ax_ctrl5_t ctrl5; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL5, (uint8_t *)&ctrl5, 1); + switch (ctrl5.bus_act_sel) + { + case ST1VAFE6AX_IBI_2us: + *val = ST1VAFE6AX_IBI_2us; + break; + + case ST1VAFE6AX_IBI_50us: + *val = ST1VAFE6AX_IBI_50us; + break; + + case ST1VAFE6AX_IBI_1ms: + *val = ST1VAFE6AX_IBI_1ms; + break; + + case ST1VAFE6AX_IBI_25ms: + *val = ST1VAFE6AX_IBI_25ms; + break; + + default: + *val = ST1VAFE6AX_IBI_2us; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Interrupt pins + * @brief This section groups all the functions that manage interrupt pins + * @{ + * + */ + +/** + * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[set] + * + * @param ctx read / write interface definitions + * @param val PUSH_PULL, OPEN_DRAIN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_int_pin_mode_set(const stmdev_ctx_t *ctx, + st1vafe6ax_int_pin_mode_t val) +{ + st1vafe6ax_if_cfg_t if_cfg; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.pp_od = (uint8_t)val & 0x01U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[get] + * + * @param ctx read / write interface definitions + * @param val PUSH_PULL, OPEN_DRAIN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_int_pin_mode_get(const stmdev_ctx_t *ctx, + st1vafe6ax_int_pin_mode_t *val) +{ + st1vafe6ax_if_cfg_t if_cfg; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_IF_CFG, (uint8_t *)&if_cfg, 1); + switch (if_cfg.pp_od) + { + case ST1VAFE6AX_PUSH_PULL: + *val = ST1VAFE6AX_PUSH_PULL; + break; + + case ST1VAFE6AX_OPEN_DRAIN: + *val = ST1VAFE6AX_OPEN_DRAIN; + break; + + default: + *val = ST1VAFE6AX_PUSH_PULL; + break; + } + return ret; +} + +/** + * @brief Interrupt activation level.[set] + * + * @param ctx read / write interface definitions + * @param val ACTIVE_HIGH, ACTIVE_LOW, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_pin_polarity_set(const stmdev_ctx_t *ctx, + st1vafe6ax_pin_polarity_t val) +{ + st1vafe6ax_if_cfg_t if_cfg; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_IF_CFG, (uint8_t *)&if_cfg, 1); + if (ret == 0) + { + if_cfg.h_lactive = (uint8_t)val & 0x01U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_IF_CFG, (uint8_t *)&if_cfg, 1); + } + + return ret; +} + +/** + * @brief Interrupt activation level.[get] + * + * @param ctx read / write interface definitions + * @param val ACTIVE_HIGH, ACTIVE_LOW, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_pin_polarity_get(const stmdev_ctx_t *ctx, + st1vafe6ax_pin_polarity_t *val) +{ + st1vafe6ax_if_cfg_t if_cfg; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_IF_CFG, (uint8_t *)&if_cfg, 1); + switch (if_cfg.h_lactive) + { + case ST1VAFE6AX_ACTIVE_HIGH: + *val = ST1VAFE6AX_ACTIVE_HIGH; + break; + + case ST1VAFE6AX_ACTIVE_LOW: + *val = ST1VAFE6AX_ACTIVE_LOW; + break; + + default: + *val = ST1VAFE6AX_ACTIVE_HIGH; + break; + } + return ret; +} + +/** + * @brief It routes interrupt signals on INT 1 pin.[set] + * + * @param ctx read / write interface definitions + * @param val It routes interrupt signals on INT 1 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_pin_int1_route_set(const stmdev_ctx_t *ctx, + st1vafe6ax_pin_int_route_t val) +{ + st1vafe6ax_functions_enable_t functions_enable; + st1vafe6ax_pin_int_route_t pin_int2_route; + st1vafe6ax_inactivity_dur_t inactivity_dur; + st1vafe6ax_emb_func_int1_t emb_func_int1; + st1vafe6ax_pedo_cmd_reg_t pedo_cmd_reg; + st1vafe6ax_int2_ctrl_t int2_ctrl; + st1vafe6ax_int1_ctrl_t int1_ctrl; + st1vafe6ax_fsm_int1_t fsm_int1; + st1vafe6ax_mlc_int1_t mlc_int1; + st1vafe6ax_md1_cfg_t md1_cfg; + st1vafe6ax_md2_cfg_t md2_cfg; + st1vafe6ax_ctrl4_t ctrl4; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FSM_INT1, (uint8_t *)&fsm_int1, 1); + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MLC_INT1, (uint8_t *)&mlc_int1, 1); + } + + if (ret == 0) + { + emb_func_int1.int1_step_detector = val.step_detector; + emb_func_int1.int1_tilt = val.tilt; + emb_func_int1.int1_sig_mot = val.sig_mot; + emb_func_int1.int1_fsm_lc = val.fsm_lc; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + } + if (ret == 0) + { + fsm_int1.int1_fsm1 = val.fsm1; + fsm_int1.int1_fsm2 = val.fsm2; + fsm_int1.int1_fsm3 = val.fsm3; + fsm_int1.int1_fsm4 = val.fsm4; + fsm_int1.int1_fsm5 = val.fsm5; + fsm_int1.int1_fsm6 = val.fsm6; + fsm_int1.int1_fsm7 = val.fsm7; + fsm_int1.int1_fsm8 = val.fsm8; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FSM_INT1, (uint8_t *)&fsm_int1, 1); + } + if (ret == 0) + { + mlc_int1.int1_mlc1 = val.mlc1; + mlc_int1.int1_mlc2 = val.mlc2; + mlc_int1.int1_mlc3 = val.mlc3; + mlc_int1.int1_mlc4 = val.mlc4; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_MLC_INT1, (uint8_t *)&mlc_int1, 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL4, (uint8_t *)&ctrl4, 1); + } + if (ret == 0) + { + if ((val.emb_func_stand_by | val.timestamp) != PROPERTY_DISABLE) + { + ctrl4.int2_on_int1 = PROPERTY_ENABLE; + } + else + { + ctrl4.int2_on_int1 = PROPERTY_DISABLE; + } + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL4, (uint8_t *)&ctrl4, 1); + } + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + } + + if (ret == 0) + { + int2_ctrl.int2_emb_func_endop = val.emb_func_stand_by; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + } + + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + if (ret == 0) + { + md2_cfg.int2_timestamp = val.timestamp; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + if (ret == 0) + { + inactivity_dur.sleep_status_on_int = val.sleep_status; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + } + + if (ret == 0) + { + int1_ctrl.int1_drdy_xl = val.drdy_xl; + int1_ctrl.int1_drdy_g = val.drdy_gy; + int1_ctrl.int1_fifo_th = val.fifo_th; + int1_ctrl.int1_fifo_ovr = val.fifo_ovr; + int1_ctrl.int1_fifo_full = val.fifo_full; + int1_ctrl.int1_cnt_bdr = val.fifo_bdr; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + } + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MD1_CFG, (uint8_t *)&md1_cfg, 1); + } + + if (ret == 0) + { + if ((emb_func_int1.int1_fsm_lc + | emb_func_int1.int1_sig_mot + | emb_func_int1.int1_step_detector + | emb_func_int1.int1_tilt + | fsm_int1.int1_fsm1 + | fsm_int1.int1_fsm2 + | fsm_int1.int1_fsm3 + | fsm_int1.int1_fsm4 + | fsm_int1.int1_fsm5 + | fsm_int1.int1_fsm6 + | fsm_int1.int1_fsm7 + | fsm_int1.int1_fsm8 + | mlc_int1.int1_mlc1 + | mlc_int1.int1_mlc2 + | mlc_int1.int1_mlc3 + | mlc_int1.int1_mlc4) != PROPERTY_DISABLE) + { + md1_cfg.int1_emb_func = PROPERTY_ENABLE; + } + else + { + md1_cfg.int1_emb_func = PROPERTY_DISABLE; + } + md1_cfg.int1_6d = val.six_d; + md1_cfg.int1_double_tap = val.double_tap; + md1_cfg.int1_ff = val.free_fall; + md1_cfg.int1_wu = val.wake_up; + md1_cfg.int1_single_tap = val.single_tap; + if ((val.sleep_status | val.sleep_change) != PROPERTY_DISABLE) + { + md1_cfg.int1_sleep_change = PROPERTY_ENABLE; + } + else + { + md1_cfg.int1_sleep_change = PROPERTY_DISABLE; + } + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_MD1_CFG, (uint8_t *)&md1_cfg, 1); + } + + if (ret == 0) + { + ret = st1vafe6ax_ln_pg_read(ctx, ST1VAFE6AX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + if (ret == 0) + { + pedo_cmd_reg.carry_count_en = val.step_count_overflow; + ret = st1vafe6ax_ln_pg_write(ctx, ST1VAFE6AX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + + if (ret == 0) + { + ret = st1vafe6ax_pin_int2_route_get(ctx, &pin_int2_route); + } + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + if (ret == 0) + { + if ((pin_int2_route.six_d + | pin_int2_route.double_tap + | pin_int2_route.free_fall + | pin_int2_route.wake_up + | pin_int2_route.single_tap + | pin_int2_route.sleep_status + | pin_int2_route.sleep_change + | val.six_d + | val.double_tap + | val.free_fall + | val.wake_up + | val.single_tap + | val.sleep_status + | val.sleep_change) != PROPERTY_DISABLE) + { + functions_enable.interrupts_enable = PROPERTY_ENABLE; + } + + else + { + functions_enable.interrupts_enable = PROPERTY_DISABLE; + } + + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + return ret; +} + +/** + * @brief It routes interrupt signals on INT 1 pin.[get] + * + * @param ctx read / write interface definitions + * @param val It routes interrupt signals on INT 1 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_pin_int1_route_get(const stmdev_ctx_t *ctx, + st1vafe6ax_pin_int_route_t *val) +{ + st1vafe6ax_inactivity_dur_t inactivity_dur; + st1vafe6ax_emb_func_int1_t emb_func_int1; + st1vafe6ax_pedo_cmd_reg_t pedo_cmd_reg; + st1vafe6ax_int1_ctrl_t int1_ctrl; + st1vafe6ax_int2_ctrl_t int2_ctrl; + st1vafe6ax_fsm_int1_t fsm_int1; + st1vafe6ax_mlc_int1_t mlc_int1; + st1vafe6ax_md1_cfg_t md1_cfg; + st1vafe6ax_md2_cfg_t md2_cfg; + st1vafe6ax_ctrl4_t ctrl4; + int32_t ret; + + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL4, (uint8_t *)&ctrl4, 1); + if (ctrl4.int2_on_int1 == PROPERTY_ENABLE) + { + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop; + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + val->timestamp = md2_cfg.int2_timestamp; + } + } + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + val->sleep_status = inactivity_dur.sleep_status_on_int; + } + + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INT1_CTRL, (uint8_t *)&int1_ctrl, 1); + val->drdy_xl = int1_ctrl.int1_drdy_xl; + val->drdy_gy = int1_ctrl.int1_drdy_g; + val->fifo_th = int1_ctrl.int1_fifo_th; + val->fifo_ovr = int1_ctrl.int1_fifo_ovr; + val->fifo_full = int1_ctrl.int1_fifo_full; + val->fifo_bdr = int1_ctrl.int1_cnt_bdr; + } + + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MD1_CFG, (uint8_t *)&md1_cfg, 1); + val->six_d = md1_cfg.int1_6d; + val->double_tap = md1_cfg.int1_double_tap; + val->free_fall = md1_cfg.int1_ff; + val->wake_up = md1_cfg.int1_wu; + val->single_tap = md1_cfg.int1_single_tap; + val->sleep_change = md1_cfg.int1_sleep_change; + } + + if (ret == 0) + { + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1); + val->step_detector = emb_func_int1.int1_step_detector; + val->tilt = emb_func_int1.int1_tilt; + val->sig_mot = emb_func_int1.int1_sig_mot; + val->fsm_lc = emb_func_int1.int1_fsm_lc; + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FSM_INT1, (uint8_t *)&fsm_int1, 1); + val->fsm1 = fsm_int1.int1_fsm1; + val->fsm2 = fsm_int1.int1_fsm2; + val->fsm3 = fsm_int1.int1_fsm3; + val->fsm4 = fsm_int1.int1_fsm4; + val->fsm5 = fsm_int1.int1_fsm5; + val->fsm6 = fsm_int1.int1_fsm6; + val->fsm7 = fsm_int1.int1_fsm7; + val->fsm8 = fsm_int1.int1_fsm8; + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MLC_INT1, (uint8_t *)&mlc_int1, 1); + val->mlc1 = mlc_int1.int1_mlc1; + val->mlc2 = mlc_int1.int1_mlc2; + val->mlc3 = mlc_int1.int1_mlc3; + val->mlc4 = mlc_int1.int1_mlc4; + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = st1vafe6ax_ln_pg_read(ctx, ST1VAFE6AX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + val->step_count_overflow = pedo_cmd_reg.carry_count_en; + } + + return ret; +} + + +/** + * @brief It routes interrupt signals on INT 2 pin.[set] + * + * @param ctx read / write interface definitions + * @param val It routes interrupt signals on INT 2 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_pin_int2_route_set(const stmdev_ctx_t *ctx, + st1vafe6ax_pin_int_route_t val) +{ + st1vafe6ax_functions_enable_t functions_enable; + st1vafe6ax_pin_int_route_t pin_int1_route; + st1vafe6ax_inactivity_dur_t inactivity_dur; + st1vafe6ax_emb_func_int2_t emb_func_int2; + st1vafe6ax_pedo_cmd_reg_t pedo_cmd_reg; + st1vafe6ax_int2_ctrl_t int2_ctrl; + st1vafe6ax_fsm_int2_t fsm_int2; + st1vafe6ax_mlc_int2_t mlc_int2; + st1vafe6ax_ctrl7_t ctrl7; + st1vafe6ax_md2_cfg_t md2_cfg; + st1vafe6ax_ctrl4_t ctrl4; + int32_t ret; + + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FSM_INT2, (uint8_t *)&fsm_int2, 1); + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MLC_INT2, (uint8_t *)&mlc_int2, 1); + } + + if (ret == 0) + { + emb_func_int2.int2_step_detector = val.step_detector; + emb_func_int2.int2_tilt = val.tilt; + emb_func_int2.int2_sig_mot = val.sig_mot; + emb_func_int2.int2_fsm_lc = val.fsm_lc; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + } + if (ret == 0) + { + fsm_int2.int2_fsm1 = val.fsm1; + fsm_int2.int2_fsm2 = val.fsm2; + fsm_int2.int2_fsm3 = val.fsm3; + fsm_int2.int2_fsm4 = val.fsm4; + fsm_int2.int2_fsm5 = val.fsm5; + fsm_int2.int2_fsm6 = val.fsm6; + fsm_int2.int2_fsm7 = val.fsm7; + fsm_int2.int2_fsm8 = val.fsm8; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FSM_INT2, (uint8_t *)&fsm_int2, 1); + } + if (ret == 0) + { + mlc_int2.int2_mlc1 = val.mlc1; + mlc_int2.int2_mlc2 = val.mlc2; + mlc_int2.int2_mlc3 = val.mlc3; + mlc_int2.int2_mlc4 = val.mlc4; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_MLC_INT2, (uint8_t *)&mlc_int2, 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL4, (uint8_t *)&ctrl4, 1); + } + if (ret == 0) + { + if ((val.emb_func_stand_by | val.timestamp) != PROPERTY_DISABLE) + { + ctrl4.int2_on_int1 = PROPERTY_DISABLE; + } + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL4, (uint8_t *)&ctrl4, 1); + } + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + if (ret == 0) + { + inactivity_dur.sleep_status_on_int = val.sleep_status; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + } + + if (ret == 0) + { + int2_ctrl.int2_drdy_xl = val.drdy_xl; + int2_ctrl.int2_drdy_g = val.drdy_gy; + int2_ctrl.int2_fifo_th = val.fifo_th; + int2_ctrl.int2_fifo_ovr = val.fifo_ovr; + int2_ctrl.int2_fifo_full = val.fifo_full; + int2_ctrl.int2_cnt_bdr = val.fifo_bdr; + int2_ctrl.int2_emb_func_endop = val.emb_func_stand_by; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + } + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL7, (uint8_t *)&ctrl7, 1); + ctrl7.int2_drdy_ah_bio = val.drdy_ah_bio; + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL7, (uint8_t *)&ctrl7, 1); + } + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + if (ret == 0) + { + if ((emb_func_int2.int2_fsm_lc + | emb_func_int2.int2_sig_mot + | emb_func_int2.int2_step_detector + | emb_func_int2.int2_tilt + | fsm_int2.int2_fsm1 + | fsm_int2.int2_fsm2 + | fsm_int2.int2_fsm3 + | fsm_int2.int2_fsm4 + | fsm_int2.int2_fsm5 + | fsm_int2.int2_fsm6 + | fsm_int2.int2_fsm7 + | fsm_int2.int2_fsm8 + | mlc_int2.int2_mlc1 + | mlc_int2.int2_mlc2 + | mlc_int2.int2_mlc3 + | mlc_int2.int2_mlc4) != PROPERTY_DISABLE) + { + md2_cfg.int2_emb_func = PROPERTY_ENABLE; + } + else + { + md2_cfg.int2_emb_func = PROPERTY_DISABLE; + } + md2_cfg.int2_6d = val.six_d; + md2_cfg.int2_double_tap = val.double_tap; + md2_cfg.int2_ff = val.free_fall; + md2_cfg.int2_wu = val.wake_up; + md2_cfg.int2_single_tap = val.single_tap; + md2_cfg.int2_timestamp = val.timestamp; + if ((val.sleep_status | val.sleep_change) != PROPERTY_DISABLE) + { + md2_cfg.int2_sleep_change = PROPERTY_ENABLE; + } + else + { + md2_cfg.int2_sleep_change = PROPERTY_DISABLE; + } + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + } + + if (ret == 0) + { + ret = st1vafe6ax_ln_pg_read(ctx, ST1VAFE6AX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + if (ret == 0) + { + pedo_cmd_reg.carry_count_en = val.step_count_overflow; + ret = st1vafe6ax_ln_pg_write(ctx, ST1VAFE6AX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + + if (ret == 0) + { + ret = st1vafe6ax_pin_int1_route_get(ctx, &pin_int1_route); + } + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + if (ret == 0) + { + if ((pin_int1_route.six_d + | pin_int1_route.double_tap + | pin_int1_route.free_fall + | pin_int1_route.wake_up + | pin_int1_route.single_tap + | pin_int1_route.sleep_status + | pin_int1_route.sleep_change + | val.six_d + | val.double_tap + | val.free_fall + | val.wake_up + | val.single_tap + | val.sleep_status + | val.sleep_change) != PROPERTY_DISABLE) + { + functions_enable.interrupts_enable = PROPERTY_ENABLE; + } + + else + { + functions_enable.interrupts_enable = PROPERTY_DISABLE; + } + + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + return ret; +} + +/** + * @brief It routes interrupt signals on INT 2 pin.[get] + * + * @param ctx read / write interface definitions + * @param val It routes interrupt signals on INT 2 pin. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_pin_int2_route_get(const stmdev_ctx_t *ctx, + st1vafe6ax_pin_int_route_t *val) +{ + st1vafe6ax_inactivity_dur_t inactivity_dur; + st1vafe6ax_emb_func_int2_t emb_func_int2; + st1vafe6ax_pedo_cmd_reg_t pedo_cmd_reg; + st1vafe6ax_int2_ctrl_t int2_ctrl; + st1vafe6ax_fsm_int2_t fsm_int2; + st1vafe6ax_mlc_int2_t mlc_int2; + st1vafe6ax_ctrl7_t ctrl7; + st1vafe6ax_md2_cfg_t md2_cfg; + st1vafe6ax_ctrl4_t ctrl4; + int32_t ret; + + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL4, (uint8_t *)&ctrl4, 1); + if (ctrl4.int2_on_int1 == PROPERTY_DISABLE) + { + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop; + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + val->timestamp = md2_cfg.int2_timestamp; + } + } + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + val->sleep_status = inactivity_dur.sleep_status_on_int; + } + + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1); + val->drdy_xl = int2_ctrl.int2_drdy_xl; + val->drdy_gy = int2_ctrl.int2_drdy_g; + val->fifo_th = int2_ctrl.int2_fifo_th; + val->fifo_ovr = int2_ctrl.int2_fifo_ovr; + val->fifo_full = int2_ctrl.int2_fifo_full; + val->fifo_bdr = int2_ctrl.int2_cnt_bdr; + } + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL7, (uint8_t *)&ctrl7, 1); + val->drdy_ah_bio = ctrl7.int2_drdy_ah_bio; + } + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MD2_CFG, (uint8_t *)&md2_cfg, 1); + val->six_d = md2_cfg.int2_6d; + val->double_tap = md2_cfg.int2_double_tap; + val->free_fall = md2_cfg.int2_ff; + val->wake_up = md2_cfg.int2_wu; + val->single_tap = md2_cfg.int2_single_tap; + val->sleep_change = md2_cfg.int2_sleep_change; + } + + if (ret == 0) + { + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1); + val->step_detector = emb_func_int2.int2_step_detector; + val->tilt = emb_func_int2.int2_tilt; + val->sig_mot = emb_func_int2.int2_sig_mot; + val->fsm_lc = emb_func_int2.int2_fsm_lc; + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FSM_INT2, (uint8_t *)&fsm_int2, 1); + val->fsm1 = fsm_int2.int2_fsm1; + val->fsm2 = fsm_int2.int2_fsm2; + val->fsm3 = fsm_int2.int2_fsm3; + val->fsm4 = fsm_int2.int2_fsm4; + val->fsm5 = fsm_int2.int2_fsm5; + val->fsm6 = fsm_int2.int2_fsm6; + val->fsm7 = fsm_int2.int2_fsm7; + val->fsm8 = fsm_int2.int2_fsm8; + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MLC_INT2, (uint8_t *)&mlc_int2, 1); + val->mlc1 = mlc_int2.int2_mlc1; + val->mlc2 = mlc_int2.int2_mlc2; + val->mlc3 = mlc_int2.int2_mlc3; + val->mlc4 = mlc_int2.int2_mlc4; + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = st1vafe6ax_ln_pg_read(ctx, ST1VAFE6AX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + val->step_count_overflow = pedo_cmd_reg.carry_count_en; + } + + return ret; +} + +/** + * @brief Enables INT pin when I3C is enabled.[set] + * + * @param ctx read / write interface definitions + * @param val Enables INT pin when I3C is enabled. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_pin_int_en_when_i2c_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + st1vafe6ax_ctrl5_t ctrl5; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL5, (uint8_t *)&ctrl5, 1); + if (ret == 0) + { + ctrl5.int_en_i3c = val; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL5, (uint8_t *)&ctrl5, 1); + } + + return ret; +} + +/** + * @brief Enables INT pin when I3C is enabled.[get] + * + * @param ctx read / write interface definitions + * @param val Enables INT pin when I3C is enabled. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_pin_int_en_when_i2c_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + st1vafe6ax_ctrl5_t ctrl5; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL5, (uint8_t *)&ctrl5, 1); + *val = ctrl5.int_en_i3c; + + return ret; +} + +/** + * @brief Interrupt notification mode.[set] + * + * @param ctx read / write interface definitions + * @param val ALL_INT_PULSED, BASE_LATCHED_EMB_PULSED, BASE_PULSED_EMB_LATCHED, ALL_INT_LATCHED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_int_notification_set(const stmdev_ctx_t *ctx, + st1vafe6ax_int_notification_t val) +{ + st1vafe6ax_tap_cfg0_t tap_cfg0; + st1vafe6ax_page_rw_t page_rw; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret == 0) + { + tap_cfg0.lir = (uint8_t)val & 0x01U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + if (ret == 0) + { + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + if (ret == 0) + { + page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Interrupt notification mode.[get] + * + * @param ctx read / write interface definitions + * @param val ALL_INT_PULSED, BASE_LATCHED_EMB_PULSED, BASE_PULSED_EMB_LATCHED, ALL_INT_LATCHED, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_int_notification_get(const stmdev_ctx_t *ctx, + st1vafe6ax_int_notification_t *val) +{ + st1vafe6ax_tap_cfg0_t tap_cfg0; + st1vafe6ax_page_rw_t page_rw; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret == 0) + { + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PAGE_RW, (uint8_t *)&page_rw, 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir) + { + case ST1VAFE6AX_ALL_INT_PULSED: + *val = ST1VAFE6AX_ALL_INT_PULSED; + break; + + case ST1VAFE6AX_BASE_LATCHED_EMB_PULSED: + *val = ST1VAFE6AX_BASE_LATCHED_EMB_PULSED; + break; + + case ST1VAFE6AX_BASE_PULSED_EMB_LATCHED: + *val = ST1VAFE6AX_BASE_PULSED_EMB_LATCHED; + break; + + case ST1VAFE6AX_ALL_INT_LATCHED: + *val = ST1VAFE6AX_ALL_INT_LATCHED; + break; + + default: + *val = ST1VAFE6AX_ALL_INT_PULSED; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Wake Up event and Activity / Inactivity detection + * @brief This section groups all the functions that manage the Wake Up + * event generation. + * @{ + * + */ + +/** + * @brief Enable activity/inactivity (sleep) function.[set] + * + * @param ctx read / write interface definitions + * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_act_mode_set(const stmdev_ctx_t *ctx, st1vafe6ax_act_mode_t val) +{ + st1vafe6ax_functions_enable_t functions_enable; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + if (ret == 0) + { + functions_enable.inact_en = (uint8_t)val & 0x03U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + } + + return ret; +} + +/** + * @brief Enable activity/inactivity (sleep) function.[get] + * + * @param ctx read / write interface definitions + * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_act_mode_get(const stmdev_ctx_t *ctx, st1vafe6ax_act_mode_t *val) +{ + st1vafe6ax_functions_enable_t functions_enable; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1); + switch (functions_enable.inact_en) + { + case ST1VAFE6AX_XL_AND_GY_NOT_AFFECTED: + *val = ST1VAFE6AX_XL_AND_GY_NOT_AFFECTED; + break; + + case ST1VAFE6AX_XL_LOW_POWER_GY_NOT_AFFECTED: + *val = ST1VAFE6AX_XL_LOW_POWER_GY_NOT_AFFECTED; + break; + + case ST1VAFE6AX_XL_LOW_POWER_GY_SLEEP: + *val = ST1VAFE6AX_XL_LOW_POWER_GY_SLEEP; + break; + + case ST1VAFE6AX_XL_LOW_POWER_GY_POWER_DOWN: + *val = ST1VAFE6AX_XL_LOW_POWER_GY_POWER_DOWN; + break; + + default: + *val = ST1VAFE6AX_XL_AND_GY_NOT_AFFECTED; + break; + } + return ret; +} + +/** + * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[set] + * + * @param ctx read / write interface definitions + * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_act_from_sleep_to_act_dur_set(const stmdev_ctx_t *ctx, + st1vafe6ax_act_from_sleep_to_act_dur_t val) +{ + st1vafe6ax_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret == 0) + { + inactivity_dur.inact_dur = (uint8_t)val & 0x3U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + return ret; +} + +/** + * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[get] + * + * @param ctx read / write interface definitions + * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx, + st1vafe6ax_act_from_sleep_to_act_dur_t *val) +{ + st1vafe6ax_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + switch (inactivity_dur.inact_dur) + { + case ST1VAFE6AX_SLEEP_TO_ACT_AT_1ST_SAMPLE: + *val = ST1VAFE6AX_SLEEP_TO_ACT_AT_1ST_SAMPLE; + break; + + case ST1VAFE6AX_SLEEP_TO_ACT_AT_2ND_SAMPLE: + *val = ST1VAFE6AX_SLEEP_TO_ACT_AT_2ND_SAMPLE; + break; + + case ST1VAFE6AX_SLEEP_TO_ACT_AT_3RD_SAMPLE: + *val = ST1VAFE6AX_SLEEP_TO_ACT_AT_3RD_SAMPLE; + break; + + case ST1VAFE6AX_SLEEP_TO_ACT_AT_4th_SAMPLE: + *val = ST1VAFE6AX_SLEEP_TO_ACT_AT_4th_SAMPLE; + break; + + default: + *val = ST1VAFE6AX_SLEEP_TO_ACT_AT_1ST_SAMPLE; + break; + } + return ret; +} + +/** + * @brief Selects the accelerometer data rate during Inactivity.[set] + * + * @param ctx read / write interface definitions + * @param val 1Hz875, 15Hz, 30Hz, 60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_act_sleep_xl_odr_set(const stmdev_ctx_t *ctx, + st1vafe6ax_act_sleep_xl_odr_t val) +{ + st1vafe6ax_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret == 0) + { + inactivity_dur.xl_inact_odr = (uint8_t)val & 0x03U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + + return ret; +} + +/** + * @brief Selects the accelerometer data rate during Inactivity.[get] + * + * @param ctx read / write interface definitions + * @param val 1Hz875, 15Hz, 30Hz, 60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx, + st1vafe6ax_act_sleep_xl_odr_t *val) +{ + st1vafe6ax_inactivity_dur_t inactivity_dur; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + switch (inactivity_dur.xl_inact_odr) + { + case ST1VAFE6AX_1Hz875: + *val = ST1VAFE6AX_1Hz875; + break; + + case ST1VAFE6AX_15Hz: + *val = ST1VAFE6AX_15Hz; + break; + + case ST1VAFE6AX_30Hz: + *val = ST1VAFE6AX_30Hz; + break; + + case ST1VAFE6AX_60Hz: + *val = ST1VAFE6AX_60Hz; + break; + + default: + *val = ST1VAFE6AX_1Hz875; + break; + } + return ret; +} + +/** + * @brief Wakeup and activity/inactivity threshold.[set] + * + * @param ctx read / write interface definitions + * @param val Wakeup and activity/inactivity threshold. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_act_thresholds_set(const stmdev_ctx_t *ctx, + st1vafe6ax_act_thresholds_t val) +{ + st1vafe6ax_inactivity_ths_t inactivity_ths; + st1vafe6ax_inactivity_dur_t inactivity_dur; + st1vafe6ax_wake_up_ths_t wake_up_ths; + int32_t ret; + float_t tmp; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + } + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + if ((val.wk_ths_mg < (uint32_t)(7.8125f * 63.0f)) + && (val.inact_ths_mg < (uint32_t)(7.8125f * 63.0f))) + { + inactivity_dur.wu_inact_ths_w = 0; + + tmp = (float_t)val.inact_ths_mg / 7.8125f; + inactivity_ths.inact_ths = (uint8_t)tmp; + + tmp = (float_t)val.wk_ths_mg / 7.8125f; + wake_up_ths.wk_ths = (uint8_t)tmp; + } + else if ((val.wk_ths_mg < (uint32_t)(15.625f * 63.0f)) + && (val.inact_ths_mg < (uint32_t)(15.625f * 63.0f))) + { + inactivity_dur.wu_inact_ths_w = 1; + + tmp = (float_t)val.inact_ths_mg / 15.625f; + inactivity_ths.inact_ths = (uint8_t)tmp; + + tmp = (float_t)val.wk_ths_mg / 15.625f; + wake_up_ths.wk_ths = (uint8_t)tmp; + } + else if ((val.wk_ths_mg < (uint32_t)(31.25f * 63.0f)) + && (val.inact_ths_mg < (uint32_t)(31.25f * 63.0f))) + { + inactivity_dur.wu_inact_ths_w = 2; + + tmp = (float_t)val.inact_ths_mg / 31.25f; + inactivity_ths.inact_ths = (uint8_t)tmp; + + tmp = (float_t)val.wk_ths_mg / 31.25f; + wake_up_ths.wk_ths = (uint8_t)tmp; + } + else if ((val.wk_ths_mg < (uint32_t)(62.5f * 63.0f)) + && (val.inact_ths_mg < (uint32_t)(62.5f * 63.0f))) + { + inactivity_dur.wu_inact_ths_w = 3; + + tmp = (float_t)val.inact_ths_mg / 62.5f; + inactivity_ths.inact_ths = (uint8_t)tmp; + + tmp = (float_t)val.wk_ths_mg / 62.5f; + wake_up_ths.wk_ths = (uint8_t)tmp; + } + else if ((val.wk_ths_mg < (uint32_t)(125.0f * 63.0f)) + && (val.inact_ths_mg < (uint32_t)(125.0f * 63.0f))) + { + inactivity_dur.wu_inact_ths_w = 4; + + tmp = (float_t)val.inact_ths_mg / 125.0f; + inactivity_ths.inact_ths = (uint8_t)tmp; + + tmp = (float_t)val.wk_ths_mg / 125.0f; + wake_up_ths.wk_ths = (uint8_t)tmp; + } + else if ((val.wk_ths_mg < (uint32_t)(250.0f * 63.0f)) + && (val.inact_ths_mg < (uint32_t)(250.0f * 63.0f))) + { + inactivity_dur.wu_inact_ths_w = 5; + + tmp = (float_t)val.inact_ths_mg / 250.0f; + inactivity_ths.inact_ths = (uint8_t)tmp; + + tmp = (float_t)val.wk_ths_mg / 250.0f; + wake_up_ths.wk_ths = (uint8_t)tmp; + } + else // out of limit + { + inactivity_dur.wu_inact_ths_w = 5; + inactivity_ths.inact_ths = 0x3FU; + wake_up_ths.wk_ths = 0x3FU; + } + + if (ret == 0) + { + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + } + if (ret == 0) + { + + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + } + if (ret == 0) + { + + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + return ret; +} + +/** + * @brief Wakeup and activity/inactivity threshold.[get] + * + * @param ctx read / write interface definitions + * @param val Wakeup and activity/inactivity threshold. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_act_thresholds_get(const stmdev_ctx_t *ctx, + st1vafe6ax_act_thresholds_t *val) +{ + st1vafe6ax_inactivity_dur_t inactivity_dur; + st1vafe6ax_inactivity_ths_t inactivity_ths; + st1vafe6ax_wake_up_ths_t wake_up_ths; + int32_t ret; + float_t tmp; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1); + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + switch (inactivity_dur.wu_inact_ths_w) + { + case 0: + tmp = (float_t)wake_up_ths.wk_ths * 7.8125f; + val->wk_ths_mg = (uint32_t)tmp; + + tmp = (float_t)inactivity_ths.inact_ths * 7.8125f; + val->inact_ths_mg = (uint32_t)tmp; + break; + + case 1: + tmp = (float_t)wake_up_ths.wk_ths * 15.625f; + val->wk_ths_mg = (uint32_t)tmp; + + tmp = (float_t)inactivity_ths.inact_ths * 15.625f; + val->inact_ths_mg = (uint32_t)tmp; + break; + + case 2: + tmp = (float_t)wake_up_ths.wk_ths * 31.25f; + val->wk_ths_mg = (uint32_t)tmp; + + tmp = (float_t)inactivity_ths.inact_ths * 31.25f; + val->inact_ths_mg = (uint32_t)tmp; + break; + + case 3: + tmp = (float_t)wake_up_ths.wk_ths * 62.5f; + val->wk_ths_mg = (uint32_t)tmp; + + tmp = (float_t)inactivity_ths.inact_ths * 62.5f; + val->inact_ths_mg = (uint32_t)tmp; + break; + + case 4: + tmp = (float_t)wake_up_ths.wk_ths * 125.0f; + val->wk_ths_mg = (uint32_t)tmp; + + tmp = (float_t)inactivity_ths.inact_ths * 125.0f; + val->inact_ths_mg = (uint32_t)tmp; + break; + + default: + tmp = (float_t)wake_up_ths.wk_ths * 250.0f; + val->wk_ths_mg = (uint32_t)tmp; + + tmp = (float_t)inactivity_ths.inact_ths * 250.0f; + val->inact_ths_mg = (uint32_t)tmp; + break; + } + + return ret; +} + +/** + * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [set] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_act_wkup_time_windows_set(const stmdev_ctx_t *ctx, + st1vafe6ax_act_wkup_time_windows_t val) +{ + st1vafe6ax_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + wake_up_dur.wake_dur = val.shock; + wake_up_dur.sleep_dur = val.quiet; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + } + + return ret; +} + +/** + * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [get] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, + st1vafe6ax_act_wkup_time_windows_t *val) +{ + st1vafe6ax_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + val->shock = wake_up_dur.wake_dur; + val->quiet = wake_up_dur.sleep_dur; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Tap Generator + * @brief This section groups all the functions that manage the + * tap and double tap event generation. + * @{ + * + */ + +/** + * @brief Enable axis for Tap - Double Tap detection.[set] + * + * @param ctx read / write interface definitions + * @param val Enable axis for Tap - Double Tap detection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_tap_detection_set(const stmdev_ctx_t *ctx, + st1vafe6ax_tap_detection_t val) +{ + st1vafe6ax_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + if (ret == 0) + { + tap_cfg0.tap_x_en = val.tap_x_en; + tap_cfg0.tap_y_en = val.tap_y_en; + tap_cfg0.tap_z_en = val.tap_z_en; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + } + + return ret; +} + +/** + * @brief Enable axis for Tap - Double Tap detection.[get] + * + * @param ctx read / write interface definitions + * @param val Enable axis for Tap - Double Tap detection. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_tap_detection_get(const stmdev_ctx_t *ctx, + st1vafe6ax_tap_detection_t *val) +{ + st1vafe6ax_tap_cfg0_t tap_cfg0; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1); + val->tap_x_en = tap_cfg0.tap_x_en; + val->tap_y_en = tap_cfg0.tap_y_en; + val->tap_z_en = tap_cfg0.tap_z_en; + + return ret; +} + +/** + * @brief axis Tap - Double Tap recognition thresholds.[set] + * + * @param ctx read / write interface definitions + * @param val axis Tap - Double Tap recognition thresholds. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_tap_thresholds_set(const stmdev_ctx_t *ctx, + st1vafe6ax_tap_thresholds_t val) +{ + st1vafe6ax_tap_ths_6d_t tap_ths_6d; + st1vafe6ax_tap_cfg2_t tap_cfg2; + st1vafe6ax_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + + tap_cfg1.tap_ths_z = val.z; + tap_cfg2.tap_ths_y = val.y; + tap_ths_6d.tap_ths_x = val.x; + + if (ret == 0) + { + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + if (ret == 0) + { + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + } + if (ret == 0) + { + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + } + + return ret; +} + +/** + * @brief axis Tap - Double Tap recognition thresholds.[get] + * + * @param ctx read / write interface definitions + * @param val axis Tap - Double Tap recognition thresholds. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_tap_thresholds_get(const stmdev_ctx_t *ctx, + st1vafe6ax_tap_thresholds_t *val) +{ + st1vafe6ax_tap_ths_6d_t tap_ths_6d; + st1vafe6ax_tap_cfg2_t tap_cfg2; + st1vafe6ax_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1); + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + + val->z = tap_cfg1.tap_ths_z; + val->y = tap_cfg2.tap_ths_y; + val->x = tap_ths_6d.tap_ths_x; + + return ret; +} + +/** + * @brief Selection of axis priority for TAP detection.[set] + * + * @param ctx read / write interface definitions + * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY , + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_tap_axis_priority_set(const stmdev_ctx_t *ctx, + st1vafe6ax_tap_axis_priority_t val) +{ + st1vafe6ax_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + if (ret == 0) + { + tap_cfg1.tap_priority = (uint8_t)val & 0x07U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + } + + return ret; +} + +/** + * @brief Selection of axis priority for TAP detection.[get] + * + * @param ctx read / write interface definitions + * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY , + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_tap_axis_priority_get(const stmdev_ctx_t *ctx, + st1vafe6ax_tap_axis_priority_t *val) +{ + st1vafe6ax_tap_cfg1_t tap_cfg1; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1); + switch (tap_cfg1.tap_priority) + { + case ST1VAFE6AX_XYZ : + *val = ST1VAFE6AX_XYZ ; + break; + + case ST1VAFE6AX_YXZ : + *val = ST1VAFE6AX_YXZ ; + break; + + case ST1VAFE6AX_XZY: + *val = ST1VAFE6AX_XZY; + break; + + case ST1VAFE6AX_ZYX : + *val = ST1VAFE6AX_ZYX ; + break; + + case ST1VAFE6AX_YZX : + *val = ST1VAFE6AX_YZX ; + break; + + case ST1VAFE6AX_ZXY : + *val = ST1VAFE6AX_ZXY ; + break; + + default: + *val = ST1VAFE6AX_XYZ ; + break; + } + return ret; +} + + +/** + * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[set] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_tap_time_windows_set(const stmdev_ctx_t *ctx, + st1vafe6ax_tap_time_windows_t val) +{ + st1vafe6ax_tap_dur_t tap_dur; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_DUR, (uint8_t *)&tap_dur, 1); + if (ret == 0) + { + tap_dur.shock = val.shock; + tap_dur.quiet = val.quiet; + tap_dur.dur = val.tap_gap; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_TAP_DUR, (uint8_t *)&tap_dur, 1); + } + + return ret; +} + +/** + * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[get] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_tap_time_windows_get(const stmdev_ctx_t *ctx, + st1vafe6ax_tap_time_windows_t *val) +{ + st1vafe6ax_tap_dur_t tap_dur; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_DUR, (uint8_t *)&tap_dur, 1); + val->shock = tap_dur.shock; + val->quiet = tap_dur.quiet; + val->tap_gap = tap_dur.dur; + + return ret; +} + +/** + * @brief Single/double-tap event enable.[set] + * + * @param ctx read / write interface definitions + * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_tap_mode_set(const stmdev_ctx_t *ctx, st1vafe6ax_tap_mode_t val) +{ + st1vafe6ax_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + if (ret == 0) + { + wake_up_ths.single_double_tap = (uint8_t)val & 0x01U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + } + + return ret; +} + +/** + * @brief Single/double-tap event enable.[get] + * + * @param ctx read / write interface definitions + * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_tap_mode_get(const stmdev_ctx_t *ctx, st1vafe6ax_tap_mode_t *val) +{ + st1vafe6ax_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1); + switch (wake_up_ths.single_double_tap) + { + case ST1VAFE6AX_ONLY_SINGLE: + *val = ST1VAFE6AX_ONLY_SINGLE; + break; + + case ST1VAFE6AX_BOTH_SINGLE_DOUBLE: + *val = ST1VAFE6AX_BOTH_SINGLE_DOUBLE; + break; + + default: + *val = ST1VAFE6AX_ONLY_SINGLE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Six position detection (6D) + * @brief This section groups all the functions concerning six position + * detection (6D). + * @{ + * + */ + +/** + * @brief Threshold for 4D/6D function.[set] + * + * @param ctx read / write interface definitions + * @param val DEG_80, DEG_70, DEG_60, DEG_50, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_6d_threshold_set(const stmdev_ctx_t *ctx, + st1vafe6ax_6d_threshold_t val) +{ + st1vafe6ax_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + if (ret == 0) + { + tap_ths_6d.sixd_ths = (uint8_t)val & 0x03U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + } + + return ret; +} + +/** + * @brief Threshold for 4D/6D function.[get] + * + * @param ctx read / write interface definitions + * @param val DEG_80, DEG_70, DEG_60, DEG_50, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_6d_threshold_get(const stmdev_ctx_t *ctx, + st1vafe6ax_6d_threshold_t *val) +{ + st1vafe6ax_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1); + switch (tap_ths_6d.sixd_ths) + { + case ST1VAFE6AX_DEG_80: + *val = ST1VAFE6AX_DEG_80; + break; + + case ST1VAFE6AX_DEG_70: + *val = ST1VAFE6AX_DEG_70; + break; + + case ST1VAFE6AX_DEG_60: + *val = ST1VAFE6AX_DEG_60; + break; + + case ST1VAFE6AX_DEG_50: + *val = ST1VAFE6AX_DEG_50; + break; + + default: + *val = ST1VAFE6AX_DEG_80; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Free fall + * @brief This section group all the functions concerning the free + * fall detection. + * @{ + * + */ + +/** + * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[set] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + st1vafe6ax_wake_up_dur_t wake_up_dur; + st1vafe6ax_free_fall_t free_fall; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + if (ret == 0) + { + free_fall.ff_dur = (uint8_t)val & 0x1FU; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + return ret; +} + +/** + * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[get] + * + * @param ctx read / write interface definitions + * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + st1vafe6ax_wake_up_dur_t wake_up_dur; + st1vafe6ax_free_fall_t free_fall; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; + + return ret; +} + +/** + * @brief Free fall threshold setting.[set] + * + * @param ctx read / write interface definitions + * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_ff_thresholds_set(const stmdev_ctx_t *ctx, + st1vafe6ax_ff_thresholds_t val) +{ + st1vafe6ax_free_fall_t free_fall; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FREE_FALL, (uint8_t *)&free_fall, 1); + if (ret == 0) + { + free_fall.ff_ths = (uint8_t)val & 0x7U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FREE_FALL, (uint8_t *)&free_fall, 1); + } + + return ret; +} + +/** + * @brief Free fall threshold setting.[get] + * + * @param ctx read / write interface definitions + * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_ff_thresholds_get(const stmdev_ctx_t *ctx, + st1vafe6ax_ff_thresholds_t *val) +{ + st1vafe6ax_free_fall_t free_fall; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FREE_FALL, (uint8_t *)&free_fall, 1); + + switch (free_fall.ff_ths) + { + case ST1VAFE6AX_156_mg: + *val = ST1VAFE6AX_156_mg; + break; + + case ST1VAFE6AX_219_mg: + *val = ST1VAFE6AX_219_mg; + break; + + case ST1VAFE6AX_250_mg: + *val = ST1VAFE6AX_250_mg; + break; + + case ST1VAFE6AX_312_mg: + *val = ST1VAFE6AX_312_mg; + break; + + case ST1VAFE6AX_344_mg: + *val = ST1VAFE6AX_344_mg; + break; + + case ST1VAFE6AX_406_mg: + *val = ST1VAFE6AX_406_mg; + break; + + case ST1VAFE6AX_469_mg: + *val = ST1VAFE6AX_469_mg; + break; + + case ST1VAFE6AX_500_mg: + *val = ST1VAFE6AX_500_mg; + break; + + default: + *val = ST1VAFE6AX_156_mg; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup FIFO + * @brief This section group all the functions concerning the fifo usage + * @{ + * + */ + +/** + * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[set] + * + * @param ctx read / write interface definitions + * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + st1vafe6ax_fifo_ctrl1_t fifo_ctrl1; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + + if (ret == 0) + { + fifo_ctrl1.wtm = val; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + } + + return ret; +} + +/** + * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[get] + * + * @param ctx read / write interface definitions + * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + st1vafe6ax_fifo_ctrl1_t fifo_ctrl1; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); + *val = fifo_ctrl1.wtm; + + return ret; +} + +/** + * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[set] + * + * @param ctx read / write interface definitions + * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + st1vafe6ax_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.xl_dualc_batch_from_fsm = val; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[get] + * + * @param ctx read / write interface definitions + * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + st1vafe6ax_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.xl_dualc_batch_from_fsm; + + return ret; +} + +/** + * @brief It configures the compression algorithm to write non-compressed data at each rate.[set] + * + * @param ctx read / write interface definitions + * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_compress_algo_set(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_compress_algo_t val) +{ + st1vafe6ax_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.uncompr_rate = (uint8_t)val & 0x03U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief It configures the compression algorithm to write non-compressed data at each rate.[get] + * + * @param ctx read / write interface definitions + * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_compress_algo_get(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_compress_algo_t *val) +{ + st1vafe6ax_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + + switch (fifo_ctrl2.uncompr_rate) + { + case ST1VAFE6AX_CMP_DISABLE: + *val = ST1VAFE6AX_CMP_DISABLE; + break; + + case ST1VAFE6AX_CMP_8_TO_1: + *val = ST1VAFE6AX_CMP_8_TO_1; + break; + + case ST1VAFE6AX_CMP_16_TO_1: + *val = ST1VAFE6AX_CMP_16_TO_1; + break; + + case ST1VAFE6AX_CMP_32_TO_1: + *val = ST1VAFE6AX_CMP_32_TO_1; + break; + + default: + *val = ST1VAFE6AX_CMP_DISABLE; + break; + } + return ret; +} + +/** + * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set] + * + * @param ctx read / write interface definitions + * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, + uint8_t val) +{ + st1vafe6ax_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.odr_chg_en = val; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get] + * + * @param ctx read / write interface definitions + * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, + uint8_t *val) +{ + st1vafe6ax_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.odr_chg_en; + + return ret; +} + +/** + * @brief Enables/Disables compression algorithm runtime.[set] + * + * @param ctx read / write interface definitions + * @param val Enables/Disables compression algorithm runtime. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, + uint8_t val) +{ + st1vafe6ax_emb_func_en_b_t emb_func_en_b; + st1vafe6ax_fifo_ctrl2_t fifo_ctrl2; + + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.fifo_compr_rt_en = val; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + if (ret == 0) + { + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + emb_func_en_b.fifo_compr_en = val; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables/Disables compression algorithm runtime.[get] + * + * @param ctx read / write interface definitions + * @param val Enables/Disables compression algorithm runtime. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, + uint8_t *val) +{ + st1vafe6ax_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + + *val = fifo_ctrl2.fifo_compr_rt_en; + + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at threshold level.[set] + * + * @param ctx read / write interface definitions + * @param val Sensing chain FIFO stop values memorization at threshold level. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + st1vafe6ax_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + if (ret == 0) + { + fifo_ctrl2.stop_on_wtm = val; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at threshold level.[get] + * + * @param ctx read / write interface definitions + * @param val Sensing chain FIFO stop values memorization at threshold level. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + st1vafe6ax_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); + *val = fifo_ctrl2.stop_on_wtm; + + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[set] + * + * @param ctx read / write interface definitions + * @param val st1vafe6ax_fifo_xl_batch_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_xl_batch_set(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_xl_batch_t val) +{ + st1vafe6ax_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret == 0) + { + fifo_ctrl3.bdr_xl = (uint8_t)val & 0xFU; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + } + + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[get] + * + * @param ctx read / write interface definitions + * @param val st1vafe6ax_fifo_xl_batch_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_xl_batch_get(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_xl_batch_t *val) +{ + st1vafe6ax_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + switch (fifo_ctrl3.bdr_xl) + { + case ST1VAFE6AX_XL_NOT_BATCHED: + *val = ST1VAFE6AX_XL_NOT_BATCHED; + break; + + case ST1VAFE6AX_XL_BATCHED_AT_1Hz875: + *val = ST1VAFE6AX_XL_BATCHED_AT_1Hz875; + break; + + case ST1VAFE6AX_XL_BATCHED_AT_7Hz5: + *val = ST1VAFE6AX_XL_BATCHED_AT_7Hz5; + break; + + case ST1VAFE6AX_XL_BATCHED_AT_15Hz: + *val = ST1VAFE6AX_XL_BATCHED_AT_15Hz; + break; + + case ST1VAFE6AX_XL_BATCHED_AT_30Hz: + *val = ST1VAFE6AX_XL_BATCHED_AT_30Hz; + break; + + case ST1VAFE6AX_XL_BATCHED_AT_60Hz: + *val = ST1VAFE6AX_XL_BATCHED_AT_60Hz; + break; + + case ST1VAFE6AX_XL_BATCHED_AT_120Hz: + *val = ST1VAFE6AX_XL_BATCHED_AT_120Hz; + break; + + case ST1VAFE6AX_XL_BATCHED_AT_240Hz: + *val = ST1VAFE6AX_XL_BATCHED_AT_240Hz; + break; + + case ST1VAFE6AX_XL_BATCHED_AT_480Hz: + *val = ST1VAFE6AX_XL_BATCHED_AT_480Hz; + break; + + case ST1VAFE6AX_XL_BATCHED_AT_960Hz: + *val = ST1VAFE6AX_XL_BATCHED_AT_960Hz; + break; + + case ST1VAFE6AX_XL_BATCHED_AT_1920Hz: + *val = ST1VAFE6AX_XL_BATCHED_AT_1920Hz; + break; + + case ST1VAFE6AX_XL_BATCHED_AT_3840Hz: + *val = ST1VAFE6AX_XL_BATCHED_AT_3840Hz; + break; + + default: + *val = ST1VAFE6AX_XL_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[set] + * + * @param ctx read / write interface definitions + * @param val st1vafe6ax_fifo_gy_batch_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_gy_batch_set(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_gy_batch_t val) +{ + st1vafe6ax_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + if (ret == 0) + { + fifo_ctrl3.bdr_gy = (uint8_t)val & 0xFU; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + } + + return ret; +} + +/** + * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[get] + * + * @param ctx read / write interface definitions + * @param val st1vafe6ax_fifo_gy_batch_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_gy_batch_get(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_gy_batch_t *val) +{ + st1vafe6ax_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1); + switch (fifo_ctrl3.bdr_gy) + { + case ST1VAFE6AX_GY_NOT_BATCHED: + *val = ST1VAFE6AX_GY_NOT_BATCHED; + break; + + case ST1VAFE6AX_GY_BATCHED_AT_1Hz875: + *val = ST1VAFE6AX_GY_BATCHED_AT_1Hz875; + break; + + case ST1VAFE6AX_GY_BATCHED_AT_7Hz5: + *val = ST1VAFE6AX_GY_BATCHED_AT_7Hz5; + break; + + case ST1VAFE6AX_GY_BATCHED_AT_15Hz: + *val = ST1VAFE6AX_GY_BATCHED_AT_15Hz; + break; + + case ST1VAFE6AX_GY_BATCHED_AT_30Hz: + *val = ST1VAFE6AX_GY_BATCHED_AT_30Hz; + break; + + case ST1VAFE6AX_GY_BATCHED_AT_60Hz: + *val = ST1VAFE6AX_GY_BATCHED_AT_60Hz; + break; + + case ST1VAFE6AX_GY_BATCHED_AT_120Hz: + *val = ST1VAFE6AX_GY_BATCHED_AT_120Hz; + break; + + case ST1VAFE6AX_GY_BATCHED_AT_240Hz: + *val = ST1VAFE6AX_GY_BATCHED_AT_240Hz; + break; + + case ST1VAFE6AX_GY_BATCHED_AT_480Hz: + *val = ST1VAFE6AX_GY_BATCHED_AT_480Hz; + break; + + case ST1VAFE6AX_GY_BATCHED_AT_960Hz: + *val = ST1VAFE6AX_GY_BATCHED_AT_960Hz; + break; + + case ST1VAFE6AX_GY_BATCHED_AT_1920Hz: + *val = ST1VAFE6AX_GY_BATCHED_AT_1920Hz; + break; + + case ST1VAFE6AX_GY_BATCHED_AT_3840Hz: + *val = ST1VAFE6AX_GY_BATCHED_AT_3840Hz; + break; + + default: + *val = ST1VAFE6AX_GY_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief FIFO mode selection.[set] + * + * @param ctx read / write interface definitions + * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_mode_set(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_mode_t val) +{ + st1vafe6ax_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.fifo_mode = (uint8_t)val & 0x07U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief FIFO mode selection.[get] + * + * @param ctx read / write interface definitions + * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_mode_get(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_mode_t *val) +{ + st1vafe6ax_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + switch (fifo_ctrl4.fifo_mode) + { + case ST1VAFE6AX_BYPASS_MODE: + *val = ST1VAFE6AX_BYPASS_MODE; + break; + + case ST1VAFE6AX_FIFO_MODE: + *val = ST1VAFE6AX_FIFO_MODE; + break; + + case ST1VAFE6AX_STREAM_WTM_TO_FULL_MODE: + *val = ST1VAFE6AX_STREAM_WTM_TO_FULL_MODE; + break; + + case ST1VAFE6AX_STREAM_TO_FIFO_MODE: + *val = ST1VAFE6AX_STREAM_TO_FIFO_MODE; + break; + + case ST1VAFE6AX_BYPASS_TO_STREAM_MODE: + *val = ST1VAFE6AX_BYPASS_TO_STREAM_MODE; + break; + + case ST1VAFE6AX_STREAM_MODE: + *val = ST1VAFE6AX_STREAM_MODE; + break; + + case ST1VAFE6AX_BYPASS_TO_FIFO_MODE: + *val = ST1VAFE6AX_BYPASS_TO_FIFO_MODE; + break; + + default: + *val = ST1VAFE6AX_BYPASS_MODE; + break; + } + return ret; +} + +/** + * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[set] + * + * @param ctx read / write interface definitions + * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_temp_batch_set(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_temp_batch_t val) +{ + st1vafe6ax_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.odr_t_batch = (uint8_t)val & 0x03U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[get] + * + * @param ctx read / write interface definitions + * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_temp_batch_get(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_temp_batch_t *val) +{ + st1vafe6ax_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + switch (fifo_ctrl4.odr_t_batch) + { + case ST1VAFE6AX_TEMP_NOT_BATCHED: + *val = ST1VAFE6AX_TEMP_NOT_BATCHED; + break; + + case ST1VAFE6AX_TEMP_BATCHED_AT_1Hz875: + *val = ST1VAFE6AX_TEMP_BATCHED_AT_1Hz875; + break; + + case ST1VAFE6AX_TEMP_BATCHED_AT_15Hz: + *val = ST1VAFE6AX_TEMP_BATCHED_AT_15Hz; + break; + + case ST1VAFE6AX_TEMP_BATCHED_AT_60Hz: + *val = ST1VAFE6AX_TEMP_BATCHED_AT_60Hz; + break; + + default: + *val = ST1VAFE6AX_TEMP_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[set] + * + * @param ctx read / write interface definitions + * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_timestamp_batch_t val) +{ + st1vafe6ax_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + if (ret == 0) + { + fifo_ctrl4.dec_ts_batch = (uint8_t)val & 0x3U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + } + + return ret; +} + +/** + * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[get] + * + * @param ctx read / write interface definitions + * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_timestamp_batch_t *val) +{ + st1vafe6ax_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1); + switch (fifo_ctrl4.dec_ts_batch) + { + case ST1VAFE6AX_TMSTMP_NOT_BATCHED: + *val = ST1VAFE6AX_TMSTMP_NOT_BATCHED; + break; + + case ST1VAFE6AX_TMSTMP_DEC_1: + *val = ST1VAFE6AX_TMSTMP_DEC_1; + break; + + case ST1VAFE6AX_TMSTMP_DEC_8: + *val = ST1VAFE6AX_TMSTMP_DEC_8; + break; + + case ST1VAFE6AX_TMSTMP_DEC_32: + *val = ST1VAFE6AX_TMSTMP_DEC_32; + break; + + default: + *val = ST1VAFE6AX_TMSTMP_NOT_BATCHED; + break; + } + return ret; +} + +/** + * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[set] + * + * @param ctx read / write interface definitions + * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx, + uint16_t val) +{ + st1vafe6ax_counter_bdr_reg1_t counter_bdr_reg1; + st1vafe6ax_counter_bdr_reg2_t counter_bdr_reg2; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + + if (ret == 0) + { + counter_bdr_reg2.cnt_bdr_th = (uint8_t)val & 0xFFU; + counter_bdr_reg1.cnt_bdr_th = (uint8_t)(val >> 8) & 0x3U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_COUNTER_BDR_REG2, (uint8_t *)&counter_bdr_reg2, 1); + } + + return ret; +} + +/** + * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[get] + * + * @param ctx read / write interface definitions + * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx, + uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_COUNTER_BDR_REG1, &buff[0], 2); + *val = (uint16_t)buff[0] & 0x3U; + *val = (*val * 256U) + (uint16_t)buff[1]; + + return ret; +} + +/** + * @brief Enables AH_BIO batching in FIFO.[set] + * + * @param ctx read / write interface definitions + * @param val Enables AH_BIO batching in FIFO. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_batch_ah_bio_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + st1vafe6ax_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + if (ret == 0) + { + counter_bdr_reg1.ah_bio_batch_en = val; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + } + + return ret; +} + +/** + * @brief Enables AH_BIO batching in FIFO.[get] + * + * @param ctx read / write interface definitions + * @param val Enables AH_BIO batching in FIFO. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_batch_ah_bio_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + st1vafe6ax_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + *val = counter_bdr_reg1.ah_bio_batch_en; + + return ret; +} + +/** + * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope.[set] + * + * @param ctx read / write interface definitions + * @param val XL_BATCH_EVENT, GY_BATCH_EVENT + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_batch_cnt_event_set(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_batch_cnt_event_t val) +{ + st1vafe6ax_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + + if (ret == 0) + { + counter_bdr_reg1.trig_counter_bdr = (uint8_t)val & 0x03U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + } + + return ret; +} + +/** + * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope.[get] + * + * @param ctx read / write interface definitions + * @param val XL_BATCH_EVENT, GY_BATCH_EVENT + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_batch_cnt_event_t *val) +{ + st1vafe6ax_counter_bdr_reg1_t counter_bdr_reg1; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1); + switch (counter_bdr_reg1.trig_counter_bdr) + { + case ST1VAFE6AX_XL_BATCH_EVENT: + *val = ST1VAFE6AX_XL_BATCH_EVENT; + break; + + case ST1VAFE6AX_GY_BATCH_EVENT: + *val = ST1VAFE6AX_GY_BATCH_EVENT; + break; + + default: + *val = ST1VAFE6AX_XL_BATCH_EVENT; + break; + } + return ret; +} + +/** + * @brief Batching in FIFO buffer of SFLP.[set] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of SFLP values. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_sflp_batch_set(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_sflp_raw_t val) +{ + st1vafe6ax_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + emb_func_fifo_en_a.sflp_game_fifo_en = val.game_rotation; + emb_func_fifo_en_a.sflp_gravity_fifo_en = val.gravity; + emb_func_fifo_en_a.sflp_gbias_fifo_en = val.gbias; + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_FIFO_EN_A, + (uint8_t *)&emb_func_fifo_en_a, 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of SFLP.[get] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of SFLP values. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_sflp_batch_get(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_sflp_raw_t *val) +{ + st1vafe6ax_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + + val->game_rotation = emb_func_fifo_en_a.sflp_game_fifo_en; + val->gravity = emb_func_fifo_en_a.sflp_gravity_fifo_en; + val->gbias = emb_func_fifo_en_a.sflp_gbias_fifo_en; + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Status of FIFO.[get] + * + * @param ctx read / write interface definitions + * @param val Status of FIFO (level and flags). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_status_get(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_status_t *val) +{ + uint8_t buff[2]; + st1vafe6ax_fifo_status2_t status; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_STATUS1, (uint8_t *)&buff[0], 2); + bytecpy((uint8_t *)&status, &buff[1]); + + val->fifo_bdr = status.counter_bdr_ia; + val->fifo_ovr = status.fifo_ovr_ia; + val->fifo_full = status.fifo_full_ia; + val->fifo_th = status.fifo_wtm_ia; + + val->fifo_level = (uint16_t)buff[1] & 0x01U; + val->fifo_level = (val->fifo_level * 256U) + buff[0]; + + return ret; +} + +/** + * @brief FIFO data output[get] + * + * @param ctx read / write interface definitions + * @param val st1vafe6ax_fifo_out_raw_t enum + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_out_raw_get(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_out_raw_t *val) +{ + st1vafe6ax_fifo_data_out_tag_t fifo_data_out_tag; + uint8_t buff[7]; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FIFO_DATA_OUT_TAG, buff, 7); + bytecpy((uint8_t *)&fifo_data_out_tag, &buff[0]); + + switch (fifo_data_out_tag.tag_sensor) + { + case ST1VAFE6AX_FIFO_EMPTY: + val->tag = ST1VAFE6AX_FIFO_EMPTY; + break; + + case ST1VAFE6AX_GY_NC_TAG: + val->tag = ST1VAFE6AX_GY_NC_TAG; + break; + + case ST1VAFE6AX_XL_NC_TAG: + val->tag = ST1VAFE6AX_XL_NC_TAG; + break; + + case ST1VAFE6AX_TIMESTAMP_TAG: + val->tag = ST1VAFE6AX_TIMESTAMP_TAG; + break; + + case ST1VAFE6AX_TEMPERATURE_TAG: + val->tag = ST1VAFE6AX_TEMPERATURE_TAG; + break; + + case ST1VAFE6AX_CFG_CHANGE_TAG: + val->tag = ST1VAFE6AX_CFG_CHANGE_TAG; + break; + + case ST1VAFE6AX_XL_NC_T_2_TAG: + val->tag = ST1VAFE6AX_XL_NC_T_2_TAG; + break; + + case ST1VAFE6AX_XL_NC_T_1_TAG: + val->tag = ST1VAFE6AX_XL_NC_T_1_TAG; + break; + + case ST1VAFE6AX_XL_2XC_TAG: + val->tag = ST1VAFE6AX_XL_2XC_TAG; + break; + + case ST1VAFE6AX_XL_3XC_TAG: + val->tag = ST1VAFE6AX_XL_3XC_TAG; + break; + + case ST1VAFE6AX_GY_NC_T_2_TAG: + val->tag = ST1VAFE6AX_GY_NC_T_2_TAG; + break; + + case ST1VAFE6AX_GY_NC_T_1_TAG: + val->tag = ST1VAFE6AX_GY_NC_T_1_TAG; + break; + + case ST1VAFE6AX_GY_2XC_TAG: + val->tag = ST1VAFE6AX_GY_2XC_TAG; + break; + + case ST1VAFE6AX_GY_3XC_TAG: + val->tag = ST1VAFE6AX_GY_3XC_TAG; + break; + + case ST1VAFE6AX_STEP_COUNTER_TAG: + val->tag = ST1VAFE6AX_STEP_COUNTER_TAG; + break; + + case ST1VAFE6AX_MLC_RESULT_TAG: + val->tag = ST1VAFE6AX_MLC_RESULT_TAG; + break; + + case ST1VAFE6AX_SFLP_GAME_ROTATION_VECTOR_TAG: + val->tag = ST1VAFE6AX_SFLP_GAME_ROTATION_VECTOR_TAG; + break; + + case ST1VAFE6AX_SFLP_GYROSCOPE_BIAS_TAG: + val->tag = ST1VAFE6AX_SFLP_GYROSCOPE_BIAS_TAG; + break; + + case ST1VAFE6AX_SFLP_GRAVITY_VECTOR_TAG: + val->tag = ST1VAFE6AX_SFLP_GRAVITY_VECTOR_TAG; + break; + + case ST1VAFE6AX_MLC_FILTER: + val->tag = ST1VAFE6AX_MLC_FILTER; + break; + + case ST1VAFE6AX_MLC_FEATURE: + val->tag = ST1VAFE6AX_MLC_FEATURE; + break; + + case ST1VAFE6AX_XL_DUAL_CORE: + val->tag = ST1VAFE6AX_XL_DUAL_CORE; + break; + + case ST1VAFE6AX_AH_VAFE: + val->tag = ST1VAFE6AX_AH_VAFE; + break; + + default: + val->tag = ST1VAFE6AX_FIFO_EMPTY; + break; + } + + val->cnt = fifo_data_out_tag.tag_cnt; + + val->data[0] = buff[1]; + val->data[1] = buff[2]; + val->data[2] = buff[3]; + val->data[3] = buff[4]; + val->data[4] = buff[5]; + val->data[5] = buff[6]; + + return ret; +} + +/** + * @brief Batching in FIFO buffer of step counter value.[set] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of step counter value. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + st1vafe6ax_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + if (ret == 0) + { + emb_func_fifo_en_a.step_counter_fifo_en = val; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of step counter value.[get] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of step counter value. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + st1vafe6ax_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + *val = emb_func_fifo_en_a.step_counter_fifo_en; + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + + return ret; +} + +/** + * @brief Batching in FIFO buffer of machine learning core results.[set] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of machine learning core results. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_mlc_batch_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + st1vafe6ax_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + if (ret == 0) + { + emb_func_fifo_en_a.mlc_fifo_en = val; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Batching in FIFO buffer of machine learning core results.[get] + * + * @param ctx read / write interface definitions + * @param val Batching in FIFO buffer of machine learning core results. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_mlc_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + st1vafe6ax_emb_func_fifo_en_a_t emb_func_fifo_en_a; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1); + } + + *val = emb_func_fifo_en_a.mlc_fifo_en; + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables batching in FIFO buffer of machine learning core filters and features.[set] + * + * @param ctx read / write interface definitions + * @param val Enables batching in FIFO buffer of machine learning core filters and features. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_mlc_filt_batch_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + st1vafe6ax_emb_func_fifo_en_b_t emb_func_fifo_en_b; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + } + + if (ret == 0) + { + emb_func_fifo_en_b.mlc_filter_feature_fifo_en = val; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enables batching in FIFO buffer of machine learning core filters and features.[get] + * + * @param ctx read / write interface definitions + * @param val Enables batching in FIFO buffer of machine learning core filters and features. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fifo_mlc_filt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + st1vafe6ax_emb_func_fifo_en_b_t emb_func_fifo_en_b; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1); + } + + *val = emb_func_fifo_en_b.mlc_filter_feature_fifo_en; + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Step Counter + * @brief This section groups all the functions that manage pedometer. + * @{ + * + */ + +/** + * @brief Step counter mode[set] + * + * @param ctx read / write interface definitions + * @param val false_step_rej, step_counter, step_detector, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_stpcnt_mode_set(const stmdev_ctx_t *ctx, + st1vafe6ax_stpcnt_mode_t val) +{ + st1vafe6ax_emb_func_en_a_t emb_func_en_a; + st1vafe6ax_emb_func_en_b_t emb_func_en_b; + st1vafe6ax_pedo_cmd_reg_t pedo_cmd_reg; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + if ((val.false_step_rej == PROPERTY_ENABLE) + && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) == + PROPERTY_DISABLE)) + { + emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE; + } + if (ret == 0) + { + emb_func_en_a.pedo_en = val.step_counter_enable; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = st1vafe6ax_ln_pg_read(ctx, ST1VAFE6AX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + if (ret == 0) + { + pedo_cmd_reg.fp_rejection_en = val.false_step_rej; + ret = st1vafe6ax_ln_pg_write(ctx, ST1VAFE6AX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + + return ret; +} + +/** + * @brief Step counter mode[get] + * + * @param ctx read / write interface definitions + * @param val false_step_rej, step_counter, step_detector, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_stpcnt_mode_get(const stmdev_ctx_t *ctx, + st1vafe6ax_stpcnt_mode_t *val) +{ + st1vafe6ax_emb_func_en_a_t emb_func_en_a; + st1vafe6ax_pedo_cmd_reg_t pedo_cmd_reg; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + if (ret == 0) + { + ret = st1vafe6ax_ln_pg_read(ctx, ST1VAFE6AX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1); + } + val->false_step_rej = pedo_cmd_reg.fp_rejection_en; + val->step_counter_enable = emb_func_en_a.pedo_en; + + return ret; +} + +/** + * @brief Step counter output, number of detected steps.[get] + * + * @param ctx read / write interface definitions + * @param val Step counter output, number of detected steps. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_STEP_COUNTER_L, &buff[0], 2); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief Reset step counter.[set] + * + * @param ctx read / write interface definitions + * @param val Reset step counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_stpcnt_rst_step_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + st1vafe6ax_emb_func_src_t emb_func_src; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + + if (ret == 0) + { + emb_func_src.pedo_rst_step = val; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Reset step counter.[get] + * + * @param ctx read / write interface definitions + * @param val Reset step counter. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + st1vafe6ax_emb_func_src_t emb_func_src; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1); + } + + *val = emb_func_src.pedo_rst_step; + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Pedometer debounce configuration.[set] + * + * @param ctx read / write interface definitions + * @param val Pedometer debounce configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + st1vafe6ax_pedo_deb_steps_conf_t pedo_deb_steps_conf; + int32_t ret; + + ret = st1vafe6ax_ln_pg_read(ctx, ST1VAFE6AX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, + 1); + if (ret == 0) + { + pedo_deb_steps_conf.deb_step = val; + ret = st1vafe6ax_ln_pg_write(ctx, ST1VAFE6AX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, + 1); + } + + return ret; +} + +/** + * @brief Pedometer debounce configuration.[get] + * + * @param ctx read / write interface definitions + * @param val Pedometer debounce configuration. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + st1vafe6ax_pedo_deb_steps_conf_t pedo_deb_steps_conf; + int32_t ret; + + ret = st1vafe6ax_ln_pg_read(ctx, ST1VAFE6AX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, + 1); + *val = pedo_deb_steps_conf.deb_step; + + return ret; +} + +/** + * @brief Time period register for step detection on delta time.[set] + * + * @param ctx read / write interface definitions + * @param val Time period register for step detection on delta time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + + ret = st1vafe6ax_ln_pg_write(ctx, ST1VAFE6AX_PEDO_SC_DELTAT_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief Time period register for step detection on delta time.[get] + * + * @param ctx read / write interface definitions + * @param val Time period register for step detection on delta time. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = st1vafe6ax_ln_pg_read(ctx, ST1VAFE6AX_PEDO_SC_DELTAT_L, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Significant motion + * @brief This section groups all the functions that manage the + * significant motion detection. + * @{ + * + */ + +/** + * @brief Enables significant motion detection function.[set] + * + * @param ctx read / write interface definitions + * @param val Enables significant motion detection function. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + st1vafe6ax_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { + emb_func_en_a.sign_motion_en = val; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + + return ret; +} + +/** + * @brief Enables significant motion detection function.[get] + * + * @param ctx read / write interface definitions + * @param val Enables significant motion detection function. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + st1vafe6ax_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + *val = emb_func_en_a.sign_motion_en; + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Tilt detection + * @brief This section groups all the functions that manage the tilt + * event detection. + * @{ + * + */ + +/** + * @brief Tilt calculation.[set] + * + * @param ctx read / write interface definitions + * @param val Tilt calculation. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + st1vafe6ax_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + if (ret == 0) + { + emb_func_en_a.tilt_en = val; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Tilt calculation.[get] + * + * @param ctx read / write interface definitions + * @param val Tilt calculation. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + st1vafe6ax_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + } + *val = emb_func_en_a.tilt_en; + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Sensor Fusion Low Power (SFLP) + * @brief This section groups all the functions that manage pedometer. + * @{ + * + */ + +/** + * @brief Enable SFLP Game Rotation Vector (6x).[set] + * + * @param ctx read / write interface definitions + * @param val Enable/Disable game rotation value (0/1). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + st1vafe6ax_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + emb_func_en_a.sflp_game_en = val; + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, + (uint8_t *)&emb_func_en_a, 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable SFLP Game Rotation Vector (6x).[get] + * + * @param ctx read / write interface definitions + * @param val Enable/Disable game rotation value (0/1). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + st1vafe6ax_emb_func_en_a_t emb_func_en_a; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1); + *val = emb_func_en_a.sflp_game_en; + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief SFLP Data Rate (ODR) configuration.[set] + * + * @param ctx read / write interface definitions + * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_sflp_data_rate_set(const stmdev_ctx_t *ctx, + st1vafe6ax_sflp_data_rate_t val) +{ + st1vafe6ax_sflp_odr_t sflp_odr; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + sflp_odr.sflp_game_odr = (uint8_t)val & 0x07U; + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_SFLP_ODR, (uint8_t *)&sflp_odr, + 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief SFLP Data Rate (ODR) configuration.[get] + * + * @param ctx read / write interface definitions + * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_sflp_data_rate_get(const stmdev_ctx_t *ctx, + st1vafe6ax_sflp_data_rate_t *val) +{ + st1vafe6ax_sflp_odr_t sflp_odr; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_SFLP_ODR, (uint8_t *)&sflp_odr, 1); + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + switch (sflp_odr.sflp_game_odr) + { + case ST1VAFE6AX_SFLP_15Hz: + *val = ST1VAFE6AX_SFLP_15Hz; + break; + + case ST1VAFE6AX_SFLP_30Hz: + *val = ST1VAFE6AX_SFLP_30Hz; + break; + + case ST1VAFE6AX_SFLP_60Hz: + *val = ST1VAFE6AX_SFLP_60Hz; + break; + + case ST1VAFE6AX_SFLP_120Hz: + *val = ST1VAFE6AX_SFLP_120Hz; + break; + + case ST1VAFE6AX_SFLP_240Hz: + *val = ST1VAFE6AX_SFLP_240Hz; + break; + + case ST1VAFE6AX_SFLP_480Hz: + *val = ST1VAFE6AX_SFLP_480Hz; + break; + + default: + *val = ST1VAFE6AX_SFLP_15Hz; + break; + } + return ret; +} + +/* + * Original conversion routines taken from: https://github.com/numpy/numpy + * + * uint16_t npy_floatbits_to_halfbits(uint32_t f); + * uint16_t npy_float_to_half(float_t f); + * + * Released under BSD-3-Clause License + */ + +#define NPY_HALF_GENERATE_OVERFLOW 0 /* do not trigger FP overflow */ +#define NPY_HALF_GENERATE_UNDERFLOW 0 /* do not trigger FP underflow */ +#ifndef NPY_HALF_ROUND_TIES_TO_EVEN +#define NPY_HALF_ROUND_TIES_TO_EVEN 1 +#endif + +static uint16_t npy_floatbits_to_halfbits(uint32_t f) +{ + uint32_t f_exp, f_sig; + uint16_t h_sgn, h_exp, h_sig; + + h_sgn = (uint16_t)((f & 0x80000000u) >> 16); + f_exp = (f & 0x7f800000u); + + /* Exponent overflow/NaN converts to signed inf/NaN */ + if (f_exp >= 0x47800000u) + { + if (f_exp == 0x7f800000u) + { + /* Inf or NaN */ + f_sig = (f & 0x007fffffu); + if (f_sig != 0) + { + /* NaN - propagate the flag in the significand... */ + uint16_t ret = (uint16_t)(0x7c00u + (f_sig >> 13)); + /* ...but make sure it stays a NaN */ + if (ret == 0x7c00u) + { + ret++; + } + return h_sgn + ret; + } + else + { + /* signed inf */ + return (uint16_t)(h_sgn + 0x7c00u); + } + } + else + { + /* overflow to signed inf */ +#if NPY_HALF_GENERATE_OVERFLOW + npy_set_floatstatus_overflow(); +#endif + return (uint16_t)(h_sgn + 0x7c00u); + } + } + + /* Exponent underflow converts to a subnormal half or signed zero */ + if (f_exp <= 0x38000000u) + { + /* + * Signed zeros, subnormal floats, and floats with small + * exponents all convert to signed zero half-floats. + */ + if (f_exp < 0x33000000u) + { +#if NPY_HALF_GENERATE_UNDERFLOW + /* If f != 0, it underflowed to 0 */ + if ((f & 0x7fffffff) != 0) + { + npy_set_floatstatus_underflow(); + } +#endif + return h_sgn; + } + /* Make the subnormal significand */ + f_exp >>= 23; + f_sig = (0x00800000u + (f & 0x007fffffu)); +#if NPY_HALF_GENERATE_UNDERFLOW + /* If it's not exactly represented, it underflowed */ + if ((f_sig & (((uint32_t)1 << (126 - f_exp)) - 1)) != 0) + { + npy_set_floatstatus_underflow(); + } +#endif + /* + * Usually the significand is shifted by 13. For subnormals an + * additional shift needs to occur. This shift is one for the largest + * exponent giving a subnormal `f_exp = 0x38000000 >> 23 = 112`, which + * offsets the new first bit. At most the shift can be 1+10 bits. + */ + f_sig >>= (113 - f_exp); + /* Handle rounding by adding 1 to the bit beyond half precision */ +#if NPY_HALF_ROUND_TIES_TO_EVEN + /* + * If the last bit in the half significand is 0 (already even), and + * the remaining bit pattern is 1000...0, then we do not add one + * to the bit after the half significand. However, the (113 - f_exp) + * shift can lose up to 11 bits, so the || checks them in the original. + * In all other cases, we can just add one. + */ + if (((f_sig & 0x00003fffu) != 0x00001000u) || (f & 0x000007ffu)) + { + f_sig += 0x00001000u; + } +#else + f_sig += 0x00001000u; +#endif + h_sig = (uint16_t)(f_sig >> 13); + /* + * If the rounding causes a bit to spill into h_exp, it will + * increment h_exp from zero to one and h_sig will be zero. + * This is the correct result. + */ + return (uint16_t)(h_sgn + h_sig); + } + + /* Regular case with no overflow or underflow */ + h_exp = (uint16_t)((f_exp - 0x38000000u) >> 13); + /* Handle rounding by adding 1 to the bit beyond half precision */ + f_sig = (f & 0x007fffffu); +#if NPY_HALF_ROUND_TIES_TO_EVEN + /* + * If the last bit in the half significand is 0 (already even), and + * the remaining bit pattern is 1000...0, then we do not add one + * to the bit after the half significand. In all other cases, we do. + */ + if ((f_sig & 0x00003fffu) != 0x00001000u) + { + f_sig += 0x00001000u; + } +#else + f_sig += 0x00001000u; +#endif + h_sig = (uint16_t)(f_sig >> 13); + /* + * If the rounding causes a bit to spill into h_exp, it will + * increment h_exp by one and h_sig will be zero. This is the + * correct result. h_exp may increment to 15, at greatest, in + * which case the result overflows to a signed inf. + */ +#if NPY_HALF_GENERATE_OVERFLOW + h_sig += h_exp; + if (h_sig == 0x7c00u) + { + npy_set_floatstatus_overflow(); + } + return h_sgn + h_sig; +#else + return h_sgn + h_exp + h_sig; +#endif +} + +static uint16_t npy_float_to_half(float_t f) +{ + union + { + float_t f; + uint32_t fbits; + } conv; + conv.f = f; + return npy_floatbits_to_halfbits(conv.fbits); +} + +/** + * @brief SFLP GBIAS value. The register value is expressed as half-precision + * floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent + * bits; F: 10 fraction bits).[set] + * + * @param ctx read / write interface definitions + * @param val GBIAS x/y/z val. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_sflp_game_gbias_set(const stmdev_ctx_t *ctx, + st1vafe6ax_sflp_gbias_t *val) +{ + st1vafe6ax_sflp_data_rate_t sflp_odr; + st1vafe6ax_emb_func_exec_status_t emb_func_sts; + st1vafe6ax_data_ready_t drdy; + st1vafe6ax_xl_full_scale_t xl_fs; + st1vafe6ax_ctrl10_t ctrl10; + uint8_t master_config; + uint8_t emb_func_en_saved[2]; + uint8_t conf_saved[2]; + uint8_t reg_zero[2] = {0x0, 0x0}; + uint16_t gbias_hf[3]; + float_t k = 0.005f; + int16_t xl_data[3]; + int32_t data_tmp; + uint8_t *data_ptr = (uint8_t *)&data_tmp; + uint8_t i, j; + int32_t ret; + + ret = st1vafe6ax_sflp_data_rate_get(ctx, &sflp_odr); + if (ret != 0) + { + return ret; + } + + /* Calculate k factor */ + switch (sflp_odr) + { + case ST1VAFE6AX_SFLP_15Hz: + k = 0.04f; + break; + case ST1VAFE6AX_SFLP_30Hz: + k = 0.02f; + break; + case ST1VAFE6AX_SFLP_60Hz: + k = 0.01f; + break; + case ST1VAFE6AX_SFLP_120Hz: + k = 0.005f; + break; + case ST1VAFE6AX_SFLP_240Hz: + k = 0.0025f; + break; + case ST1VAFE6AX_SFLP_480Hz: + k = 0.00125f; + break; + } + + /* compute gbias as half precision float in order to be put in embedded advanced feature register */ + gbias_hf[0] = npy_float_to_half(val->gbias_x * (3.14159265358979323846f / 180.0f) / k); + gbias_hf[1] = npy_float_to_half(val->gbias_y * (3.14159265358979323846f / 180.0f) / k); + gbias_hf[2] = npy_float_to_half(val->gbias_z * (3.14159265358979323846f / 180.0f) / k); + + /* Save sensor configuration and set high-performance mode (if the sensor is in power-down mode, turn it on) */ + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL1, conf_saved, 2); + ret += st1vafe6ax_xl_mode_set(ctx, ST1VAFE6AX_XL_HIGH_PERFORMANCE_MD); + ret += st1vafe6ax_gy_mode_set(ctx, ST1VAFE6AX_GY_HIGH_PERFORMANCE_MD); + if ((conf_saved[0] & 0x0FU) == ST1VAFE6AX_XL_ODR_OFF) + { + ret += st1vafe6ax_xl_data_rate_set(ctx, ST1VAFE6AX_XL_ODR_AT_120Hz); + } + + /* disable algos */ + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, emb_func_en_saved, + 2); + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, reg_zero, 2); + do + { + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EXEC_STATUS, + (uint8_t *)&emb_func_sts, 1); + } while (emb_func_sts.emb_func_endop != 1); + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + // enable gbias setting + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL10, (uint8_t *)&ctrl10, 1); + ctrl10.emb_func_debug = 1; + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL10, (uint8_t *)&ctrl10, 1); + + /* enable algos */ + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + emb_func_en_saved[0] |= 0x02; /* force SFLP GAME en */ + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, emb_func_en_saved, + 2); + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + ret += st1vafe6ax_xl_full_scale_get(ctx, &xl_fs); + + /* Read XL data */ + do + { + ret += st1vafe6ax_flag_data_ready_get(ctx, &drdy); + } while (drdy.drdy_xl != 1); + ret += st1vafe6ax_acceleration_raw_get(ctx, xl_data); + + /* force sflp initialization */ + master_config = 0x40; + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FUNC_CFG_ACCESS, &master_config, + 1); + for (i = 0; i < 3; i++) + { + j = 0; + data_tmp = (int32_t)xl_data[i]; + data_tmp <<= xl_fs; // shift based on current fs + ret += st1vafe6ax_write_reg(ctx, 0x02 + 3 * i, &data_ptr[j++], 1); + ret += st1vafe6ax_write_reg(ctx, 0x03 + 3 * i, &data_ptr[j++], 1); + ret += st1vafe6ax_write_reg(ctx, 0x04 + 3 * i, &data_ptr[j], 1); + } + for (i = 0; i < 3; i++) + { + j = 0; + data_tmp = 0; + ret += st1vafe6ax_write_reg(ctx, 0x0B + 3 * i, &data_ptr[j++], 1); + ret += st1vafe6ax_write_reg(ctx, 0x0C + 3 * i, &data_ptr[j++], 1); + ret += st1vafe6ax_write_reg(ctx, 0x0D + 3 * i, &data_ptr[j], 1); + } + master_config = 0x00; + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FUNC_CFG_ACCESS, &master_config, + 1); + + // wait end_op (and at least 30 us) + ctx->mdelay(1); + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + do + { + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EXEC_STATUS, + (uint8_t *)&emb_func_sts, 1); + } while (emb_func_sts.emb_func_endop != 1); + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + /* write gbias in embedded advanced features registers */ + ret += st1vafe6ax_ln_pg_write(ctx, ST1VAFE6AX_SFLP_GAME_GBIASX_L, + (uint8_t *)gbias_hf, 6); + + /* reload previous sensor configuration */ + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL1, conf_saved, 2); + + // disable gbias setting + ctrl10.emb_func_debug = 0; + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL10, (uint8_t *)&ctrl10, 1); + + return ret; +} + +/** + * @brief SFLP initial configuration [set] + * + * @param ctx read / write interface definitions + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_sflp_configure(const stmdev_ctx_t *ctx) +{ + uint8_t val = 0x50; + int32_t ret; + + ret = st1vafe6ax_ln_pg_write(ctx, 0xD2, &val, 1); + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup Finite State Machine (FSM) + * @brief This section groups all the functions that manage the + * state_machine. + * @{ + * + */ + +/** + * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[set] + * + * @param ctx read / write interface definitions + * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fsm_permission_set(const stmdev_ctx_t *ctx, + st1vafe6ax_fsm_permission_t val) +{ + st1vafe6ax_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + if (ret == 0) + { + func_cfg_access.fsm_wr_ctrl_en = (uint8_t)val & 0x01U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[get] + * + * @param ctx read / write interface definitions + * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fsm_permission_get(const stmdev_ctx_t *ctx, + st1vafe6ax_fsm_permission_t *val) +{ + st1vafe6ax_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1); + switch (func_cfg_access.fsm_wr_ctrl_en) + { + case ST1VAFE6AX_PROTECT_CTRL_REGS: + *val = ST1VAFE6AX_PROTECT_CTRL_REGS; + break; + + case ST1VAFE6AX_WRITE_CTRL_REG: + *val = ST1VAFE6AX_WRITE_CTRL_REG; + break; + + default: + *val = ST1VAFE6AX_PROTECT_CTRL_REGS; + break; + } + return ret; +} + +/** + * @brief Return the status of the CTRL registers permission (standard interface vs FSM).[get] + * + * @param ctx read / write interface definitions + * @param val 0: all FSM regs are under std_if control, 1: some regs are under FSM control. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fsm_permission_status(const stmdev_ctx_t *ctx, + st1vafe6ax_fsm_permission_status_t *val) +{ + st1vafe6ax_ctrl_status_t status; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL_STATUS, (uint8_t *)&status, 1); + *val = (status.fsm_wr_ctrl_status == 0) ? ST1VAFE6AX_STD_IF_CONTROL : ST1VAFE6AX_FSM_CONTROL; + + return ret; +} + +/** + * @brief Enable Finite State Machine (FSM) feature.[set] + * + * @param ctx read / write interface definitions + * @param val Enable Finite State Machine (FSM) feature. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fsm_mode_set(const stmdev_ctx_t *ctx, st1vafe6ax_fsm_mode_t val) +{ + st1vafe6ax_emb_func_en_b_t emb_func_en_b; + st1vafe6ax_fsm_enable_t fsm_enable; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + } + if ((val.fsm1_en | val.fsm2_en | val.fsm1_en | val.fsm1_en + | val.fsm1_en | val.fsm2_en | val.fsm1_en | val.fsm1_en) == PROPERTY_ENABLE) + { + emb_func_en_b.fsm_en = PROPERTY_ENABLE; + } + else + { + emb_func_en_b.fsm_en = PROPERTY_DISABLE; + } + if (ret == 0) + { + fsm_enable.fsm1_en = val.fsm1_en; + fsm_enable.fsm2_en = val.fsm2_en; + fsm_enable.fsm3_en = val.fsm3_en; + fsm_enable.fsm4_en = val.fsm4_en; + fsm_enable.fsm5_en = val.fsm5_en; + fsm_enable.fsm6_en = val.fsm6_en; + fsm_enable.fsm7_en = val.fsm7_en; + fsm_enable.fsm8_en = val.fsm8_en; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + } + if (ret == 0) + { + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Enable Finite State Machine (FSM) feature.[get] + * + * @param ctx read / write interface definitions + * @param val Enable Finite State Machine (FSM) feature. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fsm_mode_get(const stmdev_ctx_t *ctx, st1vafe6ax_fsm_mode_t *val) +{ + st1vafe6ax_fsm_enable_t fsm_enable; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FSM_ENABLE, (uint8_t *)&fsm_enable, 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + val->fsm1_en = fsm_enable.fsm1_en; + val->fsm2_en = fsm_enable.fsm2_en; + val->fsm3_en = fsm_enable.fsm3_en; + val->fsm4_en = fsm_enable.fsm4_en; + val->fsm5_en = fsm_enable.fsm5_en; + val->fsm6_en = fsm_enable.fsm6_en; + val->fsm7_en = fsm_enable.fsm7_en; + val->fsm8_en = fsm_enable.fsm8_en; + + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[set] + * + * @param ctx read / write interface definitions + * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FSM_LONG_COUNTER_L, (uint8_t *)&buff[0], 2); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[get] + * + * @param ctx read / write interface definitions + * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format). + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FSM_LONG_COUNTER_L, &buff[0], 2); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief FSM output registers[get] + * + * @param ctx read / write interface definitions + * @param val FSM output registers + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fsm_out_get(const stmdev_ctx_t *ctx, st1vafe6ax_fsm_out_t *val) +{ + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FSM_OUTS1, (uint8_t *)val, 8); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Finite State Machine Output Data Rate (ODR) configuration.[set] + * + * @param ctx read / write interface definitions + * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fsm_data_rate_set(const stmdev_ctx_t *ctx, + st1vafe6ax_fsm_data_rate_t val) +{ + st1vafe6ax_fsm_odr_t fsm_odr; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FSM_ODR, (uint8_t *)&fsm_odr, 1); + } + + if (ret == 0) + { + fsm_odr.fsm_odr = (uint8_t)val & 0x07U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_FSM_ODR, (uint8_t *)&fsm_odr, 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Finite State Machine Output Data Rate (ODR) configuration.[get] + * + * @param ctx read / write interface definitions + * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fsm_data_rate_get(const stmdev_ctx_t *ctx, + st1vafe6ax_fsm_data_rate_t *val) +{ + st1vafe6ax_fsm_odr_t fsm_odr; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_FSM_ODR, (uint8_t *)&fsm_odr, 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + switch (fsm_odr.fsm_odr) + { + case ST1VAFE6AX_FSM_15Hz: + *val = ST1VAFE6AX_FSM_15Hz; + break; + + case ST1VAFE6AX_FSM_30Hz: + *val = ST1VAFE6AX_FSM_30Hz; + break; + + case ST1VAFE6AX_FSM_60Hz: + *val = ST1VAFE6AX_FSM_60Hz; + break; + + case ST1VAFE6AX_FSM_120Hz: + *val = ST1VAFE6AX_FSM_120Hz; + break; + + case ST1VAFE6AX_FSM_240Hz: + *val = ST1VAFE6AX_FSM_240Hz; + break; + + case ST1VAFE6AX_FSM_480Hz: + *val = ST1VAFE6AX_FSM_480Hz; + break; + + case ST1VAFE6AX_FSM_960Hz: + *val = ST1VAFE6AX_FSM_960Hz; + break; + + default: + *val = ST1VAFE6AX_FSM_15Hz; + break; + } + return ret; +} + +/** + * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[set] + * + * @param ctx read / write interface definitions + * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fsm_long_cnt_timeout_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = st1vafe6ax_ln_pg_write(ctx, ST1VAFE6AX_FSM_LC_TIMEOUT_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[get] + * + * @param ctx read / write interface definitions + * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = st1vafe6ax_ln_pg_read(ctx, ST1VAFE6AX_FSM_LC_TIMEOUT_L, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @brief FSM number of programs.[set] + * + * @param ctx read / write interface definitions + * @param val FSM number of programs. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + st1vafe6ax_fsm_programs_t fsm_programs; + int32_t ret; + + ret = st1vafe6ax_ln_pg_read(ctx, ST1VAFE6AX_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + if (ret == 0) + { + fsm_programs.fsm_n_prog = val; + ret = st1vafe6ax_ln_pg_write(ctx, ST1VAFE6AX_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + } + + return ret; +} + +/** + * @brief FSM number of programs.[get] + * + * @param ctx read / write interface definitions + * @param val FSM number of programs. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + st1vafe6ax_fsm_programs_t fsm_programs; + int32_t ret; + + ret = st1vafe6ax_ln_pg_read(ctx, ST1VAFE6AX_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1); + *val = fsm_programs.fsm_n_prog; + + + return ret; +} + +/** + * @brief FSM start address. First available address is 0x35C.[set] + * + * @param ctx read / write interface definitions + * @param val FSM start address. First available address is 0x35C. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = st1vafe6ax_ln_pg_write(ctx, ST1VAFE6AX_FSM_START_ADD_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief FSM start address. First available address is 0x35C.[get] + * + * @param ctx read / write interface definitions + * @param val FSM start address. First available address is 0x35C. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = st1vafe6ax_ln_pg_read(ctx, ST1VAFE6AX_FSM_START_ADD_L, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @addtogroup Machine Learning Core + * @brief This section group all the functions concerning the + * usage of Machine Learning Core + * @{ + * + */ + +/** + * @brief It enables Machine Learning Core feature (MLC). When the Machine Learning Core is enabled the Finite State Machine (FSM) programs are executed before executing the MLC algorithms.[set] + * + * @param ctx read / write interface definitions + * @param val MLC_OFF, MLC_ON, MLC_BEFORE_FSM, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_mlc_set(const stmdev_ctx_t *ctx, st1vafe6ax_mlc_mode_t val) +{ + st1vafe6ax_emb_func_en_b_t emb_en_b; + st1vafe6ax_emb_func_en_a_t emb_en_a; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + + switch (val) + { + case ST1VAFE6AX_MLC_OFF: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 0; + break; + case ST1VAFE6AX_MLC_ON: + emb_en_a.mlc_before_fsm_en = 0; + emb_en_b.mlc_en = 1; + break; + case ST1VAFE6AX_MLC_ON_BEFORE_FSM: + emb_en_a.mlc_before_fsm_en = 1; + emb_en_b.mlc_en = 0; + break; + default: + break; + } + + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += st1vafe6ax_write_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief It enables Machine Learning Core feature (MLC). When the Machine Learning Core is enabled the Finite State Machine (FSM) programs are executed before executing the MLC algorithms.[get] + * + * @param ctx read / write interface definitions + * @param val MLC_OFF, MLC_ON, MLC_BEFORE_FSM, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_mlc_get(const stmdev_ctx_t *ctx, st1vafe6ax_mlc_mode_t *val) +{ + st1vafe6ax_emb_func_en_b_t emb_en_b; + st1vafe6ax_emb_func_en_a_t emb_en_a; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1); + ret += st1vafe6ax_read_reg(ctx, ST1VAFE6AX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1); + + if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U) + { + *val = ST1VAFE6AX_MLC_OFF; + } + else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U) + { + *val = ST1VAFE6AX_MLC_ON; + } + else if (emb_en_a.mlc_before_fsm_en == 1U) + { + *val = ST1VAFE6AX_MLC_ON_BEFORE_FSM; + } + else + { + /* Do nothing */ + } + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Machine Learning Core Output Data Rate (ODR) configuration.[set] + * + * @param ctx read / write interface definitions + * @param val MLC_15Hz, MLC_30Hz, MLC_60Hz, MLC_120Hz, MLC_240Hz, MLC_480Hz, MLC_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_mlc_data_rate_set(const stmdev_ctx_t *ctx, + st1vafe6ax_mlc_data_rate_t val) +{ + st1vafe6ax_mlc_odr_t mlc_odr; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MLC_ODR, (uint8_t *)&mlc_odr, 1); + } + + if (ret == 0) + { + mlc_odr.mlc_odr = (uint8_t)val & 0x07U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_MLC_ODR, (uint8_t *)&mlc_odr, 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + return ret; +} + +/** + * @brief Machine Learning Core Output Data Rate (ODR) configuration.[get] + * + * @param ctx read / write interface definitions + * @param val MLC_15Hz, MLC_30Hz, MLC_60Hz, MLC_120Hz, MLC_240Hz, MLC_480Hz, MLC_960Hz, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_mlc_data_rate_get(const stmdev_ctx_t *ctx, + st1vafe6ax_mlc_data_rate_t *val) +{ + st1vafe6ax_mlc_odr_t mlc_odr; + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MLC_ODR, (uint8_t *)&mlc_odr, 1); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + + switch (mlc_odr.mlc_odr) + { + case ST1VAFE6AX_MLC_15Hz: + *val = ST1VAFE6AX_MLC_15Hz; + break; + + case ST1VAFE6AX_MLC_30Hz: + *val = ST1VAFE6AX_MLC_30Hz; + break; + + case ST1VAFE6AX_MLC_60Hz: + *val = ST1VAFE6AX_MLC_60Hz; + break; + + case ST1VAFE6AX_MLC_120Hz: + *val = ST1VAFE6AX_MLC_120Hz; + break; + + case ST1VAFE6AX_MLC_240Hz: + *val = ST1VAFE6AX_MLC_240Hz; + break; + + case ST1VAFE6AX_MLC_480Hz: + *val = ST1VAFE6AX_MLC_480Hz; + break; + + case ST1VAFE6AX_MLC_960Hz: + *val = ST1VAFE6AX_MLC_960Hz; + break; + + default: + *val = ST1VAFE6AX_MLC_15Hz; + break; + } + return ret; +} + +/** + * @brief Output value of all MLC decision trees.[get] + * + * @param ctx read / write interface definitions + * @param val Output value of all MLC decision trees. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_mlc_out_get(const stmdev_ctx_t *ctx, st1vafe6ax_mlc_out_t *val) +{ + int32_t ret; + + ret = st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_EMBED_FUNC_MEM_BANK); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_MLC1_SRC, (uint8_t *)&val, 4); + } + + ret += st1vafe6ax_mem_bank_set(ctx, ST1VAFE6AX_MAIN_MEM_BANK); + return ret; +} + +/** + * @brief Bio sensor sensitivity value register for the Machine Learning Core. + * This register corresponds to the conversion value of the Bio sensor. + * The register value is expressed as half-precision floating-point format: + * SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set] + * + * @param ctx read / write interface definitions + * @param val Bio sensor sensitivity value register for the Machine Learning Core. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_mlc_bio_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = st1vafe6ax_ln_pg_write(ctx, ST1VAFE6AX_MLC_BIO_SENSITIVITY_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief Bio sensor sensitivity value register for the Machine Learning Core. + * This register corresponds to the conversion value of the Bio sensor. + * The register value is expressed as half-precision floating-point format: + * SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get] + * + * @param ctx read / write interface definitions + * @param val Bio sensor sensitivity value register for the Machine Learning Core. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_mlc_bio_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = st1vafe6ax_ln_pg_read(ctx, ST1VAFE6AX_MLC_BIO_SENSITIVITY_L, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @addtogroup Accelerometer user offset correction + * @brief This section group all the functions concerning the + * usage of Accelerometer user offset correction + * @{ + * + */ + +/** + * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[set] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_xl_offset_on_out_set(const stmdev_ctx_t *ctx, uint8_t val) +{ + st1vafe6ax_ctrl9_t ctrl9; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ctrl9.usr_off_on_out = val; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + } + + return ret; +} + +/** + * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[get] + * + * @param ctx read / write interface definitions + * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val) +{ + st1vafe6ax_ctrl9_t ctrl9; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + *val = ctrl9.usr_off_on_out; + + return ret; +} + +/** + * @brief Accelerometer user offset correction values in mg.[set] + * + * @param ctx read / write interface definitions + * @param val Accelerometer user offset correction values in mg. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_xl_offset_mg_set(const stmdev_ctx_t *ctx, + st1vafe6ax_xl_offset_mg_t val) +{ + st1vafe6ax_z_ofs_usr_t z_ofs_usr; + st1vafe6ax_y_ofs_usr_t y_ofs_usr; + st1vafe6ax_x_ofs_usr_t x_ofs_usr; + st1vafe6ax_ctrl9_t ctrl9; + int32_t ret; + float_t tmp; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + } + + + if ((val.x_mg < (0.0078125f * 127.0f)) && (val.x_mg > (0.0078125f * -127.0f)) && + (val.y_mg < (0.0078125f * 127.0f)) && (val.y_mg > (0.0078125f * -127.0f)) && + (val.z_mg < (0.0078125f * 127.0f)) && (val.z_mg > (0.0078125f * -127.0f))) + { + ctrl9.usr_off_w = 0; + + tmp = val.z_mg / 0.0078125f; + z_ofs_usr.z_ofs_usr = (uint8_t)tmp; + + tmp = val.y_mg / 0.0078125f; + y_ofs_usr.y_ofs_usr = (uint8_t)tmp; + + tmp = val.x_mg / 0.0078125f; + x_ofs_usr.x_ofs_usr = (uint8_t)tmp; + } + else if ((val.x_mg < (0.125f * 127.0f)) && (val.x_mg > (0.125f * -127.0f)) && + (val.y_mg < (0.125f * 127.0f)) && (val.y_mg > (0.125f * -127.0f)) && + (val.z_mg < (0.125f * 127.0f)) && (val.z_mg > (0.125f * -127.0f))) + { + ctrl9.usr_off_w = 1; + + tmp = val.z_mg / 0.125f; + z_ofs_usr.z_ofs_usr = (uint8_t)tmp; + + tmp = val.y_mg / 0.125f; + y_ofs_usr.y_ofs_usr = (uint8_t)tmp; + + tmp = val.x_mg / 0.125f; + x_ofs_usr.x_ofs_usr = (uint8_t)tmp; + } + else // out of limit + { + ctrl9.usr_off_w = 1; + z_ofs_usr.z_ofs_usr = 0xFFU; + y_ofs_usr.y_ofs_usr = 0xFFU; + x_ofs_usr.x_ofs_usr = 0xFFU; + } + + if (ret == 0) + { + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + } + if (ret == 0) + { + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + } + if (ret == 0) + { + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + } + if (ret == 0) + { + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + } + return ret; +} + +/** + * @brief Accelerometer user offset correction values in mg.[get] + * + * @param ctx read / write interface definitions + * @param val Accelerometer user offset correction values in mg. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_xl_offset_mg_get(const stmdev_ctx_t *ctx, + st1vafe6ax_xl_offset_mg_t *val) +{ + st1vafe6ax_z_ofs_usr_t z_ofs_usr; + st1vafe6ax_y_ofs_usr_t y_ofs_usr; + st1vafe6ax_x_ofs_usr_t x_ofs_usr; + st1vafe6ax_ctrl9_t ctrl9; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL9, (uint8_t *)&ctrl9, 1); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1); + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1); + } + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1); + } + + if (ctrl9.usr_off_w == PROPERTY_DISABLE) + { + val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.0078125f); + val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.0078125f); + val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.0078125f); + } + else + { + val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.125f); + val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.125f); + val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.125f); + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @addtogroup AH_BIO + * @brief This section group all the functions concerning the + * usage of AH_BIO + * @{ + * + */ + +/** + * @brief Enables AH_BIO chain. When this bit is set to ‘1’, the AH_BIO buffers are + * connected to the AH1/Bio1 and AH1/Bio2 pins. Before setting this bit to 1, + * the accelerometer and gyroscope sensor have to be configured in power-down mode.[set] + * + * @param ctx read / write interface definitions + * @param val 1: Enables AH_BIO chain, 0: Disable the AH_BIO chain + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_ah_bio_mode_set(const stmdev_ctx_t *ctx, + st1vafe6ax_ah_bio_mode_t val) +{ + st1vafe6ax_ctrl10_t ctrl10; + st1vafe6ax_ctrl7_t ctrl7; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL10, (uint8_t *)&ctrl10, 1); + } + + if (ret == 0) + { + if ((val.ah_bio1_en | val.ah_bio2_en) == PROPERTY_ENABLE) + { + ctrl7.ah_bio_en = PROPERTY_ENABLE; + } + else + { + ctrl7.ah_bio_en = PROPERTY_DISABLE; + } + ctrl7.ah_bio1_en = val.ah_bio1_en; + ctrl7.ah_bio2_en = val.ah_bio2_en; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL7, (uint8_t *)&ctrl7, 1); + } + if (ret == 0) + { + ctrl10.ah_bio_sw = val.swaps; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL10, (uint8_t *)&ctrl10, 1); + } + return ret; +} + +/** + * @brief Enables AH_BIO chain. When this bit is set to ‘1’, the AH_BIO buffers are + * connected to the AH1/Bio1 and AH1/Bio2 pins. Before setting this bit to 1, + * the accelerometer and gyroscope sensor have to be configured in power-down mode.[get] + * + * @param ctx read / write interface definitions + * @param val 1: Enables AH_BIO chain, 0: Disable the AH_BIO chain + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_ah_bio_mode_get(const stmdev_ctx_t *ctx, + st1vafe6ax_ah_bio_mode_t *val) +{ + st1vafe6ax_ctrl10_t ctrl10; + st1vafe6ax_ctrl7_t ctrl7; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret == 0) + { + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL10, (uint8_t *)&ctrl10, 1); + } + + val->ah_bio1_en = ctrl7.ah_bio1_en; + val->ah_bio2_en = ctrl7.ah_bio2_en; + val->swaps = ctrl10.ah_bio_sw; + + return ret; +} + +/** + * @brief Configures the equivalent input impedance of the AH_BIO buffers.[set] + * + * @param ctx read / write interface definitions + * @param val 2400MOhm, 730MOhm, 300MOhm, 255MOhm, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_ah_bio_zin_set(const stmdev_ctx_t *ctx, + st1vafe6ax_ah_bio_zin_t val) +{ + st1vafe6ax_ctrl7_t ctrl7; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL7, (uint8_t *)&ctrl7, 1); + if (ret == 0) + { + ctrl7.ah_bio_c_zin = (uint8_t)val & 0x03U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_CTRL7, (uint8_t *)&ctrl7, 1); + } + + return ret; +} + +/** + * @brief Configures the equivalent input impedance of the AH_BIO buffers.[get] + * + * @param ctx read / write interface definitions + * @param val 2400MOhm, 730MOhm, 300MOhm, 255MOhm, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_ah_bio_zin_get(const stmdev_ctx_t *ctx, + st1vafe6ax_ah_bio_zin_t *val) +{ + st1vafe6ax_ctrl7_t ctrl7; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_CTRL7, (uint8_t *)&ctrl7, 1); + switch (ctrl7.ah_bio_c_zin) + { + case ST1VAFE6AX_2400MOhm: + *val = ST1VAFE6AX_2400MOhm; + break; + + case ST1VAFE6AX_730MOhm: + *val = ST1VAFE6AX_730MOhm; + break; + + case ST1VAFE6AX_300MOhm: + *val = ST1VAFE6AX_300MOhm; + break; + + case ST1VAFE6AX_255MOhm: + *val = ST1VAFE6AX_255MOhm; + break; + + default: + *val = ST1VAFE6AX_2400MOhm; + break; + } + return ret; +} + +/** + * @brief Bio sensor sensitivity value register for the Finite State Machine. + * This register corresponds to the conversion value of the Bio sensor. + * The register value is expressed as half-precision floating-point format: + * SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set] + * + * @param ctx read / write interface definitions + * @param val Bio sensor sensitivity value register for the Finite State Machine. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fsm_bio_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val) +{ + uint8_t buff[2]; + int32_t ret; + + buff[1] = (uint8_t)(val / 256U); + buff[0] = (uint8_t)(val - (buff[1] * 256U)); + ret = st1vafe6ax_ln_pg_write(ctx, ST1VAFE6AX_FSM_BIO_SENSITIVITY_L, (uint8_t *)&buff[0], 2); + + return ret; +} + +/** + * @brief Bio sensor sensitivity value register for the Finite State Machine. + * This register corresponds to the conversion value of the Bio sensor. + * The register value is expressed as half-precision floating-point format: + * SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get] + * + * @param ctx read / write interface definitions + * @param val Bio sensor sensitivity value register for the Finite State Machine. + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_fsm_bio_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val) +{ + uint8_t buff[2]; + int32_t ret; + + ret = st1vafe6ax_ln_pg_read(ctx, ST1VAFE6AX_FSM_BIO_SENSITIVITY_L, &buff[0], 2); + *val = buff[1]; + *val = (*val * 256U) + buff[0]; + + return ret; +} + +/** + * @} + * + */ + +/** + * @addtogroup SenseWire (I3C) + * @brief This section group all the functions concerning the + * usage of SenseWire (I3C) + * @{ + * + */ + +/** + * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[set] + * + * @param ctx read / write interface definitions + * @param val SW_RST_DYN_ADDRESS_RST, GLOBAL_RST_, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_i3c_reset_mode_set(const stmdev_ctx_t *ctx, + st1vafe6ax_i3c_reset_mode_t val) +{ + st1vafe6ax_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + if (ret == 0) + { + pin_ctrl.ibhr_por_en = (uint8_t)val & 0x01U; + ret = st1vafe6ax_write_reg(ctx, ST1VAFE6AX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + } + + return ret; +} + +/** + * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[get] + * + * @param ctx read / write interface definitions + * @param val SW_RST_DYN_ADDRESS_RST, GLOBAL_RST_, + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t st1vafe6ax_i3c_reset_mode_get(const stmdev_ctx_t *ctx, + st1vafe6ax_i3c_reset_mode_t *val) +{ + st1vafe6ax_pin_ctrl_t pin_ctrl; + int32_t ret; + + ret = st1vafe6ax_read_reg(ctx, ST1VAFE6AX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1); + switch (pin_ctrl.ibhr_por_en) + { + case ST1VAFE6AX_SW_RST_DYN_ADDRESS_RST: + *val = ST1VAFE6AX_SW_RST_DYN_ADDRESS_RST; + break; + + case ST1VAFE6AX_I3C_GLOBAL_RST: + *val = ST1VAFE6AX_I3C_GLOBAL_RST; + break; + + default: + *val = ST1VAFE6AX_SW_RST_DYN_ADDRESS_RST; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @} + * + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/st1vafe6ax_STdC/driver/st1vafe6ax_reg.h b/sensor/stmemsc/st1vafe6ax_STdC/driver/st1vafe6ax_reg.h new file mode 100644 index 00000000..270d3e7a --- /dev/null +++ b/sensor/stmemsc/st1vafe6ax_STdC/driver/st1vafe6ax_reg.h @@ -0,0 +1,3609 @@ +/** + ****************************************************************************** + * @file st1vafe6ax_reg.h + * @author Sensors Software Solution Team + * @brief This file contains all the functions prototypes for the + * st1vafe6ax_reg.c driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2024 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef ST1VAFE6AX_REGS_H +#define ST1VAFE6AX_REGS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include + +/** @addtogroup ST1VAFE6AX + * @{ + * + */ + +/** @defgroup Endianness definitions + * @{ + * + */ + +#ifndef DRV_BYTE_ORDER +#ifndef __BYTE_ORDER__ + +#define DRV_LITTLE_ENDIAN 1234 +#define DRV_BIG_ENDIAN 4321 + +/** if _BYTE_ORDER is not defined, choose the endianness of your architecture + * by uncommenting the define which fits your platform endianness + */ +//#define DRV_BYTE_ORDER DRV_BIG_ENDIAN +#define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN + +#else /* defined __BYTE_ORDER__ */ + +#define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ +#define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ +#define DRV_BYTE_ORDER __BYTE_ORDER__ + +#endif /* __BYTE_ORDER__*/ +#endif /* DRV_BYTE_ORDER */ + +/** + * @} + * + */ + +/** @defgroup STMicroelectronics sensors common types + * @{ + * + */ + +#ifndef MEMS_SHARED_TYPES +#define MEMS_SHARED_TYPES + +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bit7 : 1; + uint8_t bit6 : 1; + uint8_t bit5 : 1; + uint8_t bit4 : 1; + uint8_t bit3 : 1; + uint8_t bit2 : 1; + uint8_t bit1 : 1; + uint8_t bit0 : 1; +#endif /* DRV_BYTE_ORDER */ +} bitwise_t; + +#define PROPERTY_DISABLE (0U) +#define PROPERTY_ENABLE (1U) + +/** @addtogroup Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); +typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); +typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); + +typedef struct +{ + /** Component mandatory fields **/ + stmdev_write_ptr write_reg; + stmdev_read_ptr read_reg; + /** Component optional fields **/ + stmdev_mdelay_ptr mdelay; + /** Customizable optional pointer **/ + void *handle; +} stmdev_ctx_t; + +/** + * @} + * + */ + +#endif /* MEMS_SHARED_TYPES */ + +#ifndef MEMS_UCF_SHARED_TYPES +#define MEMS_UCF_SHARED_TYPES + +/** @defgroup Generic address-data structure definition + * @brief This structure is useful to load a predefined configuration + * of a sensor. + * You can create a sensor configuration by your own or using + * Unico / Unicleo tools available on STMicroelectronics + * web site. + * + * @{ + * + */ + +typedef struct +{ + uint8_t address; + uint8_t data; +} ucf_line_t; + +/** + * @} + * + */ + +#endif /* MEMS_UCF_SHARED_TYPES */ + +/** + * @} + * + */ + +/** @defgroup ST1VAFE6AX_Infos + * @{ + * + */ + +/** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ +#define ST1VAFE6AX_I2C_ADD_L 0xD5U +#define ST1VAFE6AX_I2C_ADD_H 0xD7U + +/** Device Identification (Who am I) **/ +#define ST1VAFE6AX_ID 0x71U + +/** + * @} + * + */ + +/** @defgroup bitfields page main + * @{ + * + */ + +#define ST1VAFE6AX_FUNC_CFG_ACCESS 0x1U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t sw_por : 1; + uint8_t fsm_wr_ctrl_en : 1; + uint8_t not_used1 : 3; + uint8_t emb_func_reg_access : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_reg_access : 1; + uint8_t not_used1 : 3; + uint8_t fsm_wr_ctrl_en : 1; + uint8_t sw_por : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_func_cfg_access_t; + +#define ST1VAFE6AX_PIN_CTRL 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 5; + uint8_t ibhr_por_en : 1; + uint8_t sdo_pu_en : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t sdo_pu_en : 1; + uint8_t ibhr_por_en : 1; + uint8_t not_used0 : 5; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_pin_ctrl_t; + +#define ST1VAFE6AX_IF_CFG 0x3U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t i2c_i3c_disable : 1; + uint8_t not_used0 : 1; + uint8_t sim : 1; + uint8_t pp_od : 1; + uint8_t h_lactive : 1; + uint8_t asf_ctrl : 1; + uint8_t not_used1 : 1; + uint8_t sda_pu_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sda_pu_en : 1; + uint8_t not_used1 : 1; + uint8_t asf_ctrl : 1; + uint8_t h_lactive : 1; + uint8_t pp_od : 1; + uint8_t sim : 1; + uint8_t not_used0 : 1; + uint8_t i2c_i3c_disable : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_if_cfg_t; + +#define ST1VAFE6AX_FIFO_CTRL1 0x7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wtm : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t wtm : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fifo_ctrl1_t; + +#define ST1VAFE6AX_FIFO_CTRL2 0x8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xl_dualc_batch_from_fsm : 1; + uint8_t uncompr_rate : 2; + uint8_t not_used0 : 1; + uint8_t odr_chg_en : 1; + uint8_t not_used1 : 1; + uint8_t fifo_compr_rt_en : 1; + uint8_t stop_on_wtm : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t stop_on_wtm : 1; + uint8_t fifo_compr_rt_en : 1; + uint8_t not_used1 : 1; + uint8_t odr_chg_en : 1; + uint8_t not_used0 : 1; + uint8_t uncompr_rate : 2; + uint8_t xl_dualc_batch_from_fsm : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fifo_ctrl2_t; + +#define ST1VAFE6AX_FIFO_CTRL3 0x9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t bdr_xl : 4; + uint8_t bdr_gy : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t bdr_gy : 4; + uint8_t bdr_xl : 4; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fifo_ctrl3_t; + +#define ST1VAFE6AX_FIFO_CTRL4 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_mode : 3; + uint8_t not_used0 : 1; + uint8_t odr_t_batch : 2; + uint8_t dec_ts_batch : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dec_ts_batch : 2; + uint8_t odr_t_batch : 2; + uint8_t not_used0 : 1; + uint8_t fifo_mode : 3; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fifo_ctrl4_t; + +#define ST1VAFE6AX_COUNTER_BDR_REG1 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t cnt_bdr_th : 2; + uint8_t ah_bio_batch_en : 1; + uint8_t not_used0 : 2; + uint8_t trig_counter_bdr : 2; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t trig_counter_bdr : 2; + uint8_t not_used0 : 2; + uint8_t ah_bio_batch_en : 1; + uint8_t cnt_bdr_th : 2; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_counter_bdr_reg1_t; + +#define ST1VAFE6AX_COUNTER_BDR_REG2 0x0CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t cnt_bdr_th : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t cnt_bdr_th : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_counter_bdr_reg2_t; + +#define ST1VAFE6AX_INT1_CTRL 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_drdy_xl : 1; + uint8_t int1_drdy_g : 1; + uint8_t not_used0 : 1; + uint8_t int1_fifo_th : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_fifo_full : 1; + uint8_t int1_cnt_bdr : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t int1_cnt_bdr : 1; + uint8_t int1_fifo_full : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_fifo_th : 1; + uint8_t not_used0 : 1; + uint8_t int1_drdy_g : 1; + uint8_t int1_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_int1_ctrl_t; + +#define ST1VAFE6AX_INT2_CTRL 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_drdy_xl : 1; + uint8_t int2_drdy_g : 1; + uint8_t not_used0 : 1; + uint8_t int2_fifo_th : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_fifo_full : 1; + uint8_t int2_cnt_bdr : 1; + uint8_t int2_emb_func_endop : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_emb_func_endop : 1; + uint8_t int2_cnt_bdr : 1; + uint8_t int2_fifo_full : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_fifo_th : 1; + uint8_t not_used0 : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_xl : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_int2_ctrl_t; + +#define ST1VAFE6AX_WHO_AM_I 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t id : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t id : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_who_am_i_t; + +#define ST1VAFE6AX_CTRL1 0x10U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t odr_xl : 4; + uint8_t op_mode_xl : 3; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t op_mode_xl : 3; + uint8_t odr_xl : 4; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_ctrl1_t; + +#define ST1VAFE6AX_CTRL2 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t odr_g : 4; + uint8_t op_mode_g : 3; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t op_mode_g : 3; + uint8_t odr_g : 4; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_ctrl2_t; + +#define ST1VAFE6AX_CTRL3 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sw_reset : 1; + uint8_t not_used0 : 1; + uint8_t if_inc : 1; + uint8_t not_used1 : 3; + uint8_t bdu : 1; + uint8_t boot : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t boot : 1; + uint8_t bdu : 1; + uint8_t not_used1 : 3; + uint8_t if_inc : 1; + uint8_t not_used0 : 1; + uint8_t sw_reset : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_ctrl3_t; + +#define ST1VAFE6AX_CTRL4 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used1 : 1; + uint8_t drdy_pulsed : 1; + uint8_t int2_drdy_temp : 1; + uint8_t drdy_mask : 1; + uint8_t int2_on_int1 : 1; + uint8_t not_used0 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 3; + uint8_t int2_on_int1 : 1; + uint8_t drdy_mask : 1; + uint8_t int2_drdy_temp : 1; + uint8_t drdy_pulsed : 1; + uint8_t not_used1 : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_ctrl4_t; + +#define ST1VAFE6AX_CTRL5 0x14U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int_en_i3c : 1; + uint8_t bus_act_sel : 2; + uint8_t not_used0 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 5; + uint8_t bus_act_sel : 2; + uint8_t int_en_i3c : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_ctrl5_t; + +#define ST1VAFE6AX_CTRL6 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_g : 4; + uint8_t lpf1_g_bw : 3; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t lpf1_g_bw : 3; + uint8_t fs_g : 4; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_ctrl6_t; + +#define ST1VAFE6AX_CTRL7 0x16U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t lpf1_g_en : 1; + uint8_t not_used0 : 1; + uint8_t ah_bio2_en : 1; + uint8_t ah_bio1_en : 1; + uint8_t ah_bio_c_zin : 2; + uint8_t int2_drdy_ah_bio : 1; + uint8_t ah_bio_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ah_bio_en : 1; + uint8_t int2_drdy_ah_bio : 1; + uint8_t ah_bio_c_zin : 2; + uint8_t ah_bio1_en : 1; + uint8_t ah_bio2_en : 1; + uint8_t not_used0 : 1; + uint8_t lpf1_g_en : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_ctrl7_t; + +#define ST1VAFE6AX_CTRL8 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fs_xl : 2; + uint8_t not_used0 : 1; + uint8_t xl_dualc_en : 1; + uint8_t ah_bio_hpf : 1; + uint8_t hp_lpf2_xl_bw : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t hp_lpf2_xl_bw : 3; + uint8_t ah_bio_hpf : 1; + uint8_t xl_dualc_en : 1; + uint8_t not_used0 : 1; + uint8_t fs_xl : 2; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_ctrl8_t; + +#define ST1VAFE6AX_CTRL9 0x18U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t usr_off_on_out : 1; + uint8_t usr_off_w : 1; + uint8_t not_used0 : 1; + uint8_t lpf2_xl_en : 1; + uint8_t hp_slope_xl_en : 1; + uint8_t xl_fastsettl_mode : 1; + uint8_t hp_ref_mode_xl : 1; + uint8_t ah_bio_lpf : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ah_bio_lpf : 1; + uint8_t hp_ref_mode_xl : 1; + uint8_t xl_fastsettl_mode : 1; + uint8_t hp_slope_xl_en : 1; + uint8_t lpf2_xl_en : 1; + uint8_t not_used0 : 1; + uint8_t usr_off_w : 1; + uint8_t usr_off_on_out : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_ctrl9_t; + +#define ST1VAFE6AX_CTRL10 0x19U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t st_xl : 2; + uint8_t st_g : 2; + uint8_t xl_st_offset : 1; + uint8_t ah_bio_sw : 1; + uint8_t emb_func_debug : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t emb_func_debug : 1; + uint8_t ah_bio_sw : 1; + uint8_t xl_st_offset : 1; + uint8_t st_g : 2; + uint8_t st_xl : 2; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_ctrl10_t; + +#define ST1VAFE6AX_CTRL_STATUS 0x1AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t fsm_wr_ctrl_status : 1; + uint8_t not_used1 : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 5; + uint8_t fsm_wr_ctrl_status : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_ctrl_status_t; + +#define ST1VAFE6AX_FIFO_STATUS1 0x1BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t diff_fifo : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t diff_fifo : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fifo_status1_t; + +#define ST1VAFE6AX_FIFO_STATUS2 0x1CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t diff_fifo : 1; + uint8_t not_used0 : 2; + uint8_t fifo_ovr_latched : 1; + uint8_t counter_bdr_ia : 1; + uint8_t fifo_full_ia : 1; + uint8_t fifo_ovr_ia : 1; + uint8_t fifo_wtm_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_wtm_ia : 1; + uint8_t fifo_ovr_ia : 1; + uint8_t fifo_full_ia : 1; + uint8_t counter_bdr_ia : 1; + uint8_t fifo_ovr_latched : 1; + uint8_t not_used0 : 2; + uint8_t diff_fifo : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fifo_status2_t; + +#define ST1VAFE6AX_ALL_INT_SRC 0x1DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ia : 1; + uint8_t wu_ia : 1; + uint8_t tap_ia : 1; + uint8_t not_used0 : 1; + uint8_t d6d_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t not_used1 : 1; + uint8_t emb_func_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_ia : 1; + uint8_t not_used1 : 1; + uint8_t sleep_change_ia : 1; + uint8_t d6d_ia : 1; + uint8_t not_used0 : 1; + uint8_t tap_ia : 1; + uint8_t wu_ia : 1; + uint8_t ff_ia : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_all_int_src_t; + +#define ST1VAFE6AX_STATUS_REG 0x1EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t xlda : 1; + uint8_t gda : 1; + uint8_t tda : 1; + uint8_t ah_bioda : 1; + uint8_t not_used0 : 3; + uint8_t timestamp_endcount : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp_endcount : 1; + uint8_t not_used0 : 3; + uint8_t ah_bioda : 1; + uint8_t tda : 1; + uint8_t gda : 1; + uint8_t xlda : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_status_reg_t; + +#define ST1VAFE6AX_OUT_TEMP_L 0x20U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_out_temp_l_t; + +#define ST1VAFE6AX_OUT_TEMP_H 0x21U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t temp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t temp : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_out_temp_h_t; + +#define ST1VAFE6AX_OUTX_L_G 0x22U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_g : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_outx_l_g_t; + +#define ST1VAFE6AX_OUTX_H_G 0x23U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_g : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_outx_h_g_t; + +#define ST1VAFE6AX_OUTY_L_G 0x24U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_g : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_outy_l_g_t; + +#define ST1VAFE6AX_OUTY_H_G 0x25U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_g : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_outy_h_g_t; + +#define ST1VAFE6AX_OUTZ_L_G 0x26U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_g : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_outz_l_g_t; + +#define ST1VAFE6AX_OUTZ_H_G 0x27U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_g : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_g : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_outz_h_g_t; + +#define ST1VAFE6AX_OUTZ_L_A 0x28U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_a : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_outz_l_a_t; + +#define ST1VAFE6AX_OUTZ_H_A 0x29U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outz_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outz_a : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_outz_h_a_t; + +#define ST1VAFE6AX_OUTY_L_A 0x2AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_a : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_outy_l_a_t; + +#define ST1VAFE6AX_OUTY_H_A 0x2BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outy_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outy_a : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_outy_h_a_t; + +#define ST1VAFE6AX_OUTX_L_A 0x2CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_a : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_outx_l_a_t; + +#define ST1VAFE6AX_OUTX_H_A 0x2DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t outx_a : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t outx_a : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_outx_h_a_t; + +#define ST1VAFE6AX_UI_OUTZ_L_A_DUALC 0x34U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outz_a_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outz_a_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_ui_outz_l_a_dualc_t; + +#define ST1VAFE6AX_UI_OUTZ_H_A_DUALC 0x35U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outz_a_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outz_a_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_ui_outz_h_a_dualc_t; + +#define ST1VAFE6AX_UI_OUTY_L_A_DUALC 0x36U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outy_a_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outy_a_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_ui_outy_l_a_dualc_t; + +#define ST1VAFE6AX_UI_OUTY_H_A_DUALC 0x37U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outy_a_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outy_a_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_ui_outy_h_a_dualc_t; + +#define ST1VAFE6AX_UI_OUTX_L_A_DUALC 0x38U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outx_a_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outx_a_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_ui_outx_l_a_dualc_t; + +#define ST1VAFE6AX_UI_OUTX_H_A_DUALC 0x39U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ui_outx_a_dualc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ui_outx_a_dualc : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_ui_outx_h_a_dualc_t; + +#define ST1VAFE6AX_AH_BIO_OUT_L 0x3AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ah_bio : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ah_bio : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_ah_bio_out_l_t; + +#define ST1VAFE6AX_AH_BIO_OUT_H 0x3BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ah_bio : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ah_bio : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_ah_bio_out_h_t; + +#define ST1VAFE6AX_TIMESTAMP0 0x40U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_timestamp0_t; + +#define ST1VAFE6AX_TIMESTAMP1 0x41U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_timestamp1_t; + +#define ST1VAFE6AX_TIMESTAMP2 0x42U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_timestamp2_t; + +#define ST1VAFE6AX_TIMESTAMP3 0x43U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t timestamp : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t timestamp : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_timestamp3_t; + +#define ST1VAFE6AX_WAKE_UP_SRC 0x45U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t x_wu : 1; + uint8_t y_wu : 1; + uint8_t z_wu : 1; + uint8_t wu_ia : 1; + uint8_t sleep_state : 1; + uint8_t ff_ia : 1; + uint8_t sleep_change_ia : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t sleep_change_ia : 1; + uint8_t ff_ia : 1; + uint8_t sleep_state : 1; + uint8_t wu_ia : 1; + uint8_t z_wu : 1; + uint8_t y_wu : 1; + uint8_t x_wu : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_wake_up_src_t; + +#define ST1VAFE6AX_TAP_SRC 0x46U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t x_tap : 1; + uint8_t y_tap : 1; + uint8_t z_tap : 1; + uint8_t tap_sign : 1; + uint8_t not_used0 : 1; + uint8_t double_tap : 1; + uint8_t single_tap : 1; + uint8_t tap_ia : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tap_ia : 1; + uint8_t single_tap : 1; + uint8_t double_tap : 1; + uint8_t not_used0 : 1; + uint8_t tap_sign : 1; + uint8_t z_tap : 1; + uint8_t y_tap : 1; + uint8_t x_tap : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_tap_src_t; + +#define ST1VAFE6AX_D6D_SRC 0x47U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t zl : 1; + uint8_t zh : 1; + uint8_t yl : 1; + uint8_t yh : 1; + uint8_t xl : 1; + uint8_t xh : 1; + uint8_t d6d_ia : 1; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t d6d_ia : 1; + uint8_t xh : 1; + uint8_t xl : 1; + uint8_t yh : 1; + uint8_t yl : 1; + uint8_t zh : 1; + uint8_t zl : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_d6d_src_t; + +#define ST1VAFE6AX_EMB_FUNC_STATUS_MAINPAGE 0x49U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t is_step_det : 1; + uint8_t is_tilt : 1; + uint8_t is_sigmot : 1; + uint8_t not_used1 : 1; + uint8_t is_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t is_sigmot : 1; + uint8_t is_tilt : 1; + uint8_t is_step_det : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_emb_func_status_mainpage_t; + +#define ST1VAFE6AX_FSM_STATUS_MAINPAGE 0x4AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm8 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fsm_status_mainpage_t; + +#define ST1VAFE6AX_MLC_STATUS_MAINPAGE 0x4BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_mlc1 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t is_mlc4 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_mlc_status_mainpage_t; + +#define ST1VAFE6AX_INTERNAL_FREQ 0x4FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t freq_fine : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t freq_fine : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_internal_freq_t; + +#define ST1VAFE6AX_FUNCTIONS_ENABLE 0x50U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t inact_en : 2; + uint8_t not_used0 : 1; + uint8_t dis_rst_lir_all_int : 1; + uint8_t not_used1 : 2; + uint8_t timestamp_en : 1; + uint8_t interrupts_enable : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t interrupts_enable : 1; + uint8_t timestamp_en : 1; + uint8_t not_used1 : 2; + uint8_t dis_rst_lir_all_int : 1; + uint8_t not_used0 : 1; + uint8_t inact_en : 2; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_functions_enable_t; + +#define ST1VAFE6AX_INACTIVITY_DUR 0x54U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t inact_dur : 2; + uint8_t xl_inact_odr : 2; + uint8_t wu_inact_ths_w : 3; + uint8_t sleep_status_on_int : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t sleep_status_on_int : 1; + uint8_t wu_inact_ths_w : 3; + uint8_t xl_inact_odr : 2; + uint8_t inact_dur : 2; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_inactivity_dur_t; + +#define ST1VAFE6AX_INACTIVITY_THS 0x55U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t inact_ths : 6; + uint8_t not_used0 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 2; + uint8_t inact_ths : 6; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_inactivity_ths_t; + +#define ST1VAFE6AX_TAP_CFG0 0x56U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t lir : 1; + uint8_t tap_x_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_z_en : 1; + uint8_t slope_fds : 1; + uint8_t hw_func_mask_xl_settl : 1; + uint8_t low_pass_on_6d : 1; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t low_pass_on_6d : 1; + uint8_t hw_func_mask_xl_settl : 1; + uint8_t slope_fds : 1; + uint8_t tap_z_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_x_en : 1; + uint8_t lir : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_tap_cfg0_t; + +#define ST1VAFE6AX_TAP_CFG1 0x57U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths_z : 5; + uint8_t tap_priority : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tap_priority : 3; + uint8_t tap_ths_z : 5; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_tap_cfg1_t; + +#define ST1VAFE6AX_TAP_CFG2 0x58U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths_y : 5; + uint8_t not_used0 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 3; + uint8_t tap_ths_y : 5; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_tap_cfg2_t; + +#define ST1VAFE6AX_TAP_THS_6D 0x59U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t tap_ths_x : 5; + uint8_t sixd_ths : 2; + uint8_t not_used0 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 1; + uint8_t sixd_ths : 2; + uint8_t tap_ths_x : 5; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_tap_ths_6d_t; + +#define ST1VAFE6AX_TAP_DUR 0x5AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t shock : 2; + uint8_t quiet : 2; + uint8_t dur : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t dur : 4; + uint8_t quiet : 2; + uint8_t shock : 2; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_tap_dur_t; + +#define ST1VAFE6AX_WAKE_UP_THS 0x5BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t wk_ths : 6; + uint8_t usr_off_on_wu : 1; + uint8_t single_double_tap : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t single_double_tap : 1; + uint8_t usr_off_on_wu : 1; + uint8_t wk_ths : 6; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_wake_up_ths_t; + +#define ST1VAFE6AX_WAKE_UP_DUR 0x5CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t sleep_dur : 4; + uint8_t not_used0 : 1; + uint8_t wake_dur : 2; + uint8_t ff_dur : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 1; + uint8_t wake_dur : 2; + uint8_t not_used0 : 1; + uint8_t sleep_dur : 4; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_wake_up_dur_t; + +#define ST1VAFE6AX_FREE_FALL 0x5DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t ff_ths : 3; + uint8_t ff_dur : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t ff_dur : 5; + uint8_t ff_ths : 3; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_free_fall_t; + +#define ST1VAFE6AX_MD1_CFG 0x5EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t int1_emb_func : 1; + uint8_t int1_6d : 1; + uint8_t int1_double_tap : 1; + uint8_t int1_ff : 1; + uint8_t int1_wu : 1; + uint8_t int1_single_tap : 1; + uint8_t int1_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_sleep_change : 1; + uint8_t int1_single_tap : 1; + uint8_t int1_wu : 1; + uint8_t int1_ff : 1; + uint8_t int1_double_tap : 1; + uint8_t int1_6d : 1; + uint8_t int1_emb_func : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_md1_cfg_t; + +#define ST1VAFE6AX_MD2_CFG 0x5FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_timestamp : 1; + uint8_t int2_emb_func : 1; + uint8_t int2_6d : 1; + uint8_t int2_double_tap : 1; + uint8_t int2_ff : 1; + uint8_t int2_wu : 1; + uint8_t int2_single_tap : 1; + uint8_t int2_sleep_change : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_sleep_change : 1; + uint8_t int2_single_tap : 1; + uint8_t int2_wu : 1; + uint8_t int2_ff : 1; + uint8_t int2_double_tap : 1; + uint8_t int2_6d : 1; + uint8_t int2_emb_func : 1; + uint8_t int2_timestamp : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_md2_cfg_t; + +#define ST1VAFE6AX_EMB_FUNC_CFG 0x63U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t emb_func_disable : 1; + uint8_t emb_func_irq_mask_xl_settl : 1; + uint8_t emb_func_irq_mask_g_settl : 1; + uint8_t not_used1 : 1; + uint8_t xl_dualc_batch_from_if : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t xl_dualc_batch_from_if : 1; + uint8_t not_used1 : 1; + uint8_t emb_func_irq_mask_g_settl : 1; + uint8_t emb_func_irq_mask_xl_settl : 1; + uint8_t emb_func_disable : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_emb_func_cfg_t; + +#define ST1VAFE6AX_Z_OFS_USR 0x73U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t z_ofs_usr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t z_ofs_usr : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_z_ofs_usr_t; + +#define ST1VAFE6AX_Y_OFS_USR 0x74U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t y_ofs_usr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t y_ofs_usr : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_y_ofs_usr_t; + +#define ST1VAFE6AX_X_OFS_USR 0x75U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t x_ofs_usr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t x_ofs_usr : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_x_ofs_usr_t; + +#define ST1VAFE6AX_FIFO_DATA_OUT_TAG 0x78U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t tag_cnt : 2; + uint8_t tag_sensor : 5; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t tag_sensor : 5; + uint8_t tag_cnt : 2; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fifo_data_out_tag_t; + +#define ST1VAFE6AX_FIFO_DATA_OUT_BYTE_0 0x79U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fifo_data_out_byte_0_t; + +#define ST1VAFE6AX_FIFO_DATA_OUT_BYTE_1 0x7AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fifo_data_out_byte_1_t; + +#define ST1VAFE6AX_FIFO_DATA_OUT_BYTE_2 0x7BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fifo_data_out_byte_2_t; + +#define ST1VAFE6AX_FIFO_DATA_OUT_BYTE_3 0x7CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fifo_data_out_byte_3_t; + +#define ST1VAFE6AX_FIFO_DATA_OUT_BYTE_4 0x7DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fifo_data_out_byte_4_t; + +#define ST1VAFE6AX_FIFO_DATA_OUT_BYTE_5 0x7EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fifo_data_out : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fifo_data_out : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fifo_data_out_byte_5_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page embedded + * @{ + * + */ + +#define ST1VAFE6AX_PAGE_SEL 0x2U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t page_sel : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_sel : 4; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_page_sel_t; + +#define ST1VAFE6AX_EMB_FUNC_EN_A 0x4U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used2 : 1; + uint8_t sflp_game_en : 1; + uint8_t not_used0 : 1; + uint8_t pedo_en : 1; + uint8_t tilt_en : 1; + uint8_t sign_motion_en : 1; + uint8_t not_used1 : 1; + uint8_t mlc_before_fsm_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_before_fsm_en : 1; + uint8_t not_used1 : 1; + uint8_t sign_motion_en : 1; + uint8_t tilt_en : 1; + uint8_t pedo_en : 1; + uint8_t not_used0 : 1; + uint8_t sflp_game_en : 1; + uint8_t not_used2 : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_emb_func_en_a_t; + +#define ST1VAFE6AX_EMB_FUNC_EN_B 0x5U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_en : 1; + uint8_t not_used0 : 2; + uint8_t fifo_compr_en : 1; + uint8_t mlc_en : 1; + uint8_t not_used1 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 3; + uint8_t mlc_en : 1; + uint8_t fifo_compr_en : 1; + uint8_t not_used0 : 2; + uint8_t fsm_en : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_emb_func_en_b_t; + +#define ST1VAFE6AX_EMB_FUNC_EXEC_STATUS 0x7U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t emb_func_endop : 1; + uint8_t emb_func_exec_ovr : 1; + uint8_t not_used0 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 6; + uint8_t emb_func_exec_ovr : 1; + uint8_t emb_func_endop : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_emb_func_exec_status_t; + +#define ST1VAFE6AX_PAGE_ADDRESS 0x8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t page_addr : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_addr : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_page_address_t; + +#define ST1VAFE6AX_PAGE_VALUE 0x9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t page_value : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t page_value : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_page_value_t; + +#define ST1VAFE6AX_EMB_FUNC_INT1 0x0AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t int1_step_detector : 1; + uint8_t int1_tilt : 1; + uint8_t int1_sig_mot : 1; + uint8_t not_used1 : 1; + uint8_t int1_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t int1_sig_mot : 1; + uint8_t int1_tilt : 1; + uint8_t int1_step_detector : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_emb_func_int1_t; + +#define ST1VAFE6AX_FSM_INT1 0x0BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_fsm1 : 1; + uint8_t int1_fsm2 : 1; + uint8_t int1_fsm3 : 1; + uint8_t int1_fsm4 : 1; + uint8_t int1_fsm5 : 1; + uint8_t int1_fsm6 : 1; + uint8_t int1_fsm7 : 1; + uint8_t int1_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int1_fsm8 : 1; + uint8_t int1_fsm7 : 1; + uint8_t int1_fsm6 : 1; + uint8_t int1_fsm5 : 1; + uint8_t int1_fsm4 : 1; + uint8_t int1_fsm3 : 1; + uint8_t int1_fsm2 : 1; + uint8_t int1_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fsm_int1_t; + +#define ST1VAFE6AX_MLC_INT1 0x0DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int1_mlc1 : 1; + uint8_t int1_mlc2 : 1; + uint8_t int1_mlc3 : 1; + uint8_t int1_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t int1_mlc4 : 1; + uint8_t int1_mlc3 : 1; + uint8_t int1_mlc2 : 1; + uint8_t int1_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_mlc_int1_t; + +#define ST1VAFE6AX_EMB_FUNC_INT2 0x0EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t int2_step_detector : 1; + uint8_t int2_tilt : 1; + uint8_t int2_sig_mot : 1; + uint8_t not_used1 : 1; + uint8_t int2_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t int2_sig_mot : 1; + uint8_t int2_tilt : 1; + uint8_t int2_step_detector : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_emb_func_int2_t; + +#define ST1VAFE6AX_FSM_INT2 0x0FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_fsm1 : 1; + uint8_t int2_fsm2 : 1; + uint8_t int2_fsm3 : 1; + uint8_t int2_fsm4 : 1; + uint8_t int2_fsm5 : 1; + uint8_t int2_fsm6 : 1; + uint8_t int2_fsm7 : 1; + uint8_t int2_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t int2_fsm8 : 1; + uint8_t int2_fsm7 : 1; + uint8_t int2_fsm6 : 1; + uint8_t int2_fsm5 : 1; + uint8_t int2_fsm4 : 1; + uint8_t int2_fsm3 : 1; + uint8_t int2_fsm2 : 1; + uint8_t int2_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fsm_int2_t; + +#define ST1VAFE6AX_MLC_INT2 0x11U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t int2_mlc1 : 1; + uint8_t int2_mlc2 : 1; + uint8_t int2_mlc3 : 1; + uint8_t int2_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t int2_mlc4 : 1; + uint8_t int2_mlc3 : 1; + uint8_t int2_mlc2 : 1; + uint8_t int2_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_mlc_int2_t; + +#define ST1VAFE6AX_EMB_FUNC_STATUS 0x12U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t is_step_det : 1; + uint8_t is_tilt : 1; + uint8_t is_sigmot : 1; + uint8_t not_used1 : 1; + uint8_t is_fsm_lc : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm_lc : 1; + uint8_t not_used1 : 1; + uint8_t is_sigmot : 1; + uint8_t is_tilt : 1; + uint8_t is_step_det : 1; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_emb_func_status_t; + +#define ST1VAFE6AX_FSM_STATUS 0x13U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_fsm1 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm8 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t is_fsm8 : 1; + uint8_t is_fsm7 : 1; + uint8_t is_fsm6 : 1; + uint8_t is_fsm5 : 1; + uint8_t is_fsm4 : 1; + uint8_t is_fsm3 : 1; + uint8_t is_fsm2 : 1; + uint8_t is_fsm1 : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fsm_status_t; + +#define ST1VAFE6AX_MLC_STATUS 0x15U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t is_mlc1 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc4 : 1; + uint8_t not_used0 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used0 : 4; + uint8_t is_mlc4 : 1; + uint8_t is_mlc3 : 1; + uint8_t is_mlc2 : 1; + uint8_t is_mlc1 : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_mlc_status_t; + +#define ST1VAFE6AX_PAGE_RW 0x17U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 5; + uint8_t page_read : 1; + uint8_t page_write : 1; + uint8_t emb_func_lir : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t emb_func_lir : 1; + uint8_t page_write : 1; + uint8_t page_read : 1; + uint8_t not_used0 : 5; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_page_rw_t; + +#define ST1VAFE6AX_EMB_FUNC_FIFO_EN_A 0x44U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t sflp_game_fifo_en : 1; + uint8_t not_used1 : 2; + uint8_t sflp_gravity_fifo_en : 1; + uint8_t sflp_gbias_fifo_en : 1; + uint8_t step_counter_fifo_en : 1; + uint8_t mlc_fifo_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_fifo_en : 1; + uint8_t step_counter_fifo_en : 1; + uint8_t sflp_gbias_fifo_en : 1; + uint8_t sflp_gravity_fifo_en : 1; + uint8_t not_used1 : 2; + uint8_t sflp_game_fifo_en : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_emb_func_fifo_en_a_t; + +#define ST1VAFE6AX_EMB_FUNC_FIFO_EN_B 0x45U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t mlc_filter_feature_fifo_en : 1; + uint8_t not_used1 : 6; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 6; + uint8_t mlc_filter_feature_fifo_en : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_emb_func_fifo_en_b_t; + +#define ST1VAFE6AX_FSM_ENABLE 0x46U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm1_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm8_en : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm8_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm1_en : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fsm_enable_t; + +#define ST1VAFE6AX_FSM_LONG_COUNTER_L 0x48U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fsm_long_counter_l_t; + +#define ST1VAFE6AX_FSM_LONG_COUNTER_H 0x49U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fsm_long_counter_h_t; + +#define ST1VAFE6AX_INT_ACK_MASK 0x4BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t iack_mask : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t iack_mask : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_int_ack_mask_t; + +#define ST1VAFE6AX_FSM_OUTS1 0x4CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm1_n_v : 1; + uint8_t fsm1_p_v : 1; + uint8_t fsm1_n_3 : 1; + uint8_t fsm1_p_3 : 1; + uint8_t fsm1_n_2 : 1; + uint8_t fsm1_p_2 : 1; + uint8_t fsm1_n_1 : 1; + uint8_t fsm1_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm1_p_1 : 1; + uint8_t fsm1_n_1 : 1; + uint8_t fsm1_p_2 : 1; + uint8_t fsm1_n_2 : 1; + uint8_t fsm1_p_3 : 1; + uint8_t fsm1_n_3 : 1; + uint8_t fsm1_p_v : 1; + uint8_t fsm1_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fsm_outs1_t; + +#define ST1VAFE6AX_FSM_OUTS2 0x4DU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm2_n_v : 1; + uint8_t fsm2_p_v : 1; + uint8_t fsm2_n_3 : 1; + uint8_t fsm2_p_3 : 1; + uint8_t fsm2_n_2 : 1; + uint8_t fsm2_p_2 : 1; + uint8_t fsm2_n_1 : 1; + uint8_t fsm2_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm2_p_1 : 1; + uint8_t fsm2_n_1 : 1; + uint8_t fsm2_p_2 : 1; + uint8_t fsm2_n_2 : 1; + uint8_t fsm2_p_3 : 1; + uint8_t fsm2_n_3 : 1; + uint8_t fsm2_p_v : 1; + uint8_t fsm2_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fsm_outs2_t; + +#define ST1VAFE6AX_FSM_OUTS3 0x4EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm3_n_v : 1; + uint8_t fsm3_p_v : 1; + uint8_t fsm3_n_3 : 1; + uint8_t fsm3_p_3 : 1; + uint8_t fsm3_n_2 : 1; + uint8_t fsm3_p_2 : 1; + uint8_t fsm3_n_1 : 1; + uint8_t fsm3_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm3_p_1 : 1; + uint8_t fsm3_n_1 : 1; + uint8_t fsm3_p_2 : 1; + uint8_t fsm3_n_2 : 1; + uint8_t fsm3_p_3 : 1; + uint8_t fsm3_n_3 : 1; + uint8_t fsm3_p_v : 1; + uint8_t fsm3_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fsm_outs3_t; + +#define ST1VAFE6AX_FSM_OUTS4 0x4FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm4_n_v : 1; + uint8_t fsm4_p_v : 1; + uint8_t fsm4_n_3 : 1; + uint8_t fsm4_p_3 : 1; + uint8_t fsm4_n_2 : 1; + uint8_t fsm4_p_2 : 1; + uint8_t fsm4_n_1 : 1; + uint8_t fsm4_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm4_p_1 : 1; + uint8_t fsm4_n_1 : 1; + uint8_t fsm4_p_2 : 1; + uint8_t fsm4_n_2 : 1; + uint8_t fsm4_p_3 : 1; + uint8_t fsm4_n_3 : 1; + uint8_t fsm4_p_v : 1; + uint8_t fsm4_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fsm_outs4_t; + +#define ST1VAFE6AX_FSM_OUTS5 0x50U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm5_n_v : 1; + uint8_t fsm5_p_v : 1; + uint8_t fsm5_n_3 : 1; + uint8_t fsm5_p_3 : 1; + uint8_t fsm5_n_2 : 1; + uint8_t fsm5_p_2 : 1; + uint8_t fsm5_n_1 : 1; + uint8_t fsm5_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm5_p_1 : 1; + uint8_t fsm5_n_1 : 1; + uint8_t fsm5_p_2 : 1; + uint8_t fsm5_n_2 : 1; + uint8_t fsm5_p_3 : 1; + uint8_t fsm5_n_3 : 1; + uint8_t fsm5_p_v : 1; + uint8_t fsm5_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fsm_outs5_t; + +#define ST1VAFE6AX_FSM_OUTS6 0x51U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm6_n_v : 1; + uint8_t fsm6_p_v : 1; + uint8_t fsm6_n_3 : 1; + uint8_t fsm6_p_3 : 1; + uint8_t fsm6_n_2 : 1; + uint8_t fsm6_p_2 : 1; + uint8_t fsm6_n_1 : 1; + uint8_t fsm6_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm6_p_1 : 1; + uint8_t fsm6_n_1 : 1; + uint8_t fsm6_p_2 : 1; + uint8_t fsm6_n_2 : 1; + uint8_t fsm6_p_3 : 1; + uint8_t fsm6_n_3 : 1; + uint8_t fsm6_p_v : 1; + uint8_t fsm6_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fsm_outs6_t; + +#define ST1VAFE6AX_FSM_OUTS7 0x52U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm7_n_v : 1; + uint8_t fsm7_p_v : 1; + uint8_t fsm7_n_3 : 1; + uint8_t fsm7_p_3 : 1; + uint8_t fsm7_n_2 : 1; + uint8_t fsm7_p_2 : 1; + uint8_t fsm7_n_1 : 1; + uint8_t fsm7_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm7_p_1 : 1; + uint8_t fsm7_n_1 : 1; + uint8_t fsm7_p_2 : 1; + uint8_t fsm7_n_2 : 1; + uint8_t fsm7_p_3 : 1; + uint8_t fsm7_n_3 : 1; + uint8_t fsm7_p_v : 1; + uint8_t fsm7_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fsm_outs7_t; + +#define ST1VAFE6AX_FSM_OUTS8 0x53U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm8_n_v : 1; + uint8_t fsm8_p_v : 1; + uint8_t fsm8_n_3 : 1; + uint8_t fsm8_p_3 : 1; + uint8_t fsm8_n_2 : 1; + uint8_t fsm8_p_2 : 1; + uint8_t fsm8_n_1 : 1; + uint8_t fsm8_p_1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm8_p_1 : 1; + uint8_t fsm8_n_1 : 1; + uint8_t fsm8_p_2 : 1; + uint8_t fsm8_n_2 : 1; + uint8_t fsm8_p_3 : 1; + uint8_t fsm8_n_3 : 1; + uint8_t fsm8_p_v : 1; + uint8_t fsm8_n_v : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fsm_outs8_t; + +#define ST1VAFE6AX_SFLP_ODR 0x5EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t sflp_game_odr : 3; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t sflp_game_odr : 3; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_sflp_odr_t; + +#define ST1VAFE6AX_FSM_ODR 0x5FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 3; + uint8_t fsm_odr : 3; + uint8_t not_used1 : 2; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 2; + uint8_t fsm_odr : 3; + uint8_t not_used0 : 3; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fsm_odr_t; + +#define ST1VAFE6AX_MLC_ODR 0x60U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 4; + uint8_t mlc_odr : 3; + uint8_t not_used1 : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 1; + uint8_t mlc_odr : 3; + uint8_t not_used0 : 4; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_mlc_odr_t; + +#define ST1VAFE6AX_STEP_COUNTER_L 0x62U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t step : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_step_counter_l_t; + +#define ST1VAFE6AX_STEP_COUNTER_H 0x63U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t step : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_step_counter_h_t; + +#define ST1VAFE6AX_EMB_FUNC_SRC 0x64U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t stepcounter_bit_set : 1; + uint8_t step_overflow : 1; + uint8_t step_count_delta_ia : 1; + uint8_t step_detected : 1; + uint8_t not_used1 : 1; + uint8_t pedo_rst_step : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pedo_rst_step : 1; + uint8_t not_used1 : 1; + uint8_t step_detected : 1; + uint8_t step_count_delta_ia : 1; + uint8_t step_overflow : 1; + uint8_t stepcounter_bit_set : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_emb_func_src_t; + +#define ST1VAFE6AX_EMB_FUNC_INIT_A 0x66U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 1; + uint8_t sflp_game_init : 1; + uint8_t not_used2 : 1; + uint8_t step_det_init : 1; + uint8_t tilt_init : 1; + uint8_t sig_mot_init : 1; + uint8_t not_used1 : 1; + uint8_t mlc_before_fsm_init : 1; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_before_fsm_init : 1; + uint8_t not_used1 : 1; + uint8_t sig_mot_init : 1; + uint8_t tilt_init : 1; + uint8_t step_det_init : 1; + uint8_t not_used2 : 1; + uint8_t sflp_game_init : 1; + uint8_t not_used0 : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_emb_func_init_a_t; + +#define ST1VAFE6AX_EMB_FUNC_INIT_B 0x67U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_init : 1; + uint8_t not_used0 : 2; + uint8_t fifo_compr_init : 1; + uint8_t mlc_init : 1; + uint8_t not_used1 : 3; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 3; + uint8_t mlc_init : 1; + uint8_t fifo_compr_init : 1; + uint8_t not_used0 : 2; + uint8_t fsm_init : 1; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_emb_func_init_b_t; + +#define ST1VAFE6AX_MLC1_SRC 0x70U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc1_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc1_src : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_mlc1_src_t; + +#define ST1VAFE6AX_MLC2_SRC 0x71U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc2_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc2_src : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_mlc2_src_t; + +#define ST1VAFE6AX_MLC3_SRC 0x72U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc3_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc3_src : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_mlc3_src_t; + +#define ST1VAFE6AX_MLC4_SRC 0x73U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc4_src : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc4_src : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_mlc4_src_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page pg0_emb_adv + * @{ + * + */ +#define ST1VAFE6AX_EMB_ADV_PG_0 0x000 + +#define ST1VAFE6AX_SFLP_GAME_GBIASX_L 0x6EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasx : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_sflp_game_gbiasx_l_t; + +#define ST1VAFE6AX_SFLP_GAME_GBIASX_H 0x6FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasx : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasx : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_sflp_game_gbiasx_h_t; + +#define ST1VAFE6AX_SFLP_GAME_GBIASY_L 0x70U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasy : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_sflp_game_gbiasy_l_t; + +#define ST1VAFE6AX_SFLP_GAME_GBIASY_H 0x71U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasy : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasy : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_sflp_game_gbiasy_h_t; + +#define ST1VAFE6AX_SFLP_GAME_GBIASZ_L 0x72U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasz : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_sflp_game_gbiasz_l_t; + +#define ST1VAFE6AX_SFLP_GAME_GBIASZ_H 0x73U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t gbiasz : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t gbiasz : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_sflp_game_gbiasz_h_t; + +#define ST1VAFE6AX_FSM_BIO_SENSITIVITY_L 0xBAU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_bio_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_bio_s : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fsm_bio_sensitivity_l_t; + +#define ST1VAFE6AX_FSM_BIO_SENSITIVITY_H 0xBBU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_bio_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_bio_s : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fsm_bio_sensitivity_h_t; + +/** + * @} + * + */ + +/** @defgroup bitfields page pg1_emb_adv + * @{ + * + */ + +#define ST1VAFE6AX_EMB_ADV_PG_1 0x001 + +#define ST1VAFE6AX_FSM_LC_TIMEOUT_L 0x17AU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc_timeout : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc_timeout : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fsm_lc_timeout_l_t; + +#define ST1VAFE6AX_FSM_LC_TIMEOUT_H 0x17BU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_lc_timeout : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_lc_timeout : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fsm_lc_timeout_h_t; + +#define ST1VAFE6AX_FSM_PROGRAMS 0x17CU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_n_prog : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_n_prog : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fsm_programs_t; + +#define ST1VAFE6AX_FSM_START_ADD_L 0x17EU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_start : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_start : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fsm_start_add_l_t; + +#define ST1VAFE6AX_FSM_START_ADD_H 0x17FU +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t fsm_start : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t fsm_start : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_fsm_start_add_h_t; + +#define ST1VAFE6AX_PEDO_CMD_REG 0x183U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t not_used0 : 2; + uint8_t fp_rejection_en : 1; + uint8_t carry_count_en : 1; + uint8_t not_used1 : 4; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t not_used1 : 4; + uint8_t carry_count_en : 1; + uint8_t fp_rejection_en : 1; + uint8_t not_used0 : 2; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_pedo_cmd_reg_t; + +#define ST1VAFE6AX_PEDO_DEB_STEPS_CONF 0x184U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t deb_step : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t deb_step : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_pedo_deb_steps_conf_t; + +#define ST1VAFE6AX_PEDO_SC_DELTAT_L 0x1D0U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t pd_sc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pd_sc : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_pedo_sc_deltat_l_t; + +#define ST1VAFE6AX_PEDO_SC_DELTAT_H 0x1D1U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t pd_sc : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t pd_sc : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_pedo_sc_deltat_h_t; + +#define ST1VAFE6AX_MLC_BIO_SENSITIVITY_L 0x1E8U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc_bio_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_bio_s : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_mlc_bio_sensitivity_l_t; + +#define ST1VAFE6AX_MLC_BIO_SENSITIVITY_H 0x1E9U +typedef struct +{ +#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN + uint8_t mlc_bio_s : 8; +#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN + uint8_t mlc_bio_s : 8; +#endif /* DRV_BYTE_ORDER */ +} st1vafe6ax_mlc_bio_sensitivity_h_t; + +/** + * @} + * + */ + +#define ST1VAFE6AX_START_FSM_ADD 0x035CU + +/** + * @defgroup ST1VAFE6AX_Register_Union + * @brief These unions group all the registers having a bit-field + * description. + * These unions are useful but it's not needed by the driver. + * + * REMOVING this unions you are compliant with: + * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " + * + * @{ + * + */ +typedef union +{ + st1vafe6ax_func_cfg_access_t func_cfg_access; + st1vafe6ax_pin_ctrl_t pin_ctrl; + st1vafe6ax_if_cfg_t if_cfg; + st1vafe6ax_fifo_ctrl1_t fifo_ctrl1; + st1vafe6ax_fifo_ctrl2_t fifo_ctrl2; + st1vafe6ax_fifo_ctrl3_t fifo_ctrl3; + st1vafe6ax_fifo_ctrl4_t fifo_ctrl4; + st1vafe6ax_counter_bdr_reg1_t counter_bdr_reg1; + st1vafe6ax_counter_bdr_reg2_t counter_bdr_reg2; + st1vafe6ax_int1_ctrl_t int1_ctrl; + st1vafe6ax_int2_ctrl_t int2_ctrl; + st1vafe6ax_who_am_i_t who_am_i; + st1vafe6ax_ctrl1_t ctrl1; + st1vafe6ax_ctrl2_t ctrl2; + st1vafe6ax_ctrl3_t ctrl3; + st1vafe6ax_ctrl4_t ctrl4; + st1vafe6ax_ctrl5_t ctrl5; + st1vafe6ax_ctrl6_t ctrl6; + st1vafe6ax_ctrl7_t ctrl7; + st1vafe6ax_ctrl8_t ctrl8; + st1vafe6ax_ctrl9_t ctrl9; + st1vafe6ax_ctrl10_t ctrl10; + st1vafe6ax_fifo_status1_t fifo_status1; + st1vafe6ax_fifo_status2_t fifo_status2; + st1vafe6ax_all_int_src_t all_int_src; + st1vafe6ax_status_reg_t status_reg; + st1vafe6ax_out_temp_l_t out_temp_l; + st1vafe6ax_out_temp_h_t out_temp_h; + st1vafe6ax_outx_l_g_t outx_l_g; + st1vafe6ax_outx_h_g_t outx_h_g; + st1vafe6ax_outy_l_g_t outy_l_g; + st1vafe6ax_outy_h_g_t outy_h_g; + st1vafe6ax_outz_l_g_t outz_l_g; + st1vafe6ax_outz_h_g_t outz_h_g; + st1vafe6ax_outz_l_a_t outz_l_a; + st1vafe6ax_outz_h_a_t outz_h_a; + st1vafe6ax_outy_l_a_t outy_l_a; + st1vafe6ax_outy_h_a_t outy_h_a; + st1vafe6ax_outx_l_a_t outx_l_a; + st1vafe6ax_outx_h_a_t outx_h_a; + st1vafe6ax_ui_outz_l_a_dualc_t ui_outz_l_a_dualc; + st1vafe6ax_ui_outz_h_a_dualc_t ui_outz_h_a_dualc; + st1vafe6ax_ui_outy_l_a_dualc_t ui_outy_l_a_dualc; + st1vafe6ax_ui_outy_h_a_dualc_t ui_outy_h_a_dualc; + st1vafe6ax_ui_outx_l_a_dualc_t ui_outx_l_a_dualc; + st1vafe6ax_ui_outx_h_a_dualc_t ui_outx_h_a_dualc; + st1vafe6ax_ah_bio_out_l_t ah_bio_out_l; + st1vafe6ax_ah_bio_out_h_t ah_bio_out_h; + st1vafe6ax_timestamp0_t timestamp0; + st1vafe6ax_timestamp1_t timestamp1; + st1vafe6ax_timestamp2_t timestamp2; + st1vafe6ax_timestamp3_t timestamp3; + st1vafe6ax_wake_up_src_t wake_up_src; + st1vafe6ax_tap_src_t tap_src; + st1vafe6ax_d6d_src_t d6d_src; + st1vafe6ax_emb_func_status_mainpage_t emb_func_status_mainpage; + st1vafe6ax_fsm_status_mainpage_t fsm_status_mainpage; + st1vafe6ax_mlc_status_mainpage_t mlc_status_mainpage; + st1vafe6ax_internal_freq_t internal_freq; + st1vafe6ax_functions_enable_t functions_enable; + st1vafe6ax_inactivity_dur_t inactivity_dur; + st1vafe6ax_inactivity_ths_t inactivity_ths; + st1vafe6ax_tap_cfg0_t tap_cfg0; + st1vafe6ax_tap_cfg1_t tap_cfg1; + st1vafe6ax_tap_cfg2_t tap_cfg2; + st1vafe6ax_tap_ths_6d_t tap_ths_6d; + st1vafe6ax_tap_dur_t int_dur2; + st1vafe6ax_wake_up_ths_t wake_up_ths; + st1vafe6ax_wake_up_dur_t wake_up_dur; + st1vafe6ax_free_fall_t free_fall; + st1vafe6ax_md1_cfg_t md1_cfg; + st1vafe6ax_md2_cfg_t md2_cfg; + st1vafe6ax_emb_func_cfg_t emb_func_cfg; + st1vafe6ax_z_ofs_usr_t z_ofs_usr; + st1vafe6ax_y_ofs_usr_t y_ofs_usr; + st1vafe6ax_x_ofs_usr_t x_ofs_usr; + st1vafe6ax_fifo_data_out_tag_t fifo_data_out_tag; + st1vafe6ax_fifo_data_out_byte_0_t fifo_data_out_byte_0; + st1vafe6ax_fifo_data_out_byte_1_t fifo_data_out_byte_1; + st1vafe6ax_fifo_data_out_byte_2_t fifo_data_out_byte_2; + st1vafe6ax_fifo_data_out_byte_3_t fifo_data_out_byte_3; + st1vafe6ax_fifo_data_out_byte_4_t fifo_data_out_byte_4; + st1vafe6ax_fifo_data_out_byte_5_t fifo_data_out_byte_5; + st1vafe6ax_page_sel_t page_sel; + st1vafe6ax_emb_func_en_a_t emb_func_en_a; + st1vafe6ax_emb_func_en_b_t emb_func_en_b; + st1vafe6ax_emb_func_exec_status_t emb_func_exec_status; + st1vafe6ax_page_address_t page_address; + st1vafe6ax_page_value_t page_value; + st1vafe6ax_emb_func_int1_t emb_func_int1; + st1vafe6ax_fsm_int1_t fsm_int1; + st1vafe6ax_mlc_int1_t mlc_int1; + st1vafe6ax_emb_func_int2_t emb_func_int2; + st1vafe6ax_fsm_int2_t fsm_int2; + st1vafe6ax_mlc_int2_t mlc_int2; + st1vafe6ax_emb_func_status_t emb_func_status; + st1vafe6ax_fsm_status_t fsm_status; + st1vafe6ax_mlc_status_t mlc_status; + st1vafe6ax_page_rw_t page_rw; + st1vafe6ax_emb_func_fifo_en_a_t emb_func_fifo_en_a; + st1vafe6ax_emb_func_fifo_en_b_t emb_func_fifo_en_b; + st1vafe6ax_fsm_enable_t fsm_enable; + st1vafe6ax_fsm_long_counter_l_t fsm_long_counter_l; + st1vafe6ax_fsm_long_counter_h_t fsm_long_counter_h; + st1vafe6ax_fsm_outs1_t fsm_outs1; + st1vafe6ax_fsm_outs2_t fsm_outs2; + st1vafe6ax_fsm_outs3_t fsm_outs3; + st1vafe6ax_fsm_outs4_t fsm_outs4; + st1vafe6ax_fsm_outs5_t fsm_outs5; + st1vafe6ax_fsm_outs6_t fsm_outs6; + st1vafe6ax_fsm_outs7_t fsm_outs7; + st1vafe6ax_fsm_outs8_t fsm_outs8; + st1vafe6ax_fsm_odr_t fsm_odr; + st1vafe6ax_mlc_odr_t mlc_odr; + st1vafe6ax_step_counter_l_t step_counter_l; + st1vafe6ax_step_counter_h_t step_counter_h; + st1vafe6ax_emb_func_src_t emb_func_src; + st1vafe6ax_emb_func_init_a_t emb_func_init_a; + st1vafe6ax_emb_func_init_b_t emb_func_init_b; + st1vafe6ax_mlc1_src_t mlc1_src; + st1vafe6ax_mlc2_src_t mlc2_src; + st1vafe6ax_mlc3_src_t mlc3_src; + st1vafe6ax_mlc4_src_t mlc4_src; + st1vafe6ax_fsm_bio_sensitivity_l_t fsm_bio_sensitivity_l; + st1vafe6ax_fsm_bio_sensitivity_h_t fsm_bio_sensitivity_h; + st1vafe6ax_fsm_lc_timeout_l_t fsm_lc_timeout_l; + st1vafe6ax_fsm_lc_timeout_h_t fsm_lc_timeout_h; + st1vafe6ax_fsm_programs_t fsm_programs; + st1vafe6ax_fsm_start_add_l_t fsm_start_add_l; + st1vafe6ax_fsm_start_add_h_t fsm_start_add_h; + st1vafe6ax_pedo_cmd_reg_t pedo_cmd_reg; + st1vafe6ax_pedo_deb_steps_conf_t pedo_deb_steps_conf; + st1vafe6ax_pedo_sc_deltat_l_t pedo_sc_deltat_l; + st1vafe6ax_pedo_sc_deltat_h_t pedo_sc_deltat_h; + st1vafe6ax_mlc_bio_sensitivity_l_t mlc_bio_sensitivity_l; + st1vafe6ax_mlc_bio_sensitivity_h_t mlc_bio_sensitivity_h; + bitwise_t bitwise; + uint8_t byte; +} st1vafe6ax_reg_t; + + +/** + * @} + * + */ + +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ + +/* + * These are the basic platform dependent I/O routines to read + * and write device registers connected on a standard bus. + * The driver keeps offering a default implementation based on function + * pointers to read/write routines for backward compatibility. + * The __weak directive allows the final application to overwrite + * them with a custom implementation. + */ + +int32_t st1vafe6ax_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); +int32_t st1vafe6ax_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, + uint8_t *data, + uint16_t len); + +float_t st1vafe6ax_from_sflp_to_mg(int16_t lsb); +float_t st1vafe6ax_from_fs2_to_mg(int16_t lsb); +float_t st1vafe6ax_from_fs4_to_mg(int16_t lsb); +float_t st1vafe6ax_from_fs8_to_mg(int16_t lsb); +float_t st1vafe6ax_from_fs16_to_mg(int16_t lsb); + +float_t st1vafe6ax_from_fs125_to_mdps(int16_t lsb); +float_t st1vafe6ax_from_fs500_to_mdps(int16_t lsb); +float_t st1vafe6ax_from_fs250_to_mdps(int16_t lsb); +float_t st1vafe6ax_from_fs1000_to_mdps(int16_t lsb); +float_t st1vafe6ax_from_fs2000_to_mdps(int16_t lsb); +float_t st1vafe6ax_from_fs4000_to_mdps(int16_t lsb); + +float_t st1vafe6ax_from_lsb_to_celsius(int16_t lsb); + +uint64_t st1vafe6ax_from_lsb_to_nsec(uint32_t lsb); + +float_t st1vafe6ax_from_lsb_to_mv(int16_t lsb); + +typedef enum +{ + ST1VAFE6AX_READY = 0x0, + ST1VAFE6AX_GLOBAL_RST = 0x1, + ST1VAFE6AX_RESTORE_CAL_PARAM = 0x2, + ST1VAFE6AX_RESTORE_CTRL_REGS = 0x4, +} st1vafe6ax_reset_t; +int32_t st1vafe6ax_reset_set(const stmdev_ctx_t *ctx, st1vafe6ax_reset_t val); +int32_t st1vafe6ax_reset_get(const stmdev_ctx_t *ctx, st1vafe6ax_reset_t *val); + +typedef enum +{ + ST1VAFE6AX_MAIN_MEM_BANK = 0x0, + ST1VAFE6AX_EMBED_FUNC_MEM_BANK = 0x1, +} st1vafe6ax_mem_bank_t; +int32_t st1vafe6ax_mem_bank_set(const stmdev_ctx_t *ctx, st1vafe6ax_mem_bank_t val); +int32_t st1vafe6ax_mem_bank_get(const stmdev_ctx_t *ctx, + st1vafe6ax_mem_bank_t *val); + +int32_t st1vafe6ax_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ST1VAFE6AX_XL_ODR_OFF = 0x0, + ST1VAFE6AX_XL_ODR_AT_1Hz875 = 0x1, + ST1VAFE6AX_XL_ODR_AT_7Hz5 = 0x2, + ST1VAFE6AX_XL_ODR_AT_15Hz = 0x3, + ST1VAFE6AX_XL_ODR_AT_30Hz = 0x4, + ST1VAFE6AX_XL_ODR_AT_60Hz = 0x5, + ST1VAFE6AX_XL_ODR_AT_120Hz = 0x6, + ST1VAFE6AX_XL_ODR_AT_240Hz = 0x7, + ST1VAFE6AX_XL_ODR_AT_480Hz = 0x8, + ST1VAFE6AX_XL_ODR_AT_960Hz = 0x9, + ST1VAFE6AX_XL_ODR_AT_1920Hz = 0xA, + ST1VAFE6AX_XL_ODR_AT_3840Hz = 0xB, +} st1vafe6ax_xl_data_rate_t; +int32_t st1vafe6ax_xl_data_rate_set(const stmdev_ctx_t *ctx, + st1vafe6ax_xl_data_rate_t val); +int32_t st1vafe6ax_xl_data_rate_get(const stmdev_ctx_t *ctx, + st1vafe6ax_xl_data_rate_t *val); + +typedef enum +{ + ST1VAFE6AX_XL_HIGH_PERFORMANCE_MD = 0x0, + ST1VAFE6AX_XL_HIGH_PERFORMANCE_2_MD = 0x2, + ST1VAFE6AX_XL_LOW_POWER_2_AVG_MD = 0x4, + ST1VAFE6AX_XL_LOW_POWER_4_AVG_MD = 0x5, + ST1VAFE6AX_XL_LOW_POWER_8_AVG_MD = 0x6, +} st1vafe6ax_xl_mode_t; +int32_t st1vafe6ax_xl_mode_set(const stmdev_ctx_t *ctx, st1vafe6ax_xl_mode_t val); +int32_t st1vafe6ax_xl_mode_get(const stmdev_ctx_t *ctx, st1vafe6ax_xl_mode_t *val); + +typedef enum +{ + ST1VAFE6AX_GY_ODR_OFF = 0x0, + ST1VAFE6AX_GY_ODR_AT_7Hz5 = 0x2, + ST1VAFE6AX_GY_ODR_AT_15Hz = 0x3, + ST1VAFE6AX_GY_ODR_AT_30Hz = 0x4, + ST1VAFE6AX_GY_ODR_AT_60Hz = 0x5, + ST1VAFE6AX_GY_ODR_AT_120Hz = 0x6, + ST1VAFE6AX_GY_ODR_AT_240Hz = 0x7, + ST1VAFE6AX_GY_ODR_AT_480Hz = 0x8, + ST1VAFE6AX_GY_ODR_AT_960Hz = 0x9, + ST1VAFE6AX_GY_ODR_AT_1920Hz = 0xa, + ST1VAFE6AX_GY_ODR_AT_3840Hz = 0xb, +} st1vafe6ax_gy_data_rate_t; +int32_t st1vafe6ax_gy_data_rate_set(const stmdev_ctx_t *ctx, + st1vafe6ax_gy_data_rate_t val); +int32_t st1vafe6ax_gy_data_rate_get(const stmdev_ctx_t *ctx, + st1vafe6ax_gy_data_rate_t *val); + +typedef enum +{ + ST1VAFE6AX_GY_HIGH_PERFORMANCE_MD = 0x0, + ST1VAFE6AX_GY_SLEEP_MD = 0x4, + ST1VAFE6AX_GY_LOW_POWER_MD = 0x5, +} st1vafe6ax_gy_mode_t; +int32_t st1vafe6ax_gy_mode_set(const stmdev_ctx_t *ctx, st1vafe6ax_gy_mode_t val); +int32_t st1vafe6ax_gy_mode_get(const stmdev_ctx_t *ctx, st1vafe6ax_gy_mode_t *val); + +int32_t st1vafe6ax_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe6ax_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t st1vafe6ax_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe6ax_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ST1VAFE6AX_DRDY_LATCHED = 0x0, + ST1VAFE6AX_DRDY_PULSED = 0x1, +} st1vafe6ax_data_ready_mode_t; +int32_t st1vafe6ax_data_ready_mode_set(const stmdev_ctx_t *ctx, + st1vafe6ax_data_ready_mode_t val); +int32_t st1vafe6ax_data_ready_mode_get(const stmdev_ctx_t *ctx, + st1vafe6ax_data_ready_mode_t *val); + +typedef enum +{ + ST1VAFE6AX_125dps = 0x0, + ST1VAFE6AX_250dps = 0x1, + ST1VAFE6AX_500dps = 0x2, + ST1VAFE6AX_1000dps = 0x3, + ST1VAFE6AX_2000dps = 0x4, + ST1VAFE6AX_4000dps = 0xc, +} st1vafe6ax_gy_full_scale_t; +int32_t st1vafe6ax_gy_full_scale_set(const stmdev_ctx_t *ctx, + st1vafe6ax_gy_full_scale_t val); +int32_t st1vafe6ax_gy_full_scale_get(const stmdev_ctx_t *ctx, + st1vafe6ax_gy_full_scale_t *val); + +typedef enum +{ + ST1VAFE6AX_2g = 0x0, + ST1VAFE6AX_4g = 0x1, + ST1VAFE6AX_8g = 0x2, +} st1vafe6ax_xl_full_scale_t; +int32_t st1vafe6ax_xl_full_scale_set(const stmdev_ctx_t *ctx, + st1vafe6ax_xl_full_scale_t val); +int32_t st1vafe6ax_xl_full_scale_get(const stmdev_ctx_t *ctx, + st1vafe6ax_xl_full_scale_t *val); + +int32_t st1vafe6ax_xl_dual_channel_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe6ax_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ST1VAFE6AX_XL_ST_DISABLE = 0x0, + ST1VAFE6AX_XL_ST_POSITIVE = 0x1, + ST1VAFE6AX_XL_ST_NEGATIVE = 0x2, + ST1VAFE6AX_XL_ST_OFFSET_POS = 0x5, + ST1VAFE6AX_XL_ST_OFFSET_NEG = 0x6, +} st1vafe6ax_xl_self_test_t; +int32_t st1vafe6ax_xl_self_test_set(const stmdev_ctx_t *ctx, + st1vafe6ax_xl_self_test_t val); +int32_t st1vafe6ax_xl_self_test_get(const stmdev_ctx_t *ctx, + st1vafe6ax_xl_self_test_t *val); + +typedef enum +{ + ST1VAFE6AX_GY_ST_DISABLE = 0x0, + ST1VAFE6AX_GY_ST_POSITIVE = 0x1, + ST1VAFE6AX_GY_ST_NEGATIVE = 0x2, +} st1vafe6ax_gy_self_test_t; +int32_t st1vafe6ax_gy_self_test_set(const stmdev_ctx_t *ctx, + st1vafe6ax_gy_self_test_t val); +int32_t st1vafe6ax_gy_self_test_get(const stmdev_ctx_t *ctx, + st1vafe6ax_gy_self_test_t *val); + +typedef struct +{ + uint8_t drdy_xl : 1; + uint8_t drdy_gy : 1; + uint8_t drdy_temp : 1; + uint8_t drdy_ah_bio : 1; + uint8_t gy_settling : 1; + uint8_t den_flag : 1; + uint8_t timestamp : 1; + uint8_t free_fall : 1; + uint8_t wake_up : 1; + uint8_t wake_up_z : 1; + uint8_t wake_up_y : 1; + uint8_t wake_up_x : 1; + uint8_t single_tap : 1; + uint8_t double_tap : 1; + uint8_t tap_z : 1; + uint8_t tap_y : 1; + uint8_t tap_x : 1; + uint8_t tap_sign : 1; + uint8_t six_d : 1; + uint8_t six_d_xl : 1; + uint8_t six_d_xh : 1; + uint8_t six_d_yl : 1; + uint8_t six_d_yh : 1; + uint8_t six_d_zl : 1; + uint8_t six_d_zh : 1; + uint8_t sleep_change : 1; + uint8_t sleep_state : 1; + uint8_t step_detector : 1; + uint8_t step_count_inc : 1; + uint8_t step_count_overflow : 1; + uint8_t step_on_delta_time : 1; + uint8_t emb_func_stand_by : 1; + uint8_t emb_func_time_exceed: 1; + uint8_t tilt : 1; + uint8_t sig_mot : 1; + uint8_t fsm_lc : 1; + uint8_t fsm1 : 1; + uint8_t fsm2 : 1; + uint8_t fsm3 : 1; + uint8_t fsm4 : 1; + uint8_t fsm5 : 1; + uint8_t fsm6 : 1; + uint8_t fsm7 : 1; + uint8_t fsm8 : 1; + uint8_t mlc1 : 1; + uint8_t mlc2 : 1; + uint8_t mlc3 : 1; + uint8_t mlc4 : 1; + uint8_t fifo_bdr : 1; + uint8_t fifo_full : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_th : 1; +} st1vafe6ax_all_sources_t; +int32_t st1vafe6ax_all_sources_get(const stmdev_ctx_t *ctx, + st1vafe6ax_all_sources_t *val); + +typedef struct +{ + uint8_t drdy_xl : 1; + uint8_t drdy_gy : 1; + uint8_t drdy_temp : 1; + uint8_t drdy_ah_bio : 1; +} st1vafe6ax_data_ready_t; +int32_t st1vafe6ax_flag_data_ready_get(const stmdev_ctx_t *ctx, + st1vafe6ax_data_ready_t *val); + +int32_t st1vafe6ax_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t st1vafe6ax_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t st1vafe6ax_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t st1vafe6ax_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t st1vafe6ax_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, + int16_t *val); + +int32_t st1vafe6ax_ah_bio_raw_get(const stmdev_ctx_t *ctx, int16_t *val); + +int32_t st1vafe6ax_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val); + +int32_t st1vafe6ax_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len); +int32_t st1vafe6ax_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, + uint8_t *buf, uint8_t len); + +int32_t st1vafe6ax_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe6ax_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t st1vafe6ax_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); + +typedef enum +{ + ST1VAFE6AX_AUTO = 0x0, + ST1VAFE6AX_ALWAYS_ACTIVE = 0x1, +} st1vafe6ax_filt_anti_spike_t; +int32_t st1vafe6ax_filt_anti_spike_set(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_anti_spike_t val); +int32_t st1vafe6ax_filt_anti_spike_get(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_anti_spike_t *val); + +typedef struct +{ + uint8_t drdy : 1; + uint8_t irq_xl : 1; + uint8_t irq_g : 1; +} st1vafe6ax_filt_settling_mask_t; +int32_t st1vafe6ax_filt_settling_mask_set(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_settling_mask_t val); +int32_t st1vafe6ax_filt_settling_mask_get(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_settling_mask_t *val); + +typedef enum +{ + ST1VAFE6AX_GY_ULTRA_LIGHT = 0x0, + ST1VAFE6AX_GY_VERY_LIGHT = 0x1, + ST1VAFE6AX_GY_LIGHT = 0x2, + ST1VAFE6AX_GY_MEDIUM = 0x3, + ST1VAFE6AX_GY_STRONG = 0x4, + ST1VAFE6AX_GY_VERY_STRONG = 0x5, + ST1VAFE6AX_GY_AGGRESSIVE = 0x6, + ST1VAFE6AX_GY_XTREME = 0x7, +} st1vafe6ax_filt_gy_lp1_bandwidth_t; +int32_t st1vafe6ax_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_gy_lp1_bandwidth_t val); +int32_t st1vafe6ax_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_gy_lp1_bandwidth_t *val); + +int32_t st1vafe6ax_filt_gy_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe6ax_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t hpf : 1; + uint8_t lpf : 1; +} st1vafe6ax_filt_ah_bio_conf_t; +int32_t st1vafe6ax_filt_ah_bio_conf_set(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_ah_bio_conf_t val); +int32_t st1vafe6ax_filt_ah_bio_conf_get(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_ah_bio_conf_t *val); + +typedef enum +{ + ST1VAFE6AX_XL_ULTRA_LIGHT = 0x0, + ST1VAFE6AX_XL_VERY_LIGHT = 0x1, + ST1VAFE6AX_XL_LIGHT = 0x2, + ST1VAFE6AX_XL_MEDIUM = 0x3, + ST1VAFE6AX_XL_STRONG = 0x4, + ST1VAFE6AX_XL_VERY_STRONG = 0x5, + ST1VAFE6AX_XL_AGGRESSIVE = 0x6, + ST1VAFE6AX_XL_XTREME = 0x7, +} st1vafe6ax_filt_xl_lp2_bandwidth_t; +int32_t st1vafe6ax_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_xl_lp2_bandwidth_t val); +int32_t st1vafe6ax_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_xl_lp2_bandwidth_t *val); + +int32_t st1vafe6ax_filt_xl_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe6ax_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t st1vafe6ax_filt_xl_hp_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe6ax_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t st1vafe6ax_filt_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe6ax_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ST1VAFE6AX_HP_MD_NORMAL = 0x0, + ST1VAFE6AX_HP_MD_REFERENCE = 0x1, +} st1vafe6ax_filt_xl_hp_mode_t; +int32_t st1vafe6ax_filt_xl_hp_mode_set(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_xl_hp_mode_t val); +int32_t st1vafe6ax_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_xl_hp_mode_t *val); + +typedef enum +{ + ST1VAFE6AX_WK_FEED_SLOPE = 0x0, + ST1VAFE6AX_WK_FEED_HIGH_PASS = 0x1, + ST1VAFE6AX_WK_FEED_LP_WITH_OFFSET = 0x2, +} st1vafe6ax_filt_wkup_act_feed_t; +int32_t st1vafe6ax_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_wkup_act_feed_t val); +int32_t st1vafe6ax_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_wkup_act_feed_t *val); + +int32_t st1vafe6ax_mask_trigger_xl_settl_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe6ax_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ST1VAFE6AX_SIXD_FEED_ODR_DIV_2 = 0x0, + ST1VAFE6AX_SIXD_FEED_LOW_PASS = 0x1, +} st1vafe6ax_filt_sixd_feed_t; +int32_t st1vafe6ax_filt_sixd_feed_set(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_sixd_feed_t val); +int32_t st1vafe6ax_filt_sixd_feed_get(const stmdev_ctx_t *ctx, + st1vafe6ax_filt_sixd_feed_t *val); + +int32_t st1vafe6ax_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe6ax_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ST1VAFE6AX_I2C_I3C_ENABLE = 0x0, + ST1VAFE6AX_I2C_I3C_DISABLE = 0x1, +} st1vafe6ax_ui_i2c_i3c_mode_t; +int32_t st1vafe6ax_ui_i2c_i3c_mode_set(const stmdev_ctx_t *ctx, + st1vafe6ax_ui_i2c_i3c_mode_t val); +int32_t st1vafe6ax_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx, + st1vafe6ax_ui_i2c_i3c_mode_t *val); + +typedef enum +{ + ST1VAFE6AX_SPI_4_WIRE = 0x0, + ST1VAFE6AX_SPI_3_WIRE = 0x1, +} st1vafe6ax_spi_mode_t; +int32_t st1vafe6ax_spi_mode_set(const stmdev_ctx_t *ctx, st1vafe6ax_spi_mode_t val); +int32_t st1vafe6ax_spi_mode_get(const stmdev_ctx_t *ctx, + st1vafe6ax_spi_mode_t *val); + +int32_t st1vafe6ax_ui_sda_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe6ax_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ST1VAFE6AX_IBI_2us = 0x0, + ST1VAFE6AX_IBI_50us = 0x1, + ST1VAFE6AX_IBI_1ms = 0x2, + ST1VAFE6AX_IBI_25ms = 0x3, +} st1vafe6ax_i3c_ibi_time_t; +int32_t st1vafe6ax_i3c_ibi_time_set(const stmdev_ctx_t *ctx, + st1vafe6ax_i3c_ibi_time_t val); +int32_t st1vafe6ax_i3c_ibi_time_get(const stmdev_ctx_t *ctx, + st1vafe6ax_i3c_ibi_time_t *val); + +typedef enum +{ + ST1VAFE6AX_PUSH_PULL = 0x0, + ST1VAFE6AX_OPEN_DRAIN = 0x1, +} st1vafe6ax_int_pin_mode_t; +int32_t st1vafe6ax_int_pin_mode_set(const stmdev_ctx_t *ctx, + st1vafe6ax_int_pin_mode_t val); +int32_t st1vafe6ax_int_pin_mode_get(const stmdev_ctx_t *ctx, + st1vafe6ax_int_pin_mode_t *val); + +typedef enum +{ + ST1VAFE6AX_ACTIVE_HIGH = 0x0, + ST1VAFE6AX_ACTIVE_LOW = 0x1, +} st1vafe6ax_pin_polarity_t; +int32_t st1vafe6ax_pin_polarity_set(const stmdev_ctx_t *ctx, + st1vafe6ax_pin_polarity_t val); +int32_t st1vafe6ax_pin_polarity_get(const stmdev_ctx_t *ctx, + st1vafe6ax_pin_polarity_t *val); + +typedef struct +{ + uint8_t boot : 1; + uint8_t drdy_xl : 1; + uint8_t drdy_gy : 1; + uint8_t drdy_temp : 1; + uint8_t drdy_ah_bio : 1; + uint8_t fifo_th : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_full : 1; + uint8_t fifo_bdr : 1; + uint8_t den_flag : 1; + uint8_t timestamp : 1; // impact on int2 signals + uint8_t six_d : 1; + uint8_t double_tap : 1; + uint8_t free_fall : 1; + uint8_t wake_up : 1; + uint8_t single_tap : 1; + uint8_t sleep_change : 1; + uint8_t sleep_status : 1; + uint8_t step_detector : 1; + uint8_t step_count_overflow : 1; + uint8_t tilt : 1; + uint8_t sig_mot : 1; + uint8_t emb_func_stand_by : 1; // impact on int2 signals + uint8_t fsm_lc : 1; + uint8_t fsm1 : 1; + uint8_t fsm2 : 1; + uint8_t fsm3 : 1; + uint8_t fsm4 : 1; + uint8_t fsm5 : 1; + uint8_t fsm6 : 1; + uint8_t fsm7 : 1; + uint8_t fsm8 : 1; + uint8_t mlc1 : 1; + uint8_t mlc2 : 1; + uint8_t mlc3 : 1; + uint8_t mlc4 : 1; +} st1vafe6ax_pin_int_route_t; +int32_t st1vafe6ax_pin_int1_route_set(const stmdev_ctx_t *ctx, + st1vafe6ax_pin_int_route_t val); +int32_t st1vafe6ax_pin_int1_route_get(const stmdev_ctx_t *ctx, + st1vafe6ax_pin_int_route_t *val); +int32_t st1vafe6ax_pin_int2_route_set(const stmdev_ctx_t *ctx, + st1vafe6ax_pin_int_route_t val); +int32_t st1vafe6ax_pin_int2_route_get(const stmdev_ctx_t *ctx, + st1vafe6ax_pin_int_route_t *val); + +int32_t st1vafe6ax_pin_int_en_when_i2c_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe6ax_pin_int_en_when_i2c_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ST1VAFE6AX_ALL_INT_PULSED = 0x0, + ST1VAFE6AX_BASE_LATCHED_EMB_PULSED = 0x1, + ST1VAFE6AX_BASE_PULSED_EMB_LATCHED = 0x2, + ST1VAFE6AX_ALL_INT_LATCHED = 0x3, +} st1vafe6ax_int_notification_t; +int32_t st1vafe6ax_int_notification_set(const stmdev_ctx_t *ctx, + st1vafe6ax_int_notification_t val); +int32_t st1vafe6ax_int_notification_get(const stmdev_ctx_t *ctx, + st1vafe6ax_int_notification_t *val); + +typedef enum +{ + ST1VAFE6AX_XL_AND_GY_NOT_AFFECTED = 0x0, + ST1VAFE6AX_XL_LOW_POWER_GY_NOT_AFFECTED = 0x1, + ST1VAFE6AX_XL_LOW_POWER_GY_SLEEP = 0x2, + ST1VAFE6AX_XL_LOW_POWER_GY_POWER_DOWN = 0x3, +} st1vafe6ax_act_mode_t; +int32_t st1vafe6ax_act_mode_set(const stmdev_ctx_t *ctx, st1vafe6ax_act_mode_t val); +int32_t st1vafe6ax_act_mode_get(const stmdev_ctx_t *ctx, + st1vafe6ax_act_mode_t *val); + +typedef enum +{ + ST1VAFE6AX_SLEEP_TO_ACT_AT_1ST_SAMPLE = 0x0, + ST1VAFE6AX_SLEEP_TO_ACT_AT_2ND_SAMPLE = 0x1, + ST1VAFE6AX_SLEEP_TO_ACT_AT_3RD_SAMPLE = 0x2, + ST1VAFE6AX_SLEEP_TO_ACT_AT_4th_SAMPLE = 0x3, +} st1vafe6ax_act_from_sleep_to_act_dur_t; +int32_t st1vafe6ax_act_from_sleep_to_act_dur_set(const stmdev_ctx_t *ctx, + st1vafe6ax_act_from_sleep_to_act_dur_t val); +int32_t st1vafe6ax_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx, + st1vafe6ax_act_from_sleep_to_act_dur_t *val); + +typedef enum +{ + ST1VAFE6AX_1Hz875 = 0x0, + ST1VAFE6AX_15Hz = 0x1, + ST1VAFE6AX_30Hz = 0x2, + ST1VAFE6AX_60Hz = 0x3, +} st1vafe6ax_act_sleep_xl_odr_t; +int32_t st1vafe6ax_act_sleep_xl_odr_set(const stmdev_ctx_t *ctx, + st1vafe6ax_act_sleep_xl_odr_t val); +int32_t st1vafe6ax_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx, + st1vafe6ax_act_sleep_xl_odr_t *val); + +typedef struct +{ + uint32_t wk_ths_mg; + uint32_t inact_ths_mg; +} st1vafe6ax_act_thresholds_t; +int32_t st1vafe6ax_act_thresholds_set(const stmdev_ctx_t *ctx, + st1vafe6ax_act_thresholds_t val); +int32_t st1vafe6ax_act_thresholds_get(const stmdev_ctx_t *ctx, + st1vafe6ax_act_thresholds_t *val); + +typedef struct +{ + uint8_t shock : 2; + uint8_t quiet : 4; +} st1vafe6ax_act_wkup_time_windows_t; +int32_t st1vafe6ax_act_wkup_time_windows_set(const stmdev_ctx_t *ctx, + st1vafe6ax_act_wkup_time_windows_t val); +int32_t st1vafe6ax_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, + st1vafe6ax_act_wkup_time_windows_t *val); + +typedef struct +{ + uint8_t tap_x_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_z_en : 1; +} st1vafe6ax_tap_detection_t; +int32_t st1vafe6ax_tap_detection_set(const stmdev_ctx_t *ctx, + st1vafe6ax_tap_detection_t val); +int32_t st1vafe6ax_tap_detection_get(const stmdev_ctx_t *ctx, + st1vafe6ax_tap_detection_t *val); + +typedef struct +{ + uint8_t x : 1; + uint8_t y : 1; + uint8_t z : 1; +} st1vafe6ax_tap_thresholds_t; +int32_t st1vafe6ax_tap_thresholds_set(const stmdev_ctx_t *ctx, + st1vafe6ax_tap_thresholds_t val); +int32_t st1vafe6ax_tap_thresholds_get(const stmdev_ctx_t *ctx, + st1vafe6ax_tap_thresholds_t *val); + + +typedef enum +{ + ST1VAFE6AX_XYZ = 0x3, + ST1VAFE6AX_YXZ = 0x5, + ST1VAFE6AX_XZY = 0x6, + ST1VAFE6AX_ZYX = 0x0, + ST1VAFE6AX_YZX = 0x1, + ST1VAFE6AX_ZXY = 0x2, +} st1vafe6ax_tap_axis_priority_t; +int32_t st1vafe6ax_tap_axis_priority_set(const stmdev_ctx_t *ctx, + st1vafe6ax_tap_axis_priority_t val); +int32_t st1vafe6ax_tap_axis_priority_get(const stmdev_ctx_t *ctx, + st1vafe6ax_tap_axis_priority_t *val); + +typedef struct +{ + uint8_t shock : 1; + uint8_t quiet : 1; + uint8_t tap_gap : 1; +} st1vafe6ax_tap_time_windows_t; +int32_t st1vafe6ax_tap_time_windows_set(const stmdev_ctx_t *ctx, + st1vafe6ax_tap_time_windows_t val); +int32_t st1vafe6ax_tap_time_windows_get(const stmdev_ctx_t *ctx, + st1vafe6ax_tap_time_windows_t *val); + +typedef enum +{ + ST1VAFE6AX_ONLY_SINGLE = 0x0, + ST1VAFE6AX_BOTH_SINGLE_DOUBLE = 0x1, +} st1vafe6ax_tap_mode_t; +int32_t st1vafe6ax_tap_mode_set(const stmdev_ctx_t *ctx, st1vafe6ax_tap_mode_t val); +int32_t st1vafe6ax_tap_mode_get(const stmdev_ctx_t *ctx, + st1vafe6ax_tap_mode_t *val); + +typedef enum +{ + ST1VAFE6AX_DEG_80 = 0x0, + ST1VAFE6AX_DEG_70 = 0x1, + ST1VAFE6AX_DEG_60 = 0x2, + ST1VAFE6AX_DEG_50 = 0x3, +} st1vafe6ax_6d_threshold_t; +int32_t st1vafe6ax_6d_threshold_set(const stmdev_ctx_t *ctx, + st1vafe6ax_6d_threshold_t val); +int32_t st1vafe6ax_6d_threshold_get(const stmdev_ctx_t *ctx, + st1vafe6ax_6d_threshold_t *val); + +int32_t st1vafe6ax_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe6ax_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ST1VAFE6AX_156_mg = 0x0, + ST1VAFE6AX_219_mg = 0x1, + ST1VAFE6AX_250_mg = 0x2, + ST1VAFE6AX_312_mg = 0x3, + ST1VAFE6AX_344_mg = 0x4, + ST1VAFE6AX_406_mg = 0x5, + ST1VAFE6AX_469_mg = 0x6, + ST1VAFE6AX_500_mg = 0x7, +} st1vafe6ax_ff_thresholds_t; +int32_t st1vafe6ax_ff_thresholds_set(const stmdev_ctx_t *ctx, + st1vafe6ax_ff_thresholds_t val); +int32_t st1vafe6ax_ff_thresholds_get(const stmdev_ctx_t *ctx, + st1vafe6ax_ff_thresholds_t *val); + +int32_t st1vafe6ax_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe6ax_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t st1vafe6ax_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe6ax_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ST1VAFE6AX_CMP_DISABLE = 0x0, + ST1VAFE6AX_CMP_8_TO_1 = 0x1, + ST1VAFE6AX_CMP_16_TO_1 = 0x2, + ST1VAFE6AX_CMP_32_TO_1 = 0x3, +} st1vafe6ax_fifo_compress_algo_t; +int32_t st1vafe6ax_fifo_compress_algo_set(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_compress_algo_t val); +int32_t st1vafe6ax_fifo_compress_algo_get(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_compress_algo_t *val); + +int32_t st1vafe6ax_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, + uint8_t val); +int32_t st1vafe6ax_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t st1vafe6ax_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, + uint8_t val); +int32_t st1vafe6ax_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t st1vafe6ax_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe6ax_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ST1VAFE6AX_XL_NOT_BATCHED = 0x0, + ST1VAFE6AX_XL_BATCHED_AT_1Hz875 = 0x1, + ST1VAFE6AX_XL_BATCHED_AT_7Hz5 = 0x2, + ST1VAFE6AX_XL_BATCHED_AT_15Hz = 0x3, + ST1VAFE6AX_XL_BATCHED_AT_30Hz = 0x4, + ST1VAFE6AX_XL_BATCHED_AT_60Hz = 0x5, + ST1VAFE6AX_XL_BATCHED_AT_120Hz = 0x6, + ST1VAFE6AX_XL_BATCHED_AT_240Hz = 0x7, + ST1VAFE6AX_XL_BATCHED_AT_480Hz = 0x8, + ST1VAFE6AX_XL_BATCHED_AT_960Hz = 0x9, + ST1VAFE6AX_XL_BATCHED_AT_1920Hz = 0xA, + ST1VAFE6AX_XL_BATCHED_AT_3840Hz = 0xB, +} st1vafe6ax_fifo_xl_batch_t; +int32_t st1vafe6ax_fifo_xl_batch_set(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_xl_batch_t val); +int32_t st1vafe6ax_fifo_xl_batch_get(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_xl_batch_t *val); + +typedef enum +{ + ST1VAFE6AX_GY_NOT_BATCHED = 0x0, + ST1VAFE6AX_GY_BATCHED_AT_1Hz875 = 0x1, + ST1VAFE6AX_GY_BATCHED_AT_7Hz5 = 0x2, + ST1VAFE6AX_GY_BATCHED_AT_15Hz = 0x3, + ST1VAFE6AX_GY_BATCHED_AT_30Hz = 0x4, + ST1VAFE6AX_GY_BATCHED_AT_60Hz = 0x5, + ST1VAFE6AX_GY_BATCHED_AT_120Hz = 0x6, + ST1VAFE6AX_GY_BATCHED_AT_240Hz = 0x7, + ST1VAFE6AX_GY_BATCHED_AT_480Hz = 0x8, + ST1VAFE6AX_GY_BATCHED_AT_960Hz = 0x9, + ST1VAFE6AX_GY_BATCHED_AT_1920Hz = 0xa, + ST1VAFE6AX_GY_BATCHED_AT_3840Hz = 0xb, +} st1vafe6ax_fifo_gy_batch_t; +int32_t st1vafe6ax_fifo_gy_batch_set(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_gy_batch_t val); +int32_t st1vafe6ax_fifo_gy_batch_get(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_gy_batch_t *val); + +typedef enum +{ + ST1VAFE6AX_BYPASS_MODE = 0x0, + ST1VAFE6AX_FIFO_MODE = 0x1, + ST1VAFE6AX_STREAM_WTM_TO_FULL_MODE = 0x2, + ST1VAFE6AX_STREAM_TO_FIFO_MODE = 0x3, + ST1VAFE6AX_BYPASS_TO_STREAM_MODE = 0x4, + ST1VAFE6AX_STREAM_MODE = 0x6, + ST1VAFE6AX_BYPASS_TO_FIFO_MODE = 0x7, +} st1vafe6ax_fifo_mode_t; +int32_t st1vafe6ax_fifo_mode_set(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_mode_t val); +int32_t st1vafe6ax_fifo_mode_get(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_mode_t *val); + +typedef enum +{ + ST1VAFE6AX_TEMP_NOT_BATCHED = 0x0, + ST1VAFE6AX_TEMP_BATCHED_AT_1Hz875 = 0x1, + ST1VAFE6AX_TEMP_BATCHED_AT_15Hz = 0x2, + ST1VAFE6AX_TEMP_BATCHED_AT_60Hz = 0x3, +} st1vafe6ax_fifo_temp_batch_t; +int32_t st1vafe6ax_fifo_temp_batch_set(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_temp_batch_t val); +int32_t st1vafe6ax_fifo_temp_batch_get(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_temp_batch_t *val); + +typedef enum +{ + ST1VAFE6AX_TMSTMP_NOT_BATCHED = 0x0, + ST1VAFE6AX_TMSTMP_DEC_1 = 0x1, + ST1VAFE6AX_TMSTMP_DEC_8 = 0x2, + ST1VAFE6AX_TMSTMP_DEC_32 = 0x3, +} st1vafe6ax_fifo_timestamp_batch_t; +int32_t st1vafe6ax_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_timestamp_batch_t val); +int32_t st1vafe6ax_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_timestamp_batch_t *val); + +int32_t st1vafe6ax_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx, + uint16_t val); +int32_t st1vafe6ax_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx, + uint16_t *val); + +int32_t st1vafe6ax_fifo_batch_ah_bio_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe6ax_fifo_batch_ah_bio_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum +{ + ST1VAFE6AX_XL_BATCH_EVENT = 0x0, + ST1VAFE6AX_GY_BATCH_EVENT = 0x1, +} st1vafe6ax_fifo_batch_cnt_event_t; +int32_t st1vafe6ax_fifo_batch_cnt_event_set(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_batch_cnt_event_t val); +int32_t st1vafe6ax_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_batch_cnt_event_t *val); + +typedef struct +{ + uint8_t game_rotation : 1; + uint8_t gravity : 1; + uint8_t gbias : 1; +} st1vafe6ax_fifo_sflp_raw_t; +int32_t st1vafe6ax_fifo_sflp_batch_set(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_sflp_raw_t val); +int32_t st1vafe6ax_fifo_sflp_batch_get(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_sflp_raw_t *val); + +typedef struct +{ + uint16_t fifo_level : 9; + uint8_t fifo_bdr : 1; + uint8_t fifo_full : 1; + uint8_t fifo_ovr : 1; + uint8_t fifo_th : 1; +} st1vafe6ax_fifo_status_t; + +int32_t st1vafe6ax_fifo_status_get(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_status_t *val); + +typedef struct +{ + enum + { + ST1VAFE6AX_FIFO_EMPTY = 0x0, + ST1VAFE6AX_GY_NC_TAG = 0x1, + ST1VAFE6AX_XL_NC_TAG = 0x2, + ST1VAFE6AX_TEMPERATURE_TAG = 0x3, + ST1VAFE6AX_TIMESTAMP_TAG = 0x4, + ST1VAFE6AX_CFG_CHANGE_TAG = 0x5, + ST1VAFE6AX_XL_NC_T_2_TAG = 0x6, + ST1VAFE6AX_XL_NC_T_1_TAG = 0x7, + ST1VAFE6AX_XL_2XC_TAG = 0x8, + ST1VAFE6AX_XL_3XC_TAG = 0x9, + ST1VAFE6AX_GY_NC_T_2_TAG = 0xA, + ST1VAFE6AX_GY_NC_T_1_TAG = 0xB, + ST1VAFE6AX_GY_2XC_TAG = 0xC, + ST1VAFE6AX_GY_3XC_TAG = 0xD, + ST1VAFE6AX_STEP_COUNTER_TAG = 0x12, + ST1VAFE6AX_SFLP_GAME_ROTATION_VECTOR_TAG = 0x13, + ST1VAFE6AX_SFLP_GYROSCOPE_BIAS_TAG = 0x16, + ST1VAFE6AX_SFLP_GRAVITY_VECTOR_TAG = 0x17, + ST1VAFE6AX_MLC_RESULT_TAG = 0x1A, + ST1VAFE6AX_MLC_FILTER = 0x1B, + ST1VAFE6AX_MLC_FEATURE = 0x1C, + ST1VAFE6AX_XL_DUAL_CORE = 0x1D, + ST1VAFE6AX_AH_VAFE = 0x1F, + } tag; + uint8_t cnt; + uint8_t data[6]; +} st1vafe6ax_fifo_out_raw_t; +int32_t st1vafe6ax_fifo_out_raw_get(const stmdev_ctx_t *ctx, + st1vafe6ax_fifo_out_raw_t *val); + +int32_t st1vafe6ax_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe6ax_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t st1vafe6ax_fifo_mlc_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe6ax_fifo_mlc_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t st1vafe6ax_fifo_mlc_filt_batch_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe6ax_fifo_mlc_filt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + uint8_t step_counter_enable : 1; + uint8_t false_step_rej : 1; +} st1vafe6ax_stpcnt_mode_t; +int32_t st1vafe6ax_stpcnt_mode_set(const stmdev_ctx_t *ctx, + st1vafe6ax_stpcnt_mode_t val); +int32_t st1vafe6ax_stpcnt_mode_get(const stmdev_ctx_t *ctx, + st1vafe6ax_stpcnt_mode_t *val); + +int32_t st1vafe6ax_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t st1vafe6ax_stpcnt_rst_step_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe6ax_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t st1vafe6ax_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe6ax_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t st1vafe6ax_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t st1vafe6ax_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t st1vafe6ax_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe6ax_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t st1vafe6ax_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe6ax_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t st1vafe6ax_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t st1vafe6ax_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint16_t *val); + +typedef struct +{ + float_t gbias_x; /* dps */ + float_t gbias_y; /* dps */ + float_t gbias_z; /* dps */ +} st1vafe6ax_sflp_gbias_t; +int32_t st1vafe6ax_sflp_game_gbias_set(const stmdev_ctx_t *ctx, + st1vafe6ax_sflp_gbias_t *val); + +int32_t st1vafe6ax_sflp_configure(const stmdev_ctx_t *ctx); + +typedef enum +{ + ST1VAFE6AX_SFLP_15Hz = 0x0, + ST1VAFE6AX_SFLP_30Hz = 0x1, + ST1VAFE6AX_SFLP_60Hz = 0x2, + ST1VAFE6AX_SFLP_120Hz = 0x3, + ST1VAFE6AX_SFLP_240Hz = 0x4, + ST1VAFE6AX_SFLP_480Hz = 0x5, +} st1vafe6ax_sflp_data_rate_t; +int32_t st1vafe6ax_sflp_data_rate_set(const stmdev_ctx_t *ctx, + st1vafe6ax_sflp_data_rate_t val); +int32_t st1vafe6ax_sflp_data_rate_get(const stmdev_ctx_t *ctx, + st1vafe6ax_sflp_data_rate_t *val); + +typedef enum +{ + ST1VAFE6AX_PROTECT_CTRL_REGS = 0x0, + ST1VAFE6AX_WRITE_CTRL_REG = 0x1, +} st1vafe6ax_fsm_permission_t; +int32_t st1vafe6ax_fsm_permission_set(const stmdev_ctx_t *ctx, + st1vafe6ax_fsm_permission_t val); +int32_t st1vafe6ax_fsm_permission_get(const stmdev_ctx_t *ctx, + st1vafe6ax_fsm_permission_t *val); + +typedef enum +{ + ST1VAFE6AX_STD_IF_CONTROL = 0x0, + ST1VAFE6AX_FSM_CONTROL = 0x1, +} st1vafe6ax_fsm_permission_status_t; +int32_t st1vafe6ax_fsm_permission_status(const stmdev_ctx_t *ctx, + st1vafe6ax_fsm_permission_status_t *val); + +typedef struct +{ + uint8_t fsm1_en : 1; + uint8_t fsm2_en : 1; + uint8_t fsm3_en : 1; + uint8_t fsm4_en : 1; + uint8_t fsm5_en : 1; + uint8_t fsm6_en : 1; + uint8_t fsm7_en : 1; + uint8_t fsm8_en : 1; +} st1vafe6ax_fsm_mode_t; +int32_t st1vafe6ax_fsm_mode_set(const stmdev_ctx_t *ctx, st1vafe6ax_fsm_mode_t val); +int32_t st1vafe6ax_fsm_mode_get(const stmdev_ctx_t *ctx, + st1vafe6ax_fsm_mode_t *val); + +int32_t st1vafe6ax_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t st1vafe6ax_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); + +typedef struct +{ + uint8_t fsm_outs1; + uint8_t fsm_outs2; + uint8_t fsm_outs3; + uint8_t fsm_outs4; + uint8_t fsm_outs5; + uint8_t fsm_outs6; + uint8_t fsm_outs7; + uint8_t fsm_outs8; +} st1vafe6ax_fsm_out_t; +int32_t st1vafe6ax_fsm_out_get(const stmdev_ctx_t *ctx, st1vafe6ax_fsm_out_t *val); + +typedef enum +{ + ST1VAFE6AX_FSM_15Hz = 0x0, + ST1VAFE6AX_FSM_30Hz = 0x1, + ST1VAFE6AX_FSM_60Hz = 0x2, + ST1VAFE6AX_FSM_120Hz = 0x3, + ST1VAFE6AX_FSM_240Hz = 0x4, + ST1VAFE6AX_FSM_480Hz = 0x5, + ST1VAFE6AX_FSM_960Hz = 0x6, +} st1vafe6ax_fsm_data_rate_t; +int32_t st1vafe6ax_fsm_data_rate_set(const stmdev_ctx_t *ctx, + st1vafe6ax_fsm_data_rate_t val); +int32_t st1vafe6ax_fsm_data_rate_get(const stmdev_ctx_t *ctx, + st1vafe6ax_fsm_data_rate_t *val); + +int32_t st1vafe6ax_fsm_long_cnt_timeout_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t st1vafe6ax_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t st1vafe6ax_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe6ax_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val); + +int32_t st1vafe6ax_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t st1vafe6ax_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); + +typedef enum +{ + ST1VAFE6AX_MLC_OFF = 0x0, + ST1VAFE6AX_MLC_ON = 0x1, + ST1VAFE6AX_MLC_ON_BEFORE_FSM = 0x2, +} st1vafe6ax_mlc_mode_t; +int32_t st1vafe6ax_mlc_set(const stmdev_ctx_t *ctx, st1vafe6ax_mlc_mode_t val); +int32_t st1vafe6ax_mlc_get(const stmdev_ctx_t *ctx, st1vafe6ax_mlc_mode_t *val); + +typedef enum +{ + ST1VAFE6AX_MLC_15Hz = 0x0, + ST1VAFE6AX_MLC_30Hz = 0x1, + ST1VAFE6AX_MLC_60Hz = 0x2, + ST1VAFE6AX_MLC_120Hz = 0x3, + ST1VAFE6AX_MLC_240Hz = 0x4, + ST1VAFE6AX_MLC_480Hz = 0x5, + ST1VAFE6AX_MLC_960Hz = 0x6, +} st1vafe6ax_mlc_data_rate_t; +int32_t st1vafe6ax_mlc_data_rate_set(const stmdev_ctx_t *ctx, + st1vafe6ax_mlc_data_rate_t val); +int32_t st1vafe6ax_mlc_data_rate_get(const stmdev_ctx_t *ctx, + st1vafe6ax_mlc_data_rate_t *val); + +typedef struct +{ + uint8_t mlc1_src; + uint8_t mlc2_src; + uint8_t mlc3_src; + uint8_t mlc4_src; +} st1vafe6ax_mlc_out_t; +int32_t st1vafe6ax_mlc_out_get(const stmdev_ctx_t *ctx, st1vafe6ax_mlc_out_t *val); + +int32_t st1vafe6ax_mlc_bio_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t st1vafe6ax_mlc_bio_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); + +int32_t st1vafe6ax_xl_offset_on_out_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t st1vafe6ax_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct +{ + float_t z_mg; + float_t y_mg; + float_t x_mg; +} st1vafe6ax_xl_offset_mg_t; +int32_t st1vafe6ax_xl_offset_mg_set(const stmdev_ctx_t *ctx, + st1vafe6ax_xl_offset_mg_t val); +int32_t st1vafe6ax_xl_offset_mg_get(const stmdev_ctx_t *ctx, + st1vafe6ax_xl_offset_mg_t *val); + +typedef struct +{ + uint8_t ah_bio1_en : 1; + uint8_t ah_bio2_en : 1; + uint8_t swaps : 1; +} st1vafe6ax_ah_bio_mode_t; +int32_t st1vafe6ax_ah_bio_mode_set(const stmdev_ctx_t *ctx, + st1vafe6ax_ah_bio_mode_t val); +int32_t st1vafe6ax_ah_bio_mode_get(const stmdev_ctx_t *ctx, + st1vafe6ax_ah_bio_mode_t *val); + +typedef enum +{ + ST1VAFE6AX_2400MOhm = 0x0, + ST1VAFE6AX_730MOhm = 0x1, + ST1VAFE6AX_300MOhm = 0x2, + ST1VAFE6AX_255MOhm = 0x3, +} st1vafe6ax_ah_bio_zin_t; +int32_t st1vafe6ax_ah_bio_zin_set(const stmdev_ctx_t *ctx, + st1vafe6ax_ah_bio_zin_t val); +int32_t st1vafe6ax_ah_bio_zin_get(const stmdev_ctx_t *ctx, + st1vafe6ax_ah_bio_zin_t *val); + +int32_t st1vafe6ax_fsm_bio_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t st1vafe6ax_fsm_bio_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); + +typedef enum +{ + ST1VAFE6AX_SW_RST_DYN_ADDRESS_RST = 0x0, + ST1VAFE6AX_I3C_GLOBAL_RST = 0x1, +} st1vafe6ax_i3c_reset_mode_t; +int32_t st1vafe6ax_i3c_reset_mode_set(const stmdev_ctx_t *ctx, + st1vafe6ax_i3c_reset_mode_t val); +int32_t st1vafe6ax_i3c_reset_mode_get(const stmdev_ctx_t *ctx, + st1vafe6ax_i3c_reset_mode_t *val); + +/** + * @} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /*ST1VAFE6AX_DRIVER_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/sensor/stmemsc/sths34pf80_STdC/driver/sths34pf80_reg.c b/sensor/stmemsc/sths34pf80_STdC/driver/sths34pf80_reg.c index 767d238f..79a2e4a2 100644 --- a/sensor/stmemsc/sths34pf80_STdC/driver/sths34pf80_reg.c +++ b/sensor/stmemsc/sths34pf80_STdC/driver/sths34pf80_reg.c @@ -19,6 +19,25 @@ #include "sths34pf80_reg.h" +/* + * Prototypes of routines used only throughout this driver and not exported + * outside as APIs + */ +typedef struct +{ + uint8_t int_pulsed : 1; + uint8_t comp_type : 1; + uint8_t sel_abs : 1; +} sths34pf80_algo_config_t; + +static int32_t sths34pf80_reset_algo_bit_set(const stmdev_ctx_t *ctx); +static int32_t sths34pf80_algo_config_get(const stmdev_ctx_t *ctx, sths34pf80_algo_config_t *val); +static int32_t sths34pf80_algo_config_set(const stmdev_ctx_t *ctx, sths34pf80_algo_config_t val); +static int32_t sths34pf80_safe_power_down(const stmdev_ctx_t *ctx, sths34pf80_ctrl1_t *ctrl1); +static int32_t sths34pf80_odr_safe_set(const stmdev_ctx_t *ctx, + sths34pf80_ctrl1_t *ctrl1, + uint8_t odr_new); + /** * @defgroup STHS34PF80 * @brief This file provides a set of functions needed to drive the @@ -50,12 +69,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak sths34pf80_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak sths34pf80_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -71,12 +95,17 @@ int32_t __weak sths34pf80_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak sths34pf80_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak sths34pf80_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -101,7 +130,7 @@ int32_t __weak sths34pf80_write_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_device_id_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t sths34pf80_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -118,7 +147,7 @@ int32_t sths34pf80_device_id_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_avg_tobject_num_set(stmdev_ctx_t *ctx, sths34pf80_avg_tobject_num_t val) +int32_t sths34pf80_avg_tobject_num_set(const stmdev_ctx_t *ctx, sths34pf80_avg_tobject_num_t val) { sths34pf80_avg_trim_t avg_trim; int32_t ret; @@ -142,7 +171,7 @@ int32_t sths34pf80_avg_tobject_num_set(stmdev_ctx_t *ctx, sths34pf80_avg_tobject * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_avg_tobject_num_get(stmdev_ctx_t *ctx, sths34pf80_avg_tobject_num_t *val) +int32_t sths34pf80_avg_tobject_num_get(const stmdev_ctx_t *ctx, sths34pf80_avg_tobject_num_t *val) { sths34pf80_avg_trim_t avg_trim; int32_t ret; @@ -198,7 +227,7 @@ int32_t sths34pf80_avg_tobject_num_get(stmdev_ctx_t *ctx, sths34pf80_avg_tobject * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_avg_tambient_num_set(stmdev_ctx_t *ctx, sths34pf80_avg_tambient_num_t val) +int32_t sths34pf80_avg_tambient_num_set(const stmdev_ctx_t *ctx, sths34pf80_avg_tambient_num_t val) { sths34pf80_avg_trim_t avg_trim; int32_t ret; @@ -222,7 +251,7 @@ int32_t sths34pf80_avg_tambient_num_set(stmdev_ctx_t *ctx, sths34pf80_avg_tambie * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_avg_tambient_num_get(stmdev_ctx_t *ctx, sths34pf80_avg_tambient_num_t *val) +int32_t sths34pf80_avg_tambient_num_get(const stmdev_ctx_t *ctx, sths34pf80_avg_tambient_num_t *val) { sths34pf80_avg_trim_t avg_trim; int32_t ret; @@ -262,7 +291,7 @@ int32_t sths34pf80_avg_tambient_num_get(stmdev_ctx_t *ctx, sths34pf80_avg_tambie * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_gain_mode_set(stmdev_ctx_t *ctx, sths34pf80_gain_mode_t val) +int32_t sths34pf80_gain_mode_set(const stmdev_ctx_t *ctx, sths34pf80_gain_mode_t val) { sths34pf80_ctrl0_t ctrl0; int32_t ret; @@ -286,7 +315,7 @@ int32_t sths34pf80_gain_mode_set(stmdev_ctx_t *ctx, sths34pf80_gain_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_gain_mode_get(stmdev_ctx_t *ctx, sths34pf80_gain_mode_t *val) +int32_t sths34pf80_gain_mode_get(const stmdev_ctx_t *ctx, sths34pf80_gain_mode_t *val) { sths34pf80_ctrl0_t ctrl0; int32_t ret; @@ -320,14 +349,14 @@ int32_t sths34pf80_gain_mode_get(stmdev_ctx_t *ctx, sths34pf80_gain_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_tmos_sensitivity_set(stmdev_ctx_t *ctx, uint16_t *val) +int32_t sths34pf80_tobject_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t *val) { sths34pf80_sens_data_t data; int32_t ret; data.sens = (*val >= 2048U) ? - (*val - 2048U + 8U) / 16U : - (*val - 2048U - 8U) / 16U; + (*val - 2048U + 8U) / 16U : + (*val - 2048U - 8U) / 16U; ret = sths34pf80_write_reg(ctx, STHS34PF80_SENS_DATA, (uint8_t *)&data, 1); *val = (int8_t)data.sens * 16U + 2048U; @@ -342,7 +371,7 @@ int32_t sths34pf80_tmos_sensitivity_set(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_tmos_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t sths34pf80_tobject_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val) { sths34pf80_sens_data_t data; int32_t ret; @@ -354,56 +383,81 @@ int32_t sths34pf80_tmos_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val) } /** - * @brief Enter to/Exit from power-down in a safe way + * @brief Enter to power-down in a safe way * * @param ctx read / write interface definitions - * @param ctrl1 Value of CTRL1 register - * @param odr_new Value of new odr to be set + * @param ctrl1 Pointer to CTRL1 register * @retval interface status (MANDATORY: return 0 -> no Error) * */ -static int32_t sths34pf80_tmos_odr_check_safe_set(stmdev_ctx_t *ctx, - sths34pf80_ctrl1_t ctrl1, - uint8_t odr_new) +static int32_t sths34pf80_safe_power_down(const stmdev_ctx_t *ctx, sths34pf80_ctrl1_t *ctrl1) { sths34pf80_func_status_t func_status; - sths34pf80_tmos_drdy_status_t status; - int32_t ret = 0; + sths34pf80_drdy_status_t status; + int32_t ret; - if (odr_new > 0U) { - /* - * Do a clean reset algo procedure everytime odr is changed to an - * operative state. - */ - ctrl1.odr = 0; - ret = sths34pf80_write_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); + /* if sensor is already in power-down then do nothing */ + if (ctrl1->odr == 0U) + { + return 0; + } - ret += sths34pf80_algo_reset(ctx); - } else { - /* if we need to go to power-down from an operative state - * perform the safe power-down. - */ - if ((uint8_t)ctrl1.odr > 0U) { - /* reset the DRDY bit */ - ret = sths34pf80_read_reg(ctx, STHS34PF80_FUNC_STATUS, (uint8_t *)&func_status, 1); + /* reset the DRDY bit */ + ret = sths34pf80_read_reg(ctx, STHS34PF80_FUNC_STATUS, (uint8_t *)&func_status, 1); - /* wait DRDY bit go to '1' */ - do { - ret += sths34pf80_tmos_drdy_status_get(ctx, &status); + /* wait DRDY bit go to '1'. Maximum wait may be up to 4 sec (0.25 Hz) */ + uint16_t retry = 0U; + do + { + ret += sths34pf80_drdy_status_get(ctx, &status); + ctx->mdelay(1); + } while (status.drdy == 0U && retry++ < 4000U); - } while (status.drdy != 0U); + if (ret != 0 || retry >= 4000U) + { + return -1; + }; - /* set ODR to 0 */ - ctrl1.odr = 0; - ret += sths34pf80_write_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); + /* perform power-down */ + ctrl1->odr = 0U; + ret += sths34pf80_write_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)ctrl1, 1); - /* reset the DRDY bit */ - ret += sths34pf80_read_reg(ctx, STHS34PF80_FUNC_STATUS, (uint8_t *)&func_status, 1); - } - } + /* reset the DRDY bit */ + ret += sths34pf80_read_reg(ctx, STHS34PF80_FUNC_STATUS, (uint8_t *)&func_status, 1); - ctrl1.odr = (odr_new & 0xfU); - ret += sths34pf80_write_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); + return ret; +} + +/** + * @brief Change odr in a safe way + * + * @param ctx read / write interface definitions + * @param ctrl1 Pointer to CTRL1 register + * @param odr_new Value of new odr to be set + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +static int32_t sths34pf80_odr_safe_set(const stmdev_ctx_t *ctx, + sths34pf80_ctrl1_t *ctrl1, + uint8_t odr_new) +{ + int32_t ret; + + /* perform power-down transition in a safe way. */ + ret = sths34pf80_safe_power_down(ctx, ctrl1); + + if (odr_new > 0U) + { + /* + * Do a clean reset algo procedure everytime odr is changed to an + * operative state. + */ + ret += sths34pf80_reset_algo_bit_set(ctx); + + /* set new odr */ + ctrl1->odr = (odr_new & 0xfU); + ret += sths34pf80_write_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)ctrl1, 1); + } return ret; } @@ -412,15 +466,15 @@ static int32_t sths34pf80_tmos_odr_check_safe_set(stmdev_ctx_t *ctx, * @brief Selects the tmos odr.[set] * * @param ctx read / write interface definitions - * @param val TMOS_ODR_OFF, TMOS_ODR_AT_0Hz25, TMOS_ODR_AT_0Hz50, TMOS_ODR_1Hz, TMOS_ODR_2Hz, TMOS_ODR_4Hz, TMOS_ODR_8Hz, TMOS_ODR_15Hz, TMOS_ODR_30Hz, + * @param val ODR_OFF, ODR_AT_0Hz25, ODR_AT_0Hz50, ODR_1Hz, ODR_2Hz, ODR_4Hz, ODR_8Hz, ODR_15Hz, ODR_30Hz, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_tmos_odr_set(stmdev_ctx_t *ctx, sths34pf80_tmos_odr_t val) +int32_t sths34pf80_odr_set(const stmdev_ctx_t *ctx, sths34pf80_odr_t val) { sths34pf80_ctrl1_t ctrl1; sths34pf80_avg_trim_t avg_trim; - sths34pf80_tmos_odr_t max_odr = STHS34PF80_TMOS_ODR_AT_30Hz; + sths34pf80_odr_t max_odr = STHS34PF80_ODR_AT_30Hz; int32_t ret; ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); @@ -429,28 +483,28 @@ int32_t sths34pf80_tmos_odr_set(stmdev_ctx_t *ctx, sths34pf80_tmos_odr_t val) { ret = sths34pf80_read_reg(ctx, STHS34PF80_AVG_TRIM, (uint8_t *)&avg_trim, 1); - switch(avg_trim.avg_tmos) + switch (avg_trim.avg_tmos) { default: case STHS34PF80_AVG_TMOS_2: case STHS34PF80_AVG_TMOS_8: case STHS34PF80_AVG_TMOS_32: - max_odr = STHS34PF80_TMOS_ODR_AT_30Hz; + max_odr = STHS34PF80_ODR_AT_30Hz; break; case STHS34PF80_AVG_TMOS_128: - max_odr = STHS34PF80_TMOS_ODR_AT_8Hz; + max_odr = STHS34PF80_ODR_AT_8Hz; break; case STHS34PF80_AVG_TMOS_256: - max_odr = STHS34PF80_TMOS_ODR_AT_4Hz; + max_odr = STHS34PF80_ODR_AT_4Hz; break; case STHS34PF80_AVG_TMOS_512: - max_odr = STHS34PF80_TMOS_ODR_AT_2Hz; + max_odr = STHS34PF80_ODR_AT_2Hz; break; case STHS34PF80_AVG_TMOS_1024: - max_odr = STHS34PF80_TMOS_ODR_AT_1Hz; + max_odr = STHS34PF80_ODR_AT_1Hz; break; case STHS34PF80_AVG_TMOS_2048: - max_odr = STHS34PF80_TMOS_ODR_AT_0Hz50; + max_odr = STHS34PF80_ODR_AT_0Hz50; break; } } @@ -462,7 +516,7 @@ int32_t sths34pf80_tmos_odr_set(stmdev_ctx_t *ctx, sths34pf80_tmos_odr_t val) return -1; } - ret = sths34pf80_tmos_odr_check_safe_set(ctx, ctrl1, (uint8_t)val); + ret = sths34pf80_odr_safe_set(ctx, &ctrl1, (uint8_t)val); } return ret; @@ -472,11 +526,11 @@ int32_t sths34pf80_tmos_odr_set(stmdev_ctx_t *ctx, sths34pf80_tmos_odr_t val) * @brief Selects the tmos odr.[get] * * @param ctx read / write interface definitions - * @param val TMOS_ODR_OFF, TMOS_ODR_AT_0Hz25, TMOS_ODR_AT_0Hz50, TMOS_ODR_1Hz, TMOS_ODR_2Hz, TMOS_ODR_4Hz, TMOS_ODR_8Hz, TMOS_ODR_15Hz, TMOS_ODR_30Hz, + * @param val ODR_OFF, ODR_AT_0Hz25, ODR_AT_0Hz50, ODR_1Hz, ODR_2Hz, ODR_4Hz, ODR_8Hz, ODR_15Hz, ODR_30Hz, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_tmos_odr_get(stmdev_ctx_t *ctx, sths34pf80_tmos_odr_t *val) +int32_t sths34pf80_odr_get(const stmdev_ctx_t *ctx, sths34pf80_odr_t *val) { sths34pf80_ctrl1_t ctrl1; int32_t ret; @@ -485,44 +539,44 @@ int32_t sths34pf80_tmos_odr_get(stmdev_ctx_t *ctx, sths34pf80_tmos_odr_t *val) switch (ctrl1.odr) { - case STHS34PF80_TMOS_ODR_OFF: - *val = STHS34PF80_TMOS_ODR_OFF; + case STHS34PF80_ODR_OFF: + *val = STHS34PF80_ODR_OFF; break; - case STHS34PF80_TMOS_ODR_AT_0Hz25: - *val = STHS34PF80_TMOS_ODR_AT_0Hz25; + case STHS34PF80_ODR_AT_0Hz25: + *val = STHS34PF80_ODR_AT_0Hz25; break; - case STHS34PF80_TMOS_ODR_AT_0Hz50: - *val = STHS34PF80_TMOS_ODR_AT_0Hz50; + case STHS34PF80_ODR_AT_0Hz50: + *val = STHS34PF80_ODR_AT_0Hz50; break; - case STHS34PF80_TMOS_ODR_AT_1Hz: - *val = STHS34PF80_TMOS_ODR_AT_1Hz; + case STHS34PF80_ODR_AT_1Hz: + *val = STHS34PF80_ODR_AT_1Hz; break; - case STHS34PF80_TMOS_ODR_AT_2Hz: - *val = STHS34PF80_TMOS_ODR_AT_2Hz; + case STHS34PF80_ODR_AT_2Hz: + *val = STHS34PF80_ODR_AT_2Hz; break; - case STHS34PF80_TMOS_ODR_AT_4Hz: - *val = STHS34PF80_TMOS_ODR_AT_4Hz; + case STHS34PF80_ODR_AT_4Hz: + *val = STHS34PF80_ODR_AT_4Hz; break; - case STHS34PF80_TMOS_ODR_AT_8Hz: - *val = STHS34PF80_TMOS_ODR_AT_8Hz; + case STHS34PF80_ODR_AT_8Hz: + *val = STHS34PF80_ODR_AT_8Hz; break; - case STHS34PF80_TMOS_ODR_AT_15Hz: - *val = STHS34PF80_TMOS_ODR_AT_15Hz; + case STHS34PF80_ODR_AT_15Hz: + *val = STHS34PF80_ODR_AT_15Hz; break; - case STHS34PF80_TMOS_ODR_AT_30Hz: - *val = STHS34PF80_TMOS_ODR_AT_30Hz; + case STHS34PF80_ODR_AT_30Hz: + *val = STHS34PF80_ODR_AT_30Hz; break; default: - *val = STHS34PF80_TMOS_ODR_OFF; + *val = STHS34PF80_ODR_OFF; break; } return ret; @@ -536,7 +590,7 @@ int32_t sths34pf80_tmos_odr_get(stmdev_ctx_t *ctx, sths34pf80_tmos_odr_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t sths34pf80_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { sths34pf80_ctrl1_t ctrl1; int32_t ret; @@ -560,7 +614,7 @@ int32_t sths34pf80_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t sths34pf80_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { sths34pf80_ctrl1_t ctrl1; int32_t ret; @@ -577,11 +631,11 @@ int32_t sths34pf80_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @brief Selects data output mode.[set] * * @param ctx read / write interface definitions - * @param val TMOS_IDLE_MODE, TMOS_ONE_SHOT, + * @param val IDLE_MODE, ONE_SHOT * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_tmos_one_shot_set(stmdev_ctx_t *ctx, sths34pf80_tmos_one_shot_t val) +int32_t sths34pf80_one_shot_set(const stmdev_ctx_t *ctx, sths34pf80_one_shot_t val) { sths34pf80_ctrl2_t ctrl2; int32_t ret; @@ -601,11 +655,11 @@ int32_t sths34pf80_tmos_one_shot_set(stmdev_ctx_t *ctx, sths34pf80_tmos_one_shot * @brief Selects data output mode.[get] * * @param ctx read / write interface definitions - * @param val TMOS_IDLE_MODE, TMOS_ONE_SHOT, + * @param val IDLE_MODE, ONE_SHOT * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_tmos_one_shot_get(stmdev_ctx_t *ctx, sths34pf80_tmos_one_shot_t *val) +int32_t sths34pf80_one_shot_get(const stmdev_ctx_t *ctx, sths34pf80_one_shot_t *val) { sths34pf80_ctrl2_t ctrl2; int32_t ret; @@ -614,16 +668,16 @@ int32_t sths34pf80_tmos_one_shot_get(stmdev_ctx_t *ctx, sths34pf80_tmos_one_shot switch (ctrl2.one_shot) { - case STHS34PF80_TMOS_IDLE_MODE: - *val = STHS34PF80_TMOS_IDLE_MODE; + case STHS34PF80_IDLE_MODE: + *val = STHS34PF80_IDLE_MODE; break; - case STHS34PF80_TMOS_ONE_SHOT: - *val = STHS34PF80_TMOS_ONE_SHOT; + case STHS34PF80_ONE_SHOT: + *val = STHS34PF80_ONE_SHOT; break; default: - *val = STHS34PF80_TMOS_IDLE_MODE; + *val = STHS34PF80_IDLE_MODE; break; } return ret; @@ -637,7 +691,7 @@ int32_t sths34pf80_tmos_one_shot_get(stmdev_ctx_t *ctx, sths34pf80_tmos_one_shot * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_mem_bank_set(stmdev_ctx_t *ctx, sths34pf80_mem_bank_t val) +int32_t sths34pf80_mem_bank_set(const stmdev_ctx_t *ctx, sths34pf80_mem_bank_t val) { sths34pf80_ctrl2_t ctrl2; int32_t ret; @@ -661,7 +715,7 @@ int32_t sths34pf80_mem_bank_set(stmdev_ctx_t *ctx, sths34pf80_mem_bank_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_mem_bank_get(stmdev_ctx_t *ctx, sths34pf80_mem_bank_t *val) +int32_t sths34pf80_mem_bank_get(const stmdev_ctx_t *ctx, sths34pf80_mem_bank_t *val) { sths34pf80_ctrl2_t ctrl2; int32_t ret; @@ -693,7 +747,7 @@ int32_t sths34pf80_mem_bank_get(stmdev_ctx_t *ctx, sths34pf80_mem_bank_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_boot_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t sths34pf80_boot_set(const stmdev_ctx_t *ctx, uint8_t val) { sths34pf80_ctrl2_t ctrl2; int32_t ret; @@ -717,7 +771,7 @@ int32_t sths34pf80_boot_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t sths34pf80_boot_get(const stmdev_ctx_t *ctx, uint8_t *val) { sths34pf80_ctrl2_t ctrl2; int32_t ret; @@ -736,7 +790,7 @@ int32_t sths34pf80_boot_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_tmos_drdy_status_get(stmdev_ctx_t *ctx, sths34pf80_tmos_drdy_status_t *val) +int32_t sths34pf80_drdy_status_get(const stmdev_ctx_t *ctx, sths34pf80_drdy_status_t *val) { sths34pf80_status_t status; int32_t ret; @@ -756,7 +810,7 @@ int32_t sths34pf80_tmos_drdy_status_get(stmdev_ctx_t *ctx, sths34pf80_tmos_drdy_ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_tmos_func_status_get(stmdev_ctx_t *ctx, sths34pf80_tmos_func_status_t *val) +int32_t sths34pf80_func_status_get(const stmdev_ctx_t *ctx, sths34pf80_func_status_t *val) { sths34pf80_func_status_t func_status; int32_t ret; @@ -778,7 +832,7 @@ int32_t sths34pf80_tmos_func_status_get(stmdev_ctx_t *ctx, sths34pf80_tmos_func_ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_tobject_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t sths34pf80_tobject_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -799,7 +853,7 @@ int32_t sths34pf80_tobject_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_tambient_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t sths34pf80_tambient_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -820,7 +874,7 @@ int32_t sths34pf80_tambient_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_tobj_comp_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t sths34pf80_tobj_comp_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -841,7 +895,7 @@ int32_t sths34pf80_tobj_comp_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_tpresence_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t sths34pf80_tpresence_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -862,7 +916,7 @@ int32_t sths34pf80_tpresence_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_tmotion_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t sths34pf80_tmotion_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -883,7 +937,7 @@ int32_t sths34pf80_tmotion_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_tamb_shock_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t sths34pf80_tamb_shock_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -915,7 +969,7 @@ int32_t sths34pf80_tamb_shock_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_lpf_m_bandwidth_set(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t val) +int32_t sths34pf80_lpf_m_bandwidth_set(const stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t val) { sths34pf80_lpf1_t lpf1; int32_t ret; @@ -939,7 +993,7 @@ int32_t sths34pf80_lpf_m_bandwidth_set(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwid * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_lpf_m_bandwidth_get(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t *val) +int32_t sths34pf80_lpf_m_bandwidth_get(const stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t *val) { sths34pf80_lpf1_t lpf1; int32_t ret; @@ -991,7 +1045,7 @@ int32_t sths34pf80_lpf_m_bandwidth_get(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwid * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_lpf_p_m_bandwidth_set(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t val) +int32_t sths34pf80_lpf_p_m_bandwidth_set(const stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t val) { sths34pf80_lpf1_t lpf1; int32_t ret; @@ -1015,7 +1069,7 @@ int32_t sths34pf80_lpf_p_m_bandwidth_set(stmdev_ctx_t *ctx, sths34pf80_lpf_bandw * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_lpf_p_m_bandwidth_get(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t *val) +int32_t sths34pf80_lpf_p_m_bandwidth_get(const stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t *val) { sths34pf80_lpf1_t lpf1; int32_t ret; @@ -1067,7 +1121,7 @@ int32_t sths34pf80_lpf_p_m_bandwidth_get(stmdev_ctx_t *ctx, sths34pf80_lpf_bandw * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_lpf_a_t_bandwidth_set(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t val) +int32_t sths34pf80_lpf_a_t_bandwidth_set(const stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t val) { sths34pf80_lpf2_t lpf2; int32_t ret; @@ -1091,7 +1145,7 @@ int32_t sths34pf80_lpf_a_t_bandwidth_set(stmdev_ctx_t *ctx, sths34pf80_lpf_bandw * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_lpf_a_t_bandwidth_get(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t *val) +int32_t sths34pf80_lpf_a_t_bandwidth_get(const stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t *val) { sths34pf80_lpf2_t lpf2; int32_t ret; @@ -1143,7 +1197,7 @@ int32_t sths34pf80_lpf_a_t_bandwidth_get(stmdev_ctx_t *ctx, sths34pf80_lpf_bandw * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_lpf_p_bandwidth_set(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t val) +int32_t sths34pf80_lpf_p_bandwidth_set(const stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t val) { sths34pf80_lpf2_t lpf2; int32_t ret; @@ -1167,7 +1221,7 @@ int32_t sths34pf80_lpf_p_bandwidth_set(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwid * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_lpf_p_bandwidth_get(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t *val) +int32_t sths34pf80_lpf_p_bandwidth_get(const stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t *val) { sths34pf80_lpf2_t lpf2; int32_t ret; @@ -1226,11 +1280,11 @@ int32_t sths34pf80_lpf_p_bandwidth_get(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwid * @brief Selects interrupts to be routed.[set] * * @param ctx read / write interface definitions - * @param val TMOS_INT_HIZ, TMOS_INT_DRDY, TMOS_INT_OR, + * @param val INT_HIZ, INT_DRDY, INT_OR, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_tmos_route_int_set(stmdev_ctx_t *ctx, sths34pf80_tmos_route_int_t val) +int32_t sths34pf80_route_int_set(const stmdev_ctx_t *ctx, sths34pf80_route_int_t val) { sths34pf80_ctrl3_t ctrl3; int32_t ret; @@ -1240,7 +1294,8 @@ int32_t sths34pf80_tmos_route_int_set(stmdev_ctx_t *ctx, sths34pf80_tmos_route_i if (ret == 0) { ctrl3.ien = ((uint8_t)val & 0x3U); - if (val == STHS34PF80_TMOS_INT_OR) { + if (val == STHS34PF80_INT_OR) + { ctrl3.int_latched = 0; /* guarantee that latched is zero in INT_OR case */ } ret = sths34pf80_write_reg(ctx, STHS34PF80_CTRL3, (uint8_t *)&ctrl3, 1); @@ -1253,11 +1308,11 @@ int32_t sths34pf80_tmos_route_int_set(stmdev_ctx_t *ctx, sths34pf80_tmos_route_i * @brief Selects interrupts to be routed.[get] * * @param ctx read / write interface definitions - * @param val TMOS_INT_HIZ, TMOS_INT_DRDY, TMOS_INT_OR, + * @param val INT_HIZ, INT_DRDY, INT_OR, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_tmos_route_int_get(stmdev_ctx_t *ctx, sths34pf80_tmos_route_int_t *val) +int32_t sths34pf80_route_int_get(const stmdev_ctx_t *ctx, sths34pf80_route_int_t *val) { sths34pf80_ctrl3_t ctrl3; int32_t ret; @@ -1266,20 +1321,20 @@ int32_t sths34pf80_tmos_route_int_get(stmdev_ctx_t *ctx, sths34pf80_tmos_route_i switch ((ctrl3.ien)) { - case STHS34PF80_TMOS_INT_HIZ: - *val = STHS34PF80_TMOS_INT_HIZ; + case STHS34PF80_INT_HIZ: + *val = STHS34PF80_INT_HIZ; break; - case STHS34PF80_TMOS_INT_DRDY: - *val = STHS34PF80_TMOS_INT_DRDY; + case STHS34PF80_INT_DRDY: + *val = STHS34PF80_INT_DRDY; break; - case STHS34PF80_TMOS_INT_OR: - *val = STHS34PF80_TMOS_INT_OR; + case STHS34PF80_INT_OR: + *val = STHS34PF80_INT_OR; break; default: - *val = STHS34PF80_TMOS_INT_HIZ; + *val = STHS34PF80_INT_HIZ; break; } return ret; @@ -1289,11 +1344,11 @@ int32_t sths34pf80_tmos_route_int_get(stmdev_ctx_t *ctx, sths34pf80_tmos_route_i * @brief Selects interrupts output.[set] * * @param ctx read / write interface definitions - * @param val TMOS_INT_NONE, TMOS_INT_TSHOCK, TMOS_INT_MOTION, TMOS_INT_TSHOCK_MOTION, TMOS_INT_PRESENCE, TMOS_INT_TSHOCK_PRESENCE, TMOS_INT_MOTION_PRESENCE, TMOS_INT_ALL, + * @param val INT_NONE, INT_TSHOCK, INT_MOTION, INT_TSHOCK_MOTION, INT_PRESENCE, INT_TSHOCK_PRESENCE, INT_MOTION_PRESENCE, INT_ALL, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_tmos_int_or_set(stmdev_ctx_t *ctx, sths34pf80_tmos_int_or_t val) +int32_t sths34pf80_int_or_set(const stmdev_ctx_t *ctx, sths34pf80_int_or_t val) { sths34pf80_ctrl3_t ctrl3; int32_t ret; @@ -1313,11 +1368,11 @@ int32_t sths34pf80_tmos_int_or_set(stmdev_ctx_t *ctx, sths34pf80_tmos_int_or_t v * @brief Selects interrupts output.[get] * * @param ctx read / write interface definitions - * @param val TMOS_INT_NONE, TMOS_INT_TSHOCK, TMOS_INT_MOTION, TMOS_INT_TSHOCK_MOTION, TMOS_INT_PRESENCE, TMOS_INT_TSHOCK_PRESENCE, TMOS_INT_MOTION_PRESENCE, TMOS_INT_ALL, + * @param val INT_NONE, INT_TSHOCK, INT_MOTION, INT_TSHOCK_MOTION, INT_PRESENCE, INT_TSHOCK_PRESENCE, INT_MOTION_PRESENCE, INT_ALL, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_tmos_int_or_get(stmdev_ctx_t *ctx, sths34pf80_tmos_int_or_t *val) +int32_t sths34pf80_int_or_get(const stmdev_ctx_t *ctx, sths34pf80_int_or_t *val) { sths34pf80_ctrl3_t ctrl3; int32_t ret; @@ -1326,40 +1381,40 @@ int32_t sths34pf80_tmos_int_or_get(stmdev_ctx_t *ctx, sths34pf80_tmos_int_or_t * switch ((ctrl3.int_msk)) { - case STHS34PF80_TMOS_INT_NONE: - *val = STHS34PF80_TMOS_INT_NONE; + case STHS34PF80_INT_NONE: + *val = STHS34PF80_INT_NONE; break; - case STHS34PF80_TMOS_INT_TSHOCK: - *val = STHS34PF80_TMOS_INT_TSHOCK; + case STHS34PF80_INT_TSHOCK: + *val = STHS34PF80_INT_TSHOCK; break; - case STHS34PF80_TMOS_INT_MOTION: - *val = STHS34PF80_TMOS_INT_MOTION; + case STHS34PF80_INT_MOTION: + *val = STHS34PF80_INT_MOTION; break; - case STHS34PF80_TMOS_INT_TSHOCK_MOTION: - *val = STHS34PF80_TMOS_INT_TSHOCK_MOTION; + case STHS34PF80_INT_TSHOCK_MOTION: + *val = STHS34PF80_INT_TSHOCK_MOTION; break; - case STHS34PF80_TMOS_INT_PRESENCE: - *val = STHS34PF80_TMOS_INT_PRESENCE; + case STHS34PF80_INT_PRESENCE: + *val = STHS34PF80_INT_PRESENCE; break; - case STHS34PF80_TMOS_INT_TSHOCK_PRESENCE: - *val = STHS34PF80_TMOS_INT_TSHOCK_PRESENCE; + case STHS34PF80_INT_TSHOCK_PRESENCE: + *val = STHS34PF80_INT_TSHOCK_PRESENCE; break; - case STHS34PF80_TMOS_INT_MOTION_PRESENCE: - *val = STHS34PF80_TMOS_INT_MOTION_PRESENCE; + case STHS34PF80_INT_MOTION_PRESENCE: + *val = STHS34PF80_INT_MOTION_PRESENCE; break; - case STHS34PF80_TMOS_INT_ALL: - *val = STHS34PF80_TMOS_INT_ALL; + case STHS34PF80_INT_ALL: + *val = STHS34PF80_INT_ALL; break; default: - *val = STHS34PF80_TMOS_INT_NONE; + *val = STHS34PF80_INT_NONE; break; } return ret; @@ -1373,7 +1428,7 @@ int32_t sths34pf80_tmos_int_or_get(stmdev_ctx_t *ctx, sths34pf80_tmos_int_or_t * * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_int_mode_set(stmdev_ctx_t *ctx, sths34pf80_int_mode_t val) +int32_t sths34pf80_int_mode_set(const stmdev_ctx_t *ctx, sths34pf80_int_mode_t val) { sths34pf80_ctrl3_t ctrl3; int32_t ret; @@ -1398,7 +1453,7 @@ int32_t sths34pf80_int_mode_set(stmdev_ctx_t *ctx, sths34pf80_int_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_int_mode_get(stmdev_ctx_t *ctx, sths34pf80_int_mode_t *val) +int32_t sths34pf80_int_mode_get(const stmdev_ctx_t *ctx, sths34pf80_int_mode_t *val) { sths34pf80_ctrl3_t ctrl3; int32_t ret; @@ -1446,7 +1501,7 @@ int32_t sths34pf80_int_mode_get(stmdev_ctx_t *ctx, sths34pf80_int_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_drdy_mode_set(stmdev_ctx_t *ctx, sths34pf80_drdy_mode_t val) +int32_t sths34pf80_drdy_mode_set(const stmdev_ctx_t *ctx, sths34pf80_drdy_mode_t val) { sths34pf80_ctrl3_t ctrl3; int32_t ret; @@ -1470,7 +1525,7 @@ int32_t sths34pf80_drdy_mode_set(stmdev_ctx_t *ctx, sths34pf80_drdy_mode_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_drdy_mode_get(stmdev_ctx_t *ctx, sths34pf80_drdy_mode_t *val) +int32_t sths34pf80_drdy_mode_get(const stmdev_ctx_t *ctx, sths34pf80_drdy_mode_t *val) { sths34pf80_ctrl3_t ctrl3; int32_t ret; @@ -1515,7 +1570,7 @@ int32_t sths34pf80_drdy_mode_get(stmdev_ctx_t *ctx, sths34pf80_drdy_mode_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_func_cfg_write(stmdev_ctx_t *ctx, uint8_t addr, uint8_t *data, uint8_t len) +int32_t sths34pf80_func_cfg_write(const stmdev_ctx_t *ctx, uint8_t addr, uint8_t *data, uint8_t len) { sths34pf80_ctrl1_t ctrl1; uint8_t odr; @@ -1526,7 +1581,7 @@ int32_t sths34pf80_func_cfg_write(stmdev_ctx_t *ctx, uint8_t addr, uint8_t *data /* Save current odr and enter PD mode */ ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); odr = ctrl1.odr; - ret += sths34pf80_tmos_odr_check_safe_set(ctx, ctrl1, 0); + ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0); /* Enable access to embedded functions register */ ret += sths34pf80_mem_bank_set(ctx, STHS34PF80_EMBED_FUNC_MEM_BANK); @@ -1552,7 +1607,7 @@ int32_t sths34pf80_func_cfg_write(stmdev_ctx_t *ctx, uint8_t addr, uint8_t *data ret += sths34pf80_mem_bank_set(ctx, STHS34PF80_MAIN_MEM_BANK); /* Set saved odr back */ - ret += sths34pf80_tmos_odr_check_safe_set(ctx, ctrl1, odr); + ret += sths34pf80_odr_safe_set(ctx, &ctrl1, odr); return ret; } @@ -1567,7 +1622,7 @@ int32_t sths34pf80_func_cfg_write(stmdev_ctx_t *ctx, uint8_t addr, uint8_t *data * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_func_cfg_read(stmdev_ctx_t *ctx, uint8_t addr, uint8_t *data, uint8_t len) +int32_t sths34pf80_func_cfg_read(const stmdev_ctx_t *ctx, uint8_t addr, uint8_t *data, uint8_t len) { sths34pf80_ctrl1_t ctrl1; uint8_t odr; @@ -1579,7 +1634,7 @@ int32_t sths34pf80_func_cfg_read(stmdev_ctx_t *ctx, uint8_t addr, uint8_t *data, /* Save current odr and enter PD mode */ ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); odr = ctrl1.odr; - ret += sths34pf80_tmos_odr_check_safe_set(ctx, ctrl1, 0); + ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0); /* Enable access to embedded functions register */ ret += sths34pf80_mem_bank_set(ctx, STHS34PF80_EMBED_FUNC_MEM_BANK); @@ -1590,7 +1645,7 @@ int32_t sths34pf80_func_cfg_read(stmdev_ctx_t *ctx, uint8_t addr, uint8_t *data, for (i = 0; i < len; i++) { - /* Select register address */ + /* Select register address */ reg_addr = addr + i; ret += sths34pf80_write_reg(ctx, STHS34PF80_FUNC_CFG_ADDR, ®_addr, 1); @@ -1606,7 +1661,7 @@ int32_t sths34pf80_func_cfg_read(stmdev_ctx_t *ctx, uint8_t addr, uint8_t *data, ret += sths34pf80_mem_bank_set(ctx, STHS34PF80_MAIN_MEM_BANK); /* Set saved odr back */ - ret += sths34pf80_tmos_odr_check_safe_set(ctx, ctrl1, odr); + ret += sths34pf80_odr_safe_set(ctx, &ctrl1, odr); return ret; } @@ -1619,14 +1674,15 @@ int32_t sths34pf80_func_cfg_read(stmdev_ctx_t *ctx, uint8_t addr, uint8_t *data, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_presence_threshold_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t sths34pf80_presence_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { sths34pf80_ctrl1_t ctrl1; uint8_t odr; uint8_t buff[2]; int32_t ret; - if ((val & 0x8000U) != 0x0U) { + if ((val & 0x8000U) != 0x0U) + { /* threshold values are on 15 bits */ return -1; } @@ -1634,16 +1690,16 @@ int32_t sths34pf80_presence_threshold_set(stmdev_ctx_t *ctx, uint16_t val) /* Save current odr and enter PD mode */ ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); odr = ctrl1.odr; - ret += sths34pf80_tmos_odr_check_safe_set(ctx, ctrl1, 0); + ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0); buff[1] = (uint8_t)(val / 256U); buff[0] = (uint8_t)(val - (buff[1] * 256U)); ret += sths34pf80_func_cfg_write(ctx, STHS34PF80_PRESENCE_THS, &buff[0], 2); - ret += sths34pf80_algo_reset(ctx); + ret += sths34pf80_reset_algo_bit_set(ctx); /* Set saved odr back */ - ret += sths34pf80_tmos_odr_check_safe_set(ctx, ctrl1, odr); + ret += sths34pf80_odr_safe_set(ctx, &ctrl1, odr); return ret; } @@ -1656,7 +1712,7 @@ int32_t sths34pf80_presence_threshold_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_presence_threshold_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t sths34pf80_presence_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1677,14 +1733,15 @@ int32_t sths34pf80_presence_threshold_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_motion_threshold_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t sths34pf80_motion_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { sths34pf80_ctrl1_t ctrl1; uint8_t odr; uint8_t buff[2]; int32_t ret; - if ((val & 0x8000U) != 0x0U) { + if ((val & 0x8000U) != 0x0U) + { /* threshold values are on 15 bits */ return -1; } @@ -1692,16 +1749,16 @@ int32_t sths34pf80_motion_threshold_set(stmdev_ctx_t *ctx, uint16_t val) /* Save current odr and enter PD mode */ ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); odr = ctrl1.odr; - ret += sths34pf80_tmos_odr_check_safe_set(ctx, ctrl1, 0); + ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0); buff[1] = (uint8_t)(val / 256U); buff[0] = (uint8_t)(val - (buff[1] * 256U)); ret += sths34pf80_func_cfg_write(ctx, STHS34PF80_MOTION_THS, &buff[0], 2); - ret += sths34pf80_algo_reset(ctx); + ret += sths34pf80_reset_algo_bit_set(ctx); /* Set saved odr back */ - ret += sths34pf80_tmos_odr_check_safe_set(ctx, ctrl1, odr); + ret += sths34pf80_odr_safe_set(ctx, &ctrl1, odr); return ret; } @@ -1714,7 +1771,7 @@ int32_t sths34pf80_motion_threshold_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_motion_threshold_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t sths34pf80_motion_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1735,14 +1792,15 @@ int32_t sths34pf80_motion_threshold_get(stmdev_ctx_t *ctx, uint16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_tambient_shock_threshold_set(stmdev_ctx_t *ctx, uint16_t val) +int32_t sths34pf80_tambient_shock_threshold_set(const stmdev_ctx_t *ctx, uint16_t val) { sths34pf80_ctrl1_t ctrl1; uint8_t odr; uint8_t buff[2]; int32_t ret; - if ((val & 0x8000U) != 0x0U) { + if ((val & 0x8000U) != 0x0U) + { /* threshold values are on 15 bits */ return -1; } @@ -1750,16 +1808,16 @@ int32_t sths34pf80_tambient_shock_threshold_set(stmdev_ctx_t *ctx, uint16_t val) /* Save current odr and enter PD mode */ ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); odr = ctrl1.odr; - ret += sths34pf80_tmos_odr_check_safe_set(ctx, ctrl1, 0); + ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0); buff[1] = (uint8_t)(val / 256U); buff[0] = (uint8_t)(val - (buff[1] * 256U)); ret += sths34pf80_func_cfg_write(ctx, STHS34PF80_TAMB_SHOCK_THS, &buff[0], 2); - ret += sths34pf80_algo_reset(ctx); + ret += sths34pf80_reset_algo_bit_set(ctx); /* Set saved odr back */ - ret += sths34pf80_tmos_odr_check_safe_set(ctx, ctrl1, odr); + ret += sths34pf80_odr_safe_set(ctx, &ctrl1, odr); return ret; } @@ -1772,7 +1830,7 @@ int32_t sths34pf80_tambient_shock_threshold_set(stmdev_ctx_t *ctx, uint16_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_tambient_shock_threshold_get(stmdev_ctx_t *ctx, uint16_t *val) +int32_t sths34pf80_tambient_shock_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val) { uint8_t buff[2]; int32_t ret; @@ -1793,7 +1851,7 @@ int32_t sths34pf80_tambient_shock_threshold_get(stmdev_ctx_t *ctx, uint16_t *val * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_motion_hysteresis_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t sths34pf80_motion_hysteresis_set(const stmdev_ctx_t *ctx, uint8_t val) { sths34pf80_ctrl1_t ctrl1; uint8_t odr; @@ -1802,14 +1860,14 @@ int32_t sths34pf80_motion_hysteresis_set(stmdev_ctx_t *ctx, uint8_t val) /* Save current odr and enter PD mode */ ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); odr = ctrl1.odr; - ret += sths34pf80_tmos_odr_check_safe_set(ctx, ctrl1, 0); + ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0); ret += sths34pf80_func_cfg_write(ctx, STHS34PF80_HYST_MOTION, &val, 1); - ret += sths34pf80_algo_reset(ctx); + ret += sths34pf80_reset_algo_bit_set(ctx); /* Set saved odr back */ - ret += sths34pf80_tmos_odr_check_safe_set(ctx, ctrl1, odr); + ret += sths34pf80_odr_safe_set(ctx, &ctrl1, odr); return ret; } @@ -1822,7 +1880,7 @@ int32_t sths34pf80_motion_hysteresis_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_motion_hysteresis_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t sths34pf80_motion_hysteresis_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -1839,7 +1897,7 @@ int32_t sths34pf80_motion_hysteresis_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_presence_hysteresis_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t sths34pf80_presence_hysteresis_set(const stmdev_ctx_t *ctx, uint8_t val) { sths34pf80_ctrl1_t ctrl1; uint8_t odr; @@ -1848,14 +1906,14 @@ int32_t sths34pf80_presence_hysteresis_set(stmdev_ctx_t *ctx, uint8_t val) /* Save current odr and enter PD mode */ ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); odr = ctrl1.odr; - ret += sths34pf80_tmos_odr_check_safe_set(ctx, ctrl1, 0); + ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0); ret += sths34pf80_func_cfg_write(ctx, STHS34PF80_HYST_PRESENCE, &val, 1); - ret += sths34pf80_algo_reset(ctx); + ret += sths34pf80_reset_algo_bit_set(ctx); /* Set saved odr back */ - ret += sths34pf80_tmos_odr_check_safe_set(ctx, ctrl1, odr); + ret += sths34pf80_odr_safe_set(ctx, &ctrl1, odr); return ret; } @@ -1868,7 +1926,7 @@ int32_t sths34pf80_presence_hysteresis_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_presence_hysteresis_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t sths34pf80_presence_hysteresis_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -1885,7 +1943,7 @@ int32_t sths34pf80_presence_hysteresis_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_tambient_shock_hysteresis_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t sths34pf80_tambient_shock_hysteresis_set(const stmdev_ctx_t *ctx, uint8_t val) { sths34pf80_ctrl1_t ctrl1; uint8_t odr; @@ -1894,14 +1952,14 @@ int32_t sths34pf80_tambient_shock_hysteresis_set(stmdev_ctx_t *ctx, uint8_t val) /* Save current odr and enter PD mode */ ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); odr = ctrl1.odr; - ret += sths34pf80_tmos_odr_check_safe_set(ctx, ctrl1, 0); + ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0); ret += sths34pf80_func_cfg_write(ctx, STHS34PF80_HYST_TAMB_SHOCK, &val, 1); - ret += sths34pf80_algo_reset(ctx); + ret += sths34pf80_reset_algo_bit_set(ctx); /* Set saved odr back */ - ret += sths34pf80_tmos_odr_check_safe_set(ctx, ctrl1, odr); + ret += sths34pf80_odr_safe_set(ctx, &ctrl1, odr); return ret; } @@ -1914,7 +1972,7 @@ int32_t sths34pf80_tambient_shock_hysteresis_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_tambient_shock_hysteresis_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t sths34pf80_tambient_shock_hysteresis_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -1923,13 +1981,6 @@ int32_t sths34pf80_tambient_shock_hysteresis_get(stmdev_ctx_t *ctx, uint8_t *val return ret; } -typedef struct -{ - uint8_t int_pulsed : 1; - uint8_t comp_type : 1; - uint8_t sel_abs : 1; -} sths34pf80_algo_config_t; - /** * @brief Algo configuration.[set] * @@ -1938,7 +1989,7 @@ typedef struct * @retval interface status (MANDATORY: return 0 -> no Error) * */ -static int32_t sths34pf80_algo_config_set(stmdev_ctx_t *ctx, sths34pf80_algo_config_t val) +static int32_t sths34pf80_algo_config_set(const stmdev_ctx_t *ctx, sths34pf80_algo_config_t val) { uint8_t tmp; int32_t ret; @@ -1957,7 +2008,7 @@ static int32_t sths34pf80_algo_config_set(stmdev_ctx_t *ctx, sths34pf80_algo_con * @retval interface status (MANDATORY: return 0 -> no Error) * */ -static int32_t sths34pf80_algo_config_get(stmdev_ctx_t *ctx, sths34pf80_algo_config_t *val) +static int32_t sths34pf80_algo_config_get(const stmdev_ctx_t *ctx, sths34pf80_algo_config_t *val) { uint8_t tmp; int32_t ret; @@ -1978,7 +2029,7 @@ static int32_t sths34pf80_algo_config_get(stmdev_ctx_t *ctx, sths34pf80_algo_con * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_tobject_algo_compensation_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t sths34pf80_tobject_algo_compensation_set(const stmdev_ctx_t *ctx, uint8_t val) { sths34pf80_ctrl1_t ctrl1; uint8_t odr; @@ -1988,16 +2039,19 @@ int32_t sths34pf80_tobject_algo_compensation_set(stmdev_ctx_t *ctx, uint8_t val) /* Save current odr and enter PD mode */ ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); odr = ctrl1.odr; - ret += sths34pf80_tmos_odr_check_safe_set(ctx, ctrl1, 0); - if (ret != 0) { return ret; } + ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0); + if (ret != 0) + { + return ret; + } ret = sths34pf80_algo_config_get(ctx, &config); config.comp_type = val; ret += sths34pf80_algo_config_set(ctx, config); - ret += sths34pf80_algo_reset(ctx); + ret += sths34pf80_reset_algo_bit_set(ctx); /* Set saved odr back */ - ret += sths34pf80_tmos_odr_check_safe_set(ctx, ctrl1, odr); + ret += sths34pf80_odr_safe_set(ctx, &ctrl1, odr); return ret; } @@ -2010,7 +2064,7 @@ int32_t sths34pf80_tobject_algo_compensation_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_tobject_algo_compensation_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t sths34pf80_tobject_algo_compensation_get(const stmdev_ctx_t *ctx, uint8_t *val) { sths34pf80_algo_config_t config; int32_t ret; @@ -2029,7 +2083,7 @@ int32_t sths34pf80_tobject_algo_compensation_get(stmdev_ctx_t *ctx, uint8_t *val * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_presence_abs_value_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t sths34pf80_presence_abs_value_set(const stmdev_ctx_t *ctx, uint8_t val) { sths34pf80_ctrl1_t ctrl1; uint8_t odr; @@ -2039,16 +2093,19 @@ int32_t sths34pf80_presence_abs_value_set(stmdev_ctx_t *ctx, uint8_t val) /* Save current odr and enter PD mode */ ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); odr = ctrl1.odr; - ret += sths34pf80_tmos_odr_check_safe_set(ctx, ctrl1, 0); - if (ret != 0) { return ret; } + ret += sths34pf80_odr_safe_set(ctx, &ctrl1, 0); + if (ret != 0) + { + return ret; + } ret = sths34pf80_algo_config_get(ctx, &config); config.sel_abs = val; ret += sths34pf80_algo_config_set(ctx, config); - ret += sths34pf80_algo_reset(ctx); + ret += sths34pf80_reset_algo_bit_set(ctx); /* Set saved odr back */ - ret += sths34pf80_tmos_odr_check_safe_set(ctx, ctrl1, odr); + ret += sths34pf80_odr_safe_set(ctx, &ctrl1, odr); return ret; } @@ -2061,7 +2118,7 @@ int32_t sths34pf80_presence_abs_value_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_presence_abs_value_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t sths34pf80_presence_abs_value_get(const stmdev_ctx_t *ctx, uint8_t *val) { sths34pf80_algo_config_t config; int32_t ret; @@ -2080,7 +2137,7 @@ int32_t sths34pf80_presence_abs_value_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_int_or_pulsed_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t sths34pf80_int_or_pulsed_set(const stmdev_ctx_t *ctx, uint8_t val) { sths34pf80_algo_config_t config; int32_t ret; @@ -2100,7 +2157,7 @@ int32_t sths34pf80_int_or_pulsed_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_int_or_pulsed_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t sths34pf80_int_or_pulsed_get(const stmdev_ctx_t *ctx, uint8_t *val) { sths34pf80_algo_config_t config; int32_t ret; @@ -2111,6 +2168,39 @@ int32_t sths34pf80_int_or_pulsed_get(stmdev_ctx_t *ctx, uint8_t *val) return ret; } +/* + * Internal routine to reset algo bit + */ +static int32_t sths34pf80_reset_algo_bit_set(const stmdev_ctx_t *ctx) +{ + sths34pf80_page_rw_t page_rw = {0}; + int32_t ret; + + /* Enable access to embedded functions register */ + ret = sths34pf80_mem_bank_set(ctx, STHS34PF80_EMBED_FUNC_MEM_BANK); + + /* Enable write mode */ + page_rw.func_cfg_write = 1; + ret += sths34pf80_write_reg(ctx, STHS34PF80_PAGE_RW, (uint8_t *)&page_rw, 1); + + /* Select register address (it will autoincrement when writing) */ + uint8_t addr = STHS34PF80_RESET_ALGO; + ret += sths34pf80_write_reg(ctx, STHS34PF80_FUNC_CFG_ADDR, &addr, 1); + + /* Write data */ + uint8_t data = 0x01; + ret += sths34pf80_write_reg(ctx, STHS34PF80_FUNC_CFG_DATA, &data, 1); + + /* Disable write mode */ + page_rw.func_cfg_write = 0; + ret += sths34pf80_write_reg(ctx, STHS34PF80_PAGE_RW, (uint8_t *)&page_rw, 1); + + /* Disable access to embedded functions register */ + ret += sths34pf80_mem_bank_set(ctx, STHS34PF80_MAIN_MEM_BANK); + + return ret; +} + /** * @brief Reset algo * @@ -2119,13 +2209,22 @@ int32_t sths34pf80_int_or_pulsed_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t sths34pf80_algo_reset(stmdev_ctx_t *ctx) +int32_t sths34pf80_algo_reset(const stmdev_ctx_t *ctx) { - uint8_t tmp; + sths34pf80_ctrl1_t ctrl1; + uint8_t odr; int32_t ret; - tmp = 1; - ret = sths34pf80_func_cfg_write(ctx, STHS34PF80_RESET_ALGO, &tmp, 1); + /* Save current odr and enter PD mode */ + ret = sths34pf80_read_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); + odr = ctrl1.odr; + ret += sths34pf80_safe_power_down(ctx, &ctrl1); + + ret += sths34pf80_reset_algo_bit_set(ctx); + + /* Set saved odr back */ + ctrl1.odr = odr; + ret += sths34pf80_write_reg(ctx, STHS34PF80_CTRL1, (uint8_t *)&ctrl1, 1); return ret; } diff --git a/sensor/stmemsc/sths34pf80_STdC/driver/sths34pf80_reg.h b/sensor/stmemsc/sths34pf80_STdC/driver/sths34pf80_reg.h index 6e7ce885..c1c42271 100644 --- a/sensor/stmemsc/sths34pf80_STdC/driver/sths34pf80_reg.h +++ b/sensor/stmemsc/sths34pf80_STdC/driver/sths34pf80_reg.h @@ -573,14 +573,14 @@ typedef union * The default implementation is declared with a __weak directive to * allow the final application to overwrite it with a custom implementation. */ -int32_t sths34pf80_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t sths34pf80_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t sths34pf80_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t sths34pf80_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t sths34pf80_device_id_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t sths34pf80_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { @@ -593,8 +593,8 @@ typedef enum STHS34PF80_AVG_TMOS_1024 = 0x6, STHS34PF80_AVG_TMOS_2048 = 0x7, } sths34pf80_avg_tobject_num_t; -int32_t sths34pf80_avg_tobject_num_set(stmdev_ctx_t *ctx, sths34pf80_avg_tobject_num_t val); -int32_t sths34pf80_avg_tobject_num_get(stmdev_ctx_t *ctx, sths34pf80_avg_tobject_num_t *val); +int32_t sths34pf80_avg_tobject_num_set(const stmdev_ctx_t *ctx, sths34pf80_avg_tobject_num_t val); +int32_t sths34pf80_avg_tobject_num_get(const stmdev_ctx_t *ctx, sths34pf80_avg_tobject_num_t *val); typedef enum { @@ -603,8 +603,9 @@ typedef enum STHS34PF80_AVG_T_2 = 0x2, STHS34PF80_AVG_T_1 = 0x3, } sths34pf80_avg_tambient_num_t; -int32_t sths34pf80_avg_tambient_num_set(stmdev_ctx_t *ctx, sths34pf80_avg_tambient_num_t val); -int32_t sths34pf80_avg_tambient_num_get(stmdev_ctx_t *ctx, sths34pf80_avg_tambient_num_t *val); +int32_t sths34pf80_avg_tambient_num_set(const stmdev_ctx_t *ctx, sths34pf80_avg_tambient_num_t val); +int32_t sths34pf80_avg_tambient_num_get(const stmdev_ctx_t *ctx, + sths34pf80_avg_tambient_num_t *val); typedef enum { @@ -612,69 +613,63 @@ typedef enum STHS34PF80_GAIN_DEFAULT_MODE = 0x7, } sths34pf80_gain_mode_t; -int32_t sths34pf80_gain_mode_set(stmdev_ctx_t *ctx, sths34pf80_gain_mode_t val); -int32_t sths34pf80_gain_mode_get(stmdev_ctx_t *ctx, sths34pf80_gain_mode_t *val); +int32_t sths34pf80_gain_mode_set(const stmdev_ctx_t *ctx, sths34pf80_gain_mode_t val); +int32_t sths34pf80_gain_mode_get(const stmdev_ctx_t *ctx, sths34pf80_gain_mode_t *val); -int32_t sths34pf80_tmos_sensitivity_set(stmdev_ctx_t *ctx, uint16_t *val); -int32_t sths34pf80_tmos_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t sths34pf80_tobject_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t *val); +int32_t sths34pf80_tobject_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); typedef enum { - STHS34PF80_TMOS_ODR_OFF = 0x0, - STHS34PF80_TMOS_ODR_AT_0Hz25 = 0x1, - STHS34PF80_TMOS_ODR_AT_0Hz50 = 0x2, - STHS34PF80_TMOS_ODR_AT_1Hz = 0x3, - STHS34PF80_TMOS_ODR_AT_2Hz = 0x4, - STHS34PF80_TMOS_ODR_AT_4Hz = 0x5, - STHS34PF80_TMOS_ODR_AT_8Hz = 0x6, - STHS34PF80_TMOS_ODR_AT_15Hz = 0x7, - STHS34PF80_TMOS_ODR_AT_30Hz = 0x8, -} sths34pf80_tmos_odr_t; -int32_t sths34pf80_tmos_odr_set(stmdev_ctx_t *ctx, sths34pf80_tmos_odr_t val); -int32_t sths34pf80_tmos_odr_get(stmdev_ctx_t *ctx, sths34pf80_tmos_odr_t *val); - -int32_t sths34pf80_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t sths34pf80_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); + STHS34PF80_ODR_OFF = 0x0, + STHS34PF80_ODR_AT_0Hz25 = 0x1, + STHS34PF80_ODR_AT_0Hz50 = 0x2, + STHS34PF80_ODR_AT_1Hz = 0x3, + STHS34PF80_ODR_AT_2Hz = 0x4, + STHS34PF80_ODR_AT_4Hz = 0x5, + STHS34PF80_ODR_AT_8Hz = 0x6, + STHS34PF80_ODR_AT_15Hz = 0x7, + STHS34PF80_ODR_AT_30Hz = 0x8, +} sths34pf80_odr_t; +int32_t sths34pf80_odr_set(const stmdev_ctx_t *ctx, sths34pf80_odr_t val); +int32_t sths34pf80_odr_get(const stmdev_ctx_t *ctx, sths34pf80_odr_t *val); + +int32_t sths34pf80_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t sths34pf80_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef enum { - STHS34PF80_TMOS_IDLE_MODE = 0x0, - STHS34PF80_TMOS_ONE_SHOT = 0x1, -} sths34pf80_tmos_one_shot_t; -int32_t sths34pf80_tmos_one_shot_set(stmdev_ctx_t *ctx, sths34pf80_tmos_one_shot_t val); -int32_t sths34pf80_tmos_one_shot_get(stmdev_ctx_t *ctx, sths34pf80_tmos_one_shot_t *val); + STHS34PF80_IDLE_MODE = 0x0, + STHS34PF80_ONE_SHOT = 0x1, +} sths34pf80_one_shot_t; +int32_t sths34pf80_one_shot_set(const stmdev_ctx_t *ctx, sths34pf80_one_shot_t val); +int32_t sths34pf80_one_shot_get(const stmdev_ctx_t *ctx, sths34pf80_one_shot_t *val); typedef enum { STHS34PF80_MAIN_MEM_BANK = 0x0, STHS34PF80_EMBED_FUNC_MEM_BANK = 0x1, } sths34pf80_mem_bank_t; -int32_t sths34pf80_mem_bank_set(stmdev_ctx_t *ctx, sths34pf80_mem_bank_t val); -int32_t sths34pf80_mem_bank_get(stmdev_ctx_t *ctx, sths34pf80_mem_bank_t *val); +int32_t sths34pf80_mem_bank_set(const stmdev_ctx_t *ctx, sths34pf80_mem_bank_t val); +int32_t sths34pf80_mem_bank_get(const stmdev_ctx_t *ctx, sths34pf80_mem_bank_t *val); -int32_t sths34pf80_boot_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t sths34pf80_boot_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t sths34pf80_boot_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t sths34pf80_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { uint8_t drdy : 1; -} sths34pf80_tmos_drdy_status_t; -int32_t sths34pf80_tmos_drdy_status_get(stmdev_ctx_t *ctx, sths34pf80_tmos_drdy_status_t *val); +} sths34pf80_drdy_status_t; +int32_t sths34pf80_drdy_status_get(const stmdev_ctx_t *ctx, sths34pf80_drdy_status_t *val); -typedef struct -{ - uint8_t tamb_shock_flag : 1; - uint8_t mot_flag : 1; - uint8_t pres_flag : 1; -} sths34pf80_tmos_func_status_t; -int32_t sths34pf80_tmos_func_status_get(stmdev_ctx_t *ctx, sths34pf80_tmos_func_status_t *val); +int32_t sths34pf80_func_status_get(const stmdev_ctx_t *ctx, sths34pf80_func_status_t *val); -int32_t sths34pf80_tobject_raw_get(stmdev_ctx_t *ctx, int16_t *val); -int32_t sths34pf80_tambient_raw_get(stmdev_ctx_t *ctx, int16_t *val); -int32_t sths34pf80_tobj_comp_raw_get(stmdev_ctx_t *ctx, int16_t *val); -int32_t sths34pf80_tpresence_raw_get(stmdev_ctx_t *ctx, int16_t *val); -int32_t sths34pf80_tmotion_raw_get(stmdev_ctx_t *ctx, int16_t *val); -int32_t sths34pf80_tamb_shock_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t sths34pf80_tobject_raw_get(const stmdev_ctx_t *ctx, int16_t *val); +int32_t sths34pf80_tambient_raw_get(const stmdev_ctx_t *ctx, int16_t *val); +int32_t sths34pf80_tobj_comp_raw_get(const stmdev_ctx_t *ctx, int16_t *val); +int32_t sths34pf80_tpresence_raw_get(const stmdev_ctx_t *ctx, int16_t *val); +int32_t sths34pf80_tmotion_raw_get(const stmdev_ctx_t *ctx, int16_t *val); +int32_t sths34pf80_tamb_shock_raw_get(const stmdev_ctx_t *ctx, int16_t *val); typedef enum { @@ -686,89 +681,93 @@ typedef enum STHS34PF80_LPF_ODR_DIV_400 = 0x5, STHS34PF80_LPF_ODR_DIV_800 = 0x6, } sths34pf80_lpf_bandwidth_t; -int32_t sths34pf80_lpf_m_bandwidth_set(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t val); -int32_t sths34pf80_lpf_m_bandwidth_get(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t *val); -int32_t sths34pf80_lpf_p_m_bandwidth_set(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t val); -int32_t sths34pf80_lpf_p_m_bandwidth_get(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t *val); -int32_t sths34pf80_lpf_a_t_bandwidth_set(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t val); -int32_t sths34pf80_lpf_a_t_bandwidth_get(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t *val); -int32_t sths34pf80_lpf_p_bandwidth_set(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t val); -int32_t sths34pf80_lpf_p_bandwidth_get(stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t *val); +int32_t sths34pf80_lpf_m_bandwidth_set(const stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t val); +int32_t sths34pf80_lpf_m_bandwidth_get(const stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t *val); +int32_t sths34pf80_lpf_p_m_bandwidth_set(const stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t val); +int32_t sths34pf80_lpf_p_m_bandwidth_get(const stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t *val); +int32_t sths34pf80_lpf_a_t_bandwidth_set(const stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t val); +int32_t sths34pf80_lpf_a_t_bandwidth_get(const stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t *val); +int32_t sths34pf80_lpf_p_bandwidth_set(const stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t val); +int32_t sths34pf80_lpf_p_bandwidth_get(const stmdev_ctx_t *ctx, sths34pf80_lpf_bandwidth_t *val); typedef enum { - STHS34PF80_TMOS_INT_HIZ = 0x0, - STHS34PF80_TMOS_INT_DRDY = 0x1, - STHS34PF80_TMOS_INT_OR = 0x2, -} sths34pf80_tmos_route_int_t; -int32_t sths34pf80_tmos_route_int_set(stmdev_ctx_t *ctx, sths34pf80_tmos_route_int_t val); -int32_t sths34pf80_tmos_route_int_get(stmdev_ctx_t *ctx, sths34pf80_tmos_route_int_t *val); + STHS34PF80_INT_HIZ = 0x0, + STHS34PF80_INT_DRDY = 0x1, + STHS34PF80_INT_OR = 0x2, +} sths34pf80_route_int_t; +int32_t sths34pf80_route_int_set(const stmdev_ctx_t *ctx, sths34pf80_route_int_t val); +int32_t sths34pf80_route_int_get(const stmdev_ctx_t *ctx, sths34pf80_route_int_t *val); typedef enum { - STHS34PF80_TMOS_INT_NONE = 0x0, - STHS34PF80_TMOS_INT_TSHOCK = 0x1, - STHS34PF80_TMOS_INT_MOTION = 0x2, - STHS34PF80_TMOS_INT_TSHOCK_MOTION = 0x3, - STHS34PF80_TMOS_INT_PRESENCE = 0x4, - STHS34PF80_TMOS_INT_TSHOCK_PRESENCE = 0x5, - STHS34PF80_TMOS_INT_MOTION_PRESENCE = 0x6, - STHS34PF80_TMOS_INT_ALL = 0x7, -} sths34pf80_tmos_int_or_t; -int32_t sths34pf80_tmos_int_or_set(stmdev_ctx_t *ctx, sths34pf80_tmos_int_or_t val); -int32_t sths34pf80_tmos_int_or_get(stmdev_ctx_t *ctx, sths34pf80_tmos_int_or_t *val); + STHS34PF80_INT_NONE = 0x0, + STHS34PF80_INT_TSHOCK = 0x1, + STHS34PF80_INT_MOTION = 0x2, + STHS34PF80_INT_TSHOCK_MOTION = 0x3, + STHS34PF80_INT_PRESENCE = 0x4, + STHS34PF80_INT_TSHOCK_PRESENCE = 0x5, + STHS34PF80_INT_MOTION_PRESENCE = 0x6, + STHS34PF80_INT_ALL = 0x7, +} sths34pf80_int_or_t; +int32_t sths34pf80_int_or_set(const stmdev_ctx_t *ctx, sths34pf80_int_or_t val); +int32_t sths34pf80_int_or_get(const stmdev_ctx_t *ctx, sths34pf80_int_or_t *val); typedef struct { - enum { + enum + { STHS34PF80_PUSH_PULL = 0x0, STHS34PF80_OPEN_DRAIN = 0x1, } pin; - enum { + enum + { STHS34PF80_ACTIVE_HIGH = 0x0, STHS34PF80_ACTIVE_LOW = 0x1, } polarity; } sths34pf80_int_mode_t; -int32_t sths34pf80_int_mode_set(stmdev_ctx_t *ctx, sths34pf80_int_mode_t val); -int32_t sths34pf80_int_mode_get(stmdev_ctx_t *ctx, sths34pf80_int_mode_t *val); +int32_t sths34pf80_int_mode_set(const stmdev_ctx_t *ctx, sths34pf80_int_mode_t val); +int32_t sths34pf80_int_mode_get(const stmdev_ctx_t *ctx, sths34pf80_int_mode_t *val); -typedef enum { +typedef enum +{ STHS34PF80_DRDY_PULSED = 0x0, STHS34PF80_DRDY_LATCHED = 0x1, } sths34pf80_drdy_mode_t; -int32_t sths34pf80_drdy_mode_set(stmdev_ctx_t *ctx, sths34pf80_drdy_mode_t val); -int32_t sths34pf80_drdy_mode_get(stmdev_ctx_t *ctx, sths34pf80_drdy_mode_t *val); +int32_t sths34pf80_drdy_mode_set(const stmdev_ctx_t *ctx, sths34pf80_drdy_mode_t val); +int32_t sths34pf80_drdy_mode_get(const stmdev_ctx_t *ctx, sths34pf80_drdy_mode_t *val); -int32_t sths34pf80_func_cfg_write(stmdev_ctx_t *ctx, uint8_t addr, uint8_t *data, uint8_t len); -int32_t sths34pf80_func_cfg_read(stmdev_ctx_t *ctx, uint8_t addr, uint8_t *data, uint8_t len); +int32_t sths34pf80_func_cfg_write(const stmdev_ctx_t *ctx, uint8_t addr, uint8_t *data, + uint8_t len); +int32_t sths34pf80_func_cfg_read(const stmdev_ctx_t *ctx, uint8_t addr, uint8_t *data, uint8_t len); -int32_t sths34pf80_presence_threshold_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t sths34pf80_presence_threshold_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t sths34pf80_presence_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t sths34pf80_presence_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t sths34pf80_motion_threshold_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t sths34pf80_motion_threshold_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t sths34pf80_motion_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t sths34pf80_motion_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t sths34pf80_tambient_shock_threshold_set(stmdev_ctx_t *ctx, uint16_t val); -int32_t sths34pf80_tambient_shock_threshold_get(stmdev_ctx_t *ctx, uint16_t *val); +int32_t sths34pf80_tambient_shock_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); +int32_t sths34pf80_tambient_shock_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); -int32_t sths34pf80_motion_hysteresis_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t sths34pf80_motion_hysteresis_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t sths34pf80_motion_hysteresis_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t sths34pf80_motion_hysteresis_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t sths34pf80_presence_hysteresis_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t sths34pf80_presence_hysteresis_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t sths34pf80_presence_hysteresis_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t sths34pf80_presence_hysteresis_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t sths34pf80_tambient_shock_hysteresis_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t sths34pf80_tambient_shock_hysteresis_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t sths34pf80_tambient_shock_hysteresis_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t sths34pf80_tambient_shock_hysteresis_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t sths34pf80_int_or_pulsed_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t sths34pf80_int_or_pulsed_get(stmdev_ctx_t *ctx, uint8_t *val); -int32_t sths34pf80_tobject_algo_compensation_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t sths34pf80_tobject_algo_compensation_get(stmdev_ctx_t *ctx, uint8_t *val); -int32_t sths34pf80_presence_abs_value_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t sths34pf80_presence_abs_value_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t sths34pf80_int_or_pulsed_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t sths34pf80_int_or_pulsed_get(const stmdev_ctx_t *ctx, uint8_t *val); +int32_t sths34pf80_tobject_algo_compensation_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t sths34pf80_tobject_algo_compensation_get(const stmdev_ctx_t *ctx, uint8_t *val); +int32_t sths34pf80_presence_abs_value_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t sths34pf80_presence_abs_value_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t sths34pf80_algo_reset(stmdev_ctx_t *ctx); +int32_t sths34pf80_algo_reset(const stmdev_ctx_t *ctx); #ifdef __cplusplus } diff --git a/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.c b/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.c index fdd0a0ba..fdbeea36 100644 --- a/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.c +++ b/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.c @@ -46,12 +46,14 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak stts22h_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak stts22h_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +69,14 @@ int32_t __weak stts22h_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak stts22h_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak stts22h_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) return -1; + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -116,67 +120,14 @@ float_t stts22h_from_lsb_to_celsius(int16_t lsb) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t stts22h_temp_data_rate_set(stmdev_ctx_t *ctx, +int32_t stts22h_temp_data_rate_set(const stmdev_ctx_t *ctx, stts22h_odr_temp_t val) { - stts22h_software_reset_t software_reset; stts22h_ctrl_t ctrl; int32_t ret; ret = stts22h_read_reg(ctx, STTS22H_CTRL, (uint8_t *)&ctrl, 1); - if (ret == 0) - { - ret = stts22h_read_reg(ctx, STTS22H_SOFTWARE_RESET, - (uint8_t *)&software_reset, 1); - } - - if ((val == STTS22H_ONE_SHOT) && (ret == 0)) - { - software_reset.sw_reset = PROPERTY_ENABLE; - ret = stts22h_write_reg(ctx, STTS22H_SOFTWARE_RESET, - (uint8_t *)&software_reset, 1); - - if (ret == 0) - { - software_reset.sw_reset = PROPERTY_DISABLE; - ret = stts22h_write_reg(ctx, STTS22H_SOFTWARE_RESET, - (uint8_t *)&software_reset, 1); - } - } - - if (((val == STTS22H_25Hz) || (val == STTS22H_50Hz) || - (val == STTS22H_100Hz) || (val == STTS22H_200Hz)) && - (ctrl.freerun == PROPERTY_DISABLE) && (ret == 0)) - { - software_reset.sw_reset = PROPERTY_ENABLE; - ret = stts22h_write_reg(ctx, STTS22H_SOFTWARE_RESET, - (uint8_t *)&software_reset, 1); - - if (ret == 0) - { - software_reset.sw_reset = PROPERTY_DISABLE; - ret = stts22h_write_reg(ctx, STTS22H_SOFTWARE_RESET, - (uint8_t *)&software_reset, 1); - } - } - - if ((val == STTS22H_1Hz) && (ret == 0)) - { - software_reset.sw_reset = PROPERTY_ENABLE; - software_reset.low_odr_enable = PROPERTY_ENABLE; - ret = stts22h_write_reg(ctx, STTS22H_SOFTWARE_RESET, - (uint8_t *)&software_reset, 1); - - if (ret == 0) - { - software_reset.sw_reset = PROPERTY_DISABLE; - software_reset.low_odr_enable = PROPERTY_ENABLE; - ret = stts22h_write_reg(ctx, STTS22H_SOFTWARE_RESET, - (uint8_t *)&software_reset, 1); - } - } - if (ret == 0) { ctrl.one_shot = (uint8_t)val & 0x01U; @@ -197,7 +148,7 @@ int32_t stts22h_temp_data_rate_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t stts22h_temp_data_rate_get(stmdev_ctx_t *ctx, +int32_t stts22h_temp_data_rate_get(const stmdev_ctx_t *ctx, stts22h_odr_temp_t *val) { stts22h_ctrl_t ctrl; @@ -254,7 +205,7 @@ int32_t stts22h_temp_data_rate_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t stts22h_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t stts22h_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val) { stts22h_ctrl_t ctrl; int32_t ret; @@ -278,7 +229,7 @@ int32_t stts22h_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t stts22h_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t stts22h_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -295,7 +246,7 @@ int32_t stts22h_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t stts22h_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t stts22h_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val) { stts22h_status_t status; @@ -337,7 +288,7 @@ int32_t stts22h_temp_flag_data_ready_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t stts22h_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t stts22h_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -369,7 +320,7 @@ int32_t stts22h_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t stts22h_dev_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +int32_t stts22h_dev_id_get(const stmdev_ctx_t *ctx, uint8_t *buff) { int32_t ret; @@ -386,7 +337,7 @@ int32_t stts22h_dev_id_get(stmdev_ctx_t *ctx, uint8_t *buff) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t stts22h_dev_status_get(stmdev_ctx_t *ctx, +int32_t stts22h_dev_status_get(const stmdev_ctx_t *ctx, stts22h_dev_status_t *val) { stts22h_status_t status; @@ -419,7 +370,7 @@ int32_t stts22h_dev_status_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t stts22h_smbus_interface_set(stmdev_ctx_t *ctx, +int32_t stts22h_smbus_interface_set(const stmdev_ctx_t *ctx, stts22h_smbus_md_t val) { stts22h_ctrl_t ctrl; @@ -444,7 +395,7 @@ int32_t stts22h_smbus_interface_set(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t stts22h_smbus_interface_get(stmdev_ctx_t *ctx, +int32_t stts22h_smbus_interface_get(const stmdev_ctx_t *ctx, stts22h_smbus_md_t *val) { stts22h_ctrl_t ctrl; @@ -480,7 +431,7 @@ int32_t stts22h_smbus_interface_get(stmdev_ctx_t *ctx, * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t stts22h_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t stts22h_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val) { stts22h_ctrl_t ctrl; int32_t ret; @@ -505,7 +456,7 @@ int32_t stts22h_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t stts22h_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t stts22h_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val) { int32_t ret; @@ -535,7 +486,7 @@ int32_t stts22h_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t stts22h_temp_trshld_high_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t stts22h_temp_trshld_high_set(const stmdev_ctx_t *ctx, uint8_t val) { stts22h_temp_h_limit_t temp_h_limit; int32_t ret; @@ -561,7 +512,7 @@ int32_t stts22h_temp_trshld_high_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t stts22h_temp_trshld_high_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t stts22h_temp_trshld_high_get(const stmdev_ctx_t *ctx, uint8_t *val) { stts22h_temp_h_limit_t temp_h_limit; int32_t ret; @@ -581,7 +532,7 @@ int32_t stts22h_temp_trshld_high_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t stts22h_temp_trshld_low_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t stts22h_temp_trshld_low_set(const stmdev_ctx_t *ctx, uint8_t val) { stts22h_temp_l_limit_t temp_l_limit; int32_t ret; @@ -607,7 +558,7 @@ int32_t stts22h_temp_trshld_low_set(stmdev_ctx_t *ctx, uint8_t val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t stts22h_temp_trshld_low_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t stts22h_temp_trshld_low_get(const stmdev_ctx_t *ctx, uint8_t *val) { stts22h_temp_l_limit_t temp_l_limit; int32_t ret; @@ -627,7 +578,7 @@ int32_t stts22h_temp_trshld_low_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval Interface status (MANDATORY: return 0 -> no Error). * */ -int32_t stts22h_temp_trshld_src_get(stmdev_ctx_t *ctx, +int32_t stts22h_temp_trshld_src_get(const stmdev_ctx_t *ctx, stts22h_temp_trlhd_src_t *val) { stts22h_status_t status; diff --git a/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.h b/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.h index 934640dc..ba6a37f2 100644 --- a/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.h +++ b/sensor/stmemsc/stts22h_STdC/driver/stts22h_reg.h @@ -233,24 +233,6 @@ typedef struct #define STTS22H_TEMP_L_OUT 0x06U #define STTS22H_TEMP_H_OUT 0x07U -#define STTS22H_SOFTWARE_RESET 0x0CU -typedef struct -{ -#if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN - uint8_t not_used_01 : 1; - uint8_t sw_reset : 1; - uint8_t not_used_02 : 4; - uint8_t low_odr_enable : 1; - uint8_t not_used_03 : 1; -#elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN - uint8_t not_used_03 : 1; - uint8_t low_odr_enable : 1; - uint8_t not_used_02 : 4; - uint8_t sw_reset : 1; - uint8_t not_used_01 : 1; -#endif /* DRV_BYTE_ORDER */ -} stts22h_software_reset_t; - /** * @defgroup STTS22H_Register_Union @@ -270,7 +252,6 @@ typedef union stts22h_temp_l_limit_t temp_l_limit; stts22h_ctrl_t ctrl; stts22h_status_t status; - stts22h_software_reset_t software_reset; bitwise_t bitwise; uint8_t byte; } stts22h_reg_t; @@ -293,10 +274,10 @@ typedef union * them with a custom implementation. */ -int32_t stts22h_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t stts22h_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t stts22h_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t stts22h_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -312,27 +293,27 @@ typedef enum STTS22H_100Hz = 0x22, STTS22H_200Hz = 0x32, } stts22h_odr_temp_t; -int32_t stts22h_temp_data_rate_set(stmdev_ctx_t *ctx, +int32_t stts22h_temp_data_rate_set(const stmdev_ctx_t *ctx, stts22h_odr_temp_t val); -int32_t stts22h_temp_data_rate_get(stmdev_ctx_t *ctx, +int32_t stts22h_temp_data_rate_get(const stmdev_ctx_t *ctx, stts22h_odr_temp_t *val); -int32_t stts22h_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t stts22h_block_data_update_get(stmdev_ctx_t *ctx, +int32_t stts22h_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t stts22h_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t stts22h_temp_flag_data_ready_get(stmdev_ctx_t *ctx, +int32_t stts22h_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t stts22h_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t stts22h_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t stts22h_dev_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t stts22h_dev_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); typedef struct { uint8_t busy : 1; } stts22h_dev_status_t; -int32_t stts22h_dev_status_get(stmdev_ctx_t *ctx, +int32_t stts22h_dev_status_get(const stmdev_ctx_t *ctx, stts22h_dev_status_t *val); typedef enum @@ -340,26 +321,26 @@ typedef enum STTS22H_SMBUS_TIMEOUT_ENABLE = 0, STTS22H_SMBUS_TIMEOUT_DISABLE = 1, } stts22h_smbus_md_t; -int32_t stts22h_smbus_interface_set(stmdev_ctx_t *ctx, +int32_t stts22h_smbus_interface_set(const stmdev_ctx_t *ctx, stts22h_smbus_md_t val); -int32_t stts22h_smbus_interface_get(stmdev_ctx_t *ctx, +int32_t stts22h_smbus_interface_get(const stmdev_ctx_t *ctx, stts22h_smbus_md_t *val); -int32_t stts22h_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t stts22h_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t stts22h_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t stts22h_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t stts22h_temp_trshld_high_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t stts22h_temp_trshld_high_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t stts22h_temp_trshld_high_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t stts22h_temp_trshld_high_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t stts22h_temp_trshld_low_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t stts22h_temp_trshld_low_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t stts22h_temp_trshld_low_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t stts22h_temp_trshld_low_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { uint8_t under_thl : 1; uint8_t over_thh : 1; } stts22h_temp_trlhd_src_t; -int32_t stts22h_temp_trshld_src_get(stmdev_ctx_t *ctx, +int32_t stts22h_temp_trshld_src_get(const stmdev_ctx_t *ctx, stts22h_temp_trlhd_src_t *val); /** diff --git a/sensor/stmemsc/stts751_STdC/driver/stts751_reg.c b/sensor/stmemsc/stts751_STdC/driver/stts751_reg.c index 552b99bb..e5a1e108 100644 --- a/sensor/stmemsc/stts751_STdC/driver/stts751_reg.c +++ b/sensor/stmemsc/stts751_STdC/driver/stts751_reg.c @@ -46,12 +46,17 @@ * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak stts751_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak stts751_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->read_reg(ctx->handle, reg, data, len); return ret; @@ -67,12 +72,17 @@ int32_t __weak stts751_read_reg(stmdev_ctx_t *ctx, uint8_t reg, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t __weak stts751_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t __weak stts751_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len) { int32_t ret; + if (ctx == NULL) + { + return -1; + } + ret = ctx->write_reg(ctx->handle, reg, data, len); return ret; @@ -139,7 +149,7 @@ int16_t stts751_from_celsius_to_lsb(float_t celsius) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t stts751_temp_data_rate_set(stmdev_ctx_t *ctx, +int32_t stts751_temp_data_rate_set(const stmdev_ctx_t *ctx, stts751_odr_t val) { stts751_configuration_t configuration; @@ -186,7 +196,7 @@ int32_t stts751_temp_data_rate_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t stts751_temp_data_rate_get(stmdev_ctx_t *ctx, +int32_t stts751_temp_data_rate_get(const stmdev_ctx_t *ctx, stts751_odr_t *val) { stts751_conversion_rate_t conversion_rate; @@ -268,7 +278,7 @@ int32_t stts751_temp_data_rate_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t stts751_resolution_set(stmdev_ctx_t *ctx, stts751_tres_t val) +int32_t stts751_resolution_set(const stmdev_ctx_t *ctx, stts751_tres_t val) { stts751_configuration_t reg; int32_t ret; @@ -292,7 +302,7 @@ int32_t stts751_resolution_set(stmdev_ctx_t *ctx, stts751_tres_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t stts751_resolution_get(stmdev_ctx_t *ctx, stts751_tres_t *val) +int32_t stts751_resolution_get(const stmdev_ctx_t *ctx, stts751_tres_t *val) { stts751_configuration_t reg; int32_t ret; @@ -333,7 +343,7 @@ int32_t stts751_resolution_get(stmdev_ctx_t *ctx, stts751_tres_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t stts751_status_reg_get(stmdev_ctx_t *ctx, +int32_t stts751_status_reg_get(const stmdev_ctx_t *ctx, stts751_status_t *val) { int32_t ret; @@ -351,7 +361,7 @@ int32_t stts751_status_reg_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t stts751_flag_busy_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t stts751_flag_busy_get(const stmdev_ctx_t *ctx, uint8_t *val) { stts751_status_t reg; int32_t ret; @@ -383,7 +393,7 @@ int32_t stts751_flag_busy_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t stts751_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) +int32_t stts751_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; int32_t ret; @@ -422,7 +432,7 @@ int32_t stts751_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t stts751_pin_event_route_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t stts751_pin_event_route_set(const stmdev_ctx_t *ctx, uint8_t val) { stts751_configuration_t reg; int32_t ret; @@ -446,7 +456,7 @@ int32_t stts751_pin_event_route_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t stts751_pin_event_route_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t stts751_pin_event_route_get(const stmdev_ctx_t *ctx, uint8_t *val) { stts751_configuration_t reg; int32_t ret; @@ -478,7 +488,7 @@ int32_t stts751_pin_event_route_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t stts751_high_temperature_threshold_set(stmdev_ctx_t *ctx, +int32_t stts751_high_temperature_threshold_set(const stmdev_ctx_t *ctx, int16_t val) { uint8_t buff[2]; @@ -500,7 +510,7 @@ int32_t stts751_high_temperature_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t stts751_high_temperature_threshold_get(stmdev_ctx_t *ctx, +int32_t stts751_high_temperature_threshold_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; @@ -522,7 +532,7 @@ int32_t stts751_high_temperature_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t stts751_low_temperature_threshold_set(stmdev_ctx_t *ctx, +int32_t stts751_low_temperature_threshold_set(const stmdev_ctx_t *ctx, int16_t val) { uint8_t buff[2]; @@ -544,7 +554,7 @@ int32_t stts751_low_temperature_threshold_set(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t stts751_low_temperature_threshold_get(stmdev_ctx_t *ctx, +int32_t stts751_low_temperature_threshold_get(const stmdev_ctx_t *ctx, int16_t *val) { uint8_t buff[2]; @@ -579,7 +589,7 @@ int32_t stts751_low_temperature_threshold_get(stmdev_ctx_t *ctx, * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t stts751_ota_thermal_limit_set(stmdev_ctx_t *ctx, int8_t val) +int32_t stts751_ota_thermal_limit_set(const stmdev_ctx_t *ctx, int8_t val) { int32_t ret; @@ -596,7 +606,7 @@ int32_t stts751_ota_thermal_limit_set(stmdev_ctx_t *ctx, int8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t stts751_ota_thermal_limit_get(stmdev_ctx_t *ctx, int8_t *val) +int32_t stts751_ota_thermal_limit_get(const stmdev_ctx_t *ctx, int8_t *val) { int32_t ret; @@ -614,7 +624,7 @@ int32_t stts751_ota_thermal_limit_get(stmdev_ctx_t *ctx, int8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t stts751_ota_thermal_hyst_set(stmdev_ctx_t *ctx, int8_t val) +int32_t stts751_ota_thermal_hyst_set(const stmdev_ctx_t *ctx, int8_t val) { int32_t ret; @@ -633,7 +643,7 @@ int32_t stts751_ota_thermal_hyst_set(stmdev_ctx_t *ctx, int8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t stts751_ota_thermal_hyst_get(stmdev_ctx_t *ctx, int8_t *val) +int32_t stts751_ota_thermal_hyst_get(const stmdev_ctx_t *ctx, int8_t *val) { int32_t ret; @@ -663,7 +673,7 @@ int32_t stts751_ota_thermal_hyst_get(stmdev_ctx_t *ctx, int8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t stts751_smbus_timeout_set(stmdev_ctx_t *ctx, uint8_t val) +int32_t stts751_smbus_timeout_set(const stmdev_ctx_t *ctx, uint8_t val) { stts751_smbus_timeout_t reg; int32_t ret; @@ -688,7 +698,7 @@ int32_t stts751_smbus_timeout_set(stmdev_ctx_t *ctx, uint8_t val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t stts751_smbus_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) +int32_t stts751_smbus_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val) { stts751_smbus_timeout_t reg; int32_t ret; @@ -707,7 +717,7 @@ int32_t stts751_smbus_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) * @retval interface status (MANDATORY: return 0 -> no Error) * */ -int32_t stts751_device_id_get(stmdev_ctx_t *ctx, stts751_id_t *buff) +int32_t stts751_device_id_get(const stmdev_ctx_t *ctx, stts751_id_t *buff) { int32_t ret; diff --git a/sensor/stmemsc/stts751_STdC/driver/stts751_reg.h b/sensor/stmemsc/stts751_STdC/driver/stts751_reg.h index f5f59c67..58b225b9 100644 --- a/sensor/stmemsc/stts751_STdC/driver/stts751_reg.h +++ b/sensor/stmemsc/stts751_STdC/driver/stts751_reg.h @@ -306,10 +306,10 @@ typedef union * them with a custom implementation. */ -int32_t stts751_read_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t stts751_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); -int32_t stts751_write_reg(stmdev_ctx_t *ctx, uint8_t reg, +int32_t stts751_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, uint16_t len); @@ -331,9 +331,9 @@ typedef enum STTS751_TEMP_ODR_16Hz = 0x08, /* 9, 10, or 11-bit resolutions only */ STTS751_TEMP_ODR_32Hz = 0x09, /* 9 or 10-bit resolutions only */ } stts751_odr_t; -int32_t stts751_temp_data_rate_set(stmdev_ctx_t *ctx, +int32_t stts751_temp_data_rate_set(const stmdev_ctx_t *ctx, stts751_odr_t val); -int32_t stts751_temp_data_rate_get(stmdev_ctx_t *ctx, +int32_t stts751_temp_data_rate_get(const stmdev_ctx_t *ctx, stts751_odr_t *val); typedef enum @@ -343,39 +343,39 @@ typedef enum STTS751_11bit = 1, STTS751_12bit = 3, } stts751_tres_t; -int32_t stts751_resolution_set(stmdev_ctx_t *ctx, stts751_tres_t val); -int32_t stts751_resolution_get(stmdev_ctx_t *ctx, +int32_t stts751_resolution_set(const stmdev_ctx_t *ctx, stts751_tres_t val); +int32_t stts751_resolution_get(const stmdev_ctx_t *ctx, stts751_tres_t *val); -int32_t stts751_status_reg_get(stmdev_ctx_t *ctx, +int32_t stts751_status_reg_get(const stmdev_ctx_t *ctx, stts751_status_t *val); -int32_t stts751_flag_busy_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t stts751_flag_busy_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t stts751_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); +int32_t stts751_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t stts751_pin_event_route_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t stts751_pin_event_route_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t stts751_pin_event_route_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t stts751_pin_event_route_get(const stmdev_ctx_t *ctx, uint8_t *val); -int32_t stts751_high_temperature_threshold_set(stmdev_ctx_t *ctx, +int32_t stts751_high_temperature_threshold_set(const stmdev_ctx_t *ctx, int16_t val); -int32_t stts751_high_temperature_threshold_get(stmdev_ctx_t *ctx, +int32_t stts751_high_temperature_threshold_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t stts751_low_temperature_threshold_set(stmdev_ctx_t *ctx, +int32_t stts751_low_temperature_threshold_set(const stmdev_ctx_t *ctx, int16_t val); -int32_t stts751_low_temperature_threshold_get(stmdev_ctx_t *ctx, +int32_t stts751_low_temperature_threshold_get(const stmdev_ctx_t *ctx, int16_t *val); -int32_t stts751_ota_thermal_limit_set(stmdev_ctx_t *ctx, int8_t val); -int32_t stts751_ota_thermal_limit_get(stmdev_ctx_t *ctx, int8_t *val); +int32_t stts751_ota_thermal_limit_set(const stmdev_ctx_t *ctx, int8_t val); +int32_t stts751_ota_thermal_limit_get(const stmdev_ctx_t *ctx, int8_t *val); -int32_t stts751_ota_thermal_hyst_set(stmdev_ctx_t *ctx, int8_t val); -int32_t stts751_ota_thermal_hyst_get(stmdev_ctx_t *ctx, int8_t *val); +int32_t stts751_ota_thermal_hyst_set(const stmdev_ctx_t *ctx, int8_t val); +int32_t stts751_ota_thermal_hyst_get(const stmdev_ctx_t *ctx, int8_t *val); -int32_t stts751_smbus_timeout_set(stmdev_ctx_t *ctx, uint8_t val); -int32_t stts751_smbus_timeout_get(stmdev_ctx_t *ctx, uint8_t *val); +int32_t stts751_smbus_timeout_set(const stmdev_ctx_t *ctx, uint8_t val); +int32_t stts751_smbus_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val); typedef struct { @@ -383,7 +383,7 @@ typedef struct uint8_t manufacturer_id; uint8_t revision_id; } stts751_id_t; -int32_t stts751_device_id_get(stmdev_ctx_t *ctx, stts751_id_t *buff); +int32_t stts751_device_id_get(const stmdev_ctx_t *ctx, stts751_id_t *buff); /** * @} -- GitLab